1 /* $OpenBSD: piixpm.c,v 1.42 2020/01/21 06:37:24 claudio Exp $ */ 2 3 /* 4 * Copyright (c) 2005, 2006 Alexander Yurchenko <grange@openbsd.org> 5 * 6 * Permission to use, copy, modify, and distribute this software for any 7 * purpose with or without fee is hereby granted, provided that the above 8 * copyright notice and this permission notice appear in all copies. 9 * 10 * THE SOFTWARE IS PROVIDED "AS IS" AND THE AUTHOR DISCLAIMS ALL WARRANTIES 11 * WITH REGARD TO THIS SOFTWARE INCLUDING ALL IMPLIED WARRANTIES OF 12 * MERCHANTABILITY AND FITNESS. IN NO EVENT SHALL THE AUTHOR BE LIABLE FOR 13 * ANY SPECIAL, DIRECT, INDIRECT, OR CONSEQUENTIAL DAMAGES OR ANY DAMAGES 14 * WHATSOEVER RESULTING FROM LOSS OF USE, DATA OR PROFITS, WHETHER IN AN 15 * ACTION OF CONTRACT, NEGLIGENCE OR OTHER TORTIOUS ACTION, ARISING OUT OF 16 * OR IN CONNECTION WITH THE USE OR PERFORMANCE OF THIS SOFTWARE. 17 */ 18 19 /* 20 * Intel PIIX and compatible Power Management controller driver. 21 */ 22 23 #include <sys/param.h> 24 #include <sys/systm.h> 25 #include <sys/device.h> 26 #include <sys/kernel.h> 27 #include <sys/rwlock.h> 28 29 #include <machine/bus.h> 30 31 #include <dev/pci/pcidevs.h> 32 #include <dev/pci/pcireg.h> 33 #include <dev/pci/pcivar.h> 34 35 #include <dev/pci/piixreg.h> 36 37 #include <dev/i2c/i2cvar.h> 38 39 #ifdef PIIXPM_DEBUG 40 #define DPRINTF(x) printf x 41 #else 42 #define DPRINTF(x) 43 #endif 44 45 #define PIIXPM_DELAY 200 46 #define PIIXPM_TIMEOUT 1 47 48 struct piixpm_smbus { 49 int sb_bus; 50 struct piixpm_softc *sb_sc; 51 }; 52 53 struct piixpm_softc { 54 struct device sc_dev; 55 56 bus_space_tag_t sc_iot; 57 bus_space_handle_t sc_ioh; 58 bus_space_handle_t sc_sb800_ioh; 59 void * sc_ih; 60 int sc_poll; 61 int sc_is_sb800; 62 int sc_is_fch; 63 64 struct piixpm_smbus sc_busses[4]; 65 struct i2c_controller sc_i2c_tag[4]; 66 struct rwlock sc_i2c_lock; 67 struct { 68 i2c_op_t op; 69 void * buf; 70 size_t len; 71 int flags; 72 volatile int error; 73 } sc_i2c_xfer; 74 }; 75 76 int piixpm_match(struct device *, void *, void *); 77 void piixpm_attach(struct device *, struct device *, void *); 78 79 int piixpm_i2c_acquire_bus(void *, int); 80 void piixpm_i2c_release_bus(void *, int); 81 int piixpm_i2c_exec(void *, i2c_op_t, i2c_addr_t, const void *, size_t, 82 void *, size_t, int); 83 84 int piixpm_intr(void *); 85 86 struct cfattach piixpm_ca = { 87 sizeof(struct piixpm_softc), 88 piixpm_match, 89 piixpm_attach 90 }; 91 92 struct cfdriver piixpm_cd = { 93 NULL, "piixpm", DV_DULL 94 }; 95 96 const struct pci_matchid piixpm_ids[] = { 97 { PCI_VENDOR_AMD, PCI_PRODUCT_AMD_HUDSON2_SMB }, 98 { PCI_VENDOR_AMD, PCI_PRODUCT_AMD_KERNCZ_SMB }, 99 100 { PCI_VENDOR_ATI, PCI_PRODUCT_ATI_SB200_SMB }, 101 { PCI_VENDOR_ATI, PCI_PRODUCT_ATI_SB300_SMB }, 102 { PCI_VENDOR_ATI, PCI_PRODUCT_ATI_SB400_SMB }, 103 { PCI_VENDOR_ATI, PCI_PRODUCT_ATI_SBX00_SMB }, 104 105 { PCI_VENDOR_INTEL, PCI_PRODUCT_INTEL_82371AB_PM }, 106 { PCI_VENDOR_INTEL, PCI_PRODUCT_INTEL_82440MX_PM }, 107 108 { PCI_VENDOR_RCC, PCI_PRODUCT_RCC_CSB5 }, 109 { PCI_VENDOR_RCC, PCI_PRODUCT_RCC_CSB6 }, 110 { PCI_VENDOR_RCC, PCI_PRODUCT_RCC_HT_1000 }, 111 { PCI_VENDOR_RCC, PCI_PRODUCT_RCC_HT_1100 }, 112 { PCI_VENDOR_RCC, PCI_PRODUCT_RCC_OSB4 }, 113 114 { PCI_VENDOR_SMSC, PCI_PRODUCT_SMSC_VICTORY66_PM } 115 }; 116 117 int 118 piixpm_match(struct device *parent, void *match, void *aux) 119 { 120 return (pci_matchbyid(aux, piixpm_ids, 121 sizeof(piixpm_ids) / sizeof(piixpm_ids[0]))); 122 } 123 124 void 125 piixpm_attach(struct device *parent, struct device *self, void *aux) 126 { 127 struct piixpm_softc *sc = (struct piixpm_softc *)self; 128 struct pci_attach_args *pa = aux; 129 bus_space_handle_t ioh; 130 u_int16_t val, smb0en; 131 bus_addr_t base; 132 pcireg_t conf; 133 pci_intr_handle_t ih; 134 const char *intrstr = NULL; 135 struct i2cbus_attach_args iba; 136 int numbusses, i; 137 138 sc->sc_iot = pa->pa_iot; 139 numbusses = 1; 140 141 if ((PCI_VENDOR(pa->pa_id) == PCI_VENDOR_AMD && 142 PCI_PRODUCT(pa->pa_id) == PCI_PRODUCT_AMD_HUDSON2_SMB) || 143 (PCI_VENDOR(pa->pa_id) == PCI_VENDOR_AMD && 144 PCI_PRODUCT(pa->pa_id) == PCI_PRODUCT_AMD_KERNCZ_SMB) || 145 (PCI_VENDOR(pa->pa_id) == PCI_VENDOR_ATI && 146 PCI_PRODUCT(pa->pa_id) == PCI_PRODUCT_ATI_SBX00_SMB && 147 PCI_REVISION(pa->pa_class) >= 0x40)) { 148 /* 149 * On the AMD SB800+, the SMBus I/O registers are well 150 * hidden. We need to look at the "SMBus0En" Power 151 * Management register to find out where they live. 152 * We use indirect IO access through the index/data 153 * pair at 0xcd6/0xcd7 to access "SMBus0En". 154 */ 155 if (bus_space_map(sc->sc_iot, SB800_PMREG_BASE, 156 SB800_PMREG_SIZE, 0, &ioh) != 0) { 157 printf(": can't map i/o space\n"); 158 return; 159 } 160 161 /* 162 * AMD Bolton matches PCI_PRODUCT_AMD_HUDSON2_SMB but 163 * uses old register layout. Therefor check PCI_REVISION. 164 */ 165 if (PCI_VENDOR(pa->pa_id) == PCI_VENDOR_AMD && 166 ((PCI_PRODUCT(pa->pa_id) == PCI_PRODUCT_AMD_HUDSON2_SMB && 167 PCI_REVISION(pa->pa_class) >= 0x1f) || 168 PCI_PRODUCT(pa->pa_id) == PCI_PRODUCT_AMD_KERNCZ_SMB)) { 169 bus_space_write_1(sc->sc_iot, ioh, 0, 170 AMDFCH41_PM_DECODE_EN); 171 val = bus_space_read_1(sc->sc_iot, ioh, 1); 172 smb0en = val & AMDFCH41_SMBUS_EN; 173 174 bus_space_write_1(sc->sc_iot, ioh, 0, 175 AMDFCH41_PM_DECODE_EN + 1); 176 val = bus_space_read_1(sc->sc_iot, ioh, 1) << 8; 177 base = val; 178 179 sc->sc_is_fch = 1; 180 numbusses = 2; 181 } else { 182 /* Read "SmBus0En" */ 183 bus_space_write_1(sc->sc_iot, ioh, 0, 184 SB800_PMREG_SMB0EN); 185 val = bus_space_read_1(sc->sc_iot, ioh, 1); 186 187 bus_space_write_1(sc->sc_iot, ioh, 0, 188 SB800_PMREG_SMB0EN + 1); 189 val |= (bus_space_read_1(sc->sc_iot, ioh, 1) << 8); 190 smb0en = val & SB800_SMB0EN_EN; 191 base = val & SB800_SMB0EN_BASE_MASK; 192 193 bus_space_write_1(sc->sc_iot, ioh, 0, 194 SB800_PMREG_SMB0SELEN); 195 val = bus_space_read_1(sc->sc_iot, ioh, 1); 196 if (val & SB800_SMB0SELEN_EN) { 197 sc->sc_is_sb800 = 1; 198 numbusses = 4; 199 } 200 } 201 202 if (smb0en == 0) { 203 printf(": SMBus disabled\n"); 204 bus_space_unmap(sc->sc_iot, ioh, SB800_PMREG_SIZE); 205 return; 206 } 207 208 sc->sc_sb800_ioh = ioh; 209 210 /* Map I/O space */ 211 if (base == 0 || bus_space_map(sc->sc_iot, base, 212 SB800_SMB_SIZE, 0, &sc->sc_ioh)) { 213 printf(": can't map i/o space"); 214 bus_space_unmap(sc->sc_iot, ioh, SB800_PMREG_SIZE); 215 return; 216 } 217 218 /* Read configuration */ 219 conf = bus_space_read_1(sc->sc_iot, sc->sc_ioh, 220 SB800_SMB_HOSTC); 221 if (conf & SB800_SMB_HOSTC_INTMASK) 222 conf = PIIX_SMB_HOSTC_IRQ; 223 else 224 conf = PIIX_SMB_HOSTC_SMI; 225 } else { 226 /* Read configuration */ 227 conf = pci_conf_read(pa->pa_pc, pa->pa_tag, PIIX_SMB_HOSTC); 228 DPRINTF((": conf 0x%08x", conf)); 229 230 if ((conf & PIIX_SMB_HOSTC_HSTEN) == 0) { 231 printf(": SMBus disabled\n"); 232 return; 233 } 234 235 /* Map I/O space */ 236 base = pci_conf_read(pa->pa_pc, pa->pa_tag, PIIX_SMB_BASE) & 237 PIIX_SMB_BASE_MASK; 238 if (base == 0 || bus_space_map(sc->sc_iot, base, 239 PIIX_SMB_SIZE, 0, &sc->sc_ioh)) { 240 printf(": can't map i/o space\n"); 241 return; 242 } 243 } 244 245 sc->sc_poll = 1; 246 if ((conf & PIIX_SMB_HOSTC_INTMASK) == PIIX_SMB_HOSTC_SMI) { 247 /* No PCI IRQ */ 248 printf(": SMI"); 249 } else { 250 if ((conf & PIIX_SMB_HOSTC_INTMASK) == PIIX_SMB_HOSTC_IRQ) { 251 /* Install interrupt handler */ 252 if (pci_intr_map(pa, &ih) == 0) { 253 intrstr = pci_intr_string(pa->pa_pc, ih); 254 sc->sc_ih = pci_intr_establish(pa->pa_pc, 255 ih, IPL_BIO, piixpm_intr, sc, 256 sc->sc_dev.dv_xname); 257 if (sc->sc_ih != NULL) { 258 printf(": %s", intrstr); 259 sc->sc_poll = 0; 260 } 261 } 262 } 263 if (sc->sc_poll) 264 printf(": polling"); 265 } 266 267 printf("\n"); 268 269 /* Attach I2C bus */ 270 rw_init(&sc->sc_i2c_lock, "iiclk"); 271 for (i = 0; i < numbusses; i++) { 272 sc->sc_busses[i].sb_bus = i; 273 sc->sc_busses[i].sb_sc = sc; 274 sc->sc_i2c_tag[i].ic_cookie = &sc->sc_busses[i]; 275 sc->sc_i2c_tag[i].ic_acquire_bus = piixpm_i2c_acquire_bus; 276 sc->sc_i2c_tag[i].ic_release_bus = piixpm_i2c_release_bus; 277 sc->sc_i2c_tag[i].ic_exec = piixpm_i2c_exec; 278 279 bzero(&iba, sizeof(iba)); 280 iba.iba_name = "iic"; 281 iba.iba_tag = &sc->sc_i2c_tag[i]; 282 config_found(self, &iba, iicbus_print); 283 } 284 285 return; 286 } 287 288 int 289 piixpm_i2c_acquire_bus(void *cookie, int flags) 290 { 291 struct piixpm_smbus *smbus = cookie; 292 struct piixpm_softc *sc = smbus->sb_sc; 293 int rc; 294 295 if (!cold && !sc->sc_poll && !(flags & I2C_F_POLL)) 296 if ((rc = rw_enter(&sc->sc_i2c_lock, RW_WRITE | RW_INTR)) != 0) 297 return (rc); 298 299 if (sc->sc_is_fch) { 300 bus_space_write_1(sc->sc_iot, sc->sc_sb800_ioh, 0, 301 AMDFCH41_PM_PORT_INDEX); 302 bus_space_write_1(sc->sc_iot, sc->sc_sb800_ioh, 1, 303 smbus->sb_bus << 3); 304 } else if (sc->sc_is_sb800) { 305 bus_space_write_1(sc->sc_iot, sc->sc_sb800_ioh, 0, 306 SB800_PMREG_SMB0SEL); 307 bus_space_write_1(sc->sc_iot, sc->sc_sb800_ioh, 1, 308 smbus->sb_bus << 1); 309 } 310 311 return (0); 312 } 313 314 void 315 piixpm_i2c_release_bus(void *cookie, int flags) 316 { 317 struct piixpm_smbus *smbus = cookie; 318 struct piixpm_softc *sc = smbus->sb_sc; 319 320 if (sc->sc_is_fch) { 321 bus_space_write_1(sc->sc_iot, sc->sc_sb800_ioh, 0, 322 AMDFCH41_PM_PORT_INDEX); 323 bus_space_write_1(sc->sc_iot, sc->sc_sb800_ioh, 1, 324 0); 325 } else if (sc->sc_is_sb800) { 326 bus_space_write_1(sc->sc_iot, sc->sc_sb800_ioh, 0, 327 SB800_PMREG_SMB0SEL); 328 bus_space_write_1(sc->sc_iot, sc->sc_sb800_ioh, 1, 329 0); 330 } 331 332 if (cold || sc->sc_poll || (flags & I2C_F_POLL)) 333 return; 334 rw_exit(&sc->sc_i2c_lock); 335 } 336 337 int 338 piixpm_i2c_exec(void *cookie, i2c_op_t op, i2c_addr_t addr, 339 const void *cmdbuf, size_t cmdlen, void *buf, size_t len, int flags) 340 { 341 struct piixpm_smbus *smbus = cookie; 342 struct piixpm_softc *sc = smbus->sb_sc; 343 u_int8_t *b; 344 u_int8_t ctl, st; 345 int retries; 346 347 DPRINTF(("%s: exec: op %d, addr 0x%02x, cmdlen %zu, len %zu, " 348 "flags 0x%02x\n", sc->sc_dev.dv_xname, op, addr, cmdlen, 349 len, flags)); 350 351 /* Wait for bus to be idle */ 352 for (retries = 100; retries > 0; retries--) { 353 st = bus_space_read_1(sc->sc_iot, sc->sc_ioh, PIIX_SMB_HS); 354 if (!(st & PIIX_SMB_HS_BUSY)) 355 break; 356 DELAY(PIIXPM_DELAY); 357 } 358 DPRINTF(("%s: exec: st 0x%b\n", sc->sc_dev.dv_xname, st, 359 PIIX_SMB_HS_BITS)); 360 if (st & PIIX_SMB_HS_BUSY) 361 return (1); 362 363 if (cold || sc->sc_poll) 364 flags |= I2C_F_POLL; 365 366 if (!I2C_OP_STOP_P(op) || cmdlen > 1 || len > 2) 367 return (1); 368 369 /* Setup transfer */ 370 sc->sc_i2c_xfer.op = op; 371 sc->sc_i2c_xfer.buf = buf; 372 sc->sc_i2c_xfer.len = len; 373 sc->sc_i2c_xfer.flags = flags; 374 sc->sc_i2c_xfer.error = 0; 375 376 /* Set slave address and transfer direction */ 377 bus_space_write_1(sc->sc_iot, sc->sc_ioh, PIIX_SMB_TXSLVA, 378 PIIX_SMB_TXSLVA_ADDR(addr) | 379 (I2C_OP_READ_P(op) ? PIIX_SMB_TXSLVA_READ : 0)); 380 381 b = (void *)cmdbuf; 382 if (cmdlen > 0) 383 /* Set command byte */ 384 bus_space_write_1(sc->sc_iot, sc->sc_ioh, PIIX_SMB_HCMD, b[0]); 385 386 if (I2C_OP_WRITE_P(op)) { 387 /* Write data */ 388 b = buf; 389 if (len > 0) 390 bus_space_write_1(sc->sc_iot, sc->sc_ioh, 391 PIIX_SMB_HD0, b[0]); 392 if (len > 1) 393 bus_space_write_1(sc->sc_iot, sc->sc_ioh, 394 PIIX_SMB_HD1, b[1]); 395 } 396 397 /* Set SMBus command */ 398 if (len == 0) 399 ctl = PIIX_SMB_HC_CMD_BYTE; 400 else if (len == 1) 401 ctl = PIIX_SMB_HC_CMD_BDATA; 402 else if (len == 2) 403 ctl = PIIX_SMB_HC_CMD_WDATA; 404 else 405 panic("%s: unexpected len %zd", __func__, len); 406 407 if ((flags & I2C_F_POLL) == 0) 408 ctl |= PIIX_SMB_HC_INTREN; 409 410 /* Start transaction */ 411 ctl |= PIIX_SMB_HC_START; 412 bus_space_write_1(sc->sc_iot, sc->sc_ioh, PIIX_SMB_HC, ctl); 413 414 if (flags & I2C_F_POLL) { 415 /* Poll for completion */ 416 DELAY(PIIXPM_DELAY); 417 for (retries = 1000; retries > 0; retries--) { 418 st = bus_space_read_1(sc->sc_iot, sc->sc_ioh, 419 PIIX_SMB_HS); 420 if ((st & PIIX_SMB_HS_BUSY) == 0) 421 break; 422 DELAY(PIIXPM_DELAY); 423 } 424 if (st & PIIX_SMB_HS_BUSY) 425 goto timeout; 426 piixpm_intr(sc); 427 } else { 428 /* Wait for interrupt */ 429 if (tsleep_nsec(sc, PRIBIO, "piixpm", 430 SEC_TO_NSEC(PIIXPM_TIMEOUT))) 431 goto timeout; 432 } 433 434 if (sc->sc_i2c_xfer.error) 435 return (1); 436 437 return (0); 438 439 timeout: 440 /* 441 * Transfer timeout. Kill the transaction and clear status bits. 442 */ 443 printf("%s: exec: op %d, addr 0x%02x, cmdlen %zu, len %zu, " 444 "flags 0x%02x: timeout, status 0x%b\n", 445 sc->sc_dev.dv_xname, op, addr, cmdlen, len, flags, 446 st, PIIX_SMB_HS_BITS); 447 bus_space_write_1(sc->sc_iot, sc->sc_ioh, PIIX_SMB_HC, 448 PIIX_SMB_HC_KILL); 449 DELAY(PIIXPM_DELAY); 450 st = bus_space_read_1(sc->sc_iot, sc->sc_ioh, PIIX_SMB_HS); 451 if ((st & PIIX_SMB_HS_FAILED) == 0) 452 printf("%s: abort failed, status 0x%b\n", 453 sc->sc_dev.dv_xname, st, PIIX_SMB_HS_BITS); 454 bus_space_write_1(sc->sc_iot, sc->sc_ioh, PIIX_SMB_HS, st); 455 return (1); 456 } 457 458 int 459 piixpm_intr(void *arg) 460 { 461 struct piixpm_softc *sc = arg; 462 u_int8_t st; 463 u_int8_t *b; 464 size_t len; 465 466 /* Read status */ 467 st = bus_space_read_1(sc->sc_iot, sc->sc_ioh, PIIX_SMB_HS); 468 if ((st & PIIX_SMB_HS_BUSY) != 0 || (st & (PIIX_SMB_HS_INTR | 469 PIIX_SMB_HS_DEVERR | PIIX_SMB_HS_BUSERR | 470 PIIX_SMB_HS_FAILED)) == 0) 471 /* Interrupt was not for us */ 472 return (0); 473 474 DPRINTF(("%s: intr st 0x%b\n", sc->sc_dev.dv_xname, st, 475 PIIX_SMB_HS_BITS)); 476 477 /* Clear status bits */ 478 bus_space_write_1(sc->sc_iot, sc->sc_ioh, PIIX_SMB_HS, st); 479 480 /* Check for errors */ 481 if (st & (PIIX_SMB_HS_DEVERR | PIIX_SMB_HS_BUSERR | 482 PIIX_SMB_HS_FAILED)) { 483 sc->sc_i2c_xfer.error = 1; 484 goto done; 485 } 486 487 if (st & PIIX_SMB_HS_INTR) { 488 if (I2C_OP_WRITE_P(sc->sc_i2c_xfer.op)) 489 goto done; 490 491 /* Read data */ 492 b = sc->sc_i2c_xfer.buf; 493 len = sc->sc_i2c_xfer.len; 494 if (len > 0) 495 b[0] = bus_space_read_1(sc->sc_iot, sc->sc_ioh, 496 PIIX_SMB_HD0); 497 if (len > 1) 498 b[1] = bus_space_read_1(sc->sc_iot, sc->sc_ioh, 499 PIIX_SMB_HD1); 500 } 501 502 done: 503 if ((sc->sc_i2c_xfer.flags & I2C_F_POLL) == 0) 504 wakeup(sc); 505 return (1); 506 } 507