1 /* $OpenBSD: piixpm.c,v 1.32 2009/06/24 13:49:48 deraadt Exp $ */ 2 3 /* 4 * Copyright (c) 2005, 2006 Alexander Yurchenko <grange@openbsd.org> 5 * 6 * Permission to use, copy, modify, and distribute this software for any 7 * purpose with or without fee is hereby granted, provided that the above 8 * copyright notice and this permission notice appear in all copies. 9 * 10 * THE SOFTWARE IS PROVIDED "AS IS" AND THE AUTHOR DISCLAIMS ALL WARRANTIES 11 * WITH REGARD TO THIS SOFTWARE INCLUDING ALL IMPLIED WARRANTIES OF 12 * MERCHANTABILITY AND FITNESS. IN NO EVENT SHALL THE AUTHOR BE LIABLE FOR 13 * ANY SPECIAL, DIRECT, INDIRECT, OR CONSEQUENTIAL DAMAGES OR ANY DAMAGES 14 * WHATSOEVER RESULTING FROM LOSS OF USE, DATA OR PROFITS, WHETHER IN AN 15 * ACTION OF CONTRACT, NEGLIGENCE OR OTHER TORTIOUS ACTION, ARISING OUT OF 16 * OR IN CONNECTION WITH THE USE OR PERFORMANCE OF THIS SOFTWARE. 17 */ 18 19 /* 20 * Intel PIIX and compatible Power Management controller driver. 21 */ 22 23 #include <sys/param.h> 24 #include <sys/systm.h> 25 #include <sys/device.h> 26 #include <sys/kernel.h> 27 #include <sys/rwlock.h> 28 #include <sys/proc.h> 29 30 #include <machine/bus.h> 31 32 #include <dev/pci/pcidevs.h> 33 #include <dev/pci/pcireg.h> 34 #include <dev/pci/pcivar.h> 35 36 #include <dev/pci/piixreg.h> 37 38 #include <dev/i2c/i2cvar.h> 39 40 #ifdef PIIXPM_DEBUG 41 #define DPRINTF(x) printf x 42 #else 43 #define DPRINTF(x) 44 #endif 45 46 #define PIIXPM_DELAY 200 47 #define PIIXPM_TIMEOUT 1 48 49 struct piixpm_softc { 50 struct device sc_dev; 51 52 bus_space_tag_t sc_iot; 53 bus_space_handle_t sc_ioh; 54 void * sc_ih; 55 int sc_poll; 56 57 struct i2c_controller sc_i2c_tag; 58 struct rwlock sc_i2c_lock; 59 struct { 60 i2c_op_t op; 61 void * buf; 62 size_t len; 63 int flags; 64 volatile int error; 65 } sc_i2c_xfer; 66 }; 67 68 int piixpm_match(struct device *, void *, void *); 69 void piixpm_attach(struct device *, struct device *, void *); 70 71 int piixpm_i2c_acquire_bus(void *, int); 72 void piixpm_i2c_release_bus(void *, int); 73 int piixpm_i2c_exec(void *, i2c_op_t, i2c_addr_t, const void *, size_t, 74 void *, size_t, int); 75 76 int piixpm_intr(void *); 77 78 struct cfattach piixpm_ca = { 79 sizeof(struct piixpm_softc), 80 piixpm_match, 81 piixpm_attach 82 }; 83 84 struct cfdriver piixpm_cd = { 85 NULL, "piixpm", DV_DULL 86 }; 87 88 const struct pci_matchid piixpm_ids[] = { 89 { PCI_VENDOR_INTEL, PCI_PRODUCT_INTEL_82371AB_PM }, 90 { PCI_VENDOR_INTEL, PCI_PRODUCT_INTEL_82440MX_PM }, 91 { PCI_VENDOR_RCC, PCI_PRODUCT_RCC_OSB4 }, 92 { PCI_VENDOR_RCC, PCI_PRODUCT_RCC_CSB5 }, 93 { PCI_VENDOR_RCC, PCI_PRODUCT_RCC_CSB6 }, 94 { PCI_VENDOR_RCC, PCI_PRODUCT_RCC_HT_1000 }, 95 { PCI_VENDOR_RCC, PCI_PRODUCT_RCC_HT_1100 }, 96 { PCI_VENDOR_SMSC, PCI_PRODUCT_SMSC_VICTORY66_PM }, 97 { PCI_VENDOR_ATI, PCI_PRODUCT_ATI_SB200_SMB }, 98 { PCI_VENDOR_ATI, PCI_PRODUCT_ATI_SB300_SMB }, 99 { PCI_VENDOR_ATI, PCI_PRODUCT_ATI_SB400_SMB }, 100 { PCI_VENDOR_ATI, PCI_PRODUCT_ATI_SBX00_SMB } 101 }; 102 103 int 104 piixpm_match(struct device *parent, void *match, void *aux) 105 { 106 return (pci_matchbyid(aux, piixpm_ids, 107 sizeof(piixpm_ids) / sizeof(piixpm_ids[0]))); 108 } 109 110 void 111 piixpm_attach(struct device *parent, struct device *self, void *aux) 112 { 113 struct piixpm_softc *sc = (struct piixpm_softc *)self; 114 struct pci_attach_args *pa = aux; 115 struct i2cbus_attach_args iba; 116 pcireg_t base, conf; 117 pci_intr_handle_t ih; 118 const char *intrstr = NULL; 119 120 /* Read configuration */ 121 conf = pci_conf_read(pa->pa_pc, pa->pa_tag, PIIX_SMB_HOSTC); 122 DPRINTF((": conf 0x%08x", conf)); 123 124 if ((conf & PIIX_SMB_HOSTC_HSTEN) == 0) { 125 printf(": SMBus disabled\n"); 126 return; 127 } 128 129 /* Map I/O space */ 130 sc->sc_iot = pa->pa_iot; 131 base = pci_conf_read(pa->pa_pc, pa->pa_tag, PIIX_SMB_BASE) & 0xffff; 132 if (PCI_MAPREG_IO_ADDR(base) == 0 || 133 bus_space_map(sc->sc_iot, PCI_MAPREG_IO_ADDR(base), 134 PIIX_SMB_SIZE, 0, &sc->sc_ioh)) { 135 printf(": can't map i/o space\n"); 136 return; 137 } 138 139 sc->sc_poll = 1; 140 if ((conf & PIIX_SMB_HOSTC_INTMASK) == PIIX_SMB_HOSTC_SMI) { 141 /* No PCI IRQ */ 142 printf(": SMI"); 143 } else { 144 if ((conf & PIIX_SMB_HOSTC_INTMASK) == PIIX_SMB_HOSTC_IRQ) { 145 /* Install interrupt handler */ 146 if (pci_intr_map(pa, &ih) == 0) { 147 intrstr = pci_intr_string(pa->pa_pc, ih); 148 sc->sc_ih = pci_intr_establish(pa->pa_pc, 149 ih, IPL_BIO, piixpm_intr, sc, 150 sc->sc_dev.dv_xname); 151 if (sc->sc_ih != NULL) { 152 printf(": %s", intrstr); 153 sc->sc_poll = 0; 154 } 155 } 156 } 157 if (sc->sc_poll) 158 printf(": polling"); 159 } 160 161 printf("\n"); 162 163 /* Attach I2C bus */ 164 rw_init(&sc->sc_i2c_lock, "iiclk"); 165 sc->sc_i2c_tag.ic_cookie = sc; 166 sc->sc_i2c_tag.ic_acquire_bus = piixpm_i2c_acquire_bus; 167 sc->sc_i2c_tag.ic_release_bus = piixpm_i2c_release_bus; 168 sc->sc_i2c_tag.ic_exec = piixpm_i2c_exec; 169 170 bzero(&iba, sizeof(iba)); 171 iba.iba_name = "iic"; 172 iba.iba_tag = &sc->sc_i2c_tag; 173 config_found(self, &iba, iicbus_print); 174 175 return; 176 } 177 178 int 179 piixpm_i2c_acquire_bus(void *cookie, int flags) 180 { 181 struct piixpm_softc *sc = cookie; 182 183 if (cold || sc->sc_poll || (flags & I2C_F_POLL)) 184 return (0); 185 186 return (rw_enter(&sc->sc_i2c_lock, RW_WRITE | RW_INTR)); 187 } 188 189 void 190 piixpm_i2c_release_bus(void *cookie, int flags) 191 { 192 struct piixpm_softc *sc = cookie; 193 194 if (cold || sc->sc_poll || (flags & I2C_F_POLL)) 195 return; 196 197 rw_exit(&sc->sc_i2c_lock); 198 } 199 200 int 201 piixpm_i2c_exec(void *cookie, i2c_op_t op, i2c_addr_t addr, 202 const void *cmdbuf, size_t cmdlen, void *buf, size_t len, int flags) 203 { 204 struct piixpm_softc *sc = cookie; 205 u_int8_t *b; 206 u_int8_t ctl, st; 207 int retries; 208 209 DPRINTF(("%s: exec: op %d, addr 0x%02x, cmdlen %d, len %d, " 210 "flags 0x%02x\n", sc->sc_dev.dv_xname, op, addr, cmdlen, 211 len, flags)); 212 213 /* Wait for bus to be idle */ 214 for (retries = 100; retries > 0; retries--) { 215 st = bus_space_read_1(sc->sc_iot, sc->sc_ioh, PIIX_SMB_HS); 216 if (!(st & PIIX_SMB_HS_BUSY)) 217 break; 218 DELAY(PIIXPM_DELAY); 219 } 220 DPRINTF(("%s: exec: st 0x%b\n", sc->sc_dev.dv_xname, st, 221 PIIX_SMB_HS_BITS)); 222 if (st & PIIX_SMB_HS_BUSY) 223 return (1); 224 225 if (cold || sc->sc_poll) 226 flags |= I2C_F_POLL; 227 228 if (!I2C_OP_STOP_P(op) || cmdlen > 1 || len > 2) 229 return (1); 230 231 /* Setup transfer */ 232 sc->sc_i2c_xfer.op = op; 233 sc->sc_i2c_xfer.buf = buf; 234 sc->sc_i2c_xfer.len = len; 235 sc->sc_i2c_xfer.flags = flags; 236 sc->sc_i2c_xfer.error = 0; 237 238 /* Set slave address and transfer direction */ 239 bus_space_write_1(sc->sc_iot, sc->sc_ioh, PIIX_SMB_TXSLVA, 240 PIIX_SMB_TXSLVA_ADDR(addr) | 241 (I2C_OP_READ_P(op) ? PIIX_SMB_TXSLVA_READ : 0)); 242 243 b = (void *)cmdbuf; 244 if (cmdlen > 0) 245 /* Set command byte */ 246 bus_space_write_1(sc->sc_iot, sc->sc_ioh, PIIX_SMB_HCMD, b[0]); 247 248 if (I2C_OP_WRITE_P(op)) { 249 /* Write data */ 250 b = buf; 251 if (len > 0) 252 bus_space_write_1(sc->sc_iot, sc->sc_ioh, 253 PIIX_SMB_HD0, b[0]); 254 if (len > 1) 255 bus_space_write_1(sc->sc_iot, sc->sc_ioh, 256 PIIX_SMB_HD1, b[1]); 257 } 258 259 /* Set SMBus command */ 260 if (len == 0) 261 ctl = PIIX_SMB_HC_CMD_BYTE; 262 else if (len == 1) 263 ctl = PIIX_SMB_HC_CMD_BDATA; 264 else if (len == 2) 265 ctl = PIIX_SMB_HC_CMD_WDATA; 266 267 if ((flags & I2C_F_POLL) == 0) 268 ctl |= PIIX_SMB_HC_INTREN; 269 270 /* Start transaction */ 271 ctl |= PIIX_SMB_HC_START; 272 bus_space_write_1(sc->sc_iot, sc->sc_ioh, PIIX_SMB_HC, ctl); 273 274 if (flags & I2C_F_POLL) { 275 /* Poll for completion */ 276 DELAY(PIIXPM_DELAY); 277 for (retries = 1000; retries > 0; retries--) { 278 st = bus_space_read_1(sc->sc_iot, sc->sc_ioh, 279 PIIX_SMB_HS); 280 if ((st & PIIX_SMB_HS_BUSY) == 0) 281 break; 282 DELAY(PIIXPM_DELAY); 283 } 284 if (st & PIIX_SMB_HS_BUSY) 285 goto timeout; 286 piixpm_intr(sc); 287 } else { 288 /* Wait for interrupt */ 289 if (tsleep(sc, PRIBIO, "iicexec", PIIXPM_TIMEOUT * hz)) 290 goto timeout; 291 } 292 293 if (sc->sc_i2c_xfer.error) 294 return (1); 295 296 return (0); 297 298 timeout: 299 /* 300 * Transfer timeout. Kill the transaction and clear status bits. 301 */ 302 printf("%s: exec: op %d, addr 0x%02x, cmdlen %d, len %d, " 303 "flags 0x%02x: timeout, status 0x%b\n", 304 sc->sc_dev.dv_xname, op, addr, cmdlen, len, flags, 305 st, PIIX_SMB_HS_BITS); 306 bus_space_write_1(sc->sc_iot, sc->sc_ioh, PIIX_SMB_HC, 307 PIIX_SMB_HC_KILL); 308 DELAY(PIIXPM_DELAY); 309 st = bus_space_read_1(sc->sc_iot, sc->sc_ioh, PIIX_SMB_HS); 310 if ((st & PIIX_SMB_HS_FAILED) == 0) 311 printf("%s: abort failed, status 0x%b\n", 312 sc->sc_dev.dv_xname, st, PIIX_SMB_HS_BITS); 313 bus_space_write_1(sc->sc_iot, sc->sc_ioh, PIIX_SMB_HS, st); 314 return (1); 315 } 316 317 int 318 piixpm_intr(void *arg) 319 { 320 struct piixpm_softc *sc = arg; 321 u_int8_t st; 322 u_int8_t *b; 323 size_t len; 324 325 /* Read status */ 326 st = bus_space_read_1(sc->sc_iot, sc->sc_ioh, PIIX_SMB_HS); 327 if ((st & PIIX_SMB_HS_BUSY) != 0 || (st & (PIIX_SMB_HS_INTR | 328 PIIX_SMB_HS_DEVERR | PIIX_SMB_HS_BUSERR | 329 PIIX_SMB_HS_FAILED)) == 0) 330 /* Interrupt was not for us */ 331 return (0); 332 333 DPRINTF(("%s: intr st 0x%b\n", sc->sc_dev.dv_xname, st, 334 PIIX_SMB_HS_BITS)); 335 336 /* Clear status bits */ 337 bus_space_write_1(sc->sc_iot, sc->sc_ioh, PIIX_SMB_HS, st); 338 339 /* Check for errors */ 340 if (st & (PIIX_SMB_HS_DEVERR | PIIX_SMB_HS_BUSERR | 341 PIIX_SMB_HS_FAILED)) { 342 sc->sc_i2c_xfer.error = 1; 343 goto done; 344 } 345 346 if (st & PIIX_SMB_HS_INTR) { 347 if (I2C_OP_WRITE_P(sc->sc_i2c_xfer.op)) 348 goto done; 349 350 /* Read data */ 351 b = sc->sc_i2c_xfer.buf; 352 len = sc->sc_i2c_xfer.len; 353 if (len > 0) 354 b[0] = bus_space_read_1(sc->sc_iot, sc->sc_ioh, 355 PIIX_SMB_HD0); 356 if (len > 1) 357 b[1] = bus_space_read_1(sc->sc_iot, sc->sc_ioh, 358 PIIX_SMB_HD1); 359 } 360 361 done: 362 if ((sc->sc_i2c_xfer.flags & I2C_F_POLL) == 0) 363 wakeup(sc); 364 return (1); 365 } 366