1 /* $OpenBSD: pcscp.c,v 1.9 2002/03/14 01:26:59 millert Exp $ */ 2 /* $NetBSD: pcscp.c,v 1.11 2000/11/14 18:42:58 thorpej Exp $ */ 3 4 /*- 5 * Copyright (c) 1997, 1998, 1999 The NetBSD Foundation, Inc. 6 * All rights reserved. 7 * 8 * This code is derived from software contributed to The NetBSD Foundation 9 * by Jason R. Thorpe of the Numerical Aerospace Simulation Facility, 10 * NASA Ames Research Center; Izumi Tsutsui. 11 * 12 * Redistribution and use in source and binary forms, with or without 13 * modification, are permitted provided that the following conditions 14 * are met: 15 * 1. Redistributions of source code must retain the above copyright 16 * notice, this list of conditions and the following disclaimer. 17 * 2. Redistributions in binary form must reproduce the above copyright 18 * notice, this list of conditions and the following disclaimer in the 19 * documentation and/or other materials provided with the distribution. 20 * 3. All advertising materials mentioning features or use of this software 21 * must display the following acknowledgement: 22 * This product includes software developed by the NetBSD 23 * Foundation, Inc. and its contributors. 24 * 4. Neither the name of The NetBSD Foundation nor the names of its 25 * contributors may be used to endorse or promote products derived 26 * from this software without specific prior written permission. 27 * 28 * THIS SOFTWARE IS PROVIDED BY THE NETBSD FOUNDATION, INC. AND CONTRIBUTORS 29 * ``AS IS'' AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED 30 * TO, THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR 31 * PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL THE FOUNDATION OR CONTRIBUTORS 32 * BE LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR 33 * CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF 34 * SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS 35 * INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN 36 * CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) 37 * ARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE 38 * POSSIBILITY OF SUCH DAMAGE. 39 */ 40 41 /* 42 * pcscp.c: device dependent code for AMD Am53c974 (PCscsi-PCI) 43 * written by Izumi Tsutsui <tsutsui@ceres.dti.ne.jp> 44 * 45 * Technical manual available at 46 * http://www.amd.com/products/npd/techdocs/techdocs.html 47 */ 48 49 #include <sys/param.h> 50 #include <sys/systm.h> 51 #include <sys/device.h> 52 #include <sys/buf.h> 53 54 #include <machine/bus.h> 55 #include <machine/intr.h> 56 #include <machine/endian.h> 57 58 #include <scsi/scsi_all.h> 59 #include <scsi/scsiconf.h> 60 #include <scsi/scsi_message.h> 61 62 #include <dev/pci/pcireg.h> 63 #include <dev/pci/pcivar.h> 64 #include <dev/pci/pcidevs.h> 65 66 #include <dev/ic/ncr53c9xreg.h> 67 #include <dev/ic/ncr53c9xvar.h> 68 69 #include <dev/pci/pcscpreg.h> 70 71 #define IO_MAP_REG 0x10 72 #define MEM_MAP_REG 0x14 73 74 struct pcscp_softc { 75 struct ncr53c9x_softc sc_ncr53c9x; /* glue to MI code */ 76 77 bus_space_tag_t sc_st; /* bus space tag */ 78 bus_space_handle_t sc_sh; /* bus space handle */ 79 void *sc_ih; /* interrupt cookie */ 80 81 bus_dma_tag_t sc_dmat; /* DMA tag */ 82 83 bus_dmamap_t sc_xfermap; /* DMA map for transfers */ 84 85 u_int32_t *sc_mdladdr; /* MDL array */ 86 bus_dmamap_t sc_mdldmap; /* MDL DMA map */ 87 88 int sc_active; /* DMA state */ 89 int sc_datain; /* DMA Data Direction */ 90 size_t sc_dmasize; /* DMA size */ 91 char **sc_dmaaddr; /* DMA address */ 92 size_t *sc_dmalen; /* DMA length */ 93 }; 94 95 #define READ_DMAREG(sc, reg) \ 96 bus_space_read_4((sc)->sc_st, (sc)->sc_sh, (reg)) 97 #define WRITE_DMAREG(sc, reg, var) \ 98 bus_space_write_4((sc)->sc_st, (sc)->sc_sh, (reg), (var)) 99 100 /* don't have to use MI defines in MD code... */ 101 #undef NCR_READ_REG 102 #define NCR_READ_REG(sc, reg) pcscp_read_reg((sc), (reg)) 103 #undef NCR_WRITE_REG 104 #define NCR_WRITE_REG(sc, reg, val) pcscp_write_reg((sc), (reg), (val)) 105 106 int pcscp_match(struct device *, void *, void *); 107 void pcscp_attach(struct device *, struct device *, void *); 108 109 struct cfattach pcscp_ca = { 110 sizeof(struct pcscp_softc), pcscp_match, pcscp_attach 111 }; 112 113 struct cfdriver pcscp_cd = { 114 NULL, "pcscp", DV_DULL 115 }; 116 117 /* 118 * Functions and the switch for the MI code. 119 */ 120 121 u_char pcscp_read_reg(struct ncr53c9x_softc *, int); 122 void pcscp_write_reg(struct ncr53c9x_softc *, int, u_char); 123 int pcscp_dma_isintr(struct ncr53c9x_softc *); 124 void pcscp_dma_reset(struct ncr53c9x_softc *); 125 int pcscp_dma_intr(struct ncr53c9x_softc *); 126 int pcscp_dma_setup(struct ncr53c9x_softc *, caddr_t *, 127 size_t *, int, size_t *); 128 void pcscp_dma_go(struct ncr53c9x_softc *); 129 void pcscp_dma_stop(struct ncr53c9x_softc *); 130 int pcscp_dma_isactive(struct ncr53c9x_softc *); 131 132 struct scsi_adapter pcscp_adapter = { 133 ncr53c9x_scsi_cmd, /* cmd */ 134 minphys, /* minphys */ 135 0, /* open */ 136 0, /* close */ 137 }; 138 139 struct ncr53c9x_glue pcscp_glue = { 140 pcscp_read_reg, 141 pcscp_write_reg, 142 pcscp_dma_isintr, 143 pcscp_dma_reset, 144 pcscp_dma_intr, 145 pcscp_dma_setup, 146 pcscp_dma_go, 147 pcscp_dma_stop, 148 pcscp_dma_isactive, 149 NULL, /* gl_clear_latched_intr */ 150 }; 151 152 int 153 pcscp_match(parent, match, aux) 154 struct device *parent; 155 void *match, *aux; 156 { 157 struct pci_attach_args *pa = aux; 158 if (PCI_VENDOR(pa->pa_id) != PCI_VENDOR_AMD) 159 return 0; 160 161 switch (PCI_PRODUCT(pa->pa_id)) { 162 case PCI_PRODUCT_AMD_PCSCSI_PCI: 163 #if 0 164 case PCI_PRODUCT_AMD_PCNETS_PCI: 165 #endif 166 return 1; 167 } 168 return 0; 169 } 170 171 /* 172 * Attach this instance, and then all the sub-devices 173 */ 174 void 175 pcscp_attach(parent, self, aux) 176 struct device *parent, *self; 177 void *aux; 178 { 179 struct pci_attach_args *pa = aux; 180 struct pcscp_softc *esc = (void *)self; 181 struct ncr53c9x_softc *sc = &esc->sc_ncr53c9x; 182 bus_space_tag_t st, iot, memt; 183 bus_space_handle_t sh, ioh, memh; 184 int ioh_valid, memh_valid; 185 pci_intr_handle_t ih; 186 const char *intrstr; 187 pcireg_t csr; 188 bus_dma_segment_t seg; 189 int error, rseg; 190 191 ioh_valid = (pci_mapreg_map(pa, IO_MAP_REG, PCI_MAPREG_TYPE_IO, 0, 192 &iot, &ioh, NULL, NULL, 0) == 0); 193 #if 0 /* XXX cannot use memory map? */ 194 memh_valid = (pci_mapreg_map(pa, MEM_MAP_REG, 195 PCI_MAPREG_TYPE_MEM | PCI_MAPREG_MEM_TYPE_32BIT, 0, 196 &memt, &memh, NULL, NULL, 0) == 0); 197 #else 198 memh_valid = 0; 199 #endif 200 201 if (memh_valid) { 202 st = memt; 203 sh = memh; 204 } else if (ioh_valid) { 205 st = iot; 206 sh = ioh; 207 } else { 208 printf(": unable to map registers\n"); 209 return; 210 } 211 212 sc->sc_glue = &pcscp_glue; 213 214 esc->sc_st = st; 215 esc->sc_sh = sh; 216 esc->sc_dmat = pa->pa_dmat; 217 218 csr = pci_conf_read(pa->pa_pc, pa->pa_tag, PCI_COMMAND_STATUS_REG); 219 pci_conf_write(pa->pa_pc, pa->pa_tag, PCI_COMMAND_STATUS_REG, 220 csr | PCI_COMMAND_MASTER_ENABLE | PCI_COMMAND_IO_ENABLE); 221 222 /* 223 * XXX More of this should be in ncr53c9x_attach(), but 224 * XXX should we really poke around the chip that much in 225 * XXX the MI code? Think about this more... 226 */ 227 228 /* 229 * Set up static configuration info. 230 */ 231 232 /* 233 * XXX should read configuration from EEPROM? 234 * 235 * MI ncr53c9x driver does not support configuration 236 * per each target device, though... 237 */ 238 sc->sc_id = 7; 239 sc->sc_cfg1 = sc->sc_id | NCRCFG1_PARENB; 240 sc->sc_cfg2 = NCRCFG2_SCSI2 | NCRCFG2_FE; 241 sc->sc_cfg3 = NCRAMDCFG3_IDM | NCRAMDCFG3_FCLK; 242 sc->sc_cfg4 = NCRAMDCFG4_GE12NS | NCRAMDCFG4_RADE; 243 sc->sc_rev = NCR_VARIANT_AM53C974; 244 sc->sc_features = NCR_F_FASTSCSI; 245 sc->sc_cfg3_fscsi = NCRAMDCFG3_FSCSI; 246 sc->sc_freq = 40; /* MHz */ 247 248 /* 249 * XXX minsync and maxxfer _should_ be set up in MI code, 250 * XXX but it appears to have some dependency on what sort 251 * XXX of DMA we're hooked up to, etc. 252 */ 253 254 /* 255 * This is the value used to start sync negotiations 256 * Note that the NCR register "SYNCTP" is programmed 257 * in "clocks per byte", and has a minimum value of 4. 258 * The SCSI period used in negotiation is one-fourth 259 * of the time (in nanoseconds) needed to transfer one byte. 260 * Since the chip's clock is given in MHz, we have the following 261 * formula: 4 * period = (1000 / freq) * 4 262 */ 263 264 sc->sc_minsync = 1000 / sc->sc_freq; 265 266 /* Really no limit, but since we want to fit into the TCR... */ 267 sc->sc_maxxfer = 16 * 1024 * 1024; 268 269 /* map and establish interrupt */ 270 if (pci_intr_map(pa, &ih)) { 271 printf(": couldn't map interrupt\n"); 272 return; 273 } 274 275 intrstr = pci_intr_string(pa->pa_pc, ih); 276 esc->sc_ih = pci_intr_establish(pa->pa_pc, ih, IPL_BIO, 277 ncr53c9x_intr, esc, sc->sc_dev.dv_xname); 278 if (esc->sc_ih == NULL) { 279 printf(": couldn't establish interrupt"); 280 if (intrstr != NULL) 281 printf(" at %s", intrstr); 282 printf("\n"); 283 return; 284 } 285 if (intrstr != NULL) 286 printf(": %s\n", intrstr); 287 288 /* 289 * Create the DMA maps for the data transfers. 290 */ 291 292 #define MDL_SEG_SIZE 0x1000 /* 4kbyte per segment */ 293 #define MDL_SEG_OFFSET 0x0FFF 294 #define MDL_SIZE (MAXPHYS / MDL_SEG_SIZE + 1) /* no hardware limit? */ 295 296 if (bus_dmamap_create(esc->sc_dmat, MAXPHYS, MDL_SIZE, MAXPHYS, 0, 297 BUS_DMA_NOWAIT, &esc->sc_xfermap)) { 298 printf("%s: can't create dma maps\n", sc->sc_dev.dv_xname); 299 return; 300 } 301 302 /* 303 * Allocate and map memory for the MDL. 304 */ 305 306 if ((error = bus_dmamem_alloc(esc->sc_dmat, 307 sizeof(u_int32_t) * MDL_SIZE, PAGE_SIZE, 0, &seg, 1, &rseg, 308 BUS_DMA_NOWAIT)) != 0) { 309 printf("%s: unable to allocate memory for the MDL, " 310 "error = %d\n", sc->sc_dev.dv_xname, error); 311 return; 312 } 313 if ((error = bus_dmamem_map(esc->sc_dmat, &seg, rseg, 314 sizeof(u_int32_t) * MDL_SIZE , (caddr_t *)&esc->sc_mdladdr, 315 BUS_DMA_NOWAIT|BUS_DMA_COHERENT)) != 0) { 316 printf("%s: unable to map the MDL memory, error = %d\n", 317 sc->sc_dev.dv_xname, error); 318 return; 319 } 320 if ((error = bus_dmamap_create(esc->sc_dmat, 321 sizeof(u_int32_t) * MDL_SIZE, 1, sizeof(u_int32_t) * MDL_SIZE, 322 0, BUS_DMA_NOWAIT, &esc->sc_mdldmap)) != 0) { 323 printf("%s: unable to map_create for the MDL, error = %d\n", 324 sc->sc_dev.dv_xname, error); 325 return; 326 } 327 if ((error = bus_dmamap_load(esc->sc_dmat, esc->sc_mdldmap, 328 esc->sc_mdladdr, sizeof(u_int32_t) * MDL_SIZE, 329 NULL, BUS_DMA_NOWAIT)) != 0) { 330 printf("%s: unable to load for the MDL, error = %d\n", 331 sc->sc_dev.dv_xname, error); 332 return; 333 } 334 335 /* Do the common parts of attachment. */ 336 printf("%s", sc->sc_dev.dv_xname); 337 338 ncr53c9x_attach(sc, &pcscp_adapter, NULL); 339 340 /* Turn on target selection using the `dma' method */ 341 sc->sc_features |= NCR_F_DMASELECT; 342 } 343 344 /* 345 * Glue functions. 346 */ 347 348 u_char 349 pcscp_read_reg(sc, reg) 350 struct ncr53c9x_softc *sc; 351 int reg; 352 { 353 struct pcscp_softc *esc = (struct pcscp_softc *)sc; 354 355 return bus_space_read_1(esc->sc_st, esc->sc_sh, reg << 2); 356 } 357 358 void 359 pcscp_write_reg(sc, reg, v) 360 struct ncr53c9x_softc *sc; 361 int reg; 362 u_char v; 363 { 364 struct pcscp_softc *esc = (struct pcscp_softc *)sc; 365 366 bus_space_write_1(esc->sc_st, esc->sc_sh, reg << 2, v); 367 } 368 369 int 370 pcscp_dma_isintr(sc) 371 struct ncr53c9x_softc *sc; 372 { 373 374 return NCR_READ_REG(sc, NCR_STAT) & NCRSTAT_INT; 375 } 376 377 void 378 pcscp_dma_reset(sc) 379 struct ncr53c9x_softc *sc; 380 { 381 struct pcscp_softc *esc = (struct pcscp_softc *)sc; 382 383 WRITE_DMAREG(esc, DMA_CMD, DMACMD_IDLE); 384 385 esc->sc_active = 0; 386 } 387 388 int 389 pcscp_dma_intr(sc) 390 struct ncr53c9x_softc *sc; 391 { 392 struct pcscp_softc *esc = (struct pcscp_softc *)sc; 393 int trans, resid, i; 394 bus_dmamap_t dmap = esc->sc_xfermap; 395 int datain = esc->sc_datain; 396 u_int32_t dmastat; 397 char *p = NULL; 398 399 dmastat = READ_DMAREG(esc, DMA_STAT); 400 401 if (dmastat & DMASTAT_ERR) { 402 /* XXX not tested... */ 403 WRITE_DMAREG(esc, DMA_CMD, 404 DMACMD_ABORT | (datain ? DMACMD_DIR : 0)); 405 406 printf("%s: error: DMA error detected; Aborting.\n", 407 sc->sc_dev.dv_xname); 408 bus_dmamap_unload(esc->sc_dmat, dmap); 409 return -1; 410 } 411 412 if (dmastat & DMASTAT_ABT) { 413 /* XXX What should be done? */ 414 printf("%s: dma_intr: DMA aborted.\n", sc->sc_dev.dv_xname); 415 WRITE_DMAREG(esc, DMA_CMD, 416 DMACMD_IDLE | (datain ? DMACMD_DIR : 0)); 417 esc->sc_active = 0; 418 return 0; 419 } 420 421 /* This is an "assertion" :) */ 422 if (esc->sc_active == 0) 423 panic("pcscp dmaintr: DMA wasn't active"); 424 425 /* DMA has stopped */ 426 427 esc->sc_active = 0; 428 429 if (esc->sc_dmasize == 0) { 430 /* A "Transfer Pad" operation completed */ 431 NCR_DMA(("dmaintr: discarded %d bytes (tcl=%d, tcm=%d)\n", 432 NCR_READ_REG(sc, NCR_TCL) | 433 (NCR_READ_REG(sc, NCR_TCM) << 8), 434 NCR_READ_REG(sc, NCR_TCL), 435 NCR_READ_REG(sc, NCR_TCM))); 436 return 0; 437 } 438 439 resid = 0; 440 /* 441 * If a transfer onto the SCSI bus gets interrupted by the device 442 * (e.g. for a SAVEPOINTER message), the data in the FIFO counts 443 * as residual since the ESP counter registers get decremented as 444 * bytes are clocked into the FIFO. 445 */ 446 if (!datain && 447 (resid = (NCR_READ_REG(sc, NCR_FFLAG) & NCRFIFO_FF)) != 0) { 448 NCR_DMA(("pcscp_dma_intr: empty esp FIFO of %d ", resid)); 449 } 450 451 if ((sc->sc_espstat & NCRSTAT_TC) == 0) { 452 /* 453 * `Terminal count' is off, so read the residue 454 * out of the ESP counter registers. 455 */ 456 if (datain) { 457 resid = NCR_READ_REG(sc, NCR_FFLAG) & NCRFIFO_FF; 458 while (resid > 1) 459 resid = 460 NCR_READ_REG(sc, NCR_FFLAG) & NCRFIFO_FF; 461 WRITE_DMAREG(esc, DMA_CMD, DMACMD_BLAST | DMACMD_MDL | 462 (datain ? DMACMD_DIR : 0)); 463 464 for (i = 0; i < 0x8000; i++) /* XXX 0x8000 ? */ 465 if (READ_DMAREG(esc, DMA_STAT) & DMASTAT_BCMP) 466 break; 467 468 /* See the below comments... */ 469 if (resid) 470 p = *esc->sc_dmaaddr; 471 } 472 473 resid += (NCR_READ_REG(sc, NCR_TCL) | 474 (NCR_READ_REG(sc, NCR_TCM) << 8) | 475 ((sc->sc_cfg2 & NCRCFG2_FE) 476 ? (NCR_READ_REG(sc, NCR_TCH) << 16) : 0)); 477 478 if (resid == 0 && esc->sc_dmasize == 65536 && 479 (sc->sc_cfg2 & NCRCFG2_FE) == 0) 480 /* A transfer of 64K is encoded as `TCL=TCM=0' */ 481 resid = 65536; 482 } else { 483 while((dmastat & DMASTAT_DONE) == 0) 484 dmastat = READ_DMAREG(esc, DMA_STAT); 485 } 486 487 WRITE_DMAREG(esc, DMA_CMD, DMACMD_IDLE | (datain ? DMACMD_DIR : 0)); 488 489 bus_dmamap_sync(esc->sc_dmat, dmap, 0, dmap->dm_mapsize, 490 datain ? BUS_DMASYNC_POSTREAD : BUS_DMASYNC_POSTWRITE); 491 bus_dmamap_unload(esc->sc_dmat, dmap); 492 493 trans = esc->sc_dmasize - resid; 494 495 /* 496 * From the technical manual notes: 497 * 498 * `In some odd byte conditions, one residual byte will be left 499 * in the SCSI FIFO, and the FIFO flags will never count to 0. 500 * When this happens, the residual byte should be retrieved 501 * via PIO following completion of the BLAST operation.' 502 */ 503 504 if (p) { 505 p += trans; 506 *p = NCR_READ_REG(sc, NCR_FIFO); 507 trans++; 508 } 509 510 if (trans < 0) { /* transferred < 0 ? */ 511 #if 0 512 /* 513 * This situation can happen in perfectly normal operation 514 * if the ESP is reselected while using DMA to select 515 * another target. As such, don't print the warning. 516 */ 517 printf("%s: xfer (%d) > req (%d)\n", 518 sc->sc_dev.dv_xname, trans, esc->sc_dmasize); 519 #endif 520 trans = esc->sc_dmasize; 521 } 522 523 NCR_DMA(("dmaintr: tcl=%d, tcm=%d, tch=%d; trans=%d, resid=%d\n", 524 NCR_READ_REG(sc, NCR_TCL), 525 NCR_READ_REG(sc, NCR_TCM), 526 (sc->sc_cfg2 & NCRCFG2_FE) ? NCR_READ_REG(sc, NCR_TCH) : 0, 527 trans, resid)); 528 529 *esc->sc_dmalen -= trans; 530 *esc->sc_dmaaddr += trans; 531 532 return 0; 533 } 534 535 int 536 pcscp_dma_setup(sc, addr, len, datain, dmasize) 537 struct ncr53c9x_softc *sc; 538 caddr_t *addr; 539 size_t *len; 540 int datain; 541 size_t *dmasize; 542 { 543 struct pcscp_softc *esc = (struct pcscp_softc *)sc; 544 bus_dmamap_t dmap = esc->sc_xfermap; 545 u_int32_t *mdl; 546 int error, nseg, seg; 547 bus_addr_t s_offset, s_addr; 548 long rest, count; 549 550 WRITE_DMAREG(esc, DMA_CMD, DMACMD_IDLE | (datain ? DMACMD_DIR : 0)); 551 552 esc->sc_dmaaddr = addr; 553 esc->sc_dmalen = len; 554 esc->sc_dmasize = *dmasize; 555 esc->sc_datain = datain; 556 557 #ifdef DIAGNOSTIC 558 if ((*dmasize / MDL_SEG_SIZE) > MDL_SIZE) 559 panic("pcscp: transfer size too large"); 560 #endif 561 562 /* 563 * No need to set up DMA in `Transfer Pad' operation. 564 * (case of *dmasize == 0) 565 */ 566 if (*dmasize == 0) 567 return 0; 568 569 error = bus_dmamap_load(esc->sc_dmat, dmap, *esc->sc_dmaaddr, 570 *esc->sc_dmalen, NULL, 571 sc->sc_nexus->xs->flags & SCSI_NOSLEEP ? 572 BUS_DMA_NOWAIT : BUS_DMA_WAITOK); 573 if (error) { 574 printf("%s: unable to load dmamap, error = %d\n", 575 sc->sc_dev.dv_xname, error); 576 return error; 577 } 578 579 /* set transfer length */ 580 WRITE_DMAREG(esc, DMA_STC, *dmasize); 581 582 /* set up MDL */ 583 mdl = esc->sc_mdladdr; 584 nseg = dmap->dm_nsegs; 585 586 /* the first segment is possibly not aligned with 4k MDL boundary */ 587 count = dmap->dm_segs[0].ds_len; 588 s_addr = dmap->dm_segs[0].ds_addr; 589 s_offset = s_addr & MDL_SEG_OFFSET; 590 s_addr -= s_offset; 591 rest = MDL_SEG_SIZE - s_offset; 592 593 /* set the first MDL and offset */ 594 WRITE_DMAREG(esc, DMA_SPA, s_offset); 595 *mdl++ = htole32(s_addr); 596 count -= rest; 597 598 /* rests of the first dmamap segment */ 599 while (count > 0) { 600 s_addr += MDL_SEG_SIZE; 601 *mdl++ = htole32(s_addr); 602 count -= MDL_SEG_SIZE; 603 } 604 605 /* the rest dmamap segments are aligned with 4k boundary */ 606 for (seg = 1; seg < nseg; seg++) { 607 count = dmap->dm_segs[seg].ds_len; 608 s_addr = dmap->dm_segs[seg].ds_addr; 609 610 /* first 4kbyte of each dmamap segment */ 611 *mdl++ = htole32(s_addr); 612 count -= MDL_SEG_SIZE; 613 614 /* trailing contiguous 4k frames of each dmamap segments */ 615 while (count > 0) { 616 s_addr += MDL_SEG_SIZE; 617 *mdl++ = htole32(s_addr); 618 count -= MDL_SEG_SIZE; 619 } 620 } 621 622 return 0; 623 } 624 625 void 626 pcscp_dma_go(sc) 627 struct ncr53c9x_softc *sc; 628 { 629 struct pcscp_softc *esc = (struct pcscp_softc *)sc; 630 bus_dmamap_t dmap = esc->sc_xfermap, mdldmap = esc->sc_mdldmap; 631 int datain = esc->sc_datain; 632 633 /* No DMA transfer in Transfer Pad operation */ 634 if (esc->sc_dmasize == 0) 635 return; 636 637 /* sync transfer buffer */ 638 bus_dmamap_sync(esc->sc_dmat, dmap, 0, dmap->dm_mapsize, 639 datain ? BUS_DMASYNC_PREREAD : BUS_DMASYNC_PREWRITE); 640 641 /* sync MDL */ 642 bus_dmamap_sync(esc->sc_dmat, mdldmap, 0, mdldmap->dm_mapsize, 643 BUS_DMASYNC_PREWRITE); 644 645 /* set Starting MDL Address */ 646 WRITE_DMAREG(esc, DMA_SMDLA, mdldmap->dm_segs[0].ds_addr); 647 648 /* set DMA command register bits */ 649 /* XXX DMA Transfer Interrupt Enable bit is broken? */ 650 WRITE_DMAREG(esc, DMA_CMD, DMACMD_IDLE | DMACMD_MDL | 651 /* DMACMD_INTE | */ 652 (datain ? DMACMD_DIR : 0)); 653 654 /* issue DMA start command */ 655 WRITE_DMAREG(esc, DMA_CMD, DMACMD_START | DMACMD_MDL | 656 /* DMACMD_INTE | */ 657 (datain ? DMACMD_DIR : 0)); 658 659 esc->sc_active = 1; 660 } 661 662 void 663 pcscp_dma_stop(sc) 664 struct ncr53c9x_softc *sc; 665 { 666 struct pcscp_softc *esc = (struct pcscp_softc *)sc; 667 668 /* dma stop */ 669 /* XXX What should we do here ? */ 670 WRITE_DMAREG(esc, DMA_CMD, 671 DMACMD_ABORT | (esc->sc_datain ? DMACMD_DIR : 0)); 672 673 esc->sc_active = 0; 674 } 675 676 int 677 pcscp_dma_isactive(sc) 678 struct ncr53c9x_softc *sc; 679 { 680 struct pcscp_softc *esc = (struct pcscp_softc *)sc; 681 682 /* XXX should check esc->sc_active? */ 683 if ((READ_DMAREG(esc, DMA_CMD) & DMACMD_CMD) != DMACMD_IDLE) 684 return 1; 685 return 0; 686 } 687