1 /* $OpenBSD: pcscp.c,v 1.22 2024/05/24 06:02:58 jsg Exp $ */ 2 /* $NetBSD: pcscp.c,v 1.26 2003/10/19 10:25:42 tsutsui Exp $ */ 3 4 /*- 5 * Copyright (c) 1997, 1998, 1999 The NetBSD Foundation, Inc. 6 * All rights reserved. 7 * 8 * This code is derived from software contributed to The NetBSD Foundation 9 * by Jason R. Thorpe of the Numerical Aerospace Simulation Facility, 10 * NASA Ames Research Center; Izumi Tsutsui. 11 * 12 * Redistribution and use in source and binary forms, with or without 13 * modification, are permitted provided that the following conditions 14 * are met: 15 * 1. Redistributions of source code must retain the above copyright 16 * notice, this list of conditions and the following disclaimer. 17 * 2. Redistributions in binary form must reproduce the above copyright 18 * notice, this list of conditions and the following disclaimer in the 19 * documentation and/or other materials provided with the distribution. 20 * 21 * THIS SOFTWARE IS PROVIDED BY THE NETBSD FOUNDATION, INC. AND CONTRIBUTORS 22 * ``AS IS'' AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED 23 * TO, THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR 24 * PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL THE FOUNDATION OR CONTRIBUTORS 25 * BE LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR 26 * CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF 27 * SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS 28 * INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN 29 * CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) 30 * ARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE 31 * POSSIBILITY OF SUCH DAMAGE. 32 */ 33 34 /* 35 * pcscp.c: device dependent code for AMD Am53c974 (PCscsi-PCI) 36 * written by Izumi Tsutsui <tsutsui@ceres.dti.ne.jp> 37 * 38 * Technical manual available at 39 * http://www.amd.com/files/connectivitysolutions/networking/archivednetworking/19113.pdf 40 */ 41 42 #include <sys/param.h> 43 #include <sys/systm.h> 44 #include <sys/device.h> 45 46 #include <machine/bus.h> 47 48 #include <scsi/scsi_all.h> 49 #include <scsi/scsiconf.h> 50 #include <scsi/scsi_message.h> 51 52 #include <dev/pci/pcireg.h> 53 #include <dev/pci/pcivar.h> 54 #include <dev/pci/pcidevs.h> 55 56 #include <dev/ic/ncr53c9xreg.h> 57 #include <dev/ic/ncr53c9xvar.h> 58 59 #include <dev/pci/pcscpreg.h> 60 61 #define IO_MAP_REG 0x10 62 63 struct pcscp_softc { 64 struct ncr53c9x_softc sc_ncr53c9x; /* glue to MI code */ 65 66 bus_space_tag_t sc_st; /* bus space tag */ 67 bus_space_handle_t sc_sh; /* bus space handle */ 68 void *sc_ih; /* interrupt cookie */ 69 70 bus_dma_tag_t sc_dmat; /* DMA tag */ 71 72 bus_dmamap_t sc_xfermap; /* DMA map for transfers */ 73 74 u_int32_t *sc_mdladdr; /* MDL array */ 75 bus_dmamap_t sc_mdldmap; /* MDL DMA map */ 76 77 int sc_active; /* DMA state */ 78 int sc_datain; /* DMA Data Direction */ 79 size_t sc_dmasize; /* DMA size */ 80 char **sc_dmaaddr; /* DMA address */ 81 size_t *sc_dmalen; /* DMA length */ 82 }; 83 84 #define READ_DMAREG(sc, reg) \ 85 bus_space_read_4((sc)->sc_st, (sc)->sc_sh, (reg)) 86 #define WRITE_DMAREG(sc, reg, var) \ 87 bus_space_write_4((sc)->sc_st, (sc)->sc_sh, (reg), (var)) 88 89 #define PCSCP_READ_REG(sc, reg) \ 90 bus_space_read_1((sc)->sc_st, (sc)->sc_sh, (reg) << 2) 91 #define PCSCP_WRITE_REG(sc, reg, val) \ 92 bus_space_write_1((sc)->sc_st, (sc)->sc_sh, (reg) << 2, (val)) 93 94 int pcscp_match(struct device *, void *, void *); 95 void pcscp_attach(struct device *, struct device *, void *); 96 97 const struct cfattach pcscp_ca = { 98 sizeof(struct pcscp_softc), pcscp_match, pcscp_attach 99 }; 100 101 struct cfdriver pcscp_cd = { 102 NULL, "pcscp", DV_DULL 103 }; 104 105 /* 106 * Functions and the switch for the MI code. 107 */ 108 109 u_char pcscp_read_reg(struct ncr53c9x_softc *, int); 110 void pcscp_write_reg(struct ncr53c9x_softc *, int, u_char); 111 int pcscp_dma_isintr(struct ncr53c9x_softc *); 112 void pcscp_dma_reset(struct ncr53c9x_softc *); 113 int pcscp_dma_intr(struct ncr53c9x_softc *); 114 int pcscp_dma_setup(struct ncr53c9x_softc *, caddr_t *, 115 size_t *, int, size_t *); 116 void pcscp_dma_go(struct ncr53c9x_softc *); 117 void pcscp_dma_stop(struct ncr53c9x_softc *); 118 int pcscp_dma_isactive(struct ncr53c9x_softc *); 119 120 struct ncr53c9x_glue pcscp_glue = { 121 pcscp_read_reg, 122 pcscp_write_reg, 123 pcscp_dma_isintr, 124 pcscp_dma_reset, 125 pcscp_dma_intr, 126 pcscp_dma_setup, 127 pcscp_dma_go, 128 pcscp_dma_stop, 129 pcscp_dma_isactive, 130 NULL, /* gl_clear_latched_intr */ 131 }; 132 133 int 134 pcscp_match(struct device *parent, void *match, void *aux) 135 { 136 struct pci_attach_args *pa = aux; 137 138 if (PCI_VENDOR(pa->pa_id) != PCI_VENDOR_AMD) 139 return 0; 140 141 switch (PCI_PRODUCT(pa->pa_id)) { 142 case PCI_PRODUCT_AMD_PCSCSI_PCI: 143 return 1; 144 } 145 return 0; 146 } 147 148 /* 149 * Attach this instance, and then all the sub-devices 150 */ 151 void 152 pcscp_attach(struct device *parent, struct device *self, void *aux) 153 { 154 struct pci_attach_args *pa = aux; 155 struct pcscp_softc *esc = (void *)self; 156 struct ncr53c9x_softc *sc = &esc->sc_ncr53c9x; 157 bus_space_tag_t iot; 158 bus_space_handle_t ioh; 159 pci_intr_handle_t ih; 160 const char *intrstr; 161 bus_dma_segment_t seg; 162 int error, rseg; 163 164 if (pci_mapreg_map(pa, IO_MAP_REG, PCI_MAPREG_TYPE_IO, 0, 165 &iot, &ioh, NULL, NULL, 0)) { 166 printf("%s: unable to map registers\n", sc->sc_dev.dv_xname); 167 return; 168 } 169 170 sc->sc_glue = &pcscp_glue; 171 172 esc->sc_st = iot; 173 esc->sc_sh = ioh; 174 esc->sc_dmat = pa->pa_dmat; 175 176 /* 177 * XXX More of this should be in ncr53c9x_attach(), but 178 * XXX should we really poke around the chip that much in 179 * XXX the MI code? Think about this more... 180 */ 181 182 /* 183 * Set up static configuration info. 184 */ 185 186 /* 187 * XXX should read configuration from EEPROM? 188 * 189 * MI ncr53c9x driver does not support configuration 190 * per each target device, though... 191 */ 192 sc->sc_id = 7; 193 sc->sc_cfg1 = sc->sc_id | NCRCFG1_PARENB; 194 sc->sc_cfg2 = NCRCFG2_SCSI2 | NCRCFG2_FE; 195 sc->sc_cfg3 = NCRAMDCFG3_IDM | NCRAMDCFG3_FCLK; 196 sc->sc_cfg4 = NCRAMDCFG4_GE12NS | NCRAMDCFG4_RADE; 197 sc->sc_rev = NCR_VARIANT_AM53C974; 198 sc->sc_features = NCR_F_FASTSCSI; 199 sc->sc_cfg3_fscsi = NCRAMDCFG3_FSCSI; 200 sc->sc_freq = 40; /* MHz */ 201 202 /* 203 * XXX minsync and maxxfer _should_ be set up in MI code, 204 * XXX but it appears to have some dependency on what sort 205 * XXX of DMA we're hooked up to, etc. 206 */ 207 208 /* 209 * This is the value used to start sync negotiations 210 * Note that the NCR register "SYNCTP" is programmed 211 * in "clocks per byte", and has a minimum value of 4. 212 * The SCSI period used in negotiation is one-fourth 213 * of the time (in nanoseconds) needed to transfer one byte. 214 * Since the chip's clock is given in MHz, we have the following 215 * formula: 4 * period = (1000 / freq) * 4 216 */ 217 218 sc->sc_minsync = 1000 / sc->sc_freq; 219 220 /* Really no limit, but since we want to fit into the TCR... */ 221 sc->sc_maxxfer = 16 * 1024 * 1024; 222 223 /* 224 * Create the DMA maps for the data transfers. 225 */ 226 227 #define MDL_SEG_SIZE 0x1000 /* 4kbyte per segment */ 228 #define MDL_SEG_OFFSET 0x0FFF 229 #define MDL_SIZE (MAXPHYS / MDL_SEG_SIZE + 1) /* no hardware limit? */ 230 231 if (bus_dmamap_create(esc->sc_dmat, MAXPHYS, MDL_SIZE, MDL_SEG_SIZE, 232 MDL_SEG_SIZE, BUS_DMA_NOWAIT, &esc->sc_xfermap)) { 233 printf("%s: can't create dma maps\n", sc->sc_dev.dv_xname); 234 return; 235 } 236 237 /* 238 * Allocate and map memory for the MDL. 239 */ 240 241 if ((error = bus_dmamem_alloc(esc->sc_dmat, 242 sizeof(u_int32_t) * MDL_SIZE, PAGE_SIZE, 0, &seg, 1, &rseg, 243 BUS_DMA_NOWAIT)) != 0) { 244 printf("%s: unable to allocate memory for the MDL, " 245 "error = %d\n", sc->sc_dev.dv_xname, error); 246 goto fail_0; 247 } 248 if ((error = bus_dmamem_map(esc->sc_dmat, &seg, rseg, 249 sizeof(u_int32_t) * MDL_SIZE , (caddr_t *)&esc->sc_mdladdr, 250 BUS_DMA_NOWAIT|BUS_DMA_COHERENT)) != 0) { 251 printf("%s: unable to map the MDL memory, error = %d\n", 252 sc->sc_dev.dv_xname, error); 253 goto fail_1; 254 } 255 if ((error = bus_dmamap_create(esc->sc_dmat, 256 sizeof(u_int32_t) * MDL_SIZE, 1, sizeof(u_int32_t) * MDL_SIZE, 257 0, BUS_DMA_NOWAIT, &esc->sc_mdldmap)) != 0) { 258 printf("%s: unable to map_create for the MDL, error = %d\n", 259 sc->sc_dev.dv_xname, error); 260 goto fail_2; 261 } 262 if ((error = bus_dmamap_load(esc->sc_dmat, esc->sc_mdldmap, 263 esc->sc_mdladdr, sizeof(u_int32_t) * MDL_SIZE, 264 NULL, BUS_DMA_NOWAIT)) != 0) { 265 printf("%s: unable to load for the MDL, error = %d\n", 266 sc->sc_dev.dv_xname, error); 267 goto fail_3; 268 } 269 270 /* map and establish interrupt */ 271 if (pci_intr_map(pa, &ih)) { 272 printf(": couldn't map interrupt\n"); 273 goto fail_4; 274 } 275 276 intrstr = pci_intr_string(pa->pa_pc, ih); 277 esc->sc_ih = pci_intr_establish(pa->pa_pc, ih, IPL_BIO, 278 ncr53c9x_intr, esc, sc->sc_dev.dv_xname); 279 if (esc->sc_ih == NULL) { 280 printf(": couldn't establish interrupt"); 281 if (intrstr != NULL) 282 printf(" at %s", intrstr); 283 printf("\n"); 284 goto fail_4; 285 } 286 if (intrstr != NULL) 287 printf(": %s\n", intrstr); 288 289 /* Do the common parts of attachment. */ 290 printf("%s", sc->sc_dev.dv_xname); 291 292 ncr53c9x_attach(sc); 293 294 /* Turn on target selection using the `dma' method */ 295 sc->sc_features |= NCR_F_DMASELECT; 296 297 return; 298 299 fail_4: 300 bus_dmamap_unload(esc->sc_dmat, esc->sc_mdldmap); 301 fail_3: 302 bus_dmamap_destroy(esc->sc_dmat, esc->sc_mdldmap); 303 fail_2: 304 bus_dmamem_unmap(esc->sc_dmat, (caddr_t)esc->sc_mdldmap, 305 sizeof(uint32_t) * MDL_SIZE); 306 fail_1: 307 bus_dmamem_free(esc->sc_dmat, &seg, rseg); 308 fail_0: 309 bus_dmamap_destroy(esc->sc_dmat, esc->sc_xfermap); 310 } 311 312 /* 313 * Glue functions. 314 */ 315 316 u_char 317 pcscp_read_reg(struct ncr53c9x_softc *sc, int reg) 318 { 319 struct pcscp_softc *esc = (struct pcscp_softc *)sc; 320 321 return PCSCP_READ_REG(esc, reg); 322 } 323 324 void 325 pcscp_write_reg(struct ncr53c9x_softc *sc, int reg, u_char v) 326 { 327 struct pcscp_softc *esc = (struct pcscp_softc *)sc; 328 329 PCSCP_WRITE_REG(esc, reg, v); 330 } 331 332 int 333 pcscp_dma_isintr(struct ncr53c9x_softc *sc) 334 { 335 struct pcscp_softc *esc = (struct pcscp_softc *)sc; 336 337 return (PCSCP_READ_REG(esc, NCR_STAT) & NCRSTAT_INT) != 0; 338 } 339 340 void 341 pcscp_dma_reset(struct ncr53c9x_softc *sc) 342 { 343 struct pcscp_softc *esc = (struct pcscp_softc *)sc; 344 345 WRITE_DMAREG(esc, DMA_CMD, DMACMD_IDLE); 346 347 esc->sc_active = 0; 348 } 349 350 int 351 pcscp_dma_intr(struct ncr53c9x_softc *sc) 352 { 353 struct pcscp_softc *esc = (struct pcscp_softc *)sc; 354 int trans, resid, i; 355 bus_dmamap_t dmap = esc->sc_xfermap; 356 int datain = esc->sc_datain; 357 u_int32_t dmastat; 358 char *p = NULL; 359 360 dmastat = READ_DMAREG(esc, DMA_STAT); 361 362 if (dmastat & DMASTAT_ERR) { 363 /* XXX not tested... */ 364 WRITE_DMAREG(esc, DMA_CMD, 365 DMACMD_ABORT | (datain ? DMACMD_DIR : 0)); 366 367 printf("%s: error: DMA error detected; Aborting.\n", 368 sc->sc_dev.dv_xname); 369 bus_dmamap_unload(esc->sc_dmat, dmap); 370 return -1; 371 } 372 373 if (dmastat & DMASTAT_ABT) { 374 /* XXX What should be done? */ 375 printf("%s: dma_intr: DMA aborted.\n", sc->sc_dev.dv_xname); 376 WRITE_DMAREG(esc, DMA_CMD, 377 DMACMD_IDLE | (datain ? DMACMD_DIR : 0)); 378 esc->sc_active = 0; 379 return 0; 380 } 381 382 #ifdef DIAGNOSTIC 383 /* This is an "assertion" :) */ 384 if (esc->sc_active == 0) 385 panic("pcscp dmaintr: DMA wasn't active"); 386 #endif 387 388 /* DMA has stopped */ 389 390 esc->sc_active = 0; 391 392 if (esc->sc_dmasize == 0) { 393 /* A "Transfer Pad" operation completed */ 394 NCR_DMA(("dmaintr: discarded %d bytes (tcl=%d, tcm=%d)\n", 395 PCSCP_READ_REG(esc, NCR_TCL) | 396 (PCSCP_READ_REG(esc, NCR_TCM) << 8), 397 PCSCP_READ_REG(esc, NCR_TCL), 398 PCSCP_READ_REG(esc, NCR_TCM))); 399 return 0; 400 } 401 402 resid = 0; 403 /* 404 * If a transfer onto the SCSI bus gets interrupted by the device 405 * (e.g. for a SAVEPOINTER message), the data in the FIFO counts 406 * as residual since the ESP counter registers get decremented as 407 * bytes are clocked into the FIFO. 408 */ 409 if (!datain && 410 (resid = (PCSCP_READ_REG(esc, NCR_FFLAG) & NCRFIFO_FF)) != 0) { 411 NCR_DMA(("pcscp_dma_intr: empty esp FIFO of %d ", resid)); 412 } 413 414 if ((sc->sc_espstat & NCRSTAT_TC) == 0) { 415 /* 416 * `Terminal count' is off, so read the residue 417 * out of the ESP counter registers. 418 */ 419 if (datain) { 420 resid = PCSCP_READ_REG(esc, NCR_FFLAG) & NCRFIFO_FF; 421 while (resid > 1) 422 resid = 423 PCSCP_READ_REG(esc, NCR_FFLAG) & NCRFIFO_FF; 424 WRITE_DMAREG(esc, DMA_CMD, DMACMD_BLAST | DMACMD_MDL | 425 (datain ? DMACMD_DIR : 0)); 426 427 for (i = 0; i < 0x8000; i++) /* XXX 0x8000 ? */ 428 if (READ_DMAREG(esc, DMA_STAT) & DMASTAT_BCMP) 429 break; 430 431 /* See the below comments... */ 432 if (resid) 433 p = *esc->sc_dmaaddr; 434 } 435 436 resid += PCSCP_READ_REG(esc, NCR_TCL) | 437 (PCSCP_READ_REG(esc, NCR_TCM) << 8) | 438 (PCSCP_READ_REG(esc, NCR_TCH) << 16); 439 } else { 440 while ((dmastat & DMASTAT_DONE) == 0) 441 dmastat = READ_DMAREG(esc, DMA_STAT); 442 } 443 444 WRITE_DMAREG(esc, DMA_CMD, DMACMD_IDLE | (datain ? DMACMD_DIR : 0)); 445 446 /* sync MDL */ 447 bus_dmamap_sync(esc->sc_dmat, esc->sc_mdldmap, 448 0, sizeof(u_int32_t) * dmap->dm_nsegs, BUS_DMASYNC_POSTWRITE); 449 /* sync transfer buffer */ 450 bus_dmamap_sync(esc->sc_dmat, dmap, 0, dmap->dm_mapsize, 451 datain ? BUS_DMASYNC_POSTREAD : BUS_DMASYNC_POSTWRITE); 452 bus_dmamap_unload(esc->sc_dmat, dmap); 453 454 trans = esc->sc_dmasize - resid; 455 456 /* 457 * From the technical manual notes: 458 * 459 * `In some odd byte conditions, one residual byte will be left 460 * in the SCSI FIFO, and the FIFO flags will never count to 0. 461 * When this happens, the residual byte should be retrieved 462 * via PIO following completion of the BLAST operation.' 463 */ 464 465 if (p) { 466 p += trans; 467 *p = PCSCP_READ_REG(esc, NCR_FIFO); 468 trans++; 469 } 470 471 if (trans < 0) { /* transferred < 0 ? */ 472 #if 0 473 /* 474 * This situation can happen in perfectly normal operation 475 * if the ESP is reselected while using DMA to select 476 * another target. As such, don't print the warning. 477 */ 478 printf("%s: xfer (%d) > req (%d)\n", 479 sc->sc_dev.dv_xname, trans, esc->sc_dmasize); 480 #endif 481 trans = esc->sc_dmasize; 482 } 483 484 NCR_DMA(("dmaintr: tcl=%d, tcm=%d, tch=%d; trans=%d, resid=%d\n", 485 PCSCP_READ_REG(esc, NCR_TCL), 486 PCSCP_READ_REG(esc, NCR_TCM), 487 PCSCP_READ_REG(esc, NCR_TCH), 488 trans, resid)); 489 490 *esc->sc_dmalen -= trans; 491 *esc->sc_dmaaddr += trans; 492 493 return 0; 494 } 495 496 int 497 pcscp_dma_setup(struct ncr53c9x_softc *sc, caddr_t *addr, size_t *len, 498 int datain, size_t *dmasize) 499 { 500 struct pcscp_softc *esc = (struct pcscp_softc *)sc; 501 bus_dmamap_t dmap = esc->sc_xfermap; 502 u_int32_t *mdl; 503 int error, nseg, seg; 504 bus_addr_t s_offset, s_addr; 505 506 WRITE_DMAREG(esc, DMA_CMD, DMACMD_IDLE | (datain ? DMACMD_DIR : 0)); 507 508 esc->sc_dmaaddr = addr; 509 esc->sc_dmalen = len; 510 esc->sc_dmasize = *dmasize; 511 esc->sc_datain = datain; 512 513 #ifdef DIAGNOSTIC 514 if ((*dmasize / MDL_SEG_SIZE) > MDL_SIZE) 515 panic("pcscp: transfer size too large"); 516 #endif 517 518 /* 519 * No need to set up DMA in `Transfer Pad' operation. 520 * (case of *dmasize == 0) 521 */ 522 if (*dmasize == 0) 523 return 0; 524 525 error = bus_dmamap_load(esc->sc_dmat, dmap, *esc->sc_dmaaddr, 526 *esc->sc_dmalen, NULL, 527 ((sc->sc_nexus->xs->flags & SCSI_NOSLEEP) ? 528 BUS_DMA_NOWAIT : BUS_DMA_WAITOK) | BUS_DMA_STREAMING | 529 ((sc->sc_nexus->xs->flags & SCSI_DATA_IN) ? 530 BUS_DMA_READ : BUS_DMA_WRITE)); 531 if (error) { 532 printf("%s: unable to load dmamap, error = %d\n", 533 sc->sc_dev.dv_xname, error); 534 return error; 535 } 536 537 /* set transfer length */ 538 WRITE_DMAREG(esc, DMA_STC, *dmasize); 539 540 /* set up MDL */ 541 mdl = esc->sc_mdladdr; 542 nseg = dmap->dm_nsegs; 543 544 /* the first segment is possibly not aligned with 4k MDL boundary */ 545 s_addr = dmap->dm_segs[0].ds_addr; 546 s_offset = s_addr & MDL_SEG_OFFSET; 547 s_addr -= s_offset; 548 549 /* set the first MDL and offset */ 550 WRITE_DMAREG(esc, DMA_SPA, s_offset); 551 *mdl++ = htole32(s_addr); 552 553 /* the rest dmamap segments are aligned with 4k boundary */ 554 for (seg = 1; seg < nseg; seg++) 555 *mdl++ = htole32(dmap->dm_segs[seg].ds_addr); 556 557 return 0; 558 } 559 560 void 561 pcscp_dma_go(struct ncr53c9x_softc *sc) 562 { 563 struct pcscp_softc *esc = (struct pcscp_softc *)sc; 564 bus_dmamap_t dmap = esc->sc_xfermap, mdldmap = esc->sc_mdldmap; 565 int datain = esc->sc_datain; 566 567 /* No DMA transfer in Transfer Pad operation */ 568 if (esc->sc_dmasize == 0) 569 return; 570 571 /* sync transfer buffer */ 572 bus_dmamap_sync(esc->sc_dmat, dmap, 0, dmap->dm_mapsize, 573 datain ? BUS_DMASYNC_PREREAD : BUS_DMASYNC_PREWRITE); 574 575 /* sync MDL */ 576 bus_dmamap_sync(esc->sc_dmat, mdldmap, 577 0, sizeof(u_int32_t) * dmap->dm_nsegs, BUS_DMASYNC_PREWRITE); 578 579 /* set Starting MDL Address */ 580 WRITE_DMAREG(esc, DMA_SMDLA, mdldmap->dm_segs[0].ds_addr); 581 582 /* set DMA command register bits */ 583 /* XXX DMA Transfer Interrupt Enable bit is broken? */ 584 WRITE_DMAREG(esc, DMA_CMD, DMACMD_IDLE | DMACMD_MDL | 585 /* DMACMD_INTE | */ 586 (datain ? DMACMD_DIR : 0)); 587 588 /* issue DMA start command */ 589 WRITE_DMAREG(esc, DMA_CMD, DMACMD_START | DMACMD_MDL | 590 /* DMACMD_INTE | */ 591 (datain ? DMACMD_DIR : 0)); 592 593 esc->sc_active = 1; 594 } 595 596 void 597 pcscp_dma_stop(struct ncr53c9x_softc *sc) 598 { 599 struct pcscp_softc *esc = (struct pcscp_softc *)sc; 600 601 /* dma stop */ 602 /* XXX What should we do here ? */ 603 WRITE_DMAREG(esc, DMA_CMD, 604 DMACMD_ABORT | (esc->sc_datain ? DMACMD_DIR : 0)); 605 bus_dmamap_unload(esc->sc_dmat, esc->sc_xfermap); 606 607 esc->sc_active = 0; 608 } 609 610 int 611 pcscp_dma_isactive(struct ncr53c9x_softc *sc) 612 { 613 struct pcscp_softc *esc = (struct pcscp_softc *)sc; 614 615 /* XXX should check esc->sc_active? */ 616 if ((READ_DMAREG(esc, DMA_CMD) & DMACMD_CMD) != DMACMD_IDLE) 617 return 1; 618 return 0; 619 } 620