1 /* $OpenBSD: pciide.c,v 1.289 2008/09/25 19:06:57 chl Exp $ */ 2 /* $NetBSD: pciide.c,v 1.127 2001/08/03 01:31:08 tsutsui Exp $ */ 3 4 /* 5 * Copyright (c) 1999, 2000, 2001 Manuel Bouyer. 6 * 7 * Redistribution and use in source and binary forms, with or without 8 * modification, are permitted provided that the following conditions 9 * are met: 10 * 1. Redistributions of source code must retain the above copyright 11 * notice, this list of conditions and the following disclaimer. 12 * 2. Redistributions in binary form must reproduce the above copyright 13 * notice, this list of conditions and the following disclaimer in the 14 * documentation and/or other materials provided with the distribution. 15 * 3. All advertising materials mentioning features or use of this software 16 * must display the following acknowledgement: 17 * This product includes software developed by Manuel Bouyer. 18 * 4. Neither the name of the University nor the names of its contributors 19 * may be used to endorse or promote products derived from this software 20 * without specific prior written permission. 21 * 22 * THIS SOFTWARE IS PROVIDED BY THE AUTHOR ``AS IS'' AND ANY EXPRESS OR 23 * IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED WARRANTIES 24 * OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE DISCLAIMED. 25 * IN NO EVENT SHALL THE AUTHOR BE LIABLE FOR ANY DIRECT, INDIRECT, 26 * INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT 27 * NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, 28 * DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY 29 * THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT 30 * (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE OF 31 * THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE. 32 * 33 */ 34 35 /* 36 * Copyright (c) 1996, 1998 Christopher G. Demetriou. All rights reserved. 37 * 38 * Redistribution and use in source and binary forms, with or without 39 * modification, are permitted provided that the following conditions 40 * are met: 41 * 1. Redistributions of source code must retain the above copyright 42 * notice, this list of conditions and the following disclaimer. 43 * 2. Redistributions in binary form must reproduce the above copyright 44 * notice, this list of conditions and the following disclaimer in the 45 * documentation and/or other materials provided with the distribution. 46 * 3. All advertising materials mentioning features or use of this software 47 * must display the following acknowledgement: 48 * This product includes software developed by Christopher G. Demetriou 49 * for the NetBSD Project. 50 * 4. The name of the author may not be used to endorse or promote products 51 * derived from this software without specific prior written permission 52 * 53 * THIS SOFTWARE IS PROVIDED BY THE AUTHOR ``AS IS'' AND ANY EXPRESS OR 54 * IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED WARRANTIES 55 * OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE DISCLAIMED. 56 * IN NO EVENT SHALL THE AUTHOR BE LIABLE FOR ANY DIRECT, INDIRECT, 57 * INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT 58 * NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, 59 * DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY 60 * THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT 61 * (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE OF 62 * THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE. 63 */ 64 65 /* 66 * PCI IDE controller driver. 67 * 68 * Author: Christopher G. Demetriou, March 2, 1998 (derived from NetBSD 69 * sys/dev/pci/ppb.c, revision 1.16). 70 * 71 * See "PCI IDE Controller Specification, Revision 1.0 3/4/94" and 72 * "Programming Interface for Bus Master IDE Controller, Revision 1.0 73 * 5/16/94" from the PCI SIG. 74 * 75 */ 76 77 #define DEBUG_DMA 0x01 78 #define DEBUG_XFERS 0x02 79 #define DEBUG_FUNCS 0x08 80 #define DEBUG_PROBE 0x10 81 82 #ifdef WDCDEBUG 83 #ifndef WDCDEBUG_PCIIDE_MASK 84 #define WDCDEBUG_PCIIDE_MASK 0x00 85 #endif 86 int wdcdebug_pciide_mask = WDCDEBUG_PCIIDE_MASK; 87 #define WDCDEBUG_PRINT(args, level) do { \ 88 if ((wdcdebug_pciide_mask & (level)) != 0) \ 89 printf args; \ 90 } while (0) 91 #else 92 #define WDCDEBUG_PRINT(args, level) 93 #endif 94 #include <sys/param.h> 95 #include <sys/systm.h> 96 #include <sys/device.h> 97 #include <sys/malloc.h> 98 99 #include <machine/bus.h> 100 #include <machine/endian.h> 101 102 #include <dev/ata/atavar.h> 103 #include <dev/ata/satareg.h> 104 #include <dev/ic/wdcreg.h> 105 #include <dev/ic/wdcvar.h> 106 107 #include <dev/pci/pcireg.h> 108 #include <dev/pci/pcivar.h> 109 #include <dev/pci/pcidevs.h> 110 111 #include <dev/pci/pciidereg.h> 112 #include <dev/pci/pciidevar.h> 113 #include <dev/pci/pciide_piix_reg.h> 114 #include <dev/pci/pciide_amd_reg.h> 115 #include <dev/pci/pciide_apollo_reg.h> 116 #include <dev/pci/pciide_cmd_reg.h> 117 #include <dev/pci/pciide_sii3112_reg.h> 118 #include <dev/pci/pciide_cy693_reg.h> 119 #include <dev/pci/pciide_sis_reg.h> 120 #include <dev/pci/pciide_acer_reg.h> 121 #include <dev/pci/pciide_pdc202xx_reg.h> 122 #include <dev/pci/pciide_opti_reg.h> 123 #include <dev/pci/pciide_hpt_reg.h> 124 #include <dev/pci/pciide_acard_reg.h> 125 #include <dev/pci/pciide_natsemi_reg.h> 126 #include <dev/pci/pciide_nforce_reg.h> 127 #include <dev/pci/pciide_i31244_reg.h> 128 #include <dev/pci/pciide_ite_reg.h> 129 #include <dev/pci/pciide_ixp_reg.h> 130 #include <dev/pci/pciide_svwsata_reg.h> 131 #include <dev/pci/pciide_jmicron_reg.h> 132 #include <dev/pci/cy82c693var.h> 133 134 #ifdef __sparc64__ 135 #include <machine/autoconf.h> 136 #include <machine/openfirm.h> 137 #endif 138 139 /* functions for reading/writing 8-bit PCI registers */ 140 141 u_int8_t pciide_pci_read(pci_chipset_tag_t, pcitag_t, 142 int); 143 void pciide_pci_write(pci_chipset_tag_t, pcitag_t, 144 int, u_int8_t); 145 146 u_int8_t 147 pciide_pci_read(pci_chipset_tag_t pc, pcitag_t pa, int reg) 148 { 149 return (pci_conf_read(pc, pa, (reg & ~0x03)) >> 150 ((reg & 0x03) * 8) & 0xff); 151 } 152 153 void 154 pciide_pci_write(pci_chipset_tag_t pc, pcitag_t pa, int reg, u_int8_t val) 155 { 156 pcireg_t pcival; 157 158 pcival = pci_conf_read(pc, pa, (reg & ~0x03)); 159 pcival &= ~(0xff << ((reg & 0x03) * 8)); 160 pcival |= (val << ((reg & 0x03) * 8)); 161 pci_conf_write(pc, pa, (reg & ~0x03), pcival); 162 } 163 164 void default_chip_map(struct pciide_softc *, struct pci_attach_args *); 165 166 void sata_chip_map(struct pciide_softc *, struct pci_attach_args *); 167 void sata_setup_channel(struct channel_softc *); 168 169 void piix_chip_map(struct pciide_softc *, struct pci_attach_args *); 170 void piixsata_chip_map(struct pciide_softc *, struct pci_attach_args *); 171 void piix_setup_channel(struct channel_softc *); 172 void piix3_4_setup_channel(struct channel_softc *); 173 void piix_timing_debug(struct pciide_softc *); 174 175 u_int32_t piix_setup_idetim_timings(u_int8_t, u_int8_t, u_int8_t); 176 u_int32_t piix_setup_idetim_drvs(struct ata_drive_datas *); 177 u_int32_t piix_setup_sidetim_timings(u_int8_t, u_int8_t, u_int8_t); 178 179 void amd756_chip_map(struct pciide_softc *, struct pci_attach_args *); 180 void amd756_setup_channel(struct channel_softc *); 181 182 void apollo_chip_map(struct pciide_softc *, struct pci_attach_args *); 183 void apollo_setup_channel(struct channel_softc *); 184 185 void cmd_chip_map(struct pciide_softc *, struct pci_attach_args *); 186 void cmd0643_9_chip_map(struct pciide_softc *, struct pci_attach_args *); 187 void cmd0643_9_setup_channel(struct channel_softc *); 188 void cmd680_chip_map(struct pciide_softc *, struct pci_attach_args *); 189 void cmd680_setup_channel(struct channel_softc *); 190 void cmd680_channel_map(struct pci_attach_args *, struct pciide_softc *, int); 191 void cmd_channel_map(struct pci_attach_args *, 192 struct pciide_softc *, int); 193 int cmd_pci_intr(void *); 194 void cmd646_9_irqack(struct channel_softc *); 195 196 void sii_fixup_cacheline(struct pciide_softc *, struct pci_attach_args *); 197 void sii3112_chip_map(struct pciide_softc *, struct pci_attach_args *); 198 void sii3112_setup_channel(struct channel_softc *); 199 void sii3112_drv_probe(struct channel_softc *); 200 void sii3114_chip_map(struct pciide_softc *, struct pci_attach_args *); 201 void sii3114_mapreg_dma(struct pciide_softc *, struct pci_attach_args *); 202 int sii3114_chansetup(struct pciide_softc *, int); 203 void sii3114_mapchan(struct pciide_channel *); 204 u_int8_t sii3114_dmacmd_read(struct pciide_softc *, int); 205 void sii3114_dmacmd_write(struct pciide_softc *, int, u_int8_t); 206 u_int8_t sii3114_dmactl_read(struct pciide_softc *, int); 207 void sii3114_dmactl_write(struct pciide_softc *, int, u_int8_t); 208 void sii3114_dmatbl_write(struct pciide_softc *, int, u_int32_t); 209 210 void cy693_chip_map(struct pciide_softc *, struct pci_attach_args *); 211 void cy693_setup_channel(struct channel_softc *); 212 213 void sis_chip_map(struct pciide_softc *, struct pci_attach_args *); 214 void sis_setup_channel(struct channel_softc *); 215 void sis96x_setup_channel(struct channel_softc *); 216 int sis_hostbr_match(struct pci_attach_args *); 217 int sis_south_match(struct pci_attach_args *); 218 219 void natsemi_chip_map(struct pciide_softc *, struct pci_attach_args *); 220 void natsemi_setup_channel(struct channel_softc *); 221 int natsemi_pci_intr(void *); 222 void natsemi_irqack(struct channel_softc *); 223 void ns_scx200_chip_map(struct pciide_softc *, struct pci_attach_args *); 224 void ns_scx200_setup_channel(struct channel_softc *); 225 226 void acer_chip_map(struct pciide_softc *, struct pci_attach_args *); 227 void acer_setup_channel(struct channel_softc *); 228 int acer_pci_intr(void *); 229 230 void pdc202xx_chip_map(struct pciide_softc *, struct pci_attach_args *); 231 void pdc202xx_setup_channel(struct channel_softc *); 232 void pdc20268_setup_channel(struct channel_softc *); 233 int pdc202xx_pci_intr(void *); 234 int pdc20265_pci_intr(void *); 235 void pdc20262_dma_start(void *, int, int); 236 int pdc20262_dma_finish(void *, int, int, int); 237 238 u_int8_t pdc268_config_read(struct channel_softc *, int); 239 240 void pdcsata_chip_map(struct pciide_softc *, struct pci_attach_args *); 241 void pdc203xx_setup_channel(struct channel_softc *); 242 int pdc203xx_pci_intr(void *); 243 void pdc203xx_irqack(struct channel_softc *); 244 void pdc203xx_dma_start(void *,int ,int); 245 int pdc203xx_dma_finish(void *, int, int, int); 246 int pdc205xx_pci_intr(void *); 247 void pdc205xx_do_reset(struct channel_softc *); 248 void pdc205xx_drv_probe(struct channel_softc *); 249 250 void opti_chip_map(struct pciide_softc *, struct pci_attach_args *); 251 void opti_setup_channel(struct channel_softc *); 252 253 void hpt_chip_map(struct pciide_softc *, struct pci_attach_args *); 254 void hpt_setup_channel(struct channel_softc *); 255 int hpt_pci_intr(void *); 256 257 void acard_chip_map(struct pciide_softc *, struct pci_attach_args *); 258 void acard_setup_channel(struct channel_softc *); 259 260 void serverworks_chip_map(struct pciide_softc *, struct pci_attach_args *); 261 void serverworks_setup_channel(struct channel_softc *); 262 int serverworks_pci_intr(void *); 263 264 void svwsata_chip_map(struct pciide_softc *, struct pci_attach_args *); 265 void svwsata_mapreg_dma(struct pciide_softc *, struct pci_attach_args *); 266 void svwsata_mapchan(struct pciide_channel *); 267 u_int8_t svwsata_dmacmd_read(struct pciide_softc *, int); 268 void svwsata_dmacmd_write(struct pciide_softc *, int, u_int8_t); 269 u_int8_t svwsata_dmactl_read(struct pciide_softc *, int); 270 void svwsata_dmactl_write(struct pciide_softc *, int, u_int8_t); 271 void svwsata_dmatbl_write(struct pciide_softc *, int, u_int32_t); 272 void svwsata_drv_probe(struct channel_softc *); 273 274 void nforce_chip_map(struct pciide_softc *, struct pci_attach_args *); 275 void nforce_setup_channel(struct channel_softc *); 276 int nforce_pci_intr(void *); 277 278 void artisea_chip_map(struct pciide_softc *, struct pci_attach_args *); 279 280 void ite_chip_map(struct pciide_softc *, struct pci_attach_args *); 281 void ite_setup_channel(struct channel_softc *); 282 283 void ixp_chip_map(struct pciide_softc *, struct pci_attach_args *); 284 void ixp_setup_channel(struct channel_softc *); 285 286 void jmicron_chip_map(struct pciide_softc *, struct pci_attach_args *); 287 void jmicron_setup_channel(struct channel_softc *); 288 289 u_int8_t pciide_dmacmd_read(struct pciide_softc *, int); 290 void pciide_dmacmd_write(struct pciide_softc *, int, u_int8_t); 291 u_int8_t pciide_dmactl_read(struct pciide_softc *, int); 292 void pciide_dmactl_write(struct pciide_softc *, int, u_int8_t); 293 void pciide_dmatbl_write(struct pciide_softc *, int, u_int32_t); 294 295 void pciide_channel_dma_setup(struct pciide_channel *); 296 int pciide_dma_table_setup(struct pciide_softc *, int, int); 297 int pciide_dma_init(void *, int, int, void *, size_t, int); 298 void pciide_dma_start(void *, int, int); 299 int pciide_dma_finish(void *, int, int, int); 300 void pciide_irqack(struct channel_softc *); 301 void pciide_print_modes(struct pciide_channel *); 302 void pciide_print_channels(int, pcireg_t); 303 304 struct pciide_product_desc { 305 u_int32_t ide_product; 306 u_short ide_flags; 307 /* map and setup chip, probe drives */ 308 void (*chip_map)(struct pciide_softc *, struct pci_attach_args *); 309 }; 310 311 /* Flags for ide_flags */ 312 #define IDE_PCI_CLASS_OVERRIDE 0x0001 /* accept even if class != pciide */ 313 #define IDE_16BIT_IOSPACE 0x0002 /* I/O space BARS ignore upper word */ 314 315 /* Default product description for devices not known from this controller */ 316 const struct pciide_product_desc default_product_desc = { 317 0, /* Generic PCI IDE controller */ 318 0, 319 default_chip_map 320 }; 321 322 const struct pciide_product_desc pciide_intel_products[] = { 323 { PCI_PRODUCT_INTEL_31244, /* Intel 31244 SATA */ 324 0, 325 artisea_chip_map 326 }, 327 { PCI_PRODUCT_INTEL_82092AA, /* Intel 82092AA IDE */ 328 0, 329 default_chip_map 330 }, 331 { PCI_PRODUCT_INTEL_82371FB_IDE, /* Intel 82371FB IDE (PIIX) */ 332 0, 333 piix_chip_map 334 }, 335 { PCI_PRODUCT_INTEL_82371FB_ISA, /* Intel 82371FB IDE (PIIX) */ 336 0, 337 piix_chip_map 338 }, 339 { PCI_PRODUCT_INTEL_82372FB_IDE, /* Intel 82372FB IDE (PIIX4) */ 340 0, 341 piix_chip_map 342 }, 343 { PCI_PRODUCT_INTEL_82371SB_IDE, /* Intel 82371SB IDE (PIIX3) */ 344 0, 345 piix_chip_map 346 }, 347 { PCI_PRODUCT_INTEL_82371AB_IDE, /* Intel 82371AB IDE (PIIX4) */ 348 0, 349 piix_chip_map 350 }, 351 { PCI_PRODUCT_INTEL_82371MX, /* Intel 82371MX IDE */ 352 0, 353 piix_chip_map 354 }, 355 { PCI_PRODUCT_INTEL_82440MX_IDE, /* Intel 82440MX IDE */ 356 0, 357 piix_chip_map 358 }, 359 { PCI_PRODUCT_INTEL_82451NX, /* Intel 82451NX (PIIX4) IDE */ 360 0, 361 piix_chip_map 362 }, 363 { PCI_PRODUCT_INTEL_82801AA_IDE, /* Intel 82801AA IDE (ICH) */ 364 0, 365 piix_chip_map 366 }, 367 { PCI_PRODUCT_INTEL_82801AB_IDE, /* Intel 82801AB IDE (ICH0) */ 368 0, 369 piix_chip_map 370 }, 371 { PCI_PRODUCT_INTEL_82801BAM_IDE, /* Intel 82801BAM IDE (ICH2) */ 372 0, 373 piix_chip_map 374 }, 375 { PCI_PRODUCT_INTEL_82801BA_IDE, /* Intel 82801BA IDE (ICH2) */ 376 0, 377 piix_chip_map 378 }, 379 { PCI_PRODUCT_INTEL_82801CAM_IDE, /* Intel 82801CAM IDE (ICH3) */ 380 0, 381 piix_chip_map 382 }, 383 { PCI_PRODUCT_INTEL_82801CA_IDE, /* Intel 82801CA IDE (ICH3) */ 384 0, 385 piix_chip_map 386 }, 387 { PCI_PRODUCT_INTEL_82801DB_IDE, /* Intel 82801DB IDE (ICH4) */ 388 0, 389 piix_chip_map 390 }, 391 { PCI_PRODUCT_INTEL_82801DBL_IDE, /* Intel 82801DBL IDE (ICH4-L) */ 392 0, 393 piix_chip_map 394 }, 395 { PCI_PRODUCT_INTEL_82801DBM_IDE, /* Intel 82801DBM IDE (ICH4-M) */ 396 0, 397 piix_chip_map 398 }, 399 { PCI_PRODUCT_INTEL_82801EB_IDE, /* Intel 82801EB/ER (ICH5/5R) IDE */ 400 0, 401 piix_chip_map 402 }, 403 { PCI_PRODUCT_INTEL_82801EB_SATA, /* Intel 82801EB (ICH5) SATA */ 404 0, 405 piixsata_chip_map 406 }, 407 { PCI_PRODUCT_INTEL_82801ER_SATA, /* Intel 82801ER (ICH5R) SATA */ 408 0, 409 piixsata_chip_map 410 }, 411 { PCI_PRODUCT_INTEL_6300ESB_IDE, /* Intel 6300ESB IDE */ 412 0, 413 piix_chip_map 414 }, 415 { PCI_PRODUCT_INTEL_6300ESB_SATA, /* Intel 6300ESB SATA */ 416 0, 417 piixsata_chip_map 418 }, 419 { PCI_PRODUCT_INTEL_6300ESB_SATA2, /* Intel 6300ESB SATA */ 420 0, 421 piixsata_chip_map 422 }, 423 { PCI_PRODUCT_INTEL_6321ESB_IDE, /* Intel 6321ESB IDE */ 424 0, 425 piix_chip_map 426 }, 427 { PCI_PRODUCT_INTEL_82801FB_IDE, /* Intel 82801FB (ICH6) IDE */ 428 0, 429 piix_chip_map 430 }, 431 { PCI_PRODUCT_INTEL_82801FBM_SATA, /* Intel 82801FBM (ICH6M) SATA */ 432 0, 433 piixsata_chip_map 434 }, 435 { PCI_PRODUCT_INTEL_82801FB_SATA, /* Intel 82801FB (ICH6) SATA */ 436 0, 437 piixsata_chip_map 438 }, 439 { PCI_PRODUCT_INTEL_82801FR_SATA, /* Intel 82801FR (ICH6R) SATA */ 440 0, 441 piixsata_chip_map 442 }, 443 { PCI_PRODUCT_INTEL_82801GB_IDE, /* Intel 82801GB (ICH7) IDE */ 444 0, 445 piix_chip_map 446 }, 447 { PCI_PRODUCT_INTEL_82801GB_SATA, /* Intel 82801GB (ICH7) SATA */ 448 0, 449 piixsata_chip_map 450 }, 451 { PCI_PRODUCT_INTEL_82801GR_AHCI, /* Intel 82801GR (ICH7R) AHCI */ 452 0, 453 piixsata_chip_map 454 }, 455 { PCI_PRODUCT_INTEL_82801GR_RAID, /* Intel 82801GR (ICH7R) RAID */ 456 0, 457 piixsata_chip_map 458 }, 459 { PCI_PRODUCT_INTEL_82801GBM_SATA, /* Intel 82801GBM (ICH7M) SATA */ 460 0, 461 piixsata_chip_map 462 }, 463 { PCI_PRODUCT_INTEL_82801GBM_AHCI, /* Intel 82801GBM (ICH7M) AHCI */ 464 0, 465 piixsata_chip_map 466 }, 467 { PCI_PRODUCT_INTEL_82801GHM_RAID, /* Intel 82801GHM (ICH7M DH) RAID */ 468 0, 469 piixsata_chip_map 470 }, 471 { PCI_PRODUCT_INTEL_82801H_SATA_1, /* Intel 82801H (ICH8) SATA */ 472 0, 473 piixsata_chip_map 474 }, 475 { PCI_PRODUCT_INTEL_82801H_AHCI_6P, /* Intel 82801H (ICH8) AHCI */ 476 0, 477 piixsata_chip_map 478 }, 479 { PCI_PRODUCT_INTEL_82801H_RAID, /* Intel 82801H (ICH8) RAID */ 480 0, 481 piixsata_chip_map 482 }, 483 { PCI_PRODUCT_INTEL_82801H_AHCI_4P, /* Intel 82801H (ICH8) AHCI */ 484 0, 485 piixsata_chip_map 486 }, 487 { PCI_PRODUCT_INTEL_82801H_SATA_2, /* Intel 82801H (ICH8) SATA */ 488 0, 489 piixsata_chip_map 490 }, 491 { PCI_PRODUCT_INTEL_82801HBM_SATA, /* Intel 82801HBM (ICH8M) SATA */ 492 0, 493 piixsata_chip_map 494 }, 495 { PCI_PRODUCT_INTEL_82801HBM_AHCI, /* Intel 82801HBM (ICH8M) AHCI */ 496 0, 497 piixsata_chip_map 498 }, 499 { PCI_PRODUCT_INTEL_82801HBM_RAID, /* Intel 82801HBM (ICH8M) RAID */ 500 0, 501 piixsata_chip_map 502 }, 503 { PCI_PRODUCT_INTEL_82801HBM_IDE, /* Intel 82801HBM (ICH8M) IDE */ 504 0, 505 piix_chip_map 506 }, 507 { PCI_PRODUCT_INTEL_82801I_SATA_1, /* Intel 82801I (ICH9) SATA */ 508 0, 509 piixsata_chip_map 510 }, 511 { PCI_PRODUCT_INTEL_82801I_SATA_2, /* Intel 82801I (ICH9) SATA */ 512 0, 513 piixsata_chip_map 514 }, 515 { PCI_PRODUCT_INTEL_82801I_SATA_3, /* Intel 82801I (ICH9) SATA */ 516 0, 517 piixsata_chip_map 518 }, 519 { PCI_PRODUCT_INTEL_82801I_SATA_4, /* Intel 82801I (ICH9) SATA */ 520 0, 521 piixsata_chip_map 522 }, 523 { PCI_PRODUCT_INTEL_82801I_SATA_5, /* Intel 82801I (ICH9M) SATA */ 524 0, 525 piixsata_chip_map 526 }, 527 { PCI_PRODUCT_INTEL_82801I_SATA_6, /* Intel 82801I (ICH9M) SATA */ 528 0, 529 piixsata_chip_map 530 }, 531 { PCI_PRODUCT_INTEL_6321ESB_SATA, /* Intel 6321ESB SATA */ 532 0, 533 piixsata_chip_map 534 } 535 }; 536 537 const struct pciide_product_desc pciide_amd_products[] = { 538 { PCI_PRODUCT_AMD_PBC756_IDE, /* AMD 756 */ 539 0, 540 amd756_chip_map 541 }, 542 { PCI_PRODUCT_AMD_766_IDE, /* AMD 766 */ 543 0, 544 amd756_chip_map 545 }, 546 { PCI_PRODUCT_AMD_PBC768_IDE, 547 0, 548 amd756_chip_map 549 }, 550 { PCI_PRODUCT_AMD_8111_IDE, 551 0, 552 amd756_chip_map 553 }, 554 { PCI_PRODUCT_AMD_CS5536_IDE, 555 0, 556 amd756_chip_map 557 } 558 }; 559 560 #ifdef notyet 561 const struct pciide_product_desc pciide_opti_products[] = { 562 563 { PCI_PRODUCT_OPTI_82C621, 564 0, 565 opti_chip_map 566 }, 567 { PCI_PRODUCT_OPTI_82C568, 568 0, 569 opti_chip_map 570 }, 571 { PCI_PRODUCT_OPTI_82D568, 572 0, 573 opti_chip_map 574 } 575 }; 576 #endif 577 578 const struct pciide_product_desc pciide_cmd_products[] = { 579 { PCI_PRODUCT_CMDTECH_640, /* CMD Technology PCI0640 */ 580 0, 581 cmd_chip_map 582 }, 583 { PCI_PRODUCT_CMDTECH_643, /* CMD Technology PCI0643 */ 584 0, 585 cmd0643_9_chip_map 586 }, 587 { PCI_PRODUCT_CMDTECH_646, /* CMD Technology PCI0646 */ 588 0, 589 cmd0643_9_chip_map 590 }, 591 { PCI_PRODUCT_CMDTECH_648, /* CMD Technology PCI0648 */ 592 0, 593 cmd0643_9_chip_map 594 }, 595 { PCI_PRODUCT_CMDTECH_649, /* CMD Technology PCI0649 */ 596 0, 597 cmd0643_9_chip_map 598 }, 599 { PCI_PRODUCT_CMDTECH_680, /* CMD Technology PCI0680 */ 600 IDE_PCI_CLASS_OVERRIDE, 601 cmd680_chip_map 602 }, 603 { PCI_PRODUCT_CMDTECH_3112, /* SiI3112 SATA */ 604 0, 605 sii3112_chip_map 606 }, 607 { PCI_PRODUCT_CMDTECH_3512, /* SiI3512 SATA */ 608 0, 609 sii3112_chip_map 610 }, 611 { PCI_PRODUCT_CMDTECH_AAR_1210SA, /* Adaptec AAR-1210SA */ 612 0, 613 sii3112_chip_map 614 }, 615 { PCI_PRODUCT_CMDTECH_3114, /* SiI3114 SATA */ 616 0, 617 sii3114_chip_map 618 } 619 }; 620 621 const struct pciide_product_desc pciide_via_products[] = { 622 { PCI_PRODUCT_VIATECH_VT82C416, /* VIA VT82C416 IDE */ 623 0, 624 apollo_chip_map 625 }, 626 { PCI_PRODUCT_VIATECH_VT82C571, /* VIA VT82C571 IDE */ 627 0, 628 apollo_chip_map 629 }, 630 { PCI_PRODUCT_VIATECH_VT6410, /* VIA VT6410 IDE */ 631 IDE_PCI_CLASS_OVERRIDE, 632 apollo_chip_map 633 }, 634 { PCI_PRODUCT_VIATECH_CX700_IDE, /* VIA CX700 IDE */ 635 0, 636 apollo_chip_map 637 }, 638 { PCI_PRODUCT_VIATECH_VX700_IDE, /* VIA VX700 IDE */ 639 0, 640 apollo_chip_map 641 }, 642 { PCI_PRODUCT_VIATECH_VT6420_SATA, /* VIA VT6420 SATA */ 643 0, 644 sata_chip_map 645 }, 646 { PCI_PRODUCT_VIATECH_VT6421_SATA, /* VIA VT6421 SATA */ 647 0, 648 sata_chip_map 649 }, 650 { PCI_PRODUCT_VIATECH_VT8237A_SATA, /* VIA VT8237A SATA */ 651 0, 652 sata_chip_map 653 }, 654 { PCI_PRODUCT_VIATECH_VT8237A_SATA_2, /* VIA VT8237A SATA */ 655 0, 656 sata_chip_map 657 }, 658 { PCI_PRODUCT_VIATECH_VT8237S_SATA, /* VIA VT8237S SATA */ 659 0, 660 sata_chip_map 661 }, 662 { PCI_PRODUCT_VIATECH_VT8251_SATA, /* VIA VT8251 SATA */ 663 0, 664 sata_chip_map 665 } 666 }; 667 668 const struct pciide_product_desc pciide_cypress_products[] = { 669 { PCI_PRODUCT_CONTAQ_82C693, /* Contaq CY82C693 IDE */ 670 IDE_16BIT_IOSPACE, 671 cy693_chip_map 672 } 673 }; 674 675 const struct pciide_product_desc pciide_sis_products[] = { 676 { PCI_PRODUCT_SIS_5513, /* SIS 5513 EIDE */ 677 0, 678 sis_chip_map 679 }, 680 { PCI_PRODUCT_SIS_180, /* SIS 180 SATA */ 681 0, 682 sata_chip_map 683 }, 684 { PCI_PRODUCT_SIS_181, /* SIS 181 SATA */ 685 0, 686 sata_chip_map 687 }, 688 { PCI_PRODUCT_SIS_182, /* SIS 182 SATA */ 689 0, 690 sata_chip_map 691 } 692 }; 693 694 const struct pciide_product_desc pciide_natsemi_products[] = { 695 { PCI_PRODUCT_NS_PC87415, /* National Semi PC87415 IDE */ 696 0, 697 natsemi_chip_map 698 }, 699 { PCI_PRODUCT_NS_SCx200_IDE, /* National Semi SCx200 IDE */ 700 0, 701 ns_scx200_chip_map 702 } 703 }; 704 705 const struct pciide_product_desc pciide_acer_products[] = { 706 { PCI_PRODUCT_ALI_M5229, /* Acer Labs M5229 UDMA IDE */ 707 0, 708 acer_chip_map 709 } 710 }; 711 712 const struct pciide_product_desc pciide_triones_products[] = { 713 { PCI_PRODUCT_TRIONES_HPT366, /* Highpoint HPT36x/37x IDE */ 714 IDE_PCI_CLASS_OVERRIDE, 715 hpt_chip_map, 716 }, 717 { PCI_PRODUCT_TRIONES_HPT372A, /* Highpoint HPT372A IDE */ 718 IDE_PCI_CLASS_OVERRIDE, 719 hpt_chip_map 720 }, 721 { PCI_PRODUCT_TRIONES_HPT302, /* Highpoint HPT302 IDE */ 722 IDE_PCI_CLASS_OVERRIDE, 723 hpt_chip_map 724 }, 725 { PCI_PRODUCT_TRIONES_HPT371, /* Highpoint HPT371 IDE */ 726 IDE_PCI_CLASS_OVERRIDE, 727 hpt_chip_map 728 }, 729 { PCI_PRODUCT_TRIONES_HPT374, /* Highpoint HPT374 IDE */ 730 IDE_PCI_CLASS_OVERRIDE, 731 hpt_chip_map 732 } 733 }; 734 735 const struct pciide_product_desc pciide_promise_products[] = { 736 { PCI_PRODUCT_PROMISE_PDC20246, 737 IDE_PCI_CLASS_OVERRIDE, 738 pdc202xx_chip_map, 739 }, 740 { PCI_PRODUCT_PROMISE_PDC20262, 741 IDE_PCI_CLASS_OVERRIDE, 742 pdc202xx_chip_map, 743 }, 744 { PCI_PRODUCT_PROMISE_PDC20265, 745 IDE_PCI_CLASS_OVERRIDE, 746 pdc202xx_chip_map, 747 }, 748 { PCI_PRODUCT_PROMISE_PDC20267, 749 IDE_PCI_CLASS_OVERRIDE, 750 pdc202xx_chip_map, 751 }, 752 { PCI_PRODUCT_PROMISE_PDC20268, 753 IDE_PCI_CLASS_OVERRIDE, 754 pdc202xx_chip_map, 755 }, 756 { PCI_PRODUCT_PROMISE_PDC20268R, 757 IDE_PCI_CLASS_OVERRIDE, 758 pdc202xx_chip_map, 759 }, 760 { PCI_PRODUCT_PROMISE_PDC20269, 761 IDE_PCI_CLASS_OVERRIDE, 762 pdc202xx_chip_map, 763 }, 764 { PCI_PRODUCT_PROMISE_PDC20271, 765 IDE_PCI_CLASS_OVERRIDE, 766 pdc202xx_chip_map, 767 }, 768 { PCI_PRODUCT_PROMISE_PDC20275, 769 IDE_PCI_CLASS_OVERRIDE, 770 pdc202xx_chip_map, 771 }, 772 { PCI_PRODUCT_PROMISE_PDC20276, 773 IDE_PCI_CLASS_OVERRIDE, 774 pdc202xx_chip_map, 775 }, 776 { PCI_PRODUCT_PROMISE_PDC20277, 777 IDE_PCI_CLASS_OVERRIDE, 778 pdc202xx_chip_map, 779 }, 780 { PCI_PRODUCT_PROMISE_PDC20318, 781 IDE_PCI_CLASS_OVERRIDE, 782 pdcsata_chip_map, 783 }, 784 { PCI_PRODUCT_PROMISE_PDC20319, 785 IDE_PCI_CLASS_OVERRIDE, 786 pdcsata_chip_map, 787 }, 788 { PCI_PRODUCT_PROMISE_PDC20371, 789 IDE_PCI_CLASS_OVERRIDE, 790 pdcsata_chip_map, 791 }, 792 { PCI_PRODUCT_PROMISE_PDC20375, 793 IDE_PCI_CLASS_OVERRIDE, 794 pdcsata_chip_map, 795 }, 796 { PCI_PRODUCT_PROMISE_PDC20376, 797 IDE_PCI_CLASS_OVERRIDE, 798 pdcsata_chip_map, 799 }, 800 { PCI_PRODUCT_PROMISE_PDC20377, 801 IDE_PCI_CLASS_OVERRIDE, 802 pdcsata_chip_map, 803 }, 804 { PCI_PRODUCT_PROMISE_PDC20378, 805 IDE_PCI_CLASS_OVERRIDE, 806 pdcsata_chip_map, 807 }, 808 { PCI_PRODUCT_PROMISE_PDC20379, 809 IDE_PCI_CLASS_OVERRIDE, 810 pdcsata_chip_map, 811 }, 812 { PCI_PRODUCT_PROMISE_PDC40518, 813 IDE_PCI_CLASS_OVERRIDE, 814 pdcsata_chip_map, 815 }, 816 { PCI_PRODUCT_PROMISE_PDC40519, 817 IDE_PCI_CLASS_OVERRIDE, 818 pdcsata_chip_map, 819 }, 820 { PCI_PRODUCT_PROMISE_PDC40718, 821 IDE_PCI_CLASS_OVERRIDE, 822 pdcsata_chip_map, 823 }, 824 { PCI_PRODUCT_PROMISE_PDC40719, 825 IDE_PCI_CLASS_OVERRIDE, 826 pdcsata_chip_map, 827 }, 828 { PCI_PRODUCT_PROMISE_PDC40779, 829 IDE_PCI_CLASS_OVERRIDE, 830 pdcsata_chip_map, 831 }, 832 { PCI_PRODUCT_PROMISE_PDC20571, 833 IDE_PCI_CLASS_OVERRIDE, 834 pdcsata_chip_map, 835 }, 836 { PCI_PRODUCT_PROMISE_PDC20575, 837 IDE_PCI_CLASS_OVERRIDE, 838 pdcsata_chip_map, 839 }, 840 { PCI_PRODUCT_PROMISE_PDC20579, 841 IDE_PCI_CLASS_OVERRIDE, 842 pdcsata_chip_map, 843 }, 844 { PCI_PRODUCT_PROMISE_PDC20771, 845 IDE_PCI_CLASS_OVERRIDE, 846 pdcsata_chip_map, 847 }, 848 { PCI_PRODUCT_PROMISE_PDC20775, 849 IDE_PCI_CLASS_OVERRIDE, 850 pdcsata_chip_map, 851 } 852 }; 853 854 const struct pciide_product_desc pciide_acard_products[] = { 855 { PCI_PRODUCT_ACARD_ATP850U, /* Acard ATP850U Ultra33 Controller */ 856 IDE_PCI_CLASS_OVERRIDE, 857 acard_chip_map, 858 }, 859 { PCI_PRODUCT_ACARD_ATP860, /* Acard ATP860 Ultra66 Controller */ 860 IDE_PCI_CLASS_OVERRIDE, 861 acard_chip_map, 862 }, 863 { PCI_PRODUCT_ACARD_ATP860A, /* Acard ATP860-A Ultra66 Controller */ 864 IDE_PCI_CLASS_OVERRIDE, 865 acard_chip_map, 866 }, 867 { PCI_PRODUCT_ACARD_ATP865A, /* Acard ATP865-A Ultra133 Controller */ 868 IDE_PCI_CLASS_OVERRIDE, 869 acard_chip_map, 870 }, 871 { PCI_PRODUCT_ACARD_ATP865R, /* Acard ATP865-R Ultra133 Controller */ 872 IDE_PCI_CLASS_OVERRIDE, 873 acard_chip_map, 874 } 875 }; 876 877 const struct pciide_product_desc pciide_serverworks_products[] = { 878 { PCI_PRODUCT_RCC_OSB4_IDE, 879 0, 880 serverworks_chip_map, 881 }, 882 { PCI_PRODUCT_RCC_CSB5_IDE, 883 0, 884 serverworks_chip_map, 885 }, 886 { PCI_PRODUCT_RCC_CSB6_IDE, 887 0, 888 serverworks_chip_map, 889 }, 890 { PCI_PRODUCT_RCC_CSB6_RAID_IDE, 891 0, 892 serverworks_chip_map, 893 }, 894 { PCI_PRODUCT_RCC_HT_1000_IDE, 895 0, 896 serverworks_chip_map, 897 }, 898 { PCI_PRODUCT_RCC_K2_SATA, 899 0, 900 svwsata_chip_map, 901 }, 902 { PCI_PRODUCT_RCC_FRODO4_SATA, 903 0, 904 svwsata_chip_map, 905 }, 906 { PCI_PRODUCT_RCC_FRODO8_SATA, 907 0, 908 svwsata_chip_map, 909 }, 910 { PCI_PRODUCT_RCC_HT_1000_SATA_1, 911 0, 912 svwsata_chip_map, 913 }, 914 { PCI_PRODUCT_RCC_HT_1000_SATA_2, 915 0, 916 svwsata_chip_map, 917 } 918 }; 919 920 const struct pciide_product_desc pciide_nvidia_products[] = { 921 { PCI_PRODUCT_NVIDIA_NFORCE_IDE, 922 0, 923 nforce_chip_map 924 }, 925 { PCI_PRODUCT_NVIDIA_NFORCE2_IDE, 926 0, 927 nforce_chip_map 928 }, 929 { PCI_PRODUCT_NVIDIA_NFORCE2_400_IDE, 930 0, 931 nforce_chip_map 932 }, 933 { PCI_PRODUCT_NVIDIA_NFORCE3_IDE, 934 0, 935 nforce_chip_map 936 }, 937 { PCI_PRODUCT_NVIDIA_NFORCE3_250_IDE, 938 0, 939 nforce_chip_map 940 }, 941 { PCI_PRODUCT_NVIDIA_NFORCE4_ATA133, 942 0, 943 nforce_chip_map 944 }, 945 { PCI_PRODUCT_NVIDIA_MCP04_IDE, 946 0, 947 nforce_chip_map 948 }, 949 { PCI_PRODUCT_NVIDIA_MCP51_IDE, 950 0, 951 nforce_chip_map 952 }, 953 { PCI_PRODUCT_NVIDIA_MCP55_IDE, 954 0, 955 nforce_chip_map 956 }, 957 { PCI_PRODUCT_NVIDIA_MCP61_IDE, 958 0, 959 nforce_chip_map 960 }, 961 { PCI_PRODUCT_NVIDIA_MCP65_IDE, 962 0, 963 nforce_chip_map 964 }, 965 { PCI_PRODUCT_NVIDIA_MCP67_IDE, 966 0, 967 nforce_chip_map 968 }, 969 { PCI_PRODUCT_NVIDIA_MCP73_IDE, 970 0, 971 nforce_chip_map 972 }, 973 { PCI_PRODUCT_NVIDIA_MCP77_IDE, 974 0, 975 nforce_chip_map 976 }, 977 { PCI_PRODUCT_NVIDIA_NFORCE2_400_SATA, 978 0, 979 sata_chip_map 980 }, 981 { PCI_PRODUCT_NVIDIA_NFORCE3_250_SATA, 982 0, 983 sata_chip_map 984 }, 985 { PCI_PRODUCT_NVIDIA_NFORCE3_250_SATA2, 986 0, 987 sata_chip_map 988 }, 989 { PCI_PRODUCT_NVIDIA_NFORCE4_SATA1, 990 0, 991 sata_chip_map 992 }, 993 { PCI_PRODUCT_NVIDIA_NFORCE4_SATA2, 994 0, 995 sata_chip_map 996 }, 997 { PCI_PRODUCT_NVIDIA_MCP04_SATA, 998 0, 999 sata_chip_map 1000 }, 1001 { PCI_PRODUCT_NVIDIA_MCP04_SATA2, 1002 0, 1003 sata_chip_map 1004 }, 1005 { PCI_PRODUCT_NVIDIA_MCP51_SATA, 1006 0, 1007 sata_chip_map 1008 }, 1009 { PCI_PRODUCT_NVIDIA_MCP51_SATA2, 1010 0, 1011 sata_chip_map 1012 }, 1013 { PCI_PRODUCT_NVIDIA_MCP55_SATA, 1014 0, 1015 sata_chip_map 1016 }, 1017 { PCI_PRODUCT_NVIDIA_MCP55_SATA2, 1018 0, 1019 sata_chip_map 1020 }, 1021 { PCI_PRODUCT_NVIDIA_MCP61_SATA, 1022 0, 1023 sata_chip_map 1024 }, 1025 { PCI_PRODUCT_NVIDIA_MCP61_SATA2, 1026 0, 1027 sata_chip_map 1028 }, 1029 { PCI_PRODUCT_NVIDIA_MCP61_SATA3, 1030 0, 1031 sata_chip_map 1032 }, 1033 { PCI_PRODUCT_NVIDIA_MCP65_SATA, 1034 0, 1035 sata_chip_map 1036 }, 1037 { PCI_PRODUCT_NVIDIA_MCP65_SATA2, 1038 0, 1039 sata_chip_map 1040 }, 1041 { PCI_PRODUCT_NVIDIA_MCP65_SATA3, 1042 0, 1043 sata_chip_map 1044 }, 1045 { PCI_PRODUCT_NVIDIA_MCP65_SATA4, 1046 0, 1047 sata_chip_map 1048 }, 1049 { PCI_PRODUCT_NVIDIA_MCP67_SATA, 1050 0, 1051 sata_chip_map 1052 }, 1053 { PCI_PRODUCT_NVIDIA_MCP67_SATA2, 1054 0, 1055 sata_chip_map 1056 }, 1057 { PCI_PRODUCT_NVIDIA_MCP67_SATA3, 1058 0, 1059 sata_chip_map 1060 }, 1061 { PCI_PRODUCT_NVIDIA_MCP67_SATA4, 1062 0, 1063 sata_chip_map 1064 } 1065 }; 1066 1067 const struct pciide_product_desc pciide_ite_products[] = { 1068 { PCI_PRODUCT_ITEXPRESS_IT8211F, 1069 IDE_PCI_CLASS_OVERRIDE, 1070 ite_chip_map 1071 }, 1072 { PCI_PRODUCT_ITEXPRESS_IT8212F, 1073 IDE_PCI_CLASS_OVERRIDE, 1074 ite_chip_map 1075 } 1076 }; 1077 1078 const struct pciide_product_desc pciide_ati_products[] = { 1079 { PCI_PRODUCT_ATI_SB200_IDE, 1080 0, 1081 ixp_chip_map 1082 }, 1083 { PCI_PRODUCT_ATI_SB300_IDE, 1084 0, 1085 ixp_chip_map 1086 }, 1087 { PCI_PRODUCT_ATI_SB400_IDE, 1088 0, 1089 ixp_chip_map 1090 }, 1091 { PCI_PRODUCT_ATI_SB600_IDE, 1092 0, 1093 ixp_chip_map 1094 }, 1095 { PCI_PRODUCT_ATI_SB700_IDE, 1096 0, 1097 ixp_chip_map 1098 }, 1099 { PCI_PRODUCT_ATI_SB300_SATA, 1100 0, 1101 sii3112_chip_map 1102 }, 1103 { PCI_PRODUCT_ATI_SB400_SATA_1, 1104 0, 1105 sii3112_chip_map 1106 }, 1107 { PCI_PRODUCT_ATI_SB400_SATA_2, 1108 0, 1109 sii3112_chip_map 1110 } 1111 }; 1112 1113 const struct pciide_product_desc pciide_jmicron_products[] = { 1114 { PCI_PRODUCT_JMICRON_JMB361, 1115 0, 1116 jmicron_chip_map 1117 }, 1118 { PCI_PRODUCT_JMICRON_JMB363, 1119 0, 1120 jmicron_chip_map 1121 }, 1122 { PCI_PRODUCT_JMICRON_JMB365, 1123 0, 1124 jmicron_chip_map 1125 }, 1126 { PCI_PRODUCT_JMICRON_JMB366, 1127 0, 1128 jmicron_chip_map 1129 }, 1130 { PCI_PRODUCT_JMICRON_JMB368, 1131 0, 1132 jmicron_chip_map 1133 } 1134 }; 1135 1136 struct pciide_vendor_desc { 1137 u_int32_t ide_vendor; 1138 const struct pciide_product_desc *ide_products; 1139 int ide_nproducts; 1140 }; 1141 1142 const struct pciide_vendor_desc pciide_vendors[] = { 1143 { PCI_VENDOR_INTEL, pciide_intel_products, 1144 sizeof(pciide_intel_products)/sizeof(pciide_intel_products[0]) }, 1145 { PCI_VENDOR_AMD, pciide_amd_products, 1146 sizeof(pciide_amd_products)/sizeof(pciide_amd_products[0]) }, 1147 #ifdef notyet 1148 { PCI_VENDOR_OPTI, pciide_opti_products, 1149 sizeof(pciide_opti_products)/sizeof(pciide_opti_products[0]) }, 1150 #endif 1151 { PCI_VENDOR_CMDTECH, pciide_cmd_products, 1152 sizeof(pciide_cmd_products)/sizeof(pciide_cmd_products[0]) }, 1153 { PCI_VENDOR_VIATECH, pciide_via_products, 1154 sizeof(pciide_via_products)/sizeof(pciide_via_products[0]) }, 1155 { PCI_VENDOR_CONTAQ, pciide_cypress_products, 1156 sizeof(pciide_cypress_products)/sizeof(pciide_cypress_products[0]) }, 1157 { PCI_VENDOR_SIS, pciide_sis_products, 1158 sizeof(pciide_sis_products)/sizeof(pciide_sis_products[0]) }, 1159 { PCI_VENDOR_NS, pciide_natsemi_products, 1160 sizeof(pciide_natsemi_products)/sizeof(pciide_natsemi_products[0]) }, 1161 { PCI_VENDOR_ALI, pciide_acer_products, 1162 sizeof(pciide_acer_products)/sizeof(pciide_acer_products[0]) }, 1163 { PCI_VENDOR_TRIONES, pciide_triones_products, 1164 sizeof(pciide_triones_products)/sizeof(pciide_triones_products[0]) }, 1165 { PCI_VENDOR_ACARD, pciide_acard_products, 1166 sizeof(pciide_acard_products)/sizeof(pciide_acard_products[0]) }, 1167 { PCI_VENDOR_RCC, pciide_serverworks_products, 1168 sizeof(pciide_serverworks_products)/sizeof(pciide_serverworks_products[0]) }, 1169 { PCI_VENDOR_PROMISE, pciide_promise_products, 1170 sizeof(pciide_promise_products)/sizeof(pciide_promise_products[0]) }, 1171 { PCI_VENDOR_NVIDIA, pciide_nvidia_products, 1172 sizeof(pciide_nvidia_products)/sizeof(pciide_nvidia_products[0]) }, 1173 { PCI_VENDOR_ITEXPRESS, pciide_ite_products, 1174 sizeof(pciide_ite_products)/sizeof(pciide_ite_products[0]) }, 1175 { PCI_VENDOR_ATI, pciide_ati_products, 1176 sizeof(pciide_ati_products)/sizeof(pciide_ati_products[0]) }, 1177 { PCI_VENDOR_JMICRON, pciide_jmicron_products, 1178 sizeof(pciide_jmicron_products)/sizeof(pciide_jmicron_products[0]) } 1179 }; 1180 1181 /* options passed via the 'flags' config keyword */ 1182 #define PCIIDE_OPTIONS_DMA 0x01 1183 1184 int pciide_match(struct device *, void *, void *); 1185 void pciide_attach(struct device *, struct device *, void *); 1186 1187 struct cfattach pciide_pci_ca = { 1188 sizeof(struct pciide_softc), pciide_match, pciide_attach 1189 }; 1190 1191 struct cfattach pciide_jmb_ca = { 1192 sizeof(struct pciide_softc), pciide_match, pciide_attach 1193 }; 1194 1195 struct cfdriver pciide_cd = { 1196 NULL, "pciide", DV_DULL 1197 }; 1198 1199 int pciide_mapregs_compat( struct pci_attach_args *, 1200 struct pciide_channel *, int, bus_size_t *, bus_size_t *); 1201 int pciide_mapregs_native(struct pci_attach_args *, 1202 struct pciide_channel *, bus_size_t *, bus_size_t *, 1203 int (*pci_intr)(void *)); 1204 void pciide_mapreg_dma(struct pciide_softc *, 1205 struct pci_attach_args *); 1206 int pciide_chansetup(struct pciide_softc *, int, pcireg_t); 1207 void pciide_mapchan(struct pci_attach_args *, 1208 struct pciide_channel *, pcireg_t, bus_size_t *, bus_size_t *, 1209 int (*pci_intr)(void *)); 1210 int pciide_chan_candisable(struct pciide_channel *); 1211 void pciide_map_compat_intr( struct pci_attach_args *, 1212 struct pciide_channel *, int, int); 1213 void pciide_unmap_compat_intr( struct pci_attach_args *, 1214 struct pciide_channel *, int, int); 1215 int pciide_compat_intr(void *); 1216 int pciide_pci_intr(void *); 1217 int pciide_intr_flag(struct pciide_channel *); 1218 1219 const struct pciide_product_desc *pciide_lookup_product(u_int32_t); 1220 1221 const struct pciide_product_desc * 1222 pciide_lookup_product(u_int32_t id) 1223 { 1224 const struct pciide_product_desc *pp; 1225 const struct pciide_vendor_desc *vp; 1226 int i; 1227 1228 for (i = 0, vp = pciide_vendors; 1229 i < sizeof(pciide_vendors)/sizeof(pciide_vendors[0]); 1230 vp++, i++) 1231 if (PCI_VENDOR(id) == vp->ide_vendor) 1232 break; 1233 1234 if (i == sizeof(pciide_vendors)/sizeof(pciide_vendors[0])) 1235 return (NULL); 1236 1237 for (pp = vp->ide_products, i = 0; i < vp->ide_nproducts; pp++, i++) 1238 if (PCI_PRODUCT(id) == pp->ide_product) 1239 break; 1240 1241 if (i == vp->ide_nproducts) 1242 return (NULL); 1243 return (pp); 1244 } 1245 1246 int 1247 pciide_match(struct device *parent, void *match, void *aux) 1248 { 1249 struct pci_attach_args *pa = aux; 1250 const struct pciide_product_desc *pp; 1251 1252 /* 1253 * Some IDE controllers have severe bugs when used in PCI mode. 1254 * We punt and attach them to the ISA bus instead. 1255 */ 1256 if (PCI_VENDOR(pa->pa_id) == PCI_VENDOR_PCTECH && 1257 PCI_PRODUCT(pa->pa_id) == PCI_PRODUCT_PCTECH_RZ1000) 1258 return (0); 1259 1260 /* 1261 * Some controllers (e.g. promise Ultra-33) don't claim to be PCI IDE 1262 * controllers. Let see if we can deal with it anyway. 1263 */ 1264 pp = pciide_lookup_product(pa->pa_id); 1265 if (pp && (pp->ide_flags & IDE_PCI_CLASS_OVERRIDE)) 1266 return (1); 1267 1268 /* 1269 * Check the ID register to see that it's a PCI IDE controller. 1270 * If it is, we assume that we can deal with it; it _should_ 1271 * work in a standardized way... 1272 */ 1273 if (PCI_CLASS(pa->pa_class) == PCI_CLASS_MASS_STORAGE) { 1274 switch (PCI_SUBCLASS(pa->pa_class)) { 1275 case PCI_SUBCLASS_MASS_STORAGE_IDE: 1276 return (1); 1277 1278 /* 1279 * We only match these if we know they have 1280 * a match, as we may not support native interfaces 1281 * on them. 1282 */ 1283 case PCI_SUBCLASS_MASS_STORAGE_SATA: 1284 case PCI_SUBCLASS_MASS_STORAGE_RAID: 1285 case PCI_SUBCLASS_MASS_STORAGE_MISC: 1286 if (pp) 1287 return (1); 1288 else 1289 return (0); 1290 break; 1291 } 1292 } 1293 1294 return (0); 1295 } 1296 1297 void 1298 pciide_attach(struct device *parent, struct device *self, void *aux) 1299 { 1300 struct pciide_softc *sc = (struct pciide_softc *)self; 1301 struct pci_attach_args *pa = aux; 1302 1303 sc->sc_pp = pciide_lookup_product(pa->pa_id); 1304 if (sc->sc_pp == NULL) 1305 sc->sc_pp = &default_product_desc; 1306 sc->sc_rev = PCI_REVISION(pa->pa_class); 1307 1308 sc->sc_pc = pa->pa_pc; 1309 sc->sc_tag = pa->pa_tag; 1310 1311 /* Set up DMA defaults; these might be adjusted by chip_map. */ 1312 sc->sc_dma_maxsegsz = IDEDMA_BYTE_COUNT_MAX; 1313 sc->sc_dma_boundary = IDEDMA_BYTE_COUNT_ALIGN; 1314 1315 sc->sc_dmacmd_read = pciide_dmacmd_read; 1316 sc->sc_dmacmd_write = pciide_dmacmd_write; 1317 sc->sc_dmactl_read = pciide_dmactl_read; 1318 sc->sc_dmactl_write = pciide_dmactl_write; 1319 sc->sc_dmatbl_write = pciide_dmatbl_write; 1320 1321 WDCDEBUG_PRINT((" sc_pc=%p, sc_tag=%p, pa_class=0x%x\n", sc->sc_pc, 1322 sc->sc_tag, pa->pa_class), DEBUG_PROBE); 1323 1324 sc->sc_pp->chip_map(sc, pa); 1325 1326 WDCDEBUG_PRINT(("pciide: command/status register=0x%x\n", 1327 pci_conf_read(sc->sc_pc, sc->sc_tag, PCI_COMMAND_STATUS_REG)), 1328 DEBUG_PROBE); 1329 } 1330 1331 int 1332 pciide_mapregs_compat(struct pci_attach_args *pa, struct pciide_channel *cp, 1333 int compatchan, bus_size_t *cmdsizep, bus_size_t *ctlsizep) 1334 { 1335 struct pciide_softc *sc = (struct pciide_softc *)cp->wdc_channel.wdc; 1336 struct channel_softc *wdc_cp = &cp->wdc_channel; 1337 pcireg_t csr; 1338 1339 cp->compat = 1; 1340 *cmdsizep = PCIIDE_COMPAT_CMD_SIZE; 1341 *ctlsizep = PCIIDE_COMPAT_CTL_SIZE; 1342 1343 csr = pci_conf_read(sc->sc_pc, sc->sc_tag, PCI_COMMAND_STATUS_REG); 1344 pci_conf_write(sc->sc_pc, sc->sc_tag, PCI_COMMAND_STATUS_REG, 1345 csr | PCI_COMMAND_IO_ENABLE | PCI_COMMAND_MASTER_ENABLE); 1346 1347 wdc_cp->cmd_iot = pa->pa_iot; 1348 1349 if (bus_space_map(wdc_cp->cmd_iot, PCIIDE_COMPAT_CMD_BASE(compatchan), 1350 PCIIDE_COMPAT_CMD_SIZE, 0, &wdc_cp->cmd_ioh) != 0) { 1351 printf("%s: couldn't map %s cmd regs\n", 1352 sc->sc_wdcdev.sc_dev.dv_xname, cp->name); 1353 return (0); 1354 } 1355 1356 wdc_cp->ctl_iot = pa->pa_iot; 1357 1358 if (bus_space_map(wdc_cp->ctl_iot, PCIIDE_COMPAT_CTL_BASE(compatchan), 1359 PCIIDE_COMPAT_CTL_SIZE, 0, &wdc_cp->ctl_ioh) != 0) { 1360 printf("%s: couldn't map %s ctl regs\n", 1361 sc->sc_wdcdev.sc_dev.dv_xname, cp->name); 1362 bus_space_unmap(wdc_cp->cmd_iot, wdc_cp->cmd_ioh, 1363 PCIIDE_COMPAT_CMD_SIZE); 1364 return (0); 1365 } 1366 1367 return (1); 1368 } 1369 1370 int 1371 pciide_mapregs_native(struct pci_attach_args *pa, struct pciide_channel *cp, 1372 bus_size_t *cmdsizep, bus_size_t *ctlsizep, int (*pci_intr)(void *)) 1373 { 1374 struct pciide_softc *sc = (struct pciide_softc *)cp->wdc_channel.wdc; 1375 struct channel_softc *wdc_cp = &cp->wdc_channel; 1376 const char *intrstr; 1377 pci_intr_handle_t intrhandle; 1378 pcireg_t maptype; 1379 1380 cp->compat = 0; 1381 1382 if (sc->sc_pci_ih == NULL) { 1383 if (pci_intr_map(pa, &intrhandle) != 0) { 1384 printf("%s: couldn't map native-PCI interrupt\n", 1385 sc->sc_wdcdev.sc_dev.dv_xname); 1386 return (0); 1387 } 1388 intrstr = pci_intr_string(pa->pa_pc, intrhandle); 1389 sc->sc_pci_ih = pci_intr_establish(pa->pa_pc, 1390 intrhandle, IPL_BIO, pci_intr, sc, 1391 sc->sc_wdcdev.sc_dev.dv_xname); 1392 if (sc->sc_pci_ih != NULL) { 1393 printf("%s: using %s for native-PCI interrupt\n", 1394 sc->sc_wdcdev.sc_dev.dv_xname, 1395 intrstr ? intrstr : "unknown interrupt"); 1396 } else { 1397 printf("%s: couldn't establish native-PCI interrupt", 1398 sc->sc_wdcdev.sc_dev.dv_xname); 1399 if (intrstr != NULL) 1400 printf(" at %s", intrstr); 1401 printf("\n"); 1402 return (0); 1403 } 1404 } 1405 cp->ih = sc->sc_pci_ih; 1406 1407 maptype = pci_mapreg_type(pa->pa_pc, pa->pa_tag, 1408 PCIIDE_REG_CMD_BASE(wdc_cp->channel)); 1409 WDCDEBUG_PRINT(("%s: %s cmd regs mapping: %s\n", 1410 sc->sc_wdcdev.sc_dev.dv_xname, cp->name, 1411 (maptype == PCI_MAPREG_TYPE_IO ? "I/O" : "memory")), DEBUG_PROBE); 1412 if (pci_mapreg_map(pa, PCIIDE_REG_CMD_BASE(wdc_cp->channel), 1413 maptype, 0, 1414 &wdc_cp->cmd_iot, &wdc_cp->cmd_ioh, NULL, cmdsizep, 0) != 0) { 1415 printf("%s: couldn't map %s cmd regs\n", 1416 sc->sc_wdcdev.sc_dev.dv_xname, cp->name); 1417 return (0); 1418 } 1419 1420 maptype = pci_mapreg_type(pa->pa_pc, pa->pa_tag, 1421 PCIIDE_REG_CTL_BASE(wdc_cp->channel)); 1422 WDCDEBUG_PRINT(("%s: %s ctl regs mapping: %s\n", 1423 sc->sc_wdcdev.sc_dev.dv_xname, cp->name, 1424 (maptype == PCI_MAPREG_TYPE_IO ? "I/O": "memory")), DEBUG_PROBE); 1425 if (pci_mapreg_map(pa, PCIIDE_REG_CTL_BASE(wdc_cp->channel), 1426 maptype, 0, 1427 &wdc_cp->ctl_iot, &cp->ctl_baseioh, NULL, ctlsizep, 0) != 0) { 1428 printf("%s: couldn't map %s ctl regs\n", 1429 sc->sc_wdcdev.sc_dev.dv_xname, cp->name); 1430 bus_space_unmap(wdc_cp->cmd_iot, wdc_cp->cmd_ioh, *cmdsizep); 1431 return (0); 1432 } 1433 /* 1434 * In native mode, 4 bytes of I/O space are mapped for the control 1435 * register, the control register is at offset 2. Pass the generic 1436 * code a handle for only one byte at the right offset. 1437 */ 1438 if (bus_space_subregion(wdc_cp->ctl_iot, cp->ctl_baseioh, 2, 1, 1439 &wdc_cp->ctl_ioh) != 0) { 1440 printf("%s: unable to subregion %s ctl regs\n", 1441 sc->sc_wdcdev.sc_dev.dv_xname, cp->name); 1442 bus_space_unmap(wdc_cp->cmd_iot, wdc_cp->cmd_ioh, *cmdsizep); 1443 bus_space_unmap(wdc_cp->cmd_iot, cp->ctl_baseioh, *ctlsizep); 1444 return (0); 1445 } 1446 return (1); 1447 } 1448 1449 void 1450 pciide_mapreg_dma(struct pciide_softc *sc, struct pci_attach_args *pa) 1451 { 1452 pcireg_t maptype; 1453 bus_addr_t addr; 1454 1455 /* 1456 * Map DMA registers 1457 * 1458 * Note that sc_dma_ok is the right variable to test to see if 1459 * DMA can be done. If the interface doesn't support DMA, 1460 * sc_dma_ok will never be non-zero. If the DMA regs couldn't 1461 * be mapped, it'll be zero. I.e., sc_dma_ok will only be 1462 * non-zero if the interface supports DMA and the registers 1463 * could be mapped. 1464 * 1465 * XXX Note that despite the fact that the Bus Master IDE specs 1466 * XXX say that "The bus master IDE function uses 16 bytes of IO 1467 * XXX space", some controllers (at least the United 1468 * XXX Microelectronics UM8886BF) place it in memory space. 1469 */ 1470 1471 maptype = pci_mapreg_type(pa->pa_pc, pa->pa_tag, 1472 PCIIDE_REG_BUS_MASTER_DMA); 1473 1474 switch (maptype) { 1475 case PCI_MAPREG_TYPE_IO: 1476 sc->sc_dma_ok = (pci_mapreg_info(pa->pa_pc, pa->pa_tag, 1477 PCIIDE_REG_BUS_MASTER_DMA, PCI_MAPREG_TYPE_IO, 1478 &addr, NULL, NULL) == 0); 1479 if (sc->sc_dma_ok == 0) { 1480 printf(", unused (couldn't query registers)"); 1481 break; 1482 } 1483 if ((sc->sc_pp->ide_flags & IDE_16BIT_IOSPACE) 1484 && addr >= 0x10000) { 1485 sc->sc_dma_ok = 0; 1486 printf(", unused (registers at unsafe address %#lx)", addr); 1487 break; 1488 } 1489 /* FALLTHROUGH */ 1490 1491 case PCI_MAPREG_MEM_TYPE_32BIT: 1492 sc->sc_dma_ok = (pci_mapreg_map(pa, 1493 PCIIDE_REG_BUS_MASTER_DMA, maptype, 0, 1494 &sc->sc_dma_iot, &sc->sc_dma_ioh, NULL, NULL, 0) == 0); 1495 sc->sc_dmat = pa->pa_dmat; 1496 if (sc->sc_dma_ok == 0) { 1497 printf(", unused (couldn't map registers)"); 1498 } else { 1499 sc->sc_wdcdev.dma_arg = sc; 1500 sc->sc_wdcdev.dma_init = pciide_dma_init; 1501 sc->sc_wdcdev.dma_start = pciide_dma_start; 1502 sc->sc_wdcdev.dma_finish = pciide_dma_finish; 1503 } 1504 break; 1505 1506 default: 1507 sc->sc_dma_ok = 0; 1508 printf(", (unsupported maptype 0x%x)", maptype); 1509 break; 1510 } 1511 } 1512 1513 int 1514 pciide_intr_flag(struct pciide_channel *cp) 1515 { 1516 struct pciide_softc *sc = (struct pciide_softc *)cp->wdc_channel.wdc; 1517 int chan = cp->wdc_channel.channel; 1518 1519 if (cp->dma_in_progress) { 1520 int retry = 10; 1521 int status; 1522 1523 /* Check the status register */ 1524 for (retry = 10; retry > 0; retry--) { 1525 status = PCIIDE_DMACTL_READ(sc, chan); 1526 if (status & IDEDMA_CTL_INTR) { 1527 break; 1528 } 1529 DELAY(5); 1530 } 1531 1532 /* Not for us. */ 1533 if (retry == 0) 1534 return (0); 1535 1536 return (1); 1537 } 1538 1539 return (-1); 1540 } 1541 1542 int 1543 pciide_compat_intr(void *arg) 1544 { 1545 struct pciide_channel *cp = arg; 1546 1547 if (pciide_intr_flag(cp) == 0) 1548 return (0); 1549 1550 #ifdef DIAGNOSTIC 1551 /* should only be called for a compat channel */ 1552 if (cp->compat == 0) 1553 panic("pciide compat intr called for non-compat chan %p", cp); 1554 #endif 1555 return (wdcintr(&cp->wdc_channel)); 1556 } 1557 1558 int 1559 pciide_pci_intr(void *arg) 1560 { 1561 struct pciide_softc *sc = arg; 1562 struct pciide_channel *cp; 1563 struct channel_softc *wdc_cp; 1564 int i, rv, crv; 1565 1566 rv = 0; 1567 for (i = 0; i < sc->sc_wdcdev.nchannels; i++) { 1568 cp = &sc->pciide_channels[i]; 1569 wdc_cp = &cp->wdc_channel; 1570 1571 /* If a compat channel skip. */ 1572 if (cp->compat) 1573 continue; 1574 1575 if (pciide_intr_flag(cp) == 0) 1576 continue; 1577 1578 crv = wdcintr(wdc_cp); 1579 if (crv == 0) 1580 ; /* leave rv alone */ 1581 else if (crv == 1) 1582 rv = 1; /* claim the intr */ 1583 else if (rv == 0) /* crv should be -1 in this case */ 1584 rv = crv; /* if we've done no better, take it */ 1585 } 1586 return (rv); 1587 } 1588 1589 u_int8_t 1590 pciide_dmacmd_read(struct pciide_softc *sc, int chan) 1591 { 1592 return (bus_space_read_1(sc->sc_dma_iot, sc->sc_dma_ioh, 1593 IDEDMA_CMD(chan))); 1594 } 1595 1596 void 1597 pciide_dmacmd_write(struct pciide_softc *sc, int chan, u_int8_t val) 1598 { 1599 bus_space_write_1(sc->sc_dma_iot, sc->sc_dma_ioh, 1600 IDEDMA_CMD(chan), val); 1601 } 1602 1603 u_int8_t 1604 pciide_dmactl_read(struct pciide_softc *sc, int chan) 1605 { 1606 return (bus_space_read_1(sc->sc_dma_iot, sc->sc_dma_ioh, 1607 IDEDMA_CTL(chan))); 1608 } 1609 1610 void 1611 pciide_dmactl_write(struct pciide_softc *sc, int chan, u_int8_t val) 1612 { 1613 bus_space_write_1(sc->sc_dma_iot, sc->sc_dma_ioh, 1614 IDEDMA_CTL(chan), val); 1615 } 1616 1617 void 1618 pciide_dmatbl_write(struct pciide_softc *sc, int chan, u_int32_t val) 1619 { 1620 bus_space_write_4(sc->sc_dma_iot, sc->sc_dma_ioh, 1621 IDEDMA_TBL(chan), val); 1622 } 1623 1624 void 1625 pciide_channel_dma_setup(struct pciide_channel *cp) 1626 { 1627 int drive; 1628 struct pciide_softc *sc = (struct pciide_softc *)cp->wdc_channel.wdc; 1629 struct ata_drive_datas *drvp; 1630 1631 for (drive = 0; drive < 2; drive++) { 1632 drvp = &cp->wdc_channel.ch_drive[drive]; 1633 /* If no drive, skip */ 1634 if ((drvp->drive_flags & DRIVE) == 0) 1635 continue; 1636 /* setup DMA if needed */ 1637 if (((drvp->drive_flags & DRIVE_DMA) == 0 && 1638 (drvp->drive_flags & DRIVE_UDMA) == 0) || 1639 sc->sc_dma_ok == 0) { 1640 drvp->drive_flags &= ~(DRIVE_DMA | DRIVE_UDMA); 1641 continue; 1642 } 1643 if (pciide_dma_table_setup(sc, cp->wdc_channel.channel, drive) 1644 != 0) { 1645 /* Abort DMA setup */ 1646 drvp->drive_flags &= ~(DRIVE_DMA | DRIVE_UDMA); 1647 continue; 1648 } 1649 } 1650 } 1651 1652 int 1653 pciide_dma_table_setup(struct pciide_softc *sc, int channel, int drive) 1654 { 1655 bus_dma_segment_t seg; 1656 int error, rseg; 1657 const bus_size_t dma_table_size = 1658 sizeof(struct idedma_table) * NIDEDMA_TABLES; 1659 struct pciide_dma_maps *dma_maps = 1660 &sc->pciide_channels[channel].dma_maps[drive]; 1661 1662 /* If table was already allocated, just return */ 1663 if (dma_maps->dma_table) 1664 return (0); 1665 1666 /* Allocate memory for the DMA tables and map it */ 1667 if ((error = bus_dmamem_alloc(sc->sc_dmat, dma_table_size, 1668 IDEDMA_TBL_ALIGN, IDEDMA_TBL_ALIGN, &seg, 1, &rseg, 1669 BUS_DMA_NOWAIT)) != 0) { 1670 printf("%s:%d: unable to allocate table DMA for " 1671 "drive %d, error=%d\n", sc->sc_wdcdev.sc_dev.dv_xname, 1672 channel, drive, error); 1673 return (error); 1674 } 1675 1676 if ((error = bus_dmamem_map(sc->sc_dmat, &seg, rseg, 1677 dma_table_size, 1678 (caddr_t *)&dma_maps->dma_table, 1679 BUS_DMA_NOWAIT|BUS_DMA_COHERENT)) != 0) { 1680 printf("%s:%d: unable to map table DMA for" 1681 "drive %d, error=%d\n", sc->sc_wdcdev.sc_dev.dv_xname, 1682 channel, drive, error); 1683 return (error); 1684 } 1685 1686 WDCDEBUG_PRINT(("pciide_dma_table_setup: table at %p len %ld, " 1687 "phy 0x%lx\n", dma_maps->dma_table, dma_table_size, 1688 seg.ds_addr), DEBUG_PROBE); 1689 1690 /* Create and load table DMA map for this disk */ 1691 if ((error = bus_dmamap_create(sc->sc_dmat, dma_table_size, 1692 1, dma_table_size, IDEDMA_TBL_ALIGN, BUS_DMA_NOWAIT, 1693 &dma_maps->dmamap_table)) != 0) { 1694 printf("%s:%d: unable to create table DMA map for " 1695 "drive %d, error=%d\n", sc->sc_wdcdev.sc_dev.dv_xname, 1696 channel, drive, error); 1697 return (error); 1698 } 1699 if ((error = bus_dmamap_load(sc->sc_dmat, 1700 dma_maps->dmamap_table, 1701 dma_maps->dma_table, 1702 dma_table_size, NULL, BUS_DMA_NOWAIT)) != 0) { 1703 printf("%s:%d: unable to load table DMA map for " 1704 "drive %d, error=%d\n", sc->sc_wdcdev.sc_dev.dv_xname, 1705 channel, drive, error); 1706 return (error); 1707 } 1708 WDCDEBUG_PRINT(("pciide_dma_table_setup: phy addr of table 0x%lx\n", 1709 dma_maps->dmamap_table->dm_segs[0].ds_addr), DEBUG_PROBE); 1710 /* Create a xfer DMA map for this drive */ 1711 if ((error = bus_dmamap_create(sc->sc_dmat, IDEDMA_BYTE_COUNT_MAX, 1712 NIDEDMA_TABLES, sc->sc_dma_maxsegsz, sc->sc_dma_boundary, 1713 BUS_DMA_NOWAIT | BUS_DMA_ALLOCNOW, 1714 &dma_maps->dmamap_xfer)) != 0) { 1715 printf("%s:%d: unable to create xfer DMA map for " 1716 "drive %d, error=%d\n", sc->sc_wdcdev.sc_dev.dv_xname, 1717 channel, drive, error); 1718 return (error); 1719 } 1720 return (0); 1721 } 1722 1723 int 1724 pciide_dma_init(void *v, int channel, int drive, void *databuf, 1725 size_t datalen, int flags) 1726 { 1727 struct pciide_softc *sc = v; 1728 int error, seg; 1729 struct pciide_channel *cp = &sc->pciide_channels[channel]; 1730 struct pciide_dma_maps *dma_maps = 1731 &sc->pciide_channels[channel].dma_maps[drive]; 1732 #ifndef BUS_DMA_RAW 1733 #define BUS_DMA_RAW 0 1734 #endif 1735 1736 error = bus_dmamap_load(sc->sc_dmat, 1737 dma_maps->dmamap_xfer, 1738 databuf, datalen, NULL, BUS_DMA_NOWAIT|BUS_DMA_RAW); 1739 if (error) { 1740 printf("%s:%d: unable to load xfer DMA map for " 1741 "drive %d, error=%d\n", sc->sc_wdcdev.sc_dev.dv_xname, 1742 channel, drive, error); 1743 return (error); 1744 } 1745 1746 bus_dmamap_sync(sc->sc_dmat, dma_maps->dmamap_xfer, 0, 1747 dma_maps->dmamap_xfer->dm_mapsize, 1748 (flags & WDC_DMA_READ) ? 1749 BUS_DMASYNC_PREREAD : BUS_DMASYNC_PREWRITE); 1750 1751 for (seg = 0; seg < dma_maps->dmamap_xfer->dm_nsegs; seg++) { 1752 #ifdef DIAGNOSTIC 1753 /* A segment must not cross a 64k boundary */ 1754 { 1755 u_long phys = dma_maps->dmamap_xfer->dm_segs[seg].ds_addr; 1756 u_long len = dma_maps->dmamap_xfer->dm_segs[seg].ds_len; 1757 if ((phys & ~IDEDMA_BYTE_COUNT_MASK) != 1758 ((phys + len - 1) & ~IDEDMA_BYTE_COUNT_MASK)) { 1759 printf("pciide_dma: segment %d physical addr 0x%lx" 1760 " len 0x%lx not properly aligned\n", 1761 seg, phys, len); 1762 panic("pciide_dma: buf align"); 1763 } 1764 } 1765 #endif 1766 dma_maps->dma_table[seg].base_addr = 1767 htole32(dma_maps->dmamap_xfer->dm_segs[seg].ds_addr); 1768 dma_maps->dma_table[seg].byte_count = 1769 htole32(dma_maps->dmamap_xfer->dm_segs[seg].ds_len & 1770 IDEDMA_BYTE_COUNT_MASK); 1771 WDCDEBUG_PRINT(("\t seg %d len %d addr 0x%x\n", 1772 seg, letoh32(dma_maps->dma_table[seg].byte_count), 1773 letoh32(dma_maps->dma_table[seg].base_addr)), DEBUG_DMA); 1774 1775 } 1776 dma_maps->dma_table[dma_maps->dmamap_xfer->dm_nsegs -1].byte_count |= 1777 htole32(IDEDMA_BYTE_COUNT_EOT); 1778 1779 bus_dmamap_sync(sc->sc_dmat, dma_maps->dmamap_table, 0, 1780 dma_maps->dmamap_table->dm_mapsize, 1781 BUS_DMASYNC_PREWRITE); 1782 1783 /* Maps are ready. Start DMA function */ 1784 #ifdef DIAGNOSTIC 1785 if (dma_maps->dmamap_table->dm_segs[0].ds_addr & ~IDEDMA_TBL_MASK) { 1786 printf("pciide_dma_init: addr 0x%lx not properly aligned\n", 1787 dma_maps->dmamap_table->dm_segs[0].ds_addr); 1788 panic("pciide_dma_init: table align"); 1789 } 1790 #endif 1791 1792 /* Clear status bits */ 1793 PCIIDE_DMACTL_WRITE(sc, channel, PCIIDE_DMACTL_READ(sc, channel)); 1794 /* Write table addr */ 1795 PCIIDE_DMATBL_WRITE(sc, channel, 1796 dma_maps->dmamap_table->dm_segs[0].ds_addr); 1797 /* set read/write */ 1798 PCIIDE_DMACMD_WRITE(sc, channel, 1799 ((flags & WDC_DMA_READ) ? IDEDMA_CMD_WRITE : 0) | cp->idedma_cmd); 1800 /* remember flags */ 1801 dma_maps->dma_flags = flags; 1802 return (0); 1803 } 1804 1805 void 1806 pciide_dma_start(void *v, int channel, int drive) 1807 { 1808 struct pciide_softc *sc = v; 1809 1810 WDCDEBUG_PRINT(("pciide_dma_start\n"), DEBUG_XFERS); 1811 PCIIDE_DMACMD_WRITE(sc, channel, PCIIDE_DMACMD_READ(sc, channel) | 1812 IDEDMA_CMD_START); 1813 1814 sc->pciide_channels[channel].dma_in_progress = 1; 1815 } 1816 1817 int 1818 pciide_dma_finish(void *v, int channel, int drive, int force) 1819 { 1820 struct pciide_softc *sc = v; 1821 struct pciide_channel *cp = &sc->pciide_channels[channel]; 1822 u_int8_t status; 1823 int error = 0; 1824 struct pciide_dma_maps *dma_maps = 1825 &sc->pciide_channels[channel].dma_maps[drive]; 1826 1827 status = PCIIDE_DMACTL_READ(sc, channel); 1828 WDCDEBUG_PRINT(("pciide_dma_finish: status 0x%x\n", status), 1829 DEBUG_XFERS); 1830 1831 if (force == 0 && (status & IDEDMA_CTL_INTR) == 0) { 1832 error = WDC_DMAST_NOIRQ; 1833 goto done; 1834 } 1835 1836 /* stop DMA channel */ 1837 PCIIDE_DMACMD_WRITE(sc, channel, 1838 ((dma_maps->dma_flags & WDC_DMA_READ) ? 1839 0x00 : IDEDMA_CMD_WRITE) | cp->idedma_cmd); 1840 1841 /* Unload the map of the data buffer */ 1842 bus_dmamap_sync(sc->sc_dmat, dma_maps->dmamap_xfer, 0, 1843 dma_maps->dmamap_xfer->dm_mapsize, 1844 (dma_maps->dma_flags & WDC_DMA_READ) ? 1845 BUS_DMASYNC_POSTREAD : BUS_DMASYNC_POSTWRITE); 1846 bus_dmamap_unload(sc->sc_dmat, dma_maps->dmamap_xfer); 1847 1848 /* Clear status bits */ 1849 PCIIDE_DMACTL_WRITE(sc, channel, status); 1850 1851 if ((status & IDEDMA_CTL_ERR) != 0) { 1852 printf("%s:%d:%d: bus-master DMA error: status=0x%x\n", 1853 sc->sc_wdcdev.sc_dev.dv_xname, channel, drive, status); 1854 error |= WDC_DMAST_ERR; 1855 } 1856 1857 if ((status & IDEDMA_CTL_INTR) == 0) { 1858 printf("%s:%d:%d: bus-master DMA error: missing interrupt, " 1859 "status=0x%x\n", sc->sc_wdcdev.sc_dev.dv_xname, channel, 1860 drive, status); 1861 error |= WDC_DMAST_NOIRQ; 1862 } 1863 1864 if ((status & IDEDMA_CTL_ACT) != 0) { 1865 /* data underrun, may be a valid condition for ATAPI */ 1866 error |= WDC_DMAST_UNDER; 1867 } 1868 1869 done: 1870 sc->pciide_channels[channel].dma_in_progress = 0; 1871 return (error); 1872 } 1873 1874 void 1875 pciide_irqack(struct channel_softc *chp) 1876 { 1877 struct pciide_channel *cp = (struct pciide_channel *)chp; 1878 struct pciide_softc *sc = (struct pciide_softc *)cp->wdc_channel.wdc; 1879 int chan = chp->channel; 1880 1881 /* clear status bits in IDE DMA registers */ 1882 PCIIDE_DMACTL_WRITE(sc, chan, PCIIDE_DMACTL_READ(sc, chan)); 1883 } 1884 1885 /* some common code used by several chip_map */ 1886 int 1887 pciide_chansetup(struct pciide_softc *sc, int channel, pcireg_t interface) 1888 { 1889 struct pciide_channel *cp = &sc->pciide_channels[channel]; 1890 sc->wdc_chanarray[channel] = &cp->wdc_channel; 1891 cp->name = PCIIDE_CHANNEL_NAME(channel); 1892 cp->wdc_channel.channel = channel; 1893 cp->wdc_channel.wdc = &sc->sc_wdcdev; 1894 cp->wdc_channel.ch_queue = 1895 malloc(sizeof(struct channel_queue), M_DEVBUF, M_NOWAIT); 1896 if (cp->wdc_channel.ch_queue == NULL) { 1897 printf("%s: %s " 1898 "cannot allocate memory for command queue", 1899 sc->sc_wdcdev.sc_dev.dv_xname, cp->name); 1900 return (0); 1901 } 1902 cp->hw_ok = 1; 1903 1904 return (1); 1905 } 1906 1907 /* some common code used by several chip channel_map */ 1908 void 1909 pciide_mapchan(struct pci_attach_args *pa, struct pciide_channel *cp, 1910 pcireg_t interface, bus_size_t *cmdsizep, bus_size_t *ctlsizep, 1911 int (*pci_intr)(void *)) 1912 { 1913 struct channel_softc *wdc_cp = &cp->wdc_channel; 1914 1915 if (interface & PCIIDE_INTERFACE_PCI(wdc_cp->channel)) 1916 cp->hw_ok = pciide_mapregs_native(pa, cp, cmdsizep, ctlsizep, 1917 pci_intr); 1918 else 1919 cp->hw_ok = pciide_mapregs_compat(pa, cp, 1920 wdc_cp->channel, cmdsizep, ctlsizep); 1921 if (cp->hw_ok == 0) 1922 return; 1923 wdc_cp->data32iot = wdc_cp->cmd_iot; 1924 wdc_cp->data32ioh = wdc_cp->cmd_ioh; 1925 wdcattach(wdc_cp); 1926 } 1927 1928 /* 1929 * Generic code to call to know if a channel can be disabled. Return 1 1930 * if channel can be disabled, 0 if not 1931 */ 1932 int 1933 pciide_chan_candisable(struct pciide_channel *cp) 1934 { 1935 struct pciide_softc *sc = (struct pciide_softc *)cp->wdc_channel.wdc; 1936 struct channel_softc *wdc_cp = &cp->wdc_channel; 1937 1938 if ((wdc_cp->ch_drive[0].drive_flags & DRIVE) == 0 && 1939 (wdc_cp->ch_drive[1].drive_flags & DRIVE) == 0) { 1940 printf("%s: %s disabled (no drives)\n", 1941 sc->sc_wdcdev.sc_dev.dv_xname, cp->name); 1942 cp->hw_ok = 0; 1943 return (1); 1944 } 1945 return (0); 1946 } 1947 1948 /* 1949 * generic code to map the compat intr if hw_ok=1 and it is a compat channel. 1950 * Set hw_ok=0 on failure 1951 */ 1952 void 1953 pciide_map_compat_intr(struct pci_attach_args *pa, struct pciide_channel *cp, 1954 int compatchan, int interface) 1955 { 1956 struct pciide_softc *sc = (struct pciide_softc *)cp->wdc_channel.wdc; 1957 struct channel_softc *wdc_cp = &cp->wdc_channel; 1958 1959 if ((interface & PCIIDE_INTERFACE_PCI(wdc_cp->channel)) != 0) 1960 return; 1961 1962 cp->compat = 1; 1963 cp->ih = pciide_machdep_compat_intr_establish(&sc->sc_wdcdev.sc_dev, 1964 pa, compatchan, pciide_compat_intr, cp); 1965 if (cp->ih == NULL) { 1966 printf("%s: no compatibility interrupt for use by %s\n", 1967 sc->sc_wdcdev.sc_dev.dv_xname, cp->name); 1968 cp->hw_ok = 0; 1969 } 1970 } 1971 1972 /* 1973 * generic code to unmap the compat intr if hw_ok=1 and it is a compat channel. 1974 * Set hw_ok=0 on failure 1975 */ 1976 void 1977 pciide_unmap_compat_intr(struct pci_attach_args *pa, struct pciide_channel *cp, 1978 int compatchan, int interface) 1979 { 1980 struct channel_softc *wdc_cp = &cp->wdc_channel; 1981 1982 if ((interface & PCIIDE_INTERFACE_PCI(wdc_cp->channel)) != 0) 1983 return; 1984 1985 pciide_machdep_compat_intr_disestablish(pa->pa_pc, cp->ih); 1986 } 1987 1988 void 1989 pciide_print_channels(int nchannels, pcireg_t interface) 1990 { 1991 int i; 1992 1993 for (i = 0; i < nchannels; i++) { 1994 printf(", %s %s to %s", PCIIDE_CHANNEL_NAME(i), 1995 (interface & PCIIDE_INTERFACE_SETTABLE(i)) ? 1996 "configured" : "wired", 1997 (interface & PCIIDE_INTERFACE_PCI(i)) ? "native-PCI" : 1998 "compatibility"); 1999 } 2000 2001 printf("\n"); 2002 } 2003 2004 void 2005 pciide_print_modes(struct pciide_channel *cp) 2006 { 2007 wdc_print_current_modes(&cp->wdc_channel); 2008 } 2009 2010 void 2011 default_chip_map(struct pciide_softc *sc, struct pci_attach_args *pa) 2012 { 2013 struct pciide_channel *cp; 2014 pcireg_t interface = PCI_INTERFACE(pa->pa_class); 2015 pcireg_t csr; 2016 int channel, drive; 2017 struct ata_drive_datas *drvp; 2018 u_int8_t idedma_ctl; 2019 bus_size_t cmdsize, ctlsize; 2020 char *failreason; 2021 2022 if (interface & PCIIDE_INTERFACE_BUS_MASTER_DMA) { 2023 printf(": DMA"); 2024 if (sc->sc_pp == &default_product_desc && 2025 (sc->sc_wdcdev.sc_dev.dv_cfdata->cf_flags & 2026 PCIIDE_OPTIONS_DMA) == 0) { 2027 printf(" (unsupported)"); 2028 sc->sc_dma_ok = 0; 2029 } else { 2030 pciide_mapreg_dma(sc, pa); 2031 if (sc->sc_dma_ok != 0) 2032 printf(", (partial support)"); 2033 } 2034 } else { 2035 printf(": no DMA"); 2036 sc->sc_dma_ok = 0; 2037 } 2038 if (sc->sc_dma_ok) { 2039 sc->sc_wdcdev.cap |= WDC_CAPABILITY_DMA | WDC_CAPABILITY_IRQACK; 2040 sc->sc_wdcdev.irqack = pciide_irqack; 2041 } 2042 sc->sc_wdcdev.PIO_cap = 0; 2043 sc->sc_wdcdev.DMA_cap = 0; 2044 sc->sc_wdcdev.channels = sc->wdc_chanarray; 2045 sc->sc_wdcdev.nchannels = PCIIDE_NUM_CHANNELS; 2046 sc->sc_wdcdev.cap |= WDC_CAPABILITY_DATA16; 2047 2048 pciide_print_channels(sc->sc_wdcdev.nchannels, interface); 2049 2050 for (channel = 0; channel < sc->sc_wdcdev.nchannels; channel++) { 2051 cp = &sc->pciide_channels[channel]; 2052 if (pciide_chansetup(sc, channel, interface) == 0) 2053 continue; 2054 if (interface & PCIIDE_INTERFACE_PCI(channel)) { 2055 cp->hw_ok = pciide_mapregs_native(pa, cp, &cmdsize, 2056 &ctlsize, pciide_pci_intr); 2057 } else { 2058 cp->hw_ok = pciide_mapregs_compat(pa, cp, 2059 channel, &cmdsize, &ctlsize); 2060 } 2061 if (cp->hw_ok == 0) 2062 continue; 2063 /* 2064 * Check to see if something appears to be there. 2065 */ 2066 failreason = NULL; 2067 pciide_map_compat_intr(pa, cp, channel, interface); 2068 if (cp->hw_ok == 0) 2069 continue; 2070 if (!wdcprobe(&cp->wdc_channel)) { 2071 failreason = "not responding; disabled or no drives?"; 2072 goto next; 2073 } 2074 /* 2075 * Now, make sure it's actually attributable to this PCI IDE 2076 * channel by trying to access the channel again while the 2077 * PCI IDE controller's I/O space is disabled. (If the 2078 * channel no longer appears to be there, it belongs to 2079 * this controller.) YUCK! 2080 */ 2081 csr = pci_conf_read(sc->sc_pc, sc->sc_tag, 2082 PCI_COMMAND_STATUS_REG); 2083 pci_conf_write(sc->sc_pc, sc->sc_tag, PCI_COMMAND_STATUS_REG, 2084 csr & ~PCI_COMMAND_IO_ENABLE); 2085 if (wdcprobe(&cp->wdc_channel)) 2086 failreason = "other hardware responding at addresses"; 2087 pci_conf_write(sc->sc_pc, sc->sc_tag, 2088 PCI_COMMAND_STATUS_REG, csr); 2089 next: 2090 if (failreason) { 2091 printf("%s: %s ignored (%s)\n", 2092 sc->sc_wdcdev.sc_dev.dv_xname, cp->name, 2093 failreason); 2094 cp->hw_ok = 0; 2095 pciide_unmap_compat_intr(pa, cp, channel, interface); 2096 bus_space_unmap(cp->wdc_channel.cmd_iot, 2097 cp->wdc_channel.cmd_ioh, cmdsize); 2098 if (interface & PCIIDE_INTERFACE_PCI(channel)) 2099 bus_space_unmap(cp->wdc_channel.ctl_iot, 2100 cp->ctl_baseioh, ctlsize); 2101 else 2102 bus_space_unmap(cp->wdc_channel.ctl_iot, 2103 cp->wdc_channel.ctl_ioh, ctlsize); 2104 } 2105 if (cp->hw_ok) { 2106 cp->wdc_channel.data32iot = cp->wdc_channel.cmd_iot; 2107 cp->wdc_channel.data32ioh = cp->wdc_channel.cmd_ioh; 2108 wdcattach(&cp->wdc_channel); 2109 } 2110 } 2111 2112 if (sc->sc_dma_ok == 0) 2113 return; 2114 2115 /* Allocate DMA maps */ 2116 for (channel = 0; channel < sc->sc_wdcdev.nchannels; channel++) { 2117 idedma_ctl = 0; 2118 cp = &sc->pciide_channels[channel]; 2119 for (drive = 0; drive < 2; drive++) { 2120 drvp = &cp->wdc_channel.ch_drive[drive]; 2121 /* If no drive, skip */ 2122 if ((drvp->drive_flags & DRIVE) == 0) 2123 continue; 2124 if ((drvp->drive_flags & DRIVE_DMA) == 0) 2125 continue; 2126 if (pciide_dma_table_setup(sc, channel, drive) != 0) { 2127 /* Abort DMA setup */ 2128 printf("%s:%d:%d: cannot allocate DMA maps, " 2129 "using PIO transfers\n", 2130 sc->sc_wdcdev.sc_dev.dv_xname, 2131 channel, drive); 2132 drvp->drive_flags &= ~DRIVE_DMA; 2133 } 2134 printf("%s:%d:%d: using DMA data transfers\n", 2135 sc->sc_wdcdev.sc_dev.dv_xname, 2136 channel, drive); 2137 idedma_ctl |= IDEDMA_CTL_DRV_DMA(drive); 2138 } 2139 if (idedma_ctl != 0) { 2140 /* Add software bits in status register */ 2141 PCIIDE_DMACTL_WRITE(sc, channel, idedma_ctl); 2142 } 2143 } 2144 } 2145 2146 void 2147 sata_chip_map(struct pciide_softc *sc, struct pci_attach_args *pa) 2148 { 2149 struct pciide_channel *cp; 2150 pcireg_t interface = PCI_INTERFACE(pa->pa_class); 2151 int channel; 2152 bus_size_t cmdsize, ctlsize; 2153 2154 if (interface == 0) { 2155 WDCDEBUG_PRINT(("sata_chip_map interface == 0\n"), 2156 DEBUG_PROBE); 2157 interface = PCIIDE_INTERFACE_BUS_MASTER_DMA | 2158 PCIIDE_INTERFACE_PCI(0) | PCIIDE_INTERFACE_PCI(1); 2159 } 2160 2161 printf(": DMA"); 2162 pciide_mapreg_dma(sc, pa); 2163 printf("\n"); 2164 2165 if (sc->sc_dma_ok) { 2166 sc->sc_wdcdev.cap |= WDC_CAPABILITY_UDMA | 2167 WDC_CAPABILITY_DMA | WDC_CAPABILITY_IRQACK; 2168 sc->sc_wdcdev.irqack = pciide_irqack; 2169 } 2170 sc->sc_wdcdev.PIO_cap = 4; 2171 sc->sc_wdcdev.DMA_cap = 2; 2172 sc->sc_wdcdev.UDMA_cap = 6; 2173 2174 sc->sc_wdcdev.channels = sc->wdc_chanarray; 2175 sc->sc_wdcdev.nchannels = PCIIDE_NUM_CHANNELS; 2176 sc->sc_wdcdev.cap |= WDC_CAPABILITY_DATA16 | WDC_CAPABILITY_DATA32 | 2177 WDC_CAPABILITY_MODE | WDC_CAPABILITY_SATA; 2178 sc->sc_wdcdev.set_modes = sata_setup_channel; 2179 2180 for (channel = 0; channel < sc->sc_wdcdev.nchannels; channel++) { 2181 cp = &sc->pciide_channels[channel]; 2182 if (pciide_chansetup(sc, channel, interface) == 0) 2183 continue; 2184 pciide_mapchan(pa, cp, interface, &cmdsize, &ctlsize, 2185 pciide_pci_intr); 2186 sata_setup_channel(&cp->wdc_channel); 2187 } 2188 } 2189 2190 void 2191 sata_setup_channel(struct channel_softc *chp) 2192 { 2193 struct ata_drive_datas *drvp; 2194 int drive; 2195 u_int32_t idedma_ctl; 2196 struct pciide_channel *cp = (struct pciide_channel *)chp; 2197 struct pciide_softc *sc = (struct pciide_softc *)cp->wdc_channel.wdc; 2198 2199 /* setup DMA if needed */ 2200 pciide_channel_dma_setup(cp); 2201 2202 idedma_ctl = 0; 2203 2204 for (drive = 0; drive < 2; drive++) { 2205 drvp = &chp->ch_drive[drive]; 2206 /* If no drive, skip */ 2207 if ((drvp->drive_flags & DRIVE) == 0) 2208 continue; 2209 if (drvp->drive_flags & DRIVE_UDMA) { 2210 /* use Ultra/DMA */ 2211 drvp->drive_flags &= ~DRIVE_DMA; 2212 idedma_ctl |= IDEDMA_CTL_DRV_DMA(drive); 2213 } else if (drvp->drive_flags & DRIVE_DMA) { 2214 idedma_ctl |= IDEDMA_CTL_DRV_DMA(drive); 2215 } 2216 } 2217 2218 /* 2219 * Nothing to do to setup modes; it is meaningless in S-ATA 2220 * (but many S-ATA drives still want to get the SET_FEATURE 2221 * command). 2222 */ 2223 if (idedma_ctl != 0) { 2224 /* Add software bits in status register */ 2225 PCIIDE_DMACTL_WRITE(sc, chp->channel, idedma_ctl); 2226 } 2227 pciide_print_modes(cp); 2228 } 2229 2230 void 2231 piix_timing_debug(struct pciide_softc *sc) 2232 { 2233 WDCDEBUG_PRINT(("piix_setup_chip: idetim=0x%x", 2234 pci_conf_read(sc->sc_pc, sc->sc_tag, PIIX_IDETIM)), 2235 DEBUG_PROBE); 2236 if (sc->sc_pp->ide_product != PCI_PRODUCT_INTEL_82371FB_IDE && 2237 sc->sc_pp->ide_product != PCI_PRODUCT_INTEL_82371FB_ISA) { 2238 WDCDEBUG_PRINT((", sidetim=0x%x", 2239 pci_conf_read(sc->sc_pc, sc->sc_tag, PIIX_SIDETIM)), 2240 DEBUG_PROBE); 2241 if (sc->sc_wdcdev.cap & WDC_CAPABILITY_UDMA) { 2242 WDCDEBUG_PRINT((", udmareg 0x%x", 2243 pci_conf_read(sc->sc_pc, sc->sc_tag, PIIX_UDMAREG)), 2244 DEBUG_PROBE); 2245 } 2246 if (sc->sc_pp->ide_product == PCI_PRODUCT_INTEL_6300ESB_IDE || 2247 sc->sc_pp->ide_product == PCI_PRODUCT_INTEL_6321ESB_IDE || 2248 sc->sc_pp->ide_product == PCI_PRODUCT_INTEL_82801AA_IDE || 2249 sc->sc_pp->ide_product == PCI_PRODUCT_INTEL_82801AB_IDE || 2250 sc->sc_pp->ide_product == PCI_PRODUCT_INTEL_82801BAM_IDE || 2251 sc->sc_pp->ide_product == PCI_PRODUCT_INTEL_82801BA_IDE || 2252 sc->sc_pp->ide_product == PCI_PRODUCT_INTEL_82801CAM_IDE || 2253 sc->sc_pp->ide_product == PCI_PRODUCT_INTEL_82801CA_IDE || 2254 sc->sc_pp->ide_product == PCI_PRODUCT_INTEL_82801DB_IDE || 2255 sc->sc_pp->ide_product == PCI_PRODUCT_INTEL_82801DBL_IDE || 2256 sc->sc_pp->ide_product == PCI_PRODUCT_INTEL_82801DBM_IDE || 2257 sc->sc_pp->ide_product == PCI_PRODUCT_INTEL_82801EB_IDE || 2258 sc->sc_pp->ide_product == PCI_PRODUCT_INTEL_82801FB_IDE || 2259 sc->sc_pp->ide_product == PCI_PRODUCT_INTEL_82801GB_IDE || 2260 sc->sc_pp->ide_product == PCI_PRODUCT_INTEL_82801HBM_IDE || 2261 sc->sc_pp->ide_product == PCI_PRODUCT_INTEL_82372FB_IDE) { 2262 WDCDEBUG_PRINT((", IDE_CONTROL 0x%x", 2263 pci_conf_read(sc->sc_pc, sc->sc_tag, PIIX_CONFIG)), 2264 DEBUG_PROBE); 2265 } 2266 } 2267 WDCDEBUG_PRINT(("\n"), DEBUG_PROBE); 2268 } 2269 2270 void 2271 piix_chip_map(struct pciide_softc *sc, struct pci_attach_args *pa) 2272 { 2273 struct pciide_channel *cp; 2274 int channel; 2275 u_int32_t idetim; 2276 bus_size_t cmdsize, ctlsize; 2277 2278 pcireg_t interface = PCI_INTERFACE(pa->pa_class); 2279 2280 printf(": DMA"); 2281 pciide_mapreg_dma(sc, pa); 2282 sc->sc_wdcdev.cap |= WDC_CAPABILITY_DATA16 | WDC_CAPABILITY_DATA32 | 2283 WDC_CAPABILITY_MODE; 2284 if (sc->sc_dma_ok) { 2285 sc->sc_wdcdev.cap |= WDC_CAPABILITY_DMA | WDC_CAPABILITY_IRQACK; 2286 sc->sc_wdcdev.irqack = pciide_irqack; 2287 switch (sc->sc_pp->ide_product) { 2288 case PCI_PRODUCT_INTEL_6300ESB_IDE: 2289 case PCI_PRODUCT_INTEL_6321ESB_IDE: 2290 case PCI_PRODUCT_INTEL_82371AB_IDE: 2291 case PCI_PRODUCT_INTEL_82372FB_IDE: 2292 case PCI_PRODUCT_INTEL_82440MX_IDE: 2293 case PCI_PRODUCT_INTEL_82451NX: 2294 case PCI_PRODUCT_INTEL_82801AA_IDE: 2295 case PCI_PRODUCT_INTEL_82801AB_IDE: 2296 case PCI_PRODUCT_INTEL_82801BAM_IDE: 2297 case PCI_PRODUCT_INTEL_82801BA_IDE: 2298 case PCI_PRODUCT_INTEL_82801CAM_IDE: 2299 case PCI_PRODUCT_INTEL_82801CA_IDE: 2300 case PCI_PRODUCT_INTEL_82801DB_IDE: 2301 case PCI_PRODUCT_INTEL_82801DBL_IDE: 2302 case PCI_PRODUCT_INTEL_82801DBM_IDE: 2303 case PCI_PRODUCT_INTEL_82801EB_IDE: 2304 case PCI_PRODUCT_INTEL_82801FB_IDE: 2305 case PCI_PRODUCT_INTEL_82801GB_IDE: 2306 case PCI_PRODUCT_INTEL_82801HBM_IDE: 2307 sc->sc_wdcdev.cap |= WDC_CAPABILITY_UDMA; 2308 break; 2309 } 2310 } 2311 sc->sc_wdcdev.PIO_cap = 4; 2312 sc->sc_wdcdev.DMA_cap = 2; 2313 switch (sc->sc_pp->ide_product) { 2314 case PCI_PRODUCT_INTEL_82801AA_IDE: 2315 case PCI_PRODUCT_INTEL_82372FB_IDE: 2316 sc->sc_wdcdev.UDMA_cap = 4; 2317 break; 2318 case PCI_PRODUCT_INTEL_6300ESB_IDE: 2319 case PCI_PRODUCT_INTEL_6321ESB_IDE: 2320 case PCI_PRODUCT_INTEL_82801BAM_IDE: 2321 case PCI_PRODUCT_INTEL_82801BA_IDE: 2322 case PCI_PRODUCT_INTEL_82801CAM_IDE: 2323 case PCI_PRODUCT_INTEL_82801CA_IDE: 2324 case PCI_PRODUCT_INTEL_82801DB_IDE: 2325 case PCI_PRODUCT_INTEL_82801DBL_IDE: 2326 case PCI_PRODUCT_INTEL_82801DBM_IDE: 2327 case PCI_PRODUCT_INTEL_82801EB_IDE: 2328 case PCI_PRODUCT_INTEL_82801FB_IDE: 2329 case PCI_PRODUCT_INTEL_82801GB_IDE: 2330 case PCI_PRODUCT_INTEL_82801HBM_IDE: 2331 sc->sc_wdcdev.UDMA_cap = 5; 2332 break; 2333 default: 2334 sc->sc_wdcdev.UDMA_cap = 2; 2335 break; 2336 } 2337 2338 if (sc->sc_pp->ide_product == PCI_PRODUCT_INTEL_82371FB_IDE || 2339 sc->sc_pp->ide_product == PCI_PRODUCT_INTEL_82371FB_ISA) { 2340 sc->sc_wdcdev.set_modes = piix_setup_channel; 2341 } else { 2342 sc->sc_wdcdev.set_modes = piix3_4_setup_channel; 2343 } 2344 sc->sc_wdcdev.channels = sc->wdc_chanarray; 2345 sc->sc_wdcdev.nchannels = PCIIDE_NUM_CHANNELS; 2346 2347 pciide_print_channels(sc->sc_wdcdev.nchannels, interface); 2348 2349 piix_timing_debug(sc); 2350 2351 for (channel = 0; channel < sc->sc_wdcdev.nchannels; channel++) { 2352 cp = &sc->pciide_channels[channel]; 2353 2354 /* PIIX is compat-only */ 2355 if (pciide_chansetup(sc, channel, 0) == 0) 2356 continue; 2357 idetim = pci_conf_read(sc->sc_pc, sc->sc_tag, PIIX_IDETIM); 2358 if ((PIIX_IDETIM_READ(idetim, channel) & 2359 PIIX_IDETIM_IDE) == 0) { 2360 printf("%s: %s ignored (disabled)\n", 2361 sc->sc_wdcdev.sc_dev.dv_xname, cp->name); 2362 continue; 2363 } 2364 /* PIIX are compat-only pciide devices */ 2365 pciide_map_compat_intr(pa, cp, channel, 0); 2366 if (cp->hw_ok == 0) 2367 continue; 2368 pciide_mapchan(pa, cp, 0, &cmdsize, &ctlsize, pciide_pci_intr); 2369 if (cp->hw_ok == 0) 2370 goto next; 2371 if (pciide_chan_candisable(cp)) { 2372 idetim = PIIX_IDETIM_CLEAR(idetim, PIIX_IDETIM_IDE, 2373 channel); 2374 pci_conf_write(sc->sc_pc, sc->sc_tag, PIIX_IDETIM, 2375 idetim); 2376 } 2377 if (cp->hw_ok == 0) 2378 goto next; 2379 sc->sc_wdcdev.set_modes(&cp->wdc_channel); 2380 next: 2381 if (cp->hw_ok == 0) 2382 pciide_unmap_compat_intr(pa, cp, channel, 0); 2383 } 2384 2385 piix_timing_debug(sc); 2386 } 2387 2388 void 2389 piixsata_chip_map(struct pciide_softc *sc, struct pci_attach_args *pa) 2390 { 2391 struct pciide_channel *cp; 2392 pcireg_t interface = PCI_INTERFACE(pa->pa_class); 2393 int channel; 2394 bus_size_t cmdsize, ctlsize; 2395 u_int8_t reg, ich = 0; 2396 2397 printf(": DMA"); 2398 pciide_mapreg_dma(sc, pa); 2399 2400 if (sc->sc_dma_ok) { 2401 sc->sc_wdcdev.cap |= WDC_CAPABILITY_UDMA | 2402 WDC_CAPABILITY_DMA | WDC_CAPABILITY_IRQACK; 2403 sc->sc_wdcdev.irqack = pciide_irqack; 2404 sc->sc_wdcdev.DMA_cap = 2; 2405 sc->sc_wdcdev.UDMA_cap = 6; 2406 } 2407 sc->sc_wdcdev.PIO_cap = 4; 2408 2409 sc->sc_wdcdev.channels = sc->wdc_chanarray; 2410 sc->sc_wdcdev.nchannels = PCIIDE_NUM_CHANNELS; 2411 sc->sc_wdcdev.cap |= WDC_CAPABILITY_DATA16 | WDC_CAPABILITY_DATA32 | 2412 WDC_CAPABILITY_MODE | WDC_CAPABILITY_SATA; 2413 sc->sc_wdcdev.set_modes = sata_setup_channel; 2414 2415 switch(sc->sc_pp->ide_product) { 2416 case PCI_PRODUCT_INTEL_6300ESB_SATA: 2417 case PCI_PRODUCT_INTEL_6300ESB_SATA2: 2418 case PCI_PRODUCT_INTEL_82801EB_SATA: 2419 case PCI_PRODUCT_INTEL_82801ER_SATA: 2420 ich = 5; 2421 break; 2422 case PCI_PRODUCT_INTEL_82801FB_SATA: 2423 case PCI_PRODUCT_INTEL_82801FR_SATA: 2424 case PCI_PRODUCT_INTEL_82801FBM_SATA: 2425 ich = 6; 2426 break; 2427 default: 2428 ich = 7; 2429 break; 2430 } 2431 2432 /* 2433 * Put the SATA portion of controllers that don't operate in combined 2434 * mode into native PCI modes so the maximum number of devices can be 2435 * used. Intel calls this "enhanced mode" 2436 */ 2437 if (ich == 5) { 2438 reg = pciide_pci_read(sc->sc_pc, sc->sc_tag, ICH5_SATA_MAP); 2439 if ((reg & ICH5_SATA_MAP_COMBINED) == 0) { 2440 reg = pciide_pci_read(pa->pa_pc, pa->pa_tag, 2441 ICH5_SATA_PI); 2442 reg |= ICH5_SATA_PI_PRI_NATIVE | 2443 ICH5_SATA_PI_SEC_NATIVE; 2444 pciide_pci_write(pa->pa_pc, pa->pa_tag, 2445 ICH5_SATA_PI, reg); 2446 interface |= PCIIDE_INTERFACE_PCI(0) | 2447 PCIIDE_INTERFACE_PCI(1); 2448 } 2449 } else { 2450 reg = pciide_pci_read(sc->sc_pc, sc->sc_tag, ICH5_SATA_MAP) & 2451 ICH6_SATA_MAP_CMB_MASK; 2452 if (reg != ICH6_SATA_MAP_CMB_PRI && 2453 reg != ICH6_SATA_MAP_CMB_SEC) { 2454 reg = pciide_pci_read(pa->pa_pc, pa->pa_tag, 2455 ICH5_SATA_PI); 2456 reg |= ICH5_SATA_PI_PRI_NATIVE | 2457 ICH5_SATA_PI_SEC_NATIVE; 2458 2459 pciide_pci_write(pa->pa_pc, pa->pa_tag, 2460 ICH5_SATA_PI, reg); 2461 interface |= PCIIDE_INTERFACE_PCI(0) | 2462 PCIIDE_INTERFACE_PCI(1); 2463 2464 /* 2465 * Ask for SATA IDE Mode, we don't need to do this 2466 * for the combined mode case as combined mode is 2467 * only allowed in IDE Mode 2468 */ 2469 if (ich >= 7) { 2470 reg = pciide_pci_read(sc->sc_pc, sc->sc_tag, 2471 ICH5_SATA_MAP) & ~ICH7_SATA_MAP_SMS_MASK; 2472 pciide_pci_write(pa->pa_pc, pa->pa_tag, 2473 ICH5_SATA_MAP, reg); 2474 } 2475 } 2476 } 2477 2478 pciide_print_channels(sc->sc_wdcdev.nchannels, interface); 2479 2480 for (channel = 0; channel < sc->sc_wdcdev.nchannels; channel++) { 2481 cp = &sc->pciide_channels[channel]; 2482 if (pciide_chansetup(sc, channel, interface) == 0) 2483 continue; 2484 2485 pciide_map_compat_intr(pa, cp, channel, interface); 2486 if (cp->hw_ok == 0) 2487 continue; 2488 2489 pciide_mapchan(pa, cp, interface, &cmdsize, &ctlsize, 2490 pciide_pci_intr); 2491 if (cp->hw_ok != 0) 2492 sc->sc_wdcdev.set_modes(&cp->wdc_channel); 2493 2494 if (cp->hw_ok == 0) 2495 pciide_unmap_compat_intr(pa, cp, channel, interface); 2496 } 2497 } 2498 2499 void 2500 piix_setup_channel(struct channel_softc *chp) 2501 { 2502 u_int8_t mode[2], drive; 2503 u_int32_t oidetim, idetim, idedma_ctl; 2504 struct pciide_channel *cp = (struct pciide_channel *)chp; 2505 struct pciide_softc *sc = (struct pciide_softc *)cp->wdc_channel.wdc; 2506 struct ata_drive_datas *drvp = cp->wdc_channel.ch_drive; 2507 2508 oidetim = pci_conf_read(sc->sc_pc, sc->sc_tag, PIIX_IDETIM); 2509 idetim = PIIX_IDETIM_CLEAR(oidetim, 0xffff, chp->channel); 2510 idedma_ctl = 0; 2511 2512 /* set up new idetim: Enable IDE registers decode */ 2513 idetim = PIIX_IDETIM_SET(idetim, PIIX_IDETIM_IDE, 2514 chp->channel); 2515 2516 /* setup DMA */ 2517 pciide_channel_dma_setup(cp); 2518 2519 /* 2520 * Here we have to mess up with drives mode: PIIX can't have 2521 * different timings for master and slave drives. 2522 * We need to find the best combination. 2523 */ 2524 2525 /* If both drives supports DMA, take the lower mode */ 2526 if ((drvp[0].drive_flags & DRIVE_DMA) && 2527 (drvp[1].drive_flags & DRIVE_DMA)) { 2528 mode[0] = mode[1] = 2529 min(drvp[0].DMA_mode, drvp[1].DMA_mode); 2530 drvp[0].DMA_mode = mode[0]; 2531 drvp[1].DMA_mode = mode[1]; 2532 goto ok; 2533 } 2534 /* 2535 * If only one drive supports DMA, use its mode, and 2536 * put the other one in PIO mode 0 if mode not compatible 2537 */ 2538 if (drvp[0].drive_flags & DRIVE_DMA) { 2539 mode[0] = drvp[0].DMA_mode; 2540 mode[1] = drvp[1].PIO_mode; 2541 if (piix_isp_pio[mode[1]] != piix_isp_dma[mode[0]] || 2542 piix_rtc_pio[mode[1]] != piix_rtc_dma[mode[0]]) 2543 mode[1] = drvp[1].PIO_mode = 0; 2544 goto ok; 2545 } 2546 if (drvp[1].drive_flags & DRIVE_DMA) { 2547 mode[1] = drvp[1].DMA_mode; 2548 mode[0] = drvp[0].PIO_mode; 2549 if (piix_isp_pio[mode[0]] != piix_isp_dma[mode[1]] || 2550 piix_rtc_pio[mode[0]] != piix_rtc_dma[mode[1]]) 2551 mode[0] = drvp[0].PIO_mode = 0; 2552 goto ok; 2553 } 2554 /* 2555 * If both drives are not DMA, takes the lower mode, unless 2556 * one of them is PIO mode < 2 2557 */ 2558 if (drvp[0].PIO_mode < 2) { 2559 mode[0] = drvp[0].PIO_mode = 0; 2560 mode[1] = drvp[1].PIO_mode; 2561 } else if (drvp[1].PIO_mode < 2) { 2562 mode[1] = drvp[1].PIO_mode = 0; 2563 mode[0] = drvp[0].PIO_mode; 2564 } else { 2565 mode[0] = mode[1] = 2566 min(drvp[1].PIO_mode, drvp[0].PIO_mode); 2567 drvp[0].PIO_mode = mode[0]; 2568 drvp[1].PIO_mode = mode[1]; 2569 } 2570 ok: /* The modes are setup */ 2571 for (drive = 0; drive < 2; drive++) { 2572 if (drvp[drive].drive_flags & DRIVE_DMA) { 2573 idetim |= piix_setup_idetim_timings( 2574 mode[drive], 1, chp->channel); 2575 goto end; 2576 } 2577 } 2578 /* If we are there, none of the drives are DMA */ 2579 if (mode[0] >= 2) 2580 idetim |= piix_setup_idetim_timings( 2581 mode[0], 0, chp->channel); 2582 else 2583 idetim |= piix_setup_idetim_timings( 2584 mode[1], 0, chp->channel); 2585 end: /* 2586 * timing mode is now set up in the controller. Enable 2587 * it per-drive 2588 */ 2589 for (drive = 0; drive < 2; drive++) { 2590 /* If no drive, skip */ 2591 if ((drvp[drive].drive_flags & DRIVE) == 0) 2592 continue; 2593 idetim |= piix_setup_idetim_drvs(&drvp[drive]); 2594 if (drvp[drive].drive_flags & DRIVE_DMA) 2595 idedma_ctl |= IDEDMA_CTL_DRV_DMA(drive); 2596 } 2597 if (idedma_ctl != 0) { 2598 /* Add software bits in status register */ 2599 bus_space_write_1(sc->sc_dma_iot, sc->sc_dma_ioh, 2600 IDEDMA_CTL(chp->channel), 2601 idedma_ctl); 2602 } 2603 pci_conf_write(sc->sc_pc, sc->sc_tag, PIIX_IDETIM, idetim); 2604 pciide_print_modes(cp); 2605 } 2606 2607 void 2608 piix3_4_setup_channel(struct channel_softc *chp) 2609 { 2610 struct ata_drive_datas *drvp; 2611 u_int32_t oidetim, idetim, sidetim, udmareg, ideconf, idedma_ctl; 2612 struct pciide_channel *cp = (struct pciide_channel *)chp; 2613 struct pciide_softc *sc = (struct pciide_softc *)cp->wdc_channel.wdc; 2614 int drive; 2615 int channel = chp->channel; 2616 2617 oidetim = pci_conf_read(sc->sc_pc, sc->sc_tag, PIIX_IDETIM); 2618 sidetim = pci_conf_read(sc->sc_pc, sc->sc_tag, PIIX_SIDETIM); 2619 udmareg = pci_conf_read(sc->sc_pc, sc->sc_tag, PIIX_UDMAREG); 2620 ideconf = pci_conf_read(sc->sc_pc, sc->sc_tag, PIIX_CONFIG); 2621 idetim = PIIX_IDETIM_CLEAR(oidetim, 0xffff, channel); 2622 sidetim &= ~(PIIX_SIDETIM_ISP_MASK(channel) | 2623 PIIX_SIDETIM_RTC_MASK(channel)); 2624 2625 idedma_ctl = 0; 2626 /* If channel disabled, no need to go further */ 2627 if ((PIIX_IDETIM_READ(oidetim, channel) & PIIX_IDETIM_IDE) == 0) 2628 return; 2629 /* set up new idetim: Enable IDE registers decode */ 2630 idetim = PIIX_IDETIM_SET(idetim, PIIX_IDETIM_IDE, channel); 2631 2632 /* setup DMA if needed */ 2633 pciide_channel_dma_setup(cp); 2634 2635 for (drive = 0; drive < 2; drive++) { 2636 udmareg &= ~(PIIX_UDMACTL_DRV_EN(channel, drive) | 2637 PIIX_UDMATIM_SET(0x3, channel, drive)); 2638 drvp = &chp->ch_drive[drive]; 2639 /* If no drive, skip */ 2640 if ((drvp->drive_flags & DRIVE) == 0) 2641 continue; 2642 if (((drvp->drive_flags & DRIVE_DMA) == 0 && 2643 (drvp->drive_flags & DRIVE_UDMA) == 0)) 2644 goto pio; 2645 2646 if (sc->sc_pp->ide_product == PCI_PRODUCT_INTEL_6300ESB_IDE || 2647 sc->sc_pp->ide_product == PCI_PRODUCT_INTEL_6321ESB_IDE || 2648 sc->sc_pp->ide_product == PCI_PRODUCT_INTEL_82801AA_IDE || 2649 sc->sc_pp->ide_product == PCI_PRODUCT_INTEL_82801AB_IDE || 2650 sc->sc_pp->ide_product == PCI_PRODUCT_INTEL_82801BAM_IDE || 2651 sc->sc_pp->ide_product == PCI_PRODUCT_INTEL_82801BA_IDE || 2652 sc->sc_pp->ide_product == PCI_PRODUCT_INTEL_82801CAM_IDE || 2653 sc->sc_pp->ide_product == PCI_PRODUCT_INTEL_82801CA_IDE || 2654 sc->sc_pp->ide_product == PCI_PRODUCT_INTEL_82801DB_IDE || 2655 sc->sc_pp->ide_product == PCI_PRODUCT_INTEL_82801DBL_IDE || 2656 sc->sc_pp->ide_product == PCI_PRODUCT_INTEL_82801DBM_IDE || 2657 sc->sc_pp->ide_product == PCI_PRODUCT_INTEL_82801EB_IDE || 2658 sc->sc_pp->ide_product == PCI_PRODUCT_INTEL_82801FB_IDE || 2659 sc->sc_pp->ide_product == PCI_PRODUCT_INTEL_82801GB_IDE || 2660 sc->sc_pp->ide_product == PCI_PRODUCT_INTEL_82801HBM_IDE || 2661 sc->sc_pp->ide_product == PCI_PRODUCT_INTEL_82372FB_IDE) { 2662 ideconf |= PIIX_CONFIG_PINGPONG; 2663 } 2664 if (sc->sc_pp->ide_product == PCI_PRODUCT_INTEL_6300ESB_IDE || 2665 sc->sc_pp->ide_product == PCI_PRODUCT_INTEL_6321ESB_IDE || 2666 sc->sc_pp->ide_product == PCI_PRODUCT_INTEL_82801BAM_IDE || 2667 sc->sc_pp->ide_product == PCI_PRODUCT_INTEL_82801BA_IDE|| 2668 sc->sc_pp->ide_product == PCI_PRODUCT_INTEL_82801CAM_IDE|| 2669 sc->sc_pp->ide_product == PCI_PRODUCT_INTEL_82801CA_IDE || 2670 sc->sc_pp->ide_product == PCI_PRODUCT_INTEL_82801DB_IDE || 2671 sc->sc_pp->ide_product == PCI_PRODUCT_INTEL_82801DBL_IDE || 2672 sc->sc_pp->ide_product == PCI_PRODUCT_INTEL_82801DBM_IDE || 2673 sc->sc_pp->ide_product == PCI_PRODUCT_INTEL_82801EB_IDE || 2674 sc->sc_pp->ide_product == PCI_PRODUCT_INTEL_82801FB_IDE || 2675 sc->sc_pp->ide_product == PCI_PRODUCT_INTEL_82801GB_IDE || 2676 sc->sc_pp->ide_product == PCI_PRODUCT_INTEL_82801HBM_IDE) { 2677 /* setup Ultra/100 */ 2678 if (drvp->UDMA_mode > 2 && 2679 (ideconf & PIIX_CONFIG_CR(channel, drive)) == 0) 2680 drvp->UDMA_mode = 2; 2681 if (drvp->UDMA_mode > 4) { 2682 ideconf |= PIIX_CONFIG_UDMA100(channel, drive); 2683 } else { 2684 ideconf &= ~PIIX_CONFIG_UDMA100(channel, drive); 2685 if (drvp->UDMA_mode > 2) { 2686 ideconf |= PIIX_CONFIG_UDMA66(channel, 2687 drive); 2688 } else { 2689 ideconf &= ~PIIX_CONFIG_UDMA66(channel, 2690 drive); 2691 } 2692 } 2693 } 2694 if (sc->sc_pp->ide_product == PCI_PRODUCT_INTEL_82801AA_IDE || 2695 sc->sc_pp->ide_product == PCI_PRODUCT_INTEL_82372FB_IDE) { 2696 /* setup Ultra/66 */ 2697 if (drvp->UDMA_mode > 2 && 2698 (ideconf & PIIX_CONFIG_CR(channel, drive)) == 0) 2699 drvp->UDMA_mode = 2; 2700 if (drvp->UDMA_mode > 2) 2701 ideconf |= PIIX_CONFIG_UDMA66(channel, drive); 2702 else 2703 ideconf &= ~PIIX_CONFIG_UDMA66(channel, drive); 2704 } 2705 2706 if ((chp->wdc->cap & WDC_CAPABILITY_UDMA) && 2707 (drvp->drive_flags & DRIVE_UDMA)) { 2708 /* use Ultra/DMA */ 2709 drvp->drive_flags &= ~DRIVE_DMA; 2710 udmareg |= PIIX_UDMACTL_DRV_EN( channel, drive); 2711 udmareg |= PIIX_UDMATIM_SET( 2712 piix4_sct_udma[drvp->UDMA_mode], channel, drive); 2713 } else { 2714 /* use Multiword DMA */ 2715 drvp->drive_flags &= ~DRIVE_UDMA; 2716 if (drive == 0) { 2717 idetim |= piix_setup_idetim_timings( 2718 drvp->DMA_mode, 1, channel); 2719 } else { 2720 sidetim |= piix_setup_sidetim_timings( 2721 drvp->DMA_mode, 1, channel); 2722 idetim =PIIX_IDETIM_SET(idetim, 2723 PIIX_IDETIM_SITRE, channel); 2724 } 2725 } 2726 idedma_ctl |= IDEDMA_CTL_DRV_DMA(drive); 2727 2728 pio: /* use PIO mode */ 2729 idetim |= piix_setup_idetim_drvs(drvp); 2730 if (drive == 0) { 2731 idetim |= piix_setup_idetim_timings( 2732 drvp->PIO_mode, 0, channel); 2733 } else { 2734 sidetim |= piix_setup_sidetim_timings( 2735 drvp->PIO_mode, 0, channel); 2736 idetim =PIIX_IDETIM_SET(idetim, 2737 PIIX_IDETIM_SITRE, channel); 2738 } 2739 } 2740 if (idedma_ctl != 0) { 2741 /* Add software bits in status register */ 2742 bus_space_write_1(sc->sc_dma_iot, sc->sc_dma_ioh, 2743 IDEDMA_CTL(channel), 2744 idedma_ctl); 2745 } 2746 pci_conf_write(sc->sc_pc, sc->sc_tag, PIIX_IDETIM, idetim); 2747 pci_conf_write(sc->sc_pc, sc->sc_tag, PIIX_SIDETIM, sidetim); 2748 pci_conf_write(sc->sc_pc, sc->sc_tag, PIIX_UDMAREG, udmareg); 2749 pci_conf_write(sc->sc_pc, sc->sc_tag, PIIX_CONFIG, ideconf); 2750 pciide_print_modes(cp); 2751 } 2752 2753 2754 /* setup ISP and RTC fields, based on mode */ 2755 u_int32_t 2756 piix_setup_idetim_timings(u_int8_t mode, u_int8_t dma, u_int8_t channel) 2757 { 2758 2759 if (dma) 2760 return (PIIX_IDETIM_SET(0, 2761 PIIX_IDETIM_ISP_SET(piix_isp_dma[mode]) | 2762 PIIX_IDETIM_RTC_SET(piix_rtc_dma[mode]), 2763 channel)); 2764 else 2765 return (PIIX_IDETIM_SET(0, 2766 PIIX_IDETIM_ISP_SET(piix_isp_pio[mode]) | 2767 PIIX_IDETIM_RTC_SET(piix_rtc_pio[mode]), 2768 channel)); 2769 } 2770 2771 /* setup DTE, PPE, IE and TIME field based on PIO mode */ 2772 u_int32_t 2773 piix_setup_idetim_drvs(struct ata_drive_datas *drvp) 2774 { 2775 u_int32_t ret = 0; 2776 struct channel_softc *chp = drvp->chnl_softc; 2777 u_int8_t channel = chp->channel; 2778 u_int8_t drive = drvp->drive; 2779 2780 /* 2781 * If drive is using UDMA, timings setups are independant 2782 * So just check DMA and PIO here. 2783 */ 2784 if (drvp->drive_flags & DRIVE_DMA) { 2785 /* if mode = DMA mode 0, use compatible timings */ 2786 if ((drvp->drive_flags & DRIVE_DMA) && 2787 drvp->DMA_mode == 0) { 2788 drvp->PIO_mode = 0; 2789 return (ret); 2790 } 2791 ret = PIIX_IDETIM_SET(ret, PIIX_IDETIM_TIME(drive), channel); 2792 /* 2793 * PIO and DMA timings are the same, use fast timings for PIO 2794 * too, else use compat timings. 2795 */ 2796 if ((piix_isp_pio[drvp->PIO_mode] != 2797 piix_isp_dma[drvp->DMA_mode]) || 2798 (piix_rtc_pio[drvp->PIO_mode] != 2799 piix_rtc_dma[drvp->DMA_mode])) 2800 drvp->PIO_mode = 0; 2801 /* if PIO mode <= 2, use compat timings for PIO */ 2802 if (drvp->PIO_mode <= 2) { 2803 ret = PIIX_IDETIM_SET(ret, PIIX_IDETIM_DTE(drive), 2804 channel); 2805 return (ret); 2806 } 2807 } 2808 2809 /* 2810 * Now setup PIO modes. If mode < 2, use compat timings. 2811 * Else enable fast timings. Enable IORDY and prefetch/post 2812 * if PIO mode >= 3. 2813 */ 2814 2815 if (drvp->PIO_mode < 2) 2816 return (ret); 2817 2818 ret = PIIX_IDETIM_SET(ret, PIIX_IDETIM_TIME(drive), channel); 2819 if (drvp->PIO_mode >= 3) { 2820 ret = PIIX_IDETIM_SET(ret, PIIX_IDETIM_IE(drive), channel); 2821 ret = PIIX_IDETIM_SET(ret, PIIX_IDETIM_PPE(drive), channel); 2822 } 2823 return (ret); 2824 } 2825 2826 /* setup values in SIDETIM registers, based on mode */ 2827 u_int32_t 2828 piix_setup_sidetim_timings(u_int8_t mode, u_int8_t dma, u_int8_t channel) 2829 { 2830 if (dma) 2831 return (PIIX_SIDETIM_ISP_SET(piix_isp_dma[mode], channel) | 2832 PIIX_SIDETIM_RTC_SET(piix_rtc_dma[mode], channel)); 2833 else 2834 return (PIIX_SIDETIM_ISP_SET(piix_isp_pio[mode], channel) | 2835 PIIX_SIDETIM_RTC_SET(piix_rtc_pio[mode], channel)); 2836 } 2837 2838 void 2839 amd756_chip_map(struct pciide_softc *sc, struct pci_attach_args *pa) 2840 { 2841 struct pciide_channel *cp; 2842 pcireg_t interface = PCI_INTERFACE(pa->pa_class); 2843 int channel; 2844 pcireg_t chanenable; 2845 bus_size_t cmdsize, ctlsize; 2846 2847 printf(": DMA"); 2848 pciide_mapreg_dma(sc, pa); 2849 sc->sc_wdcdev.cap = WDC_CAPABILITY_DATA16 | WDC_CAPABILITY_DATA32 | 2850 WDC_CAPABILITY_MODE; 2851 if (sc->sc_dma_ok) { 2852 sc->sc_wdcdev.cap |= WDC_CAPABILITY_DMA | WDC_CAPABILITY_UDMA; 2853 sc->sc_wdcdev.cap |= WDC_CAPABILITY_IRQACK; 2854 sc->sc_wdcdev.irqack = pciide_irqack; 2855 } 2856 sc->sc_wdcdev.PIO_cap = 4; 2857 sc->sc_wdcdev.DMA_cap = 2; 2858 switch (sc->sc_pp->ide_product) { 2859 case PCI_PRODUCT_AMD_8111_IDE: 2860 sc->sc_wdcdev.UDMA_cap = 6; 2861 break; 2862 case PCI_PRODUCT_AMD_766_IDE: 2863 case PCI_PRODUCT_AMD_PBC768_IDE: 2864 sc->sc_wdcdev.UDMA_cap = 5; 2865 break; 2866 default: 2867 sc->sc_wdcdev.UDMA_cap = 4; 2868 break; 2869 } 2870 sc->sc_wdcdev.set_modes = amd756_setup_channel; 2871 sc->sc_wdcdev.channels = sc->wdc_chanarray; 2872 sc->sc_wdcdev.nchannels = PCIIDE_NUM_CHANNELS; 2873 chanenable = pci_conf_read(sc->sc_pc, sc->sc_tag, AMD756_CHANSTATUS_EN); 2874 2875 pciide_print_channels(sc->sc_wdcdev.nchannels, interface); 2876 2877 for (channel = 0; channel < sc->sc_wdcdev.nchannels; channel++) { 2878 cp = &sc->pciide_channels[channel]; 2879 if (pciide_chansetup(sc, channel, interface) == 0) 2880 continue; 2881 2882 if ((chanenable & AMD756_CHAN_EN(channel)) == 0) { 2883 printf("%s: %s ignored (disabled)\n", 2884 sc->sc_wdcdev.sc_dev.dv_xname, cp->name); 2885 continue; 2886 } 2887 pciide_map_compat_intr(pa, cp, channel, interface); 2888 if (cp->hw_ok == 0) 2889 continue; 2890 2891 pciide_mapchan(pa, cp, interface, &cmdsize, &ctlsize, 2892 pciide_pci_intr); 2893 2894 if (pciide_chan_candisable(cp)) { 2895 chanenable &= ~AMD756_CHAN_EN(channel); 2896 } 2897 if (cp->hw_ok == 0) { 2898 pciide_unmap_compat_intr(pa, cp, channel, interface); 2899 continue; 2900 } 2901 2902 amd756_setup_channel(&cp->wdc_channel); 2903 } 2904 pci_conf_write(sc->sc_pc, sc->sc_tag, AMD756_CHANSTATUS_EN, 2905 chanenable); 2906 return; 2907 } 2908 2909 void 2910 amd756_setup_channel(struct channel_softc *chp) 2911 { 2912 u_int32_t udmatim_reg, datatim_reg; 2913 u_int8_t idedma_ctl; 2914 int mode, drive; 2915 struct ata_drive_datas *drvp; 2916 struct pciide_channel *cp = (struct pciide_channel *)chp; 2917 struct pciide_softc *sc = (struct pciide_softc *)cp->wdc_channel.wdc; 2918 pcireg_t chanenable; 2919 #ifndef PCIIDE_AMD756_ENABLEDMA 2920 int product = sc->sc_pp->ide_product; 2921 int rev = sc->sc_rev; 2922 #endif 2923 2924 idedma_ctl = 0; 2925 datatim_reg = pci_conf_read(sc->sc_pc, sc->sc_tag, AMD756_DATATIM); 2926 udmatim_reg = pci_conf_read(sc->sc_pc, sc->sc_tag, AMD756_UDMA); 2927 datatim_reg &= ~AMD756_DATATIM_MASK(chp->channel); 2928 udmatim_reg &= ~AMD756_UDMA_MASK(chp->channel); 2929 chanenable = pci_conf_read(sc->sc_pc, sc->sc_tag, 2930 AMD756_CHANSTATUS_EN); 2931 2932 /* setup DMA if needed */ 2933 pciide_channel_dma_setup(cp); 2934 2935 for (drive = 0; drive < 2; drive++) { 2936 drvp = &chp->ch_drive[drive]; 2937 /* If no drive, skip */ 2938 if ((drvp->drive_flags & DRIVE) == 0) 2939 continue; 2940 /* add timing values, setup DMA if needed */ 2941 if (((drvp->drive_flags & DRIVE_DMA) == 0 && 2942 (drvp->drive_flags & DRIVE_UDMA) == 0)) { 2943 mode = drvp->PIO_mode; 2944 goto pio; 2945 } 2946 if ((chp->wdc->cap & WDC_CAPABILITY_UDMA) && 2947 (drvp->drive_flags & DRIVE_UDMA)) { 2948 /* use Ultra/DMA */ 2949 drvp->drive_flags &= ~DRIVE_DMA; 2950 2951 /* Check cable */ 2952 if ((chanenable & AMD756_CABLE(chp->channel, 2953 drive)) == 0 && drvp->UDMA_mode > 2) { 2954 WDCDEBUG_PRINT(("%s(%s:%d:%d): 80-wire " 2955 "cable not detected\n", drvp->drive_name, 2956 sc->sc_wdcdev.sc_dev.dv_xname, 2957 chp->channel, drive), DEBUG_PROBE); 2958 drvp->UDMA_mode = 2; 2959 } 2960 2961 udmatim_reg |= AMD756_UDMA_EN(chp->channel, drive) | 2962 AMD756_UDMA_EN_MTH(chp->channel, drive) | 2963 AMD756_UDMA_TIME(chp->channel, drive, 2964 amd756_udma_tim[drvp->UDMA_mode]); 2965 /* can use PIO timings, MW DMA unused */ 2966 mode = drvp->PIO_mode; 2967 } else { 2968 /* use Multiword DMA, but only if revision is OK */ 2969 drvp->drive_flags &= ~DRIVE_UDMA; 2970 #ifndef PCIIDE_AMD756_ENABLEDMA 2971 /* 2972 * The workaround doesn't seem to be necessary 2973 * with all drives, so it can be disabled by 2974 * PCIIDE_AMD756_ENABLEDMA. It causes a hard hang if 2975 * triggered. 2976 */ 2977 if (AMD756_CHIPREV_DISABLEDMA(product, rev)) { 2978 printf("%s:%d:%d: multi-word DMA disabled due " 2979 "to chip revision\n", 2980 sc->sc_wdcdev.sc_dev.dv_xname, 2981 chp->channel, drive); 2982 mode = drvp->PIO_mode; 2983 drvp->drive_flags &= ~DRIVE_DMA; 2984 goto pio; 2985 } 2986 #endif 2987 /* mode = min(pio, dma+2) */ 2988 if (drvp->PIO_mode <= (drvp->DMA_mode +2)) 2989 mode = drvp->PIO_mode; 2990 else 2991 mode = drvp->DMA_mode + 2; 2992 } 2993 idedma_ctl |= IDEDMA_CTL_DRV_DMA(drive); 2994 2995 pio: /* setup PIO mode */ 2996 if (mode <= 2) { 2997 drvp->DMA_mode = 0; 2998 drvp->PIO_mode = 0; 2999 mode = 0; 3000 } else { 3001 drvp->PIO_mode = mode; 3002 drvp->DMA_mode = mode - 2; 3003 } 3004 datatim_reg |= 3005 AMD756_DATATIM_PULSE(chp->channel, drive, 3006 amd756_pio_set[mode]) | 3007 AMD756_DATATIM_RECOV(chp->channel, drive, 3008 amd756_pio_rec[mode]); 3009 } 3010 if (idedma_ctl != 0) { 3011 /* Add software bits in status register */ 3012 bus_space_write_1(sc->sc_dma_iot, sc->sc_dma_ioh, 3013 IDEDMA_CTL(chp->channel), 3014 idedma_ctl); 3015 } 3016 pciide_print_modes(cp); 3017 pci_conf_write(sc->sc_pc, sc->sc_tag, AMD756_DATATIM, datatim_reg); 3018 pci_conf_write(sc->sc_pc, sc->sc_tag, AMD756_UDMA, udmatim_reg); 3019 } 3020 3021 void 3022 apollo_chip_map(struct pciide_softc *sc, struct pci_attach_args *pa) 3023 { 3024 struct pciide_channel *cp; 3025 pcireg_t interface; 3026 int channel; 3027 u_int32_t ideconf; 3028 bus_size_t cmdsize, ctlsize; 3029 pcitag_t tag; 3030 pcireg_t id, class; 3031 3032 /* 3033 * Fake interface since VT6410 is claimed to be a ``RAID'' device. 3034 */ 3035 if (PCI_SUBCLASS(pa->pa_class) == PCI_SUBCLASS_MASS_STORAGE_IDE) { 3036 interface = PCI_INTERFACE(pa->pa_class); 3037 } else { 3038 interface = PCIIDE_INTERFACE_BUS_MASTER_DMA | 3039 PCIIDE_INTERFACE_PCI(0) | PCIIDE_INTERFACE_PCI(1); 3040 } 3041 3042 if ((PCI_PRODUCT(pa->pa_id) == PCI_PRODUCT_VIATECH_VT6410) || 3043 (PCI_PRODUCT(pa->pa_id) == PCI_PRODUCT_VIATECH_CX700_IDE) || 3044 (PCI_PRODUCT(pa->pa_id) == PCI_PRODUCT_VIATECH_VX700_IDE)) { 3045 printf(": ATA133"); 3046 sc->sc_wdcdev.UDMA_cap = 6; 3047 } else { 3048 /* 3049 * Determine the DMA capabilities by looking at the 3050 * ISA bridge. 3051 */ 3052 tag = pci_make_tag(pa->pa_pc, pa->pa_bus, pa->pa_device, 0); 3053 id = pci_conf_read(sc->sc_pc, tag, PCI_ID_REG); 3054 class = pci_conf_read(sc->sc_pc, tag, PCI_CLASS_REG); 3055 3056 /* 3057 * XXX On the VT8237, the ISA bridge is on a different 3058 * device. 3059 */ 3060 if (PCI_CLASS(class) != PCI_CLASS_BRIDGE && 3061 pa->pa_device == 15) { 3062 tag = pci_make_tag(pa->pa_pc, pa->pa_bus, 17, 0); 3063 id = pci_conf_read(sc->sc_pc, tag, PCI_ID_REG); 3064 class = pci_conf_read(sc->sc_pc, tag, PCI_CLASS_REG); 3065 } 3066 3067 switch (PCI_PRODUCT(id)) { 3068 case PCI_PRODUCT_VIATECH_VT82C586_ISA: 3069 if (PCI_REVISION(class) >= 0x02) { 3070 printf(": ATA33"); 3071 sc->sc_wdcdev.UDMA_cap = 2; 3072 } else { 3073 printf(": DMA"); 3074 sc->sc_wdcdev.UDMA_cap = 0; 3075 } 3076 break; 3077 case PCI_PRODUCT_VIATECH_VT82C596A: 3078 if (PCI_REVISION(class) >= 0x12) { 3079 printf(": ATA66"); 3080 sc->sc_wdcdev.UDMA_cap = 4; 3081 } else { 3082 printf(": ATA33"); 3083 sc->sc_wdcdev.UDMA_cap = 2; 3084 } 3085 break; 3086 3087 case PCI_PRODUCT_VIATECH_VT82C686A_ISA: 3088 if (PCI_REVISION(class) >= 0x40) { 3089 printf(": ATA100"); 3090 sc->sc_wdcdev.UDMA_cap = 5; 3091 } else { 3092 printf(": ATA66"); 3093 sc->sc_wdcdev.UDMA_cap = 4; 3094 } 3095 break; 3096 case PCI_PRODUCT_VIATECH_VT8231_ISA: 3097 case PCI_PRODUCT_VIATECH_VT8233_ISA: 3098 printf(": ATA100"); 3099 sc->sc_wdcdev.UDMA_cap = 5; 3100 break; 3101 case PCI_PRODUCT_VIATECH_VT8233A_ISA: 3102 case PCI_PRODUCT_VIATECH_VT8235_ISA: 3103 case PCI_PRODUCT_VIATECH_VT8237_ISA: 3104 printf(": ATA133"); 3105 sc->sc_wdcdev.UDMA_cap = 6; 3106 break; 3107 default: 3108 printf(": DMA"); 3109 sc->sc_wdcdev.UDMA_cap = 0; 3110 break; 3111 } 3112 } 3113 3114 pciide_mapreg_dma(sc, pa); 3115 sc->sc_wdcdev.cap |= WDC_CAPABILITY_DATA16 | WDC_CAPABILITY_DATA32 | 3116 WDC_CAPABILITY_MODE; 3117 if (sc->sc_dma_ok) { 3118 sc->sc_wdcdev.cap |= WDC_CAPABILITY_DMA | WDC_CAPABILITY_IRQACK; 3119 sc->sc_wdcdev.irqack = pciide_irqack; 3120 if (sc->sc_wdcdev.UDMA_cap > 0) 3121 sc->sc_wdcdev.cap |= WDC_CAPABILITY_UDMA; 3122 } 3123 sc->sc_wdcdev.PIO_cap = 4; 3124 sc->sc_wdcdev.DMA_cap = 2; 3125 sc->sc_wdcdev.set_modes = apollo_setup_channel; 3126 sc->sc_wdcdev.channels = sc->wdc_chanarray; 3127 sc->sc_wdcdev.nchannels = PCIIDE_NUM_CHANNELS; 3128 3129 pciide_print_channels(sc->sc_wdcdev.nchannels, interface); 3130 3131 WDCDEBUG_PRINT(("apollo_chip_map: old APO_IDECONF=0x%x, " 3132 "APO_CTLMISC=0x%x, APO_DATATIM=0x%x, APO_UDMA=0x%x\n", 3133 pci_conf_read(sc->sc_pc, sc->sc_tag, APO_IDECONF), 3134 pci_conf_read(sc->sc_pc, sc->sc_tag, APO_CTLMISC), 3135 pci_conf_read(sc->sc_pc, sc->sc_tag, APO_DATATIM), 3136 pci_conf_read(sc->sc_pc, sc->sc_tag, APO_UDMA)), 3137 DEBUG_PROBE); 3138 3139 for (channel = 0; channel < sc->sc_wdcdev.nchannels; channel++) { 3140 cp = &sc->pciide_channels[channel]; 3141 if (pciide_chansetup(sc, channel, interface) == 0) 3142 continue; 3143 3144 ideconf = pci_conf_read(sc->sc_pc, sc->sc_tag, APO_IDECONF); 3145 if ((ideconf & APO_IDECONF_EN(channel)) == 0) { 3146 printf("%s: %s ignored (disabled)\n", 3147 sc->sc_wdcdev.sc_dev.dv_xname, cp->name); 3148 continue; 3149 } 3150 pciide_map_compat_intr(pa, cp, channel, interface); 3151 if (cp->hw_ok == 0) 3152 continue; 3153 3154 pciide_mapchan(pa, cp, interface, &cmdsize, &ctlsize, 3155 pciide_pci_intr); 3156 if (cp->hw_ok == 0) { 3157 goto next; 3158 } 3159 if (pciide_chan_candisable(cp)) { 3160 ideconf &= ~APO_IDECONF_EN(channel); 3161 pci_conf_write(sc->sc_pc, sc->sc_tag, APO_IDECONF, 3162 ideconf); 3163 } 3164 3165 if (cp->hw_ok == 0) 3166 goto next; 3167 apollo_setup_channel(&sc->pciide_channels[channel].wdc_channel); 3168 next: 3169 if (cp->hw_ok == 0) 3170 pciide_unmap_compat_intr(pa, cp, channel, interface); 3171 } 3172 WDCDEBUG_PRINT(("apollo_chip_map: APO_DATATIM=0x%x, APO_UDMA=0x%x\n", 3173 pci_conf_read(sc->sc_pc, sc->sc_tag, APO_DATATIM), 3174 pci_conf_read(sc->sc_pc, sc->sc_tag, APO_UDMA)), DEBUG_PROBE); 3175 } 3176 3177 void 3178 apollo_setup_channel(struct channel_softc *chp) 3179 { 3180 u_int32_t udmatim_reg, datatim_reg; 3181 u_int8_t idedma_ctl; 3182 int mode, drive; 3183 struct ata_drive_datas *drvp; 3184 struct pciide_channel *cp = (struct pciide_channel *)chp; 3185 struct pciide_softc *sc = (struct pciide_softc *)cp->wdc_channel.wdc; 3186 3187 idedma_ctl = 0; 3188 datatim_reg = pci_conf_read(sc->sc_pc, sc->sc_tag, APO_DATATIM); 3189 udmatim_reg = pci_conf_read(sc->sc_pc, sc->sc_tag, APO_UDMA); 3190 datatim_reg &= ~APO_DATATIM_MASK(chp->channel); 3191 udmatim_reg &= ~APO_UDMA_MASK(chp->channel); 3192 3193 /* setup DMA if needed */ 3194 pciide_channel_dma_setup(cp); 3195 3196 /* 3197 * We can't mix Ultra/33 and Ultra/66 on the same channel, so 3198 * downgrade to Ultra/33 if needed 3199 */ 3200 if ((chp->ch_drive[0].drive_flags & DRIVE_UDMA) && 3201 (chp->ch_drive[1].drive_flags & DRIVE_UDMA)) { 3202 /* both drives UDMA */ 3203 if (chp->ch_drive[0].UDMA_mode > 2 && 3204 chp->ch_drive[1].UDMA_mode <= 2) { 3205 /* drive 0 Ultra/66, drive 1 Ultra/33 */ 3206 chp->ch_drive[0].UDMA_mode = 2; 3207 } else if (chp->ch_drive[1].UDMA_mode > 2 && 3208 chp->ch_drive[0].UDMA_mode <= 2) { 3209 /* drive 1 Ultra/66, drive 0 Ultra/33 */ 3210 chp->ch_drive[1].UDMA_mode = 2; 3211 } 3212 } 3213 3214 for (drive = 0; drive < 2; drive++) { 3215 drvp = &chp->ch_drive[drive]; 3216 /* If no drive, skip */ 3217 if ((drvp->drive_flags & DRIVE) == 0) 3218 continue; 3219 /* add timing values, setup DMA if needed */ 3220 if (((drvp->drive_flags & DRIVE_DMA) == 0 && 3221 (drvp->drive_flags & DRIVE_UDMA) == 0)) { 3222 mode = drvp->PIO_mode; 3223 goto pio; 3224 } 3225 if ((chp->wdc->cap & WDC_CAPABILITY_UDMA) && 3226 (drvp->drive_flags & DRIVE_UDMA)) { 3227 /* use Ultra/DMA */ 3228 drvp->drive_flags &= ~DRIVE_DMA; 3229 udmatim_reg |= APO_UDMA_EN(chp->channel, drive) | 3230 APO_UDMA_EN_MTH(chp->channel, drive); 3231 if (sc->sc_wdcdev.UDMA_cap == 6) { 3232 udmatim_reg |= APO_UDMA_TIME(chp->channel, 3233 drive, apollo_udma133_tim[drvp->UDMA_mode]); 3234 } else if (sc->sc_wdcdev.UDMA_cap == 5) { 3235 /* 686b */ 3236 udmatim_reg |= APO_UDMA_TIME(chp->channel, 3237 drive, apollo_udma100_tim[drvp->UDMA_mode]); 3238 } else if (sc->sc_wdcdev.UDMA_cap == 4) { 3239 /* 596b or 686a */ 3240 udmatim_reg |= APO_UDMA_CLK66(chp->channel); 3241 udmatim_reg |= APO_UDMA_TIME(chp->channel, 3242 drive, apollo_udma66_tim[drvp->UDMA_mode]); 3243 } else { 3244 /* 596a or 586b */ 3245 udmatim_reg |= APO_UDMA_TIME(chp->channel, 3246 drive, apollo_udma33_tim[drvp->UDMA_mode]); 3247 } 3248 /* can use PIO timings, MW DMA unused */ 3249 mode = drvp->PIO_mode; 3250 } else { 3251 /* use Multiword DMA */ 3252 drvp->drive_flags &= ~DRIVE_UDMA; 3253 /* mode = min(pio, dma+2) */ 3254 if (drvp->PIO_mode <= (drvp->DMA_mode +2)) 3255 mode = drvp->PIO_mode; 3256 else 3257 mode = drvp->DMA_mode + 2; 3258 } 3259 idedma_ctl |= IDEDMA_CTL_DRV_DMA(drive); 3260 3261 pio: /* setup PIO mode */ 3262 if (mode <= 2) { 3263 drvp->DMA_mode = 0; 3264 drvp->PIO_mode = 0; 3265 mode = 0; 3266 } else { 3267 drvp->PIO_mode = mode; 3268 drvp->DMA_mode = mode - 2; 3269 } 3270 datatim_reg |= 3271 APO_DATATIM_PULSE(chp->channel, drive, 3272 apollo_pio_set[mode]) | 3273 APO_DATATIM_RECOV(chp->channel, drive, 3274 apollo_pio_rec[mode]); 3275 } 3276 if (idedma_ctl != 0) { 3277 /* Add software bits in status register */ 3278 bus_space_write_1(sc->sc_dma_iot, sc->sc_dma_ioh, 3279 IDEDMA_CTL(chp->channel), 3280 idedma_ctl); 3281 } 3282 pciide_print_modes(cp); 3283 pci_conf_write(sc->sc_pc, sc->sc_tag, APO_DATATIM, datatim_reg); 3284 pci_conf_write(sc->sc_pc, sc->sc_tag, APO_UDMA, udmatim_reg); 3285 } 3286 3287 void 3288 cmd_channel_map(struct pci_attach_args *pa, struct pciide_softc *sc, 3289 int channel) 3290 { 3291 struct pciide_channel *cp = &sc->pciide_channels[channel]; 3292 bus_size_t cmdsize, ctlsize; 3293 u_int8_t ctrl = pciide_pci_read(sc->sc_pc, sc->sc_tag, CMD_CTRL); 3294 pcireg_t interface; 3295 int one_channel; 3296 3297 /* 3298 * The 0648/0649 can be told to identify as a RAID controller. 3299 * In this case, we have to fake interface 3300 */ 3301 if (PCI_SUBCLASS(pa->pa_class) != PCI_SUBCLASS_MASS_STORAGE_IDE) { 3302 interface = PCIIDE_INTERFACE_SETTABLE(0) | 3303 PCIIDE_INTERFACE_SETTABLE(1); 3304 if (pciide_pci_read(pa->pa_pc, pa->pa_tag, CMD_CONF) & 3305 CMD_CONF_DSA1) 3306 interface |= PCIIDE_INTERFACE_PCI(0) | 3307 PCIIDE_INTERFACE_PCI(1); 3308 } else { 3309 interface = PCI_INTERFACE(pa->pa_class); 3310 } 3311 3312 sc->wdc_chanarray[channel] = &cp->wdc_channel; 3313 cp->name = PCIIDE_CHANNEL_NAME(channel); 3314 cp->wdc_channel.channel = channel; 3315 cp->wdc_channel.wdc = &sc->sc_wdcdev; 3316 3317 /* 3318 * Older CMD64X doesn't have independant channels 3319 */ 3320 switch (sc->sc_pp->ide_product) { 3321 case PCI_PRODUCT_CMDTECH_649: 3322 one_channel = 0; 3323 break; 3324 default: 3325 one_channel = 1; 3326 break; 3327 } 3328 3329 if (channel > 0 && one_channel) { 3330 cp->wdc_channel.ch_queue = 3331 sc->pciide_channels[0].wdc_channel.ch_queue; 3332 } else { 3333 cp->wdc_channel.ch_queue = 3334 malloc(sizeof(struct channel_queue), M_DEVBUF, M_NOWAIT); 3335 } 3336 if (cp->wdc_channel.ch_queue == NULL) { 3337 printf( 3338 "%s: %s cannot allocate memory for command queue", 3339 sc->sc_wdcdev.sc_dev.dv_xname, cp->name); 3340 return; 3341 } 3342 3343 /* 3344 * with a CMD PCI64x, if we get here, the first channel is enabled: 3345 * there's no way to disable the first channel without disabling 3346 * the whole device 3347 */ 3348 if (channel != 0 && (ctrl & CMD_CTRL_2PORT) == 0) { 3349 printf("%s: %s ignored (disabled)\n", 3350 sc->sc_wdcdev.sc_dev.dv_xname, cp->name); 3351 return; 3352 } 3353 cp->hw_ok = 1; 3354 pciide_map_compat_intr(pa, cp, channel, interface); 3355 if (cp->hw_ok == 0) 3356 return; 3357 pciide_mapchan(pa, cp, interface, &cmdsize, &ctlsize, cmd_pci_intr); 3358 if (cp->hw_ok == 0) { 3359 pciide_unmap_compat_intr(pa, cp, channel, interface); 3360 return; 3361 } 3362 if (pciide_chan_candisable(cp)) { 3363 if (channel == 1) { 3364 ctrl &= ~CMD_CTRL_2PORT; 3365 pciide_pci_write(pa->pa_pc, pa->pa_tag, 3366 CMD_CTRL, ctrl); 3367 pciide_unmap_compat_intr(pa, cp, channel, interface); 3368 } 3369 } 3370 } 3371 3372 int 3373 cmd_pci_intr(void *arg) 3374 { 3375 struct pciide_softc *sc = arg; 3376 struct pciide_channel *cp; 3377 struct channel_softc *wdc_cp; 3378 int i, rv, crv; 3379 u_int32_t priirq, secirq; 3380 3381 rv = 0; 3382 priirq = pciide_pci_read(sc->sc_pc, sc->sc_tag, CMD_CONF); 3383 secirq = pciide_pci_read(sc->sc_pc, sc->sc_tag, CMD_ARTTIM23); 3384 for (i = 0; i < sc->sc_wdcdev.nchannels; i++) { 3385 cp = &sc->pciide_channels[i]; 3386 wdc_cp = &cp->wdc_channel; 3387 /* If a compat channel skip. */ 3388 if (cp->compat) 3389 continue; 3390 if ((i == 0 && (priirq & CMD_CONF_DRV0_INTR)) || 3391 (i == 1 && (secirq & CMD_ARTTIM23_IRQ))) { 3392 crv = wdcintr(wdc_cp); 3393 if (crv == 0) { 3394 #if 0 3395 printf("%s:%d: bogus intr\n", 3396 sc->sc_wdcdev.sc_dev.dv_xname, i); 3397 #endif 3398 } else 3399 rv = 1; 3400 } 3401 } 3402 return (rv); 3403 } 3404 3405 void 3406 cmd_chip_map(struct pciide_softc *sc, struct pci_attach_args *pa) 3407 { 3408 int channel; 3409 pcireg_t interface = PCI_INTERFACE(pa->pa_class); 3410 3411 printf(": no DMA"); 3412 sc->sc_dma_ok = 0; 3413 3414 sc->sc_wdcdev.channels = sc->wdc_chanarray; 3415 sc->sc_wdcdev.nchannels = PCIIDE_NUM_CHANNELS; 3416 sc->sc_wdcdev.cap = WDC_CAPABILITY_DATA16; 3417 3418 pciide_print_channels(sc->sc_wdcdev.nchannels, interface); 3419 3420 for (channel = 0; channel < sc->sc_wdcdev.nchannels; channel++) { 3421 cmd_channel_map(pa, sc, channel); 3422 } 3423 } 3424 3425 void 3426 cmd0643_9_chip_map(struct pciide_softc *sc, struct pci_attach_args *pa) 3427 { 3428 struct pciide_channel *cp; 3429 int channel; 3430 int rev = sc->sc_rev; 3431 pcireg_t interface; 3432 3433 /* 3434 * The 0648/0649 can be told to identify as a RAID controller. 3435 * In this case, we have to fake interface 3436 */ 3437 if (PCI_SUBCLASS(pa->pa_class) != PCI_SUBCLASS_MASS_STORAGE_IDE) { 3438 interface = PCIIDE_INTERFACE_SETTABLE(0) | 3439 PCIIDE_INTERFACE_SETTABLE(1); 3440 if (pciide_pci_read(pa->pa_pc, pa->pa_tag, CMD_CONF) & 3441 CMD_CONF_DSA1) 3442 interface |= PCIIDE_INTERFACE_PCI(0) | 3443 PCIIDE_INTERFACE_PCI(1); 3444 } else { 3445 interface = PCI_INTERFACE(pa->pa_class); 3446 } 3447 3448 printf(": DMA"); 3449 pciide_mapreg_dma(sc, pa); 3450 sc->sc_wdcdev.cap = WDC_CAPABILITY_DATA16 | WDC_CAPABILITY_DATA32 | 3451 WDC_CAPABILITY_MODE; 3452 if (sc->sc_dma_ok) { 3453 sc->sc_wdcdev.cap |= WDC_CAPABILITY_DMA | WDC_CAPABILITY_IRQACK; 3454 switch (sc->sc_pp->ide_product) { 3455 case PCI_PRODUCT_CMDTECH_649: 3456 sc->sc_wdcdev.cap |= WDC_CAPABILITY_UDMA; 3457 sc->sc_wdcdev.UDMA_cap = 5; 3458 sc->sc_wdcdev.irqack = cmd646_9_irqack; 3459 break; 3460 case PCI_PRODUCT_CMDTECH_648: 3461 sc->sc_wdcdev.cap |= WDC_CAPABILITY_UDMA; 3462 sc->sc_wdcdev.UDMA_cap = 4; 3463 sc->sc_wdcdev.irqack = cmd646_9_irqack; 3464 break; 3465 case PCI_PRODUCT_CMDTECH_646: 3466 if (rev >= CMD0646U2_REV) { 3467 sc->sc_wdcdev.cap |= WDC_CAPABILITY_UDMA; 3468 sc->sc_wdcdev.UDMA_cap = 2; 3469 } else if (rev >= CMD0646U_REV) { 3470 /* 3471 * Linux's driver claims that the 646U is broken 3472 * with UDMA. Only enable it if we know what we're 3473 * doing 3474 */ 3475 #ifdef PCIIDE_CMD0646U_ENABLEUDMA 3476 sc->sc_wdcdev.cap |= WDC_CAPABILITY_UDMA; 3477 sc->sc_wdcdev.UDMA_cap = 2; 3478 #endif 3479 /* explicitly disable UDMA */ 3480 pciide_pci_write(sc->sc_pc, sc->sc_tag, 3481 CMD_UDMATIM(0), 0); 3482 pciide_pci_write(sc->sc_pc, sc->sc_tag, 3483 CMD_UDMATIM(1), 0); 3484 } 3485 sc->sc_wdcdev.irqack = cmd646_9_irqack; 3486 break; 3487 default: 3488 sc->sc_wdcdev.irqack = pciide_irqack; 3489 } 3490 } 3491 3492 sc->sc_wdcdev.channels = sc->wdc_chanarray; 3493 sc->sc_wdcdev.nchannels = PCIIDE_NUM_CHANNELS; 3494 sc->sc_wdcdev.PIO_cap = 4; 3495 sc->sc_wdcdev.DMA_cap = 2; 3496 sc->sc_wdcdev.set_modes = cmd0643_9_setup_channel; 3497 3498 pciide_print_channels(sc->sc_wdcdev.nchannels, interface); 3499 3500 WDCDEBUG_PRINT(("cmd0643_9_chip_map: old timings reg 0x%x 0x%x\n", 3501 pci_conf_read(sc->sc_pc, sc->sc_tag, 0x54), 3502 pci_conf_read(sc->sc_pc, sc->sc_tag, 0x58)), 3503 DEBUG_PROBE); 3504 for (channel = 0; channel < sc->sc_wdcdev.nchannels; channel++) { 3505 cp = &sc->pciide_channels[channel]; 3506 cmd_channel_map(pa, sc, channel); 3507 if (cp->hw_ok == 0) 3508 continue; 3509 cmd0643_9_setup_channel(&cp->wdc_channel); 3510 } 3511 /* 3512 * note - this also makes sure we clear the irq disable and reset 3513 * bits 3514 */ 3515 pciide_pci_write(sc->sc_pc, sc->sc_tag, CMD_DMA_MODE, CMD_DMA_MULTIPLE); 3516 WDCDEBUG_PRINT(("cmd0643_9_chip_map: timings reg now 0x%x 0x%x\n", 3517 pci_conf_read(sc->sc_pc, sc->sc_tag, 0x54), 3518 pci_conf_read(sc->sc_pc, sc->sc_tag, 0x58)), 3519 DEBUG_PROBE); 3520 } 3521 3522 void 3523 cmd0643_9_setup_channel(struct channel_softc *chp) 3524 { 3525 struct ata_drive_datas *drvp; 3526 u_int8_t tim; 3527 u_int32_t idedma_ctl, udma_reg; 3528 int drive; 3529 struct pciide_channel *cp = (struct pciide_channel *)chp; 3530 struct pciide_softc *sc = (struct pciide_softc *)cp->wdc_channel.wdc; 3531 3532 idedma_ctl = 0; 3533 /* setup DMA if needed */ 3534 pciide_channel_dma_setup(cp); 3535 3536 for (drive = 0; drive < 2; drive++) { 3537 drvp = &chp->ch_drive[drive]; 3538 /* If no drive, skip */ 3539 if ((drvp->drive_flags & DRIVE) == 0) 3540 continue; 3541 /* add timing values, setup DMA if needed */ 3542 tim = cmd0643_9_data_tim_pio[drvp->PIO_mode]; 3543 if (drvp->drive_flags & (DRIVE_DMA | DRIVE_UDMA)) { 3544 if (drvp->drive_flags & DRIVE_UDMA) { 3545 /* UltraDMA on a 646U2, 0648 or 0649 */ 3546 drvp->drive_flags &= ~DRIVE_DMA; 3547 udma_reg = pciide_pci_read(sc->sc_pc, 3548 sc->sc_tag, CMD_UDMATIM(chp->channel)); 3549 if (drvp->UDMA_mode > 2 && 3550 (pciide_pci_read(sc->sc_pc, sc->sc_tag, 3551 CMD_BICSR) & 3552 CMD_BICSR_80(chp->channel)) == 0) { 3553 WDCDEBUG_PRINT(("%s(%s:%d:%d): " 3554 "80-wire cable not detected\n", 3555 drvp->drive_name, 3556 sc->sc_wdcdev.sc_dev.dv_xname, 3557 chp->channel, drive), DEBUG_PROBE); 3558 drvp->UDMA_mode = 2; 3559 } 3560 if (drvp->UDMA_mode > 2) 3561 udma_reg &= ~CMD_UDMATIM_UDMA33(drive); 3562 else if (sc->sc_wdcdev.UDMA_cap > 2) 3563 udma_reg |= CMD_UDMATIM_UDMA33(drive); 3564 udma_reg |= CMD_UDMATIM_UDMA(drive); 3565 udma_reg &= ~(CMD_UDMATIM_TIM_MASK << 3566 CMD_UDMATIM_TIM_OFF(drive)); 3567 udma_reg |= 3568 (cmd0646_9_tim_udma[drvp->UDMA_mode] << 3569 CMD_UDMATIM_TIM_OFF(drive)); 3570 pciide_pci_write(sc->sc_pc, sc->sc_tag, 3571 CMD_UDMATIM(chp->channel), udma_reg); 3572 } else { 3573 /* 3574 * use Multiword DMA. 3575 * Timings will be used for both PIO and DMA, 3576 * so adjust DMA mode if needed 3577 * if we have a 0646U2/8/9, turn off UDMA 3578 */ 3579 if (sc->sc_wdcdev.cap & WDC_CAPABILITY_UDMA) { 3580 udma_reg = pciide_pci_read(sc->sc_pc, 3581 sc->sc_tag, 3582 CMD_UDMATIM(chp->channel)); 3583 udma_reg &= ~CMD_UDMATIM_UDMA(drive); 3584 pciide_pci_write(sc->sc_pc, sc->sc_tag, 3585 CMD_UDMATIM(chp->channel), 3586 udma_reg); 3587 } 3588 if (drvp->PIO_mode >= 3 && 3589 (drvp->DMA_mode + 2) > drvp->PIO_mode) { 3590 drvp->DMA_mode = drvp->PIO_mode - 2; 3591 } 3592 tim = cmd0643_9_data_tim_dma[drvp->DMA_mode]; 3593 } 3594 idedma_ctl |= IDEDMA_CTL_DRV_DMA(drive); 3595 } 3596 pciide_pci_write(sc->sc_pc, sc->sc_tag, 3597 CMD_DATA_TIM(chp->channel, drive), tim); 3598 } 3599 if (idedma_ctl != 0) { 3600 /* Add software bits in status register */ 3601 bus_space_write_1(sc->sc_dma_iot, sc->sc_dma_ioh, 3602 IDEDMA_CTL(chp->channel), 3603 idedma_ctl); 3604 } 3605 pciide_print_modes(cp); 3606 #ifdef __sparc64__ 3607 /* 3608 * The Ultra 5 has a tendency to hang during reboot. This is due 3609 * to the PCI0646U asserting a PCI interrupt line when the chip 3610 * registers claim that it is not. Performing a reset at this 3611 * point appears to eliminate the symptoms. It is likely the 3612 * real cause is still lurking somewhere in the code. 3613 */ 3614 wdcreset(chp, SILENT); 3615 #endif /* __sparc64__ */ 3616 } 3617 3618 void 3619 cmd646_9_irqack(struct channel_softc *chp) 3620 { 3621 u_int32_t priirq, secirq; 3622 struct pciide_channel *cp = (struct pciide_channel *)chp; 3623 struct pciide_softc *sc = (struct pciide_softc *)cp->wdc_channel.wdc; 3624 3625 if (chp->channel == 0) { 3626 priirq = pciide_pci_read(sc->sc_pc, sc->sc_tag, CMD_CONF); 3627 pciide_pci_write(sc->sc_pc, sc->sc_tag, CMD_CONF, priirq); 3628 } else { 3629 secirq = pciide_pci_read(sc->sc_pc, sc->sc_tag, CMD_ARTTIM23); 3630 pciide_pci_write(sc->sc_pc, sc->sc_tag, CMD_ARTTIM23, secirq); 3631 } 3632 pciide_irqack(chp); 3633 } 3634 3635 void 3636 cmd680_chip_map(struct pciide_softc *sc, struct pci_attach_args *pa) 3637 { 3638 struct pciide_channel *cp; 3639 int channel; 3640 3641 printf("\n%s: bus-master DMA support present", 3642 sc->sc_wdcdev.sc_dev.dv_xname); 3643 pciide_mapreg_dma(sc, pa); 3644 printf("\n"); 3645 sc->sc_wdcdev.cap = WDC_CAPABILITY_DATA16 | WDC_CAPABILITY_DATA32 | 3646 WDC_CAPABILITY_MODE; 3647 if (sc->sc_dma_ok) { 3648 sc->sc_wdcdev.cap |= WDC_CAPABILITY_DMA | WDC_CAPABILITY_IRQACK; 3649 sc->sc_wdcdev.cap |= WDC_CAPABILITY_UDMA; 3650 sc->sc_wdcdev.UDMA_cap = 6; 3651 sc->sc_wdcdev.irqack = pciide_irqack; 3652 } 3653 3654 sc->sc_wdcdev.channels = sc->wdc_chanarray; 3655 sc->sc_wdcdev.nchannels = PCIIDE_NUM_CHANNELS; 3656 sc->sc_wdcdev.PIO_cap = 4; 3657 sc->sc_wdcdev.DMA_cap = 2; 3658 sc->sc_wdcdev.set_modes = cmd680_setup_channel; 3659 3660 pciide_pci_write(sc->sc_pc, sc->sc_tag, 0x80, 0x00); 3661 pciide_pci_write(sc->sc_pc, sc->sc_tag, 0x84, 0x00); 3662 pciide_pci_write(sc->sc_pc, sc->sc_tag, 0x8a, 3663 pciide_pci_read(sc->sc_pc, sc->sc_tag, 0x8a) | 0x01); 3664 for (channel = 0; channel < sc->sc_wdcdev.nchannels; channel++) { 3665 cp = &sc->pciide_channels[channel]; 3666 cmd680_channel_map(pa, sc, channel); 3667 if (cp->hw_ok == 0) 3668 continue; 3669 cmd680_setup_channel(&cp->wdc_channel); 3670 } 3671 } 3672 3673 void 3674 cmd680_channel_map(struct pci_attach_args *pa, struct pciide_softc *sc, 3675 int channel) 3676 { 3677 struct pciide_channel *cp = &sc->pciide_channels[channel]; 3678 bus_size_t cmdsize, ctlsize; 3679 int interface, i, reg; 3680 static const u_int8_t init_val[] = 3681 { 0x8a, 0x32, 0x8a, 0x32, 0x8a, 0x32, 3682 0x92, 0x43, 0x92, 0x43, 0x09, 0x40, 0x09, 0x40 }; 3683 3684 if (PCI_SUBCLASS(pa->pa_class) != PCI_SUBCLASS_MASS_STORAGE_IDE) { 3685 interface = PCIIDE_INTERFACE_SETTABLE(0) | 3686 PCIIDE_INTERFACE_SETTABLE(1); 3687 interface |= PCIIDE_INTERFACE_PCI(0) | 3688 PCIIDE_INTERFACE_PCI(1); 3689 } else { 3690 interface = PCI_INTERFACE(pa->pa_class); 3691 } 3692 3693 sc->wdc_chanarray[channel] = &cp->wdc_channel; 3694 cp->name = PCIIDE_CHANNEL_NAME(channel); 3695 cp->wdc_channel.channel = channel; 3696 cp->wdc_channel.wdc = &sc->sc_wdcdev; 3697 3698 cp->wdc_channel.ch_queue = 3699 malloc(sizeof(struct channel_queue), M_DEVBUF, M_NOWAIT); 3700 if (cp->wdc_channel.ch_queue == NULL) { 3701 printf("%s %s: " 3702 "can't allocate memory for command queue", 3703 sc->sc_wdcdev.sc_dev.dv_xname, cp->name); 3704 return; 3705 } 3706 3707 /* XXX */ 3708 reg = 0xa2 + channel * 16; 3709 for (i = 0; i < sizeof(init_val); i++) 3710 pciide_pci_write(sc->sc_pc, sc->sc_tag, reg + i, init_val[i]); 3711 3712 printf("%s: %s %s to %s mode\n", 3713 sc->sc_wdcdev.sc_dev.dv_xname, cp->name, 3714 (interface & PCIIDE_INTERFACE_SETTABLE(channel)) ? 3715 "configured" : "wired", 3716 (interface & PCIIDE_INTERFACE_PCI(channel)) ? 3717 "native-PCI" : "compatibility"); 3718 3719 pciide_mapchan(pa, cp, interface, &cmdsize, &ctlsize, pciide_pci_intr); 3720 if (cp->hw_ok == 0) 3721 return; 3722 pciide_map_compat_intr(pa, cp, channel, interface); 3723 } 3724 3725 void 3726 cmd680_setup_channel(struct channel_softc *chp) 3727 { 3728 struct ata_drive_datas *drvp; 3729 u_int8_t mode, off, scsc; 3730 u_int16_t val; 3731 u_int32_t idedma_ctl; 3732 int drive; 3733 struct pciide_channel *cp = (struct pciide_channel *)chp; 3734 struct pciide_softc *sc = (struct pciide_softc *)cp->wdc_channel.wdc; 3735 pci_chipset_tag_t pc = sc->sc_pc; 3736 pcitag_t pa = sc->sc_tag; 3737 static const u_int8_t udma2_tbl[] = 3738 { 0x0f, 0x0b, 0x07, 0x06, 0x03, 0x02, 0x01 }; 3739 static const u_int8_t udma_tbl[] = 3740 { 0x0c, 0x07, 0x05, 0x04, 0x02, 0x01, 0x00 }; 3741 static const u_int16_t dma_tbl[] = 3742 { 0x2208, 0x10c2, 0x10c1 }; 3743 static const u_int16_t pio_tbl[] = 3744 { 0x328a, 0x2283, 0x1104, 0x10c3, 0x10c1 }; 3745 3746 idedma_ctl = 0; 3747 pciide_channel_dma_setup(cp); 3748 mode = pciide_pci_read(pc, pa, 0x80 + chp->channel * 4); 3749 3750 for (drive = 0; drive < 2; drive++) { 3751 drvp = &chp->ch_drive[drive]; 3752 /* If no drive, skip */ 3753 if ((drvp->drive_flags & DRIVE) == 0) 3754 continue; 3755 mode &= ~(0x03 << (drive * 4)); 3756 if (drvp->drive_flags & DRIVE_UDMA) { 3757 drvp->drive_flags &= ~DRIVE_DMA; 3758 off = 0xa0 + chp->channel * 16; 3759 if (drvp->UDMA_mode > 2 && 3760 (pciide_pci_read(pc, pa, off) & 0x01) == 0) 3761 drvp->UDMA_mode = 2; 3762 scsc = pciide_pci_read(pc, pa, 0x8a); 3763 if (drvp->UDMA_mode == 6 && (scsc & 0x30) == 0) { 3764 pciide_pci_write(pc, pa, 0x8a, scsc | 0x01); 3765 scsc = pciide_pci_read(pc, pa, 0x8a); 3766 if ((scsc & 0x30) == 0) 3767 drvp->UDMA_mode = 5; 3768 } 3769 mode |= 0x03 << (drive * 4); 3770 off = 0xac + chp->channel * 16 + drive * 2; 3771 val = pciide_pci_read(pc, pa, off) & ~0x3f; 3772 if (scsc & 0x30) 3773 val |= udma2_tbl[drvp->UDMA_mode]; 3774 else 3775 val |= udma_tbl[drvp->UDMA_mode]; 3776 pciide_pci_write(pc, pa, off, val); 3777 idedma_ctl |= IDEDMA_CTL_DRV_DMA(drive); 3778 } else if (drvp->drive_flags & DRIVE_DMA) { 3779 mode |= 0x02 << (drive * 4); 3780 off = 0xa8 + chp->channel * 16 + drive * 2; 3781 val = dma_tbl[drvp->DMA_mode]; 3782 pciide_pci_write(pc, pa, off, val & 0xff); 3783 pciide_pci_write(pc, pa, off, val >> 8); 3784 idedma_ctl |= IDEDMA_CTL_DRV_DMA(drive); 3785 } else { 3786 mode |= 0x01 << (drive * 4); 3787 off = 0xa4 + chp->channel * 16 + drive * 2; 3788 val = pio_tbl[drvp->PIO_mode]; 3789 pciide_pci_write(pc, pa, off, val & 0xff); 3790 pciide_pci_write(pc, pa, off, val >> 8); 3791 } 3792 } 3793 3794 pciide_pci_write(pc, pa, 0x80 + chp->channel * 4, mode); 3795 if (idedma_ctl != 0) { 3796 /* Add software bits in status register */ 3797 bus_space_write_1(sc->sc_dma_iot, sc->sc_dma_ioh, 3798 IDEDMA_CTL(chp->channel), 3799 idedma_ctl); 3800 } 3801 pciide_print_modes(cp); 3802 } 3803 3804 /* 3805 * When the Silicon Image 3112 retries a PCI memory read command, 3806 * it may retry it as a memory read multiple command under some 3807 * circumstances. This can totally confuse some PCI controllers, 3808 * so ensure that it will never do this by making sure that the 3809 * Read Threshold (FIFO Read Request Control) field of the FIFO 3810 * Valid Byte Count and Control registers for both channels (BA5 3811 * offset 0x40 and 0x44) are set to be at least as large as the 3812 * cacheline size register. 3813 */ 3814 void 3815 sii_fixup_cacheline(struct pciide_softc *sc, struct pci_attach_args *pa) 3816 { 3817 pcireg_t cls, reg40, reg44; 3818 3819 cls = pci_conf_read(pa->pa_pc, pa->pa_tag, PCI_BHLC_REG); 3820 cls = (cls >> PCI_CACHELINE_SHIFT) & PCI_CACHELINE_MASK; 3821 cls *= 4; 3822 if (cls > 224) { 3823 cls = pci_conf_read(pa->pa_pc, pa->pa_tag, PCI_BHLC_REG); 3824 cls &= ~(PCI_CACHELINE_MASK << PCI_CACHELINE_SHIFT); 3825 cls |= ((224/4) << PCI_CACHELINE_SHIFT); 3826 pci_conf_write(pa->pa_pc, pa->pa_tag, PCI_BHLC_REG, cls); 3827 cls = 224; 3828 } 3829 if (cls < 32) 3830 cls = 32; 3831 cls = (cls + 31) / 32; 3832 reg40 = ba5_read_4(sc, 0x40); 3833 reg44 = ba5_read_4(sc, 0x44); 3834 if ((reg40 & 0x7) < cls) 3835 ba5_write_4(sc, 0x40, (reg40 & ~0x07) | cls); 3836 if ((reg44 & 0x7) < cls) 3837 ba5_write_4(sc, 0x44, (reg44 & ~0x07) | cls); 3838 } 3839 3840 void 3841 sii3112_chip_map(struct pciide_softc *sc, struct pci_attach_args *pa) 3842 { 3843 struct pciide_channel *cp; 3844 bus_size_t cmdsize, ctlsize; 3845 pcireg_t interface, scs_cmd, cfgctl; 3846 int channel; 3847 struct pciide_satalink *sl = sc->sc_cookie; 3848 3849 /* Allocate memory for private data */ 3850 sc->sc_cookie = malloc(sizeof(*sl), M_DEVBUF, M_NOWAIT | M_ZERO); 3851 sl = sc->sc_cookie; 3852 3853 #define SII3112_RESET_BITS \ 3854 (SCS_CMD_PBM_RESET | SCS_CMD_ARB_RESET | \ 3855 SCS_CMD_FF1_RESET | SCS_CMD_FF0_RESET | \ 3856 SCS_CMD_IDE1_RESET | SCS_CMD_IDE0_RESET) 3857 3858 /* 3859 * Reset everything and then unblock all of the interrupts. 3860 */ 3861 scs_cmd = pci_conf_read(pa->pa_pc, pa->pa_tag, SII3112_SCS_CMD); 3862 pci_conf_write(pa->pa_pc, pa->pa_tag, SII3112_SCS_CMD, 3863 scs_cmd | SII3112_RESET_BITS); 3864 delay(50 * 1000); 3865 pci_conf_write(pa->pa_pc, pa->pa_tag, SII3112_SCS_CMD, 3866 scs_cmd & SCS_CMD_BA5_EN); 3867 delay(50 * 1000); 3868 3869 if (scs_cmd & SCS_CMD_BA5_EN) { 3870 if (pci_mapreg_map(pa, PCI_MAPREG_START + 0x14, 3871 PCI_MAPREG_TYPE_MEM | 3872 PCI_MAPREG_MEM_TYPE_32BIT, 0, 3873 &sl->ba5_st, &sl->ba5_sh, 3874 NULL, NULL, 0) != 0) 3875 printf(": unable to map BA5 register space\n"); 3876 else 3877 sl->ba5_en = 1; 3878 } else { 3879 cfgctl = pci_conf_read(pa->pa_pc, pa->pa_tag, 3880 SII3112_PCI_CFGCTL); 3881 pci_conf_write(pa->pa_pc, pa->pa_tag, SII3112_PCI_CFGCTL, 3882 cfgctl | CFGCTL_BA5INDEN); 3883 } 3884 3885 printf(": DMA"); 3886 pciide_mapreg_dma(sc, pa); 3887 printf("\n"); 3888 3889 /* 3890 * Rev. <= 0x01 of the 3112 have a bug that can cause data 3891 * corruption if DMA transfers cross an 8K boundary. This is 3892 * apparently hard to tickle, but we'll go ahead and play it 3893 * safe. 3894 */ 3895 if (sc->sc_rev <= 0x01) { 3896 sc->sc_dma_maxsegsz = 8192; 3897 sc->sc_dma_boundary = 8192; 3898 } 3899 3900 sii_fixup_cacheline(sc, pa); 3901 3902 sc->sc_wdcdev.cap |= WDC_CAPABILITY_DATA16 | WDC_CAPABILITY_DATA32; 3903 sc->sc_wdcdev.PIO_cap = 4; 3904 if (sc->sc_dma_ok) { 3905 sc->sc_wdcdev.cap |= WDC_CAPABILITY_DMA | WDC_CAPABILITY_UDMA; 3906 sc->sc_wdcdev.cap |= WDC_CAPABILITY_IRQACK; 3907 sc->sc_wdcdev.irqack = pciide_irqack; 3908 sc->sc_wdcdev.DMA_cap = 2; 3909 sc->sc_wdcdev.UDMA_cap = 6; 3910 } 3911 sc->sc_wdcdev.set_modes = sii3112_setup_channel; 3912 3913 /* We can use SControl and SStatus to probe for drives. */ 3914 sc->sc_wdcdev.drv_probe = sii3112_drv_probe; 3915 3916 sc->sc_wdcdev.channels = sc->wdc_chanarray; 3917 sc->sc_wdcdev.nchannels = PCIIDE_NUM_CHANNELS; 3918 3919 /* 3920 * The 3112 either identifies itself as a RAID storage device 3921 * or a Misc storage device. Fake up the interface bits for 3922 * what our driver expects. 3923 */ 3924 if (PCI_SUBCLASS(pa->pa_class) == PCI_SUBCLASS_MASS_STORAGE_IDE) { 3925 interface = PCI_INTERFACE(pa->pa_class); 3926 } else { 3927 interface = PCIIDE_INTERFACE_BUS_MASTER_DMA | 3928 PCIIDE_INTERFACE_PCI(0) | PCIIDE_INTERFACE_PCI(1); 3929 } 3930 3931 for (channel = 0; channel < sc->sc_wdcdev.nchannels; channel++) { 3932 cp = &sc->pciide_channels[channel]; 3933 if (pciide_chansetup(sc, channel, interface) == 0) 3934 continue; 3935 pciide_mapchan(pa, cp, interface, &cmdsize, &ctlsize, 3936 pciide_pci_intr); 3937 if (cp->hw_ok == 0) 3938 continue; 3939 sc->sc_wdcdev.set_modes(&cp->wdc_channel); 3940 } 3941 } 3942 3943 void 3944 sii3112_setup_channel(struct channel_softc *chp) 3945 { 3946 struct ata_drive_datas *drvp; 3947 int drive; 3948 u_int32_t idedma_ctl, dtm; 3949 struct pciide_channel *cp = (struct pciide_channel *)chp; 3950 struct pciide_softc *sc = (struct pciide_softc *)cp->wdc_channel.wdc; 3951 3952 /* setup DMA if needed */ 3953 pciide_channel_dma_setup(cp); 3954 3955 idedma_ctl = 0; 3956 dtm = 0; 3957 3958 for (drive = 0; drive < 2; drive++) { 3959 drvp = &chp->ch_drive[drive]; 3960 /* If no drive, skip */ 3961 if ((drvp->drive_flags & DRIVE) == 0) 3962 continue; 3963 if (drvp->drive_flags & DRIVE_UDMA) { 3964 /* use Ultra/DMA */ 3965 drvp->drive_flags &= ~DRIVE_DMA; 3966 idedma_ctl |= IDEDMA_CTL_DRV_DMA(drive); 3967 dtm |= DTM_IDEx_DMA; 3968 } else if (drvp->drive_flags & DRIVE_DMA) { 3969 idedma_ctl |= IDEDMA_CTL_DRV_DMA(drive); 3970 dtm |= DTM_IDEx_DMA; 3971 } else { 3972 dtm |= DTM_IDEx_PIO; 3973 } 3974 } 3975 3976 /* 3977 * Nothing to do to setup modes; it is meaningless in S-ATA 3978 * (but many S-ATA drives still want to get the SET_FEATURE 3979 * command). 3980 */ 3981 if (idedma_ctl != 0) { 3982 /* Add software bits in status register */ 3983 PCIIDE_DMACTL_WRITE(sc, chp->channel, idedma_ctl); 3984 } 3985 BA5_WRITE_4(sc, chp->channel, ba5_IDE_DTM, dtm); 3986 pciide_print_modes(cp); 3987 } 3988 3989 void 3990 sii3112_drv_probe(struct channel_softc *chp) 3991 { 3992 struct pciide_channel *cp = (struct pciide_channel *)chp; 3993 struct pciide_softc *sc = (struct pciide_softc *)cp->wdc_channel.wdc; 3994 uint32_t scontrol, sstatus; 3995 uint8_t scnt, sn, cl, ch; 3996 int i, s; 3997 3998 /* XXX This should be done by other code. */ 3999 for (i = 0; i < 2; i++) { 4000 chp->ch_drive[i].chnl_softc = chp; 4001 chp->ch_drive[i].drive = i; 4002 } 4003 4004 /* 4005 * The 3112 is a 2-port part, and only has one drive per channel 4006 * (each port emulates a master drive). 4007 * 4008 * The 3114 is similar, but has 4 channels. 4009 */ 4010 4011 /* 4012 * Request communication initialization sequence, any speed. 4013 * Performing this is the equivalent of an ATA Reset. 4014 */ 4015 scontrol = SControl_DET_INIT | SControl_SPD_ANY; 4016 4017 /* 4018 * XXX We don't yet support SATA power management; disable all 4019 * power management state transitions. 4020 */ 4021 scontrol |= SControl_IPM_NONE; 4022 4023 BA5_WRITE_4(sc, chp->channel, ba5_SControl, scontrol); 4024 delay(50 * 1000); 4025 scontrol &= ~SControl_DET_INIT; 4026 BA5_WRITE_4(sc, chp->channel, ba5_SControl, scontrol); 4027 delay(50 * 1000); 4028 4029 sstatus = BA5_READ_4(sc, chp->channel, ba5_SStatus); 4030 #if 0 4031 printf("%s: port %d: SStatus=0x%08x, SControl=0x%08x\n", 4032 sc->sc_wdcdev.sc_dev.dv_xname, chp->channel, sstatus, 4033 BA5_READ_4(sc, chp->channel, ba5_SControl)); 4034 #endif 4035 switch (sstatus & SStatus_DET_mask) { 4036 case SStatus_DET_NODEV: 4037 /* No device; be silent. */ 4038 break; 4039 4040 case SStatus_DET_DEV_NE: 4041 printf("%s: port %d: device connected, but " 4042 "communication not established\n", 4043 sc->sc_wdcdev.sc_dev.dv_xname, chp->channel); 4044 break; 4045 4046 case SStatus_DET_OFFLINE: 4047 printf("%s: port %d: PHY offline\n", 4048 sc->sc_wdcdev.sc_dev.dv_xname, chp->channel); 4049 break; 4050 4051 case SStatus_DET_DEV: 4052 /* 4053 * XXX ATAPI detection doesn't currently work. Don't 4054 * XXX know why. But, it's not like the standard method 4055 * XXX can detect an ATAPI device connected via a SATA/PATA 4056 * XXX bridge, so at least this is no worse. --thorpej 4057 */ 4058 if (chp->_vtbl != NULL) 4059 CHP_WRITE_REG(chp, wdr_sdh, WDSD_IBM | (0 << 4)); 4060 else 4061 bus_space_write_1(chp->cmd_iot, chp->cmd_ioh, 4062 wdr_sdh & _WDC_REGMASK, WDSD_IBM | (0 << 4)); 4063 delay(10); /* 400ns delay */ 4064 /* Save register contents. */ 4065 if (chp->_vtbl != NULL) { 4066 scnt = CHP_READ_REG(chp, wdr_seccnt); 4067 sn = CHP_READ_REG(chp, wdr_sector); 4068 cl = CHP_READ_REG(chp, wdr_cyl_lo); 4069 ch = CHP_READ_REG(chp, wdr_cyl_hi); 4070 } else { 4071 scnt = bus_space_read_1(chp->cmd_iot, 4072 chp->cmd_ioh, wdr_seccnt & _WDC_REGMASK); 4073 sn = bus_space_read_1(chp->cmd_iot, 4074 chp->cmd_ioh, wdr_sector & _WDC_REGMASK); 4075 cl = bus_space_read_1(chp->cmd_iot, 4076 chp->cmd_ioh, wdr_cyl_lo & _WDC_REGMASK); 4077 ch = bus_space_read_1(chp->cmd_iot, 4078 chp->cmd_ioh, wdr_cyl_hi & _WDC_REGMASK); 4079 } 4080 #if 0 4081 printf("%s: port %d: scnt=0x%x sn=0x%x cl=0x%x ch=0x%x\n", 4082 sc->sc_wdcdev.sc_dev.dv_xname, chp->channel, 4083 scnt, sn, cl, ch); 4084 #endif 4085 /* 4086 * scnt and sn are supposed to be 0x1 for ATAPI, but in some 4087 * cases we get wrong values here, so ignore it. 4088 */ 4089 s = splbio(); 4090 if (cl == 0x14 && ch == 0xeb) 4091 chp->ch_drive[0].drive_flags |= DRIVE_ATAPI; 4092 else 4093 chp->ch_drive[0].drive_flags |= DRIVE_ATA; 4094 splx(s); 4095 4096 printf("%s: port %d: device present", 4097 sc->sc_wdcdev.sc_dev.dv_xname, chp->channel); 4098 switch ((sstatus & SStatus_SPD_mask) >> SStatus_SPD_shift) { 4099 case 1: 4100 printf(", speed: 1.5Gb/s"); 4101 break; 4102 case 2: 4103 printf(", speed: 3.0Gb/s"); 4104 break; 4105 } 4106 printf("\n"); 4107 break; 4108 4109 default: 4110 printf("%s: port %d: unknown SStatus: 0x%08x\n", 4111 sc->sc_wdcdev.sc_dev.dv_xname, chp->channel, sstatus); 4112 } 4113 } 4114 4115 void 4116 sii3114_chip_map(struct pciide_softc *sc, struct pci_attach_args *pa) 4117 { 4118 struct pciide_channel *cp; 4119 pcireg_t scs_cmd; 4120 pci_intr_handle_t intrhandle; 4121 const char *intrstr; 4122 int channel; 4123 struct pciide_satalink *sl = sc->sc_cookie; 4124 4125 /* Allocate memory for private data */ 4126 sc->sc_cookie = malloc(sizeof(*sl), M_DEVBUF, M_NOWAIT | M_ZERO); 4127 sl = sc->sc_cookie; 4128 4129 #define SII3114_RESET_BITS \ 4130 (SCS_CMD_PBM_RESET | SCS_CMD_ARB_RESET | \ 4131 SCS_CMD_FF1_RESET | SCS_CMD_FF0_RESET | \ 4132 SCS_CMD_FF3_RESET | SCS_CMD_FF2_RESET | \ 4133 SCS_CMD_IDE1_RESET | SCS_CMD_IDE0_RESET | \ 4134 SCS_CMD_IDE3_RESET | SCS_CMD_IDE2_RESET) 4135 4136 /* 4137 * Reset everything and then unblock all of the interrupts. 4138 */ 4139 scs_cmd = pci_conf_read(pa->pa_pc, pa->pa_tag, SII3112_SCS_CMD); 4140 pci_conf_write(pa->pa_pc, pa->pa_tag, SII3112_SCS_CMD, 4141 scs_cmd | SII3114_RESET_BITS); 4142 delay(50 * 1000); 4143 pci_conf_write(pa->pa_pc, pa->pa_tag, SII3112_SCS_CMD, 4144 scs_cmd & SCS_CMD_M66EN); 4145 delay(50 * 1000); 4146 4147 /* 4148 * On the 3114, the BA5 register space is always enabled. In 4149 * order to use the 3114 in any sane way, we must use this BA5 4150 * register space, and so we consider it an error if we cannot 4151 * map it. 4152 * 4153 * As a consequence of using BA5, our register mapping is different 4154 * from a normal PCI IDE controller's, and so we are unable to use 4155 * most of the common PCI IDE register mapping functions. 4156 */ 4157 if (pci_mapreg_map(pa, PCI_MAPREG_START + 0x14, 4158 PCI_MAPREG_TYPE_MEM | 4159 PCI_MAPREG_MEM_TYPE_32BIT, 0, 4160 &sl->ba5_st, &sl->ba5_sh, 4161 NULL, NULL, 0) != 0) { 4162 printf(": unable to map BA5 register space\n"); 4163 return; 4164 } 4165 sl->ba5_en = 1; 4166 4167 /* 4168 * Set the Interrupt Steering bit in the IDEDMA_CMD register of 4169 * channel 2. This is required at all times for proper operation 4170 * when using the BA5 register space (otherwise interrupts from 4171 * all 4 channels won't work). 4172 */ 4173 BA5_WRITE_4(sc, 2, ba5_IDEDMA_CMD, IDEDMA_CMD_INT_STEER); 4174 4175 printf(": DMA"); 4176 sii3114_mapreg_dma(sc, pa); 4177 printf("\n"); 4178 4179 sii_fixup_cacheline(sc, pa); 4180 4181 sc->sc_wdcdev.cap |= WDC_CAPABILITY_DATA16 | WDC_CAPABILITY_DATA32; 4182 sc->sc_wdcdev.PIO_cap = 4; 4183 if (sc->sc_dma_ok) { 4184 sc->sc_wdcdev.cap |= WDC_CAPABILITY_DMA | WDC_CAPABILITY_UDMA; 4185 sc->sc_wdcdev.cap |= WDC_CAPABILITY_IRQACK; 4186 sc->sc_wdcdev.irqack = pciide_irqack; 4187 sc->sc_wdcdev.DMA_cap = 2; 4188 sc->sc_wdcdev.UDMA_cap = 6; 4189 } 4190 sc->sc_wdcdev.set_modes = sii3112_setup_channel; 4191 4192 /* We can use SControl and SStatus to probe for drives. */ 4193 sc->sc_wdcdev.drv_probe = sii3112_drv_probe; 4194 4195 sc->sc_wdcdev.channels = sc->wdc_chanarray; 4196 sc->sc_wdcdev.nchannels = 4; 4197 4198 /* Map and establish the interrupt handler. */ 4199 if (pci_intr_map(pa, &intrhandle) != 0) { 4200 printf("%s: couldn't map native-PCI interrupt\n", 4201 sc->sc_wdcdev.sc_dev.dv_xname); 4202 return; 4203 } 4204 intrstr = pci_intr_string(pa->pa_pc, intrhandle); 4205 sc->sc_pci_ih = pci_intr_establish(pa->pa_pc, intrhandle, IPL_BIO, 4206 /* XXX */ 4207 pciide_pci_intr, sc, 4208 sc->sc_wdcdev.sc_dev.dv_xname); 4209 if (sc->sc_pci_ih != NULL) { 4210 printf("%s: using %s for native-PCI interrupt\n", 4211 sc->sc_wdcdev.sc_dev.dv_xname, 4212 intrstr ? intrstr : "unknown interrupt"); 4213 } else { 4214 printf("%s: couldn't establish native-PCI interrupt", 4215 sc->sc_wdcdev.sc_dev.dv_xname); 4216 if (intrstr != NULL) 4217 printf(" at %s", intrstr); 4218 printf("\n"); 4219 return; 4220 } 4221 4222 for (channel = 0; channel < sc->sc_wdcdev.nchannels; channel++) { 4223 cp = &sc->pciide_channels[channel]; 4224 if (sii3114_chansetup(sc, channel) == 0) 4225 continue; 4226 sii3114_mapchan(cp); 4227 if (cp->hw_ok == 0) 4228 continue; 4229 sc->sc_wdcdev.set_modes(&cp->wdc_channel); 4230 } 4231 } 4232 4233 void 4234 sii3114_mapreg_dma(struct pciide_softc *sc, struct pci_attach_args *pa) 4235 { 4236 int chan, reg; 4237 bus_size_t size; 4238 struct pciide_satalink *sl = sc->sc_cookie; 4239 4240 sc->sc_wdcdev.dma_arg = sc; 4241 sc->sc_wdcdev.dma_init = pciide_dma_init; 4242 sc->sc_wdcdev.dma_start = pciide_dma_start; 4243 sc->sc_wdcdev.dma_finish = pciide_dma_finish; 4244 4245 /* 4246 * Slice off a subregion of BA5 for each of the channel's DMA 4247 * registers. 4248 */ 4249 4250 sc->sc_dma_iot = sl->ba5_st; 4251 for (chan = 0; chan < 4; chan++) { 4252 for (reg = 0; reg < IDEDMA_NREGS; reg++) { 4253 size = 4; 4254 if (size > (IDEDMA_SCH_OFFSET - reg)) 4255 size = IDEDMA_SCH_OFFSET - reg; 4256 if (bus_space_subregion(sl->ba5_st, 4257 sl->ba5_sh, 4258 satalink_ba5_regmap[chan].ba5_IDEDMA_CMD + reg, 4259 size, &sl->regs[chan].dma_iohs[reg]) != 0) { 4260 sc->sc_dma_ok = 0; 4261 printf(": can't subregion offset " 4262 "%lu size %lu", 4263 (u_long) satalink_ba5_regmap[ 4264 chan].ba5_IDEDMA_CMD + reg, 4265 (u_long) size); 4266 return; 4267 } 4268 } 4269 } 4270 4271 sc->sc_dmacmd_read = sii3114_dmacmd_read; 4272 sc->sc_dmacmd_write = sii3114_dmacmd_write; 4273 sc->sc_dmactl_read = sii3114_dmactl_read; 4274 sc->sc_dmactl_write = sii3114_dmactl_write; 4275 sc->sc_dmatbl_write = sii3114_dmatbl_write; 4276 4277 /* DMA registers all set up! */ 4278 sc->sc_dmat = pa->pa_dmat; 4279 sc->sc_dma_ok = 1; 4280 } 4281 4282 int 4283 sii3114_chansetup(struct pciide_softc *sc, int channel) 4284 { 4285 static const char *channel_names[] = { 4286 "port 0", 4287 "port 1", 4288 "port 2", 4289 "port 3", 4290 }; 4291 struct pciide_channel *cp = &sc->pciide_channels[channel]; 4292 4293 sc->wdc_chanarray[channel] = &cp->wdc_channel; 4294 4295 /* 4296 * We must always keep the Interrupt Steering bit set in channel 2's 4297 * IDEDMA_CMD register. 4298 */ 4299 if (channel == 2) 4300 cp->idedma_cmd = IDEDMA_CMD_INT_STEER; 4301 4302 cp->name = channel_names[channel]; 4303 cp->wdc_channel.channel = channel; 4304 cp->wdc_channel.wdc = &sc->sc_wdcdev; 4305 cp->wdc_channel.ch_queue = 4306 malloc(sizeof(struct channel_queue), M_DEVBUF, M_NOWAIT); 4307 if (cp->wdc_channel.ch_queue == NULL) { 4308 printf("%s %s channel: " 4309 "can't allocate memory for command queue", 4310 sc->sc_wdcdev.sc_dev.dv_xname, cp->name); 4311 return (0); 4312 } 4313 return (1); 4314 } 4315 4316 void 4317 sii3114_mapchan(struct pciide_channel *cp) 4318 { 4319 struct channel_softc *wdc_cp = &cp->wdc_channel; 4320 struct pciide_softc *sc = (struct pciide_softc *)cp->wdc_channel.wdc; 4321 struct pciide_satalink *sl = sc->sc_cookie; 4322 int chan = wdc_cp->channel; 4323 int i; 4324 4325 cp->hw_ok = 0; 4326 cp->compat = 0; 4327 cp->ih = sc->sc_pci_ih; 4328 4329 sl->regs[chan].cmd_iot = sl->ba5_st; 4330 if (bus_space_subregion(sl->ba5_st, sl->ba5_sh, 4331 satalink_ba5_regmap[chan].ba5_IDE_TF0, 4332 9, &sl->regs[chan].cmd_baseioh) != 0) { 4333 printf("%s: couldn't subregion %s cmd base\n", 4334 sc->sc_wdcdev.sc_dev.dv_xname, cp->name); 4335 return; 4336 } 4337 4338 sl->regs[chan].ctl_iot = sl->ba5_st; 4339 if (bus_space_subregion(sl->ba5_st, sl->ba5_sh, 4340 satalink_ba5_regmap[chan].ba5_IDE_TF8, 4341 1, &cp->ctl_baseioh) != 0) { 4342 printf("%s: couldn't subregion %s ctl base\n", 4343 sc->sc_wdcdev.sc_dev.dv_xname, cp->name); 4344 return; 4345 } 4346 sl->regs[chan].ctl_ioh = cp->ctl_baseioh; 4347 4348 for (i = 0; i < WDC_NREG; i++) { 4349 if (bus_space_subregion(sl->regs[chan].cmd_iot, 4350 sl->regs[chan].cmd_baseioh, 4351 i, i == 0 ? 4 : 1, 4352 &sl->regs[chan].cmd_iohs[i]) != 0) { 4353 printf("%s: couldn't subregion %s channel " 4354 "cmd regs\n", 4355 sc->sc_wdcdev.sc_dev.dv_xname, cp->name); 4356 return; 4357 } 4358 } 4359 sl->regs[chan].cmd_iohs[wdr_status & _WDC_REGMASK] = 4360 sl->regs[chan].cmd_iohs[wdr_command & _WDC_REGMASK]; 4361 sl->regs[chan].cmd_iohs[wdr_features & _WDC_REGMASK] = 4362 sl->regs[chan].cmd_iohs[wdr_error & _WDC_REGMASK]; 4363 wdc_cp->data32iot = wdc_cp->cmd_iot = sl->regs[chan].cmd_iot; 4364 wdc_cp->data32ioh = wdc_cp->cmd_ioh = sl->regs[chan].cmd_iohs[0]; 4365 wdc_cp->_vtbl = &wdc_sii3114_vtbl; 4366 wdcattach(wdc_cp); 4367 cp->hw_ok = 1; 4368 } 4369 4370 u_int8_t 4371 sii3114_read_reg(struct channel_softc *chp, enum wdc_regs reg) 4372 { 4373 struct pciide_channel *cp = (struct pciide_channel *)chp; 4374 struct pciide_softc *sc = (struct pciide_softc *)cp->wdc_channel.wdc; 4375 struct pciide_satalink *sl = sc->sc_cookie; 4376 4377 if (reg & _WDC_AUX) 4378 return (bus_space_read_1(sl->regs[chp->channel].ctl_iot, 4379 sl->regs[chp->channel].ctl_ioh, reg & _WDC_REGMASK)); 4380 else 4381 return (bus_space_read_1(sl->regs[chp->channel].cmd_iot, 4382 sl->regs[chp->channel].cmd_iohs[reg & _WDC_REGMASK], 0)); 4383 } 4384 4385 void 4386 sii3114_write_reg(struct channel_softc *chp, enum wdc_regs reg, u_int8_t val) 4387 { 4388 struct pciide_channel *cp = (struct pciide_channel *)chp; 4389 struct pciide_softc *sc = (struct pciide_softc *)cp->wdc_channel.wdc; 4390 struct pciide_satalink *sl = sc->sc_cookie; 4391 4392 if (reg & _WDC_AUX) 4393 bus_space_write_1(sl->regs[chp->channel].ctl_iot, 4394 sl->regs[chp->channel].ctl_ioh, reg & _WDC_REGMASK, val); 4395 else 4396 bus_space_write_1(sl->regs[chp->channel].cmd_iot, 4397 sl->regs[chp->channel].cmd_iohs[reg & _WDC_REGMASK], 4398 0, val); 4399 } 4400 4401 u_int8_t 4402 sii3114_dmacmd_read(struct pciide_softc *sc, int chan) 4403 { 4404 struct pciide_satalink *sl = sc->sc_cookie; 4405 4406 return (bus_space_read_1(sc->sc_dma_iot, 4407 sl->regs[chan].dma_iohs[IDEDMA_CMD(0)], 0)); 4408 } 4409 4410 void 4411 sii3114_dmacmd_write(struct pciide_softc *sc, int chan, u_int8_t val) 4412 { 4413 struct pciide_satalink *sl = sc->sc_cookie; 4414 4415 bus_space_write_1(sc->sc_dma_iot, 4416 sl->regs[chan].dma_iohs[IDEDMA_CMD(0)], 0, val); 4417 } 4418 4419 u_int8_t 4420 sii3114_dmactl_read(struct pciide_softc *sc, int chan) 4421 { 4422 struct pciide_satalink *sl = sc->sc_cookie; 4423 4424 return (bus_space_read_1(sc->sc_dma_iot, 4425 sl->regs[chan].dma_iohs[IDEDMA_CTL(0)], 0)); 4426 } 4427 4428 void 4429 sii3114_dmactl_write(struct pciide_softc *sc, int chan, u_int8_t val) 4430 { 4431 struct pciide_satalink *sl = sc->sc_cookie; 4432 4433 bus_space_write_1(sc->sc_dma_iot, 4434 sl->regs[chan].dma_iohs[IDEDMA_CTL(0)], 0, val); 4435 } 4436 4437 void 4438 sii3114_dmatbl_write(struct pciide_softc *sc, int chan, u_int32_t val) 4439 { 4440 struct pciide_satalink *sl = sc->sc_cookie; 4441 4442 bus_space_write_4(sc->sc_dma_iot, 4443 sl->regs[chan].dma_iohs[IDEDMA_TBL(0)], 0, val); 4444 } 4445 4446 void 4447 cy693_chip_map(struct pciide_softc *sc, struct pci_attach_args *pa) 4448 { 4449 struct pciide_channel *cp; 4450 pcireg_t interface = PCI_INTERFACE(pa->pa_class); 4451 bus_size_t cmdsize, ctlsize; 4452 struct pciide_cy *cy; 4453 4454 /* Allocate memory for private data */ 4455 sc->sc_cookie = malloc(sizeof(*cy), M_DEVBUF, M_NOWAIT | M_ZERO); 4456 cy = sc->sc_cookie; 4457 4458 /* 4459 * this chip has 2 PCI IDE functions, one for primary and one for 4460 * secondary. So we need to call pciide_mapregs_compat() with 4461 * the real channel 4462 */ 4463 if (pa->pa_function == 1) { 4464 cy->cy_compatchan = 0; 4465 } else if (pa->pa_function == 2) { 4466 cy->cy_compatchan = 1; 4467 } else { 4468 printf(": unexpected PCI function %d\n", pa->pa_function); 4469 return; 4470 } 4471 4472 if (interface & PCIIDE_INTERFACE_BUS_MASTER_DMA) { 4473 printf(": DMA"); 4474 pciide_mapreg_dma(sc, pa); 4475 } else { 4476 printf(": no DMA"); 4477 sc->sc_dma_ok = 0; 4478 } 4479 4480 cy->cy_handle = cy82c693_init(pa->pa_iot); 4481 if (cy->cy_handle == NULL) { 4482 printf(", (unable to map ctl registers)"); 4483 sc->sc_dma_ok = 0; 4484 } 4485 4486 sc->sc_wdcdev.cap = WDC_CAPABILITY_DATA16 | WDC_CAPABILITY_DATA32 | 4487 WDC_CAPABILITY_MODE; 4488 if (sc->sc_dma_ok) { 4489 sc->sc_wdcdev.cap |= WDC_CAPABILITY_DMA | WDC_CAPABILITY_IRQACK; 4490 sc->sc_wdcdev.irqack = pciide_irqack; 4491 } 4492 sc->sc_wdcdev.PIO_cap = 4; 4493 sc->sc_wdcdev.DMA_cap = 2; 4494 sc->sc_wdcdev.set_modes = cy693_setup_channel; 4495 4496 sc->sc_wdcdev.channels = sc->wdc_chanarray; 4497 sc->sc_wdcdev.nchannels = 1; 4498 4499 /* Only one channel for this chip; if we are here it's enabled */ 4500 cp = &sc->pciide_channels[0]; 4501 sc->wdc_chanarray[0] = &cp->wdc_channel; 4502 cp->name = PCIIDE_CHANNEL_NAME(0); 4503 cp->wdc_channel.channel = 0; 4504 cp->wdc_channel.wdc = &sc->sc_wdcdev; 4505 cp->wdc_channel.ch_queue = 4506 malloc(sizeof(struct channel_queue), M_DEVBUF, M_NOWAIT); 4507 if (cp->wdc_channel.ch_queue == NULL) { 4508 printf(": cannot allocate memory for command queue\n"); 4509 return; 4510 } 4511 printf(", %s %s to ", PCIIDE_CHANNEL_NAME(0), 4512 (interface & PCIIDE_INTERFACE_SETTABLE(0)) ? 4513 "configured" : "wired"); 4514 if (interface & PCIIDE_INTERFACE_PCI(0)) { 4515 printf("native-PCI\n"); 4516 cp->hw_ok = pciide_mapregs_native(pa, cp, &cmdsize, &ctlsize, 4517 pciide_pci_intr); 4518 } else { 4519 printf("compatibility\n"); 4520 cp->hw_ok = pciide_mapregs_compat(pa, cp, cy->cy_compatchan, 4521 &cmdsize, &ctlsize); 4522 } 4523 4524 cp->wdc_channel.data32iot = cp->wdc_channel.cmd_iot; 4525 cp->wdc_channel.data32ioh = cp->wdc_channel.cmd_ioh; 4526 pciide_map_compat_intr(pa, cp, cy->cy_compatchan, interface); 4527 if (cp->hw_ok == 0) 4528 return; 4529 wdcattach(&cp->wdc_channel); 4530 if (pciide_chan_candisable(cp)) { 4531 pci_conf_write(sc->sc_pc, sc->sc_tag, 4532 PCI_COMMAND_STATUS_REG, 0); 4533 } 4534 if (cp->hw_ok == 0) { 4535 pciide_unmap_compat_intr(pa, cp, cy->cy_compatchan, 4536 interface); 4537 return; 4538 } 4539 4540 WDCDEBUG_PRINT(("cy693_chip_map: old timings reg 0x%x\n", 4541 pci_conf_read(sc->sc_pc, sc->sc_tag, CY_CMD_CTRL)), DEBUG_PROBE); 4542 cy693_setup_channel(&cp->wdc_channel); 4543 WDCDEBUG_PRINT(("cy693_chip_map: new timings reg 0x%x\n", 4544 pci_conf_read(sc->sc_pc, sc->sc_tag, CY_CMD_CTRL)), DEBUG_PROBE); 4545 } 4546 4547 void 4548 cy693_setup_channel(struct channel_softc *chp) 4549 { 4550 struct ata_drive_datas *drvp; 4551 int drive; 4552 u_int32_t cy_cmd_ctrl; 4553 u_int32_t idedma_ctl; 4554 struct pciide_channel *cp = (struct pciide_channel *)chp; 4555 struct pciide_softc *sc = (struct pciide_softc *)cp->wdc_channel.wdc; 4556 int dma_mode = -1; 4557 struct pciide_cy *cy = sc->sc_cookie; 4558 4559 cy_cmd_ctrl = idedma_ctl = 0; 4560 4561 /* setup DMA if needed */ 4562 pciide_channel_dma_setup(cp); 4563 4564 for (drive = 0; drive < 2; drive++) { 4565 drvp = &chp->ch_drive[drive]; 4566 /* If no drive, skip */ 4567 if ((drvp->drive_flags & DRIVE) == 0) 4568 continue; 4569 /* add timing values, setup DMA if needed */ 4570 if (drvp->drive_flags & DRIVE_DMA) { 4571 idedma_ctl |= IDEDMA_CTL_DRV_DMA(drive); 4572 /* use Multiword DMA */ 4573 if (dma_mode == -1 || dma_mode > drvp->DMA_mode) 4574 dma_mode = drvp->DMA_mode; 4575 } 4576 cy_cmd_ctrl |= (cy_pio_pulse[drvp->PIO_mode] << 4577 CY_CMD_CTRL_IOW_PULSE_OFF(drive)); 4578 cy_cmd_ctrl |= (cy_pio_rec[drvp->PIO_mode] << 4579 CY_CMD_CTRL_IOW_REC_OFF(drive)); 4580 cy_cmd_ctrl |= (cy_pio_pulse[drvp->PIO_mode] << 4581 CY_CMD_CTRL_IOR_PULSE_OFF(drive)); 4582 cy_cmd_ctrl |= (cy_pio_rec[drvp->PIO_mode] << 4583 CY_CMD_CTRL_IOR_REC_OFF(drive)); 4584 } 4585 pci_conf_write(sc->sc_pc, sc->sc_tag, CY_CMD_CTRL, cy_cmd_ctrl); 4586 chp->ch_drive[0].DMA_mode = dma_mode; 4587 chp->ch_drive[1].DMA_mode = dma_mode; 4588 4589 if (dma_mode == -1) 4590 dma_mode = 0; 4591 4592 if (cy->cy_handle != NULL) { 4593 /* Note: `multiple' is implied. */ 4594 cy82c693_write(cy->cy_handle, 4595 (cy->cy_compatchan == 0) ? 4596 CY_DMA_IDX_PRIMARY : CY_DMA_IDX_SECONDARY, dma_mode); 4597 } 4598 4599 pciide_print_modes(cp); 4600 4601 if (idedma_ctl != 0) { 4602 /* Add software bits in status register */ 4603 bus_space_write_1(sc->sc_dma_iot, sc->sc_dma_ioh, 4604 IDEDMA_CTL(chp->channel), idedma_ctl); 4605 } 4606 } 4607 4608 static struct sis_hostbr_type { 4609 u_int16_t id; 4610 u_int8_t rev; 4611 u_int8_t udma_mode; 4612 char *name; 4613 u_int8_t type; 4614 #define SIS_TYPE_NOUDMA 0 4615 #define SIS_TYPE_66 1 4616 #define SIS_TYPE_100OLD 2 4617 #define SIS_TYPE_100NEW 3 4618 #define SIS_TYPE_133OLD 4 4619 #define SIS_TYPE_133NEW 5 4620 #define SIS_TYPE_SOUTH 6 4621 } sis_hostbr_type[] = { 4622 /* Most infos here are from sos@freebsd.org */ 4623 {PCI_PRODUCT_SIS_530, 0x00, 4, "530", SIS_TYPE_66}, 4624 #if 0 4625 /* 4626 * controllers associated to a rev 0x2 530 Host to PCI Bridge 4627 * have problems with UDMA (info provided by Christos) 4628 */ 4629 {PCI_PRODUCT_SIS_530, 0x02, 0, "530 (buggy)", SIS_TYPE_NOUDMA}, 4630 #endif 4631 {PCI_PRODUCT_SIS_540, 0x00, 4, "540", SIS_TYPE_66}, 4632 {PCI_PRODUCT_SIS_550, 0x00, 4, "550", SIS_TYPE_66}, 4633 {PCI_PRODUCT_SIS_620, 0x00, 4, "620", SIS_TYPE_66}, 4634 {PCI_PRODUCT_SIS_630, 0x00, 4, "630", SIS_TYPE_66}, 4635 {PCI_PRODUCT_SIS_630, 0x30, 5, "630S", SIS_TYPE_100NEW}, 4636 {PCI_PRODUCT_SIS_633, 0x00, 5, "633", SIS_TYPE_100NEW}, 4637 {PCI_PRODUCT_SIS_635, 0x00, 5, "635", SIS_TYPE_100NEW}, 4638 {PCI_PRODUCT_SIS_640, 0x00, 4, "640", SIS_TYPE_SOUTH}, 4639 {PCI_PRODUCT_SIS_645, 0x00, 6, "645", SIS_TYPE_SOUTH}, 4640 {PCI_PRODUCT_SIS_646, 0x00, 6, "645DX", SIS_TYPE_SOUTH}, 4641 {PCI_PRODUCT_SIS_648, 0x00, 6, "648", SIS_TYPE_SOUTH}, 4642 {PCI_PRODUCT_SIS_650, 0x00, 6, "650", SIS_TYPE_SOUTH}, 4643 {PCI_PRODUCT_SIS_651, 0x00, 6, "651", SIS_TYPE_SOUTH}, 4644 {PCI_PRODUCT_SIS_652, 0x00, 6, "652", SIS_TYPE_SOUTH}, 4645 {PCI_PRODUCT_SIS_655, 0x00, 6, "655", SIS_TYPE_SOUTH}, 4646 {PCI_PRODUCT_SIS_658, 0x00, 6, "658", SIS_TYPE_SOUTH}, 4647 {PCI_PRODUCT_SIS_661, 0x00, 6, "661", SIS_TYPE_SOUTH}, 4648 {PCI_PRODUCT_SIS_730, 0x00, 5, "730", SIS_TYPE_100OLD}, 4649 {PCI_PRODUCT_SIS_733, 0x00, 5, "733", SIS_TYPE_100NEW}, 4650 {PCI_PRODUCT_SIS_735, 0x00, 5, "735", SIS_TYPE_100NEW}, 4651 {PCI_PRODUCT_SIS_740, 0x00, 5, "740", SIS_TYPE_SOUTH}, 4652 {PCI_PRODUCT_SIS_741, 0x00, 6, "741", SIS_TYPE_SOUTH}, 4653 {PCI_PRODUCT_SIS_745, 0x00, 5, "745", SIS_TYPE_100NEW}, 4654 {PCI_PRODUCT_SIS_746, 0x00, 6, "746", SIS_TYPE_SOUTH}, 4655 {PCI_PRODUCT_SIS_748, 0x00, 6, "748", SIS_TYPE_SOUTH}, 4656 {PCI_PRODUCT_SIS_750, 0x00, 6, "750", SIS_TYPE_SOUTH}, 4657 {PCI_PRODUCT_SIS_751, 0x00, 6, "751", SIS_TYPE_SOUTH}, 4658 {PCI_PRODUCT_SIS_752, 0x00, 6, "752", SIS_TYPE_SOUTH}, 4659 {PCI_PRODUCT_SIS_755, 0x00, 6, "755", SIS_TYPE_SOUTH}, 4660 {PCI_PRODUCT_SIS_760, 0x00, 6, "760", SIS_TYPE_SOUTH}, 4661 /* 4662 * From sos@freebsd.org: the 0x961 ID will never be found in real world 4663 * {PCI_PRODUCT_SIS_961, 0x00, 6, "961", SIS_TYPE_133NEW}, 4664 */ 4665 {PCI_PRODUCT_SIS_962, 0x00, 6, "962", SIS_TYPE_133NEW}, 4666 {PCI_PRODUCT_SIS_963, 0x00, 6, "963", SIS_TYPE_133NEW}, 4667 {PCI_PRODUCT_SIS_964, 0x00, 6, "964", SIS_TYPE_133NEW}, 4668 {PCI_PRODUCT_SIS_965, 0x00, 6, "965", SIS_TYPE_133NEW} 4669 }; 4670 4671 static struct sis_hostbr_type *sis_hostbr_type_match; 4672 4673 int 4674 sis_hostbr_match(struct pci_attach_args *pa) 4675 { 4676 int i; 4677 4678 if (PCI_VENDOR(pa->pa_id) != PCI_VENDOR_SIS) 4679 return (0); 4680 sis_hostbr_type_match = NULL; 4681 for (i = 0; 4682 i < sizeof(sis_hostbr_type) / sizeof(sis_hostbr_type[0]); 4683 i++) { 4684 if (PCI_PRODUCT(pa->pa_id) == sis_hostbr_type[i].id && 4685 PCI_REVISION(pa->pa_class) >= sis_hostbr_type[i].rev) 4686 sis_hostbr_type_match = &sis_hostbr_type[i]; 4687 } 4688 return (sis_hostbr_type_match != NULL); 4689 } 4690 4691 int 4692 sis_south_match(struct pci_attach_args *pa) 4693 { 4694 return(PCI_VENDOR(pa->pa_id) == PCI_VENDOR_SIS && 4695 PCI_PRODUCT(pa->pa_id) == PCI_PRODUCT_SIS_85C503 && 4696 PCI_REVISION(pa->pa_class) >= 0x10); 4697 } 4698 4699 void 4700 sis_chip_map(struct pciide_softc *sc, struct pci_attach_args *pa) 4701 { 4702 struct pciide_channel *cp; 4703 int channel; 4704 u_int8_t sis_ctr0 = pciide_pci_read(sc->sc_pc, sc->sc_tag, SIS_CTRL0); 4705 pcireg_t interface = PCI_INTERFACE(pa->pa_class); 4706 int rev = sc->sc_rev; 4707 bus_size_t cmdsize, ctlsize; 4708 struct pciide_sis *sis; 4709 4710 /* Allocate memory for private data */ 4711 sc->sc_cookie = malloc(sizeof(*sis), M_DEVBUF, M_NOWAIT | M_ZERO); 4712 sis = sc->sc_cookie; 4713 4714 pci_find_device(NULL, sis_hostbr_match); 4715 4716 if (sis_hostbr_type_match) { 4717 if (sis_hostbr_type_match->type == SIS_TYPE_SOUTH) { 4718 pciide_pci_write(sc->sc_pc, sc->sc_tag, SIS_REG_57, 4719 pciide_pci_read(sc->sc_pc, sc->sc_tag, 4720 SIS_REG_57) & 0x7f); 4721 if (sc->sc_pp->ide_product == SIS_PRODUCT_5518) { 4722 sis->sis_type = SIS_TYPE_133NEW; 4723 sc->sc_wdcdev.UDMA_cap = 4724 sis_hostbr_type_match->udma_mode; 4725 } else { 4726 if (pci_find_device(NULL, sis_south_match)) { 4727 sis->sis_type = SIS_TYPE_133OLD; 4728 sc->sc_wdcdev.UDMA_cap = 4729 sis_hostbr_type_match->udma_mode; 4730 } else { 4731 sis->sis_type = SIS_TYPE_100NEW; 4732 sc->sc_wdcdev.UDMA_cap = 4733 sis_hostbr_type_match->udma_mode; 4734 } 4735 } 4736 } else { 4737 sis->sis_type = sis_hostbr_type_match->type; 4738 sc->sc_wdcdev.UDMA_cap = 4739 sis_hostbr_type_match->udma_mode; 4740 } 4741 printf(": %s", sis_hostbr_type_match->name); 4742 } else { 4743 printf(": 5597/5598"); 4744 if (rev >= 0xd0) { 4745 sc->sc_wdcdev.UDMA_cap = 2; 4746 sis->sis_type = SIS_TYPE_66; 4747 } else { 4748 sc->sc_wdcdev.UDMA_cap = 0; 4749 sis->sis_type = SIS_TYPE_NOUDMA; 4750 } 4751 } 4752 4753 printf(": DMA"); 4754 pciide_mapreg_dma(sc, pa); 4755 4756 sc->sc_wdcdev.cap = WDC_CAPABILITY_DATA16 | WDC_CAPABILITY_DATA32 | 4757 WDC_CAPABILITY_MODE; 4758 if (sc->sc_dma_ok) { 4759 sc->sc_wdcdev.cap |= WDC_CAPABILITY_DMA | WDC_CAPABILITY_IRQACK; 4760 sc->sc_wdcdev.irqack = pciide_irqack; 4761 if (sis->sis_type >= SIS_TYPE_66) 4762 sc->sc_wdcdev.cap |= WDC_CAPABILITY_UDMA; 4763 } 4764 4765 sc->sc_wdcdev.PIO_cap = 4; 4766 sc->sc_wdcdev.DMA_cap = 2; 4767 4768 sc->sc_wdcdev.channels = sc->wdc_chanarray; 4769 sc->sc_wdcdev.nchannels = PCIIDE_NUM_CHANNELS; 4770 switch (sis->sis_type) { 4771 case SIS_TYPE_NOUDMA: 4772 case SIS_TYPE_66: 4773 case SIS_TYPE_100OLD: 4774 sc->sc_wdcdev.set_modes = sis_setup_channel; 4775 pciide_pci_write(sc->sc_pc, sc->sc_tag, SIS_MISC, 4776 pciide_pci_read(sc->sc_pc, sc->sc_tag, SIS_MISC) | 4777 SIS_MISC_TIM_SEL | SIS_MISC_FIFO_SIZE | SIS_MISC_GTC); 4778 break; 4779 case SIS_TYPE_100NEW: 4780 case SIS_TYPE_133OLD: 4781 sc->sc_wdcdev.set_modes = sis_setup_channel; 4782 pciide_pci_write(sc->sc_pc, sc->sc_tag, SIS_REG_49, 4783 pciide_pci_read(sc->sc_pc, sc->sc_tag, SIS_REG_49) | 0x01); 4784 break; 4785 case SIS_TYPE_133NEW: 4786 sc->sc_wdcdev.set_modes = sis96x_setup_channel; 4787 pciide_pci_write(sc->sc_pc, sc->sc_tag, SIS_REG_50, 4788 pciide_pci_read(sc->sc_pc, sc->sc_tag, SIS_REG_50) & 0xf7); 4789 pciide_pci_write(sc->sc_pc, sc->sc_tag, SIS_REG_52, 4790 pciide_pci_read(sc->sc_pc, sc->sc_tag, SIS_REG_52) & 0xf7); 4791 break; 4792 } 4793 4794 pciide_print_channels(sc->sc_wdcdev.nchannels, interface); 4795 4796 for (channel = 0; channel < sc->sc_wdcdev.nchannels; channel++) { 4797 cp = &sc->pciide_channels[channel]; 4798 if (pciide_chansetup(sc, channel, interface) == 0) 4799 continue; 4800 if ((channel == 0 && (sis_ctr0 & SIS_CTRL0_CHAN0_EN) == 0) || 4801 (channel == 1 && (sis_ctr0 & SIS_CTRL0_CHAN1_EN) == 0)) { 4802 printf("%s: %s ignored (disabled)\n", 4803 sc->sc_wdcdev.sc_dev.dv_xname, cp->name); 4804 continue; 4805 } 4806 pciide_map_compat_intr(pa, cp, channel, interface); 4807 if (cp->hw_ok == 0) 4808 continue; 4809 pciide_mapchan(pa, cp, interface, &cmdsize, &ctlsize, 4810 pciide_pci_intr); 4811 if (cp->hw_ok == 0) { 4812 pciide_unmap_compat_intr(pa, cp, channel, interface); 4813 continue; 4814 } 4815 if (pciide_chan_candisable(cp)) { 4816 if (channel == 0) 4817 sis_ctr0 &= ~SIS_CTRL0_CHAN0_EN; 4818 else 4819 sis_ctr0 &= ~SIS_CTRL0_CHAN1_EN; 4820 pciide_pci_write(sc->sc_pc, sc->sc_tag, SIS_CTRL0, 4821 sis_ctr0); 4822 } 4823 if (cp->hw_ok == 0) { 4824 pciide_unmap_compat_intr(pa, cp, channel, interface); 4825 continue; 4826 } 4827 sc->sc_wdcdev.set_modes(&cp->wdc_channel); 4828 } 4829 } 4830 4831 void 4832 sis96x_setup_channel(struct channel_softc *chp) 4833 { 4834 struct ata_drive_datas *drvp; 4835 int drive; 4836 u_int32_t sis_tim; 4837 u_int32_t idedma_ctl; 4838 int regtim; 4839 struct pciide_channel *cp = (struct pciide_channel *)chp; 4840 struct pciide_softc *sc = (struct pciide_softc *)cp->wdc_channel.wdc; 4841 4842 sis_tim = 0; 4843 idedma_ctl = 0; 4844 /* setup DMA if needed */ 4845 pciide_channel_dma_setup(cp); 4846 4847 for (drive = 0; drive < 2; drive++) { 4848 regtim = SIS_TIM133( 4849 pciide_pci_read(sc->sc_pc, sc->sc_tag, SIS_REG_57), 4850 chp->channel, drive); 4851 drvp = &chp->ch_drive[drive]; 4852 /* If no drive, skip */ 4853 if ((drvp->drive_flags & DRIVE) == 0) 4854 continue; 4855 /* add timing values, setup DMA if needed */ 4856 if (drvp->drive_flags & DRIVE_UDMA) { 4857 /* use Ultra/DMA */ 4858 drvp->drive_flags &= ~DRIVE_DMA; 4859 if (pciide_pci_read(sc->sc_pc, sc->sc_tag, 4860 SIS96x_REG_CBL(chp->channel)) & SIS96x_REG_CBL_33) { 4861 if (drvp->UDMA_mode > 2) 4862 drvp->UDMA_mode = 2; 4863 } 4864 sis_tim |= sis_udma133new_tim[drvp->UDMA_mode]; 4865 sis_tim |= sis_pio133new_tim[drvp->PIO_mode]; 4866 idedma_ctl |= IDEDMA_CTL_DRV_DMA(drive); 4867 } else if (drvp->drive_flags & DRIVE_DMA) { 4868 /* 4869 * use Multiword DMA 4870 * Timings will be used for both PIO and DMA, 4871 * so adjust DMA mode if needed 4872 */ 4873 if (drvp->PIO_mode > (drvp->DMA_mode + 2)) 4874 drvp->PIO_mode = drvp->DMA_mode + 2; 4875 if (drvp->DMA_mode + 2 > (drvp->PIO_mode)) 4876 drvp->DMA_mode = (drvp->PIO_mode > 2) ? 4877 drvp->PIO_mode - 2 : 0; 4878 sis_tim |= sis_dma133new_tim[drvp->DMA_mode]; 4879 idedma_ctl |= IDEDMA_CTL_DRV_DMA(drive); 4880 } else { 4881 sis_tim |= sis_pio133new_tim[drvp->PIO_mode]; 4882 } 4883 WDCDEBUG_PRINT(("sis96x_setup_channel: new timings reg for " 4884 "channel %d drive %d: 0x%x (reg 0x%x)\n", 4885 chp->channel, drive, sis_tim, regtim), DEBUG_PROBE); 4886 pci_conf_write(sc->sc_pc, sc->sc_tag, regtim, sis_tim); 4887 } 4888 if (idedma_ctl != 0) { 4889 /* Add software bits in status register */ 4890 bus_space_write_1(sc->sc_dma_iot, sc->sc_dma_ioh, 4891 IDEDMA_CTL(chp->channel), idedma_ctl); 4892 } 4893 pciide_print_modes(cp); 4894 } 4895 4896 void 4897 sis_setup_channel(struct channel_softc *chp) 4898 { 4899 struct ata_drive_datas *drvp; 4900 int drive; 4901 u_int32_t sis_tim; 4902 u_int32_t idedma_ctl; 4903 struct pciide_channel *cp = (struct pciide_channel *)chp; 4904 struct pciide_softc *sc = (struct pciide_softc *)cp->wdc_channel.wdc; 4905 struct pciide_sis *sis = sc->sc_cookie; 4906 4907 WDCDEBUG_PRINT(("sis_setup_channel: old timings reg for " 4908 "channel %d 0x%x\n", chp->channel, 4909 pci_conf_read(sc->sc_pc, sc->sc_tag, SIS_TIM(chp->channel))), 4910 DEBUG_PROBE); 4911 sis_tim = 0; 4912 idedma_ctl = 0; 4913 /* setup DMA if needed */ 4914 pciide_channel_dma_setup(cp); 4915 4916 for (drive = 0; drive < 2; drive++) { 4917 drvp = &chp->ch_drive[drive]; 4918 /* If no drive, skip */ 4919 if ((drvp->drive_flags & DRIVE) == 0) 4920 continue; 4921 /* add timing values, setup DMA if needed */ 4922 if ((drvp->drive_flags & DRIVE_DMA) == 0 && 4923 (drvp->drive_flags & DRIVE_UDMA) == 0) 4924 goto pio; 4925 4926 if (drvp->drive_flags & DRIVE_UDMA) { 4927 /* use Ultra/DMA */ 4928 drvp->drive_flags &= ~DRIVE_DMA; 4929 if (pciide_pci_read(sc->sc_pc, sc->sc_tag, 4930 SIS_REG_CBL) & SIS_REG_CBL_33(chp->channel)) { 4931 if (drvp->UDMA_mode > 2) 4932 drvp->UDMA_mode = 2; 4933 } 4934 switch (sis->sis_type) { 4935 case SIS_TYPE_66: 4936 case SIS_TYPE_100OLD: 4937 sis_tim |= sis_udma66_tim[drvp->UDMA_mode] << 4938 SIS_TIM66_UDMA_TIME_OFF(drive); 4939 break; 4940 case SIS_TYPE_100NEW: 4941 sis_tim |= 4942 sis_udma100new_tim[drvp->UDMA_mode] << 4943 SIS_TIM100_UDMA_TIME_OFF(drive); 4944 break; 4945 case SIS_TYPE_133OLD: 4946 sis_tim |= 4947 sis_udma133old_tim[drvp->UDMA_mode] << 4948 SIS_TIM100_UDMA_TIME_OFF(drive); 4949 break; 4950 default: 4951 printf("unknown SiS IDE type %d\n", 4952 sis->sis_type); 4953 } 4954 } else { 4955 /* 4956 * use Multiword DMA 4957 * Timings will be used for both PIO and DMA, 4958 * so adjust DMA mode if needed 4959 */ 4960 if (drvp->PIO_mode > (drvp->DMA_mode + 2)) 4961 drvp->PIO_mode = drvp->DMA_mode + 2; 4962 if (drvp->DMA_mode + 2 > (drvp->PIO_mode)) 4963 drvp->DMA_mode = (drvp->PIO_mode > 2) ? 4964 drvp->PIO_mode - 2 : 0; 4965 if (drvp->DMA_mode == 0) 4966 drvp->PIO_mode = 0; 4967 } 4968 idedma_ctl |= IDEDMA_CTL_DRV_DMA(drive); 4969 pio: switch (sis->sis_type) { 4970 case SIS_TYPE_NOUDMA: 4971 case SIS_TYPE_66: 4972 case SIS_TYPE_100OLD: 4973 sis_tim |= sis_pio_act[drvp->PIO_mode] << 4974 SIS_TIM66_ACT_OFF(drive); 4975 sis_tim |= sis_pio_rec[drvp->PIO_mode] << 4976 SIS_TIM66_REC_OFF(drive); 4977 break; 4978 case SIS_TYPE_100NEW: 4979 case SIS_TYPE_133OLD: 4980 sis_tim |= sis_pio_act[drvp->PIO_mode] << 4981 SIS_TIM100_ACT_OFF(drive); 4982 sis_tim |= sis_pio_rec[drvp->PIO_mode] << 4983 SIS_TIM100_REC_OFF(drive); 4984 break; 4985 default: 4986 printf("unknown SiS IDE type %d\n", 4987 sis->sis_type); 4988 } 4989 } 4990 WDCDEBUG_PRINT(("sis_setup_channel: new timings reg for " 4991 "channel %d 0x%x\n", chp->channel, sis_tim), DEBUG_PROBE); 4992 pci_conf_write(sc->sc_pc, sc->sc_tag, SIS_TIM(chp->channel), sis_tim); 4993 if (idedma_ctl != 0) { 4994 /* Add software bits in status register */ 4995 bus_space_write_1(sc->sc_dma_iot, sc->sc_dma_ioh, 4996 IDEDMA_CTL(chp->channel), idedma_ctl); 4997 } 4998 pciide_print_modes(cp); 4999 } 5000 5001 void 5002 natsemi_chip_map(struct pciide_softc *sc, struct pci_attach_args *pa) 5003 { 5004 struct pciide_channel *cp; 5005 int channel; 5006 pcireg_t interface, ctl; 5007 bus_size_t cmdsize, ctlsize; 5008 5009 printf(": DMA"); 5010 pciide_mapreg_dma(sc, pa); 5011 sc->sc_wdcdev.cap = WDC_CAPABILITY_DATA16; 5012 5013 if (sc->sc_dma_ok) { 5014 sc->sc_wdcdev.cap |= WDC_CAPABILITY_DMA | WDC_CAPABILITY_IRQACK; 5015 sc->sc_wdcdev.irqack = natsemi_irqack; 5016 } 5017 5018 pciide_pci_write(sc->sc_pc, sc->sc_tag, NATSEMI_CCBT, 0xb7); 5019 5020 /* 5021 * Mask off interrupts from both channels, appropriate channel(s) 5022 * will be unmasked later. 5023 */ 5024 pciide_pci_write(sc->sc_pc, sc->sc_tag, NATSEMI_CTRL2, 5025 pciide_pci_read(sc->sc_pc, sc->sc_tag, NATSEMI_CTRL2) | 5026 NATSEMI_CHMASK(0) | NATSEMI_CHMASK(1)); 5027 5028 sc->sc_wdcdev.PIO_cap = 4; 5029 sc->sc_wdcdev.DMA_cap = 2; 5030 sc->sc_wdcdev.set_modes = natsemi_setup_channel; 5031 sc->sc_wdcdev.channels = sc->wdc_chanarray; 5032 sc->sc_wdcdev.nchannels = PCIIDE_NUM_CHANNELS; 5033 5034 interface = PCI_INTERFACE(pci_conf_read(sc->sc_pc, sc->sc_tag, 5035 PCI_CLASS_REG)); 5036 interface &= ~PCIIDE_CHANSTATUS_EN; /* Reserved on PC87415 */ 5037 pciide_print_channels(sc->sc_wdcdev.nchannels, interface); 5038 5039 /* If we're in PCIIDE mode, unmask INTA, otherwise mask it. */ 5040 ctl = pciide_pci_read(sc->sc_pc, sc->sc_tag, NATSEMI_CTRL1); 5041 if (interface & (PCIIDE_INTERFACE_PCI(0) | PCIIDE_INTERFACE_PCI(1))) 5042 ctl &= ~NATSEMI_CTRL1_INTAMASK; 5043 else 5044 ctl |= NATSEMI_CTRL1_INTAMASK; 5045 pciide_pci_write(sc->sc_pc, sc->sc_tag, NATSEMI_CTRL1, ctl); 5046 5047 for (channel = 0; channel < sc->sc_wdcdev.nchannels; channel++) { 5048 cp = &sc->pciide_channels[channel]; 5049 if (pciide_chansetup(sc, channel, interface) == 0) 5050 continue; 5051 5052 pciide_map_compat_intr(pa, cp, channel, interface); 5053 if (cp->hw_ok == 0) 5054 continue; 5055 5056 pciide_mapchan(pa, cp, interface, &cmdsize, &ctlsize, 5057 natsemi_pci_intr); 5058 if (cp->hw_ok == 0) { 5059 pciide_unmap_compat_intr(pa, cp, channel, interface); 5060 continue; 5061 } 5062 natsemi_setup_channel(&cp->wdc_channel); 5063 } 5064 } 5065 5066 void 5067 natsemi_setup_channel(struct channel_softc *chp) 5068 { 5069 struct ata_drive_datas *drvp; 5070 int drive, ndrives = 0; 5071 u_int32_t idedma_ctl = 0; 5072 struct pciide_channel *cp = (struct pciide_channel *)chp; 5073 struct pciide_softc *sc = (struct pciide_softc *)cp->wdc_channel.wdc; 5074 u_int8_t tim; 5075 5076 /* setup DMA if needed */ 5077 pciide_channel_dma_setup(cp); 5078 5079 for (drive = 0; drive < 2; drive++) { 5080 drvp = &chp->ch_drive[drive]; 5081 /* If no drive, skip */ 5082 if ((drvp->drive_flags & DRIVE) == 0) 5083 continue; 5084 5085 ndrives++; 5086 /* add timing values, setup DMA if needed */ 5087 if ((drvp->drive_flags & DRIVE_DMA) == 0) { 5088 tim = natsemi_pio_pulse[drvp->PIO_mode] | 5089 (natsemi_pio_recover[drvp->PIO_mode] << 4); 5090 } else { 5091 /* 5092 * use Multiword DMA 5093 * Timings will be used for both PIO and DMA, 5094 * so adjust DMA mode if needed 5095 */ 5096 if (drvp->PIO_mode >= 3 && 5097 (drvp->DMA_mode + 2) > drvp->PIO_mode) { 5098 drvp->DMA_mode = drvp->PIO_mode - 2; 5099 } 5100 idedma_ctl |= IDEDMA_CTL_DRV_DMA(drive); 5101 tim = natsemi_dma_pulse[drvp->DMA_mode] | 5102 (natsemi_dma_recover[drvp->DMA_mode] << 4); 5103 } 5104 5105 pciide_pci_write(sc->sc_pc, sc->sc_tag, 5106 NATSEMI_RTREG(chp->channel, drive), tim); 5107 pciide_pci_write(sc->sc_pc, sc->sc_tag, 5108 NATSEMI_WTREG(chp->channel, drive), tim); 5109 } 5110 if (idedma_ctl != 0) { 5111 /* Add software bits in status register */ 5112 bus_space_write_1(sc->sc_dma_iot, sc->sc_dma_ioh, 5113 IDEDMA_CTL(chp->channel), idedma_ctl); 5114 } 5115 if (ndrives > 0) { 5116 /* Unmask the channel if at least one drive is found */ 5117 pciide_pci_write(sc->sc_pc, sc->sc_tag, NATSEMI_CTRL2, 5118 pciide_pci_read(sc->sc_pc, sc->sc_tag, NATSEMI_CTRL2) & 5119 ~(NATSEMI_CHMASK(chp->channel))); 5120 } 5121 5122 pciide_print_modes(cp); 5123 5124 /* Go ahead and ack interrupts generated during probe. */ 5125 bus_space_write_1(sc->sc_dma_iot, sc->sc_dma_ioh, 5126 IDEDMA_CTL(chp->channel), 5127 bus_space_read_1(sc->sc_dma_iot, sc->sc_dma_ioh, 5128 IDEDMA_CTL(chp->channel))); 5129 } 5130 5131 void 5132 natsemi_irqack(struct channel_softc *chp) 5133 { 5134 struct pciide_channel *cp = (struct pciide_channel *)chp; 5135 struct pciide_softc *sc = (struct pciide_softc *)cp->wdc_channel.wdc; 5136 u_int8_t clr; 5137 5138 /* The "clear" bits are in the wrong register *sigh* */ 5139 clr = bus_space_read_1(sc->sc_dma_iot, sc->sc_dma_ioh, 5140 IDEDMA_CMD(chp->channel)); 5141 clr |= bus_space_read_1(sc->sc_dma_iot, sc->sc_dma_ioh, 5142 IDEDMA_CTL(chp->channel)) & 5143 (IDEDMA_CTL_ERR | IDEDMA_CTL_INTR); 5144 bus_space_write_1(sc->sc_dma_iot, sc->sc_dma_ioh, 5145 IDEDMA_CMD(chp->channel), clr); 5146 } 5147 5148 int 5149 natsemi_pci_intr(void *arg) 5150 { 5151 struct pciide_softc *sc = arg; 5152 struct pciide_channel *cp; 5153 struct channel_softc *wdc_cp; 5154 int i, rv, crv; 5155 u_int8_t msk; 5156 5157 rv = 0; 5158 msk = pciide_pci_read(sc->sc_pc, sc->sc_tag, NATSEMI_CTRL2); 5159 for (i = 0; i < sc->sc_wdcdev.nchannels; i++) { 5160 cp = &sc->pciide_channels[i]; 5161 wdc_cp = &cp->wdc_channel; 5162 5163 /* If a compat channel skip. */ 5164 if (cp->compat) 5165 continue; 5166 5167 /* If this channel is masked, skip it. */ 5168 if (msk & NATSEMI_CHMASK(i)) 5169 continue; 5170 5171 if (pciide_intr_flag(cp) == 0) 5172 continue; 5173 5174 crv = wdcintr(wdc_cp); 5175 if (crv == 0) 5176 ; /* leave rv alone */ 5177 else if (crv == 1) 5178 rv = 1; /* claim the intr */ 5179 else if (rv == 0) /* crv should be -1 in this case */ 5180 rv = crv; /* if we've done no better, take it */ 5181 } 5182 return (rv); 5183 } 5184 5185 void 5186 ns_scx200_chip_map(struct pciide_softc *sc, struct pci_attach_args *pa) 5187 { 5188 struct pciide_channel *cp; 5189 int channel; 5190 pcireg_t interface = PCI_INTERFACE(pa->pa_class); 5191 bus_size_t cmdsize, ctlsize; 5192 5193 printf(": DMA"); 5194 pciide_mapreg_dma(sc, pa); 5195 5196 sc->sc_wdcdev.cap = WDC_CAPABILITY_DATA16 | WDC_CAPABILITY_DATA32 | 5197 WDC_CAPABILITY_MODE; 5198 if (sc->sc_dma_ok) { 5199 sc->sc_wdcdev.cap |= WDC_CAPABILITY_DMA | WDC_CAPABILITY_UDMA; 5200 sc->sc_wdcdev.cap |= WDC_CAPABILITY_IRQACK; 5201 sc->sc_wdcdev.irqack = pciide_irqack; 5202 } 5203 sc->sc_wdcdev.PIO_cap = 4; 5204 sc->sc_wdcdev.DMA_cap = 2; 5205 sc->sc_wdcdev.UDMA_cap = 2; 5206 5207 sc->sc_wdcdev.set_modes = ns_scx200_setup_channel; 5208 sc->sc_wdcdev.channels = sc->wdc_chanarray; 5209 sc->sc_wdcdev.nchannels = PCIIDE_NUM_CHANNELS; 5210 5211 /* 5212 * Soekris net4801 errata 0003: 5213 * 5214 * The SC1100 built in busmaster IDE controller is pretty standard, 5215 * but have two bugs: data transfers need to be dword aligned and 5216 * it cannot do an exact 64Kbyte data transfer. 5217 * 5218 * Assume that reducing maximum segment size by one page 5219 * will be enough, and restrict boundary too for extra certainty. 5220 */ 5221 if (sc->sc_pp->ide_product == PCI_PRODUCT_NS_SCx200_IDE) { 5222 sc->sc_dma_maxsegsz = IDEDMA_BYTE_COUNT_MAX - PAGE_SIZE; 5223 sc->sc_dma_boundary = IDEDMA_BYTE_COUNT_MAX - PAGE_SIZE; 5224 } 5225 5226 /* 5227 * This chip seems to be unable to do one-sector transfers 5228 * using DMA. 5229 */ 5230 sc->sc_wdcdev.quirks = WDC_QUIRK_NOSHORTDMA; 5231 5232 pciide_print_channels(sc->sc_wdcdev.nchannels, interface); 5233 5234 for (channel = 0; channel < sc->sc_wdcdev.nchannels; channel++) { 5235 cp = &sc->pciide_channels[channel]; 5236 if (pciide_chansetup(sc, channel, interface) == 0) 5237 continue; 5238 pciide_map_compat_intr(pa, cp, channel, interface); 5239 if (cp->hw_ok == 0) 5240 continue; 5241 pciide_mapchan(pa, cp, interface, &cmdsize, &ctlsize, 5242 pciide_pci_intr); 5243 if (cp->hw_ok == 0) { 5244 pciide_unmap_compat_intr(pa, cp, channel, interface); 5245 continue; 5246 } 5247 sc->sc_wdcdev.set_modes(&cp->wdc_channel); 5248 } 5249 } 5250 5251 void 5252 ns_scx200_setup_channel(struct channel_softc *chp) 5253 { 5254 struct ata_drive_datas *drvp; 5255 int drive, mode; 5256 u_int32_t idedma_ctl; 5257 struct pciide_channel *cp = (struct pciide_channel*)chp; 5258 struct pciide_softc *sc = (struct pciide_softc *)cp->wdc_channel.wdc; 5259 int channel = chp->channel; 5260 int pioformat; 5261 pcireg_t piotim, dmatim; 5262 5263 /* Setup DMA if needed */ 5264 pciide_channel_dma_setup(cp); 5265 5266 idedma_ctl = 0; 5267 5268 pioformat = (pci_conf_read(sc->sc_pc, sc->sc_tag, 5269 SCx200_TIM_DMA(0, 0)) >> SCx200_PIOFORMAT_SHIFT) & 0x01; 5270 WDCDEBUG_PRINT(("%s: pio format %d\n", __func__, pioformat), 5271 DEBUG_PROBE); 5272 5273 /* Per channel settings */ 5274 for (drive = 0; drive < 2; drive++) { 5275 drvp = &chp->ch_drive[drive]; 5276 5277 /* If no drive, skip */ 5278 if ((drvp->drive_flags & DRIVE) == 0) 5279 continue; 5280 5281 piotim = pci_conf_read(sc->sc_pc, sc->sc_tag, 5282 SCx200_TIM_PIO(channel, drive)); 5283 dmatim = pci_conf_read(sc->sc_pc, sc->sc_tag, 5284 SCx200_TIM_DMA(channel, drive)); 5285 WDCDEBUG_PRINT(("%s:%d:%d: piotim=0x%x, dmatim=0x%x\n", 5286 sc->sc_wdcdev.sc_dev.dv_xname, channel, drive, 5287 piotim, dmatim), DEBUG_PROBE); 5288 5289 if ((chp->wdc->cap & WDC_CAPABILITY_UDMA) != 0 && 5290 (drvp->drive_flags & DRIVE_UDMA) != 0) { 5291 /* Setup UltraDMA mode */ 5292 drvp->drive_flags &= ~DRIVE_DMA; 5293 idedma_ctl |= IDEDMA_CTL_DRV_DMA(drive); 5294 dmatim = scx200_udma33[drvp->UDMA_mode]; 5295 mode = drvp->PIO_mode; 5296 } else if ((chp->wdc->cap & WDC_CAPABILITY_DMA) != 0 && 5297 (drvp->drive_flags & DRIVE_DMA) != 0) { 5298 /* Setup multiword DMA mode */ 5299 drvp->drive_flags &= ~DRIVE_UDMA; 5300 idedma_ctl |= IDEDMA_CTL_DRV_DMA(drive); 5301 dmatim = scx200_dma33[drvp->DMA_mode]; 5302 5303 /* mode = min(pio, dma + 2) */ 5304 if (drvp->PIO_mode <= (drvp->DMA_mode + 2)) 5305 mode = drvp->PIO_mode; 5306 else 5307 mode = drvp->DMA_mode + 2; 5308 } else { 5309 mode = drvp->PIO_mode; 5310 } 5311 5312 /* Setup PIO mode */ 5313 drvp->PIO_mode = mode; 5314 if (mode < 2) 5315 drvp->DMA_mode = 0; 5316 else 5317 drvp->DMA_mode = mode - 2; 5318 5319 piotim = scx200_pio33[pioformat][drvp->PIO_mode]; 5320 5321 WDCDEBUG_PRINT(("%s:%d:%d: new piotim=0x%x, dmatim=0x%x\n", 5322 sc->sc_wdcdev.sc_dev.dv_xname, channel, drive, 5323 piotim, dmatim), DEBUG_PROBE); 5324 5325 pci_conf_write(sc->sc_pc, sc->sc_tag, 5326 SCx200_TIM_PIO(channel, drive), piotim); 5327 pci_conf_write(sc->sc_pc, sc->sc_tag, 5328 SCx200_TIM_DMA(channel, drive), dmatim); 5329 } 5330 5331 if (idedma_ctl != 0) { 5332 /* Add software bits in status register */ 5333 bus_space_write_1(sc->sc_dma_iot, sc->sc_dma_ioh, 5334 IDEDMA_CTL(channel), idedma_ctl); 5335 } 5336 5337 pciide_print_modes(cp); 5338 } 5339 5340 void 5341 acer_chip_map(struct pciide_softc *sc, struct pci_attach_args *pa) 5342 { 5343 struct pciide_channel *cp; 5344 int channel; 5345 pcireg_t cr, interface; 5346 bus_size_t cmdsize, ctlsize; 5347 int rev = sc->sc_rev; 5348 #ifdef __sparc64__ 5349 char buf[32]; 5350 #endif 5351 5352 printf(": DMA"); 5353 pciide_mapreg_dma(sc, pa); 5354 sc->sc_wdcdev.cap = WDC_CAPABILITY_DATA16 | WDC_CAPABILITY_DATA32 | 5355 WDC_CAPABILITY_MODE; 5356 5357 #ifdef __sparc64__ 5358 /* 5359 * XXX The Tadpole SPARCLE doesn't want to do DMA. PIO works 5360 * fine, so we have this ugly hack to make the machine work. 5361 * It is likely the real cause is still lurking somewhere in 5362 * the code. 5363 */ 5364 if (OF_getprop(findroot(), "name", buf, sizeof(buf)) > 0 && 5365 strcmp(buf, "TAD,SPARCLE") == 0) 5366 sc->sc_dma_ok = 0; 5367 #endif 5368 5369 if (sc->sc_dma_ok) { 5370 sc->sc_wdcdev.cap |= WDC_CAPABILITY_DMA; 5371 if (rev >= 0x20) { 5372 sc->sc_wdcdev.cap |= WDC_CAPABILITY_UDMA; 5373 if (rev >= 0xC4) 5374 sc->sc_wdcdev.UDMA_cap = 5; 5375 else if (rev >= 0xC2) 5376 sc->sc_wdcdev.UDMA_cap = 4; 5377 else 5378 sc->sc_wdcdev.UDMA_cap = 2; 5379 } 5380 sc->sc_wdcdev.cap |= WDC_CAPABILITY_IRQACK; 5381 sc->sc_wdcdev.irqack = pciide_irqack; 5382 } 5383 5384 sc->sc_wdcdev.PIO_cap = 4; 5385 sc->sc_wdcdev.DMA_cap = 2; 5386 sc->sc_wdcdev.set_modes = acer_setup_channel; 5387 sc->sc_wdcdev.channels = sc->wdc_chanarray; 5388 sc->sc_wdcdev.nchannels = PCIIDE_NUM_CHANNELS; 5389 5390 pciide_pci_write(sc->sc_pc, sc->sc_tag, ACER_CDRC, 5391 (pciide_pci_read(sc->sc_pc, sc->sc_tag, ACER_CDRC) | 5392 ACER_CDRC_DMA_EN) & ~ACER_CDRC_FIFO_DISABLE); 5393 5394 /* Enable "microsoft register bits" R/W. */ 5395 pciide_pci_write(sc->sc_pc, sc->sc_tag, ACER_CCAR3, 5396 pciide_pci_read(sc->sc_pc, sc->sc_tag, ACER_CCAR3) | ACER_CCAR3_PI); 5397 pciide_pci_write(sc->sc_pc, sc->sc_tag, ACER_CCAR1, 5398 pciide_pci_read(sc->sc_pc, sc->sc_tag, ACER_CCAR1) & 5399 ~(ACER_CHANSTATUS_RO|PCIIDE_CHAN_RO(0)|PCIIDE_CHAN_RO(1))); 5400 pciide_pci_write(sc->sc_pc, sc->sc_tag, ACER_CCAR2, 5401 pciide_pci_read(sc->sc_pc, sc->sc_tag, ACER_CCAR2) & 5402 ~ACER_CHANSTATUSREGS_RO); 5403 cr = pci_conf_read(sc->sc_pc, sc->sc_tag, PCI_CLASS_REG); 5404 cr |= (PCIIDE_CHANSTATUS_EN << PCI_INTERFACE_SHIFT); 5405 pci_conf_write(sc->sc_pc, sc->sc_tag, PCI_CLASS_REG, cr); 5406 /* Don't use cr, re-read the real register content instead */ 5407 interface = PCI_INTERFACE(pci_conf_read(sc->sc_pc, sc->sc_tag, 5408 PCI_CLASS_REG)); 5409 5410 pciide_print_channels(sc->sc_wdcdev.nchannels, interface); 5411 5412 /* From linux: enable "Cable Detection" */ 5413 if (rev >= 0xC2) 5414 pciide_pci_write(sc->sc_pc, sc->sc_tag, ACER_0x4B, 5415 pciide_pci_read(sc->sc_pc, sc->sc_tag, ACER_0x4B) 5416 | ACER_0x4B_CDETECT); 5417 5418 for (channel = 0; channel < sc->sc_wdcdev.nchannels; channel++) { 5419 cp = &sc->pciide_channels[channel]; 5420 if (pciide_chansetup(sc, channel, interface) == 0) 5421 continue; 5422 if ((interface & PCIIDE_CHAN_EN(channel)) == 0) { 5423 printf("%s: %s ignored (disabled)\n", 5424 sc->sc_wdcdev.sc_dev.dv_xname, cp->name); 5425 continue; 5426 } 5427 pciide_map_compat_intr(pa, cp, channel, interface); 5428 if (cp->hw_ok == 0) 5429 continue; 5430 pciide_mapchan(pa, cp, interface, &cmdsize, &ctlsize, 5431 (rev >= 0xC2) ? pciide_pci_intr : acer_pci_intr); 5432 if (cp->hw_ok == 0) { 5433 pciide_unmap_compat_intr(pa, cp, channel, interface); 5434 continue; 5435 } 5436 if (pciide_chan_candisable(cp)) { 5437 cr &= ~(PCIIDE_CHAN_EN(channel) << PCI_INTERFACE_SHIFT); 5438 pci_conf_write(sc->sc_pc, sc->sc_tag, 5439 PCI_CLASS_REG, cr); 5440 } 5441 if (cp->hw_ok == 0) { 5442 pciide_unmap_compat_intr(pa, cp, channel, interface); 5443 continue; 5444 } 5445 acer_setup_channel(&cp->wdc_channel); 5446 } 5447 } 5448 5449 void 5450 acer_setup_channel(struct channel_softc *chp) 5451 { 5452 struct ata_drive_datas *drvp; 5453 int drive; 5454 u_int32_t acer_fifo_udma; 5455 u_int32_t idedma_ctl; 5456 struct pciide_channel *cp = (struct pciide_channel *)chp; 5457 struct pciide_softc *sc = (struct pciide_softc *)cp->wdc_channel.wdc; 5458 5459 idedma_ctl = 0; 5460 acer_fifo_udma = pci_conf_read(sc->sc_pc, sc->sc_tag, ACER_FTH_UDMA); 5461 WDCDEBUG_PRINT(("acer_setup_channel: old fifo/udma reg 0x%x\n", 5462 acer_fifo_udma), DEBUG_PROBE); 5463 /* setup DMA if needed */ 5464 pciide_channel_dma_setup(cp); 5465 5466 if ((chp->ch_drive[0].drive_flags | chp->ch_drive[1].drive_flags) & 5467 DRIVE_UDMA) { /* check 80 pins cable */ 5468 if (pciide_pci_read(sc->sc_pc, sc->sc_tag, ACER_0x4A) & 5469 ACER_0x4A_80PIN(chp->channel)) { 5470 WDCDEBUG_PRINT(("%s:%d: 80-wire cable not detected\n", 5471 sc->sc_wdcdev.sc_dev.dv_xname, chp->channel), 5472 DEBUG_PROBE); 5473 if (chp->ch_drive[0].UDMA_mode > 2) 5474 chp->ch_drive[0].UDMA_mode = 2; 5475 if (chp->ch_drive[1].UDMA_mode > 2) 5476 chp->ch_drive[1].UDMA_mode = 2; 5477 } 5478 } 5479 5480 for (drive = 0; drive < 2; drive++) { 5481 drvp = &chp->ch_drive[drive]; 5482 /* If no drive, skip */ 5483 if ((drvp->drive_flags & DRIVE) == 0) 5484 continue; 5485 WDCDEBUG_PRINT(("acer_setup_channel: old timings reg for " 5486 "channel %d drive %d 0x%x\n", chp->channel, drive, 5487 pciide_pci_read(sc->sc_pc, sc->sc_tag, 5488 ACER_IDETIM(chp->channel, drive))), DEBUG_PROBE); 5489 /* clear FIFO/DMA mode */ 5490 acer_fifo_udma &= ~(ACER_FTH_OPL(chp->channel, drive, 0x3) | 5491 ACER_UDMA_EN(chp->channel, drive) | 5492 ACER_UDMA_TIM(chp->channel, drive, 0x7)); 5493 5494 /* add timing values, setup DMA if needed */ 5495 if ((drvp->drive_flags & DRIVE_DMA) == 0 && 5496 (drvp->drive_flags & DRIVE_UDMA) == 0) { 5497 acer_fifo_udma |= 5498 ACER_FTH_OPL(chp->channel, drive, 0x1); 5499 goto pio; 5500 } 5501 5502 acer_fifo_udma |= ACER_FTH_OPL(chp->channel, drive, 0x2); 5503 if (drvp->drive_flags & DRIVE_UDMA) { 5504 /* use Ultra/DMA */ 5505 drvp->drive_flags &= ~DRIVE_DMA; 5506 acer_fifo_udma |= ACER_UDMA_EN(chp->channel, drive); 5507 acer_fifo_udma |= 5508 ACER_UDMA_TIM(chp->channel, drive, 5509 acer_udma[drvp->UDMA_mode]); 5510 /* XXX disable if one drive < UDMA3 ? */ 5511 if (drvp->UDMA_mode >= 3) { 5512 pciide_pci_write(sc->sc_pc, sc->sc_tag, 5513 ACER_0x4B, 5514 pciide_pci_read(sc->sc_pc, sc->sc_tag, 5515 ACER_0x4B) | ACER_0x4B_UDMA66); 5516 } 5517 } else { 5518 /* 5519 * use Multiword DMA 5520 * Timings will be used for both PIO and DMA, 5521 * so adjust DMA mode if needed 5522 */ 5523 if (drvp->PIO_mode > (drvp->DMA_mode + 2)) 5524 drvp->PIO_mode = drvp->DMA_mode + 2; 5525 if (drvp->DMA_mode + 2 > (drvp->PIO_mode)) 5526 drvp->DMA_mode = (drvp->PIO_mode > 2) ? 5527 drvp->PIO_mode - 2 : 0; 5528 if (drvp->DMA_mode == 0) 5529 drvp->PIO_mode = 0; 5530 } 5531 idedma_ctl |= IDEDMA_CTL_DRV_DMA(drive); 5532 pio: pciide_pci_write(sc->sc_pc, sc->sc_tag, 5533 ACER_IDETIM(chp->channel, drive), 5534 acer_pio[drvp->PIO_mode]); 5535 } 5536 WDCDEBUG_PRINT(("acer_setup_channel: new fifo/udma reg 0x%x\n", 5537 acer_fifo_udma), DEBUG_PROBE); 5538 pci_conf_write(sc->sc_pc, sc->sc_tag, ACER_FTH_UDMA, acer_fifo_udma); 5539 if (idedma_ctl != 0) { 5540 /* Add software bits in status register */ 5541 bus_space_write_1(sc->sc_dma_iot, sc->sc_dma_ioh, 5542 IDEDMA_CTL(chp->channel), idedma_ctl); 5543 } 5544 pciide_print_modes(cp); 5545 } 5546 5547 int 5548 acer_pci_intr(void *arg) 5549 { 5550 struct pciide_softc *sc = arg; 5551 struct pciide_channel *cp; 5552 struct channel_softc *wdc_cp; 5553 int i, rv, crv; 5554 u_int32_t chids; 5555 5556 rv = 0; 5557 chids = pciide_pci_read(sc->sc_pc, sc->sc_tag, ACER_CHIDS); 5558 for (i = 0; i < sc->sc_wdcdev.nchannels; i++) { 5559 cp = &sc->pciide_channels[i]; 5560 wdc_cp = &cp->wdc_channel; 5561 /* If a compat channel skip. */ 5562 if (cp->compat) 5563 continue; 5564 if (chids & ACER_CHIDS_INT(i)) { 5565 crv = wdcintr(wdc_cp); 5566 if (crv == 0) 5567 printf("%s:%d: bogus intr\n", 5568 sc->sc_wdcdev.sc_dev.dv_xname, i); 5569 else 5570 rv = 1; 5571 } 5572 } 5573 return (rv); 5574 } 5575 5576 void 5577 hpt_chip_map(struct pciide_softc *sc, struct pci_attach_args *pa) 5578 { 5579 struct pciide_channel *cp; 5580 int i, compatchan, revision; 5581 pcireg_t interface; 5582 bus_size_t cmdsize, ctlsize; 5583 5584 revision = sc->sc_rev; 5585 5586 /* 5587 * when the chip is in native mode it identifies itself as a 5588 * 'misc mass storage'. Fake interface in this case. 5589 */ 5590 if (PCI_SUBCLASS(pa->pa_class) == PCI_SUBCLASS_MASS_STORAGE_IDE) { 5591 interface = PCI_INTERFACE(pa->pa_class); 5592 } else { 5593 interface = PCIIDE_INTERFACE_BUS_MASTER_DMA | 5594 PCIIDE_INTERFACE_PCI(0); 5595 if ((sc->sc_pp->ide_product == PCI_PRODUCT_TRIONES_HPT366 && 5596 (revision == HPT370_REV || revision == HPT370A_REV || 5597 revision == HPT372_REV)) || 5598 sc->sc_pp->ide_product == PCI_PRODUCT_TRIONES_HPT372A || 5599 sc->sc_pp->ide_product == PCI_PRODUCT_TRIONES_HPT302 || 5600 sc->sc_pp->ide_product == PCI_PRODUCT_TRIONES_HPT371 || 5601 sc->sc_pp->ide_product == PCI_PRODUCT_TRIONES_HPT374) 5602 interface |= PCIIDE_INTERFACE_PCI(1); 5603 } 5604 5605 printf(": DMA"); 5606 pciide_mapreg_dma(sc, pa); 5607 printf("\n"); 5608 sc->sc_wdcdev.cap = WDC_CAPABILITY_DATA16 | WDC_CAPABILITY_DATA32 | 5609 WDC_CAPABILITY_MODE; 5610 if (sc->sc_dma_ok) { 5611 sc->sc_wdcdev.cap |= WDC_CAPABILITY_DMA | WDC_CAPABILITY_UDMA; 5612 sc->sc_wdcdev.cap |= WDC_CAPABILITY_IRQACK; 5613 sc->sc_wdcdev.irqack = pciide_irqack; 5614 } 5615 sc->sc_wdcdev.PIO_cap = 4; 5616 sc->sc_wdcdev.DMA_cap = 2; 5617 5618 sc->sc_wdcdev.set_modes = hpt_setup_channel; 5619 sc->sc_wdcdev.channels = sc->wdc_chanarray; 5620 if (sc->sc_pp->ide_product == PCI_PRODUCT_TRIONES_HPT366 && 5621 revision == HPT366_REV) { 5622 sc->sc_wdcdev.UDMA_cap = 4; 5623 /* 5624 * The 366 has 2 PCI IDE functions, one for primary and one 5625 * for secondary. So we need to call pciide_mapregs_compat() 5626 * with the real channel 5627 */ 5628 if (pa->pa_function == 0) { 5629 compatchan = 0; 5630 } else if (pa->pa_function == 1) { 5631 compatchan = 1; 5632 } else { 5633 printf("%s: unexpected PCI function %d\n", 5634 sc->sc_wdcdev.sc_dev.dv_xname, pa->pa_function); 5635 return; 5636 } 5637 sc->sc_wdcdev.nchannels = 1; 5638 } else { 5639 sc->sc_wdcdev.nchannels = 2; 5640 if (sc->sc_pp->ide_product == PCI_PRODUCT_TRIONES_HPT372A || 5641 sc->sc_pp->ide_product == PCI_PRODUCT_TRIONES_HPT302 || 5642 sc->sc_pp->ide_product == PCI_PRODUCT_TRIONES_HPT371 || 5643 sc->sc_pp->ide_product == PCI_PRODUCT_TRIONES_HPT374) 5644 sc->sc_wdcdev.UDMA_cap = 6; 5645 else if (sc->sc_pp->ide_product == PCI_PRODUCT_TRIONES_HPT366) { 5646 if (revision == HPT372_REV) 5647 sc->sc_wdcdev.UDMA_cap = 6; 5648 else 5649 sc->sc_wdcdev.UDMA_cap = 5; 5650 } 5651 } 5652 for (i = 0; i < sc->sc_wdcdev.nchannels; i++) { 5653 cp = &sc->pciide_channels[i]; 5654 if (sc->sc_wdcdev.nchannels > 1) { 5655 compatchan = i; 5656 if((pciide_pci_read(sc->sc_pc, sc->sc_tag, 5657 HPT370_CTRL1(i)) & HPT370_CTRL1_EN) == 0) { 5658 printf("%s: %s ignored (disabled)\n", 5659 sc->sc_wdcdev.sc_dev.dv_xname, cp->name); 5660 continue; 5661 } 5662 } 5663 if (pciide_chansetup(sc, i, interface) == 0) 5664 continue; 5665 if (interface & PCIIDE_INTERFACE_PCI(i)) { 5666 cp->hw_ok = pciide_mapregs_native(pa, cp, &cmdsize, 5667 &ctlsize, hpt_pci_intr); 5668 } else { 5669 cp->hw_ok = pciide_mapregs_compat(pa, cp, compatchan, 5670 &cmdsize, &ctlsize); 5671 } 5672 if (cp->hw_ok == 0) 5673 return; 5674 cp->wdc_channel.data32iot = cp->wdc_channel.cmd_iot; 5675 cp->wdc_channel.data32ioh = cp->wdc_channel.cmd_ioh; 5676 wdcattach(&cp->wdc_channel); 5677 hpt_setup_channel(&cp->wdc_channel); 5678 } 5679 if ((sc->sc_pp->ide_product == PCI_PRODUCT_TRIONES_HPT366 && 5680 (revision == HPT370_REV || revision == HPT370A_REV || 5681 revision == HPT372_REV)) || 5682 sc->sc_pp->ide_product == PCI_PRODUCT_TRIONES_HPT372A || 5683 sc->sc_pp->ide_product == PCI_PRODUCT_TRIONES_HPT302 || 5684 sc->sc_pp->ide_product == PCI_PRODUCT_TRIONES_HPT371 || 5685 sc->sc_pp->ide_product == PCI_PRODUCT_TRIONES_HPT374) { 5686 /* 5687 * Turn off fast interrupts 5688 */ 5689 pciide_pci_write(sc->sc_pc, sc->sc_tag, HPT370_CTRL2(0), 5690 pciide_pci_read(sc->sc_pc, sc->sc_tag, HPT370_CTRL2(0)) & 5691 ~(HPT370_CTRL2_FASTIRQ | HPT370_CTRL2_HIRQ)); 5692 pciide_pci_write(sc->sc_pc, sc->sc_tag, HPT370_CTRL2(1), 5693 pciide_pci_read(sc->sc_pc, sc->sc_tag, HPT370_CTRL2(1)) & 5694 ~(HPT370_CTRL2_FASTIRQ | HPT370_CTRL2_HIRQ)); 5695 5696 /* 5697 * HPT370 and highter has a bit to disable interrupts, 5698 * make sure to clear it 5699 */ 5700 pciide_pci_write(sc->sc_pc, sc->sc_tag, HPT_CSEL, 5701 pciide_pci_read(sc->sc_pc, sc->sc_tag, HPT_CSEL) & 5702 ~HPT_CSEL_IRQDIS); 5703 } 5704 /* set clocks, etc (mandatory on 372/4, optional otherwise) */ 5705 if (sc->sc_pp->ide_product == PCI_PRODUCT_TRIONES_HPT372A || 5706 sc->sc_pp->ide_product == PCI_PRODUCT_TRIONES_HPT302 || 5707 sc->sc_pp->ide_product == PCI_PRODUCT_TRIONES_HPT371 || 5708 sc->sc_pp->ide_product == PCI_PRODUCT_TRIONES_HPT374 || 5709 (sc->sc_pp->ide_product == PCI_PRODUCT_TRIONES_HPT366 && 5710 revision == HPT372_REV)) 5711 pciide_pci_write(sc->sc_pc, sc->sc_tag, HPT_SC2, 5712 (pciide_pci_read(sc->sc_pc, sc->sc_tag, HPT_SC2) & 5713 HPT_SC2_MAEN) | HPT_SC2_OSC_EN); 5714 5715 return; 5716 } 5717 5718 void 5719 hpt_setup_channel(struct channel_softc *chp) 5720 { 5721 struct ata_drive_datas *drvp; 5722 int drive; 5723 int cable; 5724 u_int32_t before, after; 5725 u_int32_t idedma_ctl; 5726 struct pciide_channel *cp = (struct pciide_channel *)chp; 5727 struct pciide_softc *sc = (struct pciide_softc *)cp->wdc_channel.wdc; 5728 int revision = sc->sc_rev; 5729 u_int32_t *tim_pio, *tim_dma, *tim_udma; 5730 5731 cable = pciide_pci_read(sc->sc_pc, sc->sc_tag, HPT_CSEL); 5732 5733 /* setup DMA if needed */ 5734 pciide_channel_dma_setup(cp); 5735 5736 idedma_ctl = 0; 5737 5738 switch (sc->sc_pp->ide_product) { 5739 case PCI_PRODUCT_TRIONES_HPT366: 5740 if (revision == HPT370_REV || 5741 revision == HPT370A_REV) { 5742 tim_pio = hpt370_pio; 5743 tim_dma = hpt370_dma; 5744 tim_udma = hpt370_udma; 5745 } else if (revision == HPT372_REV) { 5746 tim_pio = hpt372_pio; 5747 tim_dma = hpt372_dma; 5748 tim_udma = hpt372_udma; 5749 } else { 5750 tim_pio = hpt366_pio; 5751 tim_dma = hpt366_dma; 5752 tim_udma = hpt366_udma; 5753 } 5754 break; 5755 case PCI_PRODUCT_TRIONES_HPT372A: 5756 case PCI_PRODUCT_TRIONES_HPT302: 5757 case PCI_PRODUCT_TRIONES_HPT371: 5758 tim_pio = hpt372_pio; 5759 tim_dma = hpt372_dma; 5760 tim_udma = hpt372_udma; 5761 break; 5762 case PCI_PRODUCT_TRIONES_HPT374: 5763 tim_pio = hpt374_pio; 5764 tim_dma = hpt374_dma; 5765 tim_udma = hpt374_udma; 5766 break; 5767 default: 5768 printf("%s: no known timing values\n", 5769 sc->sc_wdcdev.sc_dev.dv_xname); 5770 goto end; 5771 } 5772 5773 /* Per drive settings */ 5774 for (drive = 0; drive < 2; drive++) { 5775 drvp = &chp->ch_drive[drive]; 5776 /* If no drive, skip */ 5777 if ((drvp->drive_flags & DRIVE) == 0) 5778 continue; 5779 before = pci_conf_read(sc->sc_pc, sc->sc_tag, 5780 HPT_IDETIM(chp->channel, drive)); 5781 5782 /* add timing values, setup DMA if needed */ 5783 if (drvp->drive_flags & DRIVE_UDMA) { 5784 /* use Ultra/DMA */ 5785 drvp->drive_flags &= ~DRIVE_DMA; 5786 if ((cable & HPT_CSEL_CBLID(chp->channel)) != 0 && 5787 drvp->UDMA_mode > 2) { 5788 WDCDEBUG_PRINT(("%s(%s:%d:%d): 80-wire " 5789 "cable not detected\n", drvp->drive_name, 5790 sc->sc_wdcdev.sc_dev.dv_xname, 5791 chp->channel, drive), DEBUG_PROBE); 5792 drvp->UDMA_mode = 2; 5793 } 5794 after = tim_udma[drvp->UDMA_mode]; 5795 idedma_ctl |= IDEDMA_CTL_DRV_DMA(drive); 5796 } else if (drvp->drive_flags & DRIVE_DMA) { 5797 /* 5798 * use Multiword DMA. 5799 * Timings will be used for both PIO and DMA, so adjust 5800 * DMA mode if needed 5801 */ 5802 if (drvp->PIO_mode >= 3 && 5803 (drvp->DMA_mode + 2) > drvp->PIO_mode) { 5804 drvp->DMA_mode = drvp->PIO_mode - 2; 5805 } 5806 after = tim_dma[drvp->DMA_mode]; 5807 idedma_ctl |= IDEDMA_CTL_DRV_DMA(drive); 5808 } else { 5809 /* PIO only */ 5810 after = tim_pio[drvp->PIO_mode]; 5811 } 5812 pci_conf_write(sc->sc_pc, sc->sc_tag, 5813 HPT_IDETIM(chp->channel, drive), after); 5814 WDCDEBUG_PRINT(("%s: bus speed register set to 0x%08x " 5815 "(BIOS 0x%08x)\n", sc->sc_wdcdev.sc_dev.dv_xname, 5816 after, before), DEBUG_PROBE); 5817 } 5818 end: 5819 if (idedma_ctl != 0) { 5820 /* Add software bits in status register */ 5821 bus_space_write_1(sc->sc_dma_iot, sc->sc_dma_ioh, 5822 IDEDMA_CTL(chp->channel), idedma_ctl); 5823 } 5824 pciide_print_modes(cp); 5825 } 5826 5827 int 5828 hpt_pci_intr(void *arg) 5829 { 5830 struct pciide_softc *sc = arg; 5831 struct pciide_channel *cp; 5832 struct channel_softc *wdc_cp; 5833 int rv = 0; 5834 int dmastat, i, crv; 5835 5836 for (i = 0; i < sc->sc_wdcdev.nchannels; i++) { 5837 dmastat = bus_space_read_1(sc->sc_dma_iot, sc->sc_dma_ioh, 5838 IDEDMA_CTL(i)); 5839 if((dmastat & (IDEDMA_CTL_ACT | IDEDMA_CTL_INTR)) != 5840 IDEDMA_CTL_INTR) 5841 continue; 5842 cp = &sc->pciide_channels[i]; 5843 wdc_cp = &cp->wdc_channel; 5844 crv = wdcintr(wdc_cp); 5845 if (crv == 0) { 5846 printf("%s:%d: bogus intr\n", 5847 sc->sc_wdcdev.sc_dev.dv_xname, i); 5848 bus_space_write_1(sc->sc_dma_iot, sc->sc_dma_ioh, 5849 IDEDMA_CTL(i), dmastat); 5850 } else 5851 rv = 1; 5852 } 5853 return (rv); 5854 } 5855 5856 /* Macros to test product */ 5857 #define PDC_IS_262(sc) \ 5858 ((sc)->sc_pp->ide_product == PCI_PRODUCT_PROMISE_PDC20262 || \ 5859 (sc)->sc_pp->ide_product == PCI_PRODUCT_PROMISE_PDC20265 || \ 5860 (sc)->sc_pp->ide_product == PCI_PRODUCT_PROMISE_PDC20267) 5861 #define PDC_IS_265(sc) \ 5862 ((sc)->sc_pp->ide_product == PCI_PRODUCT_PROMISE_PDC20265 || \ 5863 (sc)->sc_pp->ide_product == PCI_PRODUCT_PROMISE_PDC20267 || \ 5864 (sc)->sc_pp->ide_product == PCI_PRODUCT_PROMISE_PDC20268 || \ 5865 (sc)->sc_pp->ide_product == PCI_PRODUCT_PROMISE_PDC20268R || \ 5866 (sc)->sc_pp->ide_product == PCI_PRODUCT_PROMISE_PDC20269 || \ 5867 (sc)->sc_pp->ide_product == PCI_PRODUCT_PROMISE_PDC20271 || \ 5868 (sc)->sc_pp->ide_product == PCI_PRODUCT_PROMISE_PDC20275 || \ 5869 (sc)->sc_pp->ide_product == PCI_PRODUCT_PROMISE_PDC20276 || \ 5870 (sc)->sc_pp->ide_product == PCI_PRODUCT_PROMISE_PDC20277) 5871 #define PDC_IS_268(sc) \ 5872 ((sc)->sc_pp->ide_product == PCI_PRODUCT_PROMISE_PDC20268 || \ 5873 (sc)->sc_pp->ide_product == PCI_PRODUCT_PROMISE_PDC20268R || \ 5874 (sc)->sc_pp->ide_product == PCI_PRODUCT_PROMISE_PDC20269 || \ 5875 (sc)->sc_pp->ide_product == PCI_PRODUCT_PROMISE_PDC20271 || \ 5876 (sc)->sc_pp->ide_product == PCI_PRODUCT_PROMISE_PDC20275 || \ 5877 (sc)->sc_pp->ide_product == PCI_PRODUCT_PROMISE_PDC20276 || \ 5878 (sc)->sc_pp->ide_product == PCI_PRODUCT_PROMISE_PDC20277) 5879 #define PDC_IS_269(sc) \ 5880 ((sc)->sc_pp->ide_product == PCI_PRODUCT_PROMISE_PDC20269 || \ 5881 (sc)->sc_pp->ide_product == PCI_PRODUCT_PROMISE_PDC20271 || \ 5882 (sc)->sc_pp->ide_product == PCI_PRODUCT_PROMISE_PDC20275 || \ 5883 (sc)->sc_pp->ide_product == PCI_PRODUCT_PROMISE_PDC20276 || \ 5884 (sc)->sc_pp->ide_product == PCI_PRODUCT_PROMISE_PDC20277) 5885 5886 u_int8_t 5887 pdc268_config_read(struct channel_softc *chp, int index) 5888 { 5889 struct pciide_channel *cp = (struct pciide_channel *)chp; 5890 struct pciide_softc *sc = (struct pciide_softc *)cp->wdc_channel.wdc; 5891 int channel = chp->channel; 5892 5893 bus_space_write_1(sc->sc_dma_iot, sc->sc_dma_ioh, 5894 PDC268_INDEX(channel), index); 5895 return (bus_space_read_1(sc->sc_dma_iot, sc->sc_dma_ioh, 5896 PDC268_DATA(channel))); 5897 } 5898 5899 void 5900 pdc202xx_chip_map(struct pciide_softc *sc, struct pci_attach_args *pa) 5901 { 5902 struct pciide_channel *cp; 5903 int channel; 5904 pcireg_t interface, st, mode; 5905 bus_size_t cmdsize, ctlsize; 5906 5907 if (!PDC_IS_268(sc)) { 5908 st = pci_conf_read(sc->sc_pc, sc->sc_tag, PDC2xx_STATE); 5909 WDCDEBUG_PRINT(("pdc202xx_setup_chip: controller state 0x%x\n", 5910 st), DEBUG_PROBE); 5911 } 5912 5913 /* turn off RAID mode */ 5914 if (!PDC_IS_268(sc)) 5915 st &= ~PDC2xx_STATE_IDERAID; 5916 5917 /* 5918 * can't rely on the PCI_CLASS_REG content if the chip was in raid 5919 * mode. We have to fake interface 5920 */ 5921 interface = PCIIDE_INTERFACE_SETTABLE(0) | PCIIDE_INTERFACE_SETTABLE(1); 5922 if (PDC_IS_268(sc) || (st & PDC2xx_STATE_NATIVE)) 5923 interface |= PCIIDE_INTERFACE_PCI(0) | PCIIDE_INTERFACE_PCI(1); 5924 5925 printf(": DMA"); 5926 pciide_mapreg_dma(sc, pa); 5927 5928 sc->sc_wdcdev.cap = WDC_CAPABILITY_DATA16 | WDC_CAPABILITY_DATA32 | 5929 WDC_CAPABILITY_MODE; 5930 if (sc->sc_pp->ide_product == PCI_PRODUCT_PROMISE_PDC20246 || 5931 PDC_IS_262(sc)) 5932 sc->sc_wdcdev.cap |= WDC_CAPABILITY_NO_ATAPI_DMA; 5933 if (sc->sc_dma_ok) { 5934 sc->sc_wdcdev.cap |= WDC_CAPABILITY_DMA | WDC_CAPABILITY_UDMA; 5935 sc->sc_wdcdev.cap |= WDC_CAPABILITY_IRQACK; 5936 sc->sc_wdcdev.irqack = pciide_irqack; 5937 } 5938 sc->sc_wdcdev.PIO_cap = 4; 5939 sc->sc_wdcdev.DMA_cap = 2; 5940 if (PDC_IS_269(sc)) 5941 sc->sc_wdcdev.UDMA_cap = 6; 5942 else if (PDC_IS_265(sc)) 5943 sc->sc_wdcdev.UDMA_cap = 5; 5944 else if (PDC_IS_262(sc)) 5945 sc->sc_wdcdev.UDMA_cap = 4; 5946 else 5947 sc->sc_wdcdev.UDMA_cap = 2; 5948 sc->sc_wdcdev.set_modes = PDC_IS_268(sc) ? 5949 pdc20268_setup_channel : pdc202xx_setup_channel; 5950 sc->sc_wdcdev.channels = sc->wdc_chanarray; 5951 sc->sc_wdcdev.nchannels = PCIIDE_NUM_CHANNELS; 5952 5953 if (PDC_IS_262(sc)) { 5954 sc->sc_wdcdev.dma_start = pdc20262_dma_start; 5955 sc->sc_wdcdev.dma_finish = pdc20262_dma_finish; 5956 } 5957 5958 pciide_print_channels(sc->sc_wdcdev.nchannels, interface); 5959 if (!PDC_IS_268(sc)) { 5960 /* setup failsafe defaults */ 5961 mode = 0; 5962 mode = PDC2xx_TIM_SET_PA(mode, pdc2xx_pa[0]); 5963 mode = PDC2xx_TIM_SET_PB(mode, pdc2xx_pb[0]); 5964 mode = PDC2xx_TIM_SET_MB(mode, pdc2xx_dma_mb[0]); 5965 mode = PDC2xx_TIM_SET_MC(mode, pdc2xx_dma_mc[0]); 5966 for (channel = 0; 5967 channel < sc->sc_wdcdev.nchannels; 5968 channel++) { 5969 WDCDEBUG_PRINT(("pdc202xx_setup_chip: channel %d " 5970 "drive 0 initial timings 0x%x, now 0x%x\n", 5971 channel, pci_conf_read(sc->sc_pc, sc->sc_tag, 5972 PDC2xx_TIM(channel, 0)), mode | PDC2xx_TIM_IORDYp), 5973 DEBUG_PROBE); 5974 pci_conf_write(sc->sc_pc, sc->sc_tag, 5975 PDC2xx_TIM(channel, 0), mode | PDC2xx_TIM_IORDYp); 5976 WDCDEBUG_PRINT(("pdc202xx_setup_chip: channel %d " 5977 "drive 1 initial timings 0x%x, now 0x%x\n", 5978 channel, pci_conf_read(sc->sc_pc, sc->sc_tag, 5979 PDC2xx_TIM(channel, 1)), mode), DEBUG_PROBE); 5980 pci_conf_write(sc->sc_pc, sc->sc_tag, 5981 PDC2xx_TIM(channel, 1), mode); 5982 } 5983 5984 mode = PDC2xx_SCR_DMA; 5985 if (PDC_IS_262(sc)) { 5986 mode = PDC2xx_SCR_SET_GEN(mode, PDC262_SCR_GEN_LAT); 5987 } else { 5988 /* the BIOS set it up this way */ 5989 mode = PDC2xx_SCR_SET_GEN(mode, 0x1); 5990 } 5991 mode = PDC2xx_SCR_SET_I2C(mode, 0x3); /* ditto */ 5992 mode = PDC2xx_SCR_SET_POLL(mode, 0x1); /* ditto */ 5993 WDCDEBUG_PRINT(("pdc202xx_setup_chip: initial SCR 0x%x, " 5994 "now 0x%x\n", 5995 bus_space_read_4(sc->sc_dma_iot, sc->sc_dma_ioh, 5996 PDC2xx_SCR), 5997 mode), DEBUG_PROBE); 5998 bus_space_write_4(sc->sc_dma_iot, sc->sc_dma_ioh, 5999 PDC2xx_SCR, mode); 6000 6001 /* controller initial state register is OK even without BIOS */ 6002 /* Set DMA mode to IDE DMA compatibility */ 6003 mode = 6004 bus_space_read_1(sc->sc_dma_iot, sc->sc_dma_ioh, PDC2xx_PM); 6005 WDCDEBUG_PRINT(("pdc202xx_setup_chip: primary mode 0x%x", mode), 6006 DEBUG_PROBE); 6007 bus_space_write_1(sc->sc_dma_iot, sc->sc_dma_ioh, PDC2xx_PM, 6008 mode | 0x1); 6009 mode = 6010 bus_space_read_1(sc->sc_dma_iot, sc->sc_dma_ioh, PDC2xx_SM); 6011 WDCDEBUG_PRINT((", secondary mode 0x%x\n", mode ), DEBUG_PROBE); 6012 bus_space_write_1(sc->sc_dma_iot, sc->sc_dma_ioh, PDC2xx_SM, 6013 mode | 0x1); 6014 } 6015 6016 for (channel = 0; channel < sc->sc_wdcdev.nchannels; channel++) { 6017 cp = &sc->pciide_channels[channel]; 6018 if (pciide_chansetup(sc, channel, interface) == 0) 6019 continue; 6020 if (!PDC_IS_268(sc) && (st & (PDC_IS_262(sc) ? 6021 PDC262_STATE_EN(channel):PDC246_STATE_EN(channel))) == 0) { 6022 printf("%s: %s ignored (disabled)\n", 6023 sc->sc_wdcdev.sc_dev.dv_xname, cp->name); 6024 continue; 6025 } 6026 pciide_map_compat_intr(pa, cp, channel, interface); 6027 if (cp->hw_ok == 0) 6028 continue; 6029 if (PDC_IS_265(sc)) 6030 pciide_mapchan(pa, cp, interface, &cmdsize, &ctlsize, 6031 pdc20265_pci_intr); 6032 else 6033 pciide_mapchan(pa, cp, interface, &cmdsize, &ctlsize, 6034 pdc202xx_pci_intr); 6035 if (cp->hw_ok == 0) { 6036 pciide_unmap_compat_intr(pa, cp, channel, interface); 6037 continue; 6038 } 6039 if (!PDC_IS_268(sc) && pciide_chan_candisable(cp)) { 6040 st &= ~(PDC_IS_262(sc) ? 6041 PDC262_STATE_EN(channel):PDC246_STATE_EN(channel)); 6042 pciide_unmap_compat_intr(pa, cp, channel, interface); 6043 } 6044 if (PDC_IS_268(sc)) 6045 pdc20268_setup_channel(&cp->wdc_channel); 6046 else 6047 pdc202xx_setup_channel(&cp->wdc_channel); 6048 } 6049 if (!PDC_IS_268(sc)) { 6050 WDCDEBUG_PRINT(("pdc202xx_setup_chip: new controller state " 6051 "0x%x\n", st), DEBUG_PROBE); 6052 pci_conf_write(sc->sc_pc, sc->sc_tag, PDC2xx_STATE, st); 6053 } 6054 return; 6055 } 6056 6057 void 6058 pdc202xx_setup_channel(struct channel_softc *chp) 6059 { 6060 struct ata_drive_datas *drvp; 6061 int drive; 6062 pcireg_t mode, st; 6063 u_int32_t idedma_ctl, scr, atapi; 6064 struct pciide_channel *cp = (struct pciide_channel *)chp; 6065 struct pciide_softc *sc = (struct pciide_softc *)cp->wdc_channel.wdc; 6066 int channel = chp->channel; 6067 6068 /* setup DMA if needed */ 6069 pciide_channel_dma_setup(cp); 6070 6071 idedma_ctl = 0; 6072 WDCDEBUG_PRINT(("pdc202xx_setup_channel %s: scr 0x%x\n", 6073 sc->sc_wdcdev.sc_dev.dv_xname, 6074 bus_space_read_1(sc->sc_dma_iot, sc->sc_dma_ioh, PDC262_U66)), 6075 DEBUG_PROBE); 6076 6077 /* Per channel settings */ 6078 if (PDC_IS_262(sc)) { 6079 scr = bus_space_read_1(sc->sc_dma_iot, sc->sc_dma_ioh, 6080 PDC262_U66); 6081 st = pci_conf_read(sc->sc_pc, sc->sc_tag, PDC2xx_STATE); 6082 /* Check cable */ 6083 if ((st & PDC262_STATE_80P(channel)) != 0 && 6084 ((chp->ch_drive[0].drive_flags & DRIVE_UDMA && 6085 chp->ch_drive[0].UDMA_mode > 2) || 6086 (chp->ch_drive[1].drive_flags & DRIVE_UDMA && 6087 chp->ch_drive[1].UDMA_mode > 2))) { 6088 WDCDEBUG_PRINT(("%s:%d: 80-wire cable not detected\n", 6089 sc->sc_wdcdev.sc_dev.dv_xname, channel), 6090 DEBUG_PROBE); 6091 if (chp->ch_drive[0].UDMA_mode > 2) 6092 chp->ch_drive[0].UDMA_mode = 2; 6093 if (chp->ch_drive[1].UDMA_mode > 2) 6094 chp->ch_drive[1].UDMA_mode = 2; 6095 } 6096 /* Trim UDMA mode */ 6097 if ((chp->ch_drive[0].drive_flags & DRIVE_UDMA && 6098 chp->ch_drive[0].UDMA_mode <= 2) || 6099 (chp->ch_drive[1].drive_flags & DRIVE_UDMA && 6100 chp->ch_drive[1].UDMA_mode <= 2)) { 6101 if (chp->ch_drive[0].UDMA_mode > 2) 6102 chp->ch_drive[0].UDMA_mode = 2; 6103 if (chp->ch_drive[1].UDMA_mode > 2) 6104 chp->ch_drive[1].UDMA_mode = 2; 6105 } 6106 /* Set U66 if needed */ 6107 if ((chp->ch_drive[0].drive_flags & DRIVE_UDMA && 6108 chp->ch_drive[0].UDMA_mode > 2) || 6109 (chp->ch_drive[1].drive_flags & DRIVE_UDMA && 6110 chp->ch_drive[1].UDMA_mode > 2)) 6111 scr |= PDC262_U66_EN(channel); 6112 else 6113 scr &= ~PDC262_U66_EN(channel); 6114 bus_space_write_1(sc->sc_dma_iot, sc->sc_dma_ioh, 6115 PDC262_U66, scr); 6116 WDCDEBUG_PRINT(("pdc202xx_setup_channel %s:%d: ATAPI 0x%x\n", 6117 sc->sc_wdcdev.sc_dev.dv_xname, channel, 6118 bus_space_read_4(sc->sc_dma_iot, sc->sc_dma_ioh, 6119 PDC262_ATAPI(channel))), DEBUG_PROBE); 6120 if (chp->ch_drive[0].drive_flags & DRIVE_ATAPI || 6121 chp->ch_drive[1].drive_flags & DRIVE_ATAPI) { 6122 if (((chp->ch_drive[0].drive_flags & DRIVE_UDMA) && 6123 !(chp->ch_drive[1].drive_flags & DRIVE_UDMA) && 6124 (chp->ch_drive[1].drive_flags & DRIVE_DMA)) || 6125 ((chp->ch_drive[1].drive_flags & DRIVE_UDMA) && 6126 !(chp->ch_drive[0].drive_flags & DRIVE_UDMA) && 6127 (chp->ch_drive[0].drive_flags & DRIVE_DMA))) 6128 atapi = 0; 6129 else 6130 atapi = PDC262_ATAPI_UDMA; 6131 bus_space_write_4(sc->sc_dma_iot, sc->sc_dma_ioh, 6132 PDC262_ATAPI(channel), atapi); 6133 } 6134 } 6135 for (drive = 0; drive < 2; drive++) { 6136 drvp = &chp->ch_drive[drive]; 6137 /* If no drive, skip */ 6138 if ((drvp->drive_flags & DRIVE) == 0) 6139 continue; 6140 mode = 0; 6141 if (drvp->drive_flags & DRIVE_UDMA) { 6142 /* use Ultra/DMA */ 6143 drvp->drive_flags &= ~DRIVE_DMA; 6144 mode = PDC2xx_TIM_SET_MB(mode, 6145 pdc2xx_udma_mb[drvp->UDMA_mode]); 6146 mode = PDC2xx_TIM_SET_MC(mode, 6147 pdc2xx_udma_mc[drvp->UDMA_mode]); 6148 idedma_ctl |= IDEDMA_CTL_DRV_DMA(drive); 6149 } else if (drvp->drive_flags & DRIVE_DMA) { 6150 mode = PDC2xx_TIM_SET_MB(mode, 6151 pdc2xx_dma_mb[drvp->DMA_mode]); 6152 mode = PDC2xx_TIM_SET_MC(mode, 6153 pdc2xx_dma_mc[drvp->DMA_mode]); 6154 idedma_ctl |= IDEDMA_CTL_DRV_DMA(drive); 6155 } else { 6156 mode = PDC2xx_TIM_SET_MB(mode, 6157 pdc2xx_dma_mb[0]); 6158 mode = PDC2xx_TIM_SET_MC(mode, 6159 pdc2xx_dma_mc[0]); 6160 } 6161 mode = PDC2xx_TIM_SET_PA(mode, pdc2xx_pa[drvp->PIO_mode]); 6162 mode = PDC2xx_TIM_SET_PB(mode, pdc2xx_pb[drvp->PIO_mode]); 6163 if (drvp->drive_flags & DRIVE_ATA) 6164 mode |= PDC2xx_TIM_PRE; 6165 mode |= PDC2xx_TIM_SYNC | PDC2xx_TIM_ERRDY; 6166 if (drvp->PIO_mode >= 3) { 6167 mode |= PDC2xx_TIM_IORDY; 6168 if (drive == 0) 6169 mode |= PDC2xx_TIM_IORDYp; 6170 } 6171 WDCDEBUG_PRINT(("pdc202xx_setup_channel: %s:%d:%d " 6172 "timings 0x%x\n", 6173 sc->sc_wdcdev.sc_dev.dv_xname, 6174 chp->channel, drive, mode), DEBUG_PROBE); 6175 pci_conf_write(sc->sc_pc, sc->sc_tag, 6176 PDC2xx_TIM(chp->channel, drive), mode); 6177 } 6178 if (idedma_ctl != 0) { 6179 /* Add software bits in status register */ 6180 bus_space_write_1(sc->sc_dma_iot, sc->sc_dma_ioh, 6181 IDEDMA_CTL(channel), idedma_ctl); 6182 } 6183 pciide_print_modes(cp); 6184 } 6185 6186 void 6187 pdc20268_setup_channel(struct channel_softc *chp) 6188 { 6189 struct ata_drive_datas *drvp; 6190 int drive, cable; 6191 u_int32_t idedma_ctl; 6192 struct pciide_channel *cp = (struct pciide_channel *)chp; 6193 struct pciide_softc *sc = (struct pciide_softc *)cp->wdc_channel.wdc; 6194 int channel = chp->channel; 6195 6196 /* check 80 pins cable */ 6197 cable = pdc268_config_read(chp, 0x0b) & PDC268_CABLE; 6198 6199 /* setup DMA if needed */ 6200 pciide_channel_dma_setup(cp); 6201 6202 idedma_ctl = 0; 6203 6204 for (drive = 0; drive < 2; drive++) { 6205 drvp = &chp->ch_drive[drive]; 6206 /* If no drive, skip */ 6207 if ((drvp->drive_flags & DRIVE) == 0) 6208 continue; 6209 if (drvp->drive_flags & DRIVE_UDMA) { 6210 /* use Ultra/DMA */ 6211 drvp->drive_flags &= ~DRIVE_DMA; 6212 idedma_ctl |= IDEDMA_CTL_DRV_DMA(drive); 6213 if (cable && drvp->UDMA_mode > 2) { 6214 WDCDEBUG_PRINT(("%s(%s:%d:%d): 80-wire " 6215 "cable not detected\n", drvp->drive_name, 6216 sc->sc_wdcdev.sc_dev.dv_xname, 6217 channel, drive), DEBUG_PROBE); 6218 drvp->UDMA_mode = 2; 6219 } 6220 } else if (drvp->drive_flags & DRIVE_DMA) { 6221 idedma_ctl |= IDEDMA_CTL_DRV_DMA(drive); 6222 } 6223 } 6224 /* nothing to do to setup modes, the controller snoop SET_FEATURE cmd */ 6225 if (idedma_ctl != 0) { 6226 /* Add software bits in status register */ 6227 bus_space_write_1(sc->sc_dma_iot, sc->sc_dma_ioh, 6228 IDEDMA_CTL(channel), idedma_ctl); 6229 } 6230 pciide_print_modes(cp); 6231 } 6232 6233 int 6234 pdc202xx_pci_intr(void *arg) 6235 { 6236 struct pciide_softc *sc = arg; 6237 struct pciide_channel *cp; 6238 struct channel_softc *wdc_cp; 6239 int i, rv, crv; 6240 u_int32_t scr; 6241 6242 rv = 0; 6243 scr = bus_space_read_4(sc->sc_dma_iot, sc->sc_dma_ioh, PDC2xx_SCR); 6244 for (i = 0; i < sc->sc_wdcdev.nchannels; i++) { 6245 cp = &sc->pciide_channels[i]; 6246 wdc_cp = &cp->wdc_channel; 6247 /* If a compat channel skip. */ 6248 if (cp->compat) 6249 continue; 6250 if (scr & PDC2xx_SCR_INT(i)) { 6251 crv = wdcintr(wdc_cp); 6252 if (crv == 0) 6253 printf("%s:%d: bogus intr (reg 0x%x)\n", 6254 sc->sc_wdcdev.sc_dev.dv_xname, i, scr); 6255 else 6256 rv = 1; 6257 } 6258 } 6259 return (rv); 6260 } 6261 6262 int 6263 pdc20265_pci_intr(void *arg) 6264 { 6265 struct pciide_softc *sc = arg; 6266 struct pciide_channel *cp; 6267 struct channel_softc *wdc_cp; 6268 int i, rv, crv; 6269 u_int32_t dmastat; 6270 6271 rv = 0; 6272 for (i = 0; i < sc->sc_wdcdev.nchannels; i++) { 6273 cp = &sc->pciide_channels[i]; 6274 wdc_cp = &cp->wdc_channel; 6275 /* If a compat channel skip. */ 6276 if (cp->compat) 6277 continue; 6278 6279 /* 6280 * In case of shared IRQ check that the interrupt 6281 * was actually generated by this channel. 6282 * Only check the channel that is enabled. 6283 */ 6284 if (cp->hw_ok && PDC_IS_268(sc)) { 6285 if ((pdc268_config_read(wdc_cp, 6286 0x0b) & PDC268_INTR) == 0) 6287 continue; 6288 } 6289 6290 /* 6291 * The Ultra/100 seems to assert PDC2xx_SCR_INT * spuriously, 6292 * however it asserts INT in IDEDMA_CTL even for non-DMA ops. 6293 * So use it instead (requires 2 reg reads instead of 1, 6294 * but we can't do it another way). 6295 */ 6296 dmastat = bus_space_read_1(sc->sc_dma_iot, 6297 sc->sc_dma_ioh, IDEDMA_CTL(i)); 6298 if ((dmastat & IDEDMA_CTL_INTR) == 0) 6299 continue; 6300 6301 crv = wdcintr(wdc_cp); 6302 if (crv == 0) 6303 printf("%s:%d: bogus intr\n", 6304 sc->sc_wdcdev.sc_dev.dv_xname, i); 6305 else 6306 rv = 1; 6307 } 6308 return (rv); 6309 } 6310 6311 void 6312 pdc20262_dma_start(void *v, int channel, int drive) 6313 { 6314 struct pciide_softc *sc = v; 6315 struct pciide_dma_maps *dma_maps = 6316 &sc->pciide_channels[channel].dma_maps[drive]; 6317 u_int8_t clock; 6318 u_int32_t count; 6319 6320 if (dma_maps->dma_flags & WDC_DMA_LBA48) { 6321 clock = bus_space_read_1(sc->sc_dma_iot, sc->sc_dma_ioh, 6322 PDC262_U66); 6323 bus_space_write_1(sc->sc_dma_iot, sc->sc_dma_ioh, 6324 PDC262_U66, clock | PDC262_U66_EN(channel)); 6325 count = dma_maps->dmamap_xfer->dm_mapsize >> 1; 6326 count |= dma_maps->dma_flags & WDC_DMA_READ ? 6327 PDC262_ATAPI_LBA48_READ : PDC262_ATAPI_LBA48_WRITE; 6328 bus_space_write_4(sc->sc_dma_iot, sc->sc_dma_ioh, 6329 PDC262_ATAPI(channel), count); 6330 } 6331 6332 pciide_dma_start(v, channel, drive); 6333 } 6334 6335 int 6336 pdc20262_dma_finish(void *v, int channel, int drive, int force) 6337 { 6338 struct pciide_softc *sc = v; 6339 struct pciide_dma_maps *dma_maps = 6340 &sc->pciide_channels[channel].dma_maps[drive]; 6341 u_int8_t clock; 6342 6343 if (dma_maps->dma_flags & WDC_DMA_LBA48) { 6344 clock = bus_space_read_1(sc->sc_dma_iot, sc->sc_dma_ioh, 6345 PDC262_U66); 6346 bus_space_write_1(sc->sc_dma_iot, sc->sc_dma_ioh, 6347 PDC262_U66, clock & ~PDC262_U66_EN(channel)); 6348 bus_space_write_4(sc->sc_dma_iot, sc->sc_dma_ioh, 6349 PDC262_ATAPI(channel), 0); 6350 } 6351 6352 return (pciide_dma_finish(v, channel, drive, force)); 6353 } 6354 6355 void 6356 pdcsata_chip_map(struct pciide_softc *sc, struct pci_attach_args *pa) 6357 { 6358 struct pciide_channel *cp; 6359 struct channel_softc *wdc_cp; 6360 struct pciide_pdcsata *ps; 6361 int channel, i; 6362 bus_size_t dmasize; 6363 pci_intr_handle_t intrhandle; 6364 const char *intrstr; 6365 6366 /* Allocate memory for private data */ 6367 sc->sc_cookie = malloc(sizeof(*ps), M_DEVBUF, M_NOWAIT | M_ZERO); 6368 ps = sc->sc_cookie; 6369 6370 /* 6371 * Promise SATA controllers have 3 or 4 channels, 6372 * the usual IDE registers are mapped in I/O space, with offsets. 6373 */ 6374 if (pci_intr_map(pa, &intrhandle) != 0) { 6375 printf(": couldn't map interrupt\n"); 6376 return; 6377 } 6378 intrstr = pci_intr_string(pa->pa_pc, intrhandle); 6379 6380 switch (sc->sc_pp->ide_product) { 6381 case PCI_PRODUCT_PROMISE_PDC20318: 6382 case PCI_PRODUCT_PROMISE_PDC20319: 6383 case PCI_PRODUCT_PROMISE_PDC20371: 6384 case PCI_PRODUCT_PROMISE_PDC20375: 6385 case PCI_PRODUCT_PROMISE_PDC20376: 6386 case PCI_PRODUCT_PROMISE_PDC20377: 6387 case PCI_PRODUCT_PROMISE_PDC20378: 6388 case PCI_PRODUCT_PROMISE_PDC20379: 6389 default: 6390 sc->sc_pci_ih = pci_intr_establish(pa->pa_pc, 6391 intrhandle, IPL_BIO, pdc203xx_pci_intr, sc, 6392 sc->sc_wdcdev.sc_dev.dv_xname); 6393 break; 6394 6395 case PCI_PRODUCT_PROMISE_PDC40518: 6396 case PCI_PRODUCT_PROMISE_PDC40519: 6397 case PCI_PRODUCT_PROMISE_PDC40718: 6398 case PCI_PRODUCT_PROMISE_PDC40719: 6399 case PCI_PRODUCT_PROMISE_PDC40779: 6400 case PCI_PRODUCT_PROMISE_PDC20571: 6401 case PCI_PRODUCT_PROMISE_PDC20575: 6402 case PCI_PRODUCT_PROMISE_PDC20579: 6403 case PCI_PRODUCT_PROMISE_PDC20771: 6404 case PCI_PRODUCT_PROMISE_PDC20775: 6405 sc->sc_pci_ih = pci_intr_establish(pa->pa_pc, 6406 intrhandle, IPL_BIO, pdc205xx_pci_intr, sc, 6407 sc->sc_wdcdev.sc_dev.dv_xname); 6408 break; 6409 } 6410 6411 if (sc->sc_pci_ih == NULL) { 6412 printf(": couldn't establish native-PCI interrupt"); 6413 if (intrstr != NULL) 6414 printf(" at %s", intrstr); 6415 printf("\n"); 6416 return; 6417 } 6418 6419 sc->sc_dma_ok = (pci_mapreg_map(pa, PCIIDE_REG_BUS_MASTER_DMA, 6420 PCI_MAPREG_MEM_TYPE_32BIT, 0, &sc->sc_dma_iot, 6421 &sc->sc_dma_ioh, NULL, &dmasize, 0) == 0); 6422 if (!sc->sc_dma_ok) { 6423 printf(": couldn't map bus-master DMA registers\n"); 6424 pci_intr_disestablish(pa->pa_pc, sc->sc_pci_ih); 6425 return; 6426 } 6427 6428 sc->sc_dmat = pa->pa_dmat; 6429 6430 if (pci_mapreg_map(pa, PDC203xx_BAR_IDEREGS, 6431 PCI_MAPREG_MEM_TYPE_32BIT, 0, &ps->ba5_st, 6432 &ps->ba5_sh, NULL, NULL, 0) != 0) { 6433 printf(": couldn't map IDE registers\n"); 6434 bus_space_unmap(sc->sc_dma_iot, sc->sc_dma_ioh, dmasize); 6435 pci_intr_disestablish(pa->pa_pc, sc->sc_pci_ih); 6436 return; 6437 } 6438 6439 printf(": DMA\n"); 6440 6441 sc->sc_wdcdev.cap = WDC_CAPABILITY_DATA16; 6442 sc->sc_wdcdev.cap |= WDC_CAPABILITY_DMA | WDC_CAPABILITY_UDMA; 6443 sc->sc_wdcdev.cap |= WDC_CAPABILITY_IRQACK; 6444 sc->sc_wdcdev.irqack = pdc203xx_irqack; 6445 sc->sc_wdcdev.PIO_cap = 4; 6446 sc->sc_wdcdev.DMA_cap = 2; 6447 sc->sc_wdcdev.UDMA_cap = 6; 6448 sc->sc_wdcdev.set_modes = pdc203xx_setup_channel; 6449 sc->sc_wdcdev.channels = sc->wdc_chanarray; 6450 6451 switch (sc->sc_pp->ide_product) { 6452 case PCI_PRODUCT_PROMISE_PDC20318: 6453 case PCI_PRODUCT_PROMISE_PDC20319: 6454 case PCI_PRODUCT_PROMISE_PDC20371: 6455 case PCI_PRODUCT_PROMISE_PDC20375: 6456 case PCI_PRODUCT_PROMISE_PDC20376: 6457 case PCI_PRODUCT_PROMISE_PDC20377: 6458 case PCI_PRODUCT_PROMISE_PDC20378: 6459 case PCI_PRODUCT_PROMISE_PDC20379: 6460 default: 6461 bus_space_write_4(ps->ba5_st, ps->ba5_sh, 0x06c, 0x00ff0033); 6462 sc->sc_wdcdev.nchannels = 6463 (bus_space_read_4(ps->ba5_st, ps->ba5_sh, 0x48) & 0x02) ? 6464 PDC203xx_NCHANNELS : 3; 6465 break; 6466 6467 case PCI_PRODUCT_PROMISE_PDC40518: 6468 case PCI_PRODUCT_PROMISE_PDC40519: 6469 case PCI_PRODUCT_PROMISE_PDC40718: 6470 case PCI_PRODUCT_PROMISE_PDC40719: 6471 case PCI_PRODUCT_PROMISE_PDC40779: 6472 case PCI_PRODUCT_PROMISE_PDC20571: 6473 bus_space_write_4(ps->ba5_st, ps->ba5_sh, 0x60, 0x00ff00ff); 6474 sc->sc_wdcdev.nchannels = PDC40718_NCHANNELS; 6475 6476 sc->sc_wdcdev.reset = pdc205xx_do_reset; 6477 sc->sc_wdcdev.drv_probe = pdc205xx_drv_probe; 6478 6479 break; 6480 case PCI_PRODUCT_PROMISE_PDC20575: 6481 case PCI_PRODUCT_PROMISE_PDC20579: 6482 case PCI_PRODUCT_PROMISE_PDC20771: 6483 case PCI_PRODUCT_PROMISE_PDC20775: 6484 bus_space_write_4(ps->ba5_st, ps->ba5_sh, 0x60, 0x00ff00ff); 6485 sc->sc_wdcdev.nchannels = PDC20575_NCHANNELS; 6486 6487 sc->sc_wdcdev.reset = pdc205xx_do_reset; 6488 sc->sc_wdcdev.drv_probe = pdc205xx_drv_probe; 6489 6490 break; 6491 } 6492 6493 sc->sc_wdcdev.dma_arg = sc; 6494 sc->sc_wdcdev.dma_init = pciide_dma_init; 6495 sc->sc_wdcdev.dma_start = pdc203xx_dma_start; 6496 sc->sc_wdcdev.dma_finish = pdc203xx_dma_finish; 6497 6498 for (channel = 0; channel < sc->sc_wdcdev.nchannels; 6499 channel++) { 6500 cp = &sc->pciide_channels[channel]; 6501 sc->wdc_chanarray[channel] = &cp->wdc_channel; 6502 6503 cp->ih = sc->sc_pci_ih; 6504 cp->name = NULL; 6505 cp->wdc_channel.channel = channel; 6506 cp->wdc_channel.wdc = &sc->sc_wdcdev; 6507 cp->wdc_channel.ch_queue = 6508 malloc(sizeof(struct channel_queue), M_DEVBUF, M_NOWAIT); 6509 if (cp->wdc_channel.ch_queue == NULL) { 6510 printf("%s: channel %d: " 6511 "can't allocate memory for command queue\n", 6512 sc->sc_wdcdev.sc_dev.dv_xname, channel); 6513 continue; 6514 } 6515 wdc_cp = &cp->wdc_channel; 6516 6517 ps->regs[channel].ctl_iot = ps->ba5_st; 6518 ps->regs[channel].cmd_iot = ps->ba5_st; 6519 6520 if (bus_space_subregion(ps->ba5_st, ps->ba5_sh, 6521 0x0238 + (channel << 7), 1, 6522 &ps->regs[channel].ctl_ioh) != 0) { 6523 printf("%s: couldn't map channel %d ctl regs\n", 6524 sc->sc_wdcdev.sc_dev.dv_xname, 6525 channel); 6526 continue; 6527 } 6528 for (i = 0; i < WDC_NREG; i++) { 6529 if (bus_space_subregion(ps->ba5_st, ps->ba5_sh, 6530 0x0200 + (i << 2) + (channel << 7), i == 0 ? 4 : 1, 6531 &ps->regs[channel].cmd_iohs[i]) != 0) { 6532 printf("%s: couldn't map channel %d cmd " 6533 "regs\n", 6534 sc->sc_wdcdev.sc_dev.dv_xname, 6535 channel); 6536 continue; 6537 } 6538 } 6539 ps->regs[channel].cmd_iohs[wdr_status & _WDC_REGMASK] = 6540 ps->regs[channel].cmd_iohs[wdr_command & _WDC_REGMASK]; 6541 ps->regs[channel].cmd_iohs[wdr_features & _WDC_REGMASK] = 6542 ps->regs[channel].cmd_iohs[wdr_error & _WDC_REGMASK]; 6543 wdc_cp->data32iot = wdc_cp->cmd_iot = 6544 ps->regs[channel].cmd_iot; 6545 wdc_cp->data32ioh = wdc_cp->cmd_ioh = 6546 ps->regs[channel].cmd_iohs[0]; 6547 wdc_cp->_vtbl = &wdc_pdc203xx_vtbl; 6548 6549 /* 6550 * Subregion de busmaster registers. They're spread all over 6551 * the controller's register space :(. They are also 4 bytes 6552 * sized, with some specific extentions in the extra bits. 6553 * It also seems that the IDEDMA_CTL register isn't available. 6554 */ 6555 if (bus_space_subregion(ps->ba5_st, ps->ba5_sh, 6556 0x260 + (channel << 7), 1, 6557 &ps->regs[channel].dma_iohs[IDEDMA_CMD(0)]) != 0) { 6558 printf("%s channel %d: can't subregion DMA " 6559 "registers\n", 6560 sc->sc_wdcdev.sc_dev.dv_xname, channel); 6561 continue; 6562 } 6563 if (bus_space_subregion(ps->ba5_st, ps->ba5_sh, 6564 0x244 + (channel << 7), 4, 6565 &ps->regs[channel].dma_iohs[IDEDMA_TBL(0)]) != 0) { 6566 printf("%s channel %d: can't subregion DMA " 6567 "registers\n", 6568 sc->sc_wdcdev.sc_dev.dv_xname, channel); 6569 continue; 6570 } 6571 6572 wdcattach(wdc_cp); 6573 bus_space_write_4(sc->sc_dma_iot, 6574 ps->regs[channel].dma_iohs[IDEDMA_CMD(0)], 0, 6575 (bus_space_read_4(sc->sc_dma_iot, 6576 ps->regs[channel].dma_iohs[IDEDMA_CMD(0)], 6577 0) & ~0x00003f9f) | (channel + 1)); 6578 bus_space_write_4(ps->ba5_st, ps->ba5_sh, 6579 (channel + 1) << 2, 0x00000001); 6580 6581 pdc203xx_setup_channel(&cp->wdc_channel); 6582 } 6583 6584 printf("%s: using %s for native-PCI interrupt\n", 6585 sc->sc_wdcdev.sc_dev.dv_xname, 6586 intrstr ? intrstr : "unknown interrupt"); 6587 } 6588 6589 void 6590 pdc203xx_setup_channel(struct channel_softc *chp) 6591 { 6592 struct ata_drive_datas *drvp; 6593 struct pciide_channel *cp = (struct pciide_channel *)chp; 6594 int drive, s; 6595 6596 pciide_channel_dma_setup(cp); 6597 6598 for (drive = 0; drive < 2; drive++) { 6599 drvp = &chp->ch_drive[drive]; 6600 if ((drvp->drive_flags & DRIVE) == 0) 6601 continue; 6602 if (drvp->drive_flags & DRIVE_UDMA) { 6603 s = splbio(); 6604 drvp->drive_flags &= ~DRIVE_DMA; 6605 splx(s); 6606 } 6607 } 6608 pciide_print_modes(cp); 6609 } 6610 6611 int 6612 pdc203xx_pci_intr(void *arg) 6613 { 6614 struct pciide_softc *sc = arg; 6615 struct pciide_channel *cp; 6616 struct channel_softc *wdc_cp; 6617 struct pciide_pdcsata *ps = sc->sc_cookie; 6618 int i, rv, crv; 6619 u_int32_t scr; 6620 6621 rv = 0; 6622 scr = bus_space_read_4(ps->ba5_st, ps->ba5_sh, 0x00040); 6623 6624 for (i = 0; i < sc->sc_wdcdev.nchannels; i++) { 6625 cp = &sc->pciide_channels[i]; 6626 wdc_cp = &cp->wdc_channel; 6627 if (scr & (1 << (i + 1))) { 6628 crv = wdcintr(wdc_cp); 6629 if (crv == 0) { 6630 printf("%s:%d: bogus intr (reg 0x%x)\n", 6631 sc->sc_wdcdev.sc_dev.dv_xname, 6632 i, scr); 6633 } else 6634 rv = 1; 6635 } 6636 } 6637 6638 return (rv); 6639 } 6640 6641 int 6642 pdc205xx_pci_intr(void *arg) 6643 { 6644 struct pciide_softc *sc = arg; 6645 struct pciide_channel *cp; 6646 struct channel_softc *wdc_cp; 6647 struct pciide_pdcsata *ps = sc->sc_cookie; 6648 int i, rv, crv; 6649 u_int32_t scr, status; 6650 6651 rv = 0; 6652 scr = bus_space_read_4(ps->ba5_st, ps->ba5_sh, 0x40); 6653 bus_space_write_4(ps->ba5_st, ps->ba5_sh, 0x40, scr & 0x0000ffff); 6654 6655 status = bus_space_read_4(ps->ba5_st, ps->ba5_sh, 0x60); 6656 bus_space_write_4(ps->ba5_st, ps->ba5_sh, 0x60, status & 0x000000ff); 6657 6658 for (i = 0; i < sc->sc_wdcdev.nchannels; i++) { 6659 cp = &sc->pciide_channels[i]; 6660 wdc_cp = &cp->wdc_channel; 6661 if (scr & (1 << (i + 1))) { 6662 crv = wdcintr(wdc_cp); 6663 if (crv == 0) { 6664 printf("%s:%d: bogus intr (reg 0x%x)\n", 6665 sc->sc_wdcdev.sc_dev.dv_xname, 6666 i, scr); 6667 } else 6668 rv = 1; 6669 } 6670 } 6671 return rv; 6672 } 6673 6674 void 6675 pdc203xx_irqack(struct channel_softc *chp) 6676 { 6677 struct pciide_channel *cp = (struct pciide_channel *)chp; 6678 struct pciide_softc *sc = (struct pciide_softc *)cp->wdc_channel.wdc; 6679 struct pciide_pdcsata *ps = sc->sc_cookie; 6680 int chan = chp->channel; 6681 6682 bus_space_write_4(sc->sc_dma_iot, 6683 ps->regs[chan].dma_iohs[IDEDMA_CMD(0)], 0, 6684 (bus_space_read_4(sc->sc_dma_iot, 6685 ps->regs[chan].dma_iohs[IDEDMA_CMD(0)], 6686 0) & ~0x00003f9f) | (chan + 1)); 6687 bus_space_write_4(ps->ba5_st, ps->ba5_sh, 6688 (chan + 1) << 2, 0x00000001); 6689 } 6690 6691 void 6692 pdc203xx_dma_start(void *v, int channel, int drive) 6693 { 6694 struct pciide_softc *sc = v; 6695 struct pciide_channel *cp = &sc->pciide_channels[channel]; 6696 struct pciide_dma_maps *dma_maps = &cp->dma_maps[drive]; 6697 struct pciide_pdcsata *ps = sc->sc_cookie; 6698 6699 /* Write table address */ 6700 bus_space_write_4(sc->sc_dma_iot, 6701 ps->regs[channel].dma_iohs[IDEDMA_TBL(0)], 0, 6702 dma_maps->dmamap_table->dm_segs[0].ds_addr); 6703 6704 /* Start DMA engine */ 6705 bus_space_write_4(sc->sc_dma_iot, 6706 ps->regs[channel].dma_iohs[IDEDMA_CMD(0)], 0, 6707 (bus_space_read_4(sc->sc_dma_iot, 6708 ps->regs[channel].dma_iohs[IDEDMA_CMD(0)], 6709 0) & ~0xc0) | ((dma_maps->dma_flags & WDC_DMA_READ) ? 0x80 : 0xc0)); 6710 } 6711 6712 int 6713 pdc203xx_dma_finish(void *v, int channel, int drive, int force) 6714 { 6715 struct pciide_softc *sc = v; 6716 struct pciide_channel *cp = &sc->pciide_channels[channel]; 6717 struct pciide_dma_maps *dma_maps = &cp->dma_maps[drive]; 6718 struct pciide_pdcsata *ps = sc->sc_cookie; 6719 6720 /* Stop DMA channel */ 6721 bus_space_write_4(sc->sc_dma_iot, 6722 ps->regs[channel].dma_iohs[IDEDMA_CMD(0)], 0, 6723 (bus_space_read_4(sc->sc_dma_iot, 6724 ps->regs[channel].dma_iohs[IDEDMA_CMD(0)], 6725 0) & ~0x80)); 6726 6727 /* Unload the map of the data buffer */ 6728 bus_dmamap_sync(sc->sc_dmat, dma_maps->dmamap_xfer, 0, 6729 dma_maps->dmamap_xfer->dm_mapsize, 6730 (dma_maps->dma_flags & WDC_DMA_READ) ? 6731 BUS_DMASYNC_POSTREAD : BUS_DMASYNC_POSTWRITE); 6732 bus_dmamap_unload(sc->sc_dmat, dma_maps->dmamap_xfer); 6733 6734 return (0); 6735 } 6736 6737 u_int8_t 6738 pdc203xx_read_reg(struct channel_softc *chp, enum wdc_regs reg) 6739 { 6740 struct pciide_channel *cp = (struct pciide_channel *)chp; 6741 struct pciide_softc *sc = (struct pciide_softc *)cp->wdc_channel.wdc; 6742 struct pciide_pdcsata *ps = sc->sc_cookie; 6743 u_int8_t val; 6744 6745 if (reg & _WDC_AUX) { 6746 return (bus_space_read_1(ps->regs[chp->channel].ctl_iot, 6747 ps->regs[chp->channel].ctl_ioh, reg & _WDC_REGMASK)); 6748 } else { 6749 val = bus_space_read_1(ps->regs[chp->channel].cmd_iot, 6750 ps->regs[chp->channel].cmd_iohs[reg & _WDC_REGMASK], 0); 6751 return (val); 6752 } 6753 } 6754 6755 void 6756 pdc203xx_write_reg(struct channel_softc *chp, enum wdc_regs reg, u_int8_t val) 6757 { 6758 struct pciide_channel *cp = (struct pciide_channel *)chp; 6759 struct pciide_softc *sc = (struct pciide_softc *)cp->wdc_channel.wdc; 6760 struct pciide_pdcsata *ps = sc->sc_cookie; 6761 6762 if (reg & _WDC_AUX) 6763 bus_space_write_1(ps->regs[chp->channel].ctl_iot, 6764 ps->regs[chp->channel].ctl_ioh, reg & _WDC_REGMASK, val); 6765 else 6766 bus_space_write_1(ps->regs[chp->channel].cmd_iot, 6767 ps->regs[chp->channel].cmd_iohs[reg & _WDC_REGMASK], 6768 0, val); 6769 } 6770 6771 void 6772 pdc205xx_do_reset(struct channel_softc *chp) 6773 { 6774 struct pciide_channel *cp = (struct pciide_channel *)chp; 6775 struct pciide_softc *sc = (struct pciide_softc *)cp->wdc_channel.wdc; 6776 struct pciide_pdcsata *ps = sc->sc_cookie; 6777 u_int32_t scontrol; 6778 6779 wdc_do_reset(chp); 6780 6781 /* reset SATA */ 6782 scontrol = SControl_DET_INIT | SControl_SPD_ANY | SControl_IPM_NONE; 6783 SCONTROL_WRITE(ps, chp->channel, scontrol); 6784 delay(50*1000); 6785 6786 scontrol &= ~SControl_DET_INIT; 6787 SCONTROL_WRITE(ps, chp->channel, scontrol); 6788 delay(50*1000); 6789 } 6790 6791 void 6792 pdc205xx_drv_probe(struct channel_softc *chp) 6793 { 6794 struct pciide_channel *cp = (struct pciide_channel *)chp; 6795 struct pciide_softc *sc = (struct pciide_softc *)cp->wdc_channel.wdc; 6796 struct pciide_pdcsata *ps = sc->sc_cookie; 6797 bus_space_handle_t *iohs; 6798 u_int32_t scontrol, sstatus; 6799 u_int16_t scnt, sn, cl, ch; 6800 int i, s; 6801 6802 /* XXX This should be done by other code. */ 6803 for (i = 0; i < 2; i++) { 6804 chp->ch_drive[i].chnl_softc = chp; 6805 chp->ch_drive[i].drive = i; 6806 } 6807 6808 SCONTROL_WRITE(ps, chp->channel, 0); 6809 delay(50*1000); 6810 6811 scontrol = SControl_DET_INIT | SControl_SPD_ANY | SControl_IPM_NONE; 6812 SCONTROL_WRITE(ps,chp->channel,scontrol); 6813 delay(50*1000); 6814 6815 scontrol &= ~SControl_DET_INIT; 6816 SCONTROL_WRITE(ps,chp->channel,scontrol); 6817 delay(50*1000); 6818 6819 sstatus = SSTATUS_READ(ps,chp->channel); 6820 6821 switch (sstatus & SStatus_DET_mask) { 6822 case SStatus_DET_NODEV: 6823 /* No Device; be silent. */ 6824 break; 6825 6826 case SStatus_DET_DEV_NE: 6827 printf("%s: port %d: device connected, but " 6828 "communication not established\n", 6829 sc->sc_wdcdev.sc_dev.dv_xname, chp->channel); 6830 break; 6831 6832 case SStatus_DET_OFFLINE: 6833 printf("%s: port %d: PHY offline\n", 6834 sc->sc_wdcdev.sc_dev.dv_xname, chp->channel); 6835 break; 6836 6837 case SStatus_DET_DEV: 6838 iohs = ps->regs[chp->channel].cmd_iohs; 6839 bus_space_write_1(chp->cmd_iot, iohs[wdr_sdh], 0, 6840 WDSD_IBM); 6841 delay(10); /* 400ns delay */ 6842 scnt = bus_space_read_2(chp->cmd_iot, iohs[wdr_seccnt], 0); 6843 sn = bus_space_read_2(chp->cmd_iot, iohs[wdr_sector], 0); 6844 cl = bus_space_read_2(chp->cmd_iot, iohs[wdr_cyl_lo], 0); 6845 ch = bus_space_read_2(chp->cmd_iot, iohs[wdr_cyl_hi], 0); 6846 #if 0 6847 printf("%s: port %d: scnt=0x%x sn=0x%x cl=0x%x ch=0x%x\n", 6848 sc->sc_wdcdev.sc_dev.dv_xname, chp->channel, 6849 scnt, sn, cl, ch); 6850 #endif 6851 /* 6852 * scnt and sn are supposed to be 0x1 for ATAPI, but in some 6853 * cases we get wrong values here, so ignore it. 6854 */ 6855 s = splbio(); 6856 if (cl == 0x14 && ch == 0xeb) 6857 chp->ch_drive[0].drive_flags |= DRIVE_ATAPI; 6858 else 6859 chp->ch_drive[0].drive_flags |= DRIVE_ATA; 6860 splx(s); 6861 #if 0 6862 printf("%s: port %d: device present", 6863 sc->sc_wdcdev.sc_dev.dv_xname, chp->channel); 6864 switch ((sstatus & SStatus_SPD_mask) >> SStatus_SPD_shift) { 6865 case 1: 6866 printf(", speed: 1.5Gb/s"); 6867 break; 6868 case 2: 6869 printf(", speed: 3.0Gb/s"); 6870 break; 6871 } 6872 printf("\n"); 6873 #endif 6874 break; 6875 6876 default: 6877 printf("%s: port %d: unknown SStatus: 0x%08x\n", 6878 sc->sc_wdcdev.sc_dev.dv_xname, chp->channel, sstatus); 6879 } 6880 } 6881 6882 #ifdef notyet 6883 /* 6884 * Inline functions for accessing the timing registers of the 6885 * OPTi controller. 6886 * 6887 * These *MUST* disable interrupts as they need atomic access to 6888 * certain magic registers. Failure to adhere to this *will* 6889 * break things in subtle ways if the wdc registers are accessed 6890 * by an interrupt routine while this magic sequence is executing. 6891 */ 6892 static __inline__ u_int8_t 6893 opti_read_config(struct channel_softc *chp, int reg) 6894 { 6895 u_int8_t rv; 6896 int s = splhigh(); 6897 6898 /* Two consecutive 16-bit reads from register #1 (0x1f1/0x171) */ 6899 (void) bus_space_read_2(chp->cmd_iot, chp->cmd_ioh, wdr_features); 6900 (void) bus_space_read_2(chp->cmd_iot, chp->cmd_ioh, wdr_features); 6901 6902 /* Followed by an 8-bit write of 0x3 to register #2 */ 6903 bus_space_write_1(chp->cmd_iot, chp->cmd_ioh, wdr_seccnt, 0x03u); 6904 6905 /* Now we can read the required register */ 6906 rv = bus_space_read_1(chp->cmd_iot, chp->cmd_ioh, reg); 6907 6908 /* Restore the real registers */ 6909 bus_space_write_1(chp->cmd_iot, chp->cmd_ioh, wdr_seccnt, 0x83u); 6910 6911 splx(s); 6912 6913 return (rv); 6914 } 6915 6916 static __inline__ void 6917 opti_write_config(struct channel_softc *chp, int reg, u_int8_t val) 6918 { 6919 int s = splhigh(); 6920 6921 /* Two consecutive 16-bit reads from register #1 (0x1f1/0x171) */ 6922 (void) bus_space_read_2(chp->cmd_iot, chp->cmd_ioh, wdr_features); 6923 (void) bus_space_read_2(chp->cmd_iot, chp->cmd_ioh, wdr_features); 6924 6925 /* Followed by an 8-bit write of 0x3 to register #2 */ 6926 bus_space_write_1(chp->cmd_iot, chp->cmd_ioh, wdr_seccnt, 0x03u); 6927 6928 /* Now we can write the required register */ 6929 bus_space_write_1(chp->cmd_iot, chp->cmd_ioh, reg, val); 6930 6931 /* Restore the real registers */ 6932 bus_space_write_1(chp->cmd_iot, chp->cmd_ioh, wdr_seccnt, 0x83u); 6933 6934 splx(s); 6935 } 6936 6937 void 6938 opti_chip_map(struct pciide_softc *sc, struct pci_attach_args *pa) 6939 { 6940 struct pciide_channel *cp; 6941 bus_size_t cmdsize, ctlsize; 6942 pcireg_t interface; 6943 u_int8_t init_ctrl; 6944 int channel; 6945 6946 printf(": DMA"); 6947 /* 6948 * XXXSCW: 6949 * There seem to be a couple of buggy revisions/implementations 6950 * of the OPTi pciide chipset. This kludge seems to fix one of 6951 * the reported problems (NetBSD PR/11644) but still fails for the 6952 * other (NetBSD PR/13151), although the latter may be due to other 6953 * issues too... 6954 */ 6955 if (sc->sc_rev <= 0x12) { 6956 printf(" (disabled)"); 6957 sc->sc_dma_ok = 0; 6958 sc->sc_wdcdev.cap = 0; 6959 } else { 6960 sc->sc_wdcdev.cap = WDC_CAPABILITY_DATA32; 6961 pciide_mapreg_dma(sc, pa); 6962 } 6963 6964 sc->sc_wdcdev.cap = WDC_CAPABILITY_DATA16 | WDC_CAPABILITY_MODE; 6965 sc->sc_wdcdev.PIO_cap = 4; 6966 if (sc->sc_dma_ok) { 6967 sc->sc_wdcdev.cap |= WDC_CAPABILITY_DMA | WDC_CAPABILITY_IRQACK; 6968 sc->sc_wdcdev.irqack = pciide_irqack; 6969 sc->sc_wdcdev.DMA_cap = 2; 6970 } 6971 sc->sc_wdcdev.set_modes = opti_setup_channel; 6972 6973 sc->sc_wdcdev.channels = sc->wdc_chanarray; 6974 sc->sc_wdcdev.nchannels = PCIIDE_NUM_CHANNELS; 6975 6976 init_ctrl = pciide_pci_read(sc->sc_pc, sc->sc_tag, 6977 OPTI_REG_INIT_CONTROL); 6978 6979 interface = PCI_INTERFACE(pa->pa_class); 6980 6981 pciide_print_channels(sc->sc_wdcdev.nchannels, interface); 6982 6983 for (channel = 0; channel < sc->sc_wdcdev.nchannels; channel++) { 6984 cp = &sc->pciide_channels[channel]; 6985 if (pciide_chansetup(sc, channel, interface) == 0) 6986 continue; 6987 if (channel == 1 && 6988 (init_ctrl & OPTI_INIT_CONTROL_CH2_DISABLE) != 0) { 6989 printf("%s: %s ignored (disabled)\n", 6990 sc->sc_wdcdev.sc_dev.dv_xname, cp->name); 6991 continue; 6992 } 6993 pciide_map_compat_intr(pa, cp, channel, interface); 6994 if (cp->hw_ok == 0) 6995 continue; 6996 pciide_mapchan(pa, cp, interface, &cmdsize, &ctlsize, 6997 pciide_pci_intr); 6998 if (cp->hw_ok == 0) { 6999 pciide_unmap_compat_intr(pa, cp, channel, interface); 7000 continue; 7001 } 7002 opti_setup_channel(&cp->wdc_channel); 7003 } 7004 } 7005 7006 void 7007 opti_setup_channel(struct channel_softc *chp) 7008 { 7009 struct ata_drive_datas *drvp; 7010 struct pciide_channel *cp = (struct pciide_channel *)chp; 7011 struct pciide_softc *sc = (struct pciide_softc *)cp->wdc_channel.wdc; 7012 int drive, spd; 7013 int mode[2]; 7014 u_int8_t rv, mr; 7015 7016 /* 7017 * The `Delay' and `Address Setup Time' fields of the 7018 * Miscellaneous Register are always zero initially. 7019 */ 7020 mr = opti_read_config(chp, OPTI_REG_MISC) & ~OPTI_MISC_INDEX_MASK; 7021 mr &= ~(OPTI_MISC_DELAY_MASK | 7022 OPTI_MISC_ADDR_SETUP_MASK | 7023 OPTI_MISC_INDEX_MASK); 7024 7025 /* Prime the control register before setting timing values */ 7026 opti_write_config(chp, OPTI_REG_CONTROL, OPTI_CONTROL_DISABLE); 7027 7028 /* Determine the clockrate of the PCIbus the chip is attached to */ 7029 spd = (int) opti_read_config(chp, OPTI_REG_STRAP); 7030 spd &= OPTI_STRAP_PCI_SPEED_MASK; 7031 7032 /* setup DMA if needed */ 7033 pciide_channel_dma_setup(cp); 7034 7035 for (drive = 0; drive < 2; drive++) { 7036 drvp = &chp->ch_drive[drive]; 7037 /* If no drive, skip */ 7038 if ((drvp->drive_flags & DRIVE) == 0) { 7039 mode[drive] = -1; 7040 continue; 7041 } 7042 7043 if ((drvp->drive_flags & DRIVE_DMA)) { 7044 /* 7045 * Timings will be used for both PIO and DMA, 7046 * so adjust DMA mode if needed 7047 */ 7048 if (drvp->PIO_mode > (drvp->DMA_mode + 2)) 7049 drvp->PIO_mode = drvp->DMA_mode + 2; 7050 if (drvp->DMA_mode + 2 > (drvp->PIO_mode)) 7051 drvp->DMA_mode = (drvp->PIO_mode > 2) ? 7052 drvp->PIO_mode - 2 : 0; 7053 if (drvp->DMA_mode == 0) 7054 drvp->PIO_mode = 0; 7055 7056 mode[drive] = drvp->DMA_mode + 5; 7057 } else 7058 mode[drive] = drvp->PIO_mode; 7059 7060 if (drive && mode[0] >= 0 && 7061 (opti_tim_as[spd][mode[0]] != opti_tim_as[spd][mode[1]])) { 7062 /* 7063 * Can't have two drives using different values 7064 * for `Address Setup Time'. 7065 * Slow down the faster drive to compensate. 7066 */ 7067 int d = (opti_tim_as[spd][mode[0]] > 7068 opti_tim_as[spd][mode[1]]) ? 0 : 1; 7069 7070 mode[d] = mode[1-d]; 7071 chp->ch_drive[d].PIO_mode = chp->ch_drive[1-d].PIO_mode; 7072 chp->ch_drive[d].DMA_mode = 0; 7073 chp->ch_drive[d].drive_flags &= DRIVE_DMA; 7074 } 7075 } 7076 7077 for (drive = 0; drive < 2; drive++) { 7078 int m; 7079 if ((m = mode[drive]) < 0) 7080 continue; 7081 7082 /* Set the Address Setup Time and select appropriate index */ 7083 rv = opti_tim_as[spd][m] << OPTI_MISC_ADDR_SETUP_SHIFT; 7084 rv |= OPTI_MISC_INDEX(drive); 7085 opti_write_config(chp, OPTI_REG_MISC, mr | rv); 7086 7087 /* Set the pulse width and recovery timing parameters */ 7088 rv = opti_tim_cp[spd][m] << OPTI_PULSE_WIDTH_SHIFT; 7089 rv |= opti_tim_rt[spd][m] << OPTI_RECOVERY_TIME_SHIFT; 7090 opti_write_config(chp, OPTI_REG_READ_CYCLE_TIMING, rv); 7091 opti_write_config(chp, OPTI_REG_WRITE_CYCLE_TIMING, rv); 7092 7093 /* Set the Enhanced Mode register appropriately */ 7094 rv = pciide_pci_read(sc->sc_pc, sc->sc_tag, OPTI_REG_ENH_MODE); 7095 rv &= ~OPTI_ENH_MODE_MASK(chp->channel, drive); 7096 rv |= OPTI_ENH_MODE(chp->channel, drive, opti_tim_em[m]); 7097 pciide_pci_write(sc->sc_pc, sc->sc_tag, OPTI_REG_ENH_MODE, rv); 7098 } 7099 7100 /* Finally, enable the timings */ 7101 opti_write_config(chp, OPTI_REG_CONTROL, OPTI_CONTROL_ENABLE); 7102 7103 pciide_print_modes(cp); 7104 } 7105 #endif 7106 7107 void 7108 serverworks_chip_map(struct pciide_softc *sc, struct pci_attach_args *pa) 7109 { 7110 struct pciide_channel *cp; 7111 pcireg_t interface = PCI_INTERFACE(pa->pa_class); 7112 pcitag_t pcib_tag; 7113 int channel; 7114 bus_size_t cmdsize, ctlsize; 7115 7116 printf(": DMA"); 7117 pciide_mapreg_dma(sc, pa); 7118 printf("\n"); 7119 sc->sc_wdcdev.cap = WDC_CAPABILITY_DATA16 | WDC_CAPABILITY_DATA32 | 7120 WDC_CAPABILITY_MODE; 7121 7122 if (sc->sc_dma_ok) { 7123 sc->sc_wdcdev.cap |= WDC_CAPABILITY_DMA | WDC_CAPABILITY_UDMA; 7124 sc->sc_wdcdev.cap |= WDC_CAPABILITY_IRQACK; 7125 sc->sc_wdcdev.irqack = pciide_irqack; 7126 } 7127 sc->sc_wdcdev.PIO_cap = 4; 7128 sc->sc_wdcdev.DMA_cap = 2; 7129 switch (sc->sc_pp->ide_product) { 7130 case PCI_PRODUCT_RCC_OSB4_IDE: 7131 sc->sc_wdcdev.UDMA_cap = 2; 7132 break; 7133 case PCI_PRODUCT_RCC_CSB5_IDE: 7134 if (sc->sc_rev < 0x92) 7135 sc->sc_wdcdev.UDMA_cap = 4; 7136 else 7137 sc->sc_wdcdev.UDMA_cap = 5; 7138 break; 7139 case PCI_PRODUCT_RCC_CSB6_IDE: 7140 sc->sc_wdcdev.UDMA_cap = 4; 7141 break; 7142 case PCI_PRODUCT_RCC_CSB6_RAID_IDE: 7143 sc->sc_wdcdev.UDMA_cap = 5; 7144 break; 7145 } 7146 7147 sc->sc_wdcdev.set_modes = serverworks_setup_channel; 7148 sc->sc_wdcdev.channels = sc->wdc_chanarray; 7149 sc->sc_wdcdev.nchannels = 7150 (sc->sc_pp->ide_product == PCI_PRODUCT_RCC_CSB6_IDE ? 1 : 2); 7151 7152 for (channel = 0; channel < sc->sc_wdcdev.nchannels; channel++) { 7153 cp = &sc->pciide_channels[channel]; 7154 if (pciide_chansetup(sc, channel, interface) == 0) 7155 continue; 7156 pciide_mapchan(pa, cp, interface, &cmdsize, &ctlsize, 7157 serverworks_pci_intr); 7158 if (cp->hw_ok == 0) 7159 return; 7160 pciide_map_compat_intr(pa, cp, channel, interface); 7161 if (cp->hw_ok == 0) 7162 return; 7163 serverworks_setup_channel(&cp->wdc_channel); 7164 } 7165 7166 pcib_tag = pci_make_tag(pa->pa_pc, pa->pa_bus, pa->pa_device, 0); 7167 pci_conf_write(pa->pa_pc, pcib_tag, 0x64, 7168 (pci_conf_read(pa->pa_pc, pcib_tag, 0x64) & ~0x2000) | 0x4000); 7169 } 7170 7171 void 7172 serverworks_setup_channel(struct channel_softc *chp) 7173 { 7174 struct ata_drive_datas *drvp; 7175 struct pciide_channel *cp = (struct pciide_channel *)chp; 7176 struct pciide_softc *sc = (struct pciide_softc *)cp->wdc_channel.wdc; 7177 int channel = chp->channel; 7178 int drive, unit; 7179 u_int32_t pio_time, dma_time, pio_mode, udma_mode; 7180 u_int32_t idedma_ctl; 7181 static const u_int8_t pio_modes[5] = {0x5d, 0x47, 0x34, 0x22, 0x20}; 7182 static const u_int8_t dma_modes[3] = {0x77, 0x21, 0x20}; 7183 7184 /* setup DMA if needed */ 7185 pciide_channel_dma_setup(cp); 7186 7187 pio_time = pci_conf_read(sc->sc_pc, sc->sc_tag, 0x40); 7188 dma_time = pci_conf_read(sc->sc_pc, sc->sc_tag, 0x44); 7189 pio_mode = pci_conf_read(sc->sc_pc, sc->sc_tag, 0x48); 7190 udma_mode = pci_conf_read(sc->sc_pc, sc->sc_tag, 0x54); 7191 7192 pio_time &= ~(0xffff << (16 * channel)); 7193 dma_time &= ~(0xffff << (16 * channel)); 7194 pio_mode &= ~(0xff << (8 * channel + 16)); 7195 udma_mode &= ~(0xff << (8 * channel + 16)); 7196 udma_mode &= ~(3 << (2 * channel)); 7197 7198 idedma_ctl = 0; 7199 7200 /* Per drive settings */ 7201 for (drive = 0; drive < 2; drive++) { 7202 drvp = &chp->ch_drive[drive]; 7203 /* If no drive, skip */ 7204 if ((drvp->drive_flags & DRIVE) == 0) 7205 continue; 7206 unit = drive + 2 * channel; 7207 /* add timing values, setup DMA if needed */ 7208 pio_time |= pio_modes[drvp->PIO_mode] << (8 * (unit^1)); 7209 pio_mode |= drvp->PIO_mode << (4 * unit + 16); 7210 if ((chp->wdc->cap & WDC_CAPABILITY_UDMA) && 7211 (drvp->drive_flags & DRIVE_UDMA)) { 7212 /* use Ultra/DMA, check for 80-pin cable */ 7213 if (sc->sc_rev <= 0x92 && drvp->UDMA_mode > 2 && 7214 (PCI_PRODUCT(pci_conf_read(sc->sc_pc, sc->sc_tag, 7215 PCI_SUBSYS_ID_REG)) & 7216 (1 << (14 + channel))) == 0) { 7217 WDCDEBUG_PRINT(("%s(%s:%d:%d): 80-wire " 7218 "cable not detected\n", drvp->drive_name, 7219 sc->sc_wdcdev.sc_dev.dv_xname, 7220 channel, drive), DEBUG_PROBE); 7221 drvp->UDMA_mode = 2; 7222 } 7223 dma_time |= dma_modes[drvp->DMA_mode] << (8 * (unit^1)); 7224 udma_mode |= drvp->UDMA_mode << (4 * unit + 16); 7225 udma_mode |= 1 << unit; 7226 idedma_ctl |= IDEDMA_CTL_DRV_DMA(drive); 7227 } else if ((chp->wdc->cap & WDC_CAPABILITY_DMA) && 7228 (drvp->drive_flags & DRIVE_DMA)) { 7229 /* use Multiword DMA */ 7230 drvp->drive_flags &= ~DRIVE_UDMA; 7231 dma_time |= dma_modes[drvp->DMA_mode] << (8 * (unit^1)); 7232 idedma_ctl |= IDEDMA_CTL_DRV_DMA(drive); 7233 } else { 7234 /* PIO only */ 7235 drvp->drive_flags &= ~(DRIVE_UDMA | DRIVE_DMA); 7236 } 7237 } 7238 7239 pci_conf_write(sc->sc_pc, sc->sc_tag, 0x40, pio_time); 7240 pci_conf_write(sc->sc_pc, sc->sc_tag, 0x44, dma_time); 7241 if (sc->sc_pp->ide_product != PCI_PRODUCT_RCC_OSB4_IDE) 7242 pci_conf_write(sc->sc_pc, sc->sc_tag, 0x48, pio_mode); 7243 pci_conf_write(sc->sc_pc, sc->sc_tag, 0x54, udma_mode); 7244 7245 if (idedma_ctl != 0) { 7246 /* Add software bits in status register */ 7247 bus_space_write_1(sc->sc_dma_iot, sc->sc_dma_ioh, 7248 IDEDMA_CTL(channel), idedma_ctl); 7249 } 7250 pciide_print_modes(cp); 7251 } 7252 7253 int 7254 serverworks_pci_intr(void *arg) 7255 { 7256 struct pciide_softc *sc = arg; 7257 struct pciide_channel *cp; 7258 struct channel_softc *wdc_cp; 7259 int rv = 0; 7260 int dmastat, i, crv; 7261 7262 for (i = 0; i < sc->sc_wdcdev.nchannels; i++) { 7263 dmastat = bus_space_read_1(sc->sc_dma_iot, sc->sc_dma_ioh, 7264 IDEDMA_CTL(i)); 7265 if ((dmastat & (IDEDMA_CTL_ACT | IDEDMA_CTL_INTR)) != 7266 IDEDMA_CTL_INTR) 7267 continue; 7268 cp = &sc->pciide_channels[i]; 7269 wdc_cp = &cp->wdc_channel; 7270 crv = wdcintr(wdc_cp); 7271 if (crv == 0) { 7272 printf("%s:%d: bogus intr\n", 7273 sc->sc_wdcdev.sc_dev.dv_xname, i); 7274 bus_space_write_1(sc->sc_dma_iot, sc->sc_dma_ioh, 7275 IDEDMA_CTL(i), dmastat); 7276 } else 7277 rv = 1; 7278 } 7279 return (rv); 7280 } 7281 7282 void 7283 svwsata_chip_map(struct pciide_softc *sc, struct pci_attach_args *pa) 7284 { 7285 struct pciide_channel *cp; 7286 pci_intr_handle_t intrhandle; 7287 const char *intrstr; 7288 int channel; 7289 struct pciide_svwsata *ss; 7290 7291 /* Allocate memory for private data */ 7292 sc->sc_cookie = malloc(sizeof(*ss), M_DEVBUF, M_NOWAIT | M_ZERO); 7293 ss = sc->sc_cookie; 7294 7295 /* The 4-port version has a dummy second function. */ 7296 if (pci_conf_read(sc->sc_pc, sc->sc_tag, 7297 PCI_MAPREG_START + 0x14) == 0) { 7298 printf("\n"); 7299 return; 7300 } 7301 7302 if (pci_mapreg_map(pa, PCI_MAPREG_START + 0x14, 7303 PCI_MAPREG_TYPE_MEM | PCI_MAPREG_MEM_TYPE_32BIT, 0, 7304 &ss->ba5_st, &ss->ba5_sh, NULL, NULL, 0) != 0) { 7305 printf(": unable to map BA5 register space\n"); 7306 return; 7307 } 7308 7309 printf(": DMA"); 7310 svwsata_mapreg_dma(sc, pa); 7311 printf("\n"); 7312 7313 if (sc->sc_dma_ok) { 7314 sc->sc_wdcdev.cap |= WDC_CAPABILITY_UDMA | 7315 WDC_CAPABILITY_DMA | WDC_CAPABILITY_IRQACK; 7316 sc->sc_wdcdev.irqack = pciide_irqack; 7317 } 7318 sc->sc_wdcdev.PIO_cap = 4; 7319 sc->sc_wdcdev.DMA_cap = 2; 7320 sc->sc_wdcdev.UDMA_cap = 6; 7321 7322 sc->sc_wdcdev.channels = sc->wdc_chanarray; 7323 sc->sc_wdcdev.nchannels = 4; 7324 sc->sc_wdcdev.cap |= WDC_CAPABILITY_DATA16 | WDC_CAPABILITY_DATA32 | 7325 WDC_CAPABILITY_MODE | WDC_CAPABILITY_SATA; 7326 sc->sc_wdcdev.set_modes = sata_setup_channel; 7327 7328 /* We can use SControl and SStatus to probe for drives. */ 7329 sc->sc_wdcdev.drv_probe = svwsata_drv_probe; 7330 7331 /* Map and establish the interrupt handler. */ 7332 if(pci_intr_map(pa, &intrhandle) != 0) { 7333 printf("%s: couldn't map native-PCI interrupt\n", 7334 sc->sc_wdcdev.sc_dev.dv_xname); 7335 return; 7336 } 7337 intrstr = pci_intr_string(pa->pa_pc, intrhandle); 7338 sc->sc_pci_ih = pci_intr_establish(pa->pa_pc, intrhandle, IPL_BIO, 7339 pciide_pci_intr, sc, sc->sc_wdcdev.sc_dev.dv_xname); 7340 if (sc->sc_pci_ih != NULL) { 7341 printf("%s: using %s for native-PCI interrupt\n", 7342 sc->sc_wdcdev.sc_dev.dv_xname, 7343 intrstr ? intrstr : "unknown interrupt"); 7344 } else { 7345 printf("%s: couldn't establish native-PCI interrupt", 7346 sc->sc_wdcdev.sc_dev.dv_xname); 7347 if (intrstr != NULL) 7348 printf(" at %s", intrstr); 7349 printf("\n"); 7350 return; 7351 } 7352 7353 for (channel = 0; channel < sc->sc_wdcdev.nchannels; channel++) { 7354 cp = &sc->pciide_channels[channel]; 7355 if (pciide_chansetup(sc, channel, 0) == 0) 7356 continue; 7357 svwsata_mapchan(cp); 7358 sata_setup_channel(&cp->wdc_channel); 7359 } 7360 } 7361 7362 void 7363 svwsata_mapreg_dma(struct pciide_softc *sc, struct pci_attach_args *pa) 7364 { 7365 struct pciide_svwsata *ss = sc->sc_cookie; 7366 7367 sc->sc_wdcdev.dma_arg = sc; 7368 sc->sc_wdcdev.dma_init = pciide_dma_init; 7369 sc->sc_wdcdev.dma_start = pciide_dma_start; 7370 sc->sc_wdcdev.dma_finish = pciide_dma_finish; 7371 7372 /* XXX */ 7373 sc->sc_dma_iot = ss->ba5_st; 7374 sc->sc_dma_ioh = ss->ba5_sh; 7375 7376 sc->sc_dmacmd_read = svwsata_dmacmd_read; 7377 sc->sc_dmacmd_write = svwsata_dmacmd_write; 7378 sc->sc_dmactl_read = svwsata_dmactl_read; 7379 sc->sc_dmactl_write = svwsata_dmactl_write; 7380 sc->sc_dmatbl_write = svwsata_dmatbl_write; 7381 7382 /* DMA registers all set up! */ 7383 sc->sc_dmat = pa->pa_dmat; 7384 sc->sc_dma_ok = 1; 7385 } 7386 7387 u_int8_t 7388 svwsata_dmacmd_read(struct pciide_softc *sc, int chan) 7389 { 7390 return (bus_space_read_1(sc->sc_dma_iot, sc->sc_dma_ioh, 7391 (chan << 8) + SVWSATA_DMA + IDEDMA_CMD(0))); 7392 } 7393 7394 void 7395 svwsata_dmacmd_write(struct pciide_softc *sc, int chan, u_int8_t val) 7396 { 7397 bus_space_write_1(sc->sc_dma_iot, sc->sc_dma_ioh, 7398 (chan << 8) + SVWSATA_DMA + IDEDMA_CMD(0), val); 7399 } 7400 7401 u_int8_t 7402 svwsata_dmactl_read(struct pciide_softc *sc, int chan) 7403 { 7404 return (bus_space_read_1(sc->sc_dma_iot, sc->sc_dma_ioh, 7405 (chan << 8) + SVWSATA_DMA + IDEDMA_CTL(0))); 7406 } 7407 7408 void 7409 svwsata_dmactl_write(struct pciide_softc *sc, int chan, u_int8_t val) 7410 { 7411 bus_space_write_1(sc->sc_dma_iot, sc->sc_dma_ioh, 7412 (chan << 8) + SVWSATA_DMA + IDEDMA_CTL(0), val); 7413 } 7414 7415 void 7416 svwsata_dmatbl_write(struct pciide_softc *sc, int chan, u_int32_t val) 7417 { 7418 bus_space_write_4(sc->sc_dma_iot, sc->sc_dma_ioh, 7419 (chan << 8) + SVWSATA_DMA + IDEDMA_TBL(0), val); 7420 } 7421 7422 void 7423 svwsata_mapchan(struct pciide_channel *cp) 7424 { 7425 struct pciide_softc *sc = (struct pciide_softc *)cp->wdc_channel.wdc; 7426 struct channel_softc *wdc_cp = &cp->wdc_channel; 7427 struct pciide_svwsata *ss = sc->sc_cookie; 7428 7429 cp->compat = 0; 7430 cp->ih = sc->sc_pci_ih; 7431 7432 if (bus_space_subregion(ss->ba5_st, ss->ba5_sh, 7433 (wdc_cp->channel << 8) + SVWSATA_TF0, 7434 SVWSATA_TF8 - SVWSATA_TF0, &wdc_cp->cmd_ioh) != 0) { 7435 printf("%s: couldn't map %s cmd regs\n", 7436 sc->sc_wdcdev.sc_dev.dv_xname, cp->name); 7437 return; 7438 } 7439 if (bus_space_subregion(ss->ba5_st, ss->ba5_sh, 7440 (wdc_cp->channel << 8) + SVWSATA_TF8, 4, 7441 &wdc_cp->ctl_ioh) != 0) { 7442 printf("%s: couldn't map %s ctl regs\n", 7443 sc->sc_wdcdev.sc_dev.dv_xname, cp->name); 7444 return; 7445 } 7446 wdc_cp->cmd_iot = wdc_cp->ctl_iot = ss->ba5_st; 7447 wdc_cp->_vtbl = &wdc_svwsata_vtbl; 7448 wdcattach(wdc_cp); 7449 } 7450 7451 void 7452 svwsata_drv_probe(struct channel_softc *chp) 7453 { 7454 struct pciide_channel *cp = (struct pciide_channel *)chp; 7455 struct pciide_softc *sc = (struct pciide_softc *)cp->wdc_channel.wdc; 7456 struct pciide_svwsata *ss = sc->sc_cookie; 7457 int channel = chp->channel; 7458 uint32_t scontrol, sstatus; 7459 uint8_t scnt, sn, cl, ch; 7460 int i, s; 7461 7462 /* XXX This should be done by other code. */ 7463 for (i = 0; i < 2; i++) { 7464 chp->ch_drive[i].chnl_softc = chp; 7465 chp->ch_drive[i].drive = i; 7466 } 7467 7468 /* 7469 * Request communication initialization sequence, any speed. 7470 * Performing this is the equivalent of an ATA Reset. 7471 */ 7472 scontrol = SControl_DET_INIT | SControl_SPD_ANY; 7473 7474 /* 7475 * XXX We don't yet support SATA power management; disable all 7476 * power management state transitions. 7477 */ 7478 scontrol |= SControl_IPM_NONE; 7479 7480 bus_space_write_4(ss->ba5_st, ss->ba5_sh, 7481 (channel << 8) + SVWSATA_SCONTROL, scontrol); 7482 delay(50 * 1000); 7483 scontrol &= ~SControl_DET_INIT; 7484 bus_space_write_4(ss->ba5_st, ss->ba5_sh, 7485 (channel << 8) + SVWSATA_SCONTROL, scontrol); 7486 delay(50 * 1000); 7487 7488 sstatus = bus_space_read_4(ss->ba5_st, ss->ba5_sh, 7489 (channel << 8) + SVWSATA_SSTATUS); 7490 #if 0 7491 printf("%s: port %d: SStatus=0x%08x, SControl=0x%08x\n", 7492 sc->sc_wdcdev.sc_dev.dv_xname, chp->channel, sstatus, 7493 bus_space_read_4(ss->ba5_st, ss->ba5_sh, 7494 (channel << 8) + SVWSATA_SSTATUS)); 7495 #endif 7496 switch (sstatus & SStatus_DET_mask) { 7497 case SStatus_DET_NODEV: 7498 /* No device; be silent. */ 7499 break; 7500 7501 case SStatus_DET_DEV_NE: 7502 printf("%s: port %d: device connected, but " 7503 "communication not established\n", 7504 sc->sc_wdcdev.sc_dev.dv_xname, chp->channel); 7505 break; 7506 7507 case SStatus_DET_OFFLINE: 7508 printf("%s: port %d: PHY offline\n", 7509 sc->sc_wdcdev.sc_dev.dv_xname, chp->channel); 7510 break; 7511 7512 case SStatus_DET_DEV: 7513 /* 7514 * XXX ATAPI detection doesn't currently work. Don't 7515 * XXX know why. But, it's not like the standard method 7516 * XXX can detect an ATAPI device connected via a SATA/PATA 7517 * XXX bridge, so at least this is no worse. --thorpej 7518 */ 7519 if (chp->_vtbl != NULL) 7520 CHP_WRITE_REG(chp, wdr_sdh, WDSD_IBM | (0 << 4)); 7521 else 7522 bus_space_write_1(chp->cmd_iot, chp->cmd_ioh, 7523 wdr_sdh & _WDC_REGMASK, WDSD_IBM | (0 << 4)); 7524 delay(10); /* 400ns delay */ 7525 /* Save register contents. */ 7526 if (chp->_vtbl != NULL) { 7527 scnt = CHP_READ_REG(chp, wdr_seccnt); 7528 sn = CHP_READ_REG(chp, wdr_sector); 7529 cl = CHP_READ_REG(chp, wdr_cyl_lo); 7530 ch = CHP_READ_REG(chp, wdr_cyl_hi); 7531 } else { 7532 scnt = bus_space_read_1(chp->cmd_iot, 7533 chp->cmd_ioh, wdr_seccnt & _WDC_REGMASK); 7534 sn = bus_space_read_1(chp->cmd_iot, 7535 chp->cmd_ioh, wdr_sector & _WDC_REGMASK); 7536 cl = bus_space_read_1(chp->cmd_iot, 7537 chp->cmd_ioh, wdr_cyl_lo & _WDC_REGMASK); 7538 ch = bus_space_read_1(chp->cmd_iot, 7539 chp->cmd_ioh, wdr_cyl_hi & _WDC_REGMASK); 7540 } 7541 #if 0 7542 printf("%s: port %d: scnt=0x%x sn=0x%x cl=0x%x ch=0x%x\n", 7543 sc->sc_wdcdev.sc_dev.dv_xname, chp->channel, 7544 scnt, sn, cl, ch); 7545 #endif 7546 /* 7547 * scnt and sn are supposed to be 0x1 for ATAPI, but in some 7548 * cases we get wrong values here, so ignore it. 7549 */ 7550 s = splbio(); 7551 if (cl == 0x14 && ch == 0xeb) 7552 chp->ch_drive[0].drive_flags |= DRIVE_ATAPI; 7553 else 7554 chp->ch_drive[0].drive_flags |= DRIVE_ATA; 7555 splx(s); 7556 7557 printf("%s: port %d: device present", 7558 sc->sc_wdcdev.sc_dev.dv_xname, chp->channel); 7559 switch ((sstatus & SStatus_SPD_mask) >> SStatus_SPD_shift) { 7560 case 1: 7561 printf(", speed: 1.5Gb/s"); 7562 break; 7563 case 2: 7564 printf(", speed: 3.0Gb/s"); 7565 break; 7566 } 7567 printf("\n"); 7568 break; 7569 7570 default: 7571 printf("%s: port %d: unknown SStatus: 0x%08x\n", 7572 sc->sc_wdcdev.sc_dev.dv_xname, chp->channel, sstatus); 7573 } 7574 } 7575 7576 u_int8_t 7577 svwsata_read_reg(struct channel_softc *chp, enum wdc_regs reg) 7578 { 7579 if (reg & _WDC_AUX) { 7580 return (bus_space_read_4(chp->ctl_iot, chp->ctl_ioh, 7581 (reg & _WDC_REGMASK) << 2)); 7582 } else { 7583 return (bus_space_read_4(chp->cmd_iot, chp->cmd_ioh, 7584 (reg & _WDC_REGMASK) << 2)); 7585 } 7586 } 7587 7588 void 7589 svwsata_write_reg(struct channel_softc *chp, enum wdc_regs reg, u_int8_t val) 7590 { 7591 if (reg & _WDC_AUX) { 7592 bus_space_write_4(chp->ctl_iot, chp->ctl_ioh, 7593 (reg & _WDC_REGMASK) << 2, val); 7594 } else { 7595 bus_space_write_4(chp->cmd_iot, chp->cmd_ioh, 7596 (reg & _WDC_REGMASK) << 2, val); 7597 } 7598 } 7599 7600 void 7601 svwsata_lba48_write_reg(struct channel_softc *chp, enum wdc_regs reg, u_int16_t val) 7602 { 7603 if (reg & _WDC_AUX) { 7604 bus_space_write_4(chp->ctl_iot, chp->ctl_ioh, 7605 (reg & _WDC_REGMASK) << 2, val); 7606 } else { 7607 bus_space_write_4(chp->cmd_iot, chp->cmd_ioh, 7608 (reg & _WDC_REGMASK) << 2, val); 7609 } 7610 } 7611 7612 #define ACARD_IS_850(sc) \ 7613 ((sc)->sc_pp->ide_product == PCI_PRODUCT_ACARD_ATP850U) 7614 7615 void 7616 acard_chip_map(struct pciide_softc *sc, struct pci_attach_args *pa) 7617 { 7618 struct pciide_channel *cp; 7619 int i; 7620 pcireg_t interface; 7621 bus_size_t cmdsize, ctlsize; 7622 7623 /* 7624 * when the chip is in native mode it identifies itself as a 7625 * 'misc mass storage'. Fake interface in this case. 7626 */ 7627 if (PCI_SUBCLASS(pa->pa_class) == PCI_SUBCLASS_MASS_STORAGE_IDE) { 7628 interface = PCI_INTERFACE(pa->pa_class); 7629 } else { 7630 interface = PCIIDE_INTERFACE_BUS_MASTER_DMA | 7631 PCIIDE_INTERFACE_PCI(0) | PCIIDE_INTERFACE_PCI(1); 7632 } 7633 7634 printf(": DMA"); 7635 pciide_mapreg_dma(sc, pa); 7636 printf("\n"); 7637 sc->sc_wdcdev.cap = WDC_CAPABILITY_DATA16 | WDC_CAPABILITY_DATA32 | 7638 WDC_CAPABILITY_MODE; 7639 7640 if (sc->sc_dma_ok) { 7641 sc->sc_wdcdev.cap |= WDC_CAPABILITY_DMA | WDC_CAPABILITY_UDMA; 7642 sc->sc_wdcdev.cap |= WDC_CAPABILITY_IRQACK; 7643 sc->sc_wdcdev.irqack = pciide_irqack; 7644 } 7645 sc->sc_wdcdev.PIO_cap = 4; 7646 sc->sc_wdcdev.DMA_cap = 2; 7647 switch (sc->sc_pp->ide_product) { 7648 case PCI_PRODUCT_ACARD_ATP850U: 7649 sc->sc_wdcdev.UDMA_cap = 2; 7650 break; 7651 case PCI_PRODUCT_ACARD_ATP860: 7652 case PCI_PRODUCT_ACARD_ATP860A: 7653 sc->sc_wdcdev.UDMA_cap = 4; 7654 break; 7655 case PCI_PRODUCT_ACARD_ATP865A: 7656 case PCI_PRODUCT_ACARD_ATP865R: 7657 sc->sc_wdcdev.UDMA_cap = 6; 7658 break; 7659 } 7660 7661 sc->sc_wdcdev.set_modes = acard_setup_channel; 7662 sc->sc_wdcdev.channels = sc->wdc_chanarray; 7663 sc->sc_wdcdev.nchannels = 2; 7664 7665 for (i = 0; i < sc->sc_wdcdev.nchannels; i++) { 7666 cp = &sc->pciide_channels[i]; 7667 if (pciide_chansetup(sc, i, interface) == 0) 7668 continue; 7669 if (interface & PCIIDE_INTERFACE_PCI(i)) { 7670 cp->hw_ok = pciide_mapregs_native(pa, cp, &cmdsize, 7671 &ctlsize, pciide_pci_intr); 7672 } else { 7673 cp->hw_ok = pciide_mapregs_compat(pa, cp, i, 7674 &cmdsize, &ctlsize); 7675 } 7676 if (cp->hw_ok == 0) 7677 return; 7678 cp->wdc_channel.data32iot = cp->wdc_channel.cmd_iot; 7679 cp->wdc_channel.data32ioh = cp->wdc_channel.cmd_ioh; 7680 wdcattach(&cp->wdc_channel); 7681 acard_setup_channel(&cp->wdc_channel); 7682 } 7683 if (!ACARD_IS_850(sc)) { 7684 u_int32_t reg; 7685 reg = pci_conf_read(sc->sc_pc, sc->sc_tag, ATP8x0_CTRL); 7686 reg &= ~ATP860_CTRL_INT; 7687 pci_conf_write(sc->sc_pc, sc->sc_tag, ATP8x0_CTRL, reg); 7688 } 7689 } 7690 7691 void 7692 acard_setup_channel(struct channel_softc *chp) 7693 { 7694 struct ata_drive_datas *drvp; 7695 struct pciide_channel *cp = (struct pciide_channel *)chp; 7696 struct pciide_softc *sc = (struct pciide_softc *)cp->wdc_channel.wdc; 7697 int channel = chp->channel; 7698 int drive; 7699 u_int32_t idetime, udma_mode; 7700 u_int32_t idedma_ctl; 7701 7702 /* setup DMA if needed */ 7703 pciide_channel_dma_setup(cp); 7704 7705 if (ACARD_IS_850(sc)) { 7706 idetime = 0; 7707 udma_mode = pci_conf_read(sc->sc_pc, sc->sc_tag, ATP850_UDMA); 7708 udma_mode &= ~ATP850_UDMA_MASK(channel); 7709 } else { 7710 idetime = pci_conf_read(sc->sc_pc, sc->sc_tag, ATP860_IDETIME); 7711 idetime &= ~ATP860_SETTIME_MASK(channel); 7712 udma_mode = pci_conf_read(sc->sc_pc, sc->sc_tag, ATP860_UDMA); 7713 udma_mode &= ~ATP860_UDMA_MASK(channel); 7714 } 7715 7716 idedma_ctl = 0; 7717 7718 /* Per drive settings */ 7719 for (drive = 0; drive < 2; drive++) { 7720 drvp = &chp->ch_drive[drive]; 7721 /* If no drive, skip */ 7722 if ((drvp->drive_flags & DRIVE) == 0) 7723 continue; 7724 /* add timing values, setup DMA if needed */ 7725 if ((chp->wdc->cap & WDC_CAPABILITY_UDMA) && 7726 (drvp->drive_flags & DRIVE_UDMA)) { 7727 /* use Ultra/DMA */ 7728 if (ACARD_IS_850(sc)) { 7729 idetime |= ATP850_SETTIME(drive, 7730 acard_act_udma[drvp->UDMA_mode], 7731 acard_rec_udma[drvp->UDMA_mode]); 7732 udma_mode |= ATP850_UDMA_MODE(channel, drive, 7733 acard_udma_conf[drvp->UDMA_mode]); 7734 } else { 7735 idetime |= ATP860_SETTIME(channel, drive, 7736 acard_act_udma[drvp->UDMA_mode], 7737 acard_rec_udma[drvp->UDMA_mode]); 7738 udma_mode |= ATP860_UDMA_MODE(channel, drive, 7739 acard_udma_conf[drvp->UDMA_mode]); 7740 } 7741 idedma_ctl |= IDEDMA_CTL_DRV_DMA(drive); 7742 } else if ((chp->wdc->cap & WDC_CAPABILITY_DMA) && 7743 (drvp->drive_flags & DRIVE_DMA)) { 7744 /* use Multiword DMA */ 7745 drvp->drive_flags &= ~DRIVE_UDMA; 7746 if (ACARD_IS_850(sc)) { 7747 idetime |= ATP850_SETTIME(drive, 7748 acard_act_dma[drvp->DMA_mode], 7749 acard_rec_dma[drvp->DMA_mode]); 7750 } else { 7751 idetime |= ATP860_SETTIME(channel, drive, 7752 acard_act_dma[drvp->DMA_mode], 7753 acard_rec_dma[drvp->DMA_mode]); 7754 } 7755 idedma_ctl |= IDEDMA_CTL_DRV_DMA(drive); 7756 } else { 7757 /* PIO only */ 7758 drvp->drive_flags &= ~(DRIVE_UDMA | DRIVE_DMA); 7759 if (ACARD_IS_850(sc)) { 7760 idetime |= ATP850_SETTIME(drive, 7761 acard_act_pio[drvp->PIO_mode], 7762 acard_rec_pio[drvp->PIO_mode]); 7763 } else { 7764 idetime |= ATP860_SETTIME(channel, drive, 7765 acard_act_pio[drvp->PIO_mode], 7766 acard_rec_pio[drvp->PIO_mode]); 7767 } 7768 pci_conf_write(sc->sc_pc, sc->sc_tag, ATP8x0_CTRL, 7769 pci_conf_read(sc->sc_pc, sc->sc_tag, ATP8x0_CTRL) 7770 | ATP8x0_CTRL_EN(channel)); 7771 } 7772 } 7773 7774 if (idedma_ctl != 0) { 7775 /* Add software bits in status register */ 7776 bus_space_write_1(sc->sc_dma_iot, sc->sc_dma_ioh, 7777 IDEDMA_CTL(channel), idedma_ctl); 7778 } 7779 pciide_print_modes(cp); 7780 7781 if (ACARD_IS_850(sc)) { 7782 pci_conf_write(sc->sc_pc, sc->sc_tag, 7783 ATP850_IDETIME(channel), idetime); 7784 pci_conf_write(sc->sc_pc, sc->sc_tag, ATP850_UDMA, udma_mode); 7785 } else { 7786 pci_conf_write(sc->sc_pc, sc->sc_tag, ATP860_IDETIME, idetime); 7787 pci_conf_write(sc->sc_pc, sc->sc_tag, ATP860_UDMA, udma_mode); 7788 } 7789 } 7790 7791 void 7792 nforce_chip_map(struct pciide_softc *sc, struct pci_attach_args *pa) 7793 { 7794 struct pciide_channel *cp; 7795 int channel; 7796 pcireg_t interface = PCI_INTERFACE(pa->pa_class); 7797 bus_size_t cmdsize, ctlsize; 7798 u_int32_t conf; 7799 7800 conf = pci_conf_read(sc->sc_pc, sc->sc_tag, NFORCE_CONF); 7801 WDCDEBUG_PRINT(("%s: conf register 0x%x\n", 7802 sc->sc_wdcdev.sc_dev.dv_xname, conf), DEBUG_PROBE); 7803 7804 printf(": DMA"); 7805 pciide_mapreg_dma(sc, pa); 7806 7807 sc->sc_wdcdev.cap = WDC_CAPABILITY_DATA16 | WDC_CAPABILITY_DATA32 | 7808 WDC_CAPABILITY_MODE; 7809 if (sc->sc_dma_ok) { 7810 sc->sc_wdcdev.cap |= WDC_CAPABILITY_DMA | WDC_CAPABILITY_UDMA; 7811 sc->sc_wdcdev.cap |= WDC_CAPABILITY_IRQACK; 7812 sc->sc_wdcdev.irqack = pciide_irqack; 7813 } 7814 sc->sc_wdcdev.PIO_cap = 4; 7815 sc->sc_wdcdev.DMA_cap = 2; 7816 switch (sc->sc_pp->ide_product) { 7817 case PCI_PRODUCT_NVIDIA_NFORCE_IDE: 7818 sc->sc_wdcdev.UDMA_cap = 5; 7819 break; 7820 default: 7821 sc->sc_wdcdev.UDMA_cap = 6; 7822 } 7823 sc->sc_wdcdev.set_modes = nforce_setup_channel; 7824 sc->sc_wdcdev.channels = sc->wdc_chanarray; 7825 sc->sc_wdcdev.nchannels = PCIIDE_NUM_CHANNELS; 7826 7827 pciide_print_channels(sc->sc_wdcdev.nchannels, interface); 7828 7829 for (channel = 0; channel < sc->sc_wdcdev.nchannels; channel++) { 7830 cp = &sc->pciide_channels[channel]; 7831 7832 if (pciide_chansetup(sc, channel, interface) == 0) 7833 continue; 7834 7835 if ((conf & NFORCE_CHAN_EN(channel)) == 0) { 7836 printf("%s: %s ignored (disabled)\n", 7837 sc->sc_wdcdev.sc_dev.dv_xname, cp->name); 7838 continue; 7839 } 7840 7841 pciide_map_compat_intr(pa, cp, channel, interface); 7842 if (cp->hw_ok == 0) 7843 continue; 7844 pciide_mapchan(pa, cp, interface, &cmdsize, &ctlsize, 7845 nforce_pci_intr); 7846 if (cp->hw_ok == 0) { 7847 pciide_unmap_compat_intr(pa, cp, channel, interface); 7848 continue; 7849 } 7850 7851 if (pciide_chan_candisable(cp)) { 7852 conf &= ~NFORCE_CHAN_EN(channel); 7853 pciide_unmap_compat_intr(pa, cp, channel, interface); 7854 continue; 7855 } 7856 7857 sc->sc_wdcdev.set_modes(&cp->wdc_channel); 7858 } 7859 WDCDEBUG_PRINT(("%s: new conf register 0x%x\n", 7860 sc->sc_wdcdev.sc_dev.dv_xname, conf), DEBUG_PROBE); 7861 pci_conf_write(sc->sc_pc, sc->sc_tag, NFORCE_CONF, conf); 7862 } 7863 7864 void 7865 nforce_setup_channel(struct channel_softc *chp) 7866 { 7867 struct ata_drive_datas *drvp; 7868 int drive, mode; 7869 u_int32_t idedma_ctl; 7870 struct pciide_channel *cp = (struct pciide_channel *)chp; 7871 struct pciide_softc *sc = (struct pciide_softc *)cp->wdc_channel.wdc; 7872 int channel = chp->channel; 7873 u_int32_t conf, piodmatim, piotim, udmatim; 7874 7875 conf = pci_conf_read(sc->sc_pc, sc->sc_tag, NFORCE_CONF); 7876 piodmatim = pci_conf_read(sc->sc_pc, sc->sc_tag, NFORCE_PIODMATIM); 7877 piotim = pci_conf_read(sc->sc_pc, sc->sc_tag, NFORCE_PIOTIM); 7878 udmatim = pci_conf_read(sc->sc_pc, sc->sc_tag, NFORCE_UDMATIM); 7879 WDCDEBUG_PRINT(("%s: %s old timing values: piodmatim=0x%x, " 7880 "piotim=0x%x, udmatim=0x%x\n", sc->sc_wdcdev.sc_dev.dv_xname, 7881 cp->name, piodmatim, piotim, udmatim), DEBUG_PROBE); 7882 7883 /* Setup DMA if needed */ 7884 pciide_channel_dma_setup(cp); 7885 7886 /* Clear all bits for this channel */ 7887 idedma_ctl = 0; 7888 piodmatim &= ~NFORCE_PIODMATIM_MASK(channel); 7889 udmatim &= ~NFORCE_UDMATIM_MASK(channel); 7890 7891 /* Per channel settings */ 7892 for (drive = 0; drive < 2; drive++) { 7893 drvp = &chp->ch_drive[drive]; 7894 7895 /* If no drive, skip */ 7896 if ((drvp->drive_flags & DRIVE) == 0) 7897 continue; 7898 7899 if ((chp->wdc->cap & WDC_CAPABILITY_UDMA) != 0 && 7900 (drvp->drive_flags & DRIVE_UDMA) != 0) { 7901 /* Setup UltraDMA mode */ 7902 drvp->drive_flags &= ~DRIVE_DMA; 7903 7904 udmatim |= NFORCE_UDMATIM_SET(channel, drive, 7905 nforce_udma[drvp->UDMA_mode]) | 7906 NFORCE_UDMA_EN(channel, drive) | 7907 NFORCE_UDMA_ENM(channel, drive); 7908 7909 mode = drvp->PIO_mode; 7910 } else if ((chp->wdc->cap & WDC_CAPABILITY_DMA) != 0 && 7911 (drvp->drive_flags & DRIVE_DMA) != 0) { 7912 /* Setup multiword DMA mode */ 7913 drvp->drive_flags &= ~DRIVE_UDMA; 7914 7915 /* mode = min(pio, dma + 2) */ 7916 if (drvp->PIO_mode <= (drvp->DMA_mode + 2)) 7917 mode = drvp->PIO_mode; 7918 else 7919 mode = drvp->DMA_mode + 2; 7920 } else { 7921 mode = drvp->PIO_mode; 7922 goto pio; 7923 } 7924 idedma_ctl |= IDEDMA_CTL_DRV_DMA(drive); 7925 7926 pio: 7927 /* Setup PIO mode */ 7928 if (mode <= 2) { 7929 drvp->DMA_mode = 0; 7930 drvp->PIO_mode = 0; 7931 mode = 0; 7932 } else { 7933 drvp->PIO_mode = mode; 7934 drvp->DMA_mode = mode - 2; 7935 } 7936 piodmatim |= NFORCE_PIODMATIM_SET(channel, drive, 7937 nforce_pio[mode]); 7938 } 7939 7940 if (idedma_ctl != 0) { 7941 /* Add software bits in status register */ 7942 bus_space_write_1(sc->sc_dma_iot, sc->sc_dma_ioh, 7943 IDEDMA_CTL(channel), idedma_ctl); 7944 } 7945 7946 WDCDEBUG_PRINT(("%s: %s new timing values: piodmatim=0x%x, " 7947 "piotim=0x%x, udmatim=0x%x\n", sc->sc_wdcdev.sc_dev.dv_xname, 7948 cp->name, piodmatim, piotim, udmatim), DEBUG_PROBE); 7949 pci_conf_write(sc->sc_pc, sc->sc_tag, NFORCE_PIODMATIM, piodmatim); 7950 pci_conf_write(sc->sc_pc, sc->sc_tag, NFORCE_UDMATIM, udmatim); 7951 7952 pciide_print_modes(cp); 7953 } 7954 7955 int 7956 nforce_pci_intr(void *arg) 7957 { 7958 struct pciide_softc *sc = arg; 7959 struct pciide_channel *cp; 7960 struct channel_softc *wdc_cp; 7961 int i, rv, crv; 7962 u_int32_t dmastat; 7963 7964 rv = 0; 7965 for (i = 0; i < sc->sc_wdcdev.nchannels; i++) { 7966 cp = &sc->pciide_channels[i]; 7967 wdc_cp = &cp->wdc_channel; 7968 7969 /* Skip compat channel */ 7970 if (cp->compat) 7971 continue; 7972 7973 dmastat = bus_space_read_1(sc->sc_dma_iot, sc->sc_dma_ioh, 7974 IDEDMA_CTL(i)); 7975 if ((dmastat & IDEDMA_CTL_INTR) == 0) 7976 continue; 7977 7978 crv = wdcintr(wdc_cp); 7979 if (crv == 0) 7980 printf("%s:%d: bogus intr\n", 7981 sc->sc_wdcdev.sc_dev.dv_xname, i); 7982 else 7983 rv = 1; 7984 } 7985 return (rv); 7986 } 7987 7988 void 7989 artisea_chip_map(struct pciide_softc *sc, struct pci_attach_args *pa) 7990 { 7991 struct pciide_channel *cp; 7992 bus_size_t cmdsize, ctlsize; 7993 pcireg_t interface; 7994 int channel; 7995 7996 printf(": DMA"); 7997 #ifdef PCIIDE_I31244_DISABLEDMA 7998 if (sc->sc_rev == 0) { 7999 printf(" disabled due to rev. 0"); 8000 sc->sc_dma_ok = 0; 8001 } else 8002 #endif 8003 pciide_mapreg_dma(sc, pa); 8004 printf("\n"); 8005 8006 /* 8007 * XXX Configure LEDs to show activity. 8008 */ 8009 8010 sc->sc_wdcdev.cap |= WDC_CAPABILITY_DATA16 | WDC_CAPABILITY_DATA32 | 8011 WDC_CAPABILITY_MODE | WDC_CAPABILITY_SATA; 8012 sc->sc_wdcdev.PIO_cap = 4; 8013 if (sc->sc_dma_ok) { 8014 sc->sc_wdcdev.cap |= WDC_CAPABILITY_DMA | WDC_CAPABILITY_UDMA; 8015 sc->sc_wdcdev.cap |= WDC_CAPABILITY_IRQACK; 8016 sc->sc_wdcdev.irqack = pciide_irqack; 8017 sc->sc_wdcdev.DMA_cap = 2; 8018 sc->sc_wdcdev.UDMA_cap = 6; 8019 } 8020 sc->sc_wdcdev.set_modes = sata_setup_channel; 8021 8022 sc->sc_wdcdev.channels = sc->wdc_chanarray; 8023 sc->sc_wdcdev.nchannels = PCIIDE_NUM_CHANNELS; 8024 8025 interface = PCI_INTERFACE(pa->pa_class); 8026 8027 for (channel = 0; channel < sc->sc_wdcdev.nchannels; channel++) { 8028 cp = &sc->pciide_channels[channel]; 8029 if (pciide_chansetup(sc, channel, interface) == 0) 8030 continue; 8031 pciide_mapchan(pa, cp, interface, &cmdsize, &ctlsize, 8032 pciide_pci_intr); 8033 if (cp->hw_ok == 0) 8034 continue; 8035 pciide_map_compat_intr(pa, cp, channel, interface); 8036 sata_setup_channel(&cp->wdc_channel); 8037 } 8038 } 8039 8040 void 8041 ite_chip_map(struct pciide_softc *sc, struct pci_attach_args *pa) 8042 { 8043 struct pciide_channel *cp; 8044 int channel; 8045 pcireg_t interface; 8046 bus_size_t cmdsize, ctlsize; 8047 pcireg_t cfg, modectl; 8048 8049 /* 8050 * Fake interface since IT8212F is claimed to be a ``RAID'' device. 8051 */ 8052 interface = PCIIDE_INTERFACE_BUS_MASTER_DMA | 8053 PCIIDE_INTERFACE_PCI(0) | PCIIDE_INTERFACE_PCI(1); 8054 8055 cfg = pci_conf_read(sc->sc_pc, sc->sc_tag, IT_CFG); 8056 modectl = pci_conf_read(sc->sc_pc, sc->sc_tag, IT_MODE); 8057 WDCDEBUG_PRINT(("%s: cfg=0x%x, modectl=0x%x\n", 8058 sc->sc_wdcdev.sc_dev.dv_xname, cfg & IT_CFG_MASK, 8059 modectl & IT_MODE_MASK), DEBUG_PROBE); 8060 8061 printf(": DMA"); 8062 pciide_mapreg_dma(sc, pa); 8063 8064 sc->sc_wdcdev.cap = WDC_CAPABILITY_DATA16 | WDC_CAPABILITY_DATA32 | 8065 WDC_CAPABILITY_MODE; 8066 if (sc->sc_dma_ok) { 8067 sc->sc_wdcdev.cap |= WDC_CAPABILITY_DMA | WDC_CAPABILITY_UDMA; 8068 sc->sc_wdcdev.cap |= WDC_CAPABILITY_IRQACK; 8069 sc->sc_wdcdev.irqack = pciide_irqack; 8070 } 8071 sc->sc_wdcdev.PIO_cap = 4; 8072 sc->sc_wdcdev.DMA_cap = 2; 8073 sc->sc_wdcdev.UDMA_cap = 6; 8074 8075 sc->sc_wdcdev.set_modes = ite_setup_channel; 8076 sc->sc_wdcdev.channels = sc->wdc_chanarray; 8077 sc->sc_wdcdev.nchannels = PCIIDE_NUM_CHANNELS; 8078 8079 pciide_print_channels(sc->sc_wdcdev.nchannels, interface); 8080 8081 /* Disable RAID */ 8082 modectl &= ~IT_MODE_RAID1; 8083 /* Disable CPU firmware mode */ 8084 modectl &= ~IT_MODE_CPU; 8085 8086 pci_conf_write(sc->sc_pc, sc->sc_tag, IT_MODE, modectl); 8087 8088 for (channel = 0; channel < sc->sc_wdcdev.nchannels; channel++) { 8089 cp = &sc->pciide_channels[channel]; 8090 8091 if (pciide_chansetup(sc, channel, interface) == 0) 8092 continue; 8093 pciide_mapchan(pa, cp, interface, &cmdsize, &ctlsize, 8094 pciide_pci_intr); 8095 sc->sc_wdcdev.set_modes(&cp->wdc_channel); 8096 } 8097 8098 /* Re-read configuration registers after channels setup */ 8099 cfg = pci_conf_read(sc->sc_pc, sc->sc_tag, IT_CFG); 8100 modectl = pci_conf_read(sc->sc_pc, sc->sc_tag, IT_MODE); 8101 WDCDEBUG_PRINT(("%s: cfg=0x%x, modectl=0x%x\n", 8102 sc->sc_wdcdev.sc_dev.dv_xname, cfg & IT_CFG_MASK, 8103 modectl & IT_MODE_MASK), DEBUG_PROBE); 8104 } 8105 8106 void 8107 ite_setup_channel(struct channel_softc *chp) 8108 { 8109 struct ata_drive_datas *drvp; 8110 int drive, mode; 8111 u_int32_t idedma_ctl; 8112 struct pciide_channel *cp = (struct pciide_channel *)chp; 8113 struct pciide_softc *sc = (struct pciide_softc *)cp->wdc_channel.wdc; 8114 int channel = chp->channel; 8115 pcireg_t cfg, modectl; 8116 pcireg_t tim; 8117 8118 cfg = pci_conf_read(sc->sc_pc, sc->sc_tag, IT_CFG); 8119 modectl = pci_conf_read(sc->sc_pc, sc->sc_tag, IT_MODE); 8120 tim = pci_conf_read(sc->sc_pc, sc->sc_tag, IT_TIM(channel)); 8121 WDCDEBUG_PRINT(("%s:%d: tim=0x%x\n", sc->sc_wdcdev.sc_dev.dv_xname, 8122 channel, tim), DEBUG_PROBE); 8123 8124 /* Setup DMA if needed */ 8125 pciide_channel_dma_setup(cp); 8126 8127 /* Clear all bits for this channel */ 8128 idedma_ctl = 0; 8129 8130 /* Per channel settings */ 8131 for (drive = 0; drive < 2; drive++) { 8132 drvp = &chp->ch_drive[drive]; 8133 8134 /* If no drive, skip */ 8135 if ((drvp->drive_flags & DRIVE) == 0) 8136 continue; 8137 8138 if ((chp->wdc->cap & WDC_CAPABILITY_UDMA) != 0 && 8139 (drvp->drive_flags & DRIVE_UDMA) != 0) { 8140 /* Setup UltraDMA mode */ 8141 drvp->drive_flags &= ~DRIVE_DMA; 8142 modectl &= ~IT_MODE_DMA(channel, drive); 8143 8144 #if 0 8145 /* Check cable, works only in CPU firmware mode */ 8146 if (drvp->UDMA_mode > 2 && 8147 (cfg & IT_CFG_CABLE(channel, drive)) == 0) { 8148 WDCDEBUG_PRINT(("%s(%s:%d:%d): " 8149 "80-wire cable not detected\n", 8150 drvp->drive_name, 8151 sc->sc_wdcdev.sc_dev.dv_xname, 8152 channel, drive), DEBUG_PROBE); 8153 drvp->UDMA_mode = 2; 8154 } 8155 #endif 8156 8157 if (drvp->UDMA_mode >= 5) 8158 tim |= IT_TIM_UDMA5(drive); 8159 else 8160 tim &= ~IT_TIM_UDMA5(drive); 8161 8162 mode = drvp->PIO_mode; 8163 } else if ((chp->wdc->cap & WDC_CAPABILITY_DMA) != 0 && 8164 (drvp->drive_flags & DRIVE_DMA) != 0) { 8165 /* Setup multiword DMA mode */ 8166 drvp->drive_flags &= ~DRIVE_UDMA; 8167 modectl |= IT_MODE_DMA(channel, drive); 8168 8169 /* mode = min(pio, dma + 2) */ 8170 if (drvp->PIO_mode <= (drvp->DMA_mode + 2)) 8171 mode = drvp->PIO_mode; 8172 else 8173 mode = drvp->DMA_mode + 2; 8174 } else { 8175 goto pio; 8176 } 8177 idedma_ctl |= IDEDMA_CTL_DRV_DMA(drive); 8178 8179 pio: 8180 /* Setup PIO mode */ 8181 if (mode <= 2) { 8182 drvp->DMA_mode = 0; 8183 drvp->PIO_mode = 0; 8184 mode = 0; 8185 } else { 8186 drvp->PIO_mode = mode; 8187 drvp->DMA_mode = mode - 2; 8188 } 8189 8190 /* Enable IORDY if PIO mode >= 3 */ 8191 if (drvp->PIO_mode >= 3) 8192 cfg |= IT_CFG_IORDY(channel); 8193 } 8194 8195 WDCDEBUG_PRINT(("%s: tim=0x%x\n", sc->sc_wdcdev.sc_dev.dv_xname, 8196 tim), DEBUG_PROBE); 8197 8198 pci_conf_write(sc->sc_pc, sc->sc_tag, IT_CFG, cfg); 8199 pci_conf_write(sc->sc_pc, sc->sc_tag, IT_MODE, modectl); 8200 pci_conf_write(sc->sc_pc, sc->sc_tag, IT_TIM(channel), tim); 8201 8202 if (idedma_ctl != 0) { 8203 /* Add software bits in status register */ 8204 bus_space_write_1(sc->sc_dma_iot, sc->sc_dma_ioh, 8205 IDEDMA_CTL(channel), idedma_ctl); 8206 } 8207 8208 pciide_print_modes(cp); 8209 } 8210 8211 void 8212 ixp_chip_map(struct pciide_softc *sc, struct pci_attach_args *pa) 8213 { 8214 struct pciide_channel *cp; 8215 int channel; 8216 pcireg_t interface = PCI_INTERFACE(pa->pa_class); 8217 bus_size_t cmdsize, ctlsize; 8218 8219 printf(": DMA"); 8220 pciide_mapreg_dma(sc, pa); 8221 8222 sc->sc_wdcdev.cap = WDC_CAPABILITY_DATA16 | WDC_CAPABILITY_DATA32 | 8223 WDC_CAPABILITY_MODE; 8224 if (sc->sc_dma_ok) { 8225 sc->sc_wdcdev.cap |= WDC_CAPABILITY_DMA | WDC_CAPABILITY_UDMA; 8226 sc->sc_wdcdev.cap |= WDC_CAPABILITY_IRQACK; 8227 sc->sc_wdcdev.irqack = pciide_irqack; 8228 } 8229 sc->sc_wdcdev.PIO_cap = 4; 8230 sc->sc_wdcdev.DMA_cap = 2; 8231 sc->sc_wdcdev.UDMA_cap = 6; 8232 8233 sc->sc_wdcdev.set_modes = ixp_setup_channel; 8234 sc->sc_wdcdev.channels = sc->wdc_chanarray; 8235 sc->sc_wdcdev.nchannels = PCIIDE_NUM_CHANNELS; 8236 8237 pciide_print_channels(sc->sc_wdcdev.nchannels, interface); 8238 8239 for (channel = 0; channel < sc->sc_wdcdev.nchannels; channel++) { 8240 cp = &sc->pciide_channels[channel]; 8241 if (pciide_chansetup(sc, channel, interface) == 0) 8242 continue; 8243 pciide_map_compat_intr(pa, cp, channel, interface); 8244 if (cp->hw_ok == 0) 8245 continue; 8246 pciide_mapchan(pa, cp, interface, &cmdsize, &ctlsize, 8247 pciide_pci_intr); 8248 if (cp->hw_ok == 0) { 8249 pciide_unmap_compat_intr(pa, cp, channel, interface); 8250 continue; 8251 } 8252 sc->sc_wdcdev.set_modes(&cp->wdc_channel); 8253 } 8254 } 8255 8256 void 8257 ixp_setup_channel(struct channel_softc *chp) 8258 { 8259 struct ata_drive_datas *drvp; 8260 int drive, mode; 8261 u_int32_t idedma_ctl; 8262 struct pciide_channel *cp = (struct pciide_channel*)chp; 8263 struct pciide_softc *sc = (struct pciide_softc *)cp->wdc_channel.wdc; 8264 int channel = chp->channel; 8265 pcireg_t udma, mdma_timing, pio, pio_timing; 8266 8267 pio_timing = pci_conf_read(sc->sc_pc, sc->sc_tag, IXP_PIO_TIMING); 8268 pio = pci_conf_read(sc->sc_pc, sc->sc_tag, IXP_PIO_CTL); 8269 mdma_timing = pci_conf_read(sc->sc_pc, sc->sc_tag, IXP_MDMA_TIMING); 8270 udma = pci_conf_read(sc->sc_pc, sc->sc_tag, IXP_UDMA_CTL); 8271 8272 /* Setup DMA if needed */ 8273 pciide_channel_dma_setup(cp); 8274 8275 idedma_ctl = 0; 8276 8277 /* Per channel settings */ 8278 for (drive = 0; drive < 2; drive++) { 8279 drvp = &chp->ch_drive[drive]; 8280 8281 /* If no drive, skip */ 8282 if ((drvp->drive_flags & DRIVE) == 0) 8283 continue; 8284 if ((chp->wdc->cap & WDC_CAPABILITY_UDMA) != 0 && 8285 (drvp->drive_flags & DRIVE_UDMA) != 0) { 8286 /* Setup UltraDMA mode */ 8287 idedma_ctl |= IDEDMA_CTL_DRV_DMA(drive); 8288 IXP_UDMA_ENABLE(udma, chp->channel, drive); 8289 IXP_SET_MODE(udma, chp->channel, drive, 8290 drvp->UDMA_mode); 8291 mode = drvp->PIO_mode; 8292 } else if ((chp->wdc->cap & WDC_CAPABILITY_DMA) != 0 && 8293 (drvp->drive_flags & DRIVE_DMA) != 0) { 8294 /* Setup multiword DMA mode */ 8295 drvp->drive_flags &= ~DRIVE_UDMA; 8296 idedma_ctl |= IDEDMA_CTL_DRV_DMA(drive); 8297 IXP_UDMA_DISABLE(udma, chp->channel, drive); 8298 IXP_SET_TIMING(mdma_timing, chp->channel, drive, 8299 ixp_mdma_timings[drvp->DMA_mode]); 8300 8301 /* mode = min(pio, dma + 2) */ 8302 if (drvp->PIO_mode <= (drvp->DMA_mode + 2)) 8303 mode = drvp->PIO_mode; 8304 else 8305 mode = drvp->DMA_mode + 2; 8306 } else { 8307 mode = drvp->PIO_mode; 8308 } 8309 8310 /* Setup PIO mode */ 8311 drvp->PIO_mode = mode; 8312 if (mode < 2) 8313 drvp->DMA_mode = 0; 8314 else 8315 drvp->DMA_mode = mode - 2; 8316 /* 8317 * Set PIO mode and timings 8318 * Linux driver avoids PIO mode 1, let's do it too. 8319 */ 8320 if (drvp->PIO_mode == 1) 8321 drvp->PIO_mode = 0; 8322 8323 IXP_SET_MODE(pio, chp->channel, drive, drvp->PIO_mode); 8324 IXP_SET_TIMING(pio_timing, chp->channel, drive, 8325 ixp_pio_timings[drvp->PIO_mode]); 8326 } 8327 8328 pci_conf_write(sc->sc_pc, sc->sc_tag, IXP_UDMA_CTL, udma); 8329 pci_conf_write(sc->sc_pc, sc->sc_tag, IXP_MDMA_TIMING, mdma_timing); 8330 pci_conf_write(sc->sc_pc, sc->sc_tag, IXP_PIO_CTL, pio); 8331 pci_conf_write(sc->sc_pc, sc->sc_tag, IXP_PIO_TIMING, pio_timing); 8332 8333 if (idedma_ctl != 0) { 8334 /* Add software bits in status register */ 8335 bus_space_write_1(sc->sc_dma_iot, sc->sc_dma_ioh, 8336 IDEDMA_CTL(channel), idedma_ctl); 8337 } 8338 8339 pciide_print_modes(cp); 8340 } 8341 8342 void 8343 jmicron_chip_map(struct pciide_softc *sc, struct pci_attach_args *pa) 8344 { 8345 struct pciide_channel *cp; 8346 int channel; 8347 pcireg_t interface = PCI_INTERFACE(pa->pa_class); 8348 bus_size_t cmdsize, ctlsize; 8349 u_int32_t conf; 8350 8351 conf = pci_conf_read(sc->sc_pc, sc->sc_tag, JMICRON_CONF); 8352 WDCDEBUG_PRINT(("%s: conf register 0x%x\n", 8353 sc->sc_wdcdev.sc_dev.dv_xname, conf), DEBUG_PROBE); 8354 8355 printf(": DMA"); 8356 pciide_mapreg_dma(sc, pa); 8357 8358 sc->sc_wdcdev.cap = WDC_CAPABILITY_DATA16 | WDC_CAPABILITY_DATA32 | 8359 WDC_CAPABILITY_MODE; 8360 if (sc->sc_dma_ok) { 8361 sc->sc_wdcdev.cap |= WDC_CAPABILITY_DMA | WDC_CAPABILITY_UDMA; 8362 sc->sc_wdcdev.cap |= WDC_CAPABILITY_IRQACK; 8363 sc->sc_wdcdev.irqack = pciide_irqack; 8364 } 8365 sc->sc_wdcdev.PIO_cap = 4; 8366 sc->sc_wdcdev.DMA_cap = 2; 8367 sc->sc_wdcdev.UDMA_cap = 6; 8368 sc->sc_wdcdev.set_modes = jmicron_setup_channel; 8369 sc->sc_wdcdev.channels = sc->wdc_chanarray; 8370 sc->sc_wdcdev.nchannels = PCIIDE_NUM_CHANNELS; 8371 8372 pciide_print_channels(sc->sc_wdcdev.nchannels, interface); 8373 8374 for (channel = 0; channel < sc->sc_wdcdev.nchannels; channel++) { 8375 cp = &sc->pciide_channels[channel]; 8376 8377 if (pciide_chansetup(sc, channel, interface) == 0) 8378 continue; 8379 8380 #if 0 8381 if ((conf & JMICRON_CHAN_EN(channel)) == 0) { 8382 printf("%s: %s ignored (disabled)\n", 8383 sc->sc_wdcdev.sc_dev.dv_xname, cp->name); 8384 continue; 8385 } 8386 #endif 8387 8388 pciide_map_compat_intr(pa, cp, channel, interface); 8389 if (cp->hw_ok == 0) 8390 continue; 8391 pciide_mapchan(pa, cp, interface, &cmdsize, &ctlsize, 8392 pciide_pci_intr); 8393 if (cp->hw_ok == 0) { 8394 pciide_unmap_compat_intr(pa, cp, channel, interface); 8395 continue; 8396 } 8397 8398 if (pciide_chan_candisable(cp)) { 8399 conf &= ~JMICRON_CHAN_EN(channel); 8400 pciide_unmap_compat_intr(pa, cp, channel, interface); 8401 continue; 8402 } 8403 8404 sc->sc_wdcdev.set_modes(&cp->wdc_channel); 8405 } 8406 WDCDEBUG_PRINT(("%s: new conf register 0x%x\n", 8407 sc->sc_wdcdev.sc_dev.dv_xname, conf), DEBUG_PROBE); 8408 pci_conf_write(sc->sc_pc, sc->sc_tag, NFORCE_CONF, conf); 8409 } 8410 8411 void 8412 jmicron_setup_channel(struct channel_softc *chp) 8413 { 8414 struct ata_drive_datas *drvp; 8415 int drive, mode; 8416 u_int32_t idedma_ctl; 8417 struct pciide_channel *cp = (struct pciide_channel *)chp; 8418 struct pciide_softc *sc = (struct pciide_softc *)cp->wdc_channel.wdc; 8419 int channel = chp->channel; 8420 u_int32_t conf; 8421 8422 conf = pci_conf_read(sc->sc_pc, sc->sc_tag, JMICRON_CONF); 8423 8424 /* Setup DMA if needed */ 8425 pciide_channel_dma_setup(cp); 8426 8427 /* Clear all bits for this channel */ 8428 idedma_ctl = 0; 8429 8430 /* Per channel settings */ 8431 for (drive = 0; drive < 2; drive++) { 8432 drvp = &chp->ch_drive[drive]; 8433 8434 /* If no drive, skip */ 8435 if ((drvp->drive_flags & DRIVE) == 0) 8436 continue; 8437 8438 if ((chp->wdc->cap & WDC_CAPABILITY_UDMA) != 0 && 8439 (drvp->drive_flags & DRIVE_UDMA) != 0) { 8440 /* Setup UltraDMA mode */ 8441 drvp->drive_flags &= ~DRIVE_DMA; 8442 8443 /* see if cable is up to scratch */ 8444 if ((conf & JMICRON_CONF_40PIN) && 8445 (drvp->UDMA_mode > 2)) 8446 drvp->UDMA_mode = 2; 8447 8448 mode = drvp->PIO_mode; 8449 } else if ((chp->wdc->cap & WDC_CAPABILITY_DMA) != 0 && 8450 (drvp->drive_flags & DRIVE_DMA) != 0) { 8451 /* Setup multiword DMA mode */ 8452 drvp->drive_flags &= ~DRIVE_UDMA; 8453 8454 /* mode = min(pio, dma + 2) */ 8455 if (drvp->PIO_mode <= (drvp->DMA_mode + 2)) 8456 mode = drvp->PIO_mode; 8457 else 8458 mode = drvp->DMA_mode + 2; 8459 } else { 8460 mode = drvp->PIO_mode; 8461 goto pio; 8462 } 8463 idedma_ctl |= IDEDMA_CTL_DRV_DMA(drive); 8464 8465 pio: 8466 /* Setup PIO mode */ 8467 if (mode <= 2) { 8468 drvp->DMA_mode = 0; 8469 drvp->PIO_mode = 0; 8470 } else { 8471 drvp->PIO_mode = mode; 8472 drvp->DMA_mode = mode - 2; 8473 } 8474 } 8475 8476 if (idedma_ctl != 0) { 8477 /* Add software bits in status register */ 8478 bus_space_write_1(sc->sc_dma_iot, sc->sc_dma_ioh, 8479 IDEDMA_CTL(channel), idedma_ctl); 8480 } 8481 8482 pciide_print_modes(cp); 8483 } 8484