1 /* $OpenBSD: pccbbvar.h,v 1.13 2007/11/30 08:12:00 miod Exp $ */ 2 /* $NetBSD: pccbbvar.h,v 1.13 2000/06/08 10:28:29 haya Exp $ */ 3 /* 4 * Copyright (c) 1999 HAYAKAWA Koichi. All rights reserved. 5 * 6 * Redistribution and use in source and binary forms, with or without 7 * modification, are permitted provided that the following conditions 8 * are met: 9 * 1. Redistributions of source code must retain the above copyright 10 * notice, this list of conditions and the following disclaimer. 11 * 2. Redistributions in binary form must reproduce the above copyright 12 * notice, this list of conditions and the following disclaimer in the 13 * documentation and/or other materials provided with the distribution. 14 * 3. All advertising materials mentioning features or use of this software 15 * must display the following acknowledgement: 16 * This product includes software developed by HAYAKAWA Koichi. 17 * 4. The name of the author may not be used to endorse or promote products 18 * derived from this software without specific prior written permission. 19 * 20 * THIS SOFTWARE IS PROVIDED BY THE AUTHOR ``AS IS'' AND ANY EXPRESS OR 21 * IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED WARRANTIES 22 * OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE DISCLAIMED. 23 * IN NO EVENT SHALL THE AUTHOR BE LIABLE FOR ANY DIRECT, INDIRECT, 24 * INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT 25 * NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, 26 * DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY 27 * THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT 28 * (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE OF 29 * THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE. 30 */ 31 32 /* require sys/device.h */ 33 /* require sys/queue.h */ 34 /* require sys/callout.h */ 35 /* require dev/ic/i82365reg.h */ 36 /* require dev/ic/i82365var.h */ 37 38 #ifndef _DEV_PCI_PCCBBVAR_H_ 39 #define _DEV_PCI_PCCBBVAR_H_ 40 41 #include <sys/timeout.h> 42 43 #define PCIC_FLAG_SOCKETP 0x0001 44 #define PCIC_FLAG_CARDP 0x0002 45 46 /* Chipset ID */ 47 #define CB_UNKNOWN 0 /* NOT Cardbus-PCI bridge */ 48 #define CB_TI113X 1 /* TI PCI1130/1131 */ 49 #define CB_TI12XX 2 /* TI PCI1250/1220 */ 50 #define CB_RX5C47X 3 /* RICOH RX5C475/476/477 */ 51 #define CB_RX5C46X 4 /* RICOH RX5C465/466/467 */ 52 #define CB_TOPIC95 5 /* Toshiba ToPIC95 */ 53 #define CB_TOPIC95B 6 /* Toshiba ToPIC95B */ 54 #define CB_TOPIC97 7 /* Toshiba ToPIC97 */ 55 #define CB_CIRRUS 8 /* Cirrus Logic CL-PD683X */ 56 #define CB_TI125X 9 /* TI PCI1250/1251(B)/1450 */ 57 #define CB_OLDO2MICRO 10 /* O2Micro */ 58 #define CB_CHIPS_LAST 11 /* Sentinel */ 59 60 #define PCCARD_VCC_UKN 0x00 /* Unknown */ 61 #define PCCARD_VCC_5V 0x01 62 #define PCCARD_VCC_3V 0x02 63 #define PCCARD_VCC_XV 0x04 64 #define PCCARD_VCC_YV 0x08 65 66 #if 0 67 static char *cb_chipset_name[CB_CHIPS_LAST] = { 68 "unknown", "TI 113X", "TI 12XX", "RF5C47X", "RF5C46X", "ToPIC95", 69 "ToPIC95B", "ToPIC97", "CL-PD 683X", "TI 125X", 70 }; 71 #endif 72 73 struct pccbb_softc; 74 struct pccbb_intrhand_list; 75 76 77 struct cbb_pcic_handle { 78 struct device *ph_parent; 79 bus_space_tag_t ph_base_t; 80 bus_space_handle_t ph_base_h; 81 u_int8_t (*ph_read)(struct cbb_pcic_handle *, int); 82 void (*ph_write)(struct cbb_pcic_handle *, int, u_int8_t); 83 int sock; 84 85 int vendor; 86 int flags; 87 int memalloc; 88 struct { 89 bus_addr_t addr; 90 bus_size_t size; 91 long offset; 92 int kind; 93 } mem[PCIC_MEM_WINS]; 94 int ioalloc; 95 struct { 96 bus_addr_t addr; 97 bus_size_t size; 98 int width; 99 } io[PCIC_IO_WINS]; 100 int ih_irq; 101 struct device *pcmcia; 102 103 int shutdown; 104 }; 105 106 struct pccbb_win_chain { 107 bus_addr_t wc_start; /* Caution: region [start, end], */ 108 bus_addr_t wc_end; /* instead of [start, end). */ 109 int wc_flags; 110 bus_space_handle_t wc_handle; 111 TAILQ_ENTRY(pccbb_win_chain) wc_list; 112 }; 113 #define PCCBB_MEM_CACHABLE 1 114 115 TAILQ_HEAD(pccbb_win_chain_head, pccbb_win_chain); 116 117 struct pccbb_softc { 118 struct device sc_dev; 119 bus_space_tag_t sc_iot; 120 bus_space_tag_t sc_memt; 121 bus_dma_tag_t sc_dmat; 122 123 rbus_tag_t sc_rbus_iot; /* rbus for i/o donated from parent */ 124 rbus_tag_t sc_rbus_memt; /* rbus for mem donated from parent */ 125 126 bus_space_tag_t sc_base_memt; 127 bus_space_handle_t sc_base_memh; 128 129 struct timeout sc_ins_tmo; 130 void *sc_ih; /* interrupt handler */ 131 int sc_intrline; /* interrupt line */ 132 pcitag_t sc_intrtag; /* copy of pa->pa_intrtag */ 133 pci_intr_pin_t sc_intrpin; /* copy of pa->pa_intrpin */ 134 int sc_function; 135 u_int32_t sc_flags; 136 #define CBB_CARDEXIST 0x01 137 #define CBB_INSERTING 0x01000000 138 #define CBB_16BITCARD 0x04 139 #define CBB_32BITCARD 0x08 140 #define CBB_MEMHMAPPED 0x02000000 141 142 pci_chipset_tag_t sc_pc; 143 pcitag_t sc_tag; 144 pcireg_t sc_id; 145 int sc_chipset; /* chipset id */ 146 int sc_ints_on; 147 148 bus_addr_t sc_mem_start; /* CardBus/PCMCIA memory start */ 149 bus_addr_t sc_mem_end; /* CardBus/PCMCIA memory end */ 150 bus_addr_t sc_io_start; /* CardBus/PCMCIA io start */ 151 bus_addr_t sc_io_end; /* CardBus/PCMCIA io end */ 152 153 pcireg_t sc_sockbase; /* Socket base register */ 154 pcireg_t sc_busnum; /* bus number */ 155 156 /* CardBus stuff */ 157 struct cardslot_softc *sc_csc; 158 159 struct pccbb_win_chain_head sc_memwindow; 160 struct pccbb_win_chain_head sc_iowindow; 161 162 /* pcmcia stuff */ 163 struct pcic_handle sc_pcmcia_h; 164 pcmcia_chipset_tag_t sc_pct; 165 int sc_pcmcia_flags; 166 #define PCCBB_PCMCIA_IO_RELOC 0x01 /* IO addr relocatable stuff exists */ 167 #define PCCBB_PCMCIA_MEM_32 0x02 /* 32-bit memory address ready */ 168 #define PCCBB_PCMCIA_16BITONLY 0x04 /* 32-bit mode disable */ 169 170 struct proc *sc_event_thread; 171 SIMPLEQ_HEAD(, pcic_event) sc_events; 172 173 /* interrupt handler list on the bridge */ 174 struct pccbb_intrhand_list *sc_pil; 175 int sc_pil_intr_enable; /* can i call intr handler for child device? */ 176 }; 177 178 /* 179 * struct pccbb_intrhand_list holds interrupt handler and argument for 180 * child devices. 181 */ 182 183 struct pccbb_intrhand_list { 184 int (*pil_func)(void *); 185 void *pil_arg; 186 int pil_level; 187 struct evcount pil_count; 188 struct pccbb_intrhand_list *pil_next; 189 }; 190 191 #endif /* _DEV_PCI_PCCBBREG_H_ */ 192