1 /* $OpenBSD: pccbb.c,v 1.96 2015/09/11 09:15:44 deraadt Exp $ */ 2 /* $NetBSD: pccbb.c,v 1.96 2004/03/28 09:49:31 nakayama Exp $ */ 3 4 /* 5 * Copyright (c) 1998, 1999 and 2000 6 * HAYAKAWA Koichi. All rights reserved. 7 * 8 * Redistribution and use in source and binary forms, with or without 9 * modification, are permitted provided that the following conditions 10 * are met: 11 * 1. Redistributions of source code must retain the above copyright 12 * notice, this list of conditions and the following disclaimer. 13 * 2. Redistributions in binary form must reproduce the above copyright 14 * notice, this list of conditions and the following disclaimer in the 15 * documentation and/or other materials provided with the distribution. 16 * 17 * THIS SOFTWARE IS PROVIDED BY THE AUTHOR ``AS IS'' AND ANY EXPRESS OR 18 * IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED WARRANTIES 19 * OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE DISCLAIMED. 20 * IN NO EVENT SHALL THE AUTHOR BE LIABLE FOR ANY DIRECT, INDIRECT, 21 * INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT 22 * NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, 23 * DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY 24 * THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT 25 * (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE OF 26 * THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE. 27 */ 28 29 /* 30 #define CBB_DEBUG 31 #define SHOW_REGS 32 #define PCCBB_PCMCIA_POLL 33 */ 34 35 /* 36 #define CB_PCMCIA_POLL 37 #define CB_PCMCIA_POLL_ONLY 38 #define LEVEL2 39 */ 40 41 #include <sys/types.h> 42 #include <sys/param.h> 43 #include <sys/systm.h> 44 #include <sys/kernel.h> 45 #include <sys/evcount.h> 46 #include <sys/ioctl.h> 47 #include <sys/syslog.h> 48 #include <sys/device.h> 49 #include <sys/malloc.h> 50 #include <sys/task.h> 51 52 #include <machine/intr.h> 53 #include <machine/bus.h> 54 55 #include <dev/pci/pcivar.h> 56 #include <dev/pci/pcireg.h> 57 #include <dev/pci/pcidevs.h> 58 59 #include <dev/pci/pccbbreg.h> 60 61 #include <dev/cardbus/cardslotvar.h> 62 63 #include <dev/cardbus/cardbusvar.h> 64 65 #include <dev/pcmcia/pcmciareg.h> 66 #include <dev/pcmcia/pcmciavar.h> 67 68 #include <dev/ic/i82365reg.h> 69 #include <dev/ic/i82365var.h> 70 #include <dev/pci/pccbbvar.h> 71 72 #ifndef __NetBSD_Version__ 73 struct cfdriver cbb_cd = { 74 NULL, "cbb", DV_DULL 75 }; 76 #endif 77 78 #if defined CBB_DEBUG 79 #define DPRINTF(x) printf x 80 #else 81 #define DPRINTF(x) 82 #endif 83 84 int pcicbbmatch(struct device *, void *, void *); 85 void pccbbattach(struct device *, struct device *, void *); 86 int pccbbactivate(struct device *, int); 87 int pccbbintr(void *); 88 void pccbb_shutdown(void *); 89 void pci113x_insert(void *); 90 int pccbbintr_function(struct pccbb_softc *); 91 92 int pccbb_checksockstat(struct pccbb_softc *); 93 int pccbb_detect_card(struct pccbb_softc *); 94 95 void pccbb_pcmcia_write(struct pcic_handle *, int, int); 96 u_int8_t pccbb_pcmcia_read(struct pcic_handle *, int); 97 #define Pcic_read(ph, reg) ((ph)->ph_read((ph), (reg))) 98 #define Pcic_write(ph, reg, val) ((ph)->ph_write((ph), (reg), (val))) 99 100 int cb_reset(struct pccbb_softc *); 101 int cb_detect_voltage(struct pccbb_softc *); 102 int cbbprint(void *, const char *); 103 104 int cb_chipset(u_int32_t, int *); 105 void pccbb_pcmcia_attach_setup(struct pccbb_softc *, 106 struct pcmciabus_attach_args *); 107 #if 0 108 void pccbb_pcmcia_attach_card(struct pcic_handle *); 109 void pccbb_pcmcia_detach_card(struct pcic_handle *, int); 110 void pccbb_pcmcia_deactivate_card(struct pcic_handle *); 111 #endif 112 113 int pccbb_ctrl(cardbus_chipset_tag_t, int); 114 int pccbb_power(cardbus_chipset_tag_t, int); 115 int pccbb_cardenable(struct pccbb_softc * sc, int function); 116 void *pccbb_intr_establish(struct pccbb_softc *, int irq, int level, 117 int (*ih) (void *), void *sc, const char *); 118 void pccbb_intr_disestablish(struct pccbb_softc *, void *ih); 119 120 void *pccbb_cb_intr_establish(cardbus_chipset_tag_t, int irq, int level, 121 int (*ih) (void *), void *sc, const char *); 122 void pccbb_cb_intr_disestablish(cardbus_chipset_tag_t ct, void *ih); 123 124 void pccbb_legacy_disable(struct pccbb_softc *sc); 125 void pccbb_chipinit(struct pccbb_softc *); 126 127 int pccbb_pcmcia_mem_alloc(pcmcia_chipset_handle_t, bus_size_t, 128 struct pcmcia_mem_handle *); 129 void pccbb_pcmcia_mem_free(pcmcia_chipset_handle_t, 130 struct pcmcia_mem_handle *); 131 int pccbb_pcmcia_mem_map(pcmcia_chipset_handle_t, int, bus_addr_t, 132 bus_size_t, struct pcmcia_mem_handle *, bus_size_t *, int *); 133 void pccbb_pcmcia_mem_unmap(pcmcia_chipset_handle_t, int); 134 int pccbb_pcmcia_io_alloc(pcmcia_chipset_handle_t, bus_addr_t, 135 bus_size_t, bus_size_t, struct pcmcia_io_handle *); 136 void pccbb_pcmcia_io_free(pcmcia_chipset_handle_t, 137 struct pcmcia_io_handle *); 138 int pccbb_pcmcia_io_map(pcmcia_chipset_handle_t, int, bus_addr_t, 139 bus_size_t, struct pcmcia_io_handle *, int *); 140 void pccbb_pcmcia_io_unmap(pcmcia_chipset_handle_t, int); 141 void *pccbb_pcmcia_intr_establish(pcmcia_chipset_handle_t, 142 struct pcmcia_function *, int, int (*)(void *), void *, char *); 143 void pccbb_pcmcia_intr_disestablish(pcmcia_chipset_handle_t, void *); 144 const char *pccbb_pcmcia_intr_string(pcmcia_chipset_handle_t, void *); 145 void pccbb_pcmcia_socket_enable(pcmcia_chipset_handle_t); 146 void pccbb_pcmcia_socket_disable(pcmcia_chipset_handle_t); 147 int pccbb_pcmcia_card_detect(pcmcia_chipset_handle_t pch); 148 149 void pccbb_pcmcia_do_io_map(struct pcic_handle *, int); 150 void pccbb_pcmcia_wait_ready(struct pcic_handle *); 151 void pccbb_pcmcia_do_mem_map(struct pcic_handle *, int); 152 153 /* bus-space allocation and deallocation functions */ 154 int pccbb_rbus_cb_space_alloc(cardbus_chipset_tag_t, rbus_tag_t, 155 bus_addr_t addr, bus_size_t size, bus_addr_t mask, bus_size_t align, 156 int flags, bus_addr_t * addrp, bus_space_handle_t * bshp); 157 int pccbb_rbus_cb_space_free(cardbus_chipset_tag_t, rbus_tag_t, 158 bus_space_handle_t, bus_size_t); 159 160 int pccbb_open_win(struct pccbb_softc *, bus_space_tag_t, 161 bus_addr_t, bus_size_t, bus_space_handle_t, int flags); 162 int pccbb_close_win(struct pccbb_softc *, bus_space_tag_t, 163 bus_space_handle_t, bus_size_t); 164 int pccbb_winlist_insert(struct pccbb_win_chain_head *, bus_addr_t, 165 bus_size_t, bus_space_handle_t, int); 166 int pccbb_winlist_delete(struct pccbb_win_chain_head *, 167 bus_space_handle_t, bus_size_t); 168 void pccbb_winset(bus_addr_t align, struct pccbb_softc *, 169 bus_space_tag_t); 170 void pccbb_winlist_show(struct pccbb_win_chain *); 171 172 /* for config_defer */ 173 void pccbb_pci_callback(struct device *); 174 175 #if defined SHOW_REGS 176 void cb_show_regs(pci_chipset_tag_t, pcitag_t, bus_space_tag_t, 177 bus_space_handle_t memh); 178 #endif 179 180 struct cfattach cbb_pci_ca = { 181 sizeof(struct pccbb_softc), pcicbbmatch, pccbbattach, NULL, 182 pccbbactivate 183 }; 184 185 static struct pcmcia_chip_functions pccbb_pcmcia_funcs = { 186 pccbb_pcmcia_mem_alloc, 187 pccbb_pcmcia_mem_free, 188 pccbb_pcmcia_mem_map, 189 pccbb_pcmcia_mem_unmap, 190 pccbb_pcmcia_io_alloc, 191 pccbb_pcmcia_io_free, 192 pccbb_pcmcia_io_map, 193 pccbb_pcmcia_io_unmap, 194 pccbb_pcmcia_intr_establish, 195 pccbb_pcmcia_intr_disestablish, 196 pccbb_pcmcia_intr_string, 197 pccbb_pcmcia_socket_enable, 198 pccbb_pcmcia_socket_disable, 199 pccbb_pcmcia_card_detect 200 }; 201 202 static struct cardbus_functions pccbb_funcs = { 203 pccbb_rbus_cb_space_alloc, 204 pccbb_rbus_cb_space_free, 205 pccbb_cb_intr_establish, 206 pccbb_cb_intr_disestablish, 207 pccbb_ctrl, 208 pccbb_power, 209 }; 210 211 /* 212 * delay_ms() is wait in milliseconds. It should be used instead 213 * of delay() if you want to wait more than 1 ms. 214 */ 215 static inline void 216 delay_ms(int millis, void *param) 217 { 218 if (cold) 219 delay(millis * 1000); 220 else 221 tsleep(param, PWAIT, "pccbb", MAX(2, hz * millis / 1000)); 222 } 223 224 int 225 pcicbbmatch(parent, match, aux) 226 struct device *parent; 227 void *match; 228 void *aux; 229 { 230 struct pci_attach_args *pa = (struct pci_attach_args *)aux; 231 232 if (PCI_CLASS(pa->pa_class) == PCI_CLASS_BRIDGE && 233 PCI_SUBCLASS(pa->pa_class) == PCI_SUBCLASS_BRIDGE_CARDBUS && 234 PCI_INTERFACE(pa->pa_class) == 0) { 235 return 1; 236 } 237 238 return 0; 239 } 240 241 #define MAKEID(vendor, prod) (((vendor) << PCI_VENDOR_SHIFT) \ 242 | ((prod) << PCI_PRODUCT_SHIFT)) 243 244 struct yenta_chipinfo { 245 pcireg_t yc_id; /* vendor tag | product tag */ 246 int yc_chiptype; 247 int yc_flags; 248 } yc_chipsets[] = { 249 /* Texas Instruments chips */ 250 { MAKEID(PCI_VENDOR_TI, PCI_PRODUCT_TI_PCI1130), CB_TI113X, 251 PCCBB_PCMCIA_IO_RELOC | PCCBB_PCMCIA_MEM_32}, 252 { MAKEID(PCI_VENDOR_TI, PCI_PRODUCT_TI_PCI1131), CB_TI113X, 253 PCCBB_PCMCIA_IO_RELOC | PCCBB_PCMCIA_MEM_32}, 254 { MAKEID(PCI_VENDOR_TI, PCI_PRODUCT_TI_PCI1250), CB_TI125X, 255 PCCBB_PCMCIA_IO_RELOC | PCCBB_PCMCIA_MEM_32}, 256 { MAKEID(PCI_VENDOR_TI, PCI_PRODUCT_TI_PCI1220), CB_TI12XX, 257 PCCBB_PCMCIA_IO_RELOC | PCCBB_PCMCIA_MEM_32}, 258 { MAKEID(PCI_VENDOR_TI, PCI_PRODUCT_TI_PCI1221), CB_TI12XX, 259 PCCBB_PCMCIA_IO_RELOC | PCCBB_PCMCIA_MEM_32}, 260 { MAKEID(PCI_VENDOR_TI, PCI_PRODUCT_TI_PCI1225), CB_TI12XX, 261 PCCBB_PCMCIA_IO_RELOC | PCCBB_PCMCIA_MEM_32}, 262 { MAKEID(PCI_VENDOR_TI, PCI_PRODUCT_TI_PCI1251), CB_TI125X, 263 PCCBB_PCMCIA_IO_RELOC | PCCBB_PCMCIA_MEM_32}, 264 { MAKEID(PCI_VENDOR_TI, PCI_PRODUCT_TI_PCI1251B), CB_TI125X, 265 PCCBB_PCMCIA_IO_RELOC | PCCBB_PCMCIA_MEM_32}, 266 { MAKEID(PCI_VENDOR_TI, PCI_PRODUCT_TI_PCI1211), CB_TI12XX, 267 PCCBB_PCMCIA_IO_RELOC | PCCBB_PCMCIA_MEM_32}, 268 { MAKEID(PCI_VENDOR_TI, PCI_PRODUCT_TI_PCI1410), CB_TI12XX, 269 PCCBB_PCMCIA_IO_RELOC | PCCBB_PCMCIA_MEM_32}, 270 { MAKEID(PCI_VENDOR_TI, PCI_PRODUCT_TI_PCI1420), CB_TI12XX, 271 PCCBB_PCMCIA_IO_RELOC | PCCBB_PCMCIA_MEM_32}, 272 { MAKEID(PCI_VENDOR_TI, PCI_PRODUCT_TI_PCI1450), CB_TI125X, 273 PCCBB_PCMCIA_IO_RELOC | PCCBB_PCMCIA_MEM_32}, 274 { MAKEID(PCI_VENDOR_TI, PCI_PRODUCT_TI_PCI1451), CB_TI12XX, 275 PCCBB_PCMCIA_IO_RELOC | PCCBB_PCMCIA_MEM_32}, 276 { MAKEID(PCI_VENDOR_TI, PCI_PRODUCT_TI_PCI1510), CB_TI12XX, 277 PCCBB_PCMCIA_IO_RELOC | PCCBB_PCMCIA_MEM_32}, 278 { MAKEID(PCI_VENDOR_TI, PCI_PRODUCT_TI_PCI7XX1), CB_TI12XX, 279 PCCBB_PCMCIA_IO_RELOC | PCCBB_PCMCIA_MEM_32}, 280 281 /* Ricoh chips */ 282 { MAKEID(PCI_VENDOR_RICOH, PCI_PRODUCT_RICOH_RF5C475), CB_RX5C47X, 283 PCCBB_PCMCIA_MEM_32}, 284 { MAKEID(PCI_VENDOR_RICOH, PCI_PRODUCT_RICOH_RF5C476), CB_RX5C47X, 285 PCCBB_PCMCIA_MEM_32}, 286 { MAKEID(PCI_VENDOR_RICOH, PCI_PRODUCT_RICOH_RF5C477), CB_RX5C47X, 287 PCCBB_PCMCIA_MEM_32}, 288 { MAKEID(PCI_VENDOR_RICOH, PCI_PRODUCT_RICOH_RF5C478), CB_RX5C47X, 289 PCCBB_PCMCIA_MEM_32}, 290 { MAKEID(PCI_VENDOR_RICOH, PCI_PRODUCT_RICOH_RF5C465), CB_RX5C46X, 291 PCCBB_PCMCIA_MEM_32}, 292 { MAKEID(PCI_VENDOR_RICOH, PCI_PRODUCT_RICOH_RF5C466), CB_RX5C46X, 293 PCCBB_PCMCIA_MEM_32}, 294 295 /* Toshiba products */ 296 { MAKEID(PCI_VENDOR_TOSHIBA2, PCI_PRODUCT_TOSHIBA2_ToPIC95), 297 CB_TOPIC95, PCCBB_PCMCIA_MEM_32}, 298 { MAKEID(PCI_VENDOR_TOSHIBA2, PCI_PRODUCT_TOSHIBA2_ToPIC95B), 299 CB_TOPIC95B, PCCBB_PCMCIA_MEM_32}, 300 { MAKEID(PCI_VENDOR_TOSHIBA2, PCI_PRODUCT_TOSHIBA2_ToPIC97), 301 CB_TOPIC97, PCCBB_PCMCIA_MEM_32}, 302 { MAKEID(PCI_VENDOR_TOSHIBA2, PCI_PRODUCT_TOSHIBA2_ToPIC100), 303 CB_TOPIC97, PCCBB_PCMCIA_MEM_32}, 304 305 /* Cirrus Logic products */ 306 { MAKEID(PCI_VENDOR_CIRRUS, PCI_PRODUCT_CIRRUS_CL_PD6832), 307 CB_CIRRUS, PCCBB_PCMCIA_MEM_32}, 308 { MAKEID(PCI_VENDOR_CIRRUS, PCI_PRODUCT_CIRRUS_CL_PD6833), 309 CB_CIRRUS, PCCBB_PCMCIA_MEM_32}, 310 311 /* older O2Micro bridges */ 312 { MAKEID(PCI_VENDOR_O2MICRO, PCI_PRODUCT_O2MICRO_OZ6729), 313 CB_OLDO2MICRO, PCCBB_PCMCIA_MEM_32}, 314 { MAKEID(PCI_VENDOR_O2MICRO, PCI_PRODUCT_O2MICRO_OZ6730), 315 CB_OLDO2MICRO, PCCBB_PCMCIA_MEM_32}, 316 { MAKEID(PCI_VENDOR_O2MICRO, PCI_PRODUCT_O2MICRO_OZ6872), /* 68[71]2 */ 317 CB_OLDO2MICRO, PCCBB_PCMCIA_MEM_32}, 318 { MAKEID(PCI_VENDOR_O2MICRO, PCI_PRODUCT_O2MICRO_OZ6832), 319 CB_OLDO2MICRO, PCCBB_PCMCIA_MEM_32}, 320 { MAKEID(PCI_VENDOR_O2MICRO, PCI_PRODUCT_O2MICRO_OZ6836), 321 CB_OLDO2MICRO, PCCBB_PCMCIA_MEM_32}, 322 323 /* sentinel, or Generic chip */ 324 { 0 /* null id */ , CB_UNKNOWN, PCCBB_PCMCIA_MEM_32}, 325 }; 326 327 int 328 cb_chipset(pci_id, flagp) 329 u_int32_t pci_id; 330 int *flagp; 331 { 332 struct yenta_chipinfo *yc; 333 334 /* Loop over except the last default entry. */ 335 for (yc = yc_chipsets; yc < yc_chipsets + 336 sizeof(yc_chipsets) / sizeof(yc_chipsets[0]) - 1; yc++) 337 if (pci_id == yc->yc_id) 338 break; 339 340 if (flagp != NULL) 341 *flagp = yc->yc_flags; 342 343 return (yc->yc_chiptype); 344 } 345 346 void 347 pccbb_shutdown(void *arg) 348 { 349 struct pccbb_softc *sc = arg; 350 pcireg_t command; 351 352 DPRINTF(("%s: shutdown\n", sc->sc_dev.dv_xname)); 353 354 /* turn off power */ 355 pccbb_power((cardbus_chipset_tag_t)sc, CARDBUS_VCC_0V | CARDBUS_VPP_0V); 356 357 bus_space_write_4(sc->sc_base_memt, sc->sc_base_memh, CB_SOCKET_MASK, 358 0); 359 360 command = pci_conf_read(sc->sc_pc, sc->sc_tag, PCI_COMMAND_STATUS_REG); 361 362 command &= ~(PCI_COMMAND_IO_ENABLE | PCI_COMMAND_MEM_ENABLE | 363 PCI_COMMAND_MASTER_ENABLE); 364 pci_conf_write(sc->sc_pc, sc->sc_tag, PCI_COMMAND_STATUS_REG, command); 365 } 366 367 void 368 pccbbattach(struct device *parent, struct device *self, void *aux) 369 { 370 struct pccbb_softc *sc = (void *)self; 371 struct pci_attach_args *pa = aux; 372 pci_chipset_tag_t pc = pa->pa_pc; 373 pci_intr_handle_t ih; 374 const char *intrstr = NULL; 375 u_long busnum; 376 int flags; 377 378 pccbb_attach_hook(parent, self, pa); 379 380 sc->sc_chipset = cb_chipset(pa->pa_id, &flags); 381 sc->sc_id = pa->pa_id; 382 383 #ifdef CBB_DEBUG 384 printf(" (chipflags %x)", flags); 385 #endif 386 387 TAILQ_INIT(&sc->sc_memwindow); 388 TAILQ_INIT(&sc->sc_iowindow); 389 390 sc->sc_rbus_iot = rbus_pccbb_parent_io(self, pa); 391 sc->sc_rbus_memt = rbus_pccbb_parent_mem(self, pa); 392 393 /* 394 * MAP socket registers and ExCA registers on memory-space 395 */ 396 if (pci_mapreg_map(pa, PCI_SOCKBASE, PCI_MAPREG_TYPE_MEM, 0, 397 &sc->sc_base_memt, &sc->sc_base_memh, NULL, NULL, 0)) { 398 printf("can't map registers\n"); 399 return; 400 } 401 402 sc->sc_busnum = pci_conf_read(pc, pa->pa_tag, PCI_BUSNUM); 403 404 #if defined CBB_DEBUG 405 { 406 static char *intrname[5] = { "NON", "A", "B", "C", "D" }; 407 printf(": intrpin %s, line %d\n", 408 intrname[pa->pa_intrpin], pa->pa_intrline); 409 } 410 #endif 411 412 /* setup softc */ 413 sc->sc_pc = pc; 414 sc->sc_iot = pa->pa_iot; 415 sc->sc_memt = pa->pa_memt; 416 sc->sc_dmat = pa->pa_dmat; 417 sc->sc_tag = pa->pa_tag; 418 sc->sc_function = pa->pa_function; 419 sc->sc_intrtag = pa->pa_intrtag; 420 sc->sc_intrpin = pa->pa_intrpin; 421 422 sc->sc_pcmcia_flags = flags; /* set PCMCIA facility */ 423 424 /* Map and establish the interrupt. */ 425 if (pci_intr_map(pa, &ih)) { 426 printf(": couldn't map interrupt\n"); 427 return; 428 } 429 intrstr = pci_intr_string(pc, ih); 430 /* must do this after intr is mapped and established */ 431 sc->sc_intrline = pci_intr_line(pc, ih); 432 433 /* 434 * XXX pccbbintr should be called under the priority lower 435 * than any other hard interrupts. 436 */ 437 sc->sc_ih = pci_intr_establish(pc, ih, IPL_BIO, pccbbintr, sc, 438 sc->sc_dev.dv_xname); 439 440 if (sc->sc_ih == NULL) { 441 printf(": couldn't establish interrupt"); 442 if (intrstr != NULL) { 443 printf(" at %s", intrstr); 444 } 445 printf("\n"); 446 return; 447 } 448 printf(": %s", intrstr); 449 450 /* 451 * When the bus number isn't configured, try to allocate one 452 * ourselves. 453 */ 454 if ((sc->sc_busnum & 0x00ffff00) == 0 && pa->pa_busex && 455 extent_alloc(pa->pa_busex, 1, 1, 0, 0, EX_NOWAIT, &busnum) == 0) { 456 sc->sc_busnum |= (busnum << 8); 457 sc->sc_busnum |= (busnum << 16); 458 pci_conf_write(pc, pa->pa_tag, PCI_BUSNUM, sc->sc_busnum); 459 } 460 461 /* 462 * When the bus number still isn't set correctly, give up 463 * using 32-bit CardBus mode. 464 */ 465 if (((sc->sc_busnum >> 8) & 0xff) == 0) { 466 printf(", CardBus support disabled"); 467 sc->sc_pcmcia_flags |= PCCBB_PCMCIA_16BITONLY; 468 } 469 470 printf("\n"); 471 472 /* Disable legacy register mapping. */ 473 pccbb_legacy_disable(sc); 474 475 timeout_set(&sc->sc_ins_tmo, pci113x_insert, sc); 476 config_defer(self, pccbb_pci_callback); 477 } 478 479 /* 480 * void pccbb_pci_callback(struct device *self) 481 * 482 * The actual attach routine: get memory space for YENTA register 483 * space, setup YENTA register and route interrupt. 484 * 485 * This function should be deferred because this device may obtain 486 * memory space dynamically. This function must avoid obtaining 487 * memory area which has already kept for another device. Also, 488 * this function MUST be done before ISA attach process because this 489 * function kills pcic compatible port used by ISA pcic. 490 */ 491 void 492 pccbb_pci_callback(struct device *self) 493 { 494 struct pccbb_softc *sc = (void *)self; 495 pci_chipset_tag_t pc = sc->sc_pc; 496 bus_space_tag_t base_memt; 497 bus_space_handle_t base_memh; 498 u_int32_t maskreg; 499 struct cbslot_attach_args cba; 500 struct pcmciabus_attach_args paa; 501 struct cardslot_attach_args caa; 502 struct cardslot_softc *csc; 503 u_int32_t sockstat; 504 505 base_memt = sc->sc_base_memt; /* socket regs memory tag */ 506 base_memh = sc->sc_base_memh; /* socket regs memory handle */ 507 508 /* bus bridge initialization */ 509 pccbb_chipinit(sc); 510 511 /* clear data structure for child device interrupt handlers */ 512 sc->sc_pil = NULL; 513 sc->sc_pil_intr_enable = 1; 514 515 sockstat = bus_space_read_4(base_memt, base_memh, CB_SOCKET_STAT); 516 if ((sockstat & CB_SOCKET_STAT_CD) == 0) 517 sc->sc_flags |= CBB_CARDEXIST; 518 519 /* 520 * attach cardbus 521 */ 522 if (!(sc->sc_pcmcia_flags & PCCBB_PCMCIA_16BITONLY)) { 523 pcireg_t busreg = pci_conf_read(pc, sc->sc_tag, PCI_BUSNUM); 524 pcireg_t bhlc = pci_conf_read(pc, sc->sc_tag, PCI_BHLC_REG); 525 526 /* initialize cbslot_attach */ 527 cba.cba_busname = "cardbus"; 528 cba.cba_iot = sc->sc_iot; 529 cba.cba_memt = sc->sc_memt; 530 cba.cba_dmat = sc->sc_dmat; 531 cba.cba_bus = (busreg >> 8) & 0x0ff; 532 cba.cba_cc = (void *)sc; 533 cba.cba_pc = sc->sc_pc; 534 cba.cba_cf = &pccbb_funcs; 535 cba.cba_intrline = sc->sc_intrline; 536 537 cba.cba_rbus_iot = sc->sc_rbus_iot; 538 cba.cba_rbus_memt = sc->sc_rbus_memt; 539 540 cba.cba_cacheline = PCI_CACHELINE(bhlc); 541 cba.cba_lattimer = PCI_CB_LATENCY(busreg); 542 543 #if defined CBB_DEBUG 544 printf("%s: cacheline 0x%x lattimer 0x%x\n", 545 sc->sc_dev.dv_xname, cba.cba_cacheline, cba.cba_lattimer); 546 printf("%s: bhlc 0x%x lscp 0x%x\n", sc->sc_dev.dv_xname, bhlc, 547 busreg); 548 #endif 549 #if defined SHOW_REGS 550 cb_show_regs(sc->sc_pc, sc->sc_tag, sc->sc_base_memt, 551 sc->sc_base_memh); 552 #endif 553 } 554 555 pccbb_pcmcia_attach_setup(sc, &paa); 556 caa.caa_cb_attach = NULL; 557 if (!(sc->sc_pcmcia_flags & PCCBB_PCMCIA_16BITONLY)) { 558 caa.caa_cb_attach = &cba; 559 } 560 caa.caa_16_attach = &paa; 561 caa.caa_ph = &sc->sc_pcmcia_h; 562 563 if (NULL != (csc = (void *)config_found(self, &caa, cbbprint))) { 564 DPRINTF(("pccbbattach: found cardslot\n")); 565 sc->sc_csc = csc; 566 } 567 568 sc->sc_ints_on = 1; 569 570 /* CSC Interrupt: Card detect interrupt on */ 571 maskreg = bus_space_read_4(base_memt, base_memh, CB_SOCKET_MASK); 572 maskreg |= CB_SOCKET_MASK_CD; /* Card detect intr is turned on. */ 573 bus_space_write_4(base_memt, base_memh, CB_SOCKET_MASK, maskreg); 574 /* reset interrupt */ 575 bus_space_write_4(base_memt, base_memh, CB_SOCKET_EVENT, 576 bus_space_read_4(base_memt, base_memh, CB_SOCKET_EVENT)); 577 578 return; 579 } 580 581 void 582 pccbb_legacy_disable(struct pccbb_softc *sc) 583 { 584 pcireg_t reg; 585 586 switch (sc->sc_chipset) { 587 case CB_RX5C46X: 588 /* 589 * The legacy pcic io-port on Ricoh RX5C46X CardBus bridges 590 * cannot be disabled by substituting 0 into PCI_LEGACY 591 * register. Ricoh CardBus bridges have special bits on Bridge 592 * control reg (addr 0x3e on PCI config space). 593 */ 594 reg = pci_conf_read(sc->sc_pc, sc->sc_tag, PCI_BCR_INTR); 595 reg &= ~(CB_BCRI_RL_3E0_ENA | CB_BCRI_RL_3E2_ENA); 596 pci_conf_write(sc->sc_pc, sc->sc_tag, PCI_BCR_INTR, reg); 597 break; 598 599 default: 600 pci_conf_write(sc->sc_pc, sc->sc_tag, PCI_LEGACY, 0x0); 601 break; 602 } 603 } 604 605 /* 606 * void pccbb_chipinit(struct pccbb_softc *sc) 607 * 608 * This function initialize YENTA chip registers listed below: 609 * 1) PCI command reg, 610 * 2) PCI and CardBus latency timer, 611 * 3) route PCI interrupt, 612 * 4) close all memory and io windows. 613 */ 614 void 615 pccbb_chipinit(struct pccbb_softc *sc) 616 { 617 pci_chipset_tag_t pc = sc->sc_pc; 618 pcitag_t tag = sc->sc_tag; 619 pcireg_t reg; 620 621 /* Power on the controller if the BIOS didn't */ 622 pci_set_powerstate(pc, tag, PCI_PMCSR_STATE_D0); 623 624 /* 625 * Set PCI command reg. 626 * Some laptop's BIOSes (i.e. TICO) do not enable CardBus chip. 627 */ 628 reg = pci_conf_read(pc, tag, PCI_COMMAND_STATUS_REG); 629 /* I believe it is harmless. */ 630 reg |= (PCI_COMMAND_IO_ENABLE | PCI_COMMAND_MEM_ENABLE | 631 PCI_COMMAND_MASTER_ENABLE); 632 pci_conf_write(pc, tag, PCI_COMMAND_STATUS_REG, reg); 633 634 /* 635 * Set CardBus latency timer. 636 */ 637 reg = pci_conf_read(pc, tag, PCI_CB_LSCP_REG); 638 if (PCI_CB_LATENCY(reg) < 0x20) { 639 reg &= ~(PCI_CB_LATENCY_MASK << PCI_CB_LATENCY_SHIFT); 640 reg |= (0x20 << PCI_CB_LATENCY_SHIFT); 641 pci_conf_write(pc, tag, PCI_CB_LSCP_REG, reg); 642 } 643 DPRINTF(("CardBus latency timer 0x%x (%x)\n", 644 PCI_CB_LATENCY(reg), pci_conf_read(pc, tag, PCI_CB_LSCP_REG))); 645 646 /* 647 * Set PCI latency timer. 648 */ 649 reg = pci_conf_read(pc, tag, PCI_BHLC_REG); 650 if (PCI_LATTIMER(reg) < 0x10) { 651 reg &= ~(PCI_LATTIMER_MASK << PCI_LATTIMER_SHIFT); 652 reg |= (0x10 << PCI_LATTIMER_SHIFT); 653 pci_conf_write(pc, tag, PCI_BHLC_REG, reg); 654 } 655 DPRINTF(("PCI latency timer 0x%x (%x)\n", 656 PCI_LATTIMER(reg), pci_conf_read(pc, tag, PCI_BHLC_REG))); 657 658 /* Route functional interrupts to PCI. */ 659 reg = pci_conf_read(pc, tag, PCI_BCR_INTR); 660 reg |= CB_BCR_INTR_IREQ_ENABLE; /* disable PCI Intr */ 661 reg |= CB_BCR_WRITE_POST_ENABLE; /* enable write post */ 662 reg |= CB_BCR_RESET_ENABLE; /* assert reset */ 663 pci_conf_write(pc, tag, PCI_BCR_INTR, reg); 664 665 switch (sc->sc_chipset) { 666 case CB_TI113X: 667 reg = pci_conf_read(pc, tag, PCI_CBCTRL); 668 /* This bit is shared, but may read as 0 on some chips, so set 669 it explicitly on both functions. */ 670 reg |= PCI113X_CBCTRL_PCI_IRQ_ENA; 671 /* CSC intr enable */ 672 reg |= PCI113X_CBCTRL_PCI_CSC; 673 /* functional intr prohibit | prohibit ISA routing */ 674 reg &= ~(PCI113X_CBCTRL_PCI_INTR | PCI113X_CBCTRL_INT_MASK); 675 pci_conf_write(pc, tag, PCI_CBCTRL, reg); 676 break; 677 678 case CB_TI12XX: 679 /* 680 * Some TI 12xx (and [14][45]xx) based pci cards 681 * sometimes have issues with the MFUNC register not 682 * being initialized due to a bad EEPROM on board. 683 * Laptops that this matters on have this register 684 * properly initialized. 685 * 686 * The TI125X parts have a different register. 687 */ 688 reg = pci_conf_read(pc, tag, PCI12XX_MFUNC); 689 if (reg == PCI12XX_MFUNC_DEFAULT) { 690 reg &= ~PCI12XX_MFUNC_PIN0; 691 reg |= PCI12XX_MFUNC_PIN0_INTA; 692 if ((pci_conf_read(pc, tag, PCI_SYSCTRL) & 693 PCI12XX_SYSCTRL_INTRTIE) == 0) { 694 reg &= ~PCI12XX_MFUNC_PIN1; 695 reg |= PCI12XX_MFUNC_PIN1_INTB; 696 } 697 pci_conf_write(pc, tag, PCI12XX_MFUNC, reg); 698 } 699 /* FALLTHROUGH */ 700 701 case CB_TI125X: 702 /* 703 * Disable zoom video. Some machines initialize this 704 * improperly and experience has shown that this helps 705 * prevent strange behavior. 706 */ 707 pci_conf_write(pc, tag, PCI12XX_MMCTRL, 0); 708 709 reg = pci_conf_read(pc, tag, PCI_SYSCTRL); 710 reg |= PCI12XX_SYSCTRL_VCCPROT; 711 pci_conf_write(pc, tag, PCI_SYSCTRL, reg); 712 reg = pci_conf_read(pc, tag, PCI_CBCTRL); 713 reg |= PCI12XX_CBCTRL_CSC; 714 pci_conf_write(pc, tag, PCI_CBCTRL, reg); 715 break; 716 717 case CB_TOPIC95B: 718 reg = pci_conf_read(pc, tag, TOPIC_SOCKET_CTRL); 719 reg |= TOPIC_SOCKET_CTRL_SCR_IRQSEL; 720 pci_conf_write(pc, tag, TOPIC_SOCKET_CTRL, reg); 721 722 reg = pci_conf_read(pc, tag, TOPIC_SLOT_CTRL); 723 DPRINTF(("%s: topic slot ctrl reg 0x%x -> ", 724 sc->sc_dev.dv_xname, reg)); 725 reg |= (TOPIC_SLOT_CTRL_SLOTON | TOPIC_SLOT_CTRL_SLOTEN | 726 TOPIC_SLOT_CTRL_ID_LOCK | TOPIC_SLOT_CTRL_CARDBUS); 727 reg &= ~TOPIC_SLOT_CTRL_SWDETECT; 728 DPRINTF(("0x%x\n", reg)); 729 pci_conf_write(pc, tag, TOPIC_SLOT_CTRL, reg); 730 break; 731 732 case CB_TOPIC97: 733 reg = pci_conf_read(pc, tag, TOPIC_SLOT_CTRL); 734 DPRINTF(("%s: topic slot ctrl reg 0x%x -> ", 735 sc->sc_dev.dv_xname, reg)); 736 reg |= (TOPIC_SLOT_CTRL_SLOTON | TOPIC_SLOT_CTRL_SLOTEN | 737 TOPIC_SLOT_CTRL_ID_LOCK | TOPIC_SLOT_CTRL_CARDBUS); 738 reg &= ~TOPIC_SLOT_CTRL_SWDETECT; 739 reg |= TOPIC97_SLOT_CTRL_PCIINT; 740 reg &= ~(TOPIC97_SLOT_CTRL_STSIRQP | TOPIC97_SLOT_CTRL_IRQP); 741 DPRINTF(("0x%x\n", reg)); 742 pci_conf_write(pc, tag, TOPIC_SLOT_CTRL, reg); 743 744 /* make sure to assert LV card support bits */ 745 bus_space_write_1(sc->sc_base_memt, sc->sc_base_memh, 746 0x800 + 0x3e, bus_space_read_1(sc->sc_base_memt, 747 sc->sc_base_memh, 0x800 + 0x3e) | 0x03); 748 break; 749 750 case CB_OLDO2MICRO: 751 /* 752 * older bridges have problems with both read prefetch and 753 * write bursting depending on the combination of the chipset, 754 * bridge and the cardbus card. so disable them to be on the 755 * safe side. One example is O2Micro 6812 with Atheros AR5012 756 * chipsets 757 */ 758 DPRINTF(("%s: old O2Micro bridge found\n", 759 sc->sc_dev.dv_xname, reg)); 760 reg = pci_conf_read(pc, tag, O2MICRO_RESERVED1); 761 pci_conf_write(pc, tag, O2MICRO_RESERVED1, reg & 762 ~(O2MICRO_RES_READ_PREFETCH | O2MICRO_RES_WRITE_BURST)); 763 reg = pci_conf_read(pc, tag, O2MICRO_RESERVED2); 764 pci_conf_write(pc, tag, O2MICRO_RESERVED2, reg & 765 ~(O2MICRO_RES_READ_PREFETCH | O2MICRO_RES_WRITE_BURST)); 766 break; 767 } 768 769 /* Close all memory and I/O windows. */ 770 pci_conf_write(pc, tag, PCI_CB_MEMBASE0, 0xffffffff); 771 pci_conf_write(pc, tag, PCI_CB_MEMLIMIT0, 0); 772 pci_conf_write(pc, tag, PCI_CB_MEMBASE1, 0xffffffff); 773 pci_conf_write(pc, tag, PCI_CB_MEMLIMIT1, 0); 774 pci_conf_write(pc, tag, PCI_CB_IOBASE0, 0xffffffff); 775 pci_conf_write(pc, tag, PCI_CB_IOLIMIT0, 0); 776 pci_conf_write(pc, tag, PCI_CB_IOBASE1, 0xffffffff); 777 pci_conf_write(pc, tag, PCI_CB_IOLIMIT1, 0); 778 779 /* reset 16-bit pcmcia bus */ 780 bus_space_write_1(sc->sc_base_memt, sc->sc_base_memh, 781 0x800 + PCIC_INTR, 782 bus_space_read_1(sc->sc_base_memt, sc->sc_base_memh, 783 0x800 + PCIC_INTR) & ~PCIC_INTR_RESET); 784 785 /* turn off power */ 786 pccbb_power((cardbus_chipset_tag_t)sc, CARDBUS_VCC_0V | CARDBUS_VPP_0V); 787 } 788 789 790 791 792 /* 793 * void pccbb_pcmcia_attach_setup(struct pccbb_softc *sc, 794 * struct pcmciabus_attach_args *paa) 795 * 796 * This function attaches 16-bit PCcard bus. 797 */ 798 void 799 pccbb_pcmcia_attach_setup(struct pccbb_softc *sc, 800 struct pcmciabus_attach_args *paa) 801 { 802 struct pcic_handle *ph = &sc->sc_pcmcia_h; 803 rbus_tag_t rb; 804 805 /* initialize pcmcia part in pccbb_softc */ 806 ph->ph_parent = (struct device *)sc; 807 ph->sock = sc->sc_function; 808 ph->flags = 0; 809 ph->shutdown = 0; 810 ph->ih_irq = sc->sc_intrline; 811 ph->ph_bus_t = sc->sc_base_memt; 812 ph->ph_bus_h = sc->sc_base_memh; 813 ph->ph_read = pccbb_pcmcia_read; 814 ph->ph_write = pccbb_pcmcia_write; 815 sc->sc_pct = &pccbb_pcmcia_funcs; 816 817 /* 818 * We need to do a few things here: 819 * 1) Disable routing of CSC and functional interrupts to ISA IRQs by 820 * setting the IRQ numbers to 0. 821 * 2) Set bit 4 of PCIC_INTR, which is needed on some chips to enable 822 * routing of CSC interrupts (e.g. card removal) to PCI while in 823 * PCMCIA mode. We just leave this set all the time. 824 * 3) Enable card insertion/removal interrupts in case the chip also 825 * needs that while in PCMCIA mode. 826 * 4) Clear any pending CSC interrupt. 827 */ 828 Pcic_write(ph, PCIC_INTR, PCIC_INTR_ENABLE | PCIC_INTR_RESET); 829 if (sc->sc_chipset == CB_TI113X) { 830 Pcic_write(ph, PCIC_CSC_INTR, 0); 831 } else { 832 Pcic_write(ph, PCIC_CSC_INTR, PCIC_CSC_INTR_CD_ENABLE); 833 Pcic_read(ph, PCIC_CSC); 834 } 835 836 /* initialize pcmcia bus attachment */ 837 paa->paa_busname = "pcmcia"; 838 paa->pct = sc->sc_pct; 839 paa->pch = ph; 840 paa->iobase = 0; /* I don't use them */ 841 paa->iosize = 0; 842 rb = ((struct pccbb_softc *)(ph->ph_parent))->sc_rbus_iot; 843 paa->iobase = rb->rb_start + rb->rb_offset; 844 paa->iosize = rb->rb_end - rb->rb_start; 845 846 return; 847 } 848 849 #if 0 850 void 851 pccbb_pcmcia_attach_card(struct pcic_handle *ph) 852 { 853 if (ph->flags & PCIC_FLAG_CARDP) { 854 panic("pccbb_pcmcia_attach_card: already attached"); 855 } 856 857 /* call the MI attach function */ 858 pcmcia_card_attach(ph->pcmcia); 859 860 ph->flags |= PCIC_FLAG_CARDP; 861 } 862 863 void 864 pccbb_pcmcia_detach_card(struct pcic_handle *ph, int flags) 865 { 866 if (!(ph->flags & PCIC_FLAG_CARDP)) { 867 panic("pccbb_pcmcia_detach_card: already detached"); 868 } 869 870 ph->flags &= ~PCIC_FLAG_CARDP; 871 872 /* call the MI detach function */ 873 pcmcia_card_detach(ph->pcmcia, flags); 874 } 875 #endif 876 877 int 878 pccbb_checksockstat(struct pccbb_softc *sc) 879 { 880 u_int32_t sockstate; 881 882 sockstate = bus_space_read_4(sc->sc_base_memt, sc->sc_base_memh, 883 CB_SOCKET_STAT); 884 885 if ((sockstate & CB_SOCKET_STAT_CD) != 0) { 886 /* A card should be removed. */ 887 if (sc->sc_flags & CBB_CARDEXIST) { 888 DPRINTF(("%s: card removed, 0x%08x\n", 889 sc->sc_dev.dv_xname, sockstate)); 890 sc->sc_flags &= ~CBB_CARDEXIST; 891 if (sc->sc_csc->sc_status & CARDSLOT_STATUS_CARD_16) { 892 #if 0 893 struct pcic_handle *ph = 894 &sc->sc_pcmcia_h; 895 896 pcmcia_card_deactivate(ph->pcmcia); 897 pccbb_pcmcia_socket_disable(ph); 898 pccbb_pcmcia_detach_card(ph, 899 DETACH_FORCE); 900 #endif 901 cardslot_event_throw(sc->sc_csc, 902 CARDSLOT_EVENT_REMOVAL_16); 903 } else if (sc->sc_csc->sc_status & 904 CARDSLOT_STATUS_CARD_CB) { 905 /* Cardbus intr removed */ 906 cardslot_event_throw(sc->sc_csc, 907 CARDSLOT_EVENT_REMOVAL_CB); 908 } 909 } 910 return (1); 911 } else if ((sockstate & CB_SOCKET_STAT_CD) == 0 && 912 (sc->sc_flags & CBB_CARDEXIST) == 0) { 913 timeout_add_msec(&sc->sc_ins_tmo, 100); 914 sc->sc_flags |= CBB_INSERTING; 915 return (1); 916 } 917 return (0); 918 } 919 920 /* 921 * int pccbbintr(arg) 922 * void *arg; 923 * This routine handles the interrupt from Yenta PCI-CardBus bridge 924 * itself. 925 */ 926 int 927 pccbbintr(void *arg) 928 { 929 struct pccbb_softc *sc = (struct pccbb_softc *)arg; 930 u_int32_t sockevent; 931 struct pcic_handle *ph = &sc->sc_pcmcia_h; 932 933 if (!sc->sc_ints_on) 934 return 0; 935 936 sockevent = bus_space_read_4(sc->sc_base_memt, sc->sc_base_memh, 937 CB_SOCKET_EVENT); 938 bus_space_write_4(sc->sc_base_memt, sc->sc_base_memh, 939 CB_SOCKET_EVENT, sockevent); 940 Pcic_read(ph, PCIC_CSC); 941 942 if (sockevent & CB_SOCKET_EVENT_CD) { 943 if (pccbb_checksockstat(sc)) 944 return (1); 945 } 946 947 if (sc->sc_pil_intr_enable) 948 return pccbbintr_function(sc); 949 return (0); 950 } 951 952 /* 953 * int pccbbintr_function(struct pccbb_softc *sc) 954 * 955 * This function calls each interrupt handler registered at the 956 * bridge. The interrupt handlers are called in registered order. 957 */ 958 int 959 pccbbintr_function(struct pccbb_softc *sc) 960 { 961 int retval = 0, val; 962 struct pccbb_intrhand_list *pil; 963 int s, splchanged; 964 965 for (pil = sc->sc_pil; pil != NULL; pil = pil->pil_next) { 966 /* 967 * XXX priority change. gross. I use if-else 968 * sentences instead of switch-case sentences in order 969 * to avoid duplicate case value error. More than one 970 * IPL_XXX may use the same value. It depends on the 971 * implementation. 972 */ 973 splchanged = 1; 974 #if 0 975 if (pil->pil_level == IPL_SERIAL) { 976 s = splserial(); 977 } else if (pil->pil_level == IPL_HIGH) { 978 #endif 979 if (pil->pil_level == IPL_HIGH) { 980 s = splhigh(); 981 } else if (pil->pil_level == IPL_CLOCK) { 982 s = splclock(); 983 } else if (pil->pil_level == IPL_AUDIO) { 984 s = splaudio(); 985 } else if (pil->pil_level == IPL_VM) { 986 s = splvm(); 987 } else if (pil->pil_level == IPL_TTY) { 988 s = spltty(); 989 #if 0 990 } else if (pil->pil_level == IPL_SOFTSERIAL) { 991 s = splsoftserial(); 992 #endif 993 } else if (pil->pil_level == IPL_NET) { 994 s = splnet(); 995 } else { 996 splchanged = 0; 997 /* XXX: ih lower than IPL_BIO runs w/ IPL_BIO. */ 998 } 999 1000 val = (*pil->pil_func)(pil->pil_arg); 1001 if (val != 0) 1002 pil->pil_count.ec_count++; 1003 1004 if (splchanged != 0) { 1005 splx(s); 1006 } 1007 1008 if (retval == 0 || val != 0) 1009 retval = val; 1010 } 1011 1012 return retval; 1013 } 1014 1015 void 1016 pci113x_insert(void *arg) 1017 { 1018 struct pccbb_softc *sc = (struct pccbb_softc *)arg; 1019 u_int32_t sockevent, sockstate; 1020 1021 sockevent = bus_space_read_4(sc->sc_base_memt, sc->sc_base_memh, 1022 CB_SOCKET_EVENT); 1023 sockstate = bus_space_read_4(sc->sc_base_memt, sc->sc_base_memh, 1024 CB_SOCKET_STAT); 1025 1026 if (0 == (sockstate & CB_SOCKET_STAT_CD)) { /* card exist */ 1027 DPRINTF(("%s: 0x%08x", sc->sc_dev.dv_xname, sockevent)); 1028 DPRINTF((" card inserted, 0x%08x\n", sockstate)); 1029 sc->sc_flags |= CBB_CARDEXIST; 1030 /* call pccard interrupt handler here */ 1031 if (sockstate & CB_SOCKET_STAT_16BIT) { 1032 /* 16-bit card found */ 1033 /* pccbb_pcmcia_attach_card(&sc->sc_pcmcia_h); */ 1034 cardslot_event_throw(sc->sc_csc, 1035 CARDSLOT_EVENT_INSERTION_16); 1036 } else if (sockstate & CB_SOCKET_STAT_CB) { 1037 /* cardbus card found */ 1038 /* cardbus_attach_card(sc->sc_csc); */ 1039 cardslot_event_throw(sc->sc_csc, 1040 CARDSLOT_EVENT_INSERTION_CB); 1041 } else { 1042 /* who are you? */ 1043 } 1044 } else { 1045 timeout_add_msec(&sc->sc_ins_tmo, 100); 1046 } 1047 } 1048 1049 #define PCCBB_PCMCIA_OFFSET 0x800 1050 u_int8_t 1051 pccbb_pcmcia_read(struct pcic_handle *ph, int reg) 1052 { 1053 bus_space_barrier(ph->ph_bus_t, ph->ph_bus_h, 1054 PCCBB_PCMCIA_OFFSET + reg, 1, BUS_SPACE_BARRIER_READ); 1055 1056 return bus_space_read_1(ph->ph_bus_t, ph->ph_bus_h, 1057 PCCBB_PCMCIA_OFFSET + reg); 1058 } 1059 1060 void 1061 pccbb_pcmcia_write(struct pcic_handle *ph, int reg, int val) 1062 { 1063 bus_space_barrier(ph->ph_bus_t, ph->ph_bus_h, 1064 PCCBB_PCMCIA_OFFSET + reg, 1, BUS_SPACE_BARRIER_WRITE); 1065 1066 bus_space_write_1(ph->ph_bus_t, ph->ph_bus_h, PCCBB_PCMCIA_OFFSET + reg, 1067 val); 1068 } 1069 1070 /* 1071 * int pccbb_ctrl(cardbus_chipset_tag_t, int) 1072 */ 1073 int 1074 pccbb_ctrl(cardbus_chipset_tag_t ct, int command) 1075 { 1076 struct pccbb_softc *sc = (struct pccbb_softc *)ct; 1077 1078 switch (command) { 1079 case CARDBUS_CD: 1080 if (2 == pccbb_detect_card(sc)) { 1081 int retval = 0; 1082 int status = cb_detect_voltage(sc); 1083 if (PCCARD_VCC_5V & status) { 1084 retval |= CARDBUS_5V_CARD; 1085 } 1086 if (PCCARD_VCC_3V & status) { 1087 retval |= CARDBUS_3V_CARD; 1088 } 1089 if (PCCARD_VCC_XV & status) { 1090 retval |= CARDBUS_XV_CARD; 1091 } 1092 if (PCCARD_VCC_YV & status) { 1093 retval |= CARDBUS_YV_CARD; 1094 } 1095 return retval; 1096 } else { 1097 return 0; 1098 } 1099 break; 1100 case CARDBUS_RESET: 1101 return cb_reset(sc); 1102 break; 1103 case CARDBUS_IO_ENABLE: /* fallthrough */ 1104 case CARDBUS_IO_DISABLE: /* fallthrough */ 1105 case CARDBUS_MEM_ENABLE: /* fallthrough */ 1106 case CARDBUS_MEM_DISABLE: /* fallthrough */ 1107 case CARDBUS_BM_ENABLE: /* fallthrough */ 1108 case CARDBUS_BM_DISABLE: /* fallthrough */ 1109 return pccbb_cardenable(sc, command); 1110 break; 1111 } 1112 1113 return 0; 1114 } 1115 1116 /* 1117 * int pccbb_power(cardbus_chipset_tag_t, int) 1118 * This function returns true when it succeeds and returns false when 1119 * it fails. 1120 */ 1121 int 1122 pccbb_power(cardbus_chipset_tag_t ct, int command) 1123 { 1124 struct pccbb_softc *sc = (struct pccbb_softc *)ct; 1125 1126 u_int32_t status, sock_ctrl; 1127 bus_space_tag_t memt = sc->sc_base_memt; 1128 bus_space_handle_t memh = sc->sc_base_memh; 1129 1130 DPRINTF(("pccbb_power: %s and %s [%x]\n", 1131 (command & CARDBUS_VCCMASK) == CARDBUS_VCC_UC ? "CARDBUS_VCC_UC" : 1132 (command & CARDBUS_VCCMASK) == CARDBUS_VCC_5V ? "CARDBUS_VCC_5V" : 1133 (command & CARDBUS_VCCMASK) == CARDBUS_VCC_3V ? "CARDBUS_VCC_3V" : 1134 (command & CARDBUS_VCCMASK) == CARDBUS_VCC_XV ? "CARDBUS_VCC_XV" : 1135 (command & CARDBUS_VCCMASK) == CARDBUS_VCC_YV ? "CARDBUS_VCC_YV" : 1136 (command & CARDBUS_VCCMASK) == CARDBUS_VCC_0V ? "CARDBUS_VCC_0V" : 1137 "UNKNOWN", 1138 (command & CARDBUS_VPPMASK) == CARDBUS_VPP_UC ? "CARDBUS_VPP_UC" : 1139 (command & CARDBUS_VPPMASK) == CARDBUS_VPP_12V ? "CARDBUS_VPP_12V" : 1140 (command & CARDBUS_VPPMASK) == CARDBUS_VPP_VCC ? "CARDBUS_VPP_VCC" : 1141 (command & CARDBUS_VPPMASK) == CARDBUS_VPP_0V ? "CARDBUS_VPP_0V" : 1142 "UNKNOWN", command)); 1143 1144 status = bus_space_read_4(memt, memh, CB_SOCKET_STAT); 1145 sock_ctrl = bus_space_read_4(memt, memh, CB_SOCKET_CTRL); 1146 1147 switch (command & CARDBUS_VCCMASK) { 1148 case CARDBUS_VCC_UC: 1149 break; 1150 case CARDBUS_VCC_5V: 1151 if (CB_SOCKET_STAT_5VCARD & status) { /* check 5 V card */ 1152 sock_ctrl &= ~CB_SOCKET_CTRL_VCCMASK; 1153 sock_ctrl |= CB_SOCKET_CTRL_VCC_5V; 1154 } else { 1155 printf("%s: BAD voltage request: no 5 V card\n", 1156 sc->sc_dev.dv_xname); 1157 } 1158 break; 1159 case CARDBUS_VCC_3V: 1160 if (CB_SOCKET_STAT_3VCARD & status) { 1161 sock_ctrl &= ~CB_SOCKET_CTRL_VCCMASK; 1162 sock_ctrl |= CB_SOCKET_CTRL_VCC_3V; 1163 } else { 1164 printf("%s: BAD voltage request: no 3.3 V card\n", 1165 sc->sc_dev.dv_xname); 1166 } 1167 break; 1168 case CARDBUS_VCC_0V: 1169 sock_ctrl &= ~CB_SOCKET_CTRL_VCCMASK; 1170 break; 1171 default: 1172 return 0; /* power NEVER changed */ 1173 break; 1174 } 1175 1176 switch (command & CARDBUS_VPPMASK) { 1177 case CARDBUS_VPP_UC: 1178 break; 1179 case CARDBUS_VPP_0V: 1180 sock_ctrl &= ~CB_SOCKET_CTRL_VPPMASK; 1181 break; 1182 case CARDBUS_VPP_VCC: 1183 sock_ctrl &= ~CB_SOCKET_CTRL_VPPMASK; 1184 sock_ctrl |= ((sock_ctrl >> 4) & 0x07); 1185 break; 1186 case CARDBUS_VPP_12V: 1187 sock_ctrl &= ~CB_SOCKET_CTRL_VPPMASK; 1188 sock_ctrl |= CB_SOCKET_CTRL_VPP_12V; 1189 break; 1190 } 1191 1192 #if 0 1193 DPRINTF(("sock_ctrl: %x\n", sock_ctrl)); 1194 #endif 1195 bus_space_write_4(memt, memh, CB_SOCKET_CTRL, sock_ctrl); 1196 status = bus_space_read_4(memt, memh, CB_SOCKET_STAT); 1197 1198 if (status & CB_SOCKET_STAT_BADVCC) { /* bad Vcc request */ 1199 printf 1200 ("%s: bad Vcc request. sock_ctrl 0x%x, sock_status 0x%x\n", 1201 sc->sc_dev.dv_xname, sock_ctrl, status); 1202 DPRINTF(("pccbb_power: %s and %s [%x]\n", 1203 (command & CARDBUS_VCCMASK) == 1204 CARDBUS_VCC_UC ? "CARDBUS_VCC_UC" : (command & 1205 CARDBUS_VCCMASK) == 1206 CARDBUS_VCC_5V ? "CARDBUS_VCC_5V" : (command & 1207 CARDBUS_VCCMASK) == 1208 CARDBUS_VCC_3V ? "CARDBUS_VCC_3V" : (command & 1209 CARDBUS_VCCMASK) == 1210 CARDBUS_VCC_XV ? "CARDBUS_VCC_XV" : (command & 1211 CARDBUS_VCCMASK) == 1212 CARDBUS_VCC_YV ? "CARDBUS_VCC_YV" : (command & 1213 CARDBUS_VCCMASK) == 1214 CARDBUS_VCC_0V ? "CARDBUS_VCC_0V" : "UNKNOWN", 1215 (command & CARDBUS_VPPMASK) == 1216 CARDBUS_VPP_UC ? "CARDBUS_VPP_UC" : (command & 1217 CARDBUS_VPPMASK) == 1218 CARDBUS_VPP_12V ? "CARDBUS_VPP_12V" : (command & 1219 CARDBUS_VPPMASK) == 1220 CARDBUS_VPP_VCC ? "CARDBUS_VPP_VCC" : (command & 1221 CARDBUS_VPPMASK) == 1222 CARDBUS_VPP_0V ? "CARDBUS_VPP_0V" : "UNKNOWN", command)); 1223 #if 0 1224 if (command == (CARDBUS_VCC_0V | CARDBUS_VPP_0V)) { 1225 u_int32_t force = 1226 bus_space_read_4(memt, memh, CB_SOCKET_FORCE); 1227 /* Reset Bad Vcc request */ 1228 force &= ~CB_SOCKET_FORCE_BADVCC; 1229 bus_space_write_4(memt, memh, CB_SOCKET_FORCE, force); 1230 printf("new status 0x%x\n", bus_space_read_4(memt, memh, 1231 CB_SOCKET_STAT)); 1232 return 1; 1233 } 1234 #endif 1235 return 0; 1236 } 1237 1238 /* 1239 * XXX delay 300 ms: though the standard defines that the Vcc set-up 1240 * time is 20 ms, some PC-Card bridge requires longer duration. 1241 */ 1242 delay(300 * 1000); 1243 1244 return 1; /* power changed correctly */ 1245 } 1246 1247 #if defined CB_PCMCIA_POLL 1248 struct cb_poll_str { 1249 void *arg; 1250 int (*func)(void *); 1251 int level; 1252 pccard_chipset_tag_t ct; 1253 int count; 1254 }; 1255 1256 static struct cb_poll_str cb_poll[10]; 1257 static int cb_poll_n = 0; 1258 static struct timeout cb_poll_timeout; 1259 1260 void cb_pcmcia_poll(void *arg); 1261 1262 void 1263 cb_pcmcia_poll(void *arg) 1264 { 1265 struct cb_poll_str *poll = arg; 1266 struct cbb_pcmcia_softc *psc = (void *)poll->ct->v; 1267 struct pccbb_softc *sc = psc->cpc_parent; 1268 int s; 1269 u_int32_t spsr; /* socket present-state reg */ 1270 1271 timeout_set(&cb_poll_timeout, cb_pcmcia_poll, arg); 1272 timeout_add(&cb_poll_timeout, hz / 10); 1273 switch (poll->level) { 1274 case IPL_NET: 1275 s = splnet(); 1276 break; 1277 case IPL_BIO: 1278 s = splbio(); 1279 break; 1280 case IPL_TTY: /* fallthrough */ 1281 default: 1282 s = spltty(); 1283 break; 1284 } 1285 1286 spsr = 1287 bus_space_read_4(sc->sc_base_memt, sc->sc_base_memh, 1288 CB_SOCKET_STAT); 1289 1290 #if defined CB_PCMCIA_POLL_ONLY && defined LEVEL2 1291 if (!(spsr & 0x40)) { /* CINT low */ 1292 #else 1293 if (1) { 1294 #endif 1295 if ((*poll->func) (poll->arg) == 1) { 1296 ++poll->count; 1297 printf("intr: reported from poller, 0x%x\n", spsr); 1298 #if defined LEVEL2 1299 } else { 1300 printf("intr: miss! 0x%x\n", spsr); 1301 #endif 1302 } 1303 } 1304 splx(s); 1305 } 1306 #endif /* defined CB_PCMCIA_POLL */ 1307 1308 /* 1309 * int pccbb_detect_card(struct pccbb_softc *sc) 1310 * return value: 0 if no card exists. 1311 * 1 if 16-bit card exists. 1312 * 2 if cardbus card exists. 1313 */ 1314 int 1315 pccbb_detect_card(struct pccbb_softc *sc) 1316 { 1317 bus_space_handle_t base_memh = sc->sc_base_memh; 1318 bus_space_tag_t base_memt = sc->sc_base_memt; 1319 u_int32_t sockstat = 1320 bus_space_read_4(base_memt, base_memh, CB_SOCKET_STAT); 1321 int retval = 0; 1322 1323 /* 1324 * The SCM Microsystems TI1225-based PCI-CardBus dock card that 1325 * ships with some Lucent WaveLAN cards has only one physical slot 1326 * but OpenBSD probes two. The phantom card in the second slot can 1327 * be ignored by punting on unsupported voltages. 1328 */ 1329 if (sockstat & CB_SOCKET_STAT_XVCARD) 1330 return 0; 1331 1332 /* CD1 and CD2 asserted */ 1333 if (0x00 == (sockstat & CB_SOCKET_STAT_CD)) { 1334 /* card must be present */ 1335 if (!(CB_SOCKET_STAT_NOTCARD & sockstat)) { 1336 /* NOTACARD DEASSERTED */ 1337 if (CB_SOCKET_STAT_CB & sockstat) { 1338 /* CardBus mode */ 1339 retval = 2; 1340 } else if (CB_SOCKET_STAT_16BIT & sockstat) { 1341 /* 16-bit mode */ 1342 retval = 1; 1343 } 1344 } 1345 } 1346 return retval; 1347 } 1348 1349 /* 1350 * int cb_reset(struct pccbb_softc *sc) 1351 * This function resets CardBus card. 1352 */ 1353 int 1354 cb_reset(struct pccbb_softc *sc) 1355 { 1356 /* 1357 * Reset Assert at least 20 ms 1358 * Some machines request longer duration. 1359 */ 1360 int reset_duration = (sc->sc_chipset == CB_RX5C47X ? 400 : 50); 1361 u_int32_t bcr = pci_conf_read(sc->sc_pc, sc->sc_tag, PCI_BCR_INTR); 1362 1363 /* Reset bit Assert (bit 6 at 0x3E) */ 1364 bcr |= CB_BCR_RESET_ENABLE; 1365 pci_conf_write(sc->sc_pc, sc->sc_tag, PCI_BCR_INTR, bcr); 1366 delay_ms(reset_duration, sc); 1367 1368 if (CBB_CARDEXIST & sc->sc_flags) { /* A card exists. Reset it! */ 1369 /* Reset bit Deassert (bit 6 at 0x3E) */ 1370 bcr &= ~CB_BCR_RESET_ENABLE; 1371 pci_conf_write(sc->sc_pc, sc->sc_tag, PCI_BCR_INTR, bcr); 1372 delay_ms(reset_duration, sc); 1373 } 1374 /* No card found on the slot. Keep Reset. */ 1375 return 1; 1376 } 1377 1378 /* 1379 * int cb_detect_voltage(struct pccbb_softc *sc) 1380 * This function detect card Voltage. 1381 */ 1382 int 1383 cb_detect_voltage(struct pccbb_softc *sc) 1384 { 1385 u_int32_t psr; /* socket present-state reg */ 1386 bus_space_tag_t iot = sc->sc_base_memt; 1387 bus_space_handle_t ioh = sc->sc_base_memh; 1388 int vol = PCCARD_VCC_UKN; /* set 0 */ 1389 1390 psr = bus_space_read_4(iot, ioh, CB_SOCKET_STAT); 1391 1392 if (0x400u & psr) { 1393 vol |= PCCARD_VCC_5V; 1394 } 1395 if (0x800u & psr) { 1396 vol |= PCCARD_VCC_3V; 1397 } 1398 1399 return vol; 1400 } 1401 1402 int 1403 cbbprint(void *aux, const char *pcic) 1404 { 1405 /* 1406 struct cbslot_attach_args *cba = aux; 1407 1408 if (cba->cba_slot >= 0) { 1409 printf(" slot %d", cba->cba_slot); 1410 } 1411 */ 1412 return UNCONF; 1413 } 1414 1415 /* 1416 * int pccbb_cardenable(struct pccbb_softc *sc, int function) 1417 * This function enables and disables the card 1418 */ 1419 int 1420 pccbb_cardenable(struct pccbb_softc *sc, int function) 1421 { 1422 u_int32_t command = 1423 pci_conf_read(sc->sc_pc, sc->sc_tag, PCI_COMMAND_STATUS_REG); 1424 1425 DPRINTF(("pccbb_cardenable:")); 1426 switch (function) { 1427 case CARDBUS_IO_ENABLE: 1428 command |= PCI_COMMAND_IO_ENABLE; 1429 break; 1430 case CARDBUS_IO_DISABLE: 1431 command &= ~PCI_COMMAND_IO_ENABLE; 1432 break; 1433 case CARDBUS_MEM_ENABLE: 1434 command |= PCI_COMMAND_MEM_ENABLE; 1435 break; 1436 case CARDBUS_MEM_DISABLE: 1437 command &= ~PCI_COMMAND_MEM_ENABLE; 1438 break; 1439 case CARDBUS_BM_ENABLE: 1440 command |= PCI_COMMAND_MASTER_ENABLE; 1441 break; 1442 case CARDBUS_BM_DISABLE: 1443 command &= ~PCI_COMMAND_MASTER_ENABLE; 1444 break; 1445 default: 1446 return 0; 1447 } 1448 1449 pci_conf_write(sc->sc_pc, sc->sc_tag, PCI_COMMAND_STATUS_REG, command); 1450 DPRINTF((" command reg 0x%x\n", command)); 1451 return 1; 1452 } 1453 1454 /* 1455 * void *pccbb_cb_intr_establish(cardbus_chipset_tag_t ct, 1456 * int irq, 1457 * int level, 1458 * int (* func)(void *), 1459 * void *arg, 1460 * const char *name) 1461 * 1462 * This function registers an interrupt handler at the bridge, in 1463 * order not to call the interrupt handlers of child devices when 1464 * a card-deletion interrupt occurs. 1465 * 1466 * The arguments irq is not used because pccbb selects intr vector. 1467 */ 1468 void * 1469 pccbb_cb_intr_establish(cardbus_chipset_tag_t ct, int irq, int level, 1470 int (*func)(void *), void *arg, const char *name) 1471 { 1472 struct pccbb_softc *sc = (struct pccbb_softc *)ct; 1473 1474 return pccbb_intr_establish(sc, irq, level, func, arg, name); 1475 } 1476 1477 1478 /* 1479 * void *pccbb_cb_intr_disestablish(cardbus_chipset_tag_t ct, 1480 * void *ih) 1481 * 1482 * This function removes an interrupt handler pointed by ih. 1483 */ 1484 void 1485 pccbb_cb_intr_disestablish(cardbus_chipset_tag_t ct, void *ih) 1486 { 1487 struct pccbb_softc *sc = (struct pccbb_softc *)ct; 1488 1489 pccbb_intr_disestablish(sc, ih); 1490 } 1491 1492 1493 /* 1494 * void *pccbb_intr_establish(struct pccbb_softc *sc, 1495 * int irq, 1496 * int level, 1497 * int (* func)(void *), 1498 * void *arg, 1499 * const char *name) 1500 * 1501 * This function registers an interrupt handler at the bridge, in 1502 * order not to call the interrupt handlers of child devices when 1503 * a card-deletion interrupt occurs. 1504 * 1505 * The arguments irq and level are not used. 1506 */ 1507 void * 1508 pccbb_intr_establish(struct pccbb_softc *sc, int irq, int level, 1509 int (*func)(void *), void *arg, const char *name) 1510 { 1511 struct pccbb_intrhand_list *pil, *newpil; 1512 pcireg_t reg; 1513 1514 DPRINTF(("pccbb_intr_establish start. %p\n", sc->sc_pil)); 1515 1516 if (sc->sc_pil == NULL) { 1517 /* initialize bridge intr routing */ 1518 reg = pci_conf_read(sc->sc_pc, sc->sc_tag, PCI_BCR_INTR); 1519 reg &= ~CB_BCR_INTR_IREQ_ENABLE; 1520 pci_conf_write(sc->sc_pc, sc->sc_tag, PCI_BCR_INTR, reg); 1521 1522 switch (sc->sc_chipset) { 1523 case CB_TI113X: 1524 reg = pci_conf_read(sc->sc_pc, sc->sc_tag, PCI_CBCTRL); 1525 /* functional intr enabled */ 1526 reg |= PCI113X_CBCTRL_PCI_INTR; 1527 pci_conf_write(sc->sc_pc, sc->sc_tag, PCI_CBCTRL, reg); 1528 break; 1529 default: 1530 break; 1531 } 1532 } 1533 1534 /* 1535 * Allocate a room for interrupt handler structure. 1536 */ 1537 newpil = (struct pccbb_intrhand_list *) 1538 malloc(sizeof(struct pccbb_intrhand_list), M_DEVBUF, M_WAITOK); 1539 1540 newpil->pil_func = func; 1541 newpil->pil_arg = arg; 1542 newpil->pil_level = level; 1543 evcount_attach(&newpil->pil_count, name, &sc->sc_intrline); 1544 newpil->pil_next = NULL; 1545 1546 if (sc->sc_pil == NULL) { 1547 sc->sc_pil = newpil; 1548 } else { 1549 for (pil = sc->sc_pil; pil->pil_next != NULL; 1550 pil = pil->pil_next); 1551 pil->pil_next = newpil; 1552 } 1553 1554 DPRINTF(("pccbb_intr_establish add pil. %p\n", sc->sc_pil)); 1555 1556 return newpil; 1557 } 1558 1559 /* 1560 * void *pccbb_intr_disestablish(struct pccbb_softc *sc, 1561 * void *ih) 1562 * 1563 * This function removes an interrupt handler pointed by ih. 1564 */ 1565 void 1566 pccbb_intr_disestablish(struct pccbb_softc *sc, void *ih) 1567 { 1568 struct pccbb_intrhand_list *pil, **pil_prev; 1569 pcireg_t reg; 1570 1571 DPRINTF(("pccbb_intr_disestablish start. %p\n", sc->sc_pil)); 1572 1573 pil_prev = &sc->sc_pil; 1574 1575 for (pil = sc->sc_pil; pil != NULL; pil = pil->pil_next) { 1576 if (pil == ih) { 1577 evcount_detach(&pil->pil_count); 1578 *pil_prev = pil->pil_next; 1579 free(pil, M_DEVBUF, sizeof *pil); 1580 DPRINTF(("pccbb_intr_disestablish frees one pil\n")); 1581 break; 1582 } 1583 pil_prev = &pil->pil_next; 1584 } 1585 1586 if (sc->sc_pil == NULL) { 1587 /* No interrupt handlers */ 1588 1589 DPRINTF(("pccbb_intr_disestablish: no interrupt handler\n")); 1590 1591 /* stop routing PCI intr */ 1592 reg = pci_conf_read(sc->sc_pc, sc->sc_tag, PCI_BCR_INTR); 1593 reg |= CB_BCR_INTR_IREQ_ENABLE; 1594 pci_conf_write(sc->sc_pc, sc->sc_tag, PCI_BCR_INTR, reg); 1595 1596 switch (sc->sc_chipset) { 1597 case CB_TI113X: 1598 reg = pci_conf_read(sc->sc_pc, sc->sc_tag, PCI_CBCTRL); 1599 /* functional intr disabled */ 1600 reg &= ~PCI113X_CBCTRL_PCI_INTR; 1601 pci_conf_write(sc->sc_pc, sc->sc_tag, PCI_CBCTRL, reg); 1602 break; 1603 default: 1604 break; 1605 } 1606 } 1607 } 1608 1609 #if defined SHOW_REGS 1610 void 1611 cb_show_regs(pci_chipset_tag_t pc, pcitag_t tag, bus_space_tag_t memt, 1612 bus_space_handle_t memh) 1613 { 1614 int i; 1615 printf("PCI config regs:"); 1616 for (i = 0; i < 0x50; i += 4) { 1617 if (i % 16 == 0) { 1618 printf("\n 0x%02x:", i); 1619 } 1620 printf(" %08x", pci_conf_read(pc, tag, i)); 1621 } 1622 for (i = 0x80; i < 0xb0; i += 4) { 1623 if (i % 16 == 0) { 1624 printf("\n 0x%02x:", i); 1625 } 1626 printf(" %08x", pci_conf_read(pc, tag, i)); 1627 } 1628 1629 if (memh == 0) { 1630 printf("\n"); 1631 return; 1632 } 1633 1634 printf("\nsocket regs:"); 1635 for (i = 0; i <= 0x10; i += 0x04) { 1636 printf(" %08x", bus_space_read_4(memt, memh, i)); 1637 } 1638 printf("\nExCA regs:"); 1639 for (i = 0; i < 0x08; ++i) { 1640 printf(" %02x", bus_space_read_1(memt, memh, 0x800 + i)); 1641 } 1642 printf("\n"); 1643 return; 1644 } 1645 #endif 1646 1647 /* 1648 * int pccbb_pcmcia_io_alloc(pcmcia_chipset_handle_t pch, 1649 * bus_addr_t start, bus_size_t size, 1650 * bus_size_t align, 1651 * struct pcmcia_io_handle *pcihp 1652 * 1653 * This function only allocates I/O region for pccard. This function 1654 * never maps the allocated region to pccard I/O area. 1655 * 1656 * XXX: The interface of this function is not very good, I believe. 1657 */ 1658 int 1659 pccbb_pcmcia_io_alloc(pcmcia_chipset_handle_t pch, bus_addr_t start, 1660 bus_size_t size, bus_size_t align, struct pcmcia_io_handle *pcihp) 1661 { 1662 struct pcic_handle *ph = (struct pcic_handle *)pch; 1663 bus_addr_t ioaddr; 1664 int flags = 0; 1665 bus_space_tag_t iot; 1666 bus_space_handle_t ioh; 1667 bus_addr_t mask; 1668 rbus_tag_t rb; 1669 1670 if (align == 0) { 1671 align = size; /* XXX: funny??? */ 1672 } 1673 1674 if (start != 0) { 1675 /* XXX: assume all card decode lower 10 bits by its hardware */ 1676 mask = 0x3ff; 1677 /* enforce to use only masked address */ 1678 start &= mask; 1679 } else { 1680 /* 1681 * calculate mask: 1682 * 1. get the most significant bit of size (call it msb). 1683 * 2. compare msb with the value of size. 1684 * 3. if size is larger, shift msb left once. 1685 * 4. obtain mask value to decrement msb. 1686 */ 1687 bus_size_t size_tmp = size; 1688 int shifts = 0; 1689 1690 while (size_tmp) { 1691 ++shifts; 1692 size_tmp >>= 1; 1693 } 1694 mask = (1 << shifts); 1695 if (mask < size) { 1696 mask <<= 1; 1697 } 1698 mask--; 1699 } 1700 1701 /* 1702 * Allocate some arbitrary I/O space. 1703 */ 1704 1705 iot = ((struct pccbb_softc *)(ph->ph_parent))->sc_iot; 1706 1707 rb = ((struct pccbb_softc *)(ph->ph_parent))->sc_rbus_iot; 1708 if (rbus_space_alloc(rb, start, size, mask, align, 0, &ioaddr, &ioh)) { 1709 return 1; 1710 } 1711 1712 pcihp->iot = iot; 1713 pcihp->ioh = ioh; 1714 pcihp->addr = ioaddr; 1715 pcihp->size = size; 1716 pcihp->flags = flags; 1717 1718 return 0; 1719 } 1720 1721 /* 1722 * int pccbb_pcmcia_io_free(pcmcia_chipset_handle_t pch, 1723 * struct pcmcia_io_handle *pcihp) 1724 * 1725 * This function only frees I/O region for pccard. 1726 * 1727 * XXX: The interface of this function is not very good, I believe. 1728 */ 1729 void 1730 pccbb_pcmcia_io_free(pcmcia_chipset_handle_t pch, 1731 struct pcmcia_io_handle *pcihp) 1732 { 1733 bus_space_handle_t ioh = pcihp->ioh; 1734 bus_size_t size = pcihp->size; 1735 1736 struct pccbb_softc *sc = 1737 (struct pccbb_softc *)((struct pcic_handle *)pch)->ph_parent; 1738 rbus_tag_t rb = sc->sc_rbus_iot; 1739 1740 rbus_space_free(rb, ioh, size, NULL); 1741 } 1742 1743 /* 1744 * int pccbb_pcmcia_io_map(pcmcia_chipset_handle_t pch, int width, 1745 * bus_addr_t offset, bus_size_t size, 1746 * struct pcmcia_io_handle *pcihp, 1747 * int *windowp) 1748 * 1749 * This function maps the allocated I/O region to pccard. This function 1750 * never allocates any I/O region for pccard I/O area. I don't 1751 * understand why the original authors of pcmciabus separated alloc and 1752 * map. I believe the two must be unite. 1753 * 1754 * XXX: no wait timing control? 1755 */ 1756 int 1757 pccbb_pcmcia_io_map(pcmcia_chipset_handle_t pch, int width, bus_addr_t offset, 1758 bus_size_t size, struct pcmcia_io_handle *pcihp, int *windowp) 1759 { 1760 struct pcic_handle *ph = (struct pcic_handle *)pch; 1761 bus_addr_t ioaddr = pcihp->addr + offset; 1762 int i, win; 1763 #if defined CBB_DEBUG 1764 static char *width_names[] = { "dynamic", "io8", "io16" }; 1765 #endif 1766 1767 /* Sanity check I/O handle. */ 1768 1769 if (((struct pccbb_softc *)ph->ph_parent)->sc_iot != pcihp->iot) { 1770 panic("pccbb_pcmcia_io_map iot is bogus"); 1771 } 1772 1773 /* XXX Sanity check offset/size. */ 1774 1775 win = -1; 1776 for (i = 0; i < PCIC_IO_WINS; i++) { 1777 if ((ph->ioalloc & (1 << i)) == 0) { 1778 win = i; 1779 ph->ioalloc |= (1 << i); 1780 break; 1781 } 1782 } 1783 1784 if (win == -1) { 1785 return 1; 1786 } 1787 1788 *windowp = win; 1789 1790 /* XXX this is pretty gross */ 1791 1792 DPRINTF(("pccbb_pcmcia_io_map window %d %s port %lx+%lx\n", 1793 win, width_names[width], (u_long) ioaddr, (u_long) size)); 1794 1795 /* XXX wtf is this doing here? */ 1796 1797 #if 0 1798 printf(" port 0x%lx", (u_long) ioaddr); 1799 if (size > 1) { 1800 printf("-0x%lx", (u_long) ioaddr + (u_long) size - 1); 1801 } 1802 #endif 1803 1804 ph->io[win].addr = ioaddr; 1805 ph->io[win].size = size; 1806 ph->io[win].width = width; 1807 1808 /* actual dirty register-value changing in the function below. */ 1809 pccbb_pcmcia_do_io_map(ph, win); 1810 1811 return 0; 1812 } 1813 1814 /* 1815 * void pccbb_pcmcia_do_io_map(struct pcic_handle *h, int win) 1816 * 1817 * This function changes register-value to map I/O region for pccard. 1818 */ 1819 void 1820 pccbb_pcmcia_do_io_map(struct pcic_handle *ph, int win) 1821 { 1822 static u_int8_t pcic_iowidth[3] = { 1823 PCIC_IOCTL_IO0_IOCS16SRC_CARD, 1824 PCIC_IOCTL_IO0_IOCS16SRC_DATASIZE | 1825 PCIC_IOCTL_IO0_DATASIZE_8BIT, 1826 PCIC_IOCTL_IO0_IOCS16SRC_DATASIZE | 1827 PCIC_IOCTL_IO0_DATASIZE_16BIT, 1828 }; 1829 1830 #define PCIC_SIA_START_LOW 0 1831 #define PCIC_SIA_START_HIGH 1 1832 #define PCIC_SIA_STOP_LOW 2 1833 #define PCIC_SIA_STOP_HIGH 3 1834 1835 int regbase_win = 0x8 + win * 0x04; 1836 u_int8_t ioctl, enable; 1837 1838 DPRINTF( 1839 ("pccbb_pcmcia_do_io_map win %d addr 0x%lx size 0x%lx width %d\n", 1840 win, (long)ph->io[win].addr, (long)ph->io[win].size, 1841 ph->io[win].width * 8)); 1842 1843 Pcic_write(ph, regbase_win + PCIC_SIA_START_LOW, 1844 ph->io[win].addr & 0xff); 1845 Pcic_write(ph, regbase_win + PCIC_SIA_START_HIGH, 1846 (ph->io[win].addr >> 8) & 0xff); 1847 1848 Pcic_write(ph, regbase_win + PCIC_SIA_STOP_LOW, 1849 (ph->io[win].addr + ph->io[win].size - 1) & 0xff); 1850 Pcic_write(ph, regbase_win + PCIC_SIA_STOP_HIGH, 1851 ((ph->io[win].addr + ph->io[win].size - 1) >> 8) & 0xff); 1852 1853 ioctl = Pcic_read(ph, PCIC_IOCTL); 1854 enable = Pcic_read(ph, PCIC_ADDRWIN_ENABLE); 1855 switch (win) { 1856 case 0: 1857 ioctl &= ~(PCIC_IOCTL_IO0_WAITSTATE | PCIC_IOCTL_IO0_ZEROWAIT | 1858 PCIC_IOCTL_IO0_IOCS16SRC_MASK | 1859 PCIC_IOCTL_IO0_DATASIZE_MASK); 1860 ioctl |= pcic_iowidth[ph->io[win].width]; 1861 enable |= PCIC_ADDRWIN_ENABLE_IO0; 1862 break; 1863 case 1: 1864 ioctl &= ~(PCIC_IOCTL_IO1_WAITSTATE | PCIC_IOCTL_IO1_ZEROWAIT | 1865 PCIC_IOCTL_IO1_IOCS16SRC_MASK | 1866 PCIC_IOCTL_IO1_DATASIZE_MASK); 1867 ioctl |= (pcic_iowidth[ph->io[win].width] << 4); 1868 enable |= PCIC_ADDRWIN_ENABLE_IO1; 1869 break; 1870 } 1871 Pcic_write(ph, PCIC_IOCTL, ioctl); 1872 Pcic_write(ph, PCIC_ADDRWIN_ENABLE, enable); 1873 #if defined CBB_DEBUG 1874 { 1875 u_int8_t start_low = 1876 Pcic_read(ph, regbase_win + PCIC_SIA_START_LOW); 1877 u_int8_t start_high = 1878 Pcic_read(ph, regbase_win + PCIC_SIA_START_HIGH); 1879 u_int8_t stop_low = 1880 Pcic_read(ph, regbase_win + PCIC_SIA_STOP_LOW); 1881 u_int8_t stop_high = 1882 Pcic_read(ph, regbase_win + PCIC_SIA_STOP_HIGH); 1883 printf 1884 (" start %02x %02x, stop %02x %02x, ioctl %02x enable %02x\n", 1885 start_low, start_high, stop_low, stop_high, ioctl, enable); 1886 } 1887 #endif 1888 } 1889 1890 /* 1891 * void pccbb_pcmcia_io_unmap(pcmcia_chipset_handle_t *h, int win) 1892 * 1893 * This function unmaps I/O region. No return value. 1894 */ 1895 void 1896 pccbb_pcmcia_io_unmap(pcmcia_chipset_handle_t pch, int win) 1897 { 1898 struct pcic_handle *ph = (struct pcic_handle *)pch; 1899 int reg; 1900 1901 if (win >= PCIC_IO_WINS || win < 0) { 1902 panic("pccbb_pcmcia_io_unmap: window out of range"); 1903 } 1904 1905 reg = Pcic_read(ph, PCIC_ADDRWIN_ENABLE); 1906 switch (win) { 1907 case 0: 1908 reg &= ~PCIC_ADDRWIN_ENABLE_IO0; 1909 break; 1910 case 1: 1911 reg &= ~PCIC_ADDRWIN_ENABLE_IO1; 1912 break; 1913 } 1914 Pcic_write(ph, PCIC_ADDRWIN_ENABLE, reg); 1915 1916 ph->ioalloc &= ~(1 << win); 1917 } 1918 1919 /* 1920 * void pccbb_pcmcia_wait_ready(struct pcic_handle *ph) 1921 * 1922 * This function enables the card. All information is stored in 1923 * the first argument, pcmcia_chipset_handle_t. 1924 */ 1925 void 1926 pccbb_pcmcia_wait_ready(struct pcic_handle *ph) 1927 { 1928 int i; 1929 1930 DPRINTF(("pccbb_pcmcia_wait_ready: status 0x%02x\n", 1931 Pcic_read(ph, PCIC_IF_STATUS))); 1932 1933 for (i = 0; i < 10000; i++) { 1934 if (Pcic_read(ph, PCIC_IF_STATUS) & PCIC_IF_STATUS_READY) { 1935 return; 1936 } 1937 delay(500); 1938 #ifdef CBB_DEBUG 1939 if ((i > 5000) && (i % 100 == 99)) 1940 printf("."); 1941 #endif 1942 } 1943 1944 #ifdef DIAGNOSTIC 1945 printf("pcic_wait_ready: ready never happened, status = %02x\n", 1946 Pcic_read(ph, PCIC_IF_STATUS)); 1947 #endif 1948 } 1949 1950 /* 1951 * void pccbb_pcmcia_socket_enable(pcmcia_chipset_handle_t pch) 1952 * 1953 * This function enables the card. All information is stored in 1954 * the first argument, pcmcia_chipset_handle_t. 1955 */ 1956 void 1957 pccbb_pcmcia_socket_enable(pcmcia_chipset_handle_t pch) 1958 { 1959 struct pcic_handle *ph = (struct pcic_handle *)pch; 1960 struct pccbb_softc *sc = (struct pccbb_softc *)ph->ph_parent; 1961 int cardtype, win; 1962 u_int8_t power, intr; 1963 pcireg_t spsr; 1964 int voltage; 1965 1966 /* this bit is mostly stolen from pcic_attach_card */ 1967 1968 DPRINTF(("pccbb_pcmcia_socket_enable: ")); 1969 1970 /* get card Vcc info */ 1971 1972 spsr = 1973 bus_space_read_4(sc->sc_base_memt, sc->sc_base_memh, 1974 CB_SOCKET_STAT); 1975 if (spsr & CB_SOCKET_STAT_5VCARD) { 1976 DPRINTF(("5V card\n")); 1977 voltage = CARDBUS_VCC_5V | CARDBUS_VPP_VCC; 1978 } else if (spsr & CB_SOCKET_STAT_3VCARD) { 1979 DPRINTF(("3V card\n")); 1980 voltage = CARDBUS_VCC_3V | CARDBUS_VPP_VCC; 1981 } else { 1982 DPRINTF(("?V card, 0x%x\n", spsr)); /* XXX */ 1983 return; 1984 } 1985 1986 /* disable socket i/o: negate output enable bit */ 1987 1988 power = 0; 1989 Pcic_write(ph, PCIC_PWRCTL, power); 1990 1991 /* power down the socket to reset it, clear the card reset pin */ 1992 1993 pccbb_power((cardbus_chipset_tag_t)sc, CARDBUS_VCC_0V | CARDBUS_VPP_0V); 1994 1995 /* 1996 * wait 200ms until power fails (Tpf). Then, wait 100ms since 1997 * we are changing Vcc (Toff). 1998 */ 1999 /* delay(300*1000); too much */ 2000 2001 /* assert reset bit */ 2002 intr = Pcic_read(ph, PCIC_INTR); 2003 intr &= ~(PCIC_INTR_RESET | PCIC_INTR_CARDTYPE_MASK); 2004 Pcic_write(ph, PCIC_INTR, intr); 2005 2006 /* Power up the socket. */ 2007 power = Pcic_read(ph, PCIC_PWRCTL); 2008 Pcic_write(ph, PCIC_PWRCTL, (power & ~PCIC_PWRCTL_OE)); 2009 pccbb_power((cardbus_chipset_tag_t)sc, voltage); 2010 2011 /* Now output enable */ 2012 power = Pcic_read(ph, PCIC_PWRCTL); 2013 Pcic_write(ph, PCIC_PWRCTL, power | PCIC_PWRCTL_OE); 2014 2015 /* 2016 * hold RESET at least 10us. 2017 */ 2018 delay(10); 2019 delay(2 * 1000); /* XXX: TI1130 requires it. */ 2020 delay(20 * 1000); /* XXX: TI1130 requires it. */ 2021 2022 /* clear the reset flag */ 2023 2024 intr |= PCIC_INTR_RESET; 2025 Pcic_write(ph, PCIC_INTR, intr); 2026 2027 /* wait 20ms as per pc card standard (r2.01) section 4.3.6 */ 2028 2029 delay(20000); 2030 2031 /* wait for the chip to finish initializing */ 2032 2033 pccbb_pcmcia_wait_ready(ph); 2034 2035 /* zero out the address windows */ 2036 2037 Pcic_write(ph, PCIC_ADDRWIN_ENABLE, 0); 2038 2039 /* set the card type */ 2040 2041 cardtype = pcmcia_card_gettype(ph->pcmcia); 2042 2043 intr |= ((cardtype == PCMCIA_IFTYPE_IO) ? 2044 PCIC_INTR_CARDTYPE_IO : PCIC_INTR_CARDTYPE_MEM); 2045 Pcic_write(ph, PCIC_INTR, intr); 2046 2047 DPRINTF(("%s: pccbb_pcmcia_socket_enable %02x cardtype %s %02x\n", 2048 ph->ph_parent->dv_xname, ph->sock, 2049 ((cardtype == PCMCIA_IFTYPE_IO) ? "io" : "mem"), intr)); 2050 2051 /* reinstall all the memory and io mappings */ 2052 2053 for (win = 0; win < PCIC_MEM_WINS; ++win) { 2054 if (ph->memalloc & (1 << win)) { 2055 pccbb_pcmcia_do_mem_map(ph, win); 2056 } 2057 } 2058 2059 for (win = 0; win < PCIC_IO_WINS; ++win) { 2060 if (ph->ioalloc & (1 << win)) { 2061 pccbb_pcmcia_do_io_map(ph, win); 2062 } 2063 } 2064 } 2065 2066 /* 2067 * void pccbb_pcmcia_socket_disable(pcmcia_chipset_handle_t *ph) 2068 * 2069 * This function disables the card. All information is stored in 2070 * the first argument, pcmcia_chipset_handle_t. 2071 */ 2072 void 2073 pccbb_pcmcia_socket_disable(pcmcia_chipset_handle_t pch) 2074 { 2075 struct pcic_handle *ph = (struct pcic_handle *)pch; 2076 struct pccbb_softc *sc = (struct pccbb_softc *)ph->ph_parent; 2077 u_int8_t power, intr; 2078 2079 DPRINTF(("pccbb_pcmcia_socket_disable\n")); 2080 2081 /* reset signal asserting... */ 2082 2083 intr = Pcic_read(ph, PCIC_INTR); 2084 intr &= ~(PCIC_INTR_CARDTYPE_MASK); 2085 Pcic_write(ph, PCIC_INTR, intr); 2086 delay(2 * 1000); 2087 2088 /* power down the socket */ 2089 power = Pcic_read(ph, PCIC_PWRCTL); 2090 power &= ~PCIC_PWRCTL_OE; 2091 Pcic_write(ph, PCIC_PWRCTL, power); 2092 pccbb_power((cardbus_chipset_tag_t)sc, CARDBUS_VCC_0V | CARDBUS_VPP_0V); 2093 /* 2094 * wait 300ms until power fails (Tpf). 2095 */ 2096 delay(300 * 1000); 2097 } 2098 2099 /* 2100 * int pccbb_pcmcia_card_detect(pcmcia_chipset_handle_t *ph) 2101 * 2102 * This function detects whether a card is in the slot or not. 2103 * If a card is inserted, return 1. Otherwise, return 0. 2104 */ 2105 int 2106 pccbb_pcmcia_card_detect(pcmcia_chipset_handle_t pch) 2107 { 2108 struct pcic_handle *ph = (struct pcic_handle *)pch; 2109 struct pccbb_softc *sc = (struct pccbb_softc *)ph->ph_parent; 2110 2111 DPRINTF(("pccbb_pcmcia_card_detect\n")); 2112 return pccbb_detect_card(sc) == 1 ? 1 : 0; 2113 } 2114 2115 /* 2116 * int pccbb_pcmcia_mem_alloc(pcmcia_chipset_handle_t pch, 2117 * bus_size_t size, 2118 * struct pcmcia_mem_handle *pcmhp) 2119 * 2120 * This function only allocates memory region for pccard. This 2121 * function never maps the allocated region to pccard memory area. 2122 * 2123 * XXX: Why the argument of start address is not in? 2124 */ 2125 int 2126 pccbb_pcmcia_mem_alloc(pcmcia_chipset_handle_t pch, bus_size_t size, 2127 struct pcmcia_mem_handle *pcmhp) 2128 { 2129 struct pcic_handle *ph = (struct pcic_handle *)pch; 2130 bus_space_handle_t memh; 2131 bus_addr_t addr; 2132 bus_size_t sizepg; 2133 struct pccbb_softc *sc = (struct pccbb_softc *)ph->ph_parent; 2134 rbus_tag_t rb; 2135 2136 /* out of sc->memh, allocate as many pages as necessary */ 2137 2138 /* convert size to PCIC pages */ 2139 /* 2140 * This is not enough; when the requested region is on the page 2141 * boundaries, this may calculate wrong result. 2142 */ 2143 sizepg = (size + (PCIC_MEM_PAGESIZE - 1)) / PCIC_MEM_PAGESIZE; 2144 #if 0 2145 if (sizepg > PCIC_MAX_MEM_PAGES) { 2146 return 1; 2147 } 2148 #endif 2149 2150 if (!(sc->sc_pcmcia_flags & PCCBB_PCMCIA_MEM_32)) { 2151 return 1; 2152 } 2153 2154 addr = 0; /* XXX gcc -Wuninitialized */ 2155 2156 rb = sc->sc_rbus_memt; 2157 if (rbus_space_alloc(rb, 0, sizepg * PCIC_MEM_PAGESIZE, 2158 sizepg * PCIC_MEM_PAGESIZE - 1, PCIC_MEM_PAGESIZE, 0, 2159 &addr, &memh)) { 2160 return 1; 2161 } 2162 2163 DPRINTF( 2164 ("pccbb_pcmcia_alloc_mem: addr 0x%lx size 0x%lx, realsize 0x%lx\n", 2165 addr, size, sizepg * PCIC_MEM_PAGESIZE)); 2166 2167 pcmhp->memt = sc->sc_memt; 2168 pcmhp->memh = memh; 2169 pcmhp->addr = addr; 2170 pcmhp->size = size; 2171 pcmhp->realsize = sizepg * PCIC_MEM_PAGESIZE; 2172 /* What is mhandle? I feel it is very dirty and it must go trush. */ 2173 pcmhp->mhandle = 0; 2174 /* No offset??? Funny. */ 2175 2176 return 0; 2177 } 2178 2179 /* 2180 * void pccbb_pcmcia_mem_free(pcmcia_chipset_handle_t pch, 2181 * struct pcmcia_mem_handle *pcmhp) 2182 * 2183 * This function release the memory space allocated by the function 2184 * pccbb_pcmcia_mem_alloc(). 2185 */ 2186 void 2187 pccbb_pcmcia_mem_free(pcmcia_chipset_handle_t pch, 2188 struct pcmcia_mem_handle *pcmhp) 2189 { 2190 struct pcic_handle *ph = (struct pcic_handle *)pch; 2191 struct pccbb_softc *sc = (struct pccbb_softc *)ph->ph_parent; 2192 2193 rbus_space_free(sc->sc_rbus_memt, pcmhp->memh, pcmhp->realsize, NULL); 2194 } 2195 2196 /* 2197 * void pccbb_pcmcia_do_mem_map(struct pcic_handle *ph, int win) 2198 * 2199 * This function release the memory space allocated by the function 2200 * pccbb_pcmcia_mem_alloc(). 2201 */ 2202 void 2203 pccbb_pcmcia_do_mem_map(struct pcic_handle *ph, int win) 2204 { 2205 int regbase_win; 2206 bus_addr_t phys_addr; 2207 bus_addr_t phys_end; 2208 2209 #define PCIC_SMM_START_LOW 0 2210 #define PCIC_SMM_START_HIGH 1 2211 #define PCIC_SMM_STOP_LOW 2 2212 #define PCIC_SMM_STOP_HIGH 3 2213 #define PCIC_CMA_LOW 4 2214 #define PCIC_CMA_HIGH 5 2215 2216 u_int8_t start_low, start_high = 0; 2217 u_int8_t stop_low, stop_high; 2218 u_int8_t off_low, off_high; 2219 u_int8_t mem_window; 2220 int reg; 2221 2222 regbase_win = 0x10 + win * 0x08; 2223 2224 phys_addr = ph->mem[win].addr; 2225 phys_end = phys_addr + ph->mem[win].size; 2226 2227 DPRINTF(("pccbb_pcmcia_do_mem_map: start 0x%lx end 0x%lx off 0x%lx\n", 2228 phys_addr, phys_end, ph->mem[win].offset)); 2229 2230 #define PCIC_MEMREG_LSB_SHIFT PCIC_SYSMEM_ADDRX_SHIFT 2231 #define PCIC_MEMREG_MSB_SHIFT (PCIC_SYSMEM_ADDRX_SHIFT + 8) 2232 #define PCIC_MEMREG_WIN_SHIFT (PCIC_SYSMEM_ADDRX_SHIFT + 12) 2233 2234 /* bit 19:12 */ 2235 start_low = (phys_addr >> PCIC_MEMREG_LSB_SHIFT) & 0xff; 2236 /* bit 23:20 and bit 7 on */ 2237 start_high = ((phys_addr >> PCIC_MEMREG_MSB_SHIFT) & 0x0f) 2238 | PCIC_SYSMEM_ADDRX_START_MSB_DATASIZE_16BIT; /* bit 7 on */ 2239 /* bit 31:24, for 32-bit address */ 2240 mem_window = (phys_addr >> PCIC_MEMREG_WIN_SHIFT) & 0xff; 2241 2242 Pcic_write(ph, regbase_win + PCIC_SMM_START_LOW, start_low); 2243 Pcic_write(ph, regbase_win + PCIC_SMM_START_HIGH, start_high); 2244 2245 if (((struct pccbb_softc *)ph-> 2246 ph_parent)->sc_pcmcia_flags & PCCBB_PCMCIA_MEM_32) { 2247 Pcic_write(ph, 0x40 + win, mem_window); 2248 } 2249 2250 stop_low = (phys_end >> PCIC_MEMREG_LSB_SHIFT) & 0xff; 2251 stop_high = ((phys_end >> PCIC_MEMREG_MSB_SHIFT) & 0x0f) 2252 | PCIC_SYSMEM_ADDRX_STOP_MSB_WAIT2; /* wait 2 cycles */ 2253 /* XXX Geee, WAIT2!! Crazy!! I must rewrite this routine. */ 2254 2255 Pcic_write(ph, regbase_win + PCIC_SMM_STOP_LOW, stop_low); 2256 Pcic_write(ph, regbase_win + PCIC_SMM_STOP_HIGH, stop_high); 2257 2258 off_low = (ph->mem[win].offset >> PCIC_CARDMEM_ADDRX_SHIFT) & 0xff; 2259 off_high = ((ph->mem[win].offset >> (PCIC_CARDMEM_ADDRX_SHIFT + 8)) 2260 & PCIC_CARDMEM_ADDRX_MSB_ADDR_MASK) 2261 | ((ph->mem[win].kind == PCMCIA_MEM_ATTR) ? 2262 PCIC_CARDMEM_ADDRX_MSB_REGACTIVE_ATTR : 0); 2263 2264 Pcic_write(ph, regbase_win + PCIC_CMA_LOW, off_low); 2265 Pcic_write(ph, regbase_win + PCIC_CMA_HIGH, off_high); 2266 2267 reg = Pcic_read(ph, PCIC_ADDRWIN_ENABLE); 2268 reg |= ((1 << win) | PCIC_ADDRWIN_ENABLE_MEMCS16); 2269 Pcic_write(ph, PCIC_ADDRWIN_ENABLE, reg); 2270 2271 #if defined CBB_DEBUG 2272 { 2273 int r1, r2, r3, r4, r5, r6, r7 = 0; 2274 2275 r1 = Pcic_read(ph, regbase_win + PCIC_SMM_START_LOW); 2276 r2 = Pcic_read(ph, regbase_win + PCIC_SMM_START_HIGH); 2277 r3 = Pcic_read(ph, regbase_win + PCIC_SMM_STOP_LOW); 2278 r4 = Pcic_read(ph, regbase_win + PCIC_SMM_STOP_HIGH); 2279 r5 = Pcic_read(ph, regbase_win + PCIC_CMA_LOW); 2280 r6 = Pcic_read(ph, regbase_win + PCIC_CMA_HIGH); 2281 if (((struct pccbb_softc *)(ph-> 2282 ph_parent))->sc_pcmcia_flags & PCCBB_PCMCIA_MEM_32) { 2283 r7 = Pcic_read(ph, 0x40 + win); 2284 } 2285 2286 DPRINTF(("pccbb_pcmcia_do_mem_map window %d: %02x%02x %02x%02x " 2287 "%02x%02x", win, r1, r2, r3, r4, r5, r6)); 2288 if (((struct pccbb_softc *)(ph-> 2289 ph_parent))->sc_pcmcia_flags & PCCBB_PCMCIA_MEM_32) { 2290 DPRINTF((" %02x", r7)); 2291 } 2292 DPRINTF(("\n")); 2293 } 2294 #endif 2295 } 2296 2297 /* 2298 * int pccbb_pcmcia_mem_map(pcmcia_chipset_handle_t pch, int kind, 2299 * bus_addr_t card_addr, bus_size_t size, 2300 * struct pcmcia_mem_handle *pcmhp, 2301 * bus_size_t *offsetp, int *windowp) 2302 * 2303 * This function maps memory space allocated by the function 2304 * pccbb_pcmcia_mem_alloc(). 2305 */ 2306 int 2307 pccbb_pcmcia_mem_map(pcmcia_chipset_handle_t pch, int kind, 2308 bus_addr_t card_addr, bus_size_t size, struct pcmcia_mem_handle *pcmhp, 2309 bus_size_t *offsetp, int *windowp) 2310 { 2311 struct pcic_handle *ph = (struct pcic_handle *)pch; 2312 bus_addr_t busaddr; 2313 long card_offset; 2314 int win; 2315 2316 for (win = 0; win < PCIC_MEM_WINS; ++win) { 2317 if ((ph->memalloc & (1 << win)) == 0) { 2318 ph->memalloc |= (1 << win); 2319 break; 2320 } 2321 } 2322 2323 if (win == PCIC_MEM_WINS) { 2324 return 1; 2325 } 2326 2327 *windowp = win; 2328 2329 /* XXX this is pretty gross */ 2330 2331 if (((struct pccbb_softc *)ph->ph_parent)->sc_memt != pcmhp->memt) { 2332 panic("pccbb_pcmcia_mem_map memt is bogus"); 2333 } 2334 2335 busaddr = pcmhp->addr; 2336 2337 /* 2338 * compute the address offset to the pcmcia address space for the 2339 * pcic. this is intentionally signed. The masks and shifts below 2340 * will cause TRT to happen in the pcic registers. Deal with making 2341 * sure the address is aligned, and return the alignment offset. 2342 */ 2343 2344 *offsetp = card_addr % PCIC_MEM_PAGESIZE; 2345 card_addr -= *offsetp; 2346 2347 DPRINTF(("pccbb_pcmcia_mem_map window %d bus %lx+%lx+%lx at card addr " 2348 "%lx\n", win, (u_long) busaddr, (u_long) * offsetp, (u_long) size, 2349 (u_long) card_addr)); 2350 2351 /* 2352 * include the offset in the size, and decrement size by one, since 2353 * the hw wants start/stop 2354 */ 2355 size += *offsetp - 1; 2356 2357 card_offset = (((long)card_addr) - ((long)busaddr)); 2358 2359 ph->mem[win].addr = busaddr; 2360 ph->mem[win].size = size; 2361 ph->mem[win].offset = card_offset; 2362 ph->mem[win].kind = kind; 2363 2364 pccbb_pcmcia_do_mem_map(ph, win); 2365 2366 return 0; 2367 } 2368 2369 /* 2370 * int pccbb_pcmcia_mem_unmap(pcmcia_chipset_handle_t pch, 2371 * int window) 2372 * 2373 * This function unmaps memory space which mapped by the function 2374 * pccbb_pcmcia_mem_map(). 2375 */ 2376 void 2377 pccbb_pcmcia_mem_unmap(pcmcia_chipset_handle_t pch, int window) 2378 { 2379 struct pcic_handle *ph = (struct pcic_handle *)pch; 2380 int reg; 2381 2382 if (window >= PCIC_MEM_WINS) { 2383 panic("pccbb_pcmcia_mem_unmap: window out of range"); 2384 } 2385 2386 reg = Pcic_read(ph, PCIC_ADDRWIN_ENABLE); 2387 reg &= ~(1 << window); 2388 Pcic_write(ph, PCIC_ADDRWIN_ENABLE, reg); 2389 2390 ph->memalloc &= ~(1 << window); 2391 } 2392 2393 #if defined PCCBB_PCMCIA_POLL 2394 struct pccbb_poll_str { 2395 void *arg; 2396 int (*func)(void *); 2397 int level; 2398 struct pcic_handle *ph; 2399 int count; 2400 int num; 2401 }; 2402 2403 static struct pccbb_poll_str pccbb_poll[10]; 2404 static int pccbb_poll_n = 0; 2405 static struct timeout pccbb_poll_timeout; 2406 2407 void pccbb_pcmcia_poll(void *arg); 2408 2409 void 2410 pccbb_pcmcia_poll(void *arg) 2411 { 2412 struct pccbb_poll_str *poll = arg; 2413 struct pcic_handle *ph = poll->ph; 2414 struct pccbb_softc *sc = ph->sc; 2415 int s; 2416 u_int32_t spsr; /* socket present-state reg */ 2417 2418 timeout_set(&pccbb_poll_timeout, pccbb_pcmcia_poll, arg); 2419 timeout_add_sec(&pccbb_poll_timeout, 2); 2420 switch (poll->level) { 2421 case IPL_NET: 2422 s = splnet(); 2423 break; 2424 case IPL_BIO: 2425 s = splbio(); 2426 break; 2427 case IPL_TTY: /* fallthrough */ 2428 default: 2429 s = spltty(); 2430 break; 2431 } 2432 2433 spsr = 2434 bus_space_read_4(sc->sc_base_memt, sc->sc_base_memh, 2435 CB_SOCKET_STAT); 2436 2437 #if defined PCCBB_PCMCIA_POLL_ONLY && defined LEVEL2 2438 if (!(spsr & 0x40)) /* CINT low */ 2439 #else 2440 if (1) 2441 #endif 2442 { 2443 if ((*poll->func) (poll->arg) > 0) { 2444 ++poll->count; 2445 /* printf("intr: reported from poller, 0x%x\n", spsr); */ 2446 #if defined LEVEL2 2447 } else { 2448 printf("intr: miss! 0x%x\n", spsr); 2449 #endif 2450 } 2451 } 2452 splx(s); 2453 } 2454 #endif /* defined CB_PCMCIA_POLL */ 2455 2456 /* 2457 * void *pccbb_pcmcia_intr_establish(pcmcia_chipset_handle_t pch, 2458 * struct pcmcia_function *pf, 2459 * int ipl, 2460 * int (*func)(void *), 2461 * void *arg); 2462 * 2463 * This function enables PC-Card interrupt. PCCBB uses PCI interrupt line. 2464 */ 2465 void * 2466 pccbb_pcmcia_intr_establish(pcmcia_chipset_handle_t pch, 2467 struct pcmcia_function *pf, int ipl, int (*func)(void *), void *arg, 2468 char *xname) 2469 { 2470 struct pcic_handle *ph = (struct pcic_handle *)pch; 2471 struct pccbb_softc *sc = (struct pccbb_softc *)ph->ph_parent; 2472 2473 if (!(pf->cfe->flags & PCMCIA_CFE_IRQLEVEL)) { 2474 /* what should I do? */ 2475 if ((pf->cfe->flags & PCMCIA_CFE_IRQLEVEL)) { 2476 DPRINTF( 2477 ("%s does not provide edge nor pulse interrupt\n", 2478 sc->sc_dev.dv_xname)); 2479 return NULL; 2480 } 2481 /* 2482 * XXX Noooooo! The interrupt flag must set properly!! 2483 * dumb pcmcia driver!! 2484 */ 2485 } 2486 2487 return pccbb_intr_establish(sc, -1, ipl, func, arg, xname); 2488 } 2489 2490 /* 2491 * void pccbb_pcmcia_intr_disestablish(pcmcia_chipset_handle_t pch, 2492 * void *ih) 2493 * 2494 * This function disables PC-Card interrupt. 2495 */ 2496 void 2497 pccbb_pcmcia_intr_disestablish(pcmcia_chipset_handle_t pch, void *ih) 2498 { 2499 struct pcic_handle *ph = (struct pcic_handle *)pch; 2500 struct pccbb_softc *sc = (struct pccbb_softc *)ph->ph_parent; 2501 2502 pccbb_intr_disestablish(sc, ih); 2503 } 2504 2505 const char * 2506 pccbb_pcmcia_intr_string(pcmcia_chipset_handle_t pch, void *ih) 2507 { 2508 if (ih == NULL) 2509 return "couldn't establish interrupt"; 2510 else 2511 return ""; /* card shares interrupt of the bridge */ 2512 } 2513 2514 /* 2515 * int 2516 * pccbb_rbus_cb_space_alloc(cardbus_chipset_tag_t ct, rbus_tag_t rb, 2517 * bus_addr_t addr, bus_size_t size, 2518 * bus_addr_t mask, bus_size_t align, 2519 * int flags, bus_addr_t *addrp; 2520 * bus_space_handle_t *bshp) 2521 * 2522 * This function allocates a portion of memory or io space for 2523 * clients. This function is called from CardBus card drivers. 2524 */ 2525 int 2526 pccbb_rbus_cb_space_alloc(cardbus_chipset_tag_t ct, rbus_tag_t rb, 2527 bus_addr_t addr, bus_size_t size, bus_addr_t mask, bus_size_t align, 2528 int flags, bus_addr_t *addrp, bus_space_handle_t *bshp) 2529 { 2530 struct pccbb_softc *sc = (struct pccbb_softc *)ct; 2531 2532 DPRINTF( 2533 ("pccbb_rbus_cb_space_alloc: adr %lx, size %lx, mask %lx, align %lx\n", 2534 addr, size, mask, align)); 2535 2536 align = max(align, 4); 2537 mask = max(mask, (4 - 1)); 2538 if (rb->rb_bt == sc->sc_memt) { 2539 align = max(align, 0x1000); 2540 mask = max(mask, (0x1000 - 1)); 2541 } 2542 2543 if (rb->rb_bt == sc->sc_iot) { 2544 /* XXX: hack for avoiding ISA image */ 2545 if (mask < 0x0100) { 2546 mask = 0x3ff; 2547 addr = 0x300; 2548 } 2549 } 2550 2551 if (rbus_space_alloc(rb, addr, size, mask, align, flags, addrp, bshp)) { 2552 printf("%s: <rbus> no bus space\n", sc->sc_dev.dv_xname); 2553 return 1; 2554 } 2555 2556 pccbb_open_win(sc, rb->rb_bt, *addrp, size, *bshp, 0); 2557 2558 return 0; 2559 } 2560 2561 /* 2562 * int 2563 * pccbb_rbus_cb_space_free(cardbus_chipset_tag_t *ct, rbus_tag_t rb, 2564 * bus_space_handle_t *bshp, bus_size_t size); 2565 * 2566 * This function is called from CardBus card drivers. 2567 */ 2568 int 2569 pccbb_rbus_cb_space_free(cardbus_chipset_tag_t ct, rbus_tag_t rb, 2570 bus_space_handle_t bsh, bus_size_t size) 2571 { 2572 struct pccbb_softc *sc = (struct pccbb_softc *)ct; 2573 bus_space_tag_t bt = rb->rb_bt; 2574 2575 pccbb_close_win(sc, bt, bsh, size); 2576 2577 if (bt == sc->sc_memt) { 2578 } else if (bt == sc->sc_iot) { 2579 } else { 2580 return 1; 2581 /* XXX: panic here? */ 2582 } 2583 2584 return rbus_space_free(rb, bsh, size, NULL); 2585 } 2586 2587 int 2588 pccbb_open_win(struct pccbb_softc *sc, bus_space_tag_t bst, bus_addr_t addr, 2589 bus_size_t size, bus_space_handle_t bsh, int flags) 2590 { 2591 struct pccbb_win_chain_head *head; 2592 bus_addr_t align; 2593 2594 head = &sc->sc_iowindow; 2595 align = 0x04; 2596 if (sc->sc_memt == bst) { 2597 head = &sc->sc_memwindow; 2598 align = 0x1000; 2599 DPRINTF(("using memory window, %x %x %x\n\n", 2600 sc->sc_iot, sc->sc_memt, bst)); 2601 } 2602 2603 if (pccbb_winlist_insert(head, addr, size, bsh, flags)) { 2604 printf("%s: pccbb_open_win: %s winlist insert failed\n", 2605 sc->sc_dev.dv_xname, 2606 (head == &sc->sc_memwindow) ? "mem" : "io"); 2607 } 2608 pccbb_winset(align, sc, bst); 2609 2610 return 0; 2611 } 2612 2613 int 2614 pccbb_close_win(struct pccbb_softc *sc, bus_space_tag_t bst, 2615 bus_space_handle_t bsh, bus_size_t size) 2616 { 2617 struct pccbb_win_chain_head *head; 2618 bus_addr_t align; 2619 2620 head = &sc->sc_iowindow; 2621 align = 0x04; 2622 if (sc->sc_memt == bst) { 2623 head = &sc->sc_memwindow; 2624 align = 0x1000; 2625 } 2626 2627 if (pccbb_winlist_delete(head, bsh, size)) { 2628 printf("%s: pccbb_close_win: %s winlist delete failed\n", 2629 sc->sc_dev.dv_xname, 2630 (head == &sc->sc_memwindow) ? "mem" : "io"); 2631 } 2632 pccbb_winset(align, sc, bst); 2633 2634 return 0; 2635 } 2636 2637 int 2638 pccbb_winlist_insert(struct pccbb_win_chain_head *head, bus_addr_t start, 2639 bus_size_t size, bus_space_handle_t bsh, int flags) 2640 { 2641 struct pccbb_win_chain *chainp, *elem; 2642 2643 if ((elem = malloc(sizeof(struct pccbb_win_chain), M_DEVBUF, 2644 M_NOWAIT)) == NULL) 2645 return (1); /* fail */ 2646 2647 elem->wc_start = start; 2648 elem->wc_end = start + (size - 1); 2649 elem->wc_handle = bsh; 2650 elem->wc_flags = flags; 2651 2652 for (chainp = TAILQ_FIRST(head); chainp != NULL; 2653 chainp = TAILQ_NEXT(chainp, wc_list)) { 2654 if (chainp->wc_end < start) 2655 continue; 2656 TAILQ_INSERT_AFTER(head, chainp, elem, wc_list); 2657 return (0); 2658 } 2659 2660 TAILQ_INSERT_TAIL(head, elem, wc_list); 2661 return (0); 2662 } 2663 2664 int 2665 pccbb_winlist_delete(struct pccbb_win_chain_head *head, bus_space_handle_t bsh, 2666 bus_size_t size) 2667 { 2668 struct pccbb_win_chain *chainp; 2669 2670 for (chainp = TAILQ_FIRST(head); chainp != NULL; 2671 chainp = TAILQ_NEXT(chainp, wc_list)) { 2672 if (memcmp(&chainp->wc_handle, &bsh, sizeof(bsh))) 2673 continue; 2674 if ((chainp->wc_end - chainp->wc_start) != (size - 1)) { 2675 printf("pccbb_winlist_delete: window 0x%lx size " 2676 "inconsistent: 0x%lx, 0x%lx\n", 2677 chainp->wc_start, 2678 chainp->wc_end - chainp->wc_start, 2679 size - 1); 2680 return 1; 2681 } 2682 2683 TAILQ_REMOVE(head, chainp, wc_list); 2684 free(chainp, M_DEVBUF, sizeof *chainp); 2685 2686 return 0; 2687 } 2688 2689 return 1; /* fail: no candidate to remove */ 2690 } 2691 2692 void 2693 pccbb_winset(bus_addr_t align, struct pccbb_softc *sc, bus_space_tag_t bst) 2694 { 2695 pci_chipset_tag_t pc; 2696 pcitag_t tag; 2697 bus_addr_t mask = ~(align - 1); 2698 struct { 2699 pcireg_t win_start; 2700 pcireg_t win_limit; 2701 int win_flags; 2702 } win[2]; 2703 struct pccbb_win_chain *chainp; 2704 int offs; 2705 2706 win[0].win_start = win[1].win_start = 0xffffffff; 2707 win[0].win_limit = win[1].win_limit = 0; 2708 win[0].win_flags = win[1].win_flags = 0; 2709 2710 chainp = TAILQ_FIRST(&sc->sc_iowindow); 2711 offs = PCI_CB_IOBASE0; 2712 if (sc->sc_memt == bst) { 2713 chainp = TAILQ_FIRST(&sc->sc_memwindow); 2714 offs = PCI_CB_MEMBASE0; 2715 } 2716 2717 if (chainp != NULL) { 2718 win[0].win_start = chainp->wc_start & mask; 2719 win[0].win_limit = chainp->wc_end & mask; 2720 win[0].win_flags = chainp->wc_flags; 2721 chainp = TAILQ_NEXT(chainp, wc_list); 2722 } 2723 2724 for (; chainp != NULL; chainp = TAILQ_NEXT(chainp, wc_list)) { 2725 if (win[1].win_start == 0xffffffff) { 2726 /* window 1 is not used */ 2727 if ((win[0].win_flags == chainp->wc_flags) && 2728 (win[0].win_limit + align >= 2729 (chainp->wc_start & mask))) { 2730 /* concatenate */ 2731 win[0].win_limit = chainp->wc_end & mask; 2732 } else { 2733 /* make new window */ 2734 win[1].win_start = chainp->wc_start & mask; 2735 win[1].win_limit = chainp->wc_end & mask; 2736 win[1].win_flags = chainp->wc_flags; 2737 } 2738 continue; 2739 } 2740 2741 /* Both windows are engaged. */ 2742 if (win[0].win_flags == win[1].win_flags) { 2743 /* same flags */ 2744 if (win[0].win_flags == chainp->wc_flags) { 2745 if (win[1].win_start - (win[0].win_limit + 2746 align) < 2747 (chainp->wc_start & mask) - 2748 ((chainp->wc_end & mask) + align)) { 2749 /* 2750 * merge window 0 and 1, and set win1 2751 * to chainp 2752 */ 2753 win[0].win_limit = win[1].win_limit; 2754 win[1].win_start = 2755 chainp->wc_start & mask; 2756 win[1].win_limit = 2757 chainp->wc_end & mask; 2758 } else { 2759 win[1].win_limit = 2760 chainp->wc_end & mask; 2761 } 2762 } else { 2763 /* different flags */ 2764 2765 /* concatenate win0 and win1 */ 2766 win[0].win_limit = win[1].win_limit; 2767 /* allocate win[1] to new space */ 2768 win[1].win_start = chainp->wc_start & mask; 2769 win[1].win_limit = chainp->wc_end & mask; 2770 win[1].win_flags = chainp->wc_flags; 2771 } 2772 } else { 2773 /* the flags of win[0] and win[1] are different */ 2774 if (win[0].win_flags == chainp->wc_flags) { 2775 win[0].win_limit = chainp->wc_end & mask; 2776 /* 2777 * XXX this creates overlapping windows, so 2778 * what should the poor bridge do if one is 2779 * cachable, and the other is not? 2780 */ 2781 printf("%s: overlapping windows\n", 2782 sc->sc_dev.dv_xname); 2783 } else { 2784 win[1].win_limit = chainp->wc_end & mask; 2785 } 2786 } 2787 } 2788 2789 pc = sc->sc_pc; 2790 tag = sc->sc_tag; 2791 pci_conf_write(pc, tag, offs, win[0].win_start); 2792 pci_conf_write(pc, tag, offs + 4, win[0].win_limit); 2793 pci_conf_write(pc, tag, offs + 8, win[1].win_start); 2794 pci_conf_write(pc, tag, offs + 12, win[1].win_limit); 2795 DPRINTF(("--pccbb_winset: win0 [%x, %lx), win1 [%x, %lx)\n", 2796 pci_conf_read(pc, tag, offs), 2797 pci_conf_read(pc, tag, offs + 4) + align, 2798 pci_conf_read(pc, tag, offs + 8), 2799 pci_conf_read(pc, tag, offs + 12) + align)); 2800 2801 if (bst == sc->sc_memt) { 2802 pcireg_t bcr = pci_conf_read(pc, tag, PCI_BCR_INTR); 2803 2804 bcr &= ~(CB_BCR_PREFETCH_MEMWIN0 | CB_BCR_PREFETCH_MEMWIN1); 2805 if (win[0].win_flags & PCCBB_MEM_CACHABLE) 2806 bcr |= CB_BCR_PREFETCH_MEMWIN0; 2807 if (win[1].win_flags & PCCBB_MEM_CACHABLE) 2808 bcr |= CB_BCR_PREFETCH_MEMWIN1; 2809 pci_conf_write(pc, tag, PCI_BCR_INTR, bcr); 2810 } 2811 } 2812 2813 int 2814 pccbbactivate(struct device *self, int act) 2815 { 2816 struct pccbb_softc *sc = (struct pccbb_softc *)self; 2817 pci_chipset_tag_t pc = sc->sc_pc; 2818 pcitag_t tag = sc->sc_tag; 2819 pcireg_t csr; 2820 u_int32_t reg; 2821 bus_space_tag_t base_memt = sc->sc_base_memt; /* socket regs memory */ 2822 bus_space_handle_t base_memh = sc->sc_base_memh; 2823 int rv = 0; 2824 2825 switch (act) { 2826 case DVACT_SUSPEND: 2827 rv = config_activate_children(self, act); 2828 2829 sc->sc_pil_intr_enable = 0; 2830 2831 /* Save registers that may get lost. */ 2832 sc->sc_csr = pci_conf_read(pc, tag, PCI_COMMAND_STATUS_REG); 2833 sc->sc_bhlcr = pci_conf_read(pc, tag, PCI_BHLC_REG); 2834 sc->sc_int = pci_conf_read(pc, tag, PCI_INTERRUPT_REG); 2835 2836 sc->sc_sockbase = pci_conf_read(pc, tag, PCI_SOCKBASE); 2837 sc->sc_busnum = pci_conf_read(pc, tag, PCI_BUSNUM); 2838 2839 sc->sc_membase[0] = pci_conf_read(pc, tag, PCI_CB_MEMBASE0); 2840 sc->sc_memlimit[0] = pci_conf_read(pc, tag, PCI_CB_MEMLIMIT0); 2841 sc->sc_membase[1] = pci_conf_read(pc, tag, PCI_CB_MEMBASE1); 2842 sc->sc_memlimit[1] = pci_conf_read(pc, tag, PCI_CB_MEMLIMIT1); 2843 sc->sc_iobase[0] = pci_conf_read(pc, tag, PCI_CB_IOBASE0); 2844 sc->sc_iolimit[0] = pci_conf_read(pc, tag, PCI_CB_IOLIMIT0); 2845 sc->sc_iobase[1] = pci_conf_read(pc, tag, PCI_CB_IOBASE1); 2846 sc->sc_iolimit[1] = pci_conf_read(pc, tag, PCI_CB_IOLIMIT1); 2847 break; 2848 case DVACT_RESUME: 2849 /* Restore the registers saved above. */ 2850 pci_conf_write(pc, tag, PCI_BHLC_REG, sc->sc_bhlcr); 2851 pci_conf_write(pc, tag, PCI_INTERRUPT_REG, sc->sc_int); 2852 2853 pci_conf_write(pc, tag, PCI_SOCKBASE, sc->sc_sockbase); 2854 pci_conf_write(pc, tag, PCI_BUSNUM, sc->sc_busnum); 2855 2856 pci_conf_write(pc, tag, PCI_CB_MEMBASE0, sc->sc_membase[0]); 2857 pci_conf_write(pc, tag, PCI_CB_MEMLIMIT0, sc->sc_memlimit[0]); 2858 pci_conf_write(pc, tag, PCI_CB_MEMBASE1, sc->sc_membase[1]); 2859 pci_conf_write(pc, tag, PCI_CB_MEMLIMIT1, sc->sc_memlimit[1]); 2860 pci_conf_write(pc, tag, PCI_CB_IOBASE0, sc->sc_iobase[0]); 2861 pci_conf_write(pc, tag, PCI_CB_IOLIMIT0, sc->sc_iolimit[0]); 2862 pci_conf_write(pc, tag, PCI_CB_IOBASE1, sc->sc_iobase[1]); 2863 pci_conf_write(pc, tag, PCI_CB_IOLIMIT1, sc->sc_iolimit[1]); 2864 2865 /* Disable legacy register mapping. */ 2866 pccbb_legacy_disable(sc); 2867 2868 /* 2869 * Restore command register last to avoid exposing 2870 * uninitialised windows. 2871 */ 2872 csr = pci_conf_read(pc, tag, PCI_COMMAND_STATUS_REG); 2873 pci_conf_write(pc, tag, PCI_COMMAND_STATUS_REG, 2874 (csr & 0xffff0000) | (sc->sc_csr & 0x0000ffff)); 2875 2876 /* CSC Interrupt: Card detect interrupt on */ 2877 reg = bus_space_read_4(base_memt, base_memh, CB_SOCKET_MASK); 2878 /* Card detect intr is turned on. */ 2879 reg |= CB_SOCKET_MASK_CD; 2880 bus_space_write_4(base_memt, base_memh, CB_SOCKET_MASK, reg); 2881 2882 /* reset interrupt */ 2883 reg = bus_space_read_4(base_memt, base_memh, CB_SOCKET_EVENT); 2884 bus_space_write_4(base_memt, base_memh, CB_SOCKET_EVENT, reg); 2885 2886 /* re-check all cards */ 2887 pccbb_checksockstat(sc); 2888 2889 /* 2890 * XXX Because the cardslot stuff is so obfuscated with threads, 2891 * here we are activating children which may have been 2892 * ejected while we were asleep. This needs to be solved. 2893 */ 2894 rv = config_activate_children(self, act); 2895 2896 sc->sc_pil_intr_enable = 1; 2897 break; 2898 case DVACT_POWERDOWN: 2899 rv = config_activate_children(self, act); 2900 pccbb_shutdown(self); 2901 break; 2902 default: 2903 rv = config_activate_children(self, act); 2904 break; 2905 } 2906 return (rv); 2907 } 2908