1 /* $OpenBSD: pccbb.c,v 1.100 2020/03/20 19:32:41 cheloha Exp $ */ 2 /* $NetBSD: pccbb.c,v 1.96 2004/03/28 09:49:31 nakayama Exp $ */ 3 4 /* 5 * Copyright (c) 1998, 1999 and 2000 6 * HAYAKAWA Koichi. All rights reserved. 7 * 8 * Redistribution and use in source and binary forms, with or without 9 * modification, are permitted provided that the following conditions 10 * are met: 11 * 1. Redistributions of source code must retain the above copyright 12 * notice, this list of conditions and the following disclaimer. 13 * 2. Redistributions in binary form must reproduce the above copyright 14 * notice, this list of conditions and the following disclaimer in the 15 * documentation and/or other materials provided with the distribution. 16 * 17 * THIS SOFTWARE IS PROVIDED BY THE AUTHOR ``AS IS'' AND ANY EXPRESS OR 18 * IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED WARRANTIES 19 * OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE DISCLAIMED. 20 * IN NO EVENT SHALL THE AUTHOR BE LIABLE FOR ANY DIRECT, INDIRECT, 21 * INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT 22 * NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, 23 * DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY 24 * THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT 25 * (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE OF 26 * THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE. 27 */ 28 29 /* 30 #define CBB_DEBUG 31 #define SHOW_REGS 32 #define PCCBB_PCMCIA_POLL 33 */ 34 35 /* 36 #define CB_PCMCIA_POLL 37 #define CB_PCMCIA_POLL_ONLY 38 #define LEVEL2 39 */ 40 41 #include <sys/param.h> 42 #include <sys/systm.h> 43 #include <sys/kernel.h> 44 #include <sys/evcount.h> 45 #include <sys/ioctl.h> 46 #include <sys/syslog.h> 47 #include <sys/device.h> 48 #include <sys/malloc.h> 49 #include <sys/task.h> 50 #include <sys/time.h> 51 #include <sys/timeout.h> 52 53 #include <machine/intr.h> 54 #include <machine/bus.h> 55 56 #include <dev/pci/pcivar.h> 57 #include <dev/pci/pcireg.h> 58 #include <dev/pci/pcidevs.h> 59 60 #include <dev/pci/pccbbreg.h> 61 62 #include <dev/cardbus/cardslotvar.h> 63 64 #include <dev/cardbus/cardbusvar.h> 65 66 #include <dev/pcmcia/pcmciareg.h> 67 #include <dev/pcmcia/pcmciavar.h> 68 69 #include <dev/ic/i82365reg.h> 70 #include <dev/ic/i82365var.h> 71 #include <dev/pci/pccbbvar.h> 72 73 #ifndef __NetBSD_Version__ 74 struct cfdriver cbb_cd = { 75 NULL, "cbb", DV_DULL 76 }; 77 #endif 78 79 #if defined CBB_DEBUG 80 #define DPRINTF(x) printf x 81 #else 82 #define DPRINTF(x) 83 #endif 84 85 int pcicbbmatch(struct device *, void *, void *); 86 void pccbbattach(struct device *, struct device *, void *); 87 int pccbbactivate(struct device *, int); 88 int pccbbintr(void *); 89 void pccbb_shutdown(void *); 90 void pci113x_insert(void *); 91 int pccbbintr_function(struct pccbb_softc *); 92 93 int pccbb_checksockstat(struct pccbb_softc *); 94 int pccbb_detect_card(struct pccbb_softc *); 95 96 void pccbb_pcmcia_write(struct pcic_handle *, int, int); 97 u_int8_t pccbb_pcmcia_read(struct pcic_handle *, int); 98 #define Pcic_read(ph, reg) ((ph)->ph_read((ph), (reg))) 99 #define Pcic_write(ph, reg, val) ((ph)->ph_write((ph), (reg), (val))) 100 101 int cb_reset(struct pccbb_softc *); 102 int cb_detect_voltage(struct pccbb_softc *); 103 int cbbprint(void *, const char *); 104 105 int cb_chipset(u_int32_t, int *); 106 void pccbb_pcmcia_attach_setup(struct pccbb_softc *, 107 struct pcmciabus_attach_args *); 108 #if 0 109 void pccbb_pcmcia_attach_card(struct pcic_handle *); 110 void pccbb_pcmcia_detach_card(struct pcic_handle *, int); 111 void pccbb_pcmcia_deactivate_card(struct pcic_handle *); 112 #endif 113 114 int pccbb_ctrl(cardbus_chipset_tag_t, int); 115 int pccbb_power(cardbus_chipset_tag_t, int); 116 int pccbb_cardenable(struct pccbb_softc * sc, int function); 117 void *pccbb_intr_establish(struct pccbb_softc *, int irq, int level, 118 int (*ih) (void *), void *sc, const char *); 119 void pccbb_intr_disestablish(struct pccbb_softc *, void *ih); 120 121 void *pccbb_cb_intr_establish(cardbus_chipset_tag_t, int irq, int level, 122 int (*ih) (void *), void *sc, const char *); 123 void pccbb_cb_intr_disestablish(cardbus_chipset_tag_t ct, void *ih); 124 125 void pccbb_legacy_disable(struct pccbb_softc *sc); 126 void pccbb_chipinit(struct pccbb_softc *); 127 128 int pccbb_pcmcia_mem_alloc(pcmcia_chipset_handle_t, bus_size_t, 129 struct pcmcia_mem_handle *); 130 void pccbb_pcmcia_mem_free(pcmcia_chipset_handle_t, 131 struct pcmcia_mem_handle *); 132 int pccbb_pcmcia_mem_map(pcmcia_chipset_handle_t, int, bus_addr_t, 133 bus_size_t, struct pcmcia_mem_handle *, bus_size_t *, int *); 134 void pccbb_pcmcia_mem_unmap(pcmcia_chipset_handle_t, int); 135 int pccbb_pcmcia_io_alloc(pcmcia_chipset_handle_t, bus_addr_t, 136 bus_size_t, bus_size_t, struct pcmcia_io_handle *); 137 void pccbb_pcmcia_io_free(pcmcia_chipset_handle_t, 138 struct pcmcia_io_handle *); 139 int pccbb_pcmcia_io_map(pcmcia_chipset_handle_t, int, bus_addr_t, 140 bus_size_t, struct pcmcia_io_handle *, int *); 141 void pccbb_pcmcia_io_unmap(pcmcia_chipset_handle_t, int); 142 void *pccbb_pcmcia_intr_establish(pcmcia_chipset_handle_t, 143 struct pcmcia_function *, int, int (*)(void *), void *, char *); 144 void pccbb_pcmcia_intr_disestablish(pcmcia_chipset_handle_t, void *); 145 const char *pccbb_pcmcia_intr_string(pcmcia_chipset_handle_t, void *); 146 void pccbb_pcmcia_socket_enable(pcmcia_chipset_handle_t); 147 void pccbb_pcmcia_socket_disable(pcmcia_chipset_handle_t); 148 int pccbb_pcmcia_card_detect(pcmcia_chipset_handle_t pch); 149 150 void pccbb_pcmcia_do_io_map(struct pcic_handle *, int); 151 void pccbb_pcmcia_wait_ready(struct pcic_handle *); 152 void pccbb_pcmcia_do_mem_map(struct pcic_handle *, int); 153 154 /* bus-space allocation and deallocation functions */ 155 int pccbb_rbus_cb_space_alloc(cardbus_chipset_tag_t, rbus_tag_t, 156 bus_addr_t addr, bus_size_t size, bus_addr_t mask, bus_size_t align, 157 int flags, bus_addr_t * addrp, bus_space_handle_t * bshp); 158 int pccbb_rbus_cb_space_free(cardbus_chipset_tag_t, rbus_tag_t, 159 bus_space_handle_t, bus_size_t); 160 161 int pccbb_open_win(struct pccbb_softc *, bus_space_tag_t, 162 bus_addr_t, bus_size_t, bus_space_handle_t, int flags); 163 int pccbb_close_win(struct pccbb_softc *, bus_space_tag_t, 164 bus_space_handle_t, bus_size_t); 165 int pccbb_winlist_insert(struct pccbb_win_chain_head *, bus_addr_t, 166 bus_size_t, bus_space_handle_t, int); 167 int pccbb_winlist_delete(struct pccbb_win_chain_head *, 168 bus_space_handle_t, bus_size_t); 169 void pccbb_winset(bus_addr_t align, struct pccbb_softc *, 170 bus_space_tag_t); 171 void pccbb_winlist_show(struct pccbb_win_chain *); 172 173 /* for config_defer */ 174 void pccbb_pci_callback(struct device *); 175 176 #if defined SHOW_REGS 177 void cb_show_regs(pci_chipset_tag_t, pcitag_t, bus_space_tag_t, 178 bus_space_handle_t memh); 179 #endif 180 181 struct cfattach cbb_pci_ca = { 182 sizeof(struct pccbb_softc), pcicbbmatch, pccbbattach, NULL, 183 pccbbactivate 184 }; 185 186 static struct pcmcia_chip_functions pccbb_pcmcia_funcs = { 187 pccbb_pcmcia_mem_alloc, 188 pccbb_pcmcia_mem_free, 189 pccbb_pcmcia_mem_map, 190 pccbb_pcmcia_mem_unmap, 191 pccbb_pcmcia_io_alloc, 192 pccbb_pcmcia_io_free, 193 pccbb_pcmcia_io_map, 194 pccbb_pcmcia_io_unmap, 195 pccbb_pcmcia_intr_establish, 196 pccbb_pcmcia_intr_disestablish, 197 pccbb_pcmcia_intr_string, 198 pccbb_pcmcia_socket_enable, 199 pccbb_pcmcia_socket_disable, 200 pccbb_pcmcia_card_detect 201 }; 202 203 static struct cardbus_functions pccbb_funcs = { 204 pccbb_rbus_cb_space_alloc, 205 pccbb_rbus_cb_space_free, 206 pccbb_cb_intr_establish, 207 pccbb_cb_intr_disestablish, 208 pccbb_ctrl, 209 pccbb_power, 210 }; 211 212 /* 213 * delay_ms() is wait in milliseconds. It should be used instead 214 * of delay() if you want to wait more than 1 ms. 215 */ 216 static inline void 217 delay_ms(int millis, void *param) 218 { 219 if (cold) 220 delay(millis * 1000); 221 else 222 tsleep_nsec(param, PWAIT, "pccbb", MSEC_TO_NSEC(millis)); 223 } 224 225 int 226 pcicbbmatch(parent, match, aux) 227 struct device *parent; 228 void *match; 229 void *aux; 230 { 231 struct pci_attach_args *pa = (struct pci_attach_args *)aux; 232 233 if (PCI_CLASS(pa->pa_class) == PCI_CLASS_BRIDGE && 234 PCI_SUBCLASS(pa->pa_class) == PCI_SUBCLASS_BRIDGE_CARDBUS && 235 PCI_INTERFACE(pa->pa_class) == 0) { 236 return 1; 237 } 238 239 return 0; 240 } 241 242 #define MAKEID(vendor, prod) (((vendor) << PCI_VENDOR_SHIFT) \ 243 | ((prod) << PCI_PRODUCT_SHIFT)) 244 245 struct yenta_chipinfo { 246 pcireg_t yc_id; /* vendor tag | product tag */ 247 int yc_chiptype; 248 int yc_flags; 249 } yc_chipsets[] = { 250 /* Texas Instruments chips */ 251 { MAKEID(PCI_VENDOR_TI, PCI_PRODUCT_TI_PCI1130), CB_TI113X, 252 PCCBB_PCMCIA_IO_RELOC | PCCBB_PCMCIA_MEM_32}, 253 { MAKEID(PCI_VENDOR_TI, PCI_PRODUCT_TI_PCI1131), CB_TI113X, 254 PCCBB_PCMCIA_IO_RELOC | PCCBB_PCMCIA_MEM_32}, 255 { MAKEID(PCI_VENDOR_TI, PCI_PRODUCT_TI_PCI1250), CB_TI125X, 256 PCCBB_PCMCIA_IO_RELOC | PCCBB_PCMCIA_MEM_32}, 257 { MAKEID(PCI_VENDOR_TI, PCI_PRODUCT_TI_PCI1220), CB_TI12XX, 258 PCCBB_PCMCIA_IO_RELOC | PCCBB_PCMCIA_MEM_32}, 259 { MAKEID(PCI_VENDOR_TI, PCI_PRODUCT_TI_PCI1221), CB_TI12XX, 260 PCCBB_PCMCIA_IO_RELOC | PCCBB_PCMCIA_MEM_32}, 261 { MAKEID(PCI_VENDOR_TI, PCI_PRODUCT_TI_PCI1225), CB_TI12XX, 262 PCCBB_PCMCIA_IO_RELOC | PCCBB_PCMCIA_MEM_32}, 263 { MAKEID(PCI_VENDOR_TI, PCI_PRODUCT_TI_PCI1251), CB_TI125X, 264 PCCBB_PCMCIA_IO_RELOC | PCCBB_PCMCIA_MEM_32}, 265 { MAKEID(PCI_VENDOR_TI, PCI_PRODUCT_TI_PCI1251B), CB_TI125X, 266 PCCBB_PCMCIA_IO_RELOC | PCCBB_PCMCIA_MEM_32}, 267 { MAKEID(PCI_VENDOR_TI, PCI_PRODUCT_TI_PCI1211), CB_TI12XX, 268 PCCBB_PCMCIA_IO_RELOC | PCCBB_PCMCIA_MEM_32}, 269 { MAKEID(PCI_VENDOR_TI, PCI_PRODUCT_TI_PCI1410), CB_TI12XX, 270 PCCBB_PCMCIA_IO_RELOC | PCCBB_PCMCIA_MEM_32}, 271 { MAKEID(PCI_VENDOR_TI, PCI_PRODUCT_TI_PCI1420), CB_TI12XX, 272 PCCBB_PCMCIA_IO_RELOC | PCCBB_PCMCIA_MEM_32}, 273 { MAKEID(PCI_VENDOR_TI, PCI_PRODUCT_TI_PCI1450), CB_TI125X, 274 PCCBB_PCMCIA_IO_RELOC | PCCBB_PCMCIA_MEM_32}, 275 { MAKEID(PCI_VENDOR_TI, PCI_PRODUCT_TI_PCI1451), CB_TI12XX, 276 PCCBB_PCMCIA_IO_RELOC | PCCBB_PCMCIA_MEM_32}, 277 { MAKEID(PCI_VENDOR_TI, PCI_PRODUCT_TI_PCI1510), CB_TI12XX, 278 PCCBB_PCMCIA_IO_RELOC | PCCBB_PCMCIA_MEM_32}, 279 { MAKEID(PCI_VENDOR_TI, PCI_PRODUCT_TI_PCI7XX1), CB_TI12XX, 280 PCCBB_PCMCIA_IO_RELOC | PCCBB_PCMCIA_MEM_32}, 281 282 /* Ricoh chips */ 283 { MAKEID(PCI_VENDOR_RICOH, PCI_PRODUCT_RICOH_RF5C475), CB_RX5C47X, 284 PCCBB_PCMCIA_MEM_32}, 285 { MAKEID(PCI_VENDOR_RICOH, PCI_PRODUCT_RICOH_RF5C476), CB_RX5C47X, 286 PCCBB_PCMCIA_MEM_32}, 287 { MAKEID(PCI_VENDOR_RICOH, PCI_PRODUCT_RICOH_RF5C477), CB_RX5C47X, 288 PCCBB_PCMCIA_MEM_32}, 289 { MAKEID(PCI_VENDOR_RICOH, PCI_PRODUCT_RICOH_RF5C478), CB_RX5C47X, 290 PCCBB_PCMCIA_MEM_32}, 291 { MAKEID(PCI_VENDOR_RICOH, PCI_PRODUCT_RICOH_RF5C465), CB_RX5C46X, 292 PCCBB_PCMCIA_MEM_32}, 293 { MAKEID(PCI_VENDOR_RICOH, PCI_PRODUCT_RICOH_RF5C466), CB_RX5C46X, 294 PCCBB_PCMCIA_MEM_32}, 295 296 /* Toshiba products */ 297 { MAKEID(PCI_VENDOR_TOSHIBA2, PCI_PRODUCT_TOSHIBA2_TOPIC95), 298 CB_TOPIC95, PCCBB_PCMCIA_MEM_32}, 299 { MAKEID(PCI_VENDOR_TOSHIBA2, PCI_PRODUCT_TOSHIBA2_TOPIC95B), 300 CB_TOPIC95B, PCCBB_PCMCIA_MEM_32}, 301 { MAKEID(PCI_VENDOR_TOSHIBA2, PCI_PRODUCT_TOSHIBA2_TOPIC97), 302 CB_TOPIC97, PCCBB_PCMCIA_MEM_32}, 303 { MAKEID(PCI_VENDOR_TOSHIBA2, PCI_PRODUCT_TOSHIBA2_TOPIC100), 304 CB_TOPIC97, PCCBB_PCMCIA_MEM_32}, 305 306 /* Cirrus Logic products */ 307 { MAKEID(PCI_VENDOR_CIRRUS, PCI_PRODUCT_CIRRUS_CL_PD6832), 308 CB_CIRRUS, PCCBB_PCMCIA_MEM_32}, 309 { MAKEID(PCI_VENDOR_CIRRUS, PCI_PRODUCT_CIRRUS_CL_PD6833), 310 CB_CIRRUS, PCCBB_PCMCIA_MEM_32}, 311 312 /* older O2Micro bridges */ 313 { MAKEID(PCI_VENDOR_O2MICRO, PCI_PRODUCT_O2MICRO_OZ6729), 314 CB_OLDO2MICRO, PCCBB_PCMCIA_MEM_32}, 315 { MAKEID(PCI_VENDOR_O2MICRO, PCI_PRODUCT_O2MICRO_OZ6730), 316 CB_OLDO2MICRO, PCCBB_PCMCIA_MEM_32}, 317 { MAKEID(PCI_VENDOR_O2MICRO, PCI_PRODUCT_O2MICRO_OZ6872), /* 68[71]2 */ 318 CB_OLDO2MICRO, PCCBB_PCMCIA_MEM_32}, 319 { MAKEID(PCI_VENDOR_O2MICRO, PCI_PRODUCT_O2MICRO_OZ6832), 320 CB_OLDO2MICRO, PCCBB_PCMCIA_MEM_32}, 321 { MAKEID(PCI_VENDOR_O2MICRO, PCI_PRODUCT_O2MICRO_OZ6836), 322 CB_OLDO2MICRO, PCCBB_PCMCIA_MEM_32}, 323 324 /* sentinel, or Generic chip */ 325 { 0 /* null id */ , CB_UNKNOWN, PCCBB_PCMCIA_MEM_32}, 326 }; 327 328 int 329 cb_chipset(pci_id, flagp) 330 u_int32_t pci_id; 331 int *flagp; 332 { 333 struct yenta_chipinfo *yc; 334 335 /* Loop over except the last default entry. */ 336 for (yc = yc_chipsets; yc < yc_chipsets + 337 sizeof(yc_chipsets) / sizeof(yc_chipsets[0]) - 1; yc++) 338 if (pci_id == yc->yc_id) 339 break; 340 341 if (flagp != NULL) 342 *flagp = yc->yc_flags; 343 344 return (yc->yc_chiptype); 345 } 346 347 void 348 pccbb_shutdown(void *arg) 349 { 350 struct pccbb_softc *sc = arg; 351 pcireg_t command; 352 353 DPRINTF(("%s: shutdown\n", sc->sc_dev.dv_xname)); 354 355 /* turn off power */ 356 pccbb_power((cardbus_chipset_tag_t)sc, CARDBUS_VCC_0V | CARDBUS_VPP_0V); 357 358 bus_space_write_4(sc->sc_base_memt, sc->sc_base_memh, CB_SOCKET_MASK, 359 0); 360 361 command = pci_conf_read(sc->sc_pc, sc->sc_tag, PCI_COMMAND_STATUS_REG); 362 363 command &= ~(PCI_COMMAND_IO_ENABLE | PCI_COMMAND_MEM_ENABLE | 364 PCI_COMMAND_MASTER_ENABLE); 365 pci_conf_write(sc->sc_pc, sc->sc_tag, PCI_COMMAND_STATUS_REG, command); 366 } 367 368 void 369 pccbbattach(struct device *parent, struct device *self, void *aux) 370 { 371 struct pccbb_softc *sc = (void *)self; 372 struct pci_attach_args *pa = aux; 373 pci_chipset_tag_t pc = pa->pa_pc; 374 pci_intr_handle_t ih; 375 const char *intrstr = NULL; 376 u_long busnum; 377 int flags; 378 379 pccbb_attach_hook(parent, self, pa); 380 381 sc->sc_chipset = cb_chipset(pa->pa_id, &flags); 382 sc->sc_id = pa->pa_id; 383 384 #ifdef CBB_DEBUG 385 printf(" (chipflags %x)", flags); 386 #endif 387 388 TAILQ_INIT(&sc->sc_memwindow); 389 TAILQ_INIT(&sc->sc_iowindow); 390 391 sc->sc_rbus_iot = rbus_pccbb_parent_io(self, pa); 392 sc->sc_rbus_memt = rbus_pccbb_parent_mem(self, pa); 393 394 /* 395 * MAP socket registers and ExCA registers on memory-space 396 */ 397 if (pci_mapreg_map(pa, PCI_SOCKBASE, PCI_MAPREG_TYPE_MEM, 0, 398 &sc->sc_base_memt, &sc->sc_base_memh, NULL, NULL, 0)) { 399 printf("can't map registers\n"); 400 return; 401 } 402 403 sc->sc_busnum = pci_conf_read(pc, pa->pa_tag, PCI_BUSNUM); 404 405 #if defined CBB_DEBUG 406 { 407 static char *intrname[5] = { "NON", "A", "B", "C", "D" }; 408 printf(": intrpin %s, line %d\n", 409 intrname[pa->pa_intrpin], pa->pa_intrline); 410 } 411 #endif 412 413 /* setup softc */ 414 sc->sc_pc = pc; 415 sc->sc_iot = pa->pa_iot; 416 sc->sc_memt = pa->pa_memt; 417 sc->sc_dmat = pa->pa_dmat; 418 sc->sc_tag = pa->pa_tag; 419 sc->sc_function = pa->pa_function; 420 sc->sc_intrtag = pa->pa_intrtag; 421 sc->sc_intrpin = pa->pa_intrpin; 422 423 sc->sc_pcmcia_flags = flags; /* set PCMCIA facility */ 424 425 /* Map and establish the interrupt. */ 426 if (pci_intr_map(pa, &ih)) { 427 printf(": couldn't map interrupt\n"); 428 return; 429 } 430 intrstr = pci_intr_string(pc, ih); 431 /* must do this after intr is mapped and established */ 432 sc->sc_intrline = pci_intr_line(pc, ih); 433 434 /* 435 * XXX pccbbintr should be called under the priority lower 436 * than any other hard interrupts. 437 */ 438 sc->sc_ih = pci_intr_establish(pc, ih, IPL_BIO, pccbbintr, sc, 439 sc->sc_dev.dv_xname); 440 441 if (sc->sc_ih == NULL) { 442 printf(": couldn't establish interrupt"); 443 if (intrstr != NULL) { 444 printf(" at %s", intrstr); 445 } 446 printf("\n"); 447 return; 448 } 449 printf(": %s", intrstr); 450 451 /* 452 * When the bus number isn't configured, try to allocate one 453 * ourselves. 454 */ 455 if ((sc->sc_busnum & 0x00ffff00) == 0 && pa->pa_busex && 456 extent_alloc(pa->pa_busex, 1, 1, 0, 0, EX_NOWAIT, &busnum) == 0) { 457 sc->sc_busnum |= (busnum << 8); 458 sc->sc_busnum |= (busnum << 16); 459 pci_conf_write(pc, pa->pa_tag, PCI_BUSNUM, sc->sc_busnum); 460 } 461 462 /* 463 * When the bus number still isn't set correctly, give up 464 * using 32-bit CardBus mode. 465 */ 466 if (((sc->sc_busnum >> 8) & 0xff) == 0) { 467 printf(", CardBus support disabled"); 468 sc->sc_pcmcia_flags |= PCCBB_PCMCIA_16BITONLY; 469 } 470 471 printf("\n"); 472 473 /* Disable legacy register mapping. */ 474 pccbb_legacy_disable(sc); 475 476 timeout_set(&sc->sc_ins_tmo, pci113x_insert, sc); 477 config_defer(self, pccbb_pci_callback); 478 } 479 480 /* 481 * void pccbb_pci_callback(struct device *self) 482 * 483 * The actual attach routine: get memory space for YENTA register 484 * space, setup YENTA register and route interrupt. 485 * 486 * This function should be deferred because this device may obtain 487 * memory space dynamically. This function must avoid obtaining 488 * memory area which has already kept for another device. Also, 489 * this function MUST be done before ISA attach process because this 490 * function kills pcic compatible port used by ISA pcic. 491 */ 492 void 493 pccbb_pci_callback(struct device *self) 494 { 495 struct pccbb_softc *sc = (void *)self; 496 pci_chipset_tag_t pc = sc->sc_pc; 497 bus_space_tag_t base_memt; 498 bus_space_handle_t base_memh; 499 u_int32_t maskreg; 500 struct cbslot_attach_args cba; 501 struct pcmciabus_attach_args paa; 502 struct cardslot_attach_args caa; 503 struct cardslot_softc *csc; 504 u_int32_t sockstat; 505 506 base_memt = sc->sc_base_memt; /* socket regs memory tag */ 507 base_memh = sc->sc_base_memh; /* socket regs memory handle */ 508 509 /* bus bridge initialization */ 510 pccbb_chipinit(sc); 511 512 /* clear data structure for child device interrupt handlers */ 513 sc->sc_pil = NULL; 514 sc->sc_pil_intr_enable = 1; 515 516 sockstat = bus_space_read_4(base_memt, base_memh, CB_SOCKET_STAT); 517 if ((sockstat & CB_SOCKET_STAT_CD) == 0) 518 sc->sc_flags |= CBB_CARDEXIST; 519 520 /* 521 * attach cardbus 522 */ 523 if (!(sc->sc_pcmcia_flags & PCCBB_PCMCIA_16BITONLY)) { 524 pcireg_t busreg = pci_conf_read(pc, sc->sc_tag, PCI_BUSNUM); 525 pcireg_t bhlc = pci_conf_read(pc, sc->sc_tag, PCI_BHLC_REG); 526 527 /* initialize cbslot_attach */ 528 cba.cba_busname = "cardbus"; 529 cba.cba_iot = sc->sc_iot; 530 cba.cba_memt = sc->sc_memt; 531 cba.cba_dmat = sc->sc_dmat; 532 cba.cba_bus = (busreg >> 8) & 0x0ff; 533 cba.cba_cc = (void *)sc; 534 cba.cba_pc = sc->sc_pc; 535 cba.cba_cf = &pccbb_funcs; 536 cba.cba_intrline = sc->sc_intrline; 537 538 cba.cba_rbus_iot = sc->sc_rbus_iot; 539 cba.cba_rbus_memt = sc->sc_rbus_memt; 540 541 cba.cba_cacheline = PCI_CACHELINE(bhlc); 542 cba.cba_lattimer = PCI_CB_LATENCY(busreg); 543 544 #if defined CBB_DEBUG 545 printf("%s: cacheline 0x%x lattimer 0x%x\n", 546 sc->sc_dev.dv_xname, cba.cba_cacheline, cba.cba_lattimer); 547 printf("%s: bhlc 0x%x lscp 0x%x\n", sc->sc_dev.dv_xname, bhlc, 548 busreg); 549 #endif 550 #if defined SHOW_REGS 551 cb_show_regs(sc->sc_pc, sc->sc_tag, sc->sc_base_memt, 552 sc->sc_base_memh); 553 #endif 554 } 555 556 pccbb_pcmcia_attach_setup(sc, &paa); 557 caa.caa_cb_attach = NULL; 558 if (!(sc->sc_pcmcia_flags & PCCBB_PCMCIA_16BITONLY)) { 559 caa.caa_cb_attach = &cba; 560 } 561 caa.caa_16_attach = &paa; 562 caa.caa_ph = &sc->sc_pcmcia_h; 563 564 if (NULL != (csc = (void *)config_found(self, &caa, cbbprint))) { 565 DPRINTF(("pccbbattach: found cardslot\n")); 566 sc->sc_csc = csc; 567 } 568 569 sc->sc_ints_on = 1; 570 571 /* CSC Interrupt: Card detect interrupt on */ 572 maskreg = bus_space_read_4(base_memt, base_memh, CB_SOCKET_MASK); 573 maskreg |= CB_SOCKET_MASK_CD; /* Card detect intr is turned on. */ 574 bus_space_write_4(base_memt, base_memh, CB_SOCKET_MASK, maskreg); 575 /* reset interrupt */ 576 bus_space_write_4(base_memt, base_memh, CB_SOCKET_EVENT, 577 bus_space_read_4(base_memt, base_memh, CB_SOCKET_EVENT)); 578 579 return; 580 } 581 582 void 583 pccbb_legacy_disable(struct pccbb_softc *sc) 584 { 585 pcireg_t reg; 586 587 switch (sc->sc_chipset) { 588 case CB_RX5C46X: 589 /* 590 * The legacy pcic io-port on Ricoh RX5C46X CardBus bridges 591 * cannot be disabled by substituting 0 into PCI_LEGACY 592 * register. Ricoh CardBus bridges have special bits on Bridge 593 * control reg (addr 0x3e on PCI config space). 594 */ 595 reg = pci_conf_read(sc->sc_pc, sc->sc_tag, PCI_BCR_INTR); 596 reg &= ~(CB_BCRI_RL_3E0_ENA | CB_BCRI_RL_3E2_ENA); 597 pci_conf_write(sc->sc_pc, sc->sc_tag, PCI_BCR_INTR, reg); 598 break; 599 600 default: 601 pci_conf_write(sc->sc_pc, sc->sc_tag, PCI_LEGACY, 0x0); 602 break; 603 } 604 } 605 606 /* 607 * void pccbb_chipinit(struct pccbb_softc *sc) 608 * 609 * This function initialize YENTA chip registers listed below: 610 * 1) PCI command reg, 611 * 2) PCI and CardBus latency timer, 612 * 3) route PCI interrupt, 613 * 4) close all memory and io windows. 614 */ 615 void 616 pccbb_chipinit(struct pccbb_softc *sc) 617 { 618 pci_chipset_tag_t pc = sc->sc_pc; 619 pcitag_t tag = sc->sc_tag; 620 pcireg_t reg; 621 622 /* Power on the controller if the BIOS didn't */ 623 pci_set_powerstate(pc, tag, PCI_PMCSR_STATE_D0); 624 625 /* 626 * Set PCI command reg. 627 * Some laptop's BIOSes (i.e. TICO) do not enable CardBus chip. 628 */ 629 reg = pci_conf_read(pc, tag, PCI_COMMAND_STATUS_REG); 630 /* I believe it is harmless. */ 631 reg |= (PCI_COMMAND_IO_ENABLE | PCI_COMMAND_MEM_ENABLE | 632 PCI_COMMAND_MASTER_ENABLE); 633 pci_conf_write(pc, tag, PCI_COMMAND_STATUS_REG, reg); 634 635 /* 636 * Set CardBus latency timer. 637 */ 638 reg = pci_conf_read(pc, tag, PCI_CB_LSCP_REG); 639 if (PCI_CB_LATENCY(reg) < 0x20) { 640 reg &= ~(PCI_CB_LATENCY_MASK << PCI_CB_LATENCY_SHIFT); 641 reg |= (0x20 << PCI_CB_LATENCY_SHIFT); 642 pci_conf_write(pc, tag, PCI_CB_LSCP_REG, reg); 643 } 644 DPRINTF(("CardBus latency timer 0x%x (%x)\n", 645 PCI_CB_LATENCY(reg), pci_conf_read(pc, tag, PCI_CB_LSCP_REG))); 646 647 /* 648 * Set PCI latency timer. 649 */ 650 reg = pci_conf_read(pc, tag, PCI_BHLC_REG); 651 if (PCI_LATTIMER(reg) < 0x10) { 652 reg &= ~(PCI_LATTIMER_MASK << PCI_LATTIMER_SHIFT); 653 reg |= (0x10 << PCI_LATTIMER_SHIFT); 654 pci_conf_write(pc, tag, PCI_BHLC_REG, reg); 655 } 656 DPRINTF(("PCI latency timer 0x%x (%x)\n", 657 PCI_LATTIMER(reg), pci_conf_read(pc, tag, PCI_BHLC_REG))); 658 659 /* Route functional interrupts to PCI. */ 660 reg = pci_conf_read(pc, tag, PCI_BCR_INTR); 661 reg |= CB_BCR_INTR_IREQ_ENABLE; /* disable PCI Intr */ 662 reg |= CB_BCR_WRITE_POST_ENABLE; /* enable write post */ 663 reg |= CB_BCR_RESET_ENABLE; /* assert reset */ 664 pci_conf_write(pc, tag, PCI_BCR_INTR, reg); 665 666 switch (sc->sc_chipset) { 667 case CB_TI113X: 668 reg = pci_conf_read(pc, tag, PCI_CBCTRL); 669 /* This bit is shared, but may read as 0 on some chips, so set 670 it explicitly on both functions. */ 671 reg |= PCI113X_CBCTRL_PCI_IRQ_ENA; 672 /* CSC intr enable */ 673 reg |= PCI113X_CBCTRL_PCI_CSC; 674 /* functional intr prohibit | prohibit ISA routing */ 675 reg &= ~(PCI113X_CBCTRL_PCI_INTR | PCI113X_CBCTRL_INT_MASK); 676 pci_conf_write(pc, tag, PCI_CBCTRL, reg); 677 break; 678 679 case CB_TI12XX: 680 /* 681 * Some TI 12xx (and [14][45]xx) based pci cards 682 * sometimes have issues with the MFUNC register not 683 * being initialized due to a bad EEPROM on board. 684 * Laptops that this matters on have this register 685 * properly initialized. 686 * 687 * The TI125X parts have a different register. 688 */ 689 reg = pci_conf_read(pc, tag, PCI12XX_MFUNC); 690 if (reg == PCI12XX_MFUNC_DEFAULT) { 691 reg &= ~PCI12XX_MFUNC_PIN0; 692 reg |= PCI12XX_MFUNC_PIN0_INTA; 693 if ((pci_conf_read(pc, tag, PCI_SYSCTRL) & 694 PCI12XX_SYSCTRL_INTRTIE) == 0) { 695 reg &= ~PCI12XX_MFUNC_PIN1; 696 reg |= PCI12XX_MFUNC_PIN1_INTB; 697 } 698 pci_conf_write(pc, tag, PCI12XX_MFUNC, reg); 699 } 700 /* FALLTHROUGH */ 701 702 case CB_TI125X: 703 /* 704 * Disable zoom video. Some machines initialize this 705 * improperly and experience has shown that this helps 706 * prevent strange behavior. 707 */ 708 pci_conf_write(pc, tag, PCI12XX_MMCTRL, 0); 709 710 reg = pci_conf_read(pc, tag, PCI_SYSCTRL); 711 reg |= PCI12XX_SYSCTRL_VCCPROT; 712 pci_conf_write(pc, tag, PCI_SYSCTRL, reg); 713 reg = pci_conf_read(pc, tag, PCI_CBCTRL); 714 reg |= PCI12XX_CBCTRL_CSC; 715 pci_conf_write(pc, tag, PCI_CBCTRL, reg); 716 break; 717 718 case CB_TOPIC95B: 719 reg = pci_conf_read(pc, tag, TOPIC_SOCKET_CTRL); 720 reg |= TOPIC_SOCKET_CTRL_SCR_IRQSEL; 721 pci_conf_write(pc, tag, TOPIC_SOCKET_CTRL, reg); 722 723 reg = pci_conf_read(pc, tag, TOPIC_SLOT_CTRL); 724 DPRINTF(("%s: topic slot ctrl reg 0x%x -> ", 725 sc->sc_dev.dv_xname, reg)); 726 reg |= (TOPIC_SLOT_CTRL_SLOTON | TOPIC_SLOT_CTRL_SLOTEN | 727 TOPIC_SLOT_CTRL_ID_LOCK | TOPIC_SLOT_CTRL_CARDBUS); 728 reg &= ~TOPIC_SLOT_CTRL_SWDETECT; 729 DPRINTF(("0x%x\n", reg)); 730 pci_conf_write(pc, tag, TOPIC_SLOT_CTRL, reg); 731 break; 732 733 case CB_TOPIC97: 734 reg = pci_conf_read(pc, tag, TOPIC_SLOT_CTRL); 735 DPRINTF(("%s: topic slot ctrl reg 0x%x -> ", 736 sc->sc_dev.dv_xname, reg)); 737 reg |= (TOPIC_SLOT_CTRL_SLOTON | TOPIC_SLOT_CTRL_SLOTEN | 738 TOPIC_SLOT_CTRL_ID_LOCK | TOPIC_SLOT_CTRL_CARDBUS); 739 reg &= ~TOPIC_SLOT_CTRL_SWDETECT; 740 reg |= TOPIC97_SLOT_CTRL_PCIINT; 741 reg &= ~(TOPIC97_SLOT_CTRL_STSIRQP | TOPIC97_SLOT_CTRL_IRQP); 742 DPRINTF(("0x%x\n", reg)); 743 pci_conf_write(pc, tag, TOPIC_SLOT_CTRL, reg); 744 745 /* make sure to assert LV card support bits */ 746 bus_space_write_1(sc->sc_base_memt, sc->sc_base_memh, 747 0x800 + 0x3e, bus_space_read_1(sc->sc_base_memt, 748 sc->sc_base_memh, 0x800 + 0x3e) | 0x03); 749 break; 750 751 case CB_OLDO2MICRO: 752 /* 753 * older bridges have problems with both read prefetch and 754 * write bursting depending on the combination of the chipset, 755 * bridge and the cardbus card. so disable them to be on the 756 * safe side. One example is O2Micro 6812 with Atheros AR5012 757 * chipsets 758 */ 759 DPRINTF(("%s: old O2Micro bridge found\n", 760 sc->sc_dev.dv_xname, reg)); 761 reg = pci_conf_read(pc, tag, O2MICRO_RESERVED1); 762 pci_conf_write(pc, tag, O2MICRO_RESERVED1, reg & 763 ~(O2MICRO_RES_READ_PREFETCH | O2MICRO_RES_WRITE_BURST)); 764 reg = pci_conf_read(pc, tag, O2MICRO_RESERVED2); 765 pci_conf_write(pc, tag, O2MICRO_RESERVED2, reg & 766 ~(O2MICRO_RES_READ_PREFETCH | O2MICRO_RES_WRITE_BURST)); 767 break; 768 } 769 770 /* Close all memory and I/O windows. */ 771 pci_conf_write(pc, tag, PCI_CB_MEMBASE0, 0xffffffff); 772 pci_conf_write(pc, tag, PCI_CB_MEMLIMIT0, 0); 773 pci_conf_write(pc, tag, PCI_CB_MEMBASE1, 0xffffffff); 774 pci_conf_write(pc, tag, PCI_CB_MEMLIMIT1, 0); 775 pci_conf_write(pc, tag, PCI_CB_IOBASE0, 0xffffffff); 776 pci_conf_write(pc, tag, PCI_CB_IOLIMIT0, 0); 777 pci_conf_write(pc, tag, PCI_CB_IOBASE1, 0xffffffff); 778 pci_conf_write(pc, tag, PCI_CB_IOLIMIT1, 0); 779 780 /* reset 16-bit pcmcia bus */ 781 bus_space_write_1(sc->sc_base_memt, sc->sc_base_memh, 782 0x800 + PCIC_INTR, 783 bus_space_read_1(sc->sc_base_memt, sc->sc_base_memh, 784 0x800 + PCIC_INTR) & ~PCIC_INTR_RESET); 785 786 /* turn off power */ 787 pccbb_power((cardbus_chipset_tag_t)sc, CARDBUS_VCC_0V | CARDBUS_VPP_0V); 788 } 789 790 791 792 793 /* 794 * void pccbb_pcmcia_attach_setup(struct pccbb_softc *sc, 795 * struct pcmciabus_attach_args *paa) 796 * 797 * This function attaches 16-bit PCcard bus. 798 */ 799 void 800 pccbb_pcmcia_attach_setup(struct pccbb_softc *sc, 801 struct pcmciabus_attach_args *paa) 802 { 803 struct pcic_handle *ph = &sc->sc_pcmcia_h; 804 rbus_tag_t rb; 805 806 /* initialize pcmcia part in pccbb_softc */ 807 ph->ph_parent = (struct device *)sc; 808 ph->sock = sc->sc_function; 809 ph->flags = 0; 810 ph->shutdown = 0; 811 ph->ih_irq = sc->sc_intrline; 812 ph->ph_bus_t = sc->sc_base_memt; 813 ph->ph_bus_h = sc->sc_base_memh; 814 ph->ph_read = pccbb_pcmcia_read; 815 ph->ph_write = pccbb_pcmcia_write; 816 sc->sc_pct = &pccbb_pcmcia_funcs; 817 818 /* 819 * We need to do a few things here: 820 * 1) Disable routing of CSC and functional interrupts to ISA IRQs by 821 * setting the IRQ numbers to 0. 822 * 2) Set bit 4 of PCIC_INTR, which is needed on some chips to enable 823 * routing of CSC interrupts (e.g. card removal) to PCI while in 824 * PCMCIA mode. We just leave this set all the time. 825 * 3) Enable card insertion/removal interrupts in case the chip also 826 * needs that while in PCMCIA mode. 827 * 4) Clear any pending CSC interrupt. 828 */ 829 Pcic_write(ph, PCIC_INTR, PCIC_INTR_ENABLE | PCIC_INTR_RESET); 830 if (sc->sc_chipset == CB_TI113X) { 831 Pcic_write(ph, PCIC_CSC_INTR, 0); 832 } else { 833 Pcic_write(ph, PCIC_CSC_INTR, PCIC_CSC_INTR_CD_ENABLE); 834 Pcic_read(ph, PCIC_CSC); 835 } 836 837 /* initialize pcmcia bus attachment */ 838 paa->paa_busname = "pcmcia"; 839 paa->pct = sc->sc_pct; 840 paa->pch = ph; 841 paa->iobase = 0; /* I don't use them */ 842 paa->iosize = 0; 843 rb = ((struct pccbb_softc *)(ph->ph_parent))->sc_rbus_iot; 844 paa->iobase = rb->rb_start + rb->rb_offset; 845 paa->iosize = rb->rb_end - rb->rb_start; 846 847 return; 848 } 849 850 #if 0 851 void 852 pccbb_pcmcia_attach_card(struct pcic_handle *ph) 853 { 854 if (ph->flags & PCIC_FLAG_CARDP) { 855 panic("pccbb_pcmcia_attach_card: already attached"); 856 } 857 858 /* call the MI attach function */ 859 pcmcia_card_attach(ph->pcmcia); 860 861 ph->flags |= PCIC_FLAG_CARDP; 862 } 863 864 void 865 pccbb_pcmcia_detach_card(struct pcic_handle *ph, int flags) 866 { 867 if (!(ph->flags & PCIC_FLAG_CARDP)) { 868 panic("pccbb_pcmcia_detach_card: already detached"); 869 } 870 871 ph->flags &= ~PCIC_FLAG_CARDP; 872 873 /* call the MI detach function */ 874 pcmcia_card_detach(ph->pcmcia, flags); 875 } 876 #endif 877 878 int 879 pccbb_checksockstat(struct pccbb_softc *sc) 880 { 881 u_int32_t sockstate; 882 883 sockstate = bus_space_read_4(sc->sc_base_memt, sc->sc_base_memh, 884 CB_SOCKET_STAT); 885 886 if ((sockstate & CB_SOCKET_STAT_CD) != 0) { 887 /* A card should be removed. */ 888 if (sc->sc_flags & CBB_CARDEXIST) { 889 DPRINTF(("%s: card removed, 0x%08x\n", 890 sc->sc_dev.dv_xname, sockstate)); 891 sc->sc_flags &= ~CBB_CARDEXIST; 892 if (sc->sc_csc->sc_status & CARDSLOT_STATUS_CARD_16) { 893 #if 0 894 struct pcic_handle *ph = 895 &sc->sc_pcmcia_h; 896 897 pcmcia_card_deactivate(ph->pcmcia); 898 pccbb_pcmcia_socket_disable(ph); 899 pccbb_pcmcia_detach_card(ph, 900 DETACH_FORCE); 901 #endif 902 cardslot_event_throw(sc->sc_csc, 903 CARDSLOT_EVENT_REMOVAL_16); 904 } else if (sc->sc_csc->sc_status & 905 CARDSLOT_STATUS_CARD_CB) { 906 /* Cardbus intr removed */ 907 cardslot_event_throw(sc->sc_csc, 908 CARDSLOT_EVENT_REMOVAL_CB); 909 } 910 } 911 return (1); 912 } else if ((sockstate & CB_SOCKET_STAT_CD) == 0 && 913 (sc->sc_flags & CBB_CARDEXIST) == 0) { 914 timeout_add_msec(&sc->sc_ins_tmo, 100); 915 sc->sc_flags |= CBB_INSERTING; 916 return (1); 917 } 918 return (0); 919 } 920 921 /* 922 * int pccbbintr(arg) 923 * void *arg; 924 * This routine handles the interrupt from Yenta PCI-CardBus bridge 925 * itself. 926 */ 927 int 928 pccbbintr(void *arg) 929 { 930 struct pccbb_softc *sc = (struct pccbb_softc *)arg; 931 u_int32_t sockevent; 932 struct pcic_handle *ph = &sc->sc_pcmcia_h; 933 934 if (!sc->sc_ints_on) 935 return 0; 936 937 sockevent = bus_space_read_4(sc->sc_base_memt, sc->sc_base_memh, 938 CB_SOCKET_EVENT); 939 bus_space_write_4(sc->sc_base_memt, sc->sc_base_memh, 940 CB_SOCKET_EVENT, sockevent); 941 Pcic_read(ph, PCIC_CSC); 942 943 if (sockevent & CB_SOCKET_EVENT_CD) { 944 if (pccbb_checksockstat(sc)) 945 return (1); 946 } 947 948 if (sc->sc_pil_intr_enable) 949 return pccbbintr_function(sc); 950 return (0); 951 } 952 953 /* 954 * int pccbbintr_function(struct pccbb_softc *sc) 955 * 956 * This function calls each interrupt handler registered at the 957 * bridge. The interrupt handlers are called in registered order. 958 */ 959 int 960 pccbbintr_function(struct pccbb_softc *sc) 961 { 962 int retval = 0, val; 963 struct pccbb_intrhand_list *pil; 964 int s; 965 966 for (pil = sc->sc_pil; pil != NULL; pil = pil->pil_next) { 967 s = splraise(pil->pil_level); 968 969 val = (*pil->pil_func)(pil->pil_arg); 970 if (val != 0) 971 pil->pil_count.ec_count++; 972 973 splx(s); 974 975 if (retval == 0 || val != 0) 976 retval = val; 977 } 978 979 return retval; 980 } 981 982 void 983 pci113x_insert(void *arg) 984 { 985 struct pccbb_softc *sc = (struct pccbb_softc *)arg; 986 u_int32_t sockevent, sockstate; 987 988 sockevent = bus_space_read_4(sc->sc_base_memt, sc->sc_base_memh, 989 CB_SOCKET_EVENT); 990 sockstate = bus_space_read_4(sc->sc_base_memt, sc->sc_base_memh, 991 CB_SOCKET_STAT); 992 993 if (0 == (sockstate & CB_SOCKET_STAT_CD)) { /* card exist */ 994 DPRINTF(("%s: 0x%08x", sc->sc_dev.dv_xname, sockevent)); 995 DPRINTF((" card inserted, 0x%08x\n", sockstate)); 996 sc->sc_flags |= CBB_CARDEXIST; 997 /* call pccard interrupt handler here */ 998 if (sockstate & CB_SOCKET_STAT_16BIT) { 999 /* 16-bit card found */ 1000 /* pccbb_pcmcia_attach_card(&sc->sc_pcmcia_h); */ 1001 cardslot_event_throw(sc->sc_csc, 1002 CARDSLOT_EVENT_INSERTION_16); 1003 } else if (sockstate & CB_SOCKET_STAT_CB) { 1004 /* cardbus card found */ 1005 /* cardbus_attach_card(sc->sc_csc); */ 1006 cardslot_event_throw(sc->sc_csc, 1007 CARDSLOT_EVENT_INSERTION_CB); 1008 } else { 1009 /* who are you? */ 1010 } 1011 } else { 1012 timeout_add_msec(&sc->sc_ins_tmo, 100); 1013 } 1014 } 1015 1016 #define PCCBB_PCMCIA_OFFSET 0x800 1017 u_int8_t 1018 pccbb_pcmcia_read(struct pcic_handle *ph, int reg) 1019 { 1020 bus_space_barrier(ph->ph_bus_t, ph->ph_bus_h, 1021 PCCBB_PCMCIA_OFFSET + reg, 1, BUS_SPACE_BARRIER_READ); 1022 1023 return bus_space_read_1(ph->ph_bus_t, ph->ph_bus_h, 1024 PCCBB_PCMCIA_OFFSET + reg); 1025 } 1026 1027 void 1028 pccbb_pcmcia_write(struct pcic_handle *ph, int reg, int val) 1029 { 1030 bus_space_barrier(ph->ph_bus_t, ph->ph_bus_h, 1031 PCCBB_PCMCIA_OFFSET + reg, 1, BUS_SPACE_BARRIER_WRITE); 1032 1033 bus_space_write_1(ph->ph_bus_t, ph->ph_bus_h, PCCBB_PCMCIA_OFFSET + reg, 1034 val); 1035 } 1036 1037 /* 1038 * int pccbb_ctrl(cardbus_chipset_tag_t, int) 1039 */ 1040 int 1041 pccbb_ctrl(cardbus_chipset_tag_t ct, int command) 1042 { 1043 struct pccbb_softc *sc = (struct pccbb_softc *)ct; 1044 1045 switch (command) { 1046 case CARDBUS_CD: 1047 if (2 == pccbb_detect_card(sc)) { 1048 int retval = 0; 1049 int status = cb_detect_voltage(sc); 1050 if (PCCARD_VCC_5V & status) { 1051 retval |= CARDBUS_5V_CARD; 1052 } 1053 if (PCCARD_VCC_3V & status) { 1054 retval |= CARDBUS_3V_CARD; 1055 } 1056 if (PCCARD_VCC_XV & status) { 1057 retval |= CARDBUS_XV_CARD; 1058 } 1059 if (PCCARD_VCC_YV & status) { 1060 retval |= CARDBUS_YV_CARD; 1061 } 1062 return retval; 1063 } else { 1064 return 0; 1065 } 1066 break; 1067 case CARDBUS_RESET: 1068 return cb_reset(sc); 1069 break; 1070 case CARDBUS_IO_ENABLE: /* fallthrough */ 1071 case CARDBUS_IO_DISABLE: /* fallthrough */ 1072 case CARDBUS_MEM_ENABLE: /* fallthrough */ 1073 case CARDBUS_MEM_DISABLE: /* fallthrough */ 1074 case CARDBUS_BM_ENABLE: /* fallthrough */ 1075 case CARDBUS_BM_DISABLE: /* fallthrough */ 1076 return pccbb_cardenable(sc, command); 1077 break; 1078 } 1079 1080 return 0; 1081 } 1082 1083 /* 1084 * int pccbb_power(cardbus_chipset_tag_t, int) 1085 * This function returns true when it succeeds and returns false when 1086 * it fails. 1087 */ 1088 int 1089 pccbb_power(cardbus_chipset_tag_t ct, int command) 1090 { 1091 struct pccbb_softc *sc = (struct pccbb_softc *)ct; 1092 1093 u_int32_t status, sock_ctrl; 1094 bus_space_tag_t memt = sc->sc_base_memt; 1095 bus_space_handle_t memh = sc->sc_base_memh; 1096 1097 DPRINTF(("pccbb_power: %s and %s [%x]\n", 1098 (command & CARDBUS_VCCMASK) == CARDBUS_VCC_UC ? "CARDBUS_VCC_UC" : 1099 (command & CARDBUS_VCCMASK) == CARDBUS_VCC_5V ? "CARDBUS_VCC_5V" : 1100 (command & CARDBUS_VCCMASK) == CARDBUS_VCC_3V ? "CARDBUS_VCC_3V" : 1101 (command & CARDBUS_VCCMASK) == CARDBUS_VCC_XV ? "CARDBUS_VCC_XV" : 1102 (command & CARDBUS_VCCMASK) == CARDBUS_VCC_YV ? "CARDBUS_VCC_YV" : 1103 (command & CARDBUS_VCCMASK) == CARDBUS_VCC_0V ? "CARDBUS_VCC_0V" : 1104 "UNKNOWN", 1105 (command & CARDBUS_VPPMASK) == CARDBUS_VPP_UC ? "CARDBUS_VPP_UC" : 1106 (command & CARDBUS_VPPMASK) == CARDBUS_VPP_12V ? "CARDBUS_VPP_12V" : 1107 (command & CARDBUS_VPPMASK) == CARDBUS_VPP_VCC ? "CARDBUS_VPP_VCC" : 1108 (command & CARDBUS_VPPMASK) == CARDBUS_VPP_0V ? "CARDBUS_VPP_0V" : 1109 "UNKNOWN", command)); 1110 1111 status = bus_space_read_4(memt, memh, CB_SOCKET_STAT); 1112 sock_ctrl = bus_space_read_4(memt, memh, CB_SOCKET_CTRL); 1113 1114 switch (command & CARDBUS_VCCMASK) { 1115 case CARDBUS_VCC_UC: 1116 break; 1117 case CARDBUS_VCC_5V: 1118 if (CB_SOCKET_STAT_5VCARD & status) { /* check 5 V card */ 1119 sock_ctrl &= ~CB_SOCKET_CTRL_VCCMASK; 1120 sock_ctrl |= CB_SOCKET_CTRL_VCC_5V; 1121 } else { 1122 printf("%s: BAD voltage request: no 5 V card\n", 1123 sc->sc_dev.dv_xname); 1124 } 1125 break; 1126 case CARDBUS_VCC_3V: 1127 if (CB_SOCKET_STAT_3VCARD & status) { 1128 sock_ctrl &= ~CB_SOCKET_CTRL_VCCMASK; 1129 sock_ctrl |= CB_SOCKET_CTRL_VCC_3V; 1130 } else { 1131 printf("%s: BAD voltage request: no 3.3 V card\n", 1132 sc->sc_dev.dv_xname); 1133 } 1134 break; 1135 case CARDBUS_VCC_0V: 1136 sock_ctrl &= ~CB_SOCKET_CTRL_VCCMASK; 1137 break; 1138 default: 1139 return 0; /* power NEVER changed */ 1140 break; 1141 } 1142 1143 switch (command & CARDBUS_VPPMASK) { 1144 case CARDBUS_VPP_UC: 1145 break; 1146 case CARDBUS_VPP_0V: 1147 sock_ctrl &= ~CB_SOCKET_CTRL_VPPMASK; 1148 break; 1149 case CARDBUS_VPP_VCC: 1150 sock_ctrl &= ~CB_SOCKET_CTRL_VPPMASK; 1151 sock_ctrl |= ((sock_ctrl >> 4) & 0x07); 1152 break; 1153 case CARDBUS_VPP_12V: 1154 sock_ctrl &= ~CB_SOCKET_CTRL_VPPMASK; 1155 sock_ctrl |= CB_SOCKET_CTRL_VPP_12V; 1156 break; 1157 } 1158 1159 #if 0 1160 DPRINTF(("sock_ctrl: %x\n", sock_ctrl)); 1161 #endif 1162 bus_space_write_4(memt, memh, CB_SOCKET_CTRL, sock_ctrl); 1163 status = bus_space_read_4(memt, memh, CB_SOCKET_STAT); 1164 1165 if (status & CB_SOCKET_STAT_BADVCC) { /* bad Vcc request */ 1166 printf 1167 ("%s: bad Vcc request. sock_ctrl 0x%x, sock_status 0x%x\n", 1168 sc->sc_dev.dv_xname, sock_ctrl, status); 1169 DPRINTF(("pccbb_power: %s and %s [%x]\n", 1170 (command & CARDBUS_VCCMASK) == 1171 CARDBUS_VCC_UC ? "CARDBUS_VCC_UC" : (command & 1172 CARDBUS_VCCMASK) == 1173 CARDBUS_VCC_5V ? "CARDBUS_VCC_5V" : (command & 1174 CARDBUS_VCCMASK) == 1175 CARDBUS_VCC_3V ? "CARDBUS_VCC_3V" : (command & 1176 CARDBUS_VCCMASK) == 1177 CARDBUS_VCC_XV ? "CARDBUS_VCC_XV" : (command & 1178 CARDBUS_VCCMASK) == 1179 CARDBUS_VCC_YV ? "CARDBUS_VCC_YV" : (command & 1180 CARDBUS_VCCMASK) == 1181 CARDBUS_VCC_0V ? "CARDBUS_VCC_0V" : "UNKNOWN", 1182 (command & CARDBUS_VPPMASK) == 1183 CARDBUS_VPP_UC ? "CARDBUS_VPP_UC" : (command & 1184 CARDBUS_VPPMASK) == 1185 CARDBUS_VPP_12V ? "CARDBUS_VPP_12V" : (command & 1186 CARDBUS_VPPMASK) == 1187 CARDBUS_VPP_VCC ? "CARDBUS_VPP_VCC" : (command & 1188 CARDBUS_VPPMASK) == 1189 CARDBUS_VPP_0V ? "CARDBUS_VPP_0V" : "UNKNOWN", command)); 1190 #if 0 1191 if (command == (CARDBUS_VCC_0V | CARDBUS_VPP_0V)) { 1192 u_int32_t force = 1193 bus_space_read_4(memt, memh, CB_SOCKET_FORCE); 1194 /* Reset Bad Vcc request */ 1195 force &= ~CB_SOCKET_FORCE_BADVCC; 1196 bus_space_write_4(memt, memh, CB_SOCKET_FORCE, force); 1197 printf("new status 0x%x\n", bus_space_read_4(memt, memh, 1198 CB_SOCKET_STAT)); 1199 return 1; 1200 } 1201 #endif 1202 return 0; 1203 } 1204 1205 /* 1206 * XXX delay 300 ms: though the standard defines that the Vcc set-up 1207 * time is 20 ms, some PC-Card bridge requires longer duration. 1208 */ 1209 delay(300 * 1000); 1210 1211 return 1; /* power changed correctly */ 1212 } 1213 1214 #if defined CB_PCMCIA_POLL 1215 struct cb_poll_str { 1216 void *arg; 1217 int (*func)(void *); 1218 int level; 1219 pccard_chipset_tag_t ct; 1220 int count; 1221 }; 1222 1223 static struct cb_poll_str cb_poll[10]; 1224 static int cb_poll_n = 0; 1225 static struct timeout cb_poll_timeout; 1226 1227 void cb_pcmcia_poll(void *arg); 1228 1229 void 1230 cb_pcmcia_poll(void *arg) 1231 { 1232 struct cb_poll_str *poll = arg; 1233 struct cbb_pcmcia_softc *psc = (void *)poll->ct->v; 1234 struct pccbb_softc *sc = psc->cpc_parent; 1235 int s; 1236 u_int32_t spsr; /* socket present-state reg */ 1237 1238 timeout_set(&cb_poll_timeout, cb_pcmcia_poll, arg); 1239 timeout_add_msec(&cb_poll_timeout, 1000 / 10); 1240 switch (poll->level) { 1241 case IPL_NET: 1242 s = splnet(); 1243 break; 1244 case IPL_BIO: 1245 s = splbio(); 1246 break; 1247 case IPL_TTY: /* fallthrough */ 1248 default: 1249 s = spltty(); 1250 break; 1251 } 1252 1253 spsr = 1254 bus_space_read_4(sc->sc_base_memt, sc->sc_base_memh, 1255 CB_SOCKET_STAT); 1256 1257 #if defined CB_PCMCIA_POLL_ONLY && defined LEVEL2 1258 if (!(spsr & 0x40)) { /* CINT low */ 1259 #else 1260 if (1) { 1261 #endif 1262 if ((*poll->func) (poll->arg) == 1) { 1263 ++poll->count; 1264 printf("intr: reported from poller, 0x%x\n", spsr); 1265 #if defined LEVEL2 1266 } else { 1267 printf("intr: miss! 0x%x\n", spsr); 1268 #endif 1269 } 1270 } 1271 splx(s); 1272 } 1273 #endif /* defined CB_PCMCIA_POLL */ 1274 1275 /* 1276 * int pccbb_detect_card(struct pccbb_softc *sc) 1277 * return value: 0 if no card exists. 1278 * 1 if 16-bit card exists. 1279 * 2 if cardbus card exists. 1280 */ 1281 int 1282 pccbb_detect_card(struct pccbb_softc *sc) 1283 { 1284 bus_space_handle_t base_memh = sc->sc_base_memh; 1285 bus_space_tag_t base_memt = sc->sc_base_memt; 1286 u_int32_t sockstat = 1287 bus_space_read_4(base_memt, base_memh, CB_SOCKET_STAT); 1288 int retval = 0; 1289 1290 /* 1291 * The SCM Microsystems TI1225-based PCI-CardBus dock card that 1292 * ships with some Lucent WaveLAN cards has only one physical slot 1293 * but OpenBSD probes two. The phantom card in the second slot can 1294 * be ignored by punting on unsupported voltages. 1295 */ 1296 if (sockstat & CB_SOCKET_STAT_XVCARD) 1297 return 0; 1298 1299 /* CD1 and CD2 asserted */ 1300 if (0x00 == (sockstat & CB_SOCKET_STAT_CD)) { 1301 /* card must be present */ 1302 if (!(CB_SOCKET_STAT_NOTCARD & sockstat)) { 1303 /* NOTACARD DEASSERTED */ 1304 if (CB_SOCKET_STAT_CB & sockstat) { 1305 /* CardBus mode */ 1306 retval = 2; 1307 } else if (CB_SOCKET_STAT_16BIT & sockstat) { 1308 /* 16-bit mode */ 1309 retval = 1; 1310 } 1311 } 1312 } 1313 return retval; 1314 } 1315 1316 /* 1317 * int cb_reset(struct pccbb_softc *sc) 1318 * This function resets CardBus card. 1319 */ 1320 int 1321 cb_reset(struct pccbb_softc *sc) 1322 { 1323 /* 1324 * Reset Assert at least 20 ms 1325 * Some machines request longer duration. 1326 */ 1327 int reset_duration = (sc->sc_chipset == CB_RX5C47X ? 400 : 50); 1328 u_int32_t bcr = pci_conf_read(sc->sc_pc, sc->sc_tag, PCI_BCR_INTR); 1329 1330 /* Reset bit Assert (bit 6 at 0x3E) */ 1331 bcr |= CB_BCR_RESET_ENABLE; 1332 pci_conf_write(sc->sc_pc, sc->sc_tag, PCI_BCR_INTR, bcr); 1333 delay_ms(reset_duration, sc); 1334 1335 if (CBB_CARDEXIST & sc->sc_flags) { /* A card exists. Reset it! */ 1336 /* Reset bit Deassert (bit 6 at 0x3E) */ 1337 bcr &= ~CB_BCR_RESET_ENABLE; 1338 pci_conf_write(sc->sc_pc, sc->sc_tag, PCI_BCR_INTR, bcr); 1339 delay_ms(reset_duration, sc); 1340 } 1341 /* No card found on the slot. Keep Reset. */ 1342 return 1; 1343 } 1344 1345 /* 1346 * int cb_detect_voltage(struct pccbb_softc *sc) 1347 * This function detect card Voltage. 1348 */ 1349 int 1350 cb_detect_voltage(struct pccbb_softc *sc) 1351 { 1352 u_int32_t psr; /* socket present-state reg */ 1353 bus_space_tag_t iot = sc->sc_base_memt; 1354 bus_space_handle_t ioh = sc->sc_base_memh; 1355 int vol = PCCARD_VCC_UKN; /* set 0 */ 1356 1357 psr = bus_space_read_4(iot, ioh, CB_SOCKET_STAT); 1358 1359 if (0x400u & psr) { 1360 vol |= PCCARD_VCC_5V; 1361 } 1362 if (0x800u & psr) { 1363 vol |= PCCARD_VCC_3V; 1364 } 1365 1366 return vol; 1367 } 1368 1369 int 1370 cbbprint(void *aux, const char *pcic) 1371 { 1372 /* 1373 struct cbslot_attach_args *cba = aux; 1374 1375 if (cba->cba_slot >= 0) { 1376 printf(" slot %d", cba->cba_slot); 1377 } 1378 */ 1379 return UNCONF; 1380 } 1381 1382 /* 1383 * int pccbb_cardenable(struct pccbb_softc *sc, int function) 1384 * This function enables and disables the card 1385 */ 1386 int 1387 pccbb_cardenable(struct pccbb_softc *sc, int function) 1388 { 1389 u_int32_t command = 1390 pci_conf_read(sc->sc_pc, sc->sc_tag, PCI_COMMAND_STATUS_REG); 1391 1392 DPRINTF(("pccbb_cardenable:")); 1393 switch (function) { 1394 case CARDBUS_IO_ENABLE: 1395 command |= PCI_COMMAND_IO_ENABLE; 1396 break; 1397 case CARDBUS_IO_DISABLE: 1398 command &= ~PCI_COMMAND_IO_ENABLE; 1399 break; 1400 case CARDBUS_MEM_ENABLE: 1401 command |= PCI_COMMAND_MEM_ENABLE; 1402 break; 1403 case CARDBUS_MEM_DISABLE: 1404 command &= ~PCI_COMMAND_MEM_ENABLE; 1405 break; 1406 case CARDBUS_BM_ENABLE: 1407 command |= PCI_COMMAND_MASTER_ENABLE; 1408 break; 1409 case CARDBUS_BM_DISABLE: 1410 command &= ~PCI_COMMAND_MASTER_ENABLE; 1411 break; 1412 default: 1413 return 0; 1414 } 1415 1416 pci_conf_write(sc->sc_pc, sc->sc_tag, PCI_COMMAND_STATUS_REG, command); 1417 DPRINTF((" command reg 0x%x\n", command)); 1418 return 1; 1419 } 1420 1421 /* 1422 * void *pccbb_cb_intr_establish(cardbus_chipset_tag_t ct, 1423 * int irq, 1424 * int level, 1425 * int (* func)(void *), 1426 * void *arg, 1427 * const char *name) 1428 * 1429 * This function registers an interrupt handler at the bridge, in 1430 * order not to call the interrupt handlers of child devices when 1431 * a card-deletion interrupt occurs. 1432 * 1433 * The arguments irq is not used because pccbb selects intr vector. 1434 */ 1435 void * 1436 pccbb_cb_intr_establish(cardbus_chipset_tag_t ct, int irq, int level, 1437 int (*func)(void *), void *arg, const char *name) 1438 { 1439 struct pccbb_softc *sc = (struct pccbb_softc *)ct; 1440 1441 return pccbb_intr_establish(sc, irq, level, func, arg, name); 1442 } 1443 1444 1445 /* 1446 * void *pccbb_cb_intr_disestablish(cardbus_chipset_tag_t ct, 1447 * void *ih) 1448 * 1449 * This function removes an interrupt handler pointed by ih. 1450 */ 1451 void 1452 pccbb_cb_intr_disestablish(cardbus_chipset_tag_t ct, void *ih) 1453 { 1454 struct pccbb_softc *sc = (struct pccbb_softc *)ct; 1455 1456 pccbb_intr_disestablish(sc, ih); 1457 } 1458 1459 1460 /* 1461 * void *pccbb_intr_establish(struct pccbb_softc *sc, 1462 * int irq, 1463 * int level, 1464 * int (* func)(void *), 1465 * void *arg, 1466 * const char *name) 1467 * 1468 * This function registers an interrupt handler at the bridge, in 1469 * order not to call the interrupt handlers of child devices when 1470 * a card-deletion interrupt occurs. 1471 * 1472 * The arguments irq and level are not used. 1473 */ 1474 void * 1475 pccbb_intr_establish(struct pccbb_softc *sc, int irq, int level, 1476 int (*func)(void *), void *arg, const char *name) 1477 { 1478 struct pccbb_intrhand_list *pil, *newpil; 1479 pcireg_t reg; 1480 1481 DPRINTF(("pccbb_intr_establish start. %p\n", sc->sc_pil)); 1482 1483 if (sc->sc_pil == NULL) { 1484 /* initialize bridge intr routing */ 1485 reg = pci_conf_read(sc->sc_pc, sc->sc_tag, PCI_BCR_INTR); 1486 reg &= ~CB_BCR_INTR_IREQ_ENABLE; 1487 pci_conf_write(sc->sc_pc, sc->sc_tag, PCI_BCR_INTR, reg); 1488 1489 switch (sc->sc_chipset) { 1490 case CB_TI113X: 1491 reg = pci_conf_read(sc->sc_pc, sc->sc_tag, PCI_CBCTRL); 1492 /* functional intr enabled */ 1493 reg |= PCI113X_CBCTRL_PCI_INTR; 1494 pci_conf_write(sc->sc_pc, sc->sc_tag, PCI_CBCTRL, reg); 1495 break; 1496 default: 1497 break; 1498 } 1499 } 1500 1501 /* 1502 * Allocate a room for interrupt handler structure. 1503 */ 1504 newpil = (struct pccbb_intrhand_list *) 1505 malloc(sizeof(struct pccbb_intrhand_list), M_DEVBUF, M_WAITOK); 1506 1507 newpil->pil_func = func; 1508 newpil->pil_arg = arg; 1509 newpil->pil_level = level; 1510 evcount_attach(&newpil->pil_count, name, &sc->sc_intrline); 1511 newpil->pil_next = NULL; 1512 1513 if (sc->sc_pil == NULL) { 1514 sc->sc_pil = newpil; 1515 } else { 1516 for (pil = sc->sc_pil; pil->pil_next != NULL; 1517 pil = pil->pil_next); 1518 pil->pil_next = newpil; 1519 } 1520 1521 DPRINTF(("pccbb_intr_establish add pil. %p\n", sc->sc_pil)); 1522 1523 return newpil; 1524 } 1525 1526 /* 1527 * void *pccbb_intr_disestablish(struct pccbb_softc *sc, 1528 * void *ih) 1529 * 1530 * This function removes an interrupt handler pointed by ih. 1531 */ 1532 void 1533 pccbb_intr_disestablish(struct pccbb_softc *sc, void *ih) 1534 { 1535 struct pccbb_intrhand_list *pil, **pil_prev; 1536 pcireg_t reg; 1537 1538 DPRINTF(("pccbb_intr_disestablish start. %p\n", sc->sc_pil)); 1539 1540 pil_prev = &sc->sc_pil; 1541 1542 for (pil = sc->sc_pil; pil != NULL; pil = pil->pil_next) { 1543 if (pil == ih) { 1544 evcount_detach(&pil->pil_count); 1545 *pil_prev = pil->pil_next; 1546 free(pil, M_DEVBUF, sizeof *pil); 1547 DPRINTF(("pccbb_intr_disestablish frees one pil\n")); 1548 break; 1549 } 1550 pil_prev = &pil->pil_next; 1551 } 1552 1553 if (sc->sc_pil == NULL) { 1554 /* No interrupt handlers */ 1555 1556 DPRINTF(("pccbb_intr_disestablish: no interrupt handler\n")); 1557 1558 /* stop routing PCI intr */ 1559 reg = pci_conf_read(sc->sc_pc, sc->sc_tag, PCI_BCR_INTR); 1560 reg |= CB_BCR_INTR_IREQ_ENABLE; 1561 pci_conf_write(sc->sc_pc, sc->sc_tag, PCI_BCR_INTR, reg); 1562 1563 switch (sc->sc_chipset) { 1564 case CB_TI113X: 1565 reg = pci_conf_read(sc->sc_pc, sc->sc_tag, PCI_CBCTRL); 1566 /* functional intr disabled */ 1567 reg &= ~PCI113X_CBCTRL_PCI_INTR; 1568 pci_conf_write(sc->sc_pc, sc->sc_tag, PCI_CBCTRL, reg); 1569 break; 1570 default: 1571 break; 1572 } 1573 } 1574 } 1575 1576 #if defined SHOW_REGS 1577 void 1578 cb_show_regs(pci_chipset_tag_t pc, pcitag_t tag, bus_space_tag_t memt, 1579 bus_space_handle_t memh) 1580 { 1581 int i; 1582 printf("PCI config regs:"); 1583 for (i = 0; i < 0x50; i += 4) { 1584 if (i % 16 == 0) { 1585 printf("\n 0x%02x:", i); 1586 } 1587 printf(" %08x", pci_conf_read(pc, tag, i)); 1588 } 1589 for (i = 0x80; i < 0xb0; i += 4) { 1590 if (i % 16 == 0) { 1591 printf("\n 0x%02x:", i); 1592 } 1593 printf(" %08x", pci_conf_read(pc, tag, i)); 1594 } 1595 1596 if (memh == 0) { 1597 printf("\n"); 1598 return; 1599 } 1600 1601 printf("\nsocket regs:"); 1602 for (i = 0; i <= 0x10; i += 0x04) { 1603 printf(" %08x", bus_space_read_4(memt, memh, i)); 1604 } 1605 printf("\nExCA regs:"); 1606 for (i = 0; i < 0x08; ++i) { 1607 printf(" %02x", bus_space_read_1(memt, memh, 0x800 + i)); 1608 } 1609 printf("\n"); 1610 return; 1611 } 1612 #endif 1613 1614 /* 1615 * int pccbb_pcmcia_io_alloc(pcmcia_chipset_handle_t pch, 1616 * bus_addr_t start, bus_size_t size, 1617 * bus_size_t align, 1618 * struct pcmcia_io_handle *pcihp 1619 * 1620 * This function only allocates I/O region for pccard. This function 1621 * never maps the allocated region to pccard I/O area. 1622 * 1623 * XXX: The interface of this function is not very good, I believe. 1624 */ 1625 int 1626 pccbb_pcmcia_io_alloc(pcmcia_chipset_handle_t pch, bus_addr_t start, 1627 bus_size_t size, bus_size_t align, struct pcmcia_io_handle *pcihp) 1628 { 1629 struct pcic_handle *ph = (struct pcic_handle *)pch; 1630 bus_addr_t ioaddr; 1631 int flags = 0; 1632 bus_space_tag_t iot; 1633 bus_space_handle_t ioh; 1634 bus_addr_t mask; 1635 rbus_tag_t rb; 1636 1637 if (align == 0) { 1638 align = size; /* XXX: funny??? */ 1639 } 1640 1641 if (start != 0) { 1642 /* XXX: assume all card decode lower 10 bits by its hardware */ 1643 mask = 0x3ff; 1644 /* enforce to use only masked address */ 1645 start &= mask; 1646 } else { 1647 /* 1648 * calculate mask: 1649 * 1. get the most significant bit of size (call it msb). 1650 * 2. compare msb with the value of size. 1651 * 3. if size is larger, shift msb left once. 1652 * 4. obtain mask value to decrement msb. 1653 */ 1654 bus_size_t size_tmp = size; 1655 int shifts = 0; 1656 1657 while (size_tmp) { 1658 ++shifts; 1659 size_tmp >>= 1; 1660 } 1661 mask = (1 << shifts); 1662 if (mask < size) { 1663 mask <<= 1; 1664 } 1665 mask--; 1666 } 1667 1668 /* 1669 * Allocate some arbitrary I/O space. 1670 */ 1671 1672 iot = ((struct pccbb_softc *)(ph->ph_parent))->sc_iot; 1673 1674 rb = ((struct pccbb_softc *)(ph->ph_parent))->sc_rbus_iot; 1675 if (rbus_space_alloc(rb, start, size, mask, align, 0, &ioaddr, &ioh)) { 1676 return 1; 1677 } 1678 1679 pcihp->iot = iot; 1680 pcihp->ioh = ioh; 1681 pcihp->addr = ioaddr; 1682 pcihp->size = size; 1683 pcihp->flags = flags; 1684 1685 return 0; 1686 } 1687 1688 /* 1689 * int pccbb_pcmcia_io_free(pcmcia_chipset_handle_t pch, 1690 * struct pcmcia_io_handle *pcihp) 1691 * 1692 * This function only frees I/O region for pccard. 1693 * 1694 * XXX: The interface of this function is not very good, I believe. 1695 */ 1696 void 1697 pccbb_pcmcia_io_free(pcmcia_chipset_handle_t pch, 1698 struct pcmcia_io_handle *pcihp) 1699 { 1700 bus_space_handle_t ioh = pcihp->ioh; 1701 bus_size_t size = pcihp->size; 1702 1703 struct pccbb_softc *sc = 1704 (struct pccbb_softc *)((struct pcic_handle *)pch)->ph_parent; 1705 rbus_tag_t rb = sc->sc_rbus_iot; 1706 1707 rbus_space_free(rb, ioh, size, NULL); 1708 } 1709 1710 /* 1711 * int pccbb_pcmcia_io_map(pcmcia_chipset_handle_t pch, int width, 1712 * bus_addr_t offset, bus_size_t size, 1713 * struct pcmcia_io_handle *pcihp, 1714 * int *windowp) 1715 * 1716 * This function maps the allocated I/O region to pccard. This function 1717 * never allocates any I/O region for pccard I/O area. I don't 1718 * understand why the original authors of pcmciabus separated alloc and 1719 * map. I believe the two must be unite. 1720 * 1721 * XXX: no wait timing control? 1722 */ 1723 int 1724 pccbb_pcmcia_io_map(pcmcia_chipset_handle_t pch, int width, bus_addr_t offset, 1725 bus_size_t size, struct pcmcia_io_handle *pcihp, int *windowp) 1726 { 1727 struct pcic_handle *ph = (struct pcic_handle *)pch; 1728 bus_addr_t ioaddr = pcihp->addr + offset; 1729 int i, win; 1730 #if defined CBB_DEBUG 1731 static char *width_names[] = { "dynamic", "io8", "io16" }; 1732 #endif 1733 1734 /* Sanity check I/O handle. */ 1735 1736 if (((struct pccbb_softc *)ph->ph_parent)->sc_iot != pcihp->iot) { 1737 panic("pccbb_pcmcia_io_map iot is bogus"); 1738 } 1739 1740 /* XXX Sanity check offset/size. */ 1741 1742 win = -1; 1743 for (i = 0; i < PCIC_IO_WINS; i++) { 1744 if ((ph->ioalloc & (1 << i)) == 0) { 1745 win = i; 1746 ph->ioalloc |= (1 << i); 1747 break; 1748 } 1749 } 1750 1751 if (win == -1) { 1752 return 1; 1753 } 1754 1755 *windowp = win; 1756 1757 /* XXX this is pretty gross */ 1758 1759 DPRINTF(("pccbb_pcmcia_io_map window %d %s port %lx+%lx\n", 1760 win, width_names[width], (u_long) ioaddr, (u_long) size)); 1761 1762 /* XXX wtf is this doing here? */ 1763 1764 #if 0 1765 printf(" port 0x%lx", (u_long) ioaddr); 1766 if (size > 1) { 1767 printf("-0x%lx", (u_long) ioaddr + (u_long) size - 1); 1768 } 1769 #endif 1770 1771 ph->io[win].addr = ioaddr; 1772 ph->io[win].size = size; 1773 ph->io[win].width = width; 1774 1775 /* actual dirty register-value changing in the function below. */ 1776 pccbb_pcmcia_do_io_map(ph, win); 1777 1778 return 0; 1779 } 1780 1781 /* 1782 * void pccbb_pcmcia_do_io_map(struct pcic_handle *h, int win) 1783 * 1784 * This function changes register-value to map I/O region for pccard. 1785 */ 1786 void 1787 pccbb_pcmcia_do_io_map(struct pcic_handle *ph, int win) 1788 { 1789 static u_int8_t pcic_iowidth[3] = { 1790 PCIC_IOCTL_IO0_IOCS16SRC_CARD, 1791 PCIC_IOCTL_IO0_IOCS16SRC_DATASIZE | 1792 PCIC_IOCTL_IO0_DATASIZE_8BIT, 1793 PCIC_IOCTL_IO0_IOCS16SRC_DATASIZE | 1794 PCIC_IOCTL_IO0_DATASIZE_16BIT, 1795 }; 1796 1797 #define PCIC_SIA_START_LOW 0 1798 #define PCIC_SIA_START_HIGH 1 1799 #define PCIC_SIA_STOP_LOW 2 1800 #define PCIC_SIA_STOP_HIGH 3 1801 1802 int regbase_win = 0x8 + win * 0x04; 1803 u_int8_t ioctl, enable; 1804 1805 DPRINTF( 1806 ("pccbb_pcmcia_do_io_map win %d addr 0x%lx size 0x%lx width %d\n", 1807 win, (long)ph->io[win].addr, (long)ph->io[win].size, 1808 ph->io[win].width * 8)); 1809 1810 Pcic_write(ph, regbase_win + PCIC_SIA_START_LOW, 1811 ph->io[win].addr & 0xff); 1812 Pcic_write(ph, regbase_win + PCIC_SIA_START_HIGH, 1813 (ph->io[win].addr >> 8) & 0xff); 1814 1815 Pcic_write(ph, regbase_win + PCIC_SIA_STOP_LOW, 1816 (ph->io[win].addr + ph->io[win].size - 1) & 0xff); 1817 Pcic_write(ph, regbase_win + PCIC_SIA_STOP_HIGH, 1818 ((ph->io[win].addr + ph->io[win].size - 1) >> 8) & 0xff); 1819 1820 ioctl = Pcic_read(ph, PCIC_IOCTL); 1821 enable = Pcic_read(ph, PCIC_ADDRWIN_ENABLE); 1822 switch (win) { 1823 case 0: 1824 ioctl &= ~(PCIC_IOCTL_IO0_WAITSTATE | PCIC_IOCTL_IO0_ZEROWAIT | 1825 PCIC_IOCTL_IO0_IOCS16SRC_MASK | 1826 PCIC_IOCTL_IO0_DATASIZE_MASK); 1827 ioctl |= pcic_iowidth[ph->io[win].width]; 1828 enable |= PCIC_ADDRWIN_ENABLE_IO0; 1829 break; 1830 case 1: 1831 ioctl &= ~(PCIC_IOCTL_IO1_WAITSTATE | PCIC_IOCTL_IO1_ZEROWAIT | 1832 PCIC_IOCTL_IO1_IOCS16SRC_MASK | 1833 PCIC_IOCTL_IO1_DATASIZE_MASK); 1834 ioctl |= (pcic_iowidth[ph->io[win].width] << 4); 1835 enable |= PCIC_ADDRWIN_ENABLE_IO1; 1836 break; 1837 } 1838 Pcic_write(ph, PCIC_IOCTL, ioctl); 1839 Pcic_write(ph, PCIC_ADDRWIN_ENABLE, enable); 1840 #if defined CBB_DEBUG 1841 { 1842 u_int8_t start_low = 1843 Pcic_read(ph, regbase_win + PCIC_SIA_START_LOW); 1844 u_int8_t start_high = 1845 Pcic_read(ph, regbase_win + PCIC_SIA_START_HIGH); 1846 u_int8_t stop_low = 1847 Pcic_read(ph, regbase_win + PCIC_SIA_STOP_LOW); 1848 u_int8_t stop_high = 1849 Pcic_read(ph, regbase_win + PCIC_SIA_STOP_HIGH); 1850 printf 1851 (" start %02x %02x, stop %02x %02x, ioctl %02x enable %02x\n", 1852 start_low, start_high, stop_low, stop_high, ioctl, enable); 1853 } 1854 #endif 1855 } 1856 1857 /* 1858 * void pccbb_pcmcia_io_unmap(pcmcia_chipset_handle_t *h, int win) 1859 * 1860 * This function unmaps I/O region. No return value. 1861 */ 1862 void 1863 pccbb_pcmcia_io_unmap(pcmcia_chipset_handle_t pch, int win) 1864 { 1865 struct pcic_handle *ph = (struct pcic_handle *)pch; 1866 int reg; 1867 1868 if (win >= PCIC_IO_WINS || win < 0) { 1869 panic("pccbb_pcmcia_io_unmap: window out of range"); 1870 } 1871 1872 reg = Pcic_read(ph, PCIC_ADDRWIN_ENABLE); 1873 switch (win) { 1874 case 0: 1875 reg &= ~PCIC_ADDRWIN_ENABLE_IO0; 1876 break; 1877 case 1: 1878 reg &= ~PCIC_ADDRWIN_ENABLE_IO1; 1879 break; 1880 } 1881 Pcic_write(ph, PCIC_ADDRWIN_ENABLE, reg); 1882 1883 ph->ioalloc &= ~(1 << win); 1884 } 1885 1886 /* 1887 * void pccbb_pcmcia_wait_ready(struct pcic_handle *ph) 1888 * 1889 * This function enables the card. All information is stored in 1890 * the first argument, pcmcia_chipset_handle_t. 1891 */ 1892 void 1893 pccbb_pcmcia_wait_ready(struct pcic_handle *ph) 1894 { 1895 int i; 1896 1897 DPRINTF(("pccbb_pcmcia_wait_ready: status 0x%02x\n", 1898 Pcic_read(ph, PCIC_IF_STATUS))); 1899 1900 for (i = 0; i < 10000; i++) { 1901 if (Pcic_read(ph, PCIC_IF_STATUS) & PCIC_IF_STATUS_READY) { 1902 return; 1903 } 1904 delay(500); 1905 #ifdef CBB_DEBUG 1906 if ((i > 5000) && (i % 100 == 99)) 1907 printf("."); 1908 #endif 1909 } 1910 1911 #ifdef DIAGNOSTIC 1912 printf("pcic_wait_ready: ready never happened, status = %02x\n", 1913 Pcic_read(ph, PCIC_IF_STATUS)); 1914 #endif 1915 } 1916 1917 /* 1918 * void pccbb_pcmcia_socket_enable(pcmcia_chipset_handle_t pch) 1919 * 1920 * This function enables the card. All information is stored in 1921 * the first argument, pcmcia_chipset_handle_t. 1922 */ 1923 void 1924 pccbb_pcmcia_socket_enable(pcmcia_chipset_handle_t pch) 1925 { 1926 struct pcic_handle *ph = (struct pcic_handle *)pch; 1927 struct pccbb_softc *sc = (struct pccbb_softc *)ph->ph_parent; 1928 int cardtype, win; 1929 u_int8_t power, intr; 1930 pcireg_t spsr; 1931 int voltage; 1932 1933 /* this bit is mostly stolen from pcic_attach_card */ 1934 1935 DPRINTF(("pccbb_pcmcia_socket_enable: ")); 1936 1937 /* get card Vcc info */ 1938 1939 spsr = 1940 bus_space_read_4(sc->sc_base_memt, sc->sc_base_memh, 1941 CB_SOCKET_STAT); 1942 if (spsr & CB_SOCKET_STAT_5VCARD) { 1943 DPRINTF(("5V card\n")); 1944 voltage = CARDBUS_VCC_5V | CARDBUS_VPP_VCC; 1945 } else if (spsr & CB_SOCKET_STAT_3VCARD) { 1946 DPRINTF(("3V card\n")); 1947 voltage = CARDBUS_VCC_3V | CARDBUS_VPP_VCC; 1948 } else { 1949 DPRINTF(("?V card, 0x%x\n", spsr)); /* XXX */ 1950 return; 1951 } 1952 1953 /* disable socket i/o: negate output enable bit */ 1954 1955 power = 0; 1956 Pcic_write(ph, PCIC_PWRCTL, power); 1957 1958 /* power down the socket to reset it, clear the card reset pin */ 1959 1960 pccbb_power((cardbus_chipset_tag_t)sc, CARDBUS_VCC_0V | CARDBUS_VPP_0V); 1961 1962 /* 1963 * wait 200ms until power fails (Tpf). Then, wait 100ms since 1964 * we are changing Vcc (Toff). 1965 */ 1966 /* delay(300*1000); too much */ 1967 1968 /* assert reset bit */ 1969 intr = Pcic_read(ph, PCIC_INTR); 1970 intr &= ~(PCIC_INTR_RESET | PCIC_INTR_CARDTYPE_MASK); 1971 Pcic_write(ph, PCIC_INTR, intr); 1972 1973 /* Power up the socket. */ 1974 power = Pcic_read(ph, PCIC_PWRCTL); 1975 Pcic_write(ph, PCIC_PWRCTL, (power & ~PCIC_PWRCTL_OE)); 1976 pccbb_power((cardbus_chipset_tag_t)sc, voltage); 1977 1978 /* Now output enable */ 1979 power = Pcic_read(ph, PCIC_PWRCTL); 1980 Pcic_write(ph, PCIC_PWRCTL, power | PCIC_PWRCTL_OE); 1981 1982 /* 1983 * hold RESET at least 10us. 1984 */ 1985 delay(10); 1986 delay(2 * 1000); /* XXX: TI1130 requires it. */ 1987 delay(20 * 1000); /* XXX: TI1130 requires it. */ 1988 1989 /* clear the reset flag */ 1990 1991 intr |= PCIC_INTR_RESET; 1992 Pcic_write(ph, PCIC_INTR, intr); 1993 1994 /* wait 20ms as per pc card standard (r2.01) section 4.3.6 */ 1995 1996 delay(20000); 1997 1998 /* wait for the chip to finish initializing */ 1999 2000 pccbb_pcmcia_wait_ready(ph); 2001 2002 /* zero out the address windows */ 2003 2004 Pcic_write(ph, PCIC_ADDRWIN_ENABLE, 0); 2005 2006 /* set the card type */ 2007 2008 cardtype = pcmcia_card_gettype(ph->pcmcia); 2009 2010 intr |= ((cardtype == PCMCIA_IFTYPE_IO) ? 2011 PCIC_INTR_CARDTYPE_IO : PCIC_INTR_CARDTYPE_MEM); 2012 Pcic_write(ph, PCIC_INTR, intr); 2013 2014 DPRINTF(("%s: pccbb_pcmcia_socket_enable %02x cardtype %s %02x\n", 2015 ph->ph_parent->dv_xname, ph->sock, 2016 ((cardtype == PCMCIA_IFTYPE_IO) ? "io" : "mem"), intr)); 2017 2018 /* reinstall all the memory and io mappings */ 2019 2020 for (win = 0; win < PCIC_MEM_WINS; ++win) { 2021 if (ph->memalloc & (1 << win)) { 2022 pccbb_pcmcia_do_mem_map(ph, win); 2023 } 2024 } 2025 2026 for (win = 0; win < PCIC_IO_WINS; ++win) { 2027 if (ph->ioalloc & (1 << win)) { 2028 pccbb_pcmcia_do_io_map(ph, win); 2029 } 2030 } 2031 } 2032 2033 /* 2034 * void pccbb_pcmcia_socket_disable(pcmcia_chipset_handle_t *ph) 2035 * 2036 * This function disables the card. All information is stored in 2037 * the first argument, pcmcia_chipset_handle_t. 2038 */ 2039 void 2040 pccbb_pcmcia_socket_disable(pcmcia_chipset_handle_t pch) 2041 { 2042 struct pcic_handle *ph = (struct pcic_handle *)pch; 2043 struct pccbb_softc *sc = (struct pccbb_softc *)ph->ph_parent; 2044 u_int8_t power, intr; 2045 2046 DPRINTF(("pccbb_pcmcia_socket_disable\n")); 2047 2048 /* reset signal asserting... */ 2049 2050 intr = Pcic_read(ph, PCIC_INTR); 2051 intr &= ~(PCIC_INTR_CARDTYPE_MASK); 2052 Pcic_write(ph, PCIC_INTR, intr); 2053 delay(2 * 1000); 2054 2055 /* power down the socket */ 2056 power = Pcic_read(ph, PCIC_PWRCTL); 2057 power &= ~PCIC_PWRCTL_OE; 2058 Pcic_write(ph, PCIC_PWRCTL, power); 2059 pccbb_power((cardbus_chipset_tag_t)sc, CARDBUS_VCC_0V | CARDBUS_VPP_0V); 2060 /* 2061 * wait 300ms until power fails (Tpf). 2062 */ 2063 delay(300 * 1000); 2064 } 2065 2066 /* 2067 * int pccbb_pcmcia_card_detect(pcmcia_chipset_handle_t *ph) 2068 * 2069 * This function detects whether a card is in the slot or not. 2070 * If a card is inserted, return 1. Otherwise, return 0. 2071 */ 2072 int 2073 pccbb_pcmcia_card_detect(pcmcia_chipset_handle_t pch) 2074 { 2075 struct pcic_handle *ph = (struct pcic_handle *)pch; 2076 struct pccbb_softc *sc = (struct pccbb_softc *)ph->ph_parent; 2077 2078 DPRINTF(("pccbb_pcmcia_card_detect\n")); 2079 return pccbb_detect_card(sc) == 1 ? 1 : 0; 2080 } 2081 2082 /* 2083 * int pccbb_pcmcia_mem_alloc(pcmcia_chipset_handle_t pch, 2084 * bus_size_t size, 2085 * struct pcmcia_mem_handle *pcmhp) 2086 * 2087 * This function only allocates memory region for pccard. This 2088 * function never maps the allocated region to pccard memory area. 2089 * 2090 * XXX: Why the argument of start address is not in? 2091 */ 2092 int 2093 pccbb_pcmcia_mem_alloc(pcmcia_chipset_handle_t pch, bus_size_t size, 2094 struct pcmcia_mem_handle *pcmhp) 2095 { 2096 struct pcic_handle *ph = (struct pcic_handle *)pch; 2097 bus_space_handle_t memh; 2098 bus_addr_t addr; 2099 bus_size_t sizepg; 2100 struct pccbb_softc *sc = (struct pccbb_softc *)ph->ph_parent; 2101 rbus_tag_t rb; 2102 2103 /* out of sc->memh, allocate as many pages as necessary */ 2104 2105 /* convert size to PCIC pages */ 2106 /* 2107 * This is not enough; when the requested region is on the page 2108 * boundaries, this may calculate wrong result. 2109 */ 2110 sizepg = (size + (PCIC_MEM_PAGESIZE - 1)) / PCIC_MEM_PAGESIZE; 2111 #if 0 2112 if (sizepg > PCIC_MAX_MEM_PAGES) { 2113 return 1; 2114 } 2115 #endif 2116 2117 if (!(sc->sc_pcmcia_flags & PCCBB_PCMCIA_MEM_32)) { 2118 return 1; 2119 } 2120 2121 addr = 0; /* XXX gcc -Wuninitialized */ 2122 2123 rb = sc->sc_rbus_memt; 2124 if (rbus_space_alloc(rb, 0, sizepg * PCIC_MEM_PAGESIZE, 2125 sizepg * PCIC_MEM_PAGESIZE - 1, PCIC_MEM_PAGESIZE, 0, 2126 &addr, &memh)) { 2127 return 1; 2128 } 2129 2130 DPRINTF( 2131 ("pccbb_pcmcia_alloc_mem: addr 0x%lx size 0x%lx, realsize 0x%lx\n", 2132 addr, size, sizepg * PCIC_MEM_PAGESIZE)); 2133 2134 pcmhp->memt = sc->sc_memt; 2135 pcmhp->memh = memh; 2136 pcmhp->addr = addr; 2137 pcmhp->size = size; 2138 pcmhp->realsize = sizepg * PCIC_MEM_PAGESIZE; 2139 /* What is mhandle? I feel it is very dirty and it must go trush. */ 2140 pcmhp->mhandle = 0; 2141 /* No offset??? Funny. */ 2142 2143 return 0; 2144 } 2145 2146 /* 2147 * void pccbb_pcmcia_mem_free(pcmcia_chipset_handle_t pch, 2148 * struct pcmcia_mem_handle *pcmhp) 2149 * 2150 * This function release the memory space allocated by the function 2151 * pccbb_pcmcia_mem_alloc(). 2152 */ 2153 void 2154 pccbb_pcmcia_mem_free(pcmcia_chipset_handle_t pch, 2155 struct pcmcia_mem_handle *pcmhp) 2156 { 2157 struct pcic_handle *ph = (struct pcic_handle *)pch; 2158 struct pccbb_softc *sc = (struct pccbb_softc *)ph->ph_parent; 2159 2160 rbus_space_free(sc->sc_rbus_memt, pcmhp->memh, pcmhp->realsize, NULL); 2161 } 2162 2163 /* 2164 * void pccbb_pcmcia_do_mem_map(struct pcic_handle *ph, int win) 2165 * 2166 * This function release the memory space allocated by the function 2167 * pccbb_pcmcia_mem_alloc(). 2168 */ 2169 void 2170 pccbb_pcmcia_do_mem_map(struct pcic_handle *ph, int win) 2171 { 2172 int regbase_win; 2173 bus_addr_t phys_addr; 2174 bus_addr_t phys_end; 2175 2176 #define PCIC_SMM_START_LOW 0 2177 #define PCIC_SMM_START_HIGH 1 2178 #define PCIC_SMM_STOP_LOW 2 2179 #define PCIC_SMM_STOP_HIGH 3 2180 #define PCIC_CMA_LOW 4 2181 #define PCIC_CMA_HIGH 5 2182 2183 u_int8_t start_low, start_high = 0; 2184 u_int8_t stop_low, stop_high; 2185 u_int8_t off_low, off_high; 2186 u_int8_t mem_window; 2187 int reg; 2188 2189 regbase_win = 0x10 + win * 0x08; 2190 2191 phys_addr = ph->mem[win].addr; 2192 phys_end = phys_addr + ph->mem[win].size; 2193 2194 DPRINTF(("pccbb_pcmcia_do_mem_map: start 0x%lx end 0x%lx off 0x%lx\n", 2195 phys_addr, phys_end, ph->mem[win].offset)); 2196 2197 #define PCIC_MEMREG_LSB_SHIFT PCIC_SYSMEM_ADDRX_SHIFT 2198 #define PCIC_MEMREG_MSB_SHIFT (PCIC_SYSMEM_ADDRX_SHIFT + 8) 2199 #define PCIC_MEMREG_WIN_SHIFT (PCIC_SYSMEM_ADDRX_SHIFT + 12) 2200 2201 /* bit 19:12 */ 2202 start_low = (phys_addr >> PCIC_MEMREG_LSB_SHIFT) & 0xff; 2203 /* bit 23:20 and bit 7 on */ 2204 start_high = ((phys_addr >> PCIC_MEMREG_MSB_SHIFT) & 0x0f) 2205 | PCIC_SYSMEM_ADDRX_START_MSB_DATASIZE_16BIT; /* bit 7 on */ 2206 /* bit 31:24, for 32-bit address */ 2207 mem_window = (phys_addr >> PCIC_MEMREG_WIN_SHIFT) & 0xff; 2208 2209 Pcic_write(ph, regbase_win + PCIC_SMM_START_LOW, start_low); 2210 Pcic_write(ph, regbase_win + PCIC_SMM_START_HIGH, start_high); 2211 2212 if (((struct pccbb_softc *)ph-> 2213 ph_parent)->sc_pcmcia_flags & PCCBB_PCMCIA_MEM_32) { 2214 Pcic_write(ph, 0x40 + win, mem_window); 2215 } 2216 2217 stop_low = (phys_end >> PCIC_MEMREG_LSB_SHIFT) & 0xff; 2218 stop_high = ((phys_end >> PCIC_MEMREG_MSB_SHIFT) & 0x0f) 2219 | PCIC_SYSMEM_ADDRX_STOP_MSB_WAIT2; /* wait 2 cycles */ 2220 /* XXX Geee, WAIT2!! Crazy!! I must rewrite this routine. */ 2221 2222 Pcic_write(ph, regbase_win + PCIC_SMM_STOP_LOW, stop_low); 2223 Pcic_write(ph, regbase_win + PCIC_SMM_STOP_HIGH, stop_high); 2224 2225 off_low = (ph->mem[win].offset >> PCIC_CARDMEM_ADDRX_SHIFT) & 0xff; 2226 off_high = ((ph->mem[win].offset >> (PCIC_CARDMEM_ADDRX_SHIFT + 8)) 2227 & PCIC_CARDMEM_ADDRX_MSB_ADDR_MASK) 2228 | ((ph->mem[win].kind == PCMCIA_MEM_ATTR) ? 2229 PCIC_CARDMEM_ADDRX_MSB_REGACTIVE_ATTR : 0); 2230 2231 Pcic_write(ph, regbase_win + PCIC_CMA_LOW, off_low); 2232 Pcic_write(ph, regbase_win + PCIC_CMA_HIGH, off_high); 2233 2234 reg = Pcic_read(ph, PCIC_ADDRWIN_ENABLE); 2235 reg |= ((1 << win) | PCIC_ADDRWIN_ENABLE_MEMCS16); 2236 Pcic_write(ph, PCIC_ADDRWIN_ENABLE, reg); 2237 2238 #if defined CBB_DEBUG 2239 { 2240 int r1, r2, r3, r4, r5, r6, r7 = 0; 2241 2242 r1 = Pcic_read(ph, regbase_win + PCIC_SMM_START_LOW); 2243 r2 = Pcic_read(ph, regbase_win + PCIC_SMM_START_HIGH); 2244 r3 = Pcic_read(ph, regbase_win + PCIC_SMM_STOP_LOW); 2245 r4 = Pcic_read(ph, regbase_win + PCIC_SMM_STOP_HIGH); 2246 r5 = Pcic_read(ph, regbase_win + PCIC_CMA_LOW); 2247 r6 = Pcic_read(ph, regbase_win + PCIC_CMA_HIGH); 2248 if (((struct pccbb_softc *)(ph-> 2249 ph_parent))->sc_pcmcia_flags & PCCBB_PCMCIA_MEM_32) { 2250 r7 = Pcic_read(ph, 0x40 + win); 2251 } 2252 2253 DPRINTF(("pccbb_pcmcia_do_mem_map window %d: %02x%02x %02x%02x " 2254 "%02x%02x", win, r1, r2, r3, r4, r5, r6)); 2255 if (((struct pccbb_softc *)(ph-> 2256 ph_parent))->sc_pcmcia_flags & PCCBB_PCMCIA_MEM_32) { 2257 DPRINTF((" %02x", r7)); 2258 } 2259 DPRINTF(("\n")); 2260 } 2261 #endif 2262 } 2263 2264 /* 2265 * int pccbb_pcmcia_mem_map(pcmcia_chipset_handle_t pch, int kind, 2266 * bus_addr_t card_addr, bus_size_t size, 2267 * struct pcmcia_mem_handle *pcmhp, 2268 * bus_size_t *offsetp, int *windowp) 2269 * 2270 * This function maps memory space allocated by the function 2271 * pccbb_pcmcia_mem_alloc(). 2272 */ 2273 int 2274 pccbb_pcmcia_mem_map(pcmcia_chipset_handle_t pch, int kind, 2275 bus_addr_t card_addr, bus_size_t size, struct pcmcia_mem_handle *pcmhp, 2276 bus_size_t *offsetp, int *windowp) 2277 { 2278 struct pcic_handle *ph = (struct pcic_handle *)pch; 2279 bus_addr_t busaddr; 2280 long card_offset; 2281 int win; 2282 2283 for (win = 0; win < PCIC_MEM_WINS; ++win) { 2284 if ((ph->memalloc & (1 << win)) == 0) { 2285 ph->memalloc |= (1 << win); 2286 break; 2287 } 2288 } 2289 2290 if (win == PCIC_MEM_WINS) { 2291 return 1; 2292 } 2293 2294 *windowp = win; 2295 2296 /* XXX this is pretty gross */ 2297 2298 if (((struct pccbb_softc *)ph->ph_parent)->sc_memt != pcmhp->memt) { 2299 panic("pccbb_pcmcia_mem_map memt is bogus"); 2300 } 2301 2302 busaddr = pcmhp->addr; 2303 2304 /* 2305 * compute the address offset to the pcmcia address space for the 2306 * pcic. this is intentionally signed. The masks and shifts below 2307 * will cause TRT to happen in the pcic registers. Deal with making 2308 * sure the address is aligned, and return the alignment offset. 2309 */ 2310 2311 *offsetp = card_addr % PCIC_MEM_PAGESIZE; 2312 card_addr -= *offsetp; 2313 2314 DPRINTF(("pccbb_pcmcia_mem_map window %d bus %lx+%lx+%lx at card addr " 2315 "%lx\n", win, (u_long) busaddr, (u_long) * offsetp, (u_long) size, 2316 (u_long) card_addr)); 2317 2318 /* 2319 * include the offset in the size, and decrement size by one, since 2320 * the hw wants start/stop 2321 */ 2322 size += *offsetp - 1; 2323 2324 card_offset = (((long)card_addr) - ((long)busaddr)); 2325 2326 ph->mem[win].addr = busaddr; 2327 ph->mem[win].size = size; 2328 ph->mem[win].offset = card_offset; 2329 ph->mem[win].kind = kind; 2330 2331 pccbb_pcmcia_do_mem_map(ph, win); 2332 2333 return 0; 2334 } 2335 2336 /* 2337 * int pccbb_pcmcia_mem_unmap(pcmcia_chipset_handle_t pch, 2338 * int window) 2339 * 2340 * This function unmaps memory space which mapped by the function 2341 * pccbb_pcmcia_mem_map(). 2342 */ 2343 void 2344 pccbb_pcmcia_mem_unmap(pcmcia_chipset_handle_t pch, int window) 2345 { 2346 struct pcic_handle *ph = (struct pcic_handle *)pch; 2347 int reg; 2348 2349 if (window >= PCIC_MEM_WINS) { 2350 panic("pccbb_pcmcia_mem_unmap: window out of range"); 2351 } 2352 2353 reg = Pcic_read(ph, PCIC_ADDRWIN_ENABLE); 2354 reg &= ~(1 << window); 2355 Pcic_write(ph, PCIC_ADDRWIN_ENABLE, reg); 2356 2357 ph->memalloc &= ~(1 << window); 2358 } 2359 2360 #if defined PCCBB_PCMCIA_POLL 2361 struct pccbb_poll_str { 2362 void *arg; 2363 int (*func)(void *); 2364 int level; 2365 struct pcic_handle *ph; 2366 int count; 2367 int num; 2368 }; 2369 2370 static struct pccbb_poll_str pccbb_poll[10]; 2371 static int pccbb_poll_n = 0; 2372 static struct timeout pccbb_poll_timeout; 2373 2374 void pccbb_pcmcia_poll(void *arg); 2375 2376 void 2377 pccbb_pcmcia_poll(void *arg) 2378 { 2379 struct pccbb_poll_str *poll = arg; 2380 struct pcic_handle *ph = poll->ph; 2381 struct pccbb_softc *sc = ph->sc; 2382 int s; 2383 u_int32_t spsr; /* socket present-state reg */ 2384 2385 timeout_set(&pccbb_poll_timeout, pccbb_pcmcia_poll, arg); 2386 timeout_add_sec(&pccbb_poll_timeout, 2); 2387 switch (poll->level) { 2388 case IPL_NET: 2389 s = splnet(); 2390 break; 2391 case IPL_BIO: 2392 s = splbio(); 2393 break; 2394 case IPL_TTY: /* fallthrough */ 2395 default: 2396 s = spltty(); 2397 break; 2398 } 2399 2400 spsr = 2401 bus_space_read_4(sc->sc_base_memt, sc->sc_base_memh, 2402 CB_SOCKET_STAT); 2403 2404 #if defined PCCBB_PCMCIA_POLL_ONLY && defined LEVEL2 2405 if (!(spsr & 0x40)) /* CINT low */ 2406 #else 2407 if (1) 2408 #endif 2409 { 2410 if ((*poll->func) (poll->arg) > 0) { 2411 ++poll->count; 2412 /* printf("intr: reported from poller, 0x%x\n", spsr); */ 2413 #if defined LEVEL2 2414 } else { 2415 printf("intr: miss! 0x%x\n", spsr); 2416 #endif 2417 } 2418 } 2419 splx(s); 2420 } 2421 #endif /* defined CB_PCMCIA_POLL */ 2422 2423 /* 2424 * void *pccbb_pcmcia_intr_establish(pcmcia_chipset_handle_t pch, 2425 * struct pcmcia_function *pf, 2426 * int ipl, 2427 * int (*func)(void *), 2428 * void *arg); 2429 * 2430 * This function enables PC-Card interrupt. PCCBB uses PCI interrupt line. 2431 */ 2432 void * 2433 pccbb_pcmcia_intr_establish(pcmcia_chipset_handle_t pch, 2434 struct pcmcia_function *pf, int ipl, int (*func)(void *), void *arg, 2435 char *xname) 2436 { 2437 struct pcic_handle *ph = (struct pcic_handle *)pch; 2438 struct pccbb_softc *sc = (struct pccbb_softc *)ph->ph_parent; 2439 2440 if (!(pf->cfe->flags & PCMCIA_CFE_IRQLEVEL)) { 2441 /* what should I do? */ 2442 if ((pf->cfe->flags & PCMCIA_CFE_IRQLEVEL)) { 2443 DPRINTF( 2444 ("%s does not provide edge nor pulse interrupt\n", 2445 sc->sc_dev.dv_xname)); 2446 return NULL; 2447 } 2448 /* 2449 * XXX Noooooo! The interrupt flag must set properly!! 2450 * dumb pcmcia driver!! 2451 */ 2452 } 2453 2454 return pccbb_intr_establish(sc, -1, ipl, func, arg, xname); 2455 } 2456 2457 /* 2458 * void pccbb_pcmcia_intr_disestablish(pcmcia_chipset_handle_t pch, 2459 * void *ih) 2460 * 2461 * This function disables PC-Card interrupt. 2462 */ 2463 void 2464 pccbb_pcmcia_intr_disestablish(pcmcia_chipset_handle_t pch, void *ih) 2465 { 2466 struct pcic_handle *ph = (struct pcic_handle *)pch; 2467 struct pccbb_softc *sc = (struct pccbb_softc *)ph->ph_parent; 2468 2469 pccbb_intr_disestablish(sc, ih); 2470 } 2471 2472 const char * 2473 pccbb_pcmcia_intr_string(pcmcia_chipset_handle_t pch, void *ih) 2474 { 2475 if (ih == NULL) 2476 return "couldn't establish interrupt"; 2477 else 2478 return ""; /* card shares interrupt of the bridge */ 2479 } 2480 2481 /* 2482 * int 2483 * pccbb_rbus_cb_space_alloc(cardbus_chipset_tag_t ct, rbus_tag_t rb, 2484 * bus_addr_t addr, bus_size_t size, 2485 * bus_addr_t mask, bus_size_t align, 2486 * int flags, bus_addr_t *addrp; 2487 * bus_space_handle_t *bshp) 2488 * 2489 * This function allocates a portion of memory or io space for 2490 * clients. This function is called from CardBus card drivers. 2491 */ 2492 int 2493 pccbb_rbus_cb_space_alloc(cardbus_chipset_tag_t ct, rbus_tag_t rb, 2494 bus_addr_t addr, bus_size_t size, bus_addr_t mask, bus_size_t align, 2495 int flags, bus_addr_t *addrp, bus_space_handle_t *bshp) 2496 { 2497 struct pccbb_softc *sc = (struct pccbb_softc *)ct; 2498 2499 DPRINTF( 2500 ("pccbb_rbus_cb_space_alloc: adr %lx, size %lx, mask %lx, align %lx\n", 2501 addr, size, mask, align)); 2502 2503 align = max(align, 4); 2504 mask = max(mask, (4 - 1)); 2505 if (rb->rb_bt == sc->sc_memt) { 2506 align = max(align, 0x1000); 2507 mask = max(mask, (0x1000 - 1)); 2508 } 2509 2510 if (rb->rb_bt == sc->sc_iot) { 2511 /* XXX: hack for avoiding ISA image */ 2512 if (mask < 0x0100) { 2513 mask = 0x3ff; 2514 addr = 0x300; 2515 } 2516 } 2517 2518 if (rbus_space_alloc(rb, addr, size, mask, align, flags, addrp, bshp)) { 2519 printf("%s: <rbus> no bus space\n", sc->sc_dev.dv_xname); 2520 return 1; 2521 } 2522 2523 pccbb_open_win(sc, rb->rb_bt, *addrp, size, *bshp, 0); 2524 2525 return 0; 2526 } 2527 2528 /* 2529 * int 2530 * pccbb_rbus_cb_space_free(cardbus_chipset_tag_t *ct, rbus_tag_t rb, 2531 * bus_space_handle_t *bshp, bus_size_t size); 2532 * 2533 * This function is called from CardBus card drivers. 2534 */ 2535 int 2536 pccbb_rbus_cb_space_free(cardbus_chipset_tag_t ct, rbus_tag_t rb, 2537 bus_space_handle_t bsh, bus_size_t size) 2538 { 2539 struct pccbb_softc *sc = (struct pccbb_softc *)ct; 2540 bus_space_tag_t bt = rb->rb_bt; 2541 2542 pccbb_close_win(sc, bt, bsh, size); 2543 2544 if (bt == sc->sc_memt) { 2545 } else if (bt == sc->sc_iot) { 2546 } else { 2547 return 1; 2548 /* XXX: panic here? */ 2549 } 2550 2551 return rbus_space_free(rb, bsh, size, NULL); 2552 } 2553 2554 int 2555 pccbb_open_win(struct pccbb_softc *sc, bus_space_tag_t bst, bus_addr_t addr, 2556 bus_size_t size, bus_space_handle_t bsh, int flags) 2557 { 2558 struct pccbb_win_chain_head *head; 2559 bus_addr_t align; 2560 2561 head = &sc->sc_iowindow; 2562 align = 0x04; 2563 if (sc->sc_memt == bst) { 2564 head = &sc->sc_memwindow; 2565 align = 0x1000; 2566 DPRINTF(("using memory window, %x %x %x\n\n", 2567 sc->sc_iot, sc->sc_memt, bst)); 2568 } 2569 2570 if (pccbb_winlist_insert(head, addr, size, bsh, flags)) { 2571 printf("%s: pccbb_open_win: %s winlist insert failed\n", 2572 sc->sc_dev.dv_xname, 2573 (head == &sc->sc_memwindow) ? "mem" : "io"); 2574 } 2575 pccbb_winset(align, sc, bst); 2576 2577 return 0; 2578 } 2579 2580 int 2581 pccbb_close_win(struct pccbb_softc *sc, bus_space_tag_t bst, 2582 bus_space_handle_t bsh, bus_size_t size) 2583 { 2584 struct pccbb_win_chain_head *head; 2585 bus_addr_t align; 2586 2587 head = &sc->sc_iowindow; 2588 align = 0x04; 2589 if (sc->sc_memt == bst) { 2590 head = &sc->sc_memwindow; 2591 align = 0x1000; 2592 } 2593 2594 if (pccbb_winlist_delete(head, bsh, size)) { 2595 printf("%s: pccbb_close_win: %s winlist delete failed\n", 2596 sc->sc_dev.dv_xname, 2597 (head == &sc->sc_memwindow) ? "mem" : "io"); 2598 } 2599 pccbb_winset(align, sc, bst); 2600 2601 return 0; 2602 } 2603 2604 int 2605 pccbb_winlist_insert(struct pccbb_win_chain_head *head, bus_addr_t start, 2606 bus_size_t size, bus_space_handle_t bsh, int flags) 2607 { 2608 struct pccbb_win_chain *chainp, *elem; 2609 2610 if ((elem = malloc(sizeof(struct pccbb_win_chain), M_DEVBUF, 2611 M_NOWAIT)) == NULL) 2612 return (1); /* fail */ 2613 2614 elem->wc_start = start; 2615 elem->wc_end = start + (size - 1); 2616 elem->wc_handle = bsh; 2617 elem->wc_flags = flags; 2618 2619 for (chainp = TAILQ_FIRST(head); chainp != NULL; 2620 chainp = TAILQ_NEXT(chainp, wc_list)) { 2621 if (chainp->wc_end < start) 2622 continue; 2623 TAILQ_INSERT_AFTER(head, chainp, elem, wc_list); 2624 return (0); 2625 } 2626 2627 TAILQ_INSERT_TAIL(head, elem, wc_list); 2628 return (0); 2629 } 2630 2631 int 2632 pccbb_winlist_delete(struct pccbb_win_chain_head *head, bus_space_handle_t bsh, 2633 bus_size_t size) 2634 { 2635 struct pccbb_win_chain *chainp; 2636 2637 for (chainp = TAILQ_FIRST(head); chainp != NULL; 2638 chainp = TAILQ_NEXT(chainp, wc_list)) { 2639 if (memcmp(&chainp->wc_handle, &bsh, sizeof(bsh))) 2640 continue; 2641 if ((chainp->wc_end - chainp->wc_start) != (size - 1)) { 2642 printf("pccbb_winlist_delete: window 0x%lx size " 2643 "inconsistent: 0x%lx, 0x%lx\n", 2644 chainp->wc_start, 2645 chainp->wc_end - chainp->wc_start, 2646 size - 1); 2647 return 1; 2648 } 2649 2650 TAILQ_REMOVE(head, chainp, wc_list); 2651 free(chainp, M_DEVBUF, sizeof *chainp); 2652 2653 return 0; 2654 } 2655 2656 return 1; /* fail: no candidate to remove */ 2657 } 2658 2659 void 2660 pccbb_winset(bus_addr_t align, struct pccbb_softc *sc, bus_space_tag_t bst) 2661 { 2662 pci_chipset_tag_t pc; 2663 pcitag_t tag; 2664 bus_addr_t mask = ~(align - 1); 2665 struct { 2666 pcireg_t win_start; 2667 pcireg_t win_limit; 2668 int win_flags; 2669 } win[2]; 2670 struct pccbb_win_chain *chainp; 2671 int offs; 2672 2673 win[0].win_start = win[1].win_start = 0xffffffff; 2674 win[0].win_limit = win[1].win_limit = 0; 2675 win[0].win_flags = win[1].win_flags = 0; 2676 2677 chainp = TAILQ_FIRST(&sc->sc_iowindow); 2678 offs = PCI_CB_IOBASE0; 2679 if (sc->sc_memt == bst) { 2680 chainp = TAILQ_FIRST(&sc->sc_memwindow); 2681 offs = PCI_CB_MEMBASE0; 2682 } 2683 2684 if (chainp != NULL) { 2685 win[0].win_start = chainp->wc_start & mask; 2686 win[0].win_limit = chainp->wc_end & mask; 2687 win[0].win_flags = chainp->wc_flags; 2688 chainp = TAILQ_NEXT(chainp, wc_list); 2689 } 2690 2691 for (; chainp != NULL; chainp = TAILQ_NEXT(chainp, wc_list)) { 2692 if (win[1].win_start == 0xffffffff) { 2693 /* window 1 is not used */ 2694 if ((win[0].win_flags == chainp->wc_flags) && 2695 (win[0].win_limit + align >= 2696 (chainp->wc_start & mask))) { 2697 /* concatenate */ 2698 win[0].win_limit = chainp->wc_end & mask; 2699 } else { 2700 /* make new window */ 2701 win[1].win_start = chainp->wc_start & mask; 2702 win[1].win_limit = chainp->wc_end & mask; 2703 win[1].win_flags = chainp->wc_flags; 2704 } 2705 continue; 2706 } 2707 2708 /* Both windows are engaged. */ 2709 if (win[0].win_flags == win[1].win_flags) { 2710 /* same flags */ 2711 if (win[0].win_flags == chainp->wc_flags) { 2712 if (win[1].win_start - (win[0].win_limit + 2713 align) < 2714 (chainp->wc_start & mask) - 2715 ((chainp->wc_end & mask) + align)) { 2716 /* 2717 * merge window 0 and 1, and set win1 2718 * to chainp 2719 */ 2720 win[0].win_limit = win[1].win_limit; 2721 win[1].win_start = 2722 chainp->wc_start & mask; 2723 win[1].win_limit = 2724 chainp->wc_end & mask; 2725 } else { 2726 win[1].win_limit = 2727 chainp->wc_end & mask; 2728 } 2729 } else { 2730 /* different flags */ 2731 2732 /* concatenate win0 and win1 */ 2733 win[0].win_limit = win[1].win_limit; 2734 /* allocate win[1] to new space */ 2735 win[1].win_start = chainp->wc_start & mask; 2736 win[1].win_limit = chainp->wc_end & mask; 2737 win[1].win_flags = chainp->wc_flags; 2738 } 2739 } else { 2740 /* the flags of win[0] and win[1] are different */ 2741 if (win[0].win_flags == chainp->wc_flags) { 2742 win[0].win_limit = chainp->wc_end & mask; 2743 /* 2744 * XXX this creates overlapping windows, so 2745 * what should the poor bridge do if one is 2746 * cachable, and the other is not? 2747 */ 2748 printf("%s: overlapping windows\n", 2749 sc->sc_dev.dv_xname); 2750 } else { 2751 win[1].win_limit = chainp->wc_end & mask; 2752 } 2753 } 2754 } 2755 2756 pc = sc->sc_pc; 2757 tag = sc->sc_tag; 2758 pci_conf_write(pc, tag, offs, win[0].win_start); 2759 pci_conf_write(pc, tag, offs + 4, win[0].win_limit); 2760 pci_conf_write(pc, tag, offs + 8, win[1].win_start); 2761 pci_conf_write(pc, tag, offs + 12, win[1].win_limit); 2762 DPRINTF(("--pccbb_winset: win0 [%x, %lx), win1 [%x, %lx)\n", 2763 pci_conf_read(pc, tag, offs), 2764 pci_conf_read(pc, tag, offs + 4) + align, 2765 pci_conf_read(pc, tag, offs + 8), 2766 pci_conf_read(pc, tag, offs + 12) + align)); 2767 2768 if (bst == sc->sc_memt) { 2769 pcireg_t bcr = pci_conf_read(pc, tag, PCI_BCR_INTR); 2770 2771 bcr &= ~(CB_BCR_PREFETCH_MEMWIN0 | CB_BCR_PREFETCH_MEMWIN1); 2772 if (win[0].win_flags & PCCBB_MEM_CACHABLE) 2773 bcr |= CB_BCR_PREFETCH_MEMWIN0; 2774 if (win[1].win_flags & PCCBB_MEM_CACHABLE) 2775 bcr |= CB_BCR_PREFETCH_MEMWIN1; 2776 pci_conf_write(pc, tag, PCI_BCR_INTR, bcr); 2777 } 2778 } 2779 2780 int 2781 pccbbactivate(struct device *self, int act) 2782 { 2783 struct pccbb_softc *sc = (struct pccbb_softc *)self; 2784 pci_chipset_tag_t pc = sc->sc_pc; 2785 pcitag_t tag = sc->sc_tag; 2786 pcireg_t csr; 2787 u_int32_t reg; 2788 bus_space_tag_t base_memt = sc->sc_base_memt; /* socket regs memory */ 2789 bus_space_handle_t base_memh = sc->sc_base_memh; 2790 int rv = 0; 2791 2792 switch (act) { 2793 case DVACT_SUSPEND: 2794 rv = config_activate_children(self, act); 2795 2796 sc->sc_pil_intr_enable = 0; 2797 2798 /* Save registers that may get lost. */ 2799 sc->sc_csr = pci_conf_read(pc, tag, PCI_COMMAND_STATUS_REG); 2800 sc->sc_bhlcr = pci_conf_read(pc, tag, PCI_BHLC_REG); 2801 sc->sc_int = pci_conf_read(pc, tag, PCI_INTERRUPT_REG); 2802 2803 sc->sc_sockbase = pci_conf_read(pc, tag, PCI_SOCKBASE); 2804 sc->sc_busnum = pci_conf_read(pc, tag, PCI_BUSNUM); 2805 2806 sc->sc_membase[0] = pci_conf_read(pc, tag, PCI_CB_MEMBASE0); 2807 sc->sc_memlimit[0] = pci_conf_read(pc, tag, PCI_CB_MEMLIMIT0); 2808 sc->sc_membase[1] = pci_conf_read(pc, tag, PCI_CB_MEMBASE1); 2809 sc->sc_memlimit[1] = pci_conf_read(pc, tag, PCI_CB_MEMLIMIT1); 2810 sc->sc_iobase[0] = pci_conf_read(pc, tag, PCI_CB_IOBASE0); 2811 sc->sc_iolimit[0] = pci_conf_read(pc, tag, PCI_CB_IOLIMIT0); 2812 sc->sc_iobase[1] = pci_conf_read(pc, tag, PCI_CB_IOBASE1); 2813 sc->sc_iolimit[1] = pci_conf_read(pc, tag, PCI_CB_IOLIMIT1); 2814 break; 2815 case DVACT_RESUME: 2816 /* Restore the registers saved above. */ 2817 pci_conf_write(pc, tag, PCI_BHLC_REG, sc->sc_bhlcr); 2818 pci_conf_write(pc, tag, PCI_INTERRUPT_REG, sc->sc_int); 2819 2820 pci_conf_write(pc, tag, PCI_SOCKBASE, sc->sc_sockbase); 2821 pci_conf_write(pc, tag, PCI_BUSNUM, sc->sc_busnum); 2822 2823 pci_conf_write(pc, tag, PCI_CB_MEMBASE0, sc->sc_membase[0]); 2824 pci_conf_write(pc, tag, PCI_CB_MEMLIMIT0, sc->sc_memlimit[0]); 2825 pci_conf_write(pc, tag, PCI_CB_MEMBASE1, sc->sc_membase[1]); 2826 pci_conf_write(pc, tag, PCI_CB_MEMLIMIT1, sc->sc_memlimit[1]); 2827 pci_conf_write(pc, tag, PCI_CB_IOBASE0, sc->sc_iobase[0]); 2828 pci_conf_write(pc, tag, PCI_CB_IOLIMIT0, sc->sc_iolimit[0]); 2829 pci_conf_write(pc, tag, PCI_CB_IOBASE1, sc->sc_iobase[1]); 2830 pci_conf_write(pc, tag, PCI_CB_IOLIMIT1, sc->sc_iolimit[1]); 2831 2832 /* Disable legacy register mapping. */ 2833 pccbb_legacy_disable(sc); 2834 2835 /* 2836 * Restore command register last to avoid exposing 2837 * uninitialised windows. 2838 */ 2839 csr = pci_conf_read(pc, tag, PCI_COMMAND_STATUS_REG); 2840 pci_conf_write(pc, tag, PCI_COMMAND_STATUS_REG, 2841 (csr & 0xffff0000) | (sc->sc_csr & 0x0000ffff)); 2842 2843 /* CSC Interrupt: Card detect interrupt on */ 2844 reg = bus_space_read_4(base_memt, base_memh, CB_SOCKET_MASK); 2845 /* Card detect intr is turned on. */ 2846 reg |= CB_SOCKET_MASK_CD; 2847 bus_space_write_4(base_memt, base_memh, CB_SOCKET_MASK, reg); 2848 2849 /* reset interrupt */ 2850 reg = bus_space_read_4(base_memt, base_memh, CB_SOCKET_EVENT); 2851 bus_space_write_4(base_memt, base_memh, CB_SOCKET_EVENT, reg); 2852 2853 /* re-check all cards */ 2854 pccbb_checksockstat(sc); 2855 2856 /* 2857 * XXX Because the cardslot stuff is so obfuscated with threads, 2858 * here we are activating children which may have been 2859 * ejected while we were asleep. This needs to be solved. 2860 */ 2861 rv = config_activate_children(self, act); 2862 2863 sc->sc_pil_intr_enable = 1; 2864 break; 2865 case DVACT_POWERDOWN: 2866 rv = config_activate_children(self, act); 2867 pccbb_shutdown(self); 2868 break; 2869 default: 2870 rv = config_activate_children(self, act); 2871 break; 2872 } 2873 return (rv); 2874 } 2875