1 /* $OpenBSD: pccbb.c,v 1.32 2003/06/25 21:53:45 mickey Exp $ */ 2 /* $NetBSD: pccbb.c,v 1.42 2000/06/16 23:41:35 cgd Exp $ */ 3 4 /* 5 * Copyright (c) 1998, 1999 and 2000 6 * HAYAKAWA Koichi. All rights reserved. 7 * 8 * Redistribution and use in source and binary forms, with or without 9 * modification, are permitted provided that the following conditions 10 * are met: 11 * 1. Redistributions of source code must retain the above copyright 12 * notice, this list of conditions and the following disclaimer. 13 * 2. Redistributions in binary form must reproduce the above copyright 14 * notice, this list of conditions and the following disclaimer in the 15 * documentation and/or other materials provided with the distribution. 16 * 3. All advertising materials mentioning features or use of this software 17 * must display the following acknowledgement: 18 * This product includes software developed by HAYAKAWA Koichi. 19 * 4. The name of the author may not be used to endorse or promote products 20 * derived from this software without specific prior written permission. 21 * 22 * THIS SOFTWARE IS PROVIDED BY THE AUTHOR ``AS IS'' AND ANY EXPRESS OR 23 * IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED WARRANTIES 24 * OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE DISCLAIMED. 25 * IN NO EVENT SHALL THE AUTHOR BE LIABLE FOR ANY DIRECT, INDIRECT, 26 * INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT 27 * NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, 28 * DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY 29 * THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT 30 * (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE OF 31 * THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE. 32 */ 33 34 /* 35 #define CBB_DEBUG 36 #define SHOW_REGS 37 #define PCCBB_PCMCIA_POLL 38 */ 39 /* #define CBB_DEBUG */ 40 41 /* 42 #define CB_PCMCIA_POLL 43 #define CB_PCMCIA_POLL_ONLY 44 #define LEVEL2 45 */ 46 47 #include <sys/types.h> 48 #include <sys/param.h> 49 #include <sys/systm.h> 50 #include <sys/kernel.h> 51 #include <sys/errno.h> 52 #include <sys/ioctl.h> 53 #include <sys/syslog.h> 54 #include <sys/device.h> 55 #include <sys/malloc.h> 56 57 #include <machine/intr.h> 58 #include <machine/bus.h> 59 60 #include <dev/pci/pcivar.h> 61 #include <dev/pci/pcireg.h> 62 #include <dev/pci/pcidevs.h> 63 64 #include <dev/pci/pccbbreg.h> 65 66 #include <dev/cardbus/cardslotvar.h> 67 68 #include <dev/cardbus/cardbusvar.h> 69 70 #include <dev/pcmcia/pcmciareg.h> 71 #include <dev/pcmcia/pcmciavar.h> 72 73 #include <dev/ic/i82365reg.h> 74 #include <dev/ic/i82365var.h> 75 #include <dev/pci/pccbbvar.h> 76 77 #ifndef __NetBSD_Version__ 78 struct cfdriver cbb_cd = { 79 NULL, "cbb", DV_DULL 80 }; 81 #endif 82 83 #if defined CBB_DEBUG 84 #define DPRINTF(x) printf x 85 #else 86 #define DPRINTF(x) 87 #endif 88 89 int pcicbbmatch(struct device *, void *, void *); 90 void pccbbattach(struct device *, struct device *, void *); 91 int pccbbintr(void *); 92 void pccbb_shutdown(void *); 93 void pci113x_insert(void *); 94 int pccbbintr_function(struct pccbb_softc *); 95 96 int pccbb_detect_card(struct pccbb_softc *); 97 98 void pccbb_pcmcia_write(struct pcic_handle *, int, int); 99 u_int8_t pccbb_pcmcia_read(struct pcic_handle *, int); 100 #define Pcic_read(ph, reg) ((ph)->ph_read((ph), (reg))) 101 #define Pcic_write(ph, reg, val) ((ph)->ph_write((ph), (reg), (val))) 102 103 int cb_reset(struct pccbb_softc *); 104 int cb_detect_voltage(struct pccbb_softc *); 105 int cbbprint(void *, const char *); 106 107 int cb_chipset(u_int32_t, int *); 108 void pccbb_pcmcia_attach_setup(struct pccbb_softc *, 109 struct pcmciabus_attach_args *); 110 #if 0 111 void pccbb_pcmcia_attach_card(struct pcic_handle *); 112 void pccbb_pcmcia_detach_card(struct pcic_handle *, int); 113 void pccbb_pcmcia_deactivate_card(struct pcic_handle *); 114 #endif 115 116 int pccbb_ctrl(cardbus_chipset_tag_t, int); 117 int pccbb_power(cardbus_chipset_tag_t, int); 118 int pccbb_cardenable(struct pccbb_softc * sc, int function); 119 #if !rbus 120 int pccbb_io_open(cardbus_chipset_tag_t, int, u_int32_t, u_int32_t); 121 int pccbb_io_close(cardbus_chipset_tag_t, int); 122 int pccbb_mem_open(cardbus_chipset_tag_t, int, u_int32_t, u_int32_t); 123 int pccbb_mem_close(cardbus_chipset_tag_t, int); 124 #endif /* !rbus */ 125 void *pccbb_intr_establish(struct pccbb_softc *, int irq, int level, 126 int (*ih) (void *), void *sc); 127 void pccbb_intr_disestablish(struct pccbb_softc *, void *ih); 128 129 void *pccbb_cb_intr_establish(cardbus_chipset_tag_t, int irq, int level, 130 int (*ih) (void *), void *sc); 131 void pccbb_cb_intr_disestablish(cardbus_chipset_tag_t ct, void *ih); 132 133 cardbustag_t pccbb_make_tag(cardbus_chipset_tag_t, int, int, int); 134 void pccbb_free_tag(cardbus_chipset_tag_t, cardbustag_t); 135 cardbusreg_t pccbb_conf_read(cardbus_chipset_tag_t, cardbustag_t, int); 136 void pccbb_conf_write(cardbus_chipset_tag_t, cardbustag_t, int, 137 cardbusreg_t); 138 void pccbb_chipinit(struct pccbb_softc *); 139 140 int pccbb_pcmcia_mem_alloc(pcmcia_chipset_handle_t, bus_size_t, 141 struct pcmcia_mem_handle *); 142 void pccbb_pcmcia_mem_free(pcmcia_chipset_handle_t, 143 struct pcmcia_mem_handle *); 144 int pccbb_pcmcia_mem_map(pcmcia_chipset_handle_t, int, bus_addr_t, 145 bus_size_t, struct pcmcia_mem_handle *, bus_addr_t *, int *); 146 void pccbb_pcmcia_mem_unmap(pcmcia_chipset_handle_t, int); 147 int pccbb_pcmcia_io_alloc(pcmcia_chipset_handle_t, bus_addr_t, 148 bus_size_t, bus_size_t, struct pcmcia_io_handle *); 149 void pccbb_pcmcia_io_free(pcmcia_chipset_handle_t, 150 struct pcmcia_io_handle *); 151 int pccbb_pcmcia_io_map(pcmcia_chipset_handle_t, int, bus_addr_t, 152 bus_size_t, struct pcmcia_io_handle *, int *); 153 void pccbb_pcmcia_io_unmap(pcmcia_chipset_handle_t, int); 154 void *pccbb_pcmcia_intr_establish(pcmcia_chipset_handle_t, 155 struct pcmcia_function *, int, int (*)(void *), void *, char *); 156 void pccbb_pcmcia_intr_disestablish(pcmcia_chipset_handle_t, 157 void *); 158 void pccbb_pcmcia_socket_enable(pcmcia_chipset_handle_t); 159 void pccbb_pcmcia_socket_disable(pcmcia_chipset_handle_t); 160 int pccbb_pcmcia_card_detect(pcmcia_chipset_handle_t pch); 161 162 void pccbb_pcmcia_do_io_map(struct pcic_handle *, int); 163 void pccbb_pcmcia_wait_ready(struct pcic_handle *); 164 void pccbb_pcmcia_do_mem_map(struct pcic_handle *, int); 165 void pccbb_powerhook(int, void *); 166 167 /* bus-space allocation and deallocation functions */ 168 #if rbus 169 170 int pccbb_rbus_cb_space_alloc(cardbus_chipset_tag_t, rbus_tag_t, 171 bus_addr_t addr, bus_size_t size, bus_addr_t mask, bus_size_t align, 172 int flags, bus_addr_t * addrp, bus_space_handle_t * bshp); 173 int pccbb_rbus_cb_space_free(cardbus_chipset_tag_t, rbus_tag_t, 174 bus_space_handle_t, bus_size_t); 175 176 #endif /* rbus */ 177 178 #if rbus 179 180 int pccbb_open_win(struct pccbb_softc *, bus_space_tag_t, 181 bus_addr_t, bus_size_t, bus_space_handle_t, int flags); 182 int pccbb_close_win(struct pccbb_softc *, bus_space_tag_t, 183 bus_space_handle_t, bus_size_t); 184 int pccbb_winlist_insert(struct pccbb_win_chain_head *, bus_addr_t, 185 bus_size_t, bus_space_handle_t, int); 186 int pccbb_winlist_delete(struct pccbb_win_chain_head *, 187 bus_space_handle_t, bus_size_t); 188 void pccbb_winset(bus_addr_t align, struct pccbb_softc *, 189 bus_space_tag_t); 190 void pccbb_winlist_show(struct pccbb_win_chain *); 191 192 #endif /* rbus */ 193 194 /* for config_defer */ 195 void pccbb_pci_callback(struct device *); 196 197 #if defined SHOW_REGS 198 void cb_show_regs(pci_chipset_tag_t, pcitag_t, bus_space_tag_t, 199 bus_space_handle_t memh); 200 #endif 201 202 struct cfattach cbb_pci_ca = { 203 sizeof(struct pccbb_softc), pcicbbmatch, pccbbattach 204 }; 205 206 static struct pcmcia_chip_functions pccbb_pcmcia_funcs = { 207 pccbb_pcmcia_mem_alloc, 208 pccbb_pcmcia_mem_free, 209 pccbb_pcmcia_mem_map, 210 pccbb_pcmcia_mem_unmap, 211 pccbb_pcmcia_io_alloc, 212 pccbb_pcmcia_io_free, 213 pccbb_pcmcia_io_map, 214 pccbb_pcmcia_io_unmap, 215 pccbb_pcmcia_intr_establish, 216 pccbb_pcmcia_intr_disestablish, 217 pccbb_pcmcia_socket_enable, 218 pccbb_pcmcia_socket_disable, 219 pccbb_pcmcia_card_detect 220 }; 221 222 #if rbus 223 static struct cardbus_functions pccbb_funcs = { 224 pccbb_rbus_cb_space_alloc, 225 pccbb_rbus_cb_space_free, 226 pccbb_cb_intr_establish, 227 pccbb_cb_intr_disestablish, 228 pccbb_ctrl, 229 pccbb_power, 230 pccbb_make_tag, 231 pccbb_free_tag, 232 pccbb_conf_read, 233 pccbb_conf_write, 234 }; 235 #else 236 static struct cardbus_functions pccbb_funcs = { 237 pccbb_ctrl, 238 pccbb_power, 239 pccbb_mem_open, 240 pccbb_mem_close, 241 pccbb_io_open, 242 pccbb_io_close, 243 pccbb_cb_intr_establish, 244 pccbb_cb_intr_disestablish, 245 pccbb_make_tag, 246 pccbb_conf_read, 247 pccbb_conf_write, 248 }; 249 #endif 250 251 int 252 pcicbbmatch(parent, match, aux) 253 struct device *parent; 254 void *match; 255 void *aux; 256 { 257 struct pci_attach_args *pa = (struct pci_attach_args *)aux; 258 259 if (PCI_CLASS(pa->pa_class) == PCI_CLASS_BRIDGE && 260 PCI_SUBCLASS(pa->pa_class) == PCI_SUBCLASS_BRIDGE_CARDBUS && 261 PCI_INTERFACE(pa->pa_class) == 0) { 262 return 1; 263 } 264 265 return 0; 266 } 267 268 #define MAKEID(vendor, prod) (((vendor) << PCI_VENDOR_SHIFT) \ 269 | ((prod) << PCI_PRODUCT_SHIFT)) 270 271 struct yenta_chipinfo { 272 pcireg_t yc_id; /* vendor tag | product tag */ 273 int yc_chiptype; 274 int yc_flags; 275 } yc_chipsets[] = { 276 /* Texas Instruments chips */ 277 { MAKEID(PCI_VENDOR_TI, PCI_PRODUCT_TI_PCI1130), CB_TI113X, 278 PCCBB_PCMCIA_IO_RELOC | PCCBB_PCMCIA_MEM_32}, 279 { MAKEID(PCI_VENDOR_TI, PCI_PRODUCT_TI_PCI1131), CB_TI113X, 280 PCCBB_PCMCIA_IO_RELOC | PCCBB_PCMCIA_MEM_32}, 281 { MAKEID(PCI_VENDOR_TI, PCI_PRODUCT_TI_PCI1250), CB_TI12XX, 282 PCCBB_PCMCIA_IO_RELOC | PCCBB_PCMCIA_MEM_32}, 283 { MAKEID(PCI_VENDOR_TI, PCI_PRODUCT_TI_PCI1220), CB_TI12XX, 284 PCCBB_PCMCIA_IO_RELOC | PCCBB_PCMCIA_MEM_32}, 285 { MAKEID(PCI_VENDOR_TI, PCI_PRODUCT_TI_PCI1221), CB_TI12XX, 286 PCCBB_PCMCIA_IO_RELOC | PCCBB_PCMCIA_MEM_32}, 287 { MAKEID(PCI_VENDOR_TI, PCI_PRODUCT_TI_PCI1225), CB_TI12XX, 288 PCCBB_PCMCIA_IO_RELOC | PCCBB_PCMCIA_MEM_32}, 289 { MAKEID(PCI_VENDOR_TI, PCI_PRODUCT_TI_PCI1251), CB_TI12XX, 290 PCCBB_PCMCIA_IO_RELOC | PCCBB_PCMCIA_MEM_32}, 291 { MAKEID(PCI_VENDOR_TI, PCI_PRODUCT_TI_PCI1251B), CB_TI12XX, 292 PCCBB_PCMCIA_IO_RELOC | PCCBB_PCMCIA_MEM_32}, 293 { MAKEID(PCI_VENDOR_TI, PCI_PRODUCT_TI_PCI1211), CB_TI12XX, 294 PCCBB_PCMCIA_IO_RELOC | PCCBB_PCMCIA_MEM_32}, 295 { MAKEID(PCI_VENDOR_TI, PCI_PRODUCT_TI_PCI1410), CB_TI12XX, 296 PCCBB_PCMCIA_IO_RELOC | PCCBB_PCMCIA_MEM_32}, 297 { MAKEID(PCI_VENDOR_TI, PCI_PRODUCT_TI_PCI1420), CB_TI12XX, 298 PCCBB_PCMCIA_IO_RELOC | PCCBB_PCMCIA_MEM_32}, 299 { MAKEID(PCI_VENDOR_TI, PCI_PRODUCT_TI_PCI1450), CB_TI12XX, 300 PCCBB_PCMCIA_IO_RELOC | PCCBB_PCMCIA_MEM_32}, 301 { MAKEID(PCI_VENDOR_TI, PCI_PRODUCT_TI_PCI1451), CB_TI12XX, 302 PCCBB_PCMCIA_IO_RELOC | PCCBB_PCMCIA_MEM_32}, 303 304 /* Ricoh chips */ 305 { MAKEID(PCI_VENDOR_RICOH, PCI_PRODUCT_RICOH_RF5C475), CB_RX5C47X, 306 PCCBB_PCMCIA_MEM_32}, 307 { MAKEID(PCI_VENDOR_RICOH, PCI_PRODUCT_RICOH_RF5C476), CB_RX5C47X, 308 PCCBB_PCMCIA_MEM_32}, 309 { MAKEID(PCI_VENDOR_RICOH, PCI_PRODUCT_RICOH_RF5C477), CB_RX5C47X, 310 PCCBB_PCMCIA_MEM_32}, 311 { MAKEID(PCI_VENDOR_RICOH, PCI_PRODUCT_RICOH_RF5C478), CB_RX5C47X, 312 PCCBB_PCMCIA_MEM_32}, 313 { MAKEID(PCI_VENDOR_RICOH, PCI_PRODUCT_RICOH_RF5C465), CB_RX5C46X, 314 PCCBB_PCMCIA_MEM_32}, 315 { MAKEID(PCI_VENDOR_RICOH, PCI_PRODUCT_RICOH_RF5C466), CB_RX5C46X, 316 PCCBB_PCMCIA_MEM_32}, 317 318 /* Toshiba products */ 319 { MAKEID(PCI_VENDOR_TOSHIBA2, PCI_PRODUCT_TOSHIBA2_ToPIC95), 320 CB_TOPIC95, PCCBB_PCMCIA_MEM_32}, 321 { MAKEID(PCI_VENDOR_TOSHIBA2, PCI_PRODUCT_TOSHIBA2_ToPIC95B), 322 CB_TOPIC95B, PCCBB_PCMCIA_MEM_32}, 323 { MAKEID(PCI_VENDOR_TOSHIBA2, PCI_PRODUCT_TOSHIBA2_ToPIC97), 324 CB_TOPIC97, PCCBB_PCMCIA_MEM_32}, 325 { MAKEID(PCI_VENDOR_TOSHIBA2, PCI_PRODUCT_TOSHIBA2_ToPIC100), 326 CB_TOPIC97, PCCBB_PCMCIA_MEM_32}, 327 328 /* Cirrus Logic products */ 329 { MAKEID(PCI_VENDOR_CIRRUS, PCI_PRODUCT_CIRRUS_CL_PD6832), 330 CB_CIRRUS, PCCBB_PCMCIA_MEM_32}, 331 { MAKEID(PCI_VENDOR_CIRRUS, PCI_PRODUCT_CIRRUS_CL_PD6833), 332 CB_CIRRUS, PCCBB_PCMCIA_MEM_32}, 333 334 /* sentinel, or Generic chip */ 335 { 0 /* null id */ , CB_UNKNOWN, PCCBB_PCMCIA_MEM_32}, 336 }; 337 338 int 339 cb_chipset(pci_id, flagp) 340 u_int32_t pci_id; 341 int *flagp; 342 { 343 struct yenta_chipinfo *yc; 344 345 /* Loop over except the last default entry. */ 346 for (yc = yc_chipsets; yc < yc_chipsets + 347 sizeof(yc_chipsets) / sizeof(yc_chipsets[0]) - 1; yc++) 348 if (pci_id == yc->yc_id) 349 break; 350 351 if (flagp != NULL) 352 *flagp = yc->yc_flags; 353 354 return (yc->yc_chiptype); 355 } 356 357 void 358 pccbb_shutdown(void *arg) 359 { 360 struct pccbb_softc *sc = arg; 361 pcireg_t command; 362 363 DPRINTF(("%s: shutdown\n", sc->sc_dev.dv_xname)); 364 365 /* turn off power */ 366 pccbb_power((cardbus_chipset_tag_t)sc, CARDBUS_VCC_0V | CARDBUS_VPP_0V); 367 368 bus_space_write_4(sc->sc_base_memt, sc->sc_base_memh, CB_SOCKET_MASK, 369 0); 370 371 command = pci_conf_read(sc->sc_pc, sc->sc_tag, PCI_COMMAND_STATUS_REG); 372 373 command &= ~(PCI_COMMAND_IO_ENABLE | PCI_COMMAND_MEM_ENABLE | 374 PCI_COMMAND_MASTER_ENABLE); 375 pci_conf_write(sc->sc_pc, sc->sc_tag, PCI_COMMAND_STATUS_REG, command); 376 } 377 378 void 379 pccbbattach(parent, self, aux) 380 struct device *parent; 381 struct device *self; 382 void *aux; 383 { 384 struct pccbb_softc *sc = (void *)self; 385 struct pci_attach_args *pa = aux; 386 pci_chipset_tag_t pc = pa->pa_pc; 387 pcireg_t busreg, reg, sock_base; 388 pci_intr_handle_t ih; 389 const char *intrstr = NULL; 390 bus_addr_t sockbase; 391 int flags; 392 393 sc->sc_chipset = cb_chipset(pa->pa_id, &flags); 394 395 #ifdef CBB_DEBUG 396 printf(" (chipflags %x)", flags); 397 #endif 398 399 TAILQ_INIT(&sc->sc_memwindow); 400 TAILQ_INIT(&sc->sc_iowindow); 401 402 #if rbus 403 sc->sc_rbus_iot = rbus_pccbb_parent_io(self, pa); 404 sc->sc_rbus_memt = rbus_pccbb_parent_mem(self, pa); 405 #endif /* rbus */ 406 407 sc->sc_base_memh = 0; 408 409 /* 410 * MAP socket registers and ExCA registers on memory-space 411 * When no valid address is set on socket base registers (on pci 412 * config space), get it not polite way. 413 */ 414 sock_base = pci_conf_read(pc, pa->pa_tag, PCI_SOCKBASE); 415 416 if (PCI_MAPREG_MEM_ADDR(sock_base) >= 0x100000 && 417 PCI_MAPREG_MEM_ADDR(sock_base) != 0xfffffff0) { 418 /* The address must be valid. */ 419 if (pci_mapreg_map(pa, PCI_SOCKBASE, PCI_MAPREG_TYPE_MEM, 0, 420 &sc->sc_base_memt, &sc->sc_base_memh, &sockbase, NULL, 0)) 421 { 422 printf("%s: can't map socket base address 0x%x\n", 423 sc->sc_dev.dv_xname, sock_base); 424 /* 425 * I think it's funny: socket base registers must be 426 * mapped on memory space, but ... 427 */ 428 if (pci_mapreg_map(pa, PCI_SOCKBASE, 429 PCI_MAPREG_TYPE_IO, 0, &sc->sc_base_memt, 430 &sc->sc_base_memh, &sockbase, NULL, 0)) { 431 printf("%s: can't map socket base address" 432 " 0x%lx: io mode\n", sc->sc_dev.dv_xname, 433 sockbase); 434 /* give up... allocate reg space via rbus. */ 435 sc->sc_base_memh = 0; 436 pci_conf_write(pc, pa->pa_tag, PCI_SOCKBASE, 0); 437 } 438 } else { 439 DPRINTF(("%s: socket base address 0x%lx\n", 440 sc->sc_dev.dv_xname, sockbase)); 441 } 442 } 443 444 sc->sc_mem_start = 0; /* XXX */ 445 sc->sc_mem_end = 0xffffffff; /* XXX */ 446 447 /* 448 * When bus number isn't set correctly, give up using 32-bit CardBus 449 * mode. 450 */ 451 busreg = pci_conf_read(pc, pa->pa_tag, PCI_BUSNUM); 452 #if notyet 453 if (((busreg >> 8) & 0xff) == 0) { 454 printf(": CardBus support disabled because of unconfigured bus number\n"); 455 flags |= PCCBB_PCMCIA_16BITONLY; 456 } 457 #endif 458 459 /* pccbb_machdep.c end */ 460 461 #if defined CBB_DEBUG 462 { 463 static char *intrname[5] = { "NON", "A", "B", "C", "D" }; 464 printf(": intrpin %s, intrtag %d\n", 465 intrname[pa->pa_intrpin], pa->pa_intrline); 466 } 467 #endif 468 469 /* setup softc */ 470 sc->sc_pc = pc; 471 sc->sc_iot = pa->pa_iot; 472 sc->sc_memt = pa->pa_memt; 473 sc->sc_dmat = pa->pa_dmat; 474 sc->sc_tag = pa->pa_tag; 475 sc->sc_function = pa->pa_function; 476 sc->sc_sockbase = sock_base; 477 sc->sc_busnum = busreg; 478 sc->sc_intrtag = pa->pa_intrtag; 479 sc->sc_intrpin = pa->pa_intrpin; 480 481 sc->sc_pcmcia_flags = flags; /* set PCMCIA facility */ 482 483 /* Map and establish the interrupt. */ 484 if (pci_intr_map(pa, &ih)) { 485 printf(": couldn't map interrupt\n"); 486 return; 487 } 488 intrstr = pci_intr_string(pc, ih); 489 /* must do this after intr is mapped and established */ 490 sc->sc_intrline = pci_intr_line(ih); 491 492 /* 493 * XXX pccbbintr should be called under the priority lower 494 * than any other hard interrputs. 495 */ 496 sc->sc_ih = pci_intr_establish(pc, ih, IPL_BIO, pccbbintr, sc, 497 sc->sc_dev.dv_xname); 498 499 if (sc->sc_ih == NULL) { 500 printf(": couldn't establish interrupt"); 501 if (intrstr != NULL) { 502 printf(" at %s", intrstr); 503 } 504 printf("\n"); 505 return; 506 } 507 printf(": %s\n", intrstr); 508 509 shutdownhook_establish(pccbb_shutdown, sc); 510 511 /* Disable legacy register mapping. */ 512 switch (sc->sc_chipset) { 513 case CB_RX5C46X: /* fallthrough */ 514 #if 0 515 /* The RX5C47X-series requires writes to the PCI_LEGACY register. */ 516 case CB_RX5C47X: 517 #endif 518 /* 519 * The legacy pcic io-port on Ricoh RX5C46X CardBus bridges 520 * cannot be disabled by substituting 0 into PCI_LEGACY 521 * register. Ricoh CardBus bridges have special bits on Bridge 522 * control reg (addr 0x3e on PCI config space). 523 */ 524 reg = pci_conf_read(pc, pa->pa_tag, PCI_BCR_INTR); 525 reg &= ~(CB_BCRI_RL_3E0_ENA | CB_BCRI_RL_3E2_ENA); 526 pci_conf_write(pc, pa->pa_tag, PCI_BCR_INTR, reg); 527 break; 528 529 default: 530 /* XXX I don't know proper way to kill legacy I/O. */ 531 pci_conf_write(pc, pa->pa_tag, PCI_LEGACY, 0x0); 532 break; 533 } 534 535 timeout_set(&sc->sc_ins_tmo, pci113x_insert, sc); 536 config_defer(self, pccbb_pci_callback); 537 } 538 539 540 541 542 /* 543 * void pccbb_pci_callback(struct device *self) 544 * 545 * The actual attach routine: get memory space for YENTA register 546 * space, setup YENTA register and route interrupt. 547 * 548 * This function should be deferred because this device may obtain 549 * memory space dynamically. This function must avoid obtaining 550 * memory area which has already kept for another device. Also, 551 * this function MUST be done before ISA attach process because this 552 * function kills pcic compatible port used by ISA pcic. 553 */ 554 void 555 pccbb_pci_callback(self) 556 struct device *self; 557 { 558 struct pccbb_softc *sc = (void *)self; 559 pci_chipset_tag_t pc = sc->sc_pc; 560 bus_space_tag_t base_memt; 561 bus_space_handle_t base_memh; 562 u_int32_t maskreg; 563 bus_addr_t sockbase; 564 struct cbslot_attach_args cba; 565 struct pcmciabus_attach_args paa; 566 struct cardslot_attach_args caa; 567 struct cardslot_softc *csc; 568 569 if (0 == sc->sc_base_memh) { 570 /* The socket registers aren't mapped correctly. */ 571 #if rbus 572 if (rbus_space_alloc(sc->sc_rbus_memt, 0, 0x1000, 0x0fff, 573 (sc->sc_chipset == CB_RX5C47X 574 || sc->sc_chipset == CB_TI113X) ? 0x10000 : 0x1000, 575 0, &sockbase, &sc->sc_base_memh)) { 576 return; 577 } 578 sc->sc_base_memt = sc->sc_memt; 579 pci_conf_write(pc, sc->sc_tag, PCI_SOCKBASE, sockbase); 580 DPRINTF(("%s: CardBus resister address 0x%lx -> 0x%x\n", 581 sc->sc_dev.dv_xname, sockbase, pci_conf_read(pc, sc->sc_tag, 582 PCI_SOCKBASE))); 583 #else 584 sc->sc_base_memt = sc->sc_memt; 585 #if !defined CBB_PCI_BASE 586 #define CBB_PCI_BASE 0x20000000 587 #endif 588 if (bus_space_alloc(sc->sc_base_memt, CBB_PCI_BASE, 0xffffffff, 589 0x1000, 0x1000, 0, 0, &sockbase, &sc->sc_base_memh)) { 590 /* cannot allocate memory space */ 591 return; 592 } 593 pci_conf_write(pc, sc->sc_tag, PCI_SOCKBASE, sockbase); 594 DPRINTF(("%s: CardBus resister address 0x%x -> 0x%x\n", 595 sc->sc_dev.dv_xname, sock_base, pci_conf_read(pc, 596 sc->sc_tag, PCI_SOCKBASE))); 597 #endif 598 } 599 600 /* bus bridge initialization */ 601 pccbb_chipinit(sc); 602 603 base_memt = sc->sc_base_memt; /* socket regs memory tag */ 604 base_memh = sc->sc_base_memh; /* socket regs memory handle */ 605 606 /* clear data structure for child device interrupt handlers */ 607 sc->sc_pil = NULL; 608 sc->sc_pil_intr_enable = 1; 609 610 powerhook_establish(pccbb_powerhook, sc); 611 612 { 613 u_int32_t sockstat = 614 bus_space_read_4(base_memt, base_memh, CB_SOCKET_STAT); 615 if (0 == (sockstat & CB_SOCKET_STAT_CD)) { 616 sc->sc_flags |= CBB_CARDEXIST; 617 } 618 } 619 620 /* 621 * attach cardbus 622 */ 623 if (!(sc->sc_pcmcia_flags & PCCBB_PCMCIA_16BITONLY)) { 624 pcireg_t busreg = pci_conf_read(pc, sc->sc_tag, PCI_BUSNUM); 625 pcireg_t bhlc = pci_conf_read(pc, sc->sc_tag, PCI_BHLC_REG); 626 627 /* initialize cbslot_attach */ 628 cba.cba_busname = "cardbus"; 629 cba.cba_iot = sc->sc_iot; 630 cba.cba_memt = sc->sc_memt; 631 cba.cba_dmat = sc->sc_dmat; 632 cba.cba_bus = (busreg >> 8) & 0x0ff; 633 cba.cba_cc = (void *)sc; 634 cba.cba_cf = &pccbb_funcs; 635 cba.cba_intrline = sc->sc_intrline; 636 637 #if rbus 638 cba.cba_rbus_iot = sc->sc_rbus_iot; 639 cba.cba_rbus_memt = sc->sc_rbus_memt; 640 #endif 641 642 cba.cba_cacheline = PCI_CACHELINE(bhlc); 643 cba.cba_lattimer = PCI_CB_LATENCY(busreg); 644 645 #if defined CBB_DEBUG 646 printf("%s: cacheline 0x%x lattimer 0x%x\n", 647 sc->sc_dev.dv_xname, cba.cba_cacheline, cba.cba_lattimer); 648 printf("%s: bhlc 0x%x lscp 0x%x\n", sc->sc_dev.dv_xname, bhlc, 649 busreg); 650 #endif 651 #if defined SHOW_REGS 652 cb_show_regs(sc->sc_pc, sc->sc_tag, sc->sc_base_memt, 653 sc->sc_base_memh); 654 #endif 655 } 656 657 pccbb_pcmcia_attach_setup(sc, &paa); 658 caa.caa_cb_attach = NULL; 659 if (!(sc->sc_pcmcia_flags & PCCBB_PCMCIA_16BITONLY)) { 660 caa.caa_cb_attach = &cba; 661 } 662 caa.caa_16_attach = &paa; 663 caa.caa_ph = &sc->sc_pcmcia_h; 664 665 if (NULL != (csc = (void *)config_found(self, &caa, cbbprint))) { 666 DPRINTF(("pccbbattach: found cardslot\n")); 667 sc->sc_csc = csc; 668 } 669 670 sc->sc_ints_on = 1; 671 672 /* CSC Interrupt: Card detect interrupt on */ 673 maskreg = bus_space_read_4(base_memt, base_memh, CB_SOCKET_MASK); 674 maskreg |= CB_SOCKET_MASK_CD; /* Card detect intr is turned on. */ 675 bus_space_write_4(base_memt, base_memh, CB_SOCKET_MASK, maskreg); 676 /* reset interrupt */ 677 bus_space_write_4(base_memt, base_memh, CB_SOCKET_EVENT, 678 bus_space_read_4(base_memt, base_memh, CB_SOCKET_EVENT)); 679 680 return; 681 } 682 683 684 685 686 687 /* 688 * void pccbb_chipinit(struct pccbb_softc *sc) 689 * 690 * This function initialize YENTA chip registers listed below: 691 * 1) PCI command reg, 692 * 2) PCI and CardBus latency timer, 693 * 3) route PCI interrupt, 694 * 4) close all memory and io windows. 695 */ 696 void 697 pccbb_chipinit(sc) 698 struct pccbb_softc *sc; 699 { 700 pci_chipset_tag_t pc = sc->sc_pc; 701 pcitag_t tag = sc->sc_tag; 702 pcireg_t reg; 703 704 /* 705 * Set PCI command reg. 706 * Some laptop's BIOSes (i.e. TICO) do not enable CardBus chip. 707 */ 708 reg = pci_conf_read(pc, tag, PCI_COMMAND_STATUS_REG); 709 /* I believe it is harmless. */ 710 reg |= (PCI_COMMAND_IO_ENABLE | PCI_COMMAND_MEM_ENABLE | 711 PCI_COMMAND_MASTER_ENABLE); 712 pci_conf_write(pc, tag, PCI_COMMAND_STATUS_REG, reg); 713 714 /* 715 * Set CardBus latency timer. 716 */ 717 reg = pci_conf_read(pc, tag, PCI_CB_LSCP_REG); 718 if (PCI_CB_LATENCY(reg) < 0x20) { 719 reg &= ~(PCI_CB_LATENCY_MASK << PCI_CB_LATENCY_SHIFT); 720 reg |= (0x20 << PCI_CB_LATENCY_SHIFT); 721 pci_conf_write(pc, tag, PCI_CB_LSCP_REG, reg); 722 } 723 DPRINTF(("CardBus latency timer 0x%x (%x)\n", 724 PCI_CB_LATENCY(reg), pci_conf_read(pc, tag, PCI_CB_LSCP_REG))); 725 726 /* 727 * Set PCI latency timer. 728 */ 729 reg = pci_conf_read(pc, tag, PCI_BHLC_REG); 730 if (PCI_LATTIMER(reg) < 0x10) { 731 reg &= ~(PCI_LATTIMER_MASK << PCI_LATTIMER_SHIFT); 732 reg |= (0x10 << PCI_LATTIMER_SHIFT); 733 pci_conf_write(pc, tag, PCI_BHLC_REG, reg); 734 } 735 DPRINTF(("PCI latency timer 0x%x (%x)\n", 736 PCI_LATTIMER(reg), pci_conf_read(pc, tag, PCI_BHLC_REG))); 737 738 /* Route functional interrupts to PCI. */ 739 reg = pci_conf_read(pc, tag, PCI_BCR_INTR); 740 reg |= CB_BCR_INTR_IREQ_ENABLE; /* disable PCI Intr */ 741 reg |= CB_BCR_WRITE_POST_ENABLE; /* enable write post */ 742 reg |= CB_BCR_RESET_ENABLE; /* assert reset */ 743 pci_conf_write(pc, tag, PCI_BCR_INTR, reg); 744 745 switch (sc->sc_chipset) { 746 case CB_TI113X: 747 reg = pci_conf_read(pc, tag, PCI_CBCTRL); 748 /* This bit is shared, but may read as 0 on some chips, so set 749 it explicitly on both functions. */ 750 reg |= PCI113X_CBCTRL_PCI_IRQ_ENA; 751 /* CSC intr enable */ 752 reg |= PCI113X_CBCTRL_PCI_CSC; 753 /* functional intr prohibit | prohibit ISA routing */ 754 reg &= ~(PCI113X_CBCTRL_PCI_INTR | PCI113X_CBCTRL_INT_MASK); 755 pci_conf_write(pc, tag, PCI_CBCTRL, reg); 756 break; 757 758 case CB_TOPIC95B: 759 reg = pci_conf_read(pc, tag, TOPIC_SOCKET_CTRL); 760 reg |= TOPIC_SOCKET_CTRL_SCR_IRQSEL; 761 pci_conf_write(pc, tag, TOPIC_SOCKET_CTRL, reg); 762 763 reg = pci_conf_read(pc, tag, TOPIC_SLOT_CTRL); 764 DPRINTF(("%s: topic slot ctrl reg 0x%x -> ", 765 sc->sc_dev.dv_xname, reg)); 766 reg |= (TOPIC_SLOT_CTRL_SLOTON | TOPIC_SLOT_CTRL_SLOTEN | 767 TOPIC_SLOT_CTRL_ID_LOCK | TOPIC_SLOT_CTRL_CARDBUS); 768 reg &= ~TOPIC_SLOT_CTRL_SWDETECT; 769 DPRINTF(("0x%x\n", reg)); 770 pci_conf_write(pc, tag, TOPIC_SLOT_CTRL, reg); 771 break; 772 773 case CB_TOPIC97: 774 reg = pci_conf_read(pc, tag, TOPIC_SLOT_CTRL); 775 DPRINTF(("%s: topic slot ctrl reg 0x%x -> ", 776 sc->sc_dev.dv_xname, reg)); 777 reg |= (TOPIC_SLOT_CTRL_SLOTON | TOPIC_SLOT_CTRL_SLOTEN | 778 TOPIC_SLOT_CTRL_ID_LOCK | TOPIC_SLOT_CTRL_CARDBUS); 779 reg &= ~TOPIC_SLOT_CTRL_SWDETECT; 780 reg |= TOPIC97_SLOT_CTRL_PCIINT; 781 reg &= ~(TOPIC97_SLOT_CTRL_STSIRQP | TOPIC97_SLOT_CTRL_IRQP); 782 DPRINTF(("0x%x\n", reg)); 783 pci_conf_write(pc, tag, TOPIC_SLOT_CTRL, reg); 784 785 /* make sure to assert LV card support bits */ 786 bus_space_write_1(sc->sc_base_memt, sc->sc_base_memh, 787 0x800 + 0x3e, bus_space_read_1(sc->sc_base_memt, 788 sc->sc_base_memh, 0x800 + 0x3e) | 0x03); 789 790 /* Power on the controller if the BIOS didn't */ 791 reg = pci_conf_read(pc, tag, TOPIC100_PMCSR); 792 if ((reg & TOPIC100_PMCSR_MASK) != TOPIC100_PMCSR_D0) 793 pci_conf_write(pc, tag, TOPIC100_PMCSR, 794 (reg & ~TOPIC100_PMCSR_MASK) | TOPIC100_PMCSR_D0); 795 break; 796 } 797 798 /* Close all memory and I/O windows. */ 799 pci_conf_write(pc, tag, PCI_CB_MEMBASE0, 0xffffffff); 800 pci_conf_write(pc, tag, PCI_CB_MEMLIMIT0, 0); 801 pci_conf_write(pc, tag, PCI_CB_MEMBASE1, 0xffffffff); 802 pci_conf_write(pc, tag, PCI_CB_MEMLIMIT1, 0); 803 pci_conf_write(pc, tag, PCI_CB_IOBASE0, 0xffffffff); 804 pci_conf_write(pc, tag, PCI_CB_IOLIMIT0, 0); 805 pci_conf_write(pc, tag, PCI_CB_IOBASE1, 0xffffffff); 806 pci_conf_write(pc, tag, PCI_CB_IOLIMIT1, 0); 807 808 /* reset 16-bit pcmcia bus */ 809 bus_space_write_1(sc->sc_base_memt, sc->sc_base_memh, 810 0x800 + PCIC_INTR, 811 bus_space_read_1(sc->sc_base_memt, sc->sc_base_memh, 812 0x800 + PCIC_INTR) & ~PCIC_INTR_RESET); 813 814 /* turn off power */ 815 pccbb_power((cardbus_chipset_tag_t)sc, CARDBUS_VCC_0V | CARDBUS_VPP_0V); 816 } 817 818 819 820 821 /* 822 * void pccbb_pcmcia_attach_setup(struct pccbb_softc *sc, 823 * struct pcmciabus_attach_args *paa) 824 * 825 * This function attaches 16-bit PCcard bus. 826 */ 827 void 828 pccbb_pcmcia_attach_setup(sc, paa) 829 struct pccbb_softc *sc; 830 struct pcmciabus_attach_args *paa; 831 { 832 struct pcic_handle *ph = &sc->sc_pcmcia_h; 833 #if rbus 834 rbus_tag_t rb; 835 #endif 836 837 /* initialize pcmcia part in pccbb_softc */ 838 ph->ph_parent = (struct device *)sc; 839 ph->sock = sc->sc_function; 840 ph->flags = 0; 841 ph->shutdown = 0; 842 ph->ih_irq = sc->sc_intrline; 843 ph->ph_bus_t = sc->sc_base_memt; 844 ph->ph_bus_h = sc->sc_base_memh; 845 ph->ph_read = pccbb_pcmcia_read; 846 ph->ph_write = pccbb_pcmcia_write; 847 sc->sc_pct = &pccbb_pcmcia_funcs; 848 849 /* 850 * We need to do a few things here: 851 * 1) Disable routing of CSC and functional interrupts to ISA IRQs by 852 * setting the IRQ numbers to 0. 853 * 2) Set bit 4 of PCIC_INTR, which is needed on some chips to enable 854 * routing of CSC interrupts (e.g. card removal) to PCI while in 855 * PCMCIA mode. We just leave this set all the time. 856 * 3) Enable card insertion/removal interrupts in case the chip also 857 * needs that while in PCMCIA mode. 858 * 4) Clear any pending CSC interrupt. 859 */ 860 Pcic_write(ph, PCIC_INTR, PCIC_INTR_ENABLE | PCIC_INTR_RESET); 861 if (sc->sc_chipset == CB_TI113X) { 862 Pcic_write(ph, PCIC_CSC_INTR, 0); 863 } else { 864 Pcic_write(ph, PCIC_CSC_INTR, PCIC_CSC_INTR_CD_ENABLE); 865 Pcic_read(ph, PCIC_CSC); 866 } 867 868 /* initialize pcmcia bus attachment */ 869 paa->paa_busname = "pcmcia"; 870 paa->pct = sc->sc_pct; 871 paa->pch = ph; 872 paa->iobase = 0; /* I don't use them */ 873 paa->iosize = 0; 874 #if rbus 875 rb = ((struct pccbb_softc *)(ph->ph_parent))->sc_rbus_iot; 876 paa->iobase = rb->rb_start + rb->rb_offset; 877 paa->iosize = rb->rb_end - rb->rb_start; 878 #endif 879 880 return; 881 } 882 883 #if 0 884 void 885 pccbb_pcmcia_attach_card(ph) 886 struct pcic_handle *ph; 887 { 888 if (ph->flags & PCIC_FLAG_CARDP) { 889 panic("pccbb_pcmcia_attach_card: already attached"); 890 } 891 892 /* call the MI attach function */ 893 pcmcia_card_attach(ph->pcmcia); 894 895 ph->flags |= PCIC_FLAG_CARDP; 896 } 897 898 void 899 pccbb_pcmcia_detach_card(ph, flags) 900 struct pcic_handle *ph; 901 int flags; 902 { 903 if (!(ph->flags & PCIC_FLAG_CARDP)) { 904 panic("pccbb_pcmcia_detach_card: already detached"); 905 } 906 907 ph->flags &= ~PCIC_FLAG_CARDP; 908 909 /* call the MI detach function */ 910 pcmcia_card_detach(ph->pcmcia, flags); 911 } 912 #endif 913 914 /* 915 * int pccbbintr(arg) 916 * void *arg; 917 * This routine handles the interrupt from Yenta PCI-CardBus bridge 918 * itself. 919 */ 920 int 921 pccbbintr(arg) 922 void *arg; 923 { 924 struct pccbb_softc *sc = (struct pccbb_softc *)arg; 925 u_int32_t sockevent, sockstate; 926 bus_space_tag_t memt = sc->sc_base_memt; 927 bus_space_handle_t memh = sc->sc_base_memh; 928 struct pcic_handle *ph = &sc->sc_pcmcia_h; 929 930 if (!sc->sc_ints_on) 931 return 0; 932 933 sockevent = bus_space_read_4(memt, memh, CB_SOCKET_EVENT); 934 bus_space_write_4(memt, memh, CB_SOCKET_EVENT, sockevent); 935 Pcic_read(ph, PCIC_CSC); 936 937 if (sockevent == 0) { 938 /* This intr is not for me: it may be for my child devices. */ 939 if (sc->sc_pil_intr_enable) { 940 return pccbbintr_function(sc); 941 } else { 942 return 0; 943 } 944 } 945 946 if (sockevent & CB_SOCKET_EVENT_CD) { 947 sockstate = bus_space_read_4(memt, memh, CB_SOCKET_STAT); 948 if (CB_SOCKET_STAT_CD == (sockstate & CB_SOCKET_STAT_CD)) { 949 /* A card should be removed. */ 950 if (sc->sc_flags & CBB_CARDEXIST) { 951 DPRINTF(("%s: 0x%08x", sc->sc_dev.dv_xname, 952 sockevent)); 953 DPRINTF((" card removed, 0x%08x\n", sockstate)); 954 sc->sc_flags &= ~CBB_CARDEXIST; 955 if (sc->sc_csc->sc_status & 956 CARDSLOT_STATUS_CARD_16) { 957 #if 0 958 struct pcic_handle *ph = 959 &sc->sc_pcmcia_h; 960 961 pcmcia_card_deactivate(ph->pcmcia); 962 pccbb_pcmcia_socket_disable(ph); 963 pccbb_pcmcia_detach_card(ph, 964 DETACH_FORCE); 965 #endif 966 cardslot_event_throw(sc->sc_csc, 967 CARDSLOT_EVENT_REMOVAL_16); 968 } else if (sc->sc_csc->sc_status & 969 CARDSLOT_STATUS_CARD_CB) { 970 /* Cardbus intr removed */ 971 cardslot_event_throw(sc->sc_csc, 972 CARDSLOT_EVENT_REMOVAL_CB); 973 } 974 } 975 } else if (0x00 == (sockstate & CB_SOCKET_STAT_CD) && 976 /* 977 * The pccbbintr may called from powerdown hook when 978 * the system resumed, to detect the card 979 * insertion/removal during suspension. 980 */ 981 (sc->sc_flags & CBB_CARDEXIST) == 0) { 982 if (sc->sc_flags & CBB_INSERTING) { 983 timeout_del(&sc->sc_ins_tmo); 984 } 985 timeout_add(&sc->sc_ins_tmo, hz / 10); 986 sc->sc_flags |= CBB_INSERTING; 987 } 988 } 989 990 return (1); 991 } 992 993 /* 994 * int pccbbintr_function(struct pccbb_softc *sc) 995 * 996 * This function calls each interrupt handler registered at the 997 * bridge. The interrupt handlers are called in registered order. 998 */ 999 int 1000 pccbbintr_function(sc) 1001 struct pccbb_softc *sc; 1002 { 1003 int retval = 0, val; 1004 struct pccbb_intrhand_list *pil; 1005 int s, splchanged; 1006 1007 for (pil = sc->sc_pil; pil != NULL; pil = pil->pil_next) { 1008 /* 1009 * XXX priority change. gross. I use if-else 1010 * sentense instead of switch-case sentense because of 1011 * avoiding duplicate case value error. More than one 1012 * IPL_XXX use same value. It depends on 1013 * implementation. 1014 */ 1015 splchanged = 1; 1016 #if 0 1017 if (pil->pil_level == IPL_SERIAL) { 1018 s = splserial(); 1019 } else if (pil->pil_level == IPL_HIGH) { 1020 #endif 1021 if (pil->pil_level == IPL_HIGH) { 1022 s = splhigh(); 1023 } else if (pil->pil_level == IPL_CLOCK) { 1024 s = splclock(); 1025 } else if (pil->pil_level == IPL_AUDIO) { 1026 s = splaudio(); 1027 } else if (pil->pil_level == IPL_IMP) { 1028 s = splimp(); 1029 } else if (pil->pil_level == IPL_TTY) { 1030 s = spltty(); 1031 #if 0 1032 } else if (pil->pil_level == IPL_SOFTSERIAL) { 1033 s = splsoftserial(); 1034 #endif 1035 } else if (pil->pil_level == IPL_NET) { 1036 s = splnet(); 1037 } else { 1038 splchanged = 0; 1039 /* XXX: ih lower than IPL_BIO runs w/ IPL_BIO. */ 1040 } 1041 1042 val = (*pil->pil_func)(pil->pil_arg); 1043 1044 if (splchanged != 0) { 1045 splx(s); 1046 } 1047 1048 retval = retval == 1 ? 1 : 1049 retval == 0 ? val : val != 0 ? val : retval; 1050 } 1051 1052 return retval; 1053 } 1054 1055 void 1056 pci113x_insert(arg) 1057 void *arg; 1058 { 1059 struct pccbb_softc *sc = (struct pccbb_softc *)arg; 1060 u_int32_t sockevent, sockstate; 1061 1062 sockevent = bus_space_read_4(sc->sc_base_memt, sc->sc_base_memh, 1063 CB_SOCKET_EVENT); 1064 sockstate = bus_space_read_4(sc->sc_base_memt, sc->sc_base_memh, 1065 CB_SOCKET_STAT); 1066 1067 if (0 == (sockstate & CB_SOCKET_STAT_CD)) { /* card exist */ 1068 DPRINTF(("%s: 0x%08x", sc->sc_dev.dv_xname, sockevent)); 1069 DPRINTF((" card inserted, 0x%08x\n", sockstate)); 1070 sc->sc_flags |= CBB_CARDEXIST; 1071 /* call pccard interrupt handler here */ 1072 if (sockstate & CB_SOCKET_STAT_16BIT) { 1073 /* 16-bit card found */ 1074 /* pccbb_pcmcia_attach_card(&sc->sc_pcmcia_h); */ 1075 cardslot_event_throw(sc->sc_csc, 1076 CARDSLOT_EVENT_INSERTION_16); 1077 } else if (sockstate & CB_SOCKET_STAT_CB) { 1078 /* cardbus card found */ 1079 /* cardbus_attach_card(sc->sc_csc); */ 1080 cardslot_event_throw(sc->sc_csc, 1081 CARDSLOT_EVENT_INSERTION_CB); 1082 } else { 1083 /* who are you? */ 1084 } 1085 } else { 1086 timeout_add(&sc->sc_ins_tmo, hz / 10); 1087 } 1088 } 1089 1090 #define PCCBB_PCMCIA_OFFSET 0x800 1091 u_int8_t 1092 pccbb_pcmcia_read(ph, reg) 1093 struct pcic_handle *ph; 1094 int reg; 1095 { 1096 bus_space_barrier(ph->ph_bus_t, ph->ph_bus_h, 1097 PCCBB_PCMCIA_OFFSET + reg, 1, BUS_SPACE_BARRIER_READ); 1098 1099 return bus_space_read_1(ph->ph_bus_t, ph->ph_bus_h, 1100 PCCBB_PCMCIA_OFFSET + reg); 1101 } 1102 1103 void 1104 pccbb_pcmcia_write(ph, reg, val) 1105 struct pcic_handle *ph; 1106 int reg; 1107 u_int8_t val; 1108 { 1109 bus_space_barrier(ph->ph_bus_t, ph->ph_bus_h, 1110 PCCBB_PCMCIA_OFFSET + reg, 1, BUS_SPACE_BARRIER_WRITE); 1111 1112 bus_space_write_1(ph->ph_bus_t, ph->ph_bus_h, PCCBB_PCMCIA_OFFSET + reg, 1113 val); 1114 } 1115 1116 /* 1117 * int pccbb_ctrl(cardbus_chipset_tag_t, int) 1118 */ 1119 int 1120 pccbb_ctrl(ct, command) 1121 cardbus_chipset_tag_t ct; 1122 int command; 1123 { 1124 struct pccbb_softc *sc = (struct pccbb_softc *)ct; 1125 1126 switch (command) { 1127 case CARDBUS_CD: 1128 if (2 == pccbb_detect_card(sc)) { 1129 int retval = 0; 1130 int status = cb_detect_voltage(sc); 1131 if (PCCARD_VCC_5V & status) { 1132 retval |= CARDBUS_5V_CARD; 1133 } 1134 if (PCCARD_VCC_3V & status) { 1135 retval |= CARDBUS_3V_CARD; 1136 } 1137 if (PCCARD_VCC_XV & status) { 1138 retval |= CARDBUS_XV_CARD; 1139 } 1140 if (PCCARD_VCC_YV & status) { 1141 retval |= CARDBUS_YV_CARD; 1142 } 1143 return retval; 1144 } else { 1145 return 0; 1146 } 1147 break; 1148 case CARDBUS_RESET: 1149 return cb_reset(sc); 1150 break; 1151 case CARDBUS_IO_ENABLE: /* fallthrough */ 1152 case CARDBUS_IO_DISABLE: /* fallthrough */ 1153 case CARDBUS_MEM_ENABLE: /* fallthrough */ 1154 case CARDBUS_MEM_DISABLE: /* fallthrough */ 1155 case CARDBUS_BM_ENABLE: /* fallthrough */ 1156 case CARDBUS_BM_DISABLE: /* fallthrough */ 1157 return pccbb_cardenable(sc, command); 1158 break; 1159 } 1160 1161 return 0; 1162 } 1163 1164 /* 1165 * int pccbb_power(cardbus_chipset_tag_t, int) 1166 * This function returns true when it succeeds and returns false when 1167 * it fails. 1168 */ 1169 int 1170 pccbb_power(ct, command) 1171 cardbus_chipset_tag_t ct; 1172 int command; 1173 { 1174 struct pccbb_softc *sc = (struct pccbb_softc *)ct; 1175 1176 u_int32_t status, sock_ctrl; 1177 bus_space_tag_t memt = sc->sc_base_memt; 1178 bus_space_handle_t memh = sc->sc_base_memh; 1179 1180 DPRINTF(("pccbb_power: %s and %s [%x]\n", 1181 (command & CARDBUS_VCCMASK) == CARDBUS_VCC_UC ? "CARDBUS_VCC_UC" : 1182 (command & CARDBUS_VCCMASK) == CARDBUS_VCC_5V ? "CARDBUS_VCC_5V" : 1183 (command & CARDBUS_VCCMASK) == CARDBUS_VCC_3V ? "CARDBUS_VCC_3V" : 1184 (command & CARDBUS_VCCMASK) == CARDBUS_VCC_XV ? "CARDBUS_VCC_XV" : 1185 (command & CARDBUS_VCCMASK) == CARDBUS_VCC_YV ? "CARDBUS_VCC_YV" : 1186 (command & CARDBUS_VCCMASK) == CARDBUS_VCC_0V ? "CARDBUS_VCC_0V" : 1187 "UNKNOWN", 1188 (command & CARDBUS_VPPMASK) == CARDBUS_VPP_UC ? "CARDBUS_VPP_UC" : 1189 (command & CARDBUS_VPPMASK) == CARDBUS_VPP_12V ? "CARDBUS_VPP_12V" : 1190 (command & CARDBUS_VPPMASK) == CARDBUS_VPP_VCC ? "CARDBUS_VPP_VCC" : 1191 (command & CARDBUS_VPPMASK) == CARDBUS_VPP_0V ? "CARDBUS_VPP_0V" : 1192 "UNKNOWN", command)); 1193 1194 status = bus_space_read_4(memt, memh, CB_SOCKET_STAT); 1195 sock_ctrl = bus_space_read_4(memt, memh, CB_SOCKET_CTRL); 1196 1197 switch (command & CARDBUS_VCCMASK) { 1198 case CARDBUS_VCC_UC: 1199 break; 1200 case CARDBUS_VCC_5V: 1201 if (CB_SOCKET_STAT_5VCARD & status) { /* check 5 V card */ 1202 sock_ctrl &= ~CB_SOCKET_CTRL_VCCMASK; 1203 sock_ctrl |= CB_SOCKET_CTRL_VCC_5V; 1204 } else { 1205 printf("%s: BAD voltage request: no 5 V card\n", 1206 sc->sc_dev.dv_xname); 1207 } 1208 break; 1209 case CARDBUS_VCC_3V: 1210 if (CB_SOCKET_STAT_3VCARD & status) { 1211 sock_ctrl &= ~CB_SOCKET_CTRL_VCCMASK; 1212 sock_ctrl |= CB_SOCKET_CTRL_VCC_3V; 1213 } else { 1214 printf("%s: BAD voltage request: no 3.3 V card\n", 1215 sc->sc_dev.dv_xname); 1216 } 1217 break; 1218 case CARDBUS_VCC_0V: 1219 sock_ctrl &= ~CB_SOCKET_CTRL_VCCMASK; 1220 break; 1221 default: 1222 return 0; /* power NEVER changed */ 1223 break; 1224 } 1225 1226 switch (command & CARDBUS_VPPMASK) { 1227 case CARDBUS_VPP_UC: 1228 break; 1229 case CARDBUS_VPP_0V: 1230 sock_ctrl &= ~CB_SOCKET_CTRL_VPPMASK; 1231 break; 1232 case CARDBUS_VPP_VCC: 1233 sock_ctrl &= ~CB_SOCKET_CTRL_VPPMASK; 1234 sock_ctrl |= ((sock_ctrl >> 4) & 0x07); 1235 break; 1236 case CARDBUS_VPP_12V: 1237 sock_ctrl &= ~CB_SOCKET_CTRL_VPPMASK; 1238 sock_ctrl |= CB_SOCKET_CTRL_VPP_12V; 1239 break; 1240 } 1241 1242 #if 0 1243 DPRINTF(("sock_ctrl: %x\n", sock_ctrl)); 1244 #endif 1245 bus_space_write_4(memt, memh, CB_SOCKET_CTRL, sock_ctrl); 1246 status = bus_space_read_4(memt, memh, CB_SOCKET_STAT); 1247 1248 if (status & CB_SOCKET_STAT_BADVCC) { /* bad Vcc request */ 1249 printf 1250 ("%s: bad Vcc request. sock_ctrl 0x%x, sock_status 0x%x\n", 1251 sc->sc_dev.dv_xname, sock_ctrl, status); 1252 DPRINTF(("pccbb_power: %s and %s [%x]\n", 1253 (command & CARDBUS_VCCMASK) == 1254 CARDBUS_VCC_UC ? "CARDBUS_VCC_UC" : (command & 1255 CARDBUS_VCCMASK) == 1256 CARDBUS_VCC_5V ? "CARDBUS_VCC_5V" : (command & 1257 CARDBUS_VCCMASK) == 1258 CARDBUS_VCC_3V ? "CARDBUS_VCC_3V" : (command & 1259 CARDBUS_VCCMASK) == 1260 CARDBUS_VCC_XV ? "CARDBUS_VCC_XV" : (command & 1261 CARDBUS_VCCMASK) == 1262 CARDBUS_VCC_YV ? "CARDBUS_VCC_YV" : (command & 1263 CARDBUS_VCCMASK) == 1264 CARDBUS_VCC_0V ? "CARDBUS_VCC_0V" : "UNKNOWN", 1265 (command & CARDBUS_VPPMASK) == 1266 CARDBUS_VPP_UC ? "CARDBUS_VPP_UC" : (command & 1267 CARDBUS_VPPMASK) == 1268 CARDBUS_VPP_12V ? "CARDBUS_VPP_12V" : (command & 1269 CARDBUS_VPPMASK) == 1270 CARDBUS_VPP_VCC ? "CARDBUS_VPP_VCC" : (command & 1271 CARDBUS_VPPMASK) == 1272 CARDBUS_VPP_0V ? "CARDBUS_VPP_0V" : "UNKNOWN", command)); 1273 #if 0 1274 if (command == (CARDBUS_VCC_0V | CARDBUS_VPP_0V)) { 1275 u_int32_t force = 1276 bus_space_read_4(memt, memh, CB_SOCKET_FORCE); 1277 /* Reset Bad Vcc request */ 1278 force &= ~CB_SOCKET_FORCE_BADVCC; 1279 bus_space_write_4(memt, memh, CB_SOCKET_FORCE, force); 1280 printf("new status 0x%x\n", bus_space_read_4(memt, memh, 1281 CB_SOCKET_STAT)); 1282 return 1; 1283 } 1284 #endif 1285 return 0; 1286 } 1287 1288 /* 1289 * XXX delay 300 ms: though the standard defines that the Vcc set-up 1290 * time is 20 ms, some PC-Card bridge requires longer duration. 1291 */ 1292 delay(300 * 1000); 1293 1294 return 1; /* power changed correctly */ 1295 } 1296 1297 #if defined CB_PCMCIA_POLL 1298 struct cb_poll_str { 1299 void *arg; 1300 int (*func)(void *); 1301 int level; 1302 pccard_chipset_tag_t ct; 1303 int count; 1304 }; 1305 1306 static struct cb_poll_str cb_poll[10]; 1307 static int cb_poll_n = 0; 1308 static struct timeout cb_poll_timeout; 1309 1310 void cb_pcmcia_poll(void *arg); 1311 1312 void 1313 cb_pcmcia_poll(arg) 1314 void *arg; 1315 { 1316 struct cb_poll_str *poll = arg; 1317 struct cbb_pcmcia_softc *psc = (void *)poll->ct->v; 1318 struct pccbb_softc *sc = psc->cpc_parent; 1319 int s; 1320 u_int32_t spsr; /* socket present-state reg */ 1321 1322 timeout_set(&cb_poll_timeout, cb_pcmcia_poll, arg); 1323 timeout_add(&cb_poll_timeout, hz / 10); 1324 switch (poll->level) { 1325 case IPL_NET: 1326 s = splnet(); 1327 break; 1328 case IPL_BIO: 1329 s = splbio(); 1330 break; 1331 case IPL_TTY: /* fallthrough */ 1332 default: 1333 s = spltty(); 1334 break; 1335 } 1336 1337 spsr = 1338 bus_space_read_4(sc->sc_base_memt, sc->sc_base_memh, 1339 CB_SOCKET_STAT); 1340 1341 #if defined CB_PCMCIA_POLL_ONLY && defined LEVEL2 1342 if (!(spsr & 0x40)) { /* CINT low */ 1343 #else 1344 if (1) { 1345 #endif 1346 if ((*poll->func) (poll->arg) == 1) { 1347 ++poll->count; 1348 printf("intr: reported from poller, 0x%x\n", spsr); 1349 #if defined LEVEL2 1350 } else { 1351 printf("intr: miss! 0x%x\n", spsr); 1352 #endif 1353 } 1354 } 1355 splx(s); 1356 } 1357 #endif /* defined CB_PCMCIA_POLL */ 1358 1359 /* 1360 * int pccbb_detect_card(struct pccbb_softc *sc) 1361 * return value: 0 if no card exists. 1362 * 1 if 16-bit card exists. 1363 * 2 if cardbus card exists. 1364 */ 1365 int 1366 pccbb_detect_card(sc) 1367 struct pccbb_softc *sc; 1368 { 1369 bus_space_handle_t base_memh = sc->sc_base_memh; 1370 bus_space_tag_t base_memt = sc->sc_base_memt; 1371 u_int32_t sockstat = 1372 bus_space_read_4(base_memt, base_memh, CB_SOCKET_STAT); 1373 int retval = 0; 1374 1375 /* 1376 * The SCM Microsystems TI1225-based PCI-CardBus dock card that 1377 * ships with some Lucent WaveLAN cards has only one physical slot 1378 * but OpenBSD probes two. The phantom card in the second slot can 1379 * be ignored by punting on unsupported voltages. 1380 */ 1381 if (sockstat & CB_SOCKET_STAT_XVCARD) 1382 return 0; 1383 1384 /* CD1 and CD2 asserted */ 1385 if (0x00 == (sockstat & CB_SOCKET_STAT_CD)) { 1386 /* card must be present */ 1387 if (!(CB_SOCKET_STAT_NOTCARD & sockstat)) { 1388 /* NOTACARD DEASSERTED */ 1389 if (CB_SOCKET_STAT_CB & sockstat) { 1390 /* CardBus mode */ 1391 retval = 2; 1392 } else if (CB_SOCKET_STAT_16BIT & sockstat) { 1393 /* 16-bit mode */ 1394 retval = 1; 1395 } 1396 } 1397 } 1398 return retval; 1399 } 1400 1401 /* 1402 * int cb_reset(struct pccbb_softc *sc) 1403 * This function resets CardBus card. 1404 */ 1405 int 1406 cb_reset(sc) 1407 struct pccbb_softc *sc; 1408 { 1409 /* 1410 * Reset Assert at least 20 ms 1411 * Some machines request longer duration. 1412 */ 1413 int reset_duration = 1414 (sc->sc_chipset == CB_RX5C47X ? 400 * 1000 : 40 * 1000); 1415 u_int32_t bcr = pci_conf_read(sc->sc_pc, sc->sc_tag, PCI_BCR_INTR); 1416 1417 /* Reset bit Assert (bit 6 at 0x3E) */ 1418 bcr |= CB_BCR_RESET_ENABLE; 1419 pci_conf_write(sc->sc_pc, sc->sc_tag, PCI_BCR_INTR, bcr); 1420 delay(reset_duration); 1421 1422 if (CBB_CARDEXIST & sc->sc_flags) { /* A card exists. Reset it! */ 1423 /* Reset bit Deassert (bit 6 at 0x3E) */ 1424 bcr &= ~CB_BCR_RESET_ENABLE; 1425 pci_conf_write(sc->sc_pc, sc->sc_tag, PCI_BCR_INTR, bcr); 1426 delay(reset_duration); 1427 } 1428 /* No card found on the slot. Keep Reset. */ 1429 return 1; 1430 } 1431 1432 /* 1433 * int cb_detect_voltage(struct pccbb_softc *sc) 1434 * This function detect card Voltage. 1435 */ 1436 int 1437 cb_detect_voltage(sc) 1438 struct pccbb_softc *sc; 1439 { 1440 u_int32_t psr; /* socket present-state reg */ 1441 bus_space_tag_t iot = sc->sc_base_memt; 1442 bus_space_handle_t ioh = sc->sc_base_memh; 1443 int vol = PCCARD_VCC_UKN; /* set 0 */ 1444 1445 psr = bus_space_read_4(iot, ioh, CB_SOCKET_STAT); 1446 1447 if (0x400u & psr) { 1448 vol |= PCCARD_VCC_5V; 1449 } 1450 if (0x800u & psr) { 1451 vol |= PCCARD_VCC_3V; 1452 } 1453 1454 return vol; 1455 } 1456 1457 int 1458 cbbprint(aux, pcic) 1459 void *aux; 1460 const char *pcic; 1461 { 1462 /* 1463 struct cbslot_attach_args *cba = aux; 1464 1465 if (cba->cba_slot >= 0) { 1466 printf(" slot %d", cba->cba_slot); 1467 } 1468 */ 1469 return UNCONF; 1470 } 1471 1472 /* 1473 * int pccbb_cardenable(struct pccbb_softc *sc, int function) 1474 * This function enables and disables the card 1475 */ 1476 int 1477 pccbb_cardenable(sc, function) 1478 struct pccbb_softc *sc; 1479 int function; 1480 { 1481 u_int32_t command = 1482 pci_conf_read(sc->sc_pc, sc->sc_tag, PCI_COMMAND_STATUS_REG); 1483 1484 DPRINTF(("pccbb_cardenable:")); 1485 switch (function) { 1486 case CARDBUS_IO_ENABLE: 1487 command |= PCI_COMMAND_IO_ENABLE; 1488 break; 1489 case CARDBUS_IO_DISABLE: 1490 command &= ~PCI_COMMAND_IO_ENABLE; 1491 break; 1492 case CARDBUS_MEM_ENABLE: 1493 command |= PCI_COMMAND_MEM_ENABLE; 1494 break; 1495 case CARDBUS_MEM_DISABLE: 1496 command &= ~PCI_COMMAND_MEM_ENABLE; 1497 break; 1498 case CARDBUS_BM_ENABLE: 1499 command |= PCI_COMMAND_MASTER_ENABLE; 1500 break; 1501 case CARDBUS_BM_DISABLE: 1502 command &= ~PCI_COMMAND_MASTER_ENABLE; 1503 break; 1504 default: 1505 return 0; 1506 } 1507 1508 pci_conf_write(sc->sc_pc, sc->sc_tag, PCI_COMMAND_STATUS_REG, command); 1509 DPRINTF((" command reg 0x%x\n", command)); 1510 return 1; 1511 } 1512 1513 #if !rbus 1514 /* 1515 * int pccbb_io_open(cardbus_chipset_tag_t, int, u_int32_t, u_int32_t) 1516 */ 1517 int 1518 pccbb_io_open(ct, win, start, end) 1519 cardbus_chipset_tag_t ct; 1520 int win; 1521 u_int32_t start, end; 1522 { 1523 struct pccbb_softc *sc = (struct pccbb_softc *)ct; 1524 int basereg; 1525 int limitreg; 1526 1527 if ((win < 0) || (win > 2)) { 1528 #if defined DIAGNOSTIC 1529 printf("cardbus_io_open: window out of range %d\n", win); 1530 #endif 1531 return 0; 1532 } 1533 1534 basereg = win * 8 + 0x2c; 1535 limitreg = win * 8 + 0x30; 1536 1537 DPRINTF(("pccbb_io_open: 0x%x[0x%x] - 0x%x[0x%x]\n", 1538 start, basereg, end, limitreg)); 1539 1540 pci_conf_write(sc->sc_pc, sc->sc_tag, basereg, start); 1541 pci_conf_write(sc->sc_pc, sc->sc_tag, limitreg, end); 1542 return 1; 1543 } 1544 1545 /* 1546 * int pccbb_io_close(cardbus_chipset_tag_t, int) 1547 */ 1548 int 1549 pccbb_io_close(ct, win) 1550 cardbus_chipset_tag_t ct; 1551 int win; 1552 { 1553 struct pccbb_softc *sc = (struct pccbb_softc *)ct; 1554 int basereg; 1555 int limitreg; 1556 1557 if ((win < 0) || (win > 2)) { 1558 #if defined DIAGNOSTIC 1559 printf("cardbus_io_close: window out of range %d\n", win); 1560 #endif 1561 return 0; 1562 } 1563 1564 basereg = win * 8 + 0x2c; 1565 limitreg = win * 8 + 0x30; 1566 1567 pci_conf_write(sc->sc_pc, sc->sc_tag, basereg, 0); 1568 pci_conf_write(sc->sc_pc, sc->sc_tag, limitreg, 0); 1569 return 1; 1570 } 1571 1572 /* 1573 * int pccbb_mem_open(cardbus_chipset_tag_t, int, u_int32_t, u_int32_t) 1574 */ 1575 int 1576 pccbb_mem_open(ct, win, start, end) 1577 cardbus_chipset_tag_t ct; 1578 int win; 1579 u_int32_t start, end; 1580 { 1581 struct pccbb_softc *sc = (struct pccbb_softc *)ct; 1582 int basereg; 1583 int limitreg; 1584 1585 if ((win < 0) || (win > 2)) { 1586 #if defined DIAGNOSTIC 1587 printf("cardbus_mem_open: window out of range %d\n", win); 1588 #endif 1589 return 0; 1590 } 1591 1592 basereg = win * 8 + 0x1c; 1593 limitreg = win * 8 + 0x20; 1594 1595 pci_conf_write(sc->sc_pc, sc->sc_tag, basereg, start); 1596 pci_conf_write(sc->sc_pc, sc->sc_tag, limitreg, end); 1597 return 1; 1598 } 1599 1600 /* 1601 * int pccbb_mem_close(cardbus_chipset_tag_t, int) 1602 */ 1603 int 1604 pccbb_mem_close(ct, win) 1605 cardbus_chipset_tag_t ct; 1606 int win; 1607 { 1608 struct pccbb_softc *sc = (struct pccbb_softc *)ct; 1609 int basereg; 1610 int limitreg; 1611 1612 if ((win < 0) || (win > 2)) { 1613 #if defined DIAGNOSTIC 1614 printf("cardbus_mem_close: window out of range %d\n", win); 1615 #endif 1616 return 0; 1617 } 1618 1619 basereg = win * 8 + 0x1c; 1620 limitreg = win * 8 + 0x20; 1621 1622 pci_conf_write(sc->sc_pc, sc->sc_tag, basereg, 0); 1623 pci_conf_write(sc->sc_pc, sc->sc_tag, limitreg, 0); 1624 return 1; 1625 } 1626 #endif 1627 1628 /* 1629 * void *pccbb_cb_intr_establish(cardbus_chipset_tag_t ct, 1630 * int irq, 1631 * int level, 1632 * int (* func)(void *), 1633 * void *arg) 1634 * 1635 * This function registers an interrupt handler at the bridge, in 1636 * order not to call the interrupt handlers of child devices when 1637 * a card-deletion interrupt occurs. 1638 * 1639 * The arguments irq is not used because pccbb selects intr vector. 1640 */ 1641 void * 1642 pccbb_cb_intr_establish(ct, irq, level, func, arg) 1643 cardbus_chipset_tag_t ct; 1644 int irq, level; 1645 int (*func)(void *); 1646 void *arg; 1647 { 1648 struct pccbb_softc *sc = (struct pccbb_softc *)ct; 1649 1650 return pccbb_intr_establish(sc, irq, level, func, arg); 1651 } 1652 1653 1654 /* 1655 * void *pccbb_cb_intr_disestablish(cardbus_chipset_tag_t ct, 1656 * void *ih) 1657 * 1658 * This function removes an interrupt handler pointed by ih. 1659 */ 1660 void 1661 pccbb_cb_intr_disestablish(ct, ih) 1662 cardbus_chipset_tag_t ct; 1663 void *ih; 1664 { 1665 struct pccbb_softc *sc = (struct pccbb_softc *)ct; 1666 1667 pccbb_intr_disestablish(sc, ih); 1668 } 1669 1670 1671 /* 1672 * void *pccbb_intr_establish(struct pccbb_softc *sc, 1673 * int irq, 1674 * int level, 1675 * int (* func)(void *), 1676 * void *arg) 1677 * 1678 * This function registers an interrupt handler at the bridge, in 1679 * order not to call the interrupt handlers of child devices when 1680 * a card-deletion interrupt occurs. 1681 * 1682 * The arguments irq and level are not used. 1683 */ 1684 void * 1685 pccbb_intr_establish(sc, irq, level, func, arg) 1686 struct pccbb_softc *sc; 1687 int irq, level; 1688 int (*func)(void *); 1689 void *arg; 1690 { 1691 struct pccbb_intrhand_list *pil, *newpil; 1692 pcireg_t reg; 1693 1694 DPRINTF(("pccbb_intr_establish start. %p\n", sc->sc_pil)); 1695 1696 if (sc->sc_pil == NULL) { 1697 /* initialize bridge intr routing */ 1698 reg = pci_conf_read(sc->sc_pc, sc->sc_tag, PCI_BCR_INTR); 1699 reg &= ~CB_BCR_INTR_IREQ_ENABLE; 1700 pci_conf_write(sc->sc_pc, sc->sc_tag, PCI_BCR_INTR, reg); 1701 1702 switch (sc->sc_chipset) { 1703 case CB_TI113X: 1704 reg = pci_conf_read(sc->sc_pc, sc->sc_tag, PCI_CBCTRL); 1705 /* functional intr enabled */ 1706 reg |= PCI113X_CBCTRL_PCI_INTR; 1707 pci_conf_write(sc->sc_pc, sc->sc_tag, PCI_CBCTRL, reg); 1708 break; 1709 default: 1710 break; 1711 } 1712 } 1713 1714 /* 1715 * Allocate a room for interrupt handler structure. 1716 */ 1717 newpil = (struct pccbb_intrhand_list *) 1718 malloc(sizeof(struct pccbb_intrhand_list), M_DEVBUF, M_WAITOK); 1719 1720 newpil->pil_func = func; 1721 newpil->pil_arg = arg; 1722 newpil->pil_level = level; 1723 newpil->pil_next = NULL; 1724 1725 if (sc->sc_pil == NULL) { 1726 sc->sc_pil = newpil; 1727 } else { 1728 for (pil = sc->sc_pil; pil->pil_next != NULL; 1729 pil = pil->pil_next); 1730 pil->pil_next = newpil; 1731 } 1732 1733 DPRINTF(("pccbb_intr_establish add pil. %p\n", sc->sc_pil)); 1734 1735 return newpil; 1736 } 1737 1738 /* 1739 * void *pccbb_intr_disestablish(struct pccbb_softc *sc, 1740 * void *ih) 1741 * 1742 * This function removes an interrupt handler pointed by ih. 1743 */ 1744 void 1745 pccbb_intr_disestablish(sc, ih) 1746 struct pccbb_softc *sc; 1747 void *ih; 1748 { 1749 struct pccbb_intrhand_list *pil, **pil_prev; 1750 pcireg_t reg; 1751 1752 DPRINTF(("pccbb_intr_disestablish start. %p\n", sc->sc_pil)); 1753 1754 pil_prev = &sc->sc_pil; 1755 1756 for (pil = sc->sc_pil; pil != NULL; pil = pil->pil_next) { 1757 if (pil == ih) { 1758 *pil_prev = pil->pil_next; 1759 free(pil, M_DEVBUF); 1760 DPRINTF(("pccbb_intr_disestablish frees one pil\n")); 1761 break; 1762 } 1763 pil_prev = &pil->pil_next; 1764 } 1765 1766 if (sc->sc_pil == NULL) { 1767 /* No interrupt handlers */ 1768 1769 DPRINTF(("pccbb_intr_disestablish: no interrupt handler\n")); 1770 1771 /* stop routing PCI intr */ 1772 reg = pci_conf_read(sc->sc_pc, sc->sc_tag, PCI_BCR_INTR); 1773 reg |= CB_BCR_INTR_IREQ_ENABLE; 1774 pci_conf_write(sc->sc_pc, sc->sc_tag, PCI_BCR_INTR, reg); 1775 1776 switch (sc->sc_chipset) { 1777 case CB_TI113X: 1778 reg = pci_conf_read(sc->sc_pc, sc->sc_tag, PCI_CBCTRL); 1779 /* functional intr disabled */ 1780 reg &= ~PCI113X_CBCTRL_PCI_INTR; 1781 pci_conf_write(sc->sc_pc, sc->sc_tag, PCI_CBCTRL, reg); 1782 break; 1783 default: 1784 break; 1785 } 1786 } 1787 } 1788 1789 #if defined SHOW_REGS 1790 void 1791 cb_show_regs(pc, tag, memt, memh) 1792 pci_chipset_tag_t pc; 1793 pcitag_t tag; 1794 bus_space_tag_t memt; 1795 bus_space_handle_t memh; 1796 { 1797 int i; 1798 printf("PCI config regs:"); 1799 for (i = 0; i < 0x50; i += 4) { 1800 if (i % 16 == 0) { 1801 printf("\n 0x%02x:", i); 1802 } 1803 printf(" %08x", pci_conf_read(pc, tag, i)); 1804 } 1805 for (i = 0x80; i < 0xb0; i += 4) { 1806 if (i % 16 == 0) { 1807 printf("\n 0x%02x:", i); 1808 } 1809 printf(" %08x", pci_conf_read(pc, tag, i)); 1810 } 1811 1812 if (memh == 0) { 1813 printf("\n"); 1814 return; 1815 } 1816 1817 printf("\nsocket regs:"); 1818 for (i = 0; i <= 0x10; i += 0x04) { 1819 printf(" %08x", bus_space_read_4(memt, memh, i)); 1820 } 1821 printf("\nExCA regs:"); 1822 for (i = 0; i < 0x08; ++i) { 1823 printf(" %02x", bus_space_read_1(memt, memh, 0x800 + i)); 1824 } 1825 printf("\n"); 1826 return; 1827 } 1828 #endif 1829 1830 /* 1831 * cardbustag_t pccbb_make_tag(cardbus_chipset_tag_t cc, 1832 * int busno, int devno, int function) 1833 * This is the function to make a tag to access config space of 1834 * a CardBus Card. It works same as pci_conf_read. 1835 */ 1836 cardbustag_t 1837 pccbb_make_tag(cc, busno, devno, function) 1838 cardbus_chipset_tag_t cc; 1839 int busno, devno, function; 1840 { 1841 struct pccbb_softc *sc = (struct pccbb_softc *)cc; 1842 1843 return pci_make_tag(sc->sc_pc, busno, devno, function); 1844 } 1845 1846 void 1847 pccbb_free_tag(cc, tag) 1848 cardbus_chipset_tag_t cc; 1849 cardbustag_t tag; 1850 { 1851 } 1852 1853 /* 1854 * cardbusreg_t pccbb_conf_read(cardbus_chipset_tag_t cc, 1855 * cardbustag_t tag, int offset) 1856 * This is the function to read the config space of a CardBus Card. 1857 * It works same as pci_conf_read. 1858 */ 1859 cardbusreg_t 1860 pccbb_conf_read(cc, tag, offset) 1861 cardbus_chipset_tag_t cc; 1862 cardbustag_t tag; 1863 int offset; /* register offset */ 1864 { 1865 struct pccbb_softc *sc = (struct pccbb_softc *)cc; 1866 1867 return pci_conf_read(sc->sc_pc, tag, offset); 1868 } 1869 1870 /* 1871 * void pccbb_conf_write(cardbus_chipset_tag_t cc, cardbustag_t tag, 1872 * int offs, cardbusreg_t val) 1873 * This is the function to write the config space of a CardBus Card. 1874 * It works same as pci_conf_write. 1875 */ 1876 void 1877 pccbb_conf_write(cc, tag, reg, val) 1878 cardbus_chipset_tag_t cc; 1879 cardbustag_t tag; 1880 int reg; /* register offset */ 1881 cardbusreg_t val; 1882 { 1883 struct pccbb_softc *sc = (struct pccbb_softc *)cc; 1884 1885 pci_conf_write(sc->sc_pc, tag, reg, val); 1886 } 1887 1888 #if 0 1889 int 1890 pccbb_new_pcmcia_io_alloc(pcmcia_chipset_handle_t pch, 1891 bus_addr_t start, bus_size_t size, bus_size_t align, bus_addr_t mask, 1892 int speed, int flags, 1893 bus_space_handle_t * iohp) 1894 #endif 1895 /* 1896 * int pccbb_pcmcia_io_alloc(pcmcia_chipset_handle_t pch, 1897 * bus_addr_t start, bus_size_t size, 1898 * bus_size_t align, 1899 * struct pcmcia_io_handle *pcihp 1900 * 1901 * This function only allocates I/O region for pccard. This function 1902 * never maps the allocated region to pccard I/O area. 1903 * 1904 * XXX: The interface of this function is not very good, I believe. 1905 */ 1906 int 1907 pccbb_pcmcia_io_alloc(pch, start, size, align, pcihp) 1908 pcmcia_chipset_handle_t pch; 1909 bus_addr_t start; /* start address */ 1910 bus_size_t size; 1911 bus_size_t align; 1912 struct pcmcia_io_handle *pcihp; 1913 { 1914 struct pcic_handle *ph = (struct pcic_handle *)pch; 1915 bus_addr_t ioaddr; 1916 int flags = 0; 1917 bus_space_tag_t iot; 1918 bus_space_handle_t ioh; 1919 #if rbus 1920 rbus_tag_t rb; 1921 #endif 1922 if (align == 0) { 1923 align = size; /* XXX: funny??? */ 1924 } 1925 1926 /* 1927 * Allocate some arbitrary I/O space. 1928 */ 1929 1930 iot = ((struct pccbb_softc *)(ph->ph_parent))->sc_iot; 1931 1932 #if rbus 1933 rb = ((struct pccbb_softc *)(ph->ph_parent))->sc_rbus_iot; 1934 /* XXX: I assume all card decode lower 10 bits by its hardware */ 1935 if (rbus_space_alloc(rb, start, size, 0x3ff, align, 0, &ioaddr, &ioh)) { 1936 return 1; 1937 } 1938 #else 1939 if (start) { 1940 ioaddr = start; 1941 if (bus_space_map(iot, start, size, 0, &ioh)) { 1942 return 1; 1943 } 1944 DPRINTF(("pccbb_pcmcia_io_alloc map port %lx+%lx\n", 1945 (u_long) ioaddr, (u_long) size)); 1946 } else { 1947 flags |= PCMCIA_IO_ALLOCATED; 1948 if (bus_space_alloc(iot, 0x700 /* ph->sc->sc_iobase */ , 1949 0x800, /* ph->sc->sc_iobase + ph->sc->sc_iosize */ 1950 size, align, 0, 0, &ioaddr, &ioh)) { 1951 /* No room be able to be get. */ 1952 return 1; 1953 } 1954 DPRINTF(("pccbb_pcmmcia_io_alloc alloc port 0x%lx+0x%lx\n", 1955 (u_long) ioaddr, (u_long) size)); 1956 } 1957 #endif 1958 1959 pcihp->iot = iot; 1960 pcihp->ioh = ioh; 1961 pcihp->addr = ioaddr; 1962 pcihp->size = size; 1963 pcihp->flags = flags; 1964 1965 return 0; 1966 } 1967 1968 /* 1969 * int pccbb_pcmcia_io_free(pcmcia_chipset_handle_t pch, 1970 * struct pcmcia_io_handle *pcihp) 1971 * 1972 * This function only frees I/O region for pccard. 1973 * 1974 * XXX: The interface of this function is not very good, I believe. 1975 */ 1976 void 1977 pccbb_pcmcia_io_free(pch, pcihp) 1978 pcmcia_chipset_handle_t pch; 1979 struct pcmcia_io_handle *pcihp; 1980 { 1981 #if !rbus 1982 bus_space_tag_t iot = pcihp->iot; 1983 #endif 1984 bus_space_handle_t ioh = pcihp->ioh; 1985 bus_size_t size = pcihp->size; 1986 1987 #if rbus 1988 struct pccbb_softc *sc = 1989 (struct pccbb_softc *)((struct pcic_handle *)pch)->ph_parent; 1990 rbus_tag_t rb = sc->sc_rbus_iot; 1991 1992 rbus_space_free(rb, ioh, size, NULL); 1993 #else 1994 if (pcihp->flags & PCMCIA_IO_ALLOCATED) 1995 bus_space_free(iot, ioh, size); 1996 else 1997 bus_space_unmap(iot, ioh, size); 1998 #endif 1999 } 2000 2001 /* 2002 * int pccbb_pcmcia_io_map(pcmcia_chipset_handle_t pch, int width, 2003 * bus_addr_t offset, bus_size_t size, 2004 * struct pcmcia_io_handle *pcihp, 2005 * int *windowp) 2006 * 2007 * This function maps the allocated I/O region to pccard. This function 2008 * never allocates any I/O region for pccard I/O area. I don't 2009 * understand why the original authors of pcmciabus separated alloc and 2010 * map. I believe the two must be unite. 2011 * 2012 * XXX: no wait timing control? 2013 */ 2014 int 2015 pccbb_pcmcia_io_map(pch, width, offset, size, pcihp, windowp) 2016 pcmcia_chipset_handle_t pch; 2017 int width; 2018 bus_addr_t offset; 2019 bus_size_t size; 2020 struct pcmcia_io_handle *pcihp; 2021 int *windowp; 2022 { 2023 struct pcic_handle *ph = (struct pcic_handle *)pch; 2024 bus_addr_t ioaddr = pcihp->addr + offset; 2025 int i, win; 2026 #if defined CBB_DEBUG 2027 static char *width_names[] = { "dynamic", "io8", "io16" }; 2028 #endif 2029 2030 /* Sanity check I/O handle. */ 2031 2032 if (((struct pccbb_softc *)ph->ph_parent)->sc_iot != pcihp->iot) { 2033 panic("pccbb_pcmcia_io_map iot is bogus"); 2034 } 2035 2036 /* XXX Sanity check offset/size. */ 2037 2038 win = -1; 2039 for (i = 0; i < PCIC_IO_WINS; i++) { 2040 if ((ph->ioalloc & (1 << i)) == 0) { 2041 win = i; 2042 ph->ioalloc |= (1 << i); 2043 break; 2044 } 2045 } 2046 2047 if (win == -1) { 2048 return 1; 2049 } 2050 2051 *windowp = win; 2052 2053 /* XXX this is pretty gross */ 2054 2055 DPRINTF(("pccbb_pcmcia_io_map window %d %s port %lx+%lx\n", 2056 win, width_names[width], (u_long) ioaddr, (u_long) size)); 2057 2058 /* XXX wtf is this doing here? */ 2059 2060 #if 0 2061 printf(" port 0x%lx", (u_long) ioaddr); 2062 if (size > 1) { 2063 printf("-0x%lx", (u_long) ioaddr + (u_long) size - 1); 2064 } 2065 #endif 2066 2067 ph->io[win].addr = ioaddr; 2068 ph->io[win].size = size; 2069 ph->io[win].width = width; 2070 2071 /* actual dirty register-value changing in the function below. */ 2072 pccbb_pcmcia_do_io_map(ph, win); 2073 2074 return 0; 2075 } 2076 2077 /* 2078 * void pccbb_pcmcia_do_io_map(struct pcic_handle *h, int win) 2079 * 2080 * This function changes register-value to map I/O region for pccard. 2081 */ 2082 void 2083 pccbb_pcmcia_do_io_map(ph, win) 2084 struct pcic_handle *ph; 2085 int win; 2086 { 2087 static u_int8_t pcic_iowidth[3] = { 2088 PCIC_IOCTL_IO0_IOCS16SRC_CARD, 2089 PCIC_IOCTL_IO0_IOCS16SRC_DATASIZE | 2090 PCIC_IOCTL_IO0_DATASIZE_8BIT, 2091 PCIC_IOCTL_IO0_IOCS16SRC_DATASIZE | 2092 PCIC_IOCTL_IO0_DATASIZE_16BIT, 2093 }; 2094 2095 #define PCIC_SIA_START_LOW 0 2096 #define PCIC_SIA_START_HIGH 1 2097 #define PCIC_SIA_STOP_LOW 2 2098 #define PCIC_SIA_STOP_HIGH 3 2099 2100 int regbase_win = 0x8 + win * 0x04; 2101 u_int8_t ioctl, enable; 2102 2103 DPRINTF( 2104 ("pccbb_pcmcia_do_io_map win %d addr 0x%lx size 0x%lx width %d\n", 2105 win, (long)ph->io[win].addr, (long)ph->io[win].size, 2106 ph->io[win].width * 8)); 2107 2108 Pcic_write(ph, regbase_win + PCIC_SIA_START_LOW, 2109 ph->io[win].addr & 0xff); 2110 Pcic_write(ph, regbase_win + PCIC_SIA_START_HIGH, 2111 (ph->io[win].addr >> 8) & 0xff); 2112 2113 Pcic_write(ph, regbase_win + PCIC_SIA_STOP_LOW, 2114 (ph->io[win].addr + ph->io[win].size - 1) & 0xff); 2115 Pcic_write(ph, regbase_win + PCIC_SIA_STOP_HIGH, 2116 ((ph->io[win].addr + ph->io[win].size - 1) >> 8) & 0xff); 2117 2118 ioctl = Pcic_read(ph, PCIC_IOCTL); 2119 enable = Pcic_read(ph, PCIC_ADDRWIN_ENABLE); 2120 switch (win) { 2121 case 0: 2122 ioctl &= ~(PCIC_IOCTL_IO0_WAITSTATE | PCIC_IOCTL_IO0_ZEROWAIT | 2123 PCIC_IOCTL_IO0_IOCS16SRC_MASK | 2124 PCIC_IOCTL_IO0_DATASIZE_MASK); 2125 ioctl |= pcic_iowidth[ph->io[win].width]; 2126 enable |= PCIC_ADDRWIN_ENABLE_IO0; 2127 break; 2128 case 1: 2129 ioctl &= ~(PCIC_IOCTL_IO1_WAITSTATE | PCIC_IOCTL_IO1_ZEROWAIT | 2130 PCIC_IOCTL_IO1_IOCS16SRC_MASK | 2131 PCIC_IOCTL_IO1_DATASIZE_MASK); 2132 ioctl |= (pcic_iowidth[ph->io[win].width] << 4); 2133 enable |= PCIC_ADDRWIN_ENABLE_IO1; 2134 break; 2135 } 2136 Pcic_write(ph, PCIC_IOCTL, ioctl); 2137 Pcic_write(ph, PCIC_ADDRWIN_ENABLE, enable); 2138 #if defined CBB_DEBUG 2139 { 2140 u_int8_t start_low = 2141 Pcic_read(ph, regbase_win + PCIC_SIA_START_LOW); 2142 u_int8_t start_high = 2143 Pcic_read(ph, regbase_win + PCIC_SIA_START_HIGH); 2144 u_int8_t stop_low = 2145 Pcic_read(ph, regbase_win + PCIC_SIA_STOP_LOW); 2146 u_int8_t stop_high = 2147 Pcic_read(ph, regbase_win + PCIC_SIA_STOP_HIGH); 2148 printf 2149 (" start %02x %02x, stop %02x %02x, ioctl %02x enable %02x\n", 2150 start_low, start_high, stop_low, stop_high, ioctl, enable); 2151 } 2152 #endif 2153 } 2154 2155 /* 2156 * void pccbb_pcmcia_io_unmap(pcmcia_chipset_handle_t *h, int win) 2157 * 2158 * This function unmaps I/O region. No return value. 2159 */ 2160 void 2161 pccbb_pcmcia_io_unmap(pch, win) 2162 pcmcia_chipset_handle_t pch; 2163 int win; 2164 { 2165 struct pcic_handle *ph = (struct pcic_handle *)pch; 2166 int reg; 2167 2168 if (win >= PCIC_IO_WINS || win < 0) { 2169 panic("pccbb_pcmcia_io_unmap: window out of range"); 2170 } 2171 2172 reg = Pcic_read(ph, PCIC_ADDRWIN_ENABLE); 2173 switch (win) { 2174 case 0: 2175 reg &= ~PCIC_ADDRWIN_ENABLE_IO0; 2176 break; 2177 case 1: 2178 reg &= ~PCIC_ADDRWIN_ENABLE_IO1; 2179 break; 2180 } 2181 Pcic_write(ph, PCIC_ADDRWIN_ENABLE, reg); 2182 2183 ph->ioalloc &= ~(1 << win); 2184 } 2185 2186 /* 2187 * void pccbb_pcmcia_wait_ready(struct pcic_handle *ph) 2188 * 2189 * This function enables the card. All information is stored in 2190 * the first argument, pcmcia_chipset_handle_t. 2191 */ 2192 void 2193 pccbb_pcmcia_wait_ready(ph) 2194 struct pcic_handle *ph; 2195 { 2196 int i; 2197 2198 DPRINTF(("pccbb_pcmcia_wait_ready: status 0x%02x\n", 2199 Pcic_read(ph, PCIC_IF_STATUS))); 2200 2201 for (i = 0; i < 10000; i++) { 2202 if (Pcic_read(ph, PCIC_IF_STATUS) & PCIC_IF_STATUS_READY) { 2203 return; 2204 } 2205 delay(500); 2206 #ifdef CBB_DEBUG 2207 if ((i > 5000) && (i % 100 == 99)) 2208 printf("."); 2209 #endif 2210 } 2211 2212 #ifdef DIAGNOSTIC 2213 printf("pcic_wait_ready: ready never happened, status = %02x\n", 2214 Pcic_read(ph, PCIC_IF_STATUS)); 2215 #endif 2216 } 2217 2218 /* 2219 * void pccbb_pcmcia_socket_enable(pcmcia_chipset_handle_t pch) 2220 * 2221 * This function enables the card. All information is stored in 2222 * the first argument, pcmcia_chipset_handle_t. 2223 */ 2224 void 2225 pccbb_pcmcia_socket_enable(pch) 2226 pcmcia_chipset_handle_t pch; 2227 { 2228 struct pcic_handle *ph = (struct pcic_handle *)pch; 2229 struct pccbb_softc *sc = (struct pccbb_softc *)ph->ph_parent; 2230 int cardtype, win; 2231 u_int8_t power, intr; 2232 pcireg_t spsr; 2233 int voltage; 2234 2235 /* this bit is mostly stolen from pcic_attach_card */ 2236 2237 DPRINTF(("pccbb_pcmcia_socket_enable: ")); 2238 2239 /* get card Vcc info */ 2240 2241 spsr = 2242 bus_space_read_4(sc->sc_base_memt, sc->sc_base_memh, 2243 CB_SOCKET_STAT); 2244 if (spsr & CB_SOCKET_STAT_5VCARD) { 2245 DPRINTF(("5V card\n")); 2246 voltage = CARDBUS_VCC_5V | CARDBUS_VPP_VCC; 2247 } else if (spsr & CB_SOCKET_STAT_3VCARD) { 2248 DPRINTF(("3V card\n")); 2249 voltage = CARDBUS_VCC_3V | CARDBUS_VPP_VCC; 2250 } else { 2251 printf("?V card, 0x%x\n", spsr); /* XXX */ 2252 return; 2253 } 2254 2255 /* disable socket i/o: negate output enable bit */ 2256 2257 power = 0; 2258 Pcic_write(ph, PCIC_PWRCTL, power); 2259 2260 /* power down the socket to reset it, clear the card reset pin */ 2261 2262 pccbb_power(sc, CARDBUS_VCC_0V | CARDBUS_VPP_0V); 2263 2264 /* 2265 * wait 200ms until power fails (Tpf). Then, wait 100ms since 2266 * we are changing Vcc (Toff). 2267 */ 2268 /* delay(300*1000); too much */ 2269 2270 /* assert reset bit */ 2271 intr = Pcic_read(ph, PCIC_INTR); 2272 intr &= ~(PCIC_INTR_RESET | PCIC_INTR_CARDTYPE_MASK); 2273 Pcic_write(ph, PCIC_INTR, intr); 2274 2275 /* power up the socket and output enable */ 2276 power = Pcic_read(ph, PCIC_PWRCTL); 2277 power |= PCIC_PWRCTL_OE; 2278 Pcic_write(ph, PCIC_PWRCTL, power); 2279 pccbb_power(sc, voltage); 2280 2281 /* 2282 * hold RESET at least 10us. 2283 */ 2284 delay(10); 2285 delay(2 * 1000); /* XXX: TI1130 requires it. */ 2286 delay(20 * 1000); /* XXX: TI1130 requires it. */ 2287 2288 /* clear the reset flag */ 2289 2290 intr |= PCIC_INTR_RESET; 2291 Pcic_write(ph, PCIC_INTR, intr); 2292 2293 /* wait 20ms as per pc card standard (r2.01) section 4.3.6 */ 2294 2295 delay(20000); 2296 2297 /* wait for the chip to finish initializing */ 2298 2299 pccbb_pcmcia_wait_ready(ph); 2300 2301 /* zero out the address windows */ 2302 2303 Pcic_write(ph, PCIC_ADDRWIN_ENABLE, 0); 2304 2305 /* set the card type */ 2306 2307 cardtype = pcmcia_card_gettype(ph->pcmcia); 2308 2309 intr |= ((cardtype == PCMCIA_IFTYPE_IO) ? 2310 PCIC_INTR_CARDTYPE_IO : PCIC_INTR_CARDTYPE_MEM); 2311 Pcic_write(ph, PCIC_INTR, intr); 2312 2313 DPRINTF(("%s: pccbb_pcmcia_socket_enable %02x cardtype %s %02x\n", 2314 ph->ph_parent->dv_xname, ph->sock, 2315 ((cardtype == PCMCIA_IFTYPE_IO) ? "io" : "mem"), intr)); 2316 2317 /* reinstall all the memory and io mappings */ 2318 2319 for (win = 0; win < PCIC_MEM_WINS; ++win) { 2320 if (ph->memalloc & (1 << win)) { 2321 pccbb_pcmcia_do_mem_map(ph, win); 2322 } 2323 } 2324 2325 for (win = 0; win < PCIC_IO_WINS; ++win) { 2326 if (ph->ioalloc & (1 << win)) { 2327 pccbb_pcmcia_do_io_map(ph, win); 2328 } 2329 } 2330 } 2331 2332 /* 2333 * void pccbb_pcmcia_socket_disable(pcmcia_chipset_handle_t *ph) 2334 * 2335 * This function disables the card. All information is stored in 2336 * the first argument, pcmcia_chipset_handle_t. 2337 */ 2338 void 2339 pccbb_pcmcia_socket_disable(pch) 2340 pcmcia_chipset_handle_t pch; 2341 { 2342 struct pcic_handle *ph = (struct pcic_handle *)pch; 2343 struct pccbb_softc *sc = (struct pccbb_softc *)ph->ph_parent; 2344 u_int8_t power, intr; 2345 2346 DPRINTF(("pccbb_pcmcia_socket_disable\n")); 2347 2348 /* reset signal asserting... */ 2349 2350 intr = Pcic_read(ph, PCIC_INTR); 2351 intr &= ~(PCIC_INTR_CARDTYPE_MASK); 2352 Pcic_write(ph, PCIC_INTR, intr); 2353 delay(2 * 1000); 2354 2355 /* power down the socket */ 2356 power = Pcic_read(ph, PCIC_PWRCTL); 2357 power &= ~PCIC_PWRCTL_OE; 2358 Pcic_write(ph, PCIC_PWRCTL, power); 2359 pccbb_power(sc, CARDBUS_VCC_0V | CARDBUS_VPP_0V); 2360 /* 2361 * wait 300ms until power fails (Tpf). 2362 */ 2363 delay(300 * 1000); 2364 } 2365 2366 /* 2367 * int pccbb_pcmcia_card_detect(pcmcia_chipset_handle_t *ph) 2368 * 2369 * This function detects whether a card is in the slot or not. 2370 * If a card is inserted, return 1. Otherwise, return 0. 2371 */ 2372 int 2373 pccbb_pcmcia_card_detect(pch) 2374 pcmcia_chipset_handle_t pch; 2375 { 2376 struct pcic_handle *ph = (struct pcic_handle *)pch; 2377 struct pccbb_softc *sc = (struct pccbb_softc *)ph->ph_parent; 2378 2379 DPRINTF(("pccbb_pcmcia_card_detect\n")); 2380 return pccbb_detect_card(sc) == 1 ? 1 : 0; 2381 } 2382 2383 #if 0 2384 int 2385 pccbb_new_pcmcia_mem_alloc(pcmcia_chipset_handle_t pch, 2386 bus_addr_t start, bus_size_t size, bus_size_t align, int speed, int flags, 2387 bus_space_tag_t * memtp bus_space_handle_t * memhp) 2388 #endif 2389 /* 2390 * int pccbb_pcmcia_mem_alloc(pcmcia_chipset_handle_t pch, 2391 * bus_size_t size, 2392 * struct pcmcia_mem_handle *pcmhp) 2393 * 2394 * This function only allocates memory region for pccard. This 2395 * function never maps the allocated region to pccard memory area. 2396 * 2397 * XXX: Why the argument of start address is not in? 2398 */ 2399 int 2400 pccbb_pcmcia_mem_alloc(pch, size, pcmhp) 2401 pcmcia_chipset_handle_t pch; 2402 bus_size_t size; 2403 struct pcmcia_mem_handle *pcmhp; 2404 { 2405 struct pcic_handle *ph = (struct pcic_handle *)pch; 2406 bus_space_handle_t memh; 2407 bus_addr_t addr; 2408 bus_size_t sizepg; 2409 struct pccbb_softc *sc = (struct pccbb_softc *)ph->ph_parent; 2410 #if rbus 2411 rbus_tag_t rb; 2412 #endif 2413 2414 /* out of sc->memh, allocate as many pages as necessary */ 2415 2416 /* convert size to PCIC pages */ 2417 /* 2418 * This is not enough; when the requested region is on the page 2419 * boundaries, this may calculate wrong result. 2420 */ 2421 sizepg = (size + (PCIC_MEM_PAGESIZE - 1)) / PCIC_MEM_PAGESIZE; 2422 #if 0 2423 if (sizepg > PCIC_MAX_MEM_PAGES) { 2424 return 1; 2425 } 2426 #endif 2427 2428 if (!(sc->sc_pcmcia_flags & PCCBB_PCMCIA_MEM_32)) { 2429 return 1; 2430 } 2431 2432 addr = 0; /* XXX gcc -Wuninitialized */ 2433 2434 #if rbus 2435 rb = sc->sc_rbus_memt; 2436 if (rbus_space_alloc(rb, 0, sizepg * PCIC_MEM_PAGESIZE, 2437 sizepg * PCIC_MEM_PAGESIZE - 1, PCIC_MEM_PAGESIZE, 0, 2438 &addr, &memh)) { 2439 return 1; 2440 } 2441 #else 2442 if (bus_space_alloc(sc->sc_memt, sc->sc_mem_start, sc->sc_mem_end, 2443 sizepg * PCIC_MEM_PAGESIZE, PCIC_MEM_PAGESIZE, 2444 0, /* boundary */ 2445 0, /* flags */ 2446 &addr, &memh)) { 2447 return 1; 2448 } 2449 #endif 2450 2451 DPRINTF( 2452 ("pccbb_pcmcia_alloc_mem: addr 0x%lx size 0x%lx, realsize 0x%lx\n", 2453 addr, size, sizepg * PCIC_MEM_PAGESIZE)); 2454 2455 pcmhp->memt = sc->sc_memt; 2456 pcmhp->memh = memh; 2457 pcmhp->addr = addr; 2458 pcmhp->size = size; 2459 pcmhp->realsize = sizepg * PCIC_MEM_PAGESIZE; 2460 /* What is mhandle? I feel it is very dirty and it must go trush. */ 2461 pcmhp->mhandle = 0; 2462 /* No offset??? Funny. */ 2463 2464 return 0; 2465 } 2466 2467 /* 2468 * void pccbb_pcmcia_mem_free(pcmcia_chipset_handle_t pch, 2469 * struct pcmcia_mem_handle *pcmhp) 2470 * 2471 * This function release the memory space allocated by the function 2472 * pccbb_pcmcia_mem_alloc(). 2473 */ 2474 void 2475 pccbb_pcmcia_mem_free(pch, pcmhp) 2476 pcmcia_chipset_handle_t pch; 2477 struct pcmcia_mem_handle *pcmhp; 2478 { 2479 #if rbus 2480 struct pcic_handle *ph = (struct pcic_handle *)pch; 2481 struct pccbb_softc *sc = (struct pccbb_softc *)ph->ph_parent; 2482 2483 rbus_space_free(sc->sc_rbus_memt, pcmhp->memh, pcmhp->realsize, NULL); 2484 #else 2485 bus_space_free(pcmhp->memt, pcmhp->memh, pcmhp->realsize); 2486 #endif 2487 } 2488 2489 /* 2490 * void pccbb_pcmcia_do_mem_map(struct pcic_handle *ph, int win) 2491 * 2492 * This function release the memory space allocated by the function 2493 * pccbb_pcmcia_mem_alloc(). 2494 */ 2495 void 2496 pccbb_pcmcia_do_mem_map(ph, win) 2497 struct pcic_handle *ph; 2498 int win; 2499 { 2500 int regbase_win; 2501 bus_addr_t phys_addr; 2502 bus_addr_t phys_end; 2503 2504 #define PCIC_SMM_START_LOW 0 2505 #define PCIC_SMM_START_HIGH 1 2506 #define PCIC_SMM_STOP_LOW 2 2507 #define PCIC_SMM_STOP_HIGH 3 2508 #define PCIC_CMA_LOW 4 2509 #define PCIC_CMA_HIGH 5 2510 2511 u_int8_t start_low, start_high = 0; 2512 u_int8_t stop_low, stop_high; 2513 u_int8_t off_low, off_high; 2514 u_int8_t mem_window; 2515 int reg; 2516 2517 regbase_win = 0x10 + win * 0x08; 2518 2519 phys_addr = ph->mem[win].addr; 2520 phys_end = phys_addr + ph->mem[win].size; 2521 2522 DPRINTF(("pccbb_pcmcia_do_mem_map: start 0x%lx end 0x%lx off 0x%lx\n", 2523 phys_addr, phys_end, ph->mem[win].offset)); 2524 2525 #define PCIC_MEMREG_LSB_SHIFT PCIC_SYSMEM_ADDRX_SHIFT 2526 #define PCIC_MEMREG_MSB_SHIFT (PCIC_SYSMEM_ADDRX_SHIFT + 8) 2527 #define PCIC_MEMREG_WIN_SHIFT (PCIC_SYSMEM_ADDRX_SHIFT + 12) 2528 2529 /* bit 19:12 */ 2530 start_low = (phys_addr >> PCIC_MEMREG_LSB_SHIFT) & 0xff; 2531 /* bit 23:20 and bit 7 on */ 2532 start_high = ((phys_addr >> PCIC_MEMREG_MSB_SHIFT) & 0x0f) 2533 | PCIC_SYSMEM_ADDRX_START_MSB_DATASIZE_16BIT; /* bit 7 on */ 2534 /* bit 31:24, for 32-bit address */ 2535 mem_window = (phys_addr >> PCIC_MEMREG_WIN_SHIFT) & 0xff; 2536 2537 Pcic_write(ph, regbase_win + PCIC_SMM_START_LOW, start_low); 2538 Pcic_write(ph, regbase_win + PCIC_SMM_START_HIGH, start_high); 2539 2540 if (((struct pccbb_softc *)ph-> 2541 ph_parent)->sc_pcmcia_flags & PCCBB_PCMCIA_MEM_32) { 2542 Pcic_write(ph, 0x40 + win, mem_window); 2543 } 2544 2545 stop_low = (phys_end >> PCIC_MEMREG_LSB_SHIFT) & 0xff; 2546 stop_high = ((phys_end >> PCIC_MEMREG_MSB_SHIFT) & 0x0f) 2547 | PCIC_SYSMEM_ADDRX_STOP_MSB_WAIT2; /* wait 2 cycles */ 2548 /* XXX Geee, WAIT2!! Crazy!! I must rewrite this routine. */ 2549 2550 Pcic_write(ph, regbase_win + PCIC_SMM_STOP_LOW, stop_low); 2551 Pcic_write(ph, regbase_win + PCIC_SMM_STOP_HIGH, stop_high); 2552 2553 off_low = (ph->mem[win].offset >> PCIC_CARDMEM_ADDRX_SHIFT) & 0xff; 2554 off_high = ((ph->mem[win].offset >> (PCIC_CARDMEM_ADDRX_SHIFT + 8)) 2555 & PCIC_CARDMEM_ADDRX_MSB_ADDR_MASK) 2556 | ((ph->mem[win].kind == PCMCIA_MEM_ATTR) ? 2557 PCIC_CARDMEM_ADDRX_MSB_REGACTIVE_ATTR : 0); 2558 2559 Pcic_write(ph, regbase_win + PCIC_CMA_LOW, off_low); 2560 Pcic_write(ph, regbase_win + PCIC_CMA_HIGH, off_high); 2561 2562 reg = Pcic_read(ph, PCIC_ADDRWIN_ENABLE); 2563 reg |= ((1 << win) | PCIC_ADDRWIN_ENABLE_MEMCS16); 2564 Pcic_write(ph, PCIC_ADDRWIN_ENABLE, reg); 2565 2566 #if defined CBB_DEBUG 2567 { 2568 int r1, r2, r3, r4, r5, r6, r7 = 0; 2569 2570 r1 = Pcic_read(ph, regbase_win + PCIC_SMM_START_LOW); 2571 r2 = Pcic_read(ph, regbase_win + PCIC_SMM_START_HIGH); 2572 r3 = Pcic_read(ph, regbase_win + PCIC_SMM_STOP_LOW); 2573 r4 = Pcic_read(ph, regbase_win + PCIC_SMM_STOP_HIGH); 2574 r5 = Pcic_read(ph, regbase_win + PCIC_CMA_LOW); 2575 r6 = Pcic_read(ph, regbase_win + PCIC_CMA_HIGH); 2576 if (((struct pccbb_softc *)(ph-> 2577 ph_parent))->sc_pcmcia_flags & PCCBB_PCMCIA_MEM_32) { 2578 r7 = Pcic_read(ph, 0x40 + win); 2579 } 2580 2581 DPRINTF(("pccbb_pcmcia_do_mem_map window %d: %02x%02x %02x%02x " 2582 "%02x%02x", win, r1, r2, r3, r4, r5, r6)); 2583 if (((struct pccbb_softc *)(ph-> 2584 ph_parent))->sc_pcmcia_flags & PCCBB_PCMCIA_MEM_32) { 2585 DPRINTF((" %02x", r7)); 2586 } 2587 DPRINTF(("\n")); 2588 } 2589 #endif 2590 } 2591 2592 /* 2593 * int pccbb_pcmcia_mem_map(pcmcia_chipset_handle_t pch, int kind, 2594 * bus_addr_t card_addr, bus_size_t size, 2595 * struct pcmcia_mem_handle *pcmhp, 2596 * bus_addr_t *offsetp, int *windowp) 2597 * 2598 * This function maps memory space allocated by the function 2599 * pccbb_pcmcia_mem_alloc(). 2600 */ 2601 int 2602 pccbb_pcmcia_mem_map(pch, kind, card_addr, size, pcmhp, offsetp, windowp) 2603 pcmcia_chipset_handle_t pch; 2604 int kind; 2605 bus_addr_t card_addr; 2606 bus_size_t size; 2607 struct pcmcia_mem_handle *pcmhp; 2608 bus_addr_t *offsetp; 2609 int *windowp; 2610 { 2611 struct pcic_handle *ph = (struct pcic_handle *)pch; 2612 bus_addr_t busaddr; 2613 long card_offset; 2614 int win; 2615 2616 for (win = 0; win < PCIC_MEM_WINS; ++win) { 2617 if ((ph->memalloc & (1 << win)) == 0) { 2618 ph->memalloc |= (1 << win); 2619 break; 2620 } 2621 } 2622 2623 if (win == PCIC_MEM_WINS) { 2624 return 1; 2625 } 2626 2627 *windowp = win; 2628 2629 /* XXX this is pretty gross */ 2630 2631 if (((struct pccbb_softc *)ph->ph_parent)->sc_memt != pcmhp->memt) { 2632 panic("pccbb_pcmcia_mem_map memt is bogus"); 2633 } 2634 2635 busaddr = pcmhp->addr; 2636 2637 /* 2638 * compute the address offset to the pcmcia address space for the 2639 * pcic. this is intentionally signed. The masks and shifts below 2640 * will cause TRT to happen in the pcic registers. Deal with making 2641 * sure the address is aligned, and return the alignment offset. 2642 */ 2643 2644 *offsetp = card_addr % PCIC_MEM_PAGESIZE; 2645 card_addr -= *offsetp; 2646 2647 DPRINTF(("pccbb_pcmcia_mem_map window %d bus %lx+%lx+%lx at card addr " 2648 "%lx\n", win, (u_long) busaddr, (u_long) * offsetp, (u_long) size, 2649 (u_long) card_addr)); 2650 2651 /* 2652 * include the offset in the size, and decrement size by one, since 2653 * the hw wants start/stop 2654 */ 2655 size += *offsetp - 1; 2656 2657 card_offset = (((long)card_addr) - ((long)busaddr)); 2658 2659 ph->mem[win].addr = busaddr; 2660 ph->mem[win].size = size; 2661 ph->mem[win].offset = card_offset; 2662 ph->mem[win].kind = kind; 2663 2664 pccbb_pcmcia_do_mem_map(ph, win); 2665 2666 return 0; 2667 } 2668 2669 /* 2670 * int pccbb_pcmcia_mem_unmap(pcmcia_chipset_handle_t pch, 2671 * int window) 2672 * 2673 * This function unmaps memory space which mapped by the function 2674 * pccbb_pcmcia_mem_map(). 2675 */ 2676 void 2677 pccbb_pcmcia_mem_unmap(pch, window) 2678 pcmcia_chipset_handle_t pch; 2679 int window; 2680 { 2681 struct pcic_handle *ph = (struct pcic_handle *)pch; 2682 int reg; 2683 2684 if (window >= PCIC_MEM_WINS) { 2685 panic("pccbb_pcmcia_mem_unmap: window out of range"); 2686 } 2687 2688 reg = Pcic_read(ph, PCIC_ADDRWIN_ENABLE); 2689 reg &= ~(1 << window); 2690 Pcic_write(ph, PCIC_ADDRWIN_ENABLE, reg); 2691 2692 ph->memalloc &= ~(1 << window); 2693 } 2694 2695 #if defined PCCBB_PCMCIA_POLL 2696 struct pccbb_poll_str { 2697 void *arg; 2698 int (*func)(void *); 2699 int level; 2700 struct pcic_handle *ph; 2701 int count; 2702 int num; 2703 }; 2704 2705 static struct pccbb_poll_str pccbb_poll[10]; 2706 static int pccbb_poll_n = 0; 2707 static struct timeout pccbb_poll_timeout; 2708 2709 void pccbb_pcmcia_poll(void *arg); 2710 2711 void 2712 pccbb_pcmcia_poll(arg) 2713 void *arg; 2714 { 2715 struct pccbb_poll_str *poll = arg; 2716 struct pcic_handle *ph = poll->ph; 2717 struct pccbb_softc *sc = ph->sc; 2718 int s; 2719 u_int32_t spsr; /* socket present-state reg */ 2720 2721 timeout_set(&pccbb_poll_timeout, pccbb_pcmcia_poll, arg); 2722 timeout_add(&pccbb_poll_timeout, hz * 2); 2723 switch (poll->level) { 2724 case IPL_NET: 2725 s = splnet(); 2726 break; 2727 case IPL_BIO: 2728 s = splbio(); 2729 break; 2730 case IPL_TTY: /* fallthrough */ 2731 default: 2732 s = spltty(); 2733 break; 2734 } 2735 2736 spsr = 2737 bus_space_read_4(sc->sc_base_memt, sc->sc_base_memh, 2738 CB_SOCKET_STAT); 2739 2740 #if defined PCCBB_PCMCIA_POLL_ONLY && defined LEVEL2 2741 if (!(spsr & 0x40)) /* CINT low */ 2742 #else 2743 if (1) 2744 #endif 2745 { 2746 if ((*poll->func) (poll->arg) > 0) { 2747 ++poll->count; 2748 /* printf("intr: reported from poller, 0x%x\n", spsr); */ 2749 #if defined LEVEL2 2750 } else { 2751 printf("intr: miss! 0x%x\n", spsr); 2752 #endif 2753 } 2754 } 2755 splx(s); 2756 } 2757 #endif /* defined CB_PCMCIA_POLL */ 2758 2759 /* 2760 * void *pccbb_pcmcia_intr_establish(pcmcia_chipset_handle_t pch, 2761 * struct pcmcia_function *pf, 2762 * int ipl, 2763 * int (*func)(void *), 2764 * void *arg); 2765 * 2766 * This function enables PC-Card interrupt. PCCBB uses PCI interrupt line. 2767 */ 2768 void * 2769 pccbb_pcmcia_intr_establish(pch, pf, ipl, func, arg, xname) 2770 pcmcia_chipset_handle_t pch; 2771 struct pcmcia_function *pf; 2772 int ipl; 2773 int (*func)(void *); 2774 void *arg; 2775 char *xname; 2776 { 2777 struct pcic_handle *ph = (struct pcic_handle *)pch; 2778 struct pccbb_softc *sc = (struct pccbb_softc *)ph->ph_parent; 2779 2780 if (!(pf->cfe->flags & PCMCIA_CFE_IRQLEVEL)) { 2781 /* what should I do? */ 2782 if ((pf->cfe->flags & PCMCIA_CFE_IRQLEVEL)) { 2783 DPRINTF( 2784 ("%s does not provide edge nor pulse interrupt\n", 2785 sc->sc_dev.dv_xname)); 2786 return NULL; 2787 } 2788 /* 2789 * XXX Noooooo! The interrupt flag must set properly!! 2790 * dumb pcmcia driver!! 2791 */ 2792 } 2793 2794 return pccbb_intr_establish(sc, IST_LEVEL, ipl, func, arg); 2795 } 2796 2797 /* 2798 * void pccbb_pcmcia_intr_disestablish(pcmcia_chipset_handle_t pch, 2799 * void *ih) 2800 * 2801 * This function disables PC-Card interrupt. 2802 */ 2803 void 2804 pccbb_pcmcia_intr_disestablish(pch, ih) 2805 pcmcia_chipset_handle_t pch; 2806 void *ih; 2807 { 2808 struct pcic_handle *ph = (struct pcic_handle *)pch; 2809 struct pccbb_softc *sc = (struct pccbb_softc *)ph->ph_parent; 2810 2811 pccbb_intr_disestablish(sc, ih); 2812 } 2813 2814 #if rbus 2815 /* 2816 * int 2817 * pccbb_rbus_cb_space_alloc(cardbus_chipset_tag_t ct, rbus_tag_t rb, 2818 * bus_addr_t addr, bus_size_t size, 2819 * bus_addr_t mask, bus_size_t align, 2820 * int flags, bus_addr_t *addrp; 2821 * bus_space_handle_t *bshp) 2822 * 2823 * This function allocates a portion of memory or io space for 2824 * clients. This function is called from CardBus card drivers. 2825 */ 2826 int 2827 pccbb_rbus_cb_space_alloc(ct, rb, addr, size, mask, align, flags, addrp, bshp) 2828 cardbus_chipset_tag_t ct; 2829 rbus_tag_t rb; 2830 bus_addr_t addr; 2831 bus_size_t size; 2832 bus_addr_t mask; 2833 bus_size_t align; 2834 int flags; 2835 bus_addr_t *addrp; 2836 bus_space_handle_t *bshp; 2837 { 2838 struct pccbb_softc *sc = (struct pccbb_softc *)ct; 2839 2840 DPRINTF( 2841 ("pccbb_rbus_cb_space_alloc: adr %lx, size %lx, mask %lx, align %lx\n", 2842 addr, size, mask, align)); 2843 2844 if (align == 0) { 2845 align = size; 2846 } 2847 2848 if (rb->rb_bt == sc->sc_memt) { 2849 if (align < 16) { 2850 return 1; 2851 } 2852 } else if (rb->rb_bt == sc->sc_iot) { 2853 if (align < 4) { 2854 return 1; 2855 } 2856 /* XXX: hack for avoiding ISA image */ 2857 if (mask < 0x0100) { 2858 mask = 0x3ff; 2859 addr = 0x300; 2860 } 2861 2862 } else { 2863 DPRINTF( 2864 ("pccbb_rbus_cb_space_alloc: Bus space tag %x is NOT used.\n", 2865 rb->rb_bt)); 2866 return 1; 2867 /* XXX: panic here? */ 2868 } 2869 2870 if (rbus_space_alloc(rb, addr, size, mask, align, flags, addrp, bshp)) { 2871 printf("%s: <rbus> no bus space\n", sc->sc_dev.dv_xname); 2872 return 1; 2873 } 2874 2875 pccbb_open_win(sc, rb->rb_bt, *addrp, size, *bshp, 0); 2876 2877 return 0; 2878 } 2879 2880 /* 2881 * int 2882 * pccbb_rbus_cb_space_free(cardbus_chipset_tag_t *ct, rbus_tag_t rb, 2883 * bus_space_handle_t *bshp, bus_size_t size); 2884 * 2885 * This function is called from CardBus card drivers. 2886 */ 2887 int 2888 pccbb_rbus_cb_space_free(ct, rb, bsh, size) 2889 cardbus_chipset_tag_t ct; 2890 rbus_tag_t rb; 2891 bus_space_handle_t bsh; 2892 bus_size_t size; 2893 { 2894 struct pccbb_softc *sc = (struct pccbb_softc *)ct; 2895 bus_space_tag_t bt = rb->rb_bt; 2896 2897 pccbb_close_win(sc, bt, bsh, size); 2898 2899 if (bt == sc->sc_memt) { 2900 } else if (bt == sc->sc_iot) { 2901 } else { 2902 return 1; 2903 /* XXX: panic here? */ 2904 } 2905 2906 return rbus_space_free(rb, bsh, size, NULL); 2907 } 2908 #endif /* rbus */ 2909 2910 #if rbus 2911 2912 int 2913 pccbb_open_win(sc, bst, addr, size, bsh, flags) 2914 struct pccbb_softc *sc; 2915 bus_space_tag_t bst; 2916 bus_addr_t addr; 2917 bus_size_t size; 2918 bus_space_handle_t bsh; 2919 int flags; 2920 { 2921 struct pccbb_win_chain_head *head; 2922 bus_addr_t align; 2923 2924 head = &sc->sc_iowindow; 2925 align = 0x04; 2926 if (sc->sc_memt == bst) { 2927 head = &sc->sc_memwindow; 2928 align = 0x1000; 2929 DPRINTF(("using memory window, %x %x %x\n\n", 2930 sc->sc_iot, sc->sc_memt, bst)); 2931 } 2932 2933 if (pccbb_winlist_insert(head, addr, size, bsh, flags)) { 2934 printf("%s: pccbb_open_win: %s winlist insert failed\n", 2935 sc->sc_dev.dv_xname, 2936 (head == &sc->sc_memwindow) ? "mem" : "io"); 2937 } 2938 pccbb_winset(align, sc, bst); 2939 2940 return 0; 2941 } 2942 2943 int 2944 pccbb_close_win(sc, bst, bsh, size) 2945 struct pccbb_softc *sc; 2946 bus_space_tag_t bst; 2947 bus_space_handle_t bsh; 2948 bus_size_t size; 2949 { 2950 struct pccbb_win_chain_head *head; 2951 bus_addr_t align; 2952 2953 head = &sc->sc_iowindow; 2954 align = 0x04; 2955 if (sc->sc_memt == bst) { 2956 head = &sc->sc_memwindow; 2957 align = 0x1000; 2958 } 2959 2960 if (pccbb_winlist_delete(head, bsh, size)) { 2961 printf("%s: pccbb_close_win: %s winlist delete failed\n", 2962 sc->sc_dev.dv_xname, 2963 (head == &sc->sc_memwindow) ? "mem" : "io"); 2964 } 2965 pccbb_winset(align, sc, bst); 2966 2967 return 0; 2968 } 2969 2970 int 2971 pccbb_winlist_insert(head, start, size, bsh, flags) 2972 struct pccbb_win_chain_head *head; 2973 bus_addr_t start; 2974 bus_size_t size; 2975 bus_space_handle_t bsh; 2976 int flags; 2977 { 2978 struct pccbb_win_chain *chainp, *elem; 2979 2980 if ((elem = malloc(sizeof(struct pccbb_win_chain), M_DEVBUF, 2981 M_NOWAIT)) == NULL) 2982 return (1); /* fail */ 2983 2984 elem->wc_start = start; 2985 elem->wc_end = start + (size - 1); 2986 elem->wc_handle = bsh; 2987 elem->wc_flags = flags; 2988 2989 for (chainp = TAILQ_FIRST(head); chainp != NULL; 2990 chainp = TAILQ_NEXT(chainp, wc_list)) { 2991 if (chainp->wc_end < start) 2992 continue; 2993 TAILQ_INSERT_AFTER(head, chainp, elem, wc_list); 2994 return (0); 2995 } 2996 2997 TAILQ_INSERT_TAIL(head, elem, wc_list); 2998 return (0); 2999 } 3000 3001 int 3002 pccbb_winlist_delete(head, bsh, size) 3003 struct pccbb_win_chain_head *head; 3004 bus_space_handle_t bsh; 3005 bus_size_t size; 3006 { 3007 struct pccbb_win_chain *chainp; 3008 3009 for (chainp = TAILQ_FIRST(head); chainp != NULL; 3010 chainp = TAILQ_NEXT(chainp, wc_list)) { 3011 if (chainp->wc_handle != bsh) 3012 continue; 3013 if ((chainp->wc_end - chainp->wc_start) != (size - 1)) { 3014 printf("pccbb_winlist_delete: window 0x%lx size " 3015 "inconsistent: 0x%lx, 0x%lx\n", 3016 chainp->wc_start, 3017 chainp->wc_end - chainp->wc_start, 3018 size - 1); 3019 return 1; 3020 } 3021 3022 TAILQ_REMOVE(head, chainp, wc_list); 3023 free(chainp, M_DEVBUF); 3024 3025 return 0; 3026 } 3027 3028 return 1; /* fail: no candidate to remove */ 3029 } 3030 3031 void 3032 pccbb_winset(align, sc, bst) 3033 bus_addr_t align; 3034 struct pccbb_softc *sc; 3035 bus_space_tag_t bst; 3036 { 3037 pci_chipset_tag_t pc; 3038 pcitag_t tag; 3039 bus_addr_t mask = ~(align - 1); 3040 struct { 3041 cardbusreg_t win_start; 3042 cardbusreg_t win_limit; 3043 int win_flags; 3044 } win[2]; 3045 struct pccbb_win_chain *chainp; 3046 int offs; 3047 3048 win[0].win_start = win[1].win_start = 0xffffffff; 3049 win[0].win_limit = win[1].win_limit = 0; 3050 win[0].win_flags = win[1].win_flags = 0; 3051 3052 chainp = TAILQ_FIRST(&sc->sc_iowindow); 3053 offs = 0x2c; 3054 if (sc->sc_memt == bst) { 3055 chainp = TAILQ_FIRST(&sc->sc_memwindow); 3056 offs = 0x1c; 3057 } 3058 3059 if (chainp != NULL) { 3060 win[0].win_start = chainp->wc_start & mask; 3061 win[0].win_limit = chainp->wc_end & mask; 3062 win[0].win_flags = chainp->wc_flags; 3063 chainp = TAILQ_NEXT(chainp, wc_list); 3064 } 3065 3066 for (; chainp != NULL; chainp = TAILQ_NEXT(chainp, wc_list)) { 3067 if (win[1].win_start == 0xffffffff) { 3068 /* window 1 is not used */ 3069 if ((win[0].win_flags == chainp->wc_flags) && 3070 (win[0].win_limit + align >= 3071 (chainp->wc_start & mask))) { 3072 /* concatenate */ 3073 win[0].win_limit = chainp->wc_end & mask; 3074 } else { 3075 /* make new window */ 3076 win[1].win_start = chainp->wc_start & mask; 3077 win[1].win_limit = chainp->wc_end & mask; 3078 win[1].win_flags = chainp->wc_flags; 3079 } 3080 continue; 3081 } 3082 3083 /* Both windows are engaged. */ 3084 if (win[0].win_flags == win[1].win_flags) { 3085 /* same flags */ 3086 if (win[0].win_flags == chainp->wc_flags) { 3087 if (win[1].win_start - (win[0].win_limit + 3088 align) < 3089 (chainp->wc_start & mask) - 3090 ((chainp->wc_end & mask) + align)) { 3091 /* 3092 * merge window 0 and 1, and set win1 3093 * to chainp 3094 */ 3095 win[0].win_limit = win[1].win_limit; 3096 win[1].win_start = 3097 chainp->wc_start & mask; 3098 win[1].win_limit = 3099 chainp->wc_end & mask; 3100 } else { 3101 win[1].win_limit = 3102 chainp->wc_end & mask; 3103 } 3104 } else { 3105 /* different flags */ 3106 3107 /* concatenate win0 and win1 */ 3108 win[0].win_limit = win[1].win_limit; 3109 /* allocate win[1] to new space */ 3110 win[1].win_start = chainp->wc_start & mask; 3111 win[1].win_limit = chainp->wc_end & mask; 3112 win[1].win_flags = chainp->wc_flags; 3113 } 3114 } else { 3115 /* the flags of win[0] and win[1] is different */ 3116 if (win[0].win_flags == chainp->wc_flags) { 3117 win[0].win_limit = chainp->wc_end & mask; 3118 /* 3119 * XXX this creates overlapping windows, so 3120 * what should the poor bridge do if one is 3121 * cachable, and the other is not? 3122 */ 3123 printf("%s: overlapping windows\n", 3124 sc->sc_dev.dv_xname); 3125 } else { 3126 win[1].win_limit = chainp->wc_end & mask; 3127 } 3128 } 3129 } 3130 3131 pc = sc->sc_pc; 3132 tag = sc->sc_tag; 3133 pci_conf_write(pc, tag, offs, win[0].win_start); 3134 pci_conf_write(pc, tag, offs + 4, win[0].win_limit); 3135 pci_conf_write(pc, tag, offs + 8, win[1].win_start); 3136 pci_conf_write(pc, tag, offs + 12, win[1].win_limit); 3137 DPRINTF(("--pccbb_winset: win0 [%x, %lx), win1 [%x, %lx)\n", 3138 pci_conf_read(pc, tag, offs), 3139 pci_conf_read(pc, tag, offs + 4) + align, 3140 pci_conf_read(pc, tag, offs + 8), 3141 pci_conf_read(pc, tag, offs + 12) + align)); 3142 3143 if (bst == sc->sc_memt) { 3144 pcireg_t bcr = pci_conf_read(pc, tag, PCI_BCR_INTR); 3145 3146 bcr &= ~(CB_BCR_PREFETCH_MEMWIN0 | CB_BCR_PREFETCH_MEMWIN1); 3147 if (win[0].win_flags & PCCBB_MEM_CACHABLE) 3148 bcr |= CB_BCR_PREFETCH_MEMWIN0; 3149 if (win[1].win_flags & PCCBB_MEM_CACHABLE) 3150 bcr |= CB_BCR_PREFETCH_MEMWIN1; 3151 pci_conf_write(pc, tag, PCI_BCR_INTR, bcr); 3152 } 3153 } 3154 3155 #endif /* rbus */ 3156 3157 void 3158 pccbb_powerhook(why, arg) 3159 int why; 3160 void *arg; 3161 { 3162 struct pccbb_softc *sc = arg; 3163 u_int32_t reg; 3164 bus_space_tag_t base_memt = sc->sc_base_memt; /* socket regs memory */ 3165 bus_space_handle_t base_memh = sc->sc_base_memh; 3166 3167 DPRINTF(("%s: power: why %d\n", sc->sc_dev.dv_xname, why)); 3168 3169 if (why == PWR_SUSPEND || why == PWR_STANDBY) { 3170 DPRINTF(("%s: power: why %d stopping intr\n", 3171 sc->sc_dev.dv_xname, why)); 3172 if (sc->sc_pil_intr_enable) { 3173 (void)pccbbintr_function(sc); 3174 } 3175 sc->sc_pil_intr_enable = 0; 3176 3177 /* ToDo: deactivate or suspend child devices */ 3178 3179 } 3180 3181 if (why == PWR_RESUME) { 3182 if (pci_conf_read (sc->sc_pc, sc->sc_tag, PCI_SOCKBASE) == 0) 3183 /* BIOS did not recover this register */ 3184 pci_conf_write (sc->sc_pc, sc->sc_tag, 3185 PCI_SOCKBASE, sc->sc_sockbase); 3186 if (pci_conf_read (sc->sc_pc, sc->sc_tag, PCI_BUSNUM) == 0) 3187 /* BIOS did not recover this register */ 3188 pci_conf_write (sc->sc_pc, sc->sc_tag, 3189 PCI_BUSNUM, sc->sc_busnum); 3190 /* CSC Interrupt: Card detect interrupt on */ 3191 reg = bus_space_read_4(base_memt, base_memh, CB_SOCKET_MASK); 3192 /* Card detect intr is turned on. */ 3193 reg |= CB_SOCKET_MASK_CD; 3194 bus_space_write_4(base_memt, base_memh, CB_SOCKET_MASK, reg); 3195 /* reset interrupt */ 3196 reg = bus_space_read_4(base_memt, base_memh, CB_SOCKET_EVENT); 3197 bus_space_write_4(base_memt, base_memh, CB_SOCKET_EVENT, reg); 3198 3199 /* 3200 * check for card insertion or removal during suspend period. 3201 * XXX: the code can't cope with card swap (remove then 3202 * insert). how can we detect such situation? 3203 */ 3204 (void)pccbbintr(sc); 3205 3206 sc->sc_pil_intr_enable = 1; 3207 DPRINTF(("%s: power: RESUME enabling intr\n", 3208 sc->sc_dev.dv_xname)); 3209 3210 /* ToDo: activate or wakeup child devices */ 3211 } 3212 } 3213