1 /* $OpenBSD: pccbb.c,v 1.21 2001/06/20 23:12:11 niklas Exp $ */ 2 /* $NetBSD: pccbb.c,v 1.42 2000/06/16 23:41:35 cgd Exp $ */ 3 4 /* 5 * Copyright (c) 1998, 1999 and 2000 6 * HAYAKAWA Koichi. All rights reserved. 7 * 8 * Redistribution and use in source and binary forms, with or without 9 * modification, are permitted provided that the following conditions 10 * are met: 11 * 1. Redistributions of source code must retain the above copyright 12 * notice, this list of conditions and the following disclaimer. 13 * 2. Redistributions in binary form must reproduce the above copyright 14 * notice, this list of conditions and the following disclaimer in the 15 * documentation and/or other materials provided with the distribution. 16 * 3. All advertising materials mentioning features or use of this software 17 * must display the following acknowledgement: 18 * This product includes software developed by HAYAKAWA Koichi. 19 * 4. The name of the author may not be used to endorse or promote products 20 * derived from this software without specific prior written permission. 21 * 22 * THIS SOFTWARE IS PROVIDED BY THE AUTHOR ``AS IS'' AND ANY EXPRESS OR 23 * IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED WARRANTIES 24 * OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE DISCLAIMED. 25 * IN NO EVENT SHALL THE AUTHOR BE LIABLE FOR ANY DIRECT, INDIRECT, 26 * INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT 27 * NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, 28 * DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY 29 * THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT 30 * (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE OF 31 * THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE. 32 */ 33 34 /* 35 #define CBB_DEBUG 36 #define SHOW_REGS 37 #define PCCBB_PCMCIA_POLL 38 */ 39 /* #define CBB_DEBUG */ 40 41 /* 42 #define CB_PCMCIA_POLL 43 #define CB_PCMCIA_POLL_ONLY 44 #define LEVEL2 45 */ 46 47 #include <sys/types.h> 48 #include <sys/param.h> 49 #include <sys/systm.h> 50 #include <sys/kernel.h> 51 #include <sys/errno.h> 52 #include <sys/ioctl.h> 53 #include <sys/syslog.h> 54 #include <sys/device.h> 55 #include <sys/malloc.h> 56 57 #include <machine/intr.h> 58 #include <machine/bus.h> 59 60 #include <dev/pci/pcivar.h> 61 #include <dev/pci/pcireg.h> 62 #include <dev/pci/pcidevs.h> 63 64 #include <dev/pci/pccbbreg.h> 65 66 #include <dev/cardbus/cardslotvar.h> 67 68 #include <dev/cardbus/cardbusvar.h> 69 70 #include <dev/pcmcia/pcmciareg.h> 71 #include <dev/pcmcia/pcmciavar.h> 72 73 #include <dev/ic/i82365reg.h> 74 #include <dev/ic/i82365var.h> 75 #include <dev/pci/pccbbvar.h> 76 77 #ifndef __NetBSD_Version__ 78 struct cfdriver cbb_cd = { 79 NULL, "cbb", DV_DULL 80 }; 81 #endif 82 83 #if defined CBB_DEBUG 84 #define DPRINTF(x) printf x 85 #else 86 #define DPRINTF(x) 87 #endif 88 89 int pcicbbmatch __P((struct device *, void *, void *)); 90 void pccbbattach __P((struct device *, struct device *, void *)); 91 int pccbbintr __P((void *)); 92 void pccbb_shutdown __P((void *)); 93 void pci113x_insert __P((void *)); 94 int pccbbintr_function __P((struct pccbb_softc *)); 95 96 int pccbb_detect_card __P((struct pccbb_softc *)); 97 98 void pccbb_pcmcia_write __P((struct pcic_handle *, int, int)); 99 u_int8_t pccbb_pcmcia_read __P((struct pcic_handle *, int)); 100 #define Pcic_read(ph, reg) ((ph)->ph_read((ph), (reg))) 101 #define Pcic_write(ph, reg, val) ((ph)->ph_write((ph), (reg), (val))) 102 103 int cb_reset __P((struct pccbb_softc *)); 104 int cb_detect_voltage __P((struct pccbb_softc *)); 105 int cbbprint __P((void *, const char *)); 106 107 int cb_chipset __P((u_int32_t, int *)); 108 void pccbb_pcmcia_attach_setup __P((struct pccbb_softc *, 109 struct pcmciabus_attach_args *)); 110 #if 0 111 void pccbb_pcmcia_attach_card __P((struct pcic_handle *)); 112 void pccbb_pcmcia_detach_card __P((struct pcic_handle *, int)); 113 void pccbb_pcmcia_deactivate_card __P((struct pcic_handle *)); 114 #endif 115 116 int pccbb_ctrl __P((cardbus_chipset_tag_t, int)); 117 int pccbb_power __P((cardbus_chipset_tag_t, int)); 118 int pccbb_cardenable __P((struct pccbb_softc * sc, int function)); 119 #if !rbus 120 int pccbb_io_open __P((cardbus_chipset_tag_t, int, u_int32_t, u_int32_t)); 121 int pccbb_io_close __P((cardbus_chipset_tag_t, int)); 122 int pccbb_mem_open __P((cardbus_chipset_tag_t, int, u_int32_t, u_int32_t)); 123 int pccbb_mem_close __P((cardbus_chipset_tag_t, int)); 124 #endif /* !rbus */ 125 void *pccbb_intr_establish __P((struct pccbb_softc *, int irq, int level, 126 int (*ih) (void *), void *sc)); 127 void pccbb_intr_disestablish __P((struct pccbb_softc *, void *ih)); 128 129 void *pccbb_cb_intr_establish __P((cardbus_chipset_tag_t, int irq, int level, 130 int (*ih) (void *), void *sc)); 131 void pccbb_cb_intr_disestablish __P((cardbus_chipset_tag_t ct, void *ih)); 132 133 cardbustag_t pccbb_make_tag __P((cardbus_chipset_tag_t, int, int, int)); 134 void pccbb_free_tag __P((cardbus_chipset_tag_t, cardbustag_t)); 135 cardbusreg_t pccbb_conf_read __P((cardbus_chipset_tag_t, cardbustag_t, int)); 136 void pccbb_conf_write __P((cardbus_chipset_tag_t, cardbustag_t, int, 137 cardbusreg_t)); 138 void pccbb_chipinit __P((struct pccbb_softc *)); 139 140 int pccbb_pcmcia_mem_alloc __P((pcmcia_chipset_handle_t, bus_size_t, 141 struct pcmcia_mem_handle *)); 142 void pccbb_pcmcia_mem_free __P((pcmcia_chipset_handle_t, 143 struct pcmcia_mem_handle *)); 144 int pccbb_pcmcia_mem_map __P((pcmcia_chipset_handle_t, int, bus_addr_t, 145 bus_size_t, struct pcmcia_mem_handle *, bus_addr_t *, int *)); 146 void pccbb_pcmcia_mem_unmap __P((pcmcia_chipset_handle_t, int)); 147 int pccbb_pcmcia_io_alloc __P((pcmcia_chipset_handle_t, bus_addr_t, 148 bus_size_t, bus_size_t, struct pcmcia_io_handle *)); 149 void pccbb_pcmcia_io_free __P((pcmcia_chipset_handle_t, 150 struct pcmcia_io_handle *)); 151 int pccbb_pcmcia_io_map __P((pcmcia_chipset_handle_t, int, bus_addr_t, 152 bus_size_t, struct pcmcia_io_handle *, int *)); 153 void pccbb_pcmcia_io_unmap __P((pcmcia_chipset_handle_t, int)); 154 void *pccbb_pcmcia_intr_establish __P((pcmcia_chipset_handle_t, 155 struct pcmcia_function *, int, int (*)(void *), void *)); 156 void pccbb_pcmcia_intr_disestablish __P((pcmcia_chipset_handle_t, 157 void *)); 158 void pccbb_pcmcia_socket_enable __P((pcmcia_chipset_handle_t)); 159 void pccbb_pcmcia_socket_disable __P((pcmcia_chipset_handle_t)); 160 int pccbb_pcmcia_card_detect __P((pcmcia_chipset_handle_t pch)); 161 162 void pccbb_pcmcia_do_io_map __P((struct pcic_handle *, int)); 163 void pccbb_pcmcia_wait_ready __P((struct pcic_handle *)); 164 void pccbb_pcmcia_do_mem_map __P((struct pcic_handle *, int)); 165 void pccbb_powerhook __P((int, void *)); 166 167 /* bus-space allocation and deallocation functions */ 168 #if rbus 169 170 int pccbb_rbus_cb_space_alloc __P((cardbus_chipset_tag_t, rbus_tag_t, 171 bus_addr_t addr, bus_size_t size, bus_addr_t mask, bus_size_t align, 172 int flags, bus_addr_t * addrp, bus_space_handle_t * bshp)); 173 int pccbb_rbus_cb_space_free __P((cardbus_chipset_tag_t, rbus_tag_t, 174 bus_space_handle_t, bus_size_t)); 175 176 #endif /* rbus */ 177 178 #if rbus 179 180 int pccbb_open_win __P((struct pccbb_softc *, bus_space_tag_t, 181 bus_addr_t, bus_size_t, bus_space_handle_t, int flags)); 182 int pccbb_close_win __P((struct pccbb_softc *, bus_space_tag_t, 183 bus_space_handle_t, bus_size_t)); 184 int pccbb_winlist_insert __P((struct pccbb_win_chain_head *, bus_addr_t, 185 bus_size_t, bus_space_handle_t, int)); 186 int pccbb_winlist_delete __P((struct pccbb_win_chain_head *, 187 bus_space_handle_t, bus_size_t)); 188 void pccbb_winset __P((bus_addr_t align, struct pccbb_softc *, 189 bus_space_tag_t)); 190 void pccbb_winlist_show(struct pccbb_win_chain *); 191 192 #endif /* rbus */ 193 194 /* for config_defer */ 195 void pccbb_pci_callback __P((struct device *)); 196 197 #if defined SHOW_REGS 198 void cb_show_regs __P((pci_chipset_tag_t, pcitag_t, bus_space_tag_t, 199 bus_space_handle_t memh)); 200 #endif 201 202 struct cfattach cbb_pci_ca = { 203 sizeof(struct pccbb_softc), pcicbbmatch, pccbbattach 204 }; 205 206 static struct pcmcia_chip_functions pccbb_pcmcia_funcs = { 207 pccbb_pcmcia_mem_alloc, 208 pccbb_pcmcia_mem_free, 209 pccbb_pcmcia_mem_map, 210 pccbb_pcmcia_mem_unmap, 211 pccbb_pcmcia_io_alloc, 212 pccbb_pcmcia_io_free, 213 pccbb_pcmcia_io_map, 214 pccbb_pcmcia_io_unmap, 215 pccbb_pcmcia_intr_establish, 216 pccbb_pcmcia_intr_disestablish, 217 pccbb_pcmcia_socket_enable, 218 pccbb_pcmcia_socket_disable, 219 pccbb_pcmcia_card_detect 220 }; 221 222 #if rbus 223 static struct cardbus_functions pccbb_funcs = { 224 pccbb_rbus_cb_space_alloc, 225 pccbb_rbus_cb_space_free, 226 pccbb_cb_intr_establish, 227 pccbb_cb_intr_disestablish, 228 pccbb_ctrl, 229 pccbb_power, 230 pccbb_make_tag, 231 pccbb_free_tag, 232 pccbb_conf_read, 233 pccbb_conf_write, 234 }; 235 #else 236 static struct cardbus_functions pccbb_funcs = { 237 pccbb_ctrl, 238 pccbb_power, 239 pccbb_mem_open, 240 pccbb_mem_close, 241 pccbb_io_open, 242 pccbb_io_close, 243 pccbb_cb_intr_establish, 244 pccbb_cb_intr_disestablish, 245 pccbb_make_tag, 246 pccbb_conf_read, 247 pccbb_conf_write, 248 }; 249 #endif 250 251 int 252 pcicbbmatch(parent, match, aux) 253 struct device *parent; 254 void *match; 255 void *aux; 256 { 257 struct pci_attach_args *pa = (struct pci_attach_args *)aux; 258 259 if (PCI_CLASS(pa->pa_class) == PCI_CLASS_BRIDGE && 260 PCI_SUBCLASS(pa->pa_class) == PCI_SUBCLASS_BRIDGE_CARDBUS && 261 PCI_INTERFACE(pa->pa_class) == 0) { 262 return 1; 263 } 264 265 return 0; 266 } 267 268 #define MAKEID(vendor, prod) (((vendor) << PCI_VENDOR_SHIFT) \ 269 | ((prod) << PCI_PRODUCT_SHIFT)) 270 271 struct yenta_chipinfo { 272 pcireg_t yc_id; /* vendor tag | product tag */ 273 int yc_chiptype; 274 int yc_flags; 275 } yc_chipsets[] = { 276 /* Texas Instruments chips */ 277 { MAKEID(PCI_VENDOR_TI, PCI_PRODUCT_TI_PCI1130), CB_TI113X, 278 PCCBB_PCMCIA_IO_RELOC | PCCBB_PCMCIA_MEM_32}, 279 { MAKEID(PCI_VENDOR_TI, PCI_PRODUCT_TI_PCI1131), CB_TI113X, 280 PCCBB_PCMCIA_IO_RELOC | PCCBB_PCMCIA_MEM_32}, 281 { MAKEID(PCI_VENDOR_TI, PCI_PRODUCT_TI_PCI1250), CB_TI12XX, 282 PCCBB_PCMCIA_IO_RELOC | PCCBB_PCMCIA_MEM_32}, 283 { MAKEID(PCI_VENDOR_TI, PCI_PRODUCT_TI_PCI1220), CB_TI12XX, 284 PCCBB_PCMCIA_IO_RELOC | PCCBB_PCMCIA_MEM_32}, 285 { MAKEID(PCI_VENDOR_TI, PCI_PRODUCT_TI_PCI1221), CB_TI12XX, 286 PCCBB_PCMCIA_IO_RELOC | PCCBB_PCMCIA_MEM_32}, 287 { MAKEID(PCI_VENDOR_TI, PCI_PRODUCT_TI_PCI1225), CB_TI12XX, 288 PCCBB_PCMCIA_IO_RELOC | PCCBB_PCMCIA_MEM_32}, 289 { MAKEID(PCI_VENDOR_TI, PCI_PRODUCT_TI_PCI1251), CB_TI12XX, 290 PCCBB_PCMCIA_IO_RELOC | PCCBB_PCMCIA_MEM_32}, 291 { MAKEID(PCI_VENDOR_TI, PCI_PRODUCT_TI_PCI1251B), CB_TI12XX, 292 PCCBB_PCMCIA_IO_RELOC | PCCBB_PCMCIA_MEM_32}, 293 { MAKEID(PCI_VENDOR_TI, PCI_PRODUCT_TI_PCI1211), CB_TI12XX, 294 PCCBB_PCMCIA_IO_RELOC | PCCBB_PCMCIA_MEM_32}, 295 { MAKEID(PCI_VENDOR_TI, PCI_PRODUCT_TI_PCI1420), CB_TI12XX, 296 PCCBB_PCMCIA_IO_RELOC | PCCBB_PCMCIA_MEM_32}, 297 { MAKEID(PCI_VENDOR_TI, PCI_PRODUCT_TI_PCI1450), CB_TI12XX, 298 PCCBB_PCMCIA_IO_RELOC | PCCBB_PCMCIA_MEM_32}, 299 { MAKEID(PCI_VENDOR_TI, PCI_PRODUCT_TI_PCI1451), CB_TI12XX, 300 PCCBB_PCMCIA_IO_RELOC | PCCBB_PCMCIA_MEM_32}, 301 302 /* Ricoh chips */ 303 { MAKEID(PCI_VENDOR_RICOH, PCI_PRODUCT_RICOH_RF5C475), CB_RX5C47X, 304 PCCBB_PCMCIA_MEM_32}, 305 { MAKEID(PCI_VENDOR_RICOH, PCI_PRODUCT_RICOH_RF5C476), CB_RX5C47X, 306 PCCBB_PCMCIA_MEM_32}, 307 { MAKEID(PCI_VENDOR_RICOH, PCI_PRODUCT_RICOH_RF5C477), CB_RX5C47X, 308 PCCBB_PCMCIA_MEM_32}, 309 { MAKEID(PCI_VENDOR_RICOH, PCI_PRODUCT_RICOH_RF5C478), CB_RX5C47X, 310 PCCBB_PCMCIA_MEM_32}, 311 { MAKEID(PCI_VENDOR_RICOH, PCI_PRODUCT_RICOH_RF5C465), CB_RX5C46X, 312 PCCBB_PCMCIA_MEM_32}, 313 { MAKEID(PCI_VENDOR_RICOH, PCI_PRODUCT_RICOH_RF5C466), CB_RX5C46X, 314 PCCBB_PCMCIA_MEM_32}, 315 316 /* Toshiba products */ 317 { MAKEID(PCI_VENDOR_TOSHIBA2, PCI_PRODUCT_TOSHIBA2_ToPIC95), 318 CB_TOPIC95, PCCBB_PCMCIA_MEM_32}, 319 { MAKEID(PCI_VENDOR_TOSHIBA2, PCI_PRODUCT_TOSHIBA2_ToPIC95B), 320 CB_TOPIC95B, PCCBB_PCMCIA_MEM_32}, 321 { MAKEID(PCI_VENDOR_TOSHIBA2, PCI_PRODUCT_TOSHIBA2_ToPIC97), 322 CB_TOPIC97, PCCBB_PCMCIA_MEM_32}, 323 { MAKEID(PCI_VENDOR_TOSHIBA2, PCI_PRODUCT_TOSHIBA2_ToPIC100), 324 CB_TOPIC97, PCCBB_PCMCIA_MEM_32}, 325 326 /* Cirrus Logic products */ 327 { MAKEID(PCI_VENDOR_CIRRUS, PCI_PRODUCT_CIRRUS_CL_PD6832), 328 CB_CIRRUS, PCCBB_PCMCIA_MEM_32}, 329 { MAKEID(PCI_VENDOR_CIRRUS, PCI_PRODUCT_CIRRUS_CL_PD6833), 330 CB_CIRRUS, PCCBB_PCMCIA_MEM_32}, 331 332 /* sentinel, or Generic chip */ 333 { 0 /* null id */ , CB_UNKNOWN, PCCBB_PCMCIA_MEM_32}, 334 }; 335 336 int 337 cb_chipset(pci_id, flagp) 338 u_int32_t pci_id; 339 int *flagp; 340 { 341 struct yenta_chipinfo *yc; 342 343 /* Loop over except the last default entry. */ 344 for (yc = yc_chipsets; yc < yc_chipsets + 345 sizeof(yc_chipsets) / sizeof(yc_chipsets[0]) - 1; yc++) 346 if (pci_id == yc->yc_id) 347 break; 348 349 if (flagp != NULL) 350 *flagp = yc->yc_flags; 351 352 return (yc->yc_chiptype); 353 } 354 355 void 356 pccbb_shutdown(void *arg) 357 { 358 struct pccbb_softc *sc = arg; 359 pcireg_t command; 360 361 DPRINTF(("%s: shutdown\n", sc->sc_dev.dv_xname)); 362 363 /* turn off power */ 364 pccbb_power((cardbus_chipset_tag_t)sc, CARDBUS_VCC_0V | CARDBUS_VPP_0V); 365 366 bus_space_write_4(sc->sc_base_memt, sc->sc_base_memh, CB_SOCKET_MASK, 367 0); 368 369 command = pci_conf_read(sc->sc_pc, sc->sc_tag, PCI_COMMAND_STATUS_REG); 370 371 command &= ~(PCI_COMMAND_IO_ENABLE | PCI_COMMAND_MEM_ENABLE | 372 PCI_COMMAND_MASTER_ENABLE); 373 pci_conf_write(sc->sc_pc, sc->sc_tag, PCI_COMMAND_STATUS_REG, command); 374 } 375 376 void 377 pccbbattach(parent, self, aux) 378 struct device *parent; 379 struct device *self; 380 void *aux; 381 { 382 struct pccbb_softc *sc = (void *)self; 383 struct pci_attach_args *pa = aux; 384 pci_chipset_tag_t pc = pa->pa_pc; 385 pcireg_t busreg, reg, sock_base; 386 pci_intr_handle_t ih; 387 const char *intrstr = NULL; 388 bus_addr_t sockbase; 389 int flags; 390 391 sc->sc_chipset = cb_chipset(pa->pa_id, &flags); 392 393 #ifdef CBB_DEBUG 394 printf(" (chipflags %x)", flags); 395 #endif 396 397 TAILQ_INIT(&sc->sc_memwindow); 398 TAILQ_INIT(&sc->sc_iowindow); 399 400 #if rbus 401 sc->sc_rbus_iot = rbus_pccbb_parent_io(pa); 402 sc->sc_rbus_memt = rbus_pccbb_parent_mem(pa); 403 #endif /* rbus */ 404 405 sc->sc_base_memh = 0; 406 407 /* 408 * MAP socket registers and ExCA registers on memory-space 409 * When no valid address is set on socket base registers (on pci 410 * config space), get it not polite way. 411 */ 412 sock_base = pci_conf_read(pc, pa->pa_tag, PCI_SOCKBASE); 413 414 if (PCI_MAPREG_MEM_ADDR(sock_base) >= 0x100000 && 415 PCI_MAPREG_MEM_ADDR(sock_base) != 0xfffffff0) { 416 /* The address must be valid. */ 417 if (pci_mapreg_map(pa, PCI_SOCKBASE, PCI_MAPREG_TYPE_MEM, 0, 418 &sc->sc_base_memt, &sc->sc_base_memh, &sockbase, NULL, 0)) 419 { 420 printf("%s: can't map socket base address 0x%x\n", 421 sc->sc_dev.dv_xname, sock_base); 422 /* 423 * I think it's funny: socket base registers must be 424 * mapped on memory space, but ... 425 */ 426 if (pci_mapreg_map(pa, PCI_SOCKBASE, 427 PCI_MAPREG_TYPE_IO, 0, &sc->sc_base_memt, 428 &sc->sc_base_memh, &sockbase, NULL, 0)) { 429 printf("%s: can't map socket base address" 430 " 0x%lx: io mode\n", sc->sc_dev.dv_xname, 431 sockbase); 432 /* give up... allocate reg space via rbus. */ 433 sc->sc_base_memh = 0; 434 pci_conf_write(pc, pa->pa_tag, PCI_SOCKBASE, 0); 435 } 436 } else { 437 DPRINTF(("%s: socket base address 0x%lx\n", 438 sc->sc_dev.dv_xname, sockbase)); 439 } 440 } 441 442 sc->sc_mem_start = 0; /* XXX */ 443 sc->sc_mem_end = 0xffffffff; /* XXX */ 444 445 /* 446 * When bus number isn't set correctly, give up using 32-bit CardBus 447 * mode. 448 */ 449 busreg = pci_conf_read(pc, pa->pa_tag, PCI_BUSNUM); 450 #if notyet 451 if (((busreg >> 8) & 0xff) == 0) { 452 printf(": CardBus support disabled because of unconfigured bus number\n"); 453 flags |= PCCBB_PCMCIA_16BITONLY; 454 } 455 #endif 456 457 /* pccbb_machdep.c end */ 458 459 #if defined CBB_DEBUG 460 { 461 static char *intrname[5] = { "NON", "A", "B", "C", "D" }; 462 printf(": intrpin %s, intrtag %d\n", 463 intrname[pa->pa_intrpin], pa->pa_intrline); 464 } 465 #endif 466 467 /* setup softc */ 468 sc->sc_pc = pc; 469 sc->sc_iot = pa->pa_iot; 470 sc->sc_memt = pa->pa_memt; 471 sc->sc_dmat = pa->pa_dmat; 472 sc->sc_tag = pa->pa_tag; 473 sc->sc_function = pa->pa_function; 474 sc->sc_sockbase = sock_base; 475 sc->sc_busnum = busreg; 476 477 sc->sc_intrline = pa->pa_intrline; 478 sc->sc_intrtag = pa->pa_intrtag; 479 sc->sc_intrpin = pa->pa_intrpin; 480 481 sc->sc_pcmcia_flags = flags; /* set PCMCIA facility */ 482 483 /* Map and establish the interrupt. */ 484 if (pci_intr_map(pc, sc->sc_intrtag, sc->sc_intrpin, 485 sc->sc_intrline, &ih)) { 486 printf(": couldn't map interrupt\n"); 487 return; 488 } 489 intrstr = pci_intr_string(pc, ih); 490 491 /* 492 * XXX pccbbintr should be called under the priority lower 493 * than any other hard interrputs. 494 */ 495 sc->sc_ih = pci_intr_establish(pc, ih, IPL_BIO, pccbbintr, sc, 496 sc->sc_dev.dv_xname); 497 498 if (sc->sc_ih == NULL) { 499 printf(": couldn't establish interrupt"); 500 if (intrstr != NULL) { 501 printf(" at %s", intrstr); 502 } 503 printf("\n"); 504 return; 505 } 506 printf(": %s\n", intrstr); 507 508 shutdownhook_establish(pccbb_shutdown, sc); 509 510 /* Disable legacy register mapping. */ 511 switch (sc->sc_chipset) { 512 case CB_RX5C46X: /* fallthrough */ 513 #if 0 514 /* The RX5C47X-series requires writes to the PCI_LEGACY register. */ 515 case CB_RX5C47X: 516 #endif 517 /* 518 * The legacy pcic io-port on Ricoh RX5C46X CardBus bridges 519 * cannot be disabled by substituting 0 into PCI_LEGACY 520 * register. Ricoh CardBus bridges have special bits on Bridge 521 * control reg (addr 0x3e on PCI config space). 522 */ 523 reg = pci_conf_read(pc, pa->pa_tag, PCI_BCR_INTR); 524 reg &= ~(CB_BCRI_RL_3E0_ENA | CB_BCRI_RL_3E2_ENA); 525 pci_conf_write(pc, pa->pa_tag, PCI_BCR_INTR, reg); 526 break; 527 528 default: 529 /* XXX I don't know proper way to kill legacy I/O. */ 530 pci_conf_write(pc, pa->pa_tag, PCI_LEGACY, 0x0); 531 break; 532 } 533 534 timeout_set(&sc->sc_ins_tmo, pci113x_insert, sc); 535 config_defer(self, pccbb_pci_callback); 536 } 537 538 539 540 541 /* 542 * void pccbb_pci_callback(struct device *self) 543 * 544 * The actual attach routine: get memory space for YENTA register 545 * space, setup YENTA register and route interrupt. 546 * 547 * This function should be deferred because this device may obtain 548 * memory space dynamically. This function must avoid obtaining 549 * memory area which has already kept for another device. Also, 550 * this function MUST be done before ISA attach process because this 551 * function kills pcic compatible port used by ISA pcic. 552 */ 553 void 554 pccbb_pci_callback(self) 555 struct device *self; 556 { 557 struct pccbb_softc *sc = (void *)self; 558 pci_chipset_tag_t pc = sc->sc_pc; 559 bus_space_tag_t base_memt; 560 bus_space_handle_t base_memh; 561 u_int32_t maskreg; 562 bus_addr_t sockbase; 563 struct cbslot_attach_args cba; 564 struct pcmciabus_attach_args paa; 565 struct cardslot_attach_args caa; 566 struct cardslot_softc *csc; 567 568 if (0 == sc->sc_base_memh) { 569 /* The socket registers aren't mapped correctly. */ 570 #if rbus 571 if (rbus_space_alloc(sc->sc_rbus_memt, 0, 0x1000, 0x0fff, 572 (sc->sc_chipset == CB_RX5C47X 573 || sc->sc_chipset == CB_TI113X) ? 0x10000 : 0x1000, 574 0, &sockbase, &sc->sc_base_memh)) { 575 return; 576 } 577 sc->sc_base_memt = sc->sc_memt; 578 pci_conf_write(pc, sc->sc_tag, PCI_SOCKBASE, sockbase); 579 DPRINTF(("%s: CardBus resister address 0x%lx -> 0x%x\n", 580 sc->sc_dev.dv_xname, sockbase, pci_conf_read(pc, sc->sc_tag, 581 PCI_SOCKBASE))); 582 #else 583 sc->sc_base_memt = sc->sc_memt; 584 #if !defined CBB_PCI_BASE 585 #define CBB_PCI_BASE 0x20000000 586 #endif 587 if (bus_space_alloc(sc->sc_base_memt, CBB_PCI_BASE, 0xffffffff, 588 0x1000, 0x1000, 0, 0, &sockbase, &sc->sc_base_memh)) { 589 /* cannot allocate memory space */ 590 return; 591 } 592 pci_conf_write(pc, sc->sc_tag, PCI_SOCKBASE, sockbase); 593 DPRINTF(("%s: CardBus resister address 0x%x -> 0x%x\n", 594 sc->sc_dev.dv_xname, sock_base, pci_conf_read(pc, 595 sc->sc_tag, PCI_SOCKBASE))); 596 #endif 597 } 598 599 /* bus bridge initialization */ 600 pccbb_chipinit(sc); 601 602 base_memt = sc->sc_base_memt; /* socket regs memory tag */ 603 base_memh = sc->sc_base_memh; /* socket regs memory handle */ 604 605 /* clear data structure for child device interrupt handlers */ 606 sc->sc_pil = NULL; 607 sc->sc_pil_intr_enable = 1; 608 609 powerhook_establish(pccbb_powerhook, sc); 610 611 { 612 u_int32_t sockstat = 613 bus_space_read_4(base_memt, base_memh, CB_SOCKET_STAT); 614 if (0 == (sockstat & CB_SOCKET_STAT_CD)) { 615 sc->sc_flags |= CBB_CARDEXIST; 616 } 617 } 618 619 /* 620 * attach cardbus 621 */ 622 if (!(sc->sc_pcmcia_flags & PCCBB_PCMCIA_16BITONLY)) { 623 pcireg_t busreg = pci_conf_read(pc, sc->sc_tag, PCI_BUSNUM); 624 pcireg_t bhlc = pci_conf_read(pc, sc->sc_tag, PCI_BHLC_REG); 625 626 /* initialize cbslot_attach */ 627 cba.cba_busname = "cardbus"; 628 cba.cba_iot = sc->sc_iot; 629 cba.cba_memt = sc->sc_memt; 630 cba.cba_dmat = sc->sc_dmat; 631 cba.cba_bus = (busreg >> 8) & 0x0ff; 632 cba.cba_cc = (void *)sc; 633 cba.cba_cf = &pccbb_funcs; 634 cba.cba_intrline = sc->sc_intrline; 635 636 #if rbus 637 cba.cba_rbus_iot = sc->sc_rbus_iot; 638 cba.cba_rbus_memt = sc->sc_rbus_memt; 639 #endif 640 641 cba.cba_cacheline = PCI_CACHELINE(bhlc); 642 cba.cba_lattimer = PCI_CB_LATENCY(busreg); 643 644 #if defined CBB_DEBUG 645 printf("%s: cacheline 0x%x lattimer 0x%x\n", 646 sc->sc_dev.dv_xname, cba.cba_cacheline, cba.cba_lattimer); 647 printf("%s: bhlc 0x%x lscp 0x%x\n", sc->sc_dev.dv_xname, bhlc, 648 busreg); 649 #endif 650 #if defined SHOW_REGS 651 cb_show_regs(sc->sc_pc, sc->sc_tag, sc->sc_base_memt, 652 sc->sc_base_memh); 653 #endif 654 } 655 656 pccbb_pcmcia_attach_setup(sc, &paa); 657 caa.caa_cb_attach = NULL; 658 if (!(sc->sc_pcmcia_flags & PCCBB_PCMCIA_16BITONLY)) { 659 caa.caa_cb_attach = &cba; 660 } 661 caa.caa_16_attach = &paa; 662 caa.caa_ph = &sc->sc_pcmcia_h; 663 664 if (NULL != (csc = (void *)config_found(self, &caa, cbbprint))) { 665 DPRINTF(("pccbbattach: found cardslot\n")); 666 sc->sc_csc = csc; 667 } 668 669 sc->sc_ints_on = 1; 670 671 /* CSC Interrupt: Card detect interrupt on */ 672 maskreg = bus_space_read_4(base_memt, base_memh, CB_SOCKET_MASK); 673 maskreg |= CB_SOCKET_MASK_CD; /* Card detect intr is turned on. */ 674 bus_space_write_4(base_memt, base_memh, CB_SOCKET_MASK, maskreg); 675 /* reset interrupt */ 676 bus_space_write_4(base_memt, base_memh, CB_SOCKET_EVENT, 677 bus_space_read_4(base_memt, base_memh, CB_SOCKET_EVENT)); 678 679 return; 680 } 681 682 683 684 685 686 /* 687 * void pccbb_chipinit(struct pccbb_softc *sc) 688 * 689 * This function initialize YENTA chip registers listed below: 690 * 1) PCI command reg, 691 * 2) PCI and CardBus latency timer, 692 * 3) route PCI interrupt, 693 * 4) close all memory and io windows. 694 */ 695 void 696 pccbb_chipinit(sc) 697 struct pccbb_softc *sc; 698 { 699 pci_chipset_tag_t pc = sc->sc_pc; 700 pcitag_t tag = sc->sc_tag; 701 pcireg_t reg; 702 703 /* 704 * Set PCI command reg. 705 * Some laptop's BIOSes (i.e. TICO) do not enable CardBus chip. 706 */ 707 reg = pci_conf_read(pc, tag, PCI_COMMAND_STATUS_REG); 708 /* I believe it is harmless. */ 709 reg |= (PCI_COMMAND_IO_ENABLE | PCI_COMMAND_MEM_ENABLE | 710 PCI_COMMAND_MASTER_ENABLE); 711 pci_conf_write(pc, tag, PCI_COMMAND_STATUS_REG, reg); 712 713 /* 714 * Set CardBus latency timer. 715 */ 716 reg = pci_conf_read(pc, tag, PCI_CB_LSCP_REG); 717 if (PCI_CB_LATENCY(reg) < 0x20) { 718 reg &= ~(PCI_CB_LATENCY_MASK << PCI_CB_LATENCY_SHIFT); 719 reg |= (0x20 << PCI_CB_LATENCY_SHIFT); 720 pci_conf_write(pc, tag, PCI_CB_LSCP_REG, reg); 721 } 722 DPRINTF(("CardBus latency timer 0x%x (%x)\n", 723 PCI_CB_LATENCY(reg), pci_conf_read(pc, tag, PCI_CB_LSCP_REG))); 724 725 /* 726 * Set PCI latency timer. 727 */ 728 reg = pci_conf_read(pc, tag, PCI_BHLC_REG); 729 if (PCI_LATTIMER(reg) < 0x10) { 730 reg &= ~(PCI_LATTIMER_MASK << PCI_LATTIMER_SHIFT); 731 reg |= (0x10 << PCI_LATTIMER_SHIFT); 732 pci_conf_write(pc, tag, PCI_BHLC_REG, reg); 733 } 734 DPRINTF(("PCI latency timer 0x%x (%x)\n", 735 PCI_LATTIMER(reg), pci_conf_read(pc, tag, PCI_BHLC_REG))); 736 737 /* Route functional interrupts to PCI. */ 738 reg = pci_conf_read(pc, tag, PCI_BCR_INTR); 739 reg |= CB_BCR_INTR_IREQ_ENABLE; /* disable PCI Intr */ 740 reg |= CB_BCR_WRITE_POST_ENABLE; /* enable write post */ 741 reg |= CB_BCR_RESET_ENABLE; /* assert reset */ 742 pci_conf_write(pc, tag, PCI_BCR_INTR, reg); 743 744 switch (sc->sc_chipset) { 745 case CB_TI113X: 746 reg = pci_conf_read(pc, tag, PCI_CBCTRL); 747 /* This bit is shared, but may read as 0 on some chips, so set 748 it explicitly on both functions. */ 749 reg |= PCI113X_CBCTRL_PCI_IRQ_ENA; 750 /* CSC intr enable */ 751 reg |= PCI113X_CBCTRL_PCI_CSC; 752 /* functional intr prohibit | prohibit ISA routing */ 753 reg &= ~(PCI113X_CBCTRL_PCI_INTR | PCI113X_CBCTRL_INT_MASK); 754 pci_conf_write(pc, tag, PCI_CBCTRL, reg); 755 break; 756 757 case CB_TOPIC95B: 758 reg = pci_conf_read(pc, tag, TOPIC_SOCKET_CTRL); 759 reg |= TOPIC_SOCKET_CTRL_SCR_IRQSEL; 760 pci_conf_write(pc, tag, TOPIC_SOCKET_CTRL, reg); 761 762 reg = pci_conf_read(pc, tag, TOPIC_SLOT_CTRL); 763 DPRINTF(("%s: topic slot ctrl reg 0x%x -> ", 764 sc->sc_dev.dv_xname, reg)); 765 reg |= (TOPIC_SLOT_CTRL_SLOTON | TOPIC_SLOT_CTRL_SLOTEN | 766 TOPIC_SLOT_CTRL_ID_LOCK | TOPIC_SLOT_CTRL_CARDBUS); 767 reg &= ~TOPIC_SLOT_CTRL_SWDETECT; 768 DPRINTF(("0x%x\n", reg)); 769 pci_conf_write(pc, tag, TOPIC_SLOT_CTRL, reg); 770 break; 771 } 772 773 /* Close all memory and I/O windows. */ 774 pci_conf_write(pc, tag, PCI_CB_MEMBASE0, 0xffffffff); 775 pci_conf_write(pc, tag, PCI_CB_MEMLIMIT0, 0); 776 pci_conf_write(pc, tag, PCI_CB_MEMBASE1, 0xffffffff); 777 pci_conf_write(pc, tag, PCI_CB_MEMLIMIT1, 0); 778 pci_conf_write(pc, tag, PCI_CB_IOBASE0, 0xffffffff); 779 pci_conf_write(pc, tag, PCI_CB_IOLIMIT0, 0); 780 pci_conf_write(pc, tag, PCI_CB_IOBASE1, 0xffffffff); 781 pci_conf_write(pc, tag, PCI_CB_IOLIMIT1, 0); 782 783 /* reset 16-bit pcmcia bus */ 784 bus_space_write_1(sc->sc_base_memt, sc->sc_base_memh, 785 0x800 + PCIC_INTR, 786 bus_space_read_1(sc->sc_base_memt, sc->sc_base_memh, 787 0x800 + PCIC_INTR) & ~PCIC_INTR_RESET); 788 789 /* turn off power */ 790 pccbb_power((cardbus_chipset_tag_t)sc, CARDBUS_VCC_0V | CARDBUS_VPP_0V); 791 } 792 793 794 795 796 /* 797 * void pccbb_pcmcia_attach_setup(struct pccbb_softc *sc, 798 * struct pcmciabus_attach_args *paa) 799 * 800 * This function attaches 16-bit PCcard bus. 801 */ 802 void 803 pccbb_pcmcia_attach_setup(sc, paa) 804 struct pccbb_softc *sc; 805 struct pcmciabus_attach_args *paa; 806 { 807 struct pcic_handle *ph = &sc->sc_pcmcia_h; 808 #if rbus 809 rbus_tag_t rb; 810 #endif 811 812 /* initialize pcmcia part in pccbb_softc */ 813 ph->ph_parent = (struct device *)sc; 814 ph->sock = sc->sc_function; 815 ph->flags = 0; 816 ph->shutdown = 0; 817 ph->ih_irq = sc->sc_intrline; 818 ph->ph_bus_t = sc->sc_base_memt; 819 ph->ph_bus_h = sc->sc_base_memh; 820 ph->ph_read = pccbb_pcmcia_read; 821 ph->ph_write = pccbb_pcmcia_write; 822 sc->sc_pct = &pccbb_pcmcia_funcs; 823 824 /* 825 * We need to do a few things here: 826 * 1) Disable routing of CSC and functional interrupts to ISA IRQs by 827 * setting the IRQ numbers to 0. 828 * 2) Set bit 4 of PCIC_INTR, which is needed on some chips to enable 829 * routing of CSC interrupts (e.g. card removal) to PCI while in 830 * PCMCIA mode. We just leave this set all the time. 831 * 3) Enable card insertion/removal interrupts in case the chip also 832 * needs that while in PCMCIA mode. 833 * 4) Clear any pending CSC interrupt. 834 */ 835 Pcic_write(ph, PCIC_INTR, PCIC_INTR_ENABLE | PCIC_INTR_RESET); 836 if (sc->sc_chipset == CB_TI113X) { 837 Pcic_write(ph, PCIC_CSC_INTR, 0); 838 } else { 839 Pcic_write(ph, PCIC_CSC_INTR, PCIC_CSC_INTR_CD_ENABLE); 840 Pcic_read(ph, PCIC_CSC); 841 } 842 843 /* initialize pcmcia bus attachment */ 844 paa->paa_busname = "pcmcia"; 845 paa->pct = sc->sc_pct; 846 paa->pch = ph; 847 paa->iobase = 0; /* I don't use them */ 848 paa->iosize = 0; 849 #if rbus 850 rb = ((struct pccbb_softc *)(ph->ph_parent))->sc_rbus_iot; 851 paa->iobase = rb->rb_start + rb->rb_offset; 852 paa->iosize = rb->rb_end - rb->rb_start; 853 #endif 854 855 return; 856 } 857 858 #if 0 859 void 860 pccbb_pcmcia_attach_card(ph) 861 struct pcic_handle *ph; 862 { 863 if (ph->flags & PCIC_FLAG_CARDP) { 864 panic("pccbb_pcmcia_attach_card: already attached"); 865 } 866 867 /* call the MI attach function */ 868 pcmcia_card_attach(ph->pcmcia); 869 870 ph->flags |= PCIC_FLAG_CARDP; 871 } 872 873 void 874 pccbb_pcmcia_detach_card(ph, flags) 875 struct pcic_handle *ph; 876 int flags; 877 { 878 if (!(ph->flags & PCIC_FLAG_CARDP)) { 879 panic("pccbb_pcmcia_detach_card: already detached"); 880 } 881 882 ph->flags &= ~PCIC_FLAG_CARDP; 883 884 /* call the MI detach function */ 885 pcmcia_card_detach(ph->pcmcia, flags); 886 } 887 #endif 888 889 /* 890 * int pccbbintr(arg) 891 * void *arg; 892 * This routine handles the interrupt from Yenta PCI-CardBus bridge 893 * itself. 894 */ 895 int 896 pccbbintr(arg) 897 void *arg; 898 { 899 struct pccbb_softc *sc = (struct pccbb_softc *)arg; 900 u_int32_t sockevent, sockstate; 901 bus_space_tag_t memt = sc->sc_base_memt; 902 bus_space_handle_t memh = sc->sc_base_memh; 903 struct pcic_handle *ph = &sc->sc_pcmcia_h; 904 905 if (!sc->sc_ints_on) 906 return 0; 907 908 sockevent = bus_space_read_4(memt, memh, CB_SOCKET_EVENT); 909 bus_space_write_4(memt, memh, CB_SOCKET_EVENT, sockevent); 910 Pcic_read(ph, PCIC_CSC); 911 912 if (sockevent == 0) { 913 /* This intr is not for me: it may be for my child devices. */ 914 if (sc->sc_pil_intr_enable) { 915 return pccbbintr_function(sc); 916 } else { 917 return 0; 918 } 919 } 920 921 if (sockevent & CB_SOCKET_EVENT_CD) { 922 sockstate = bus_space_read_4(memt, memh, CB_SOCKET_STAT); 923 if (CB_SOCKET_STAT_CD == (sockstate & CB_SOCKET_STAT_CD)) { 924 /* A card should be removed. */ 925 if (sc->sc_flags & CBB_CARDEXIST) { 926 DPRINTF(("%s: 0x%08x", sc->sc_dev.dv_xname, 927 sockevent)); 928 DPRINTF((" card removed, 0x%08x\n", sockstate)); 929 sc->sc_flags &= ~CBB_CARDEXIST; 930 if (sc->sc_csc->sc_status & 931 CARDSLOT_STATUS_CARD_16) { 932 #if 0 933 struct pcic_handle *ph = 934 &sc->sc_pcmcia_h; 935 936 pcmcia_card_deactivate(ph->pcmcia); 937 pccbb_pcmcia_socket_disable(ph); 938 pccbb_pcmcia_detach_card(ph, 939 DETACH_FORCE); 940 #endif 941 cardslot_event_throw(sc->sc_csc, 942 CARDSLOT_EVENT_REMOVAL_16); 943 } else if (sc->sc_csc->sc_status & 944 CARDSLOT_STATUS_CARD_CB) { 945 /* Cardbus intr removed */ 946 cardslot_event_throw(sc->sc_csc, 947 CARDSLOT_EVENT_REMOVAL_CB); 948 } 949 } 950 } else if (0x00 == (sockstate & CB_SOCKET_STAT_CD) && 951 /* 952 * The pccbbintr may called from powerdown hook when 953 * the system resumed, to detect the card 954 * insertion/removal during suspension. 955 */ 956 (sc->sc_flags & CBB_CARDEXIST) == 0) { 957 if (sc->sc_flags & CBB_INSERTING) { 958 timeout_del(&sc->sc_ins_tmo); 959 } 960 timeout_add(&sc->sc_ins_tmo, hz / 10); 961 sc->sc_flags |= CBB_INSERTING; 962 } 963 } 964 965 return (1); 966 } 967 968 /* 969 * int pccbbintr_function(struct pccbb_softc *sc) 970 * 971 * This function calls each interrupt handler registered at the 972 * bridge. The interrupt handlers are called in registered order. 973 */ 974 int 975 pccbbintr_function(sc) 976 struct pccbb_softc *sc; 977 { 978 int retval = 0, val; 979 struct pccbb_intrhand_list *pil; 980 int s, splchanged; 981 982 for (pil = sc->sc_pil; pil != NULL; pil = pil->pil_next) { 983 /* 984 * XXX priority change. gross. I use if-else 985 * sentense instead of switch-case sentense because of 986 * avoiding duplicate case value error. More than one 987 * IPL_XXX use same value. It depends on 988 * implementation. 989 */ 990 splchanged = 1; 991 #if 0 992 if (pil->pil_level == IPL_SERIAL) { 993 s = splserial(); 994 } else if (pil->pil_level == IPL_HIGH) { 995 #endif 996 if (pil->pil_level == IPL_HIGH) { 997 s = splhigh(); 998 } else if (pil->pil_level == IPL_CLOCK) { 999 s = splclock(); 1000 } else if (pil->pil_level == IPL_AUDIO) { 1001 s = splaudio(); 1002 } else if (pil->pil_level == IPL_IMP) { 1003 s = splimp(); 1004 } else if (pil->pil_level == IPL_TTY) { 1005 s = spltty(); 1006 #if 0 1007 } else if (pil->pil_level == IPL_SOFTSERIAL) { 1008 s = splsoftserial(); 1009 #endif 1010 } else if (pil->pil_level == IPL_NET) { 1011 s = splnet(); 1012 } else { 1013 splchanged = 0; 1014 /* XXX: ih lower than IPL_BIO runs w/ IPL_BIO. */ 1015 } 1016 1017 val = (*pil->pil_func)(pil->pil_arg); 1018 1019 if (splchanged != 0) { 1020 splx(s); 1021 } 1022 1023 retval = retval == 1 ? 1 : 1024 retval == 0 ? val : val != 0 ? val : retval; 1025 } 1026 1027 return retval; 1028 } 1029 1030 void 1031 pci113x_insert(arg) 1032 void *arg; 1033 { 1034 struct pccbb_softc *sc = (struct pccbb_softc *)arg; 1035 u_int32_t sockevent, sockstate; 1036 1037 sockevent = bus_space_read_4(sc->sc_base_memt, sc->sc_base_memh, 1038 CB_SOCKET_EVENT); 1039 sockstate = bus_space_read_4(sc->sc_base_memt, sc->sc_base_memh, 1040 CB_SOCKET_STAT); 1041 1042 if (0 == (sockstate & CB_SOCKET_STAT_CD)) { /* card exist */ 1043 DPRINTF(("%s: 0x%08x", sc->sc_dev.dv_xname, sockevent)); 1044 DPRINTF((" card inserted, 0x%08x\n", sockstate)); 1045 sc->sc_flags |= CBB_CARDEXIST; 1046 /* call pccard interrupt handler here */ 1047 if (sockstate & CB_SOCKET_STAT_16BIT) { 1048 /* 16-bit card found */ 1049 /* pccbb_pcmcia_attach_card(&sc->sc_pcmcia_h); */ 1050 cardslot_event_throw(sc->sc_csc, 1051 CARDSLOT_EVENT_INSERTION_16); 1052 } else if (sockstate & CB_SOCKET_STAT_CB) { 1053 /* cardbus card found */ 1054 /* cardbus_attach_card(sc->sc_csc); */ 1055 cardslot_event_throw(sc->sc_csc, 1056 CARDSLOT_EVENT_INSERTION_CB); 1057 } else { 1058 /* who are you? */ 1059 } 1060 } else { 1061 timeout_add(&sc->sc_ins_tmo, hz / 10); 1062 } 1063 } 1064 1065 #define PCCBB_PCMCIA_OFFSET 0x800 1066 u_int8_t 1067 pccbb_pcmcia_read(ph, reg) 1068 struct pcic_handle *ph; 1069 int reg; 1070 { 1071 bus_space_barrier(ph->ph_bus_t, ph->ph_bus_h, 1072 PCCBB_PCMCIA_OFFSET + reg, 1, BUS_SPACE_BARRIER_READ); 1073 1074 return bus_space_read_1(ph->ph_bus_t, ph->ph_bus_h, 1075 PCCBB_PCMCIA_OFFSET + reg); 1076 } 1077 1078 void 1079 pccbb_pcmcia_write(ph, reg, val) 1080 struct pcic_handle *ph; 1081 int reg; 1082 u_int8_t val; 1083 { 1084 bus_space_barrier(ph->ph_bus_t, ph->ph_bus_h, 1085 PCCBB_PCMCIA_OFFSET + reg, 1, BUS_SPACE_BARRIER_WRITE); 1086 1087 bus_space_write_1(ph->ph_bus_t, ph->ph_bus_h, PCCBB_PCMCIA_OFFSET + reg, 1088 val); 1089 } 1090 1091 /* 1092 * int pccbb_ctrl(cardbus_chipset_tag_t, int) 1093 */ 1094 int 1095 pccbb_ctrl(ct, command) 1096 cardbus_chipset_tag_t ct; 1097 int command; 1098 { 1099 struct pccbb_softc *sc = (struct pccbb_softc *)ct; 1100 1101 switch (command) { 1102 case CARDBUS_CD: 1103 if (2 == pccbb_detect_card(sc)) { 1104 int retval = 0; 1105 int status = cb_detect_voltage(sc); 1106 if (PCCARD_VCC_5V & status) { 1107 retval |= CARDBUS_5V_CARD; 1108 } 1109 if (PCCARD_VCC_3V & status) { 1110 retval |= CARDBUS_3V_CARD; 1111 } 1112 if (PCCARD_VCC_XV & status) { 1113 retval |= CARDBUS_XV_CARD; 1114 } 1115 if (PCCARD_VCC_YV & status) { 1116 retval |= CARDBUS_YV_CARD; 1117 } 1118 return retval; 1119 } else { 1120 return 0; 1121 } 1122 break; 1123 case CARDBUS_RESET: 1124 return cb_reset(sc); 1125 break; 1126 case CARDBUS_IO_ENABLE: /* fallthrough */ 1127 case CARDBUS_IO_DISABLE: /* fallthrough */ 1128 case CARDBUS_MEM_ENABLE: /* fallthrough */ 1129 case CARDBUS_MEM_DISABLE: /* fallthrough */ 1130 case CARDBUS_BM_ENABLE: /* fallthrough */ 1131 case CARDBUS_BM_DISABLE: /* fallthrough */ 1132 return pccbb_cardenable(sc, command); 1133 break; 1134 } 1135 1136 return 0; 1137 } 1138 1139 /* 1140 * int pccbb_power(cardbus_chipset_tag_t, int) 1141 * This function returns true when it succeeds and returns false when 1142 * it fails. 1143 */ 1144 int 1145 pccbb_power(ct, command) 1146 cardbus_chipset_tag_t ct; 1147 int command; 1148 { 1149 struct pccbb_softc *sc = (struct pccbb_softc *)ct; 1150 1151 u_int32_t status, sock_ctrl; 1152 bus_space_tag_t memt = sc->sc_base_memt; 1153 bus_space_handle_t memh = sc->sc_base_memh; 1154 1155 DPRINTF(("pccbb_power: %s and %s [%x]\n", 1156 (command & CARDBUS_VCCMASK) == CARDBUS_VCC_UC ? "CARDBUS_VCC_UC" : 1157 (command & CARDBUS_VCCMASK) == CARDBUS_VCC_5V ? "CARDBUS_VCC_5V" : 1158 (command & CARDBUS_VCCMASK) == CARDBUS_VCC_3V ? "CARDBUS_VCC_3V" : 1159 (command & CARDBUS_VCCMASK) == CARDBUS_VCC_XV ? "CARDBUS_VCC_XV" : 1160 (command & CARDBUS_VCCMASK) == CARDBUS_VCC_YV ? "CARDBUS_VCC_YV" : 1161 (command & CARDBUS_VCCMASK) == CARDBUS_VCC_0V ? "CARDBUS_VCC_0V" : 1162 "UNKNOWN", 1163 (command & CARDBUS_VPPMASK) == CARDBUS_VPP_UC ? "CARDBUS_VPP_UC" : 1164 (command & CARDBUS_VPPMASK) == CARDBUS_VPP_12V ? "CARDBUS_VPP_12V" : 1165 (command & CARDBUS_VPPMASK) == CARDBUS_VPP_VCC ? "CARDBUS_VPP_VCC" : 1166 (command & CARDBUS_VPPMASK) == CARDBUS_VPP_0V ? "CARDBUS_VPP_0V" : 1167 "UNKNOWN", command)); 1168 1169 status = bus_space_read_4(memt, memh, CB_SOCKET_STAT); 1170 sock_ctrl = bus_space_read_4(memt, memh, CB_SOCKET_CTRL); 1171 1172 switch (command & CARDBUS_VCCMASK) { 1173 case CARDBUS_VCC_UC: 1174 break; 1175 case CARDBUS_VCC_5V: 1176 if (CB_SOCKET_STAT_5VCARD & status) { /* check 5 V card */ 1177 sock_ctrl &= ~CB_SOCKET_CTRL_VCCMASK; 1178 sock_ctrl |= CB_SOCKET_CTRL_VCC_5V; 1179 } else { 1180 printf("%s: BAD voltage request: no 5 V card\n", 1181 sc->sc_dev.dv_xname); 1182 } 1183 break; 1184 case CARDBUS_VCC_3V: 1185 if (CB_SOCKET_STAT_3VCARD & status) { 1186 sock_ctrl &= ~CB_SOCKET_CTRL_VCCMASK; 1187 sock_ctrl |= CB_SOCKET_CTRL_VCC_3V; 1188 } else { 1189 printf("%s: BAD voltage request: no 3.3 V card\n", 1190 sc->sc_dev.dv_xname); 1191 } 1192 break; 1193 case CARDBUS_VCC_0V: 1194 sock_ctrl &= ~CB_SOCKET_CTRL_VCCMASK; 1195 break; 1196 default: 1197 return 0; /* power NEVER changed */ 1198 break; 1199 } 1200 1201 switch (command & CARDBUS_VPPMASK) { 1202 case CARDBUS_VPP_UC: 1203 break; 1204 case CARDBUS_VPP_0V: 1205 sock_ctrl &= ~CB_SOCKET_CTRL_VPPMASK; 1206 break; 1207 case CARDBUS_VPP_VCC: 1208 sock_ctrl &= ~CB_SOCKET_CTRL_VPPMASK; 1209 sock_ctrl |= ((sock_ctrl >> 4) & 0x07); 1210 break; 1211 case CARDBUS_VPP_12V: 1212 sock_ctrl &= ~CB_SOCKET_CTRL_VPPMASK; 1213 sock_ctrl |= CB_SOCKET_CTRL_VPP_12V; 1214 break; 1215 } 1216 1217 #if 0 1218 DPRINTF(("sock_ctrl: %x\n", sock_ctrl)); 1219 #endif 1220 bus_space_write_4(memt, memh, CB_SOCKET_CTRL, sock_ctrl); 1221 status = bus_space_read_4(memt, memh, CB_SOCKET_STAT); 1222 1223 if (status & CB_SOCKET_STAT_BADVCC) { /* bad Vcc request */ 1224 printf 1225 ("%s: bad Vcc request. sock_ctrl 0x%x, sock_status 0x%x\n", 1226 sc->sc_dev.dv_xname, sock_ctrl, status); 1227 DPRINTF(("pccbb_power: %s and %s [%x]\n", 1228 (command & CARDBUS_VCCMASK) == 1229 CARDBUS_VCC_UC ? "CARDBUS_VCC_UC" : (command & 1230 CARDBUS_VCCMASK) == 1231 CARDBUS_VCC_5V ? "CARDBUS_VCC_5V" : (command & 1232 CARDBUS_VCCMASK) == 1233 CARDBUS_VCC_3V ? "CARDBUS_VCC_3V" : (command & 1234 CARDBUS_VCCMASK) == 1235 CARDBUS_VCC_XV ? "CARDBUS_VCC_XV" : (command & 1236 CARDBUS_VCCMASK) == 1237 CARDBUS_VCC_YV ? "CARDBUS_VCC_YV" : (command & 1238 CARDBUS_VCCMASK) == 1239 CARDBUS_VCC_0V ? "CARDBUS_VCC_0V" : "UNKNOWN", 1240 (command & CARDBUS_VPPMASK) == 1241 CARDBUS_VPP_UC ? "CARDBUS_VPP_UC" : (command & 1242 CARDBUS_VPPMASK) == 1243 CARDBUS_VPP_12V ? "CARDBUS_VPP_12V" : (command & 1244 CARDBUS_VPPMASK) == 1245 CARDBUS_VPP_VCC ? "CARDBUS_VPP_VCC" : (command & 1246 CARDBUS_VPPMASK) == 1247 CARDBUS_VPP_0V ? "CARDBUS_VPP_0V" : "UNKNOWN", command)); 1248 #if 0 1249 if (command == (CARDBUS_VCC_0V | CARDBUS_VPP_0V)) { 1250 u_int32_t force = 1251 bus_space_read_4(memt, memh, CB_SOCKET_FORCE); 1252 /* Reset Bad Vcc request */ 1253 force &= ~CB_SOCKET_FORCE_BADVCC; 1254 bus_space_write_4(memt, memh, CB_SOCKET_FORCE, force); 1255 printf("new status 0x%x\n", bus_space_read_4(memt, memh, 1256 CB_SOCKET_STAT)); 1257 return 1; 1258 } 1259 #endif 1260 return 0; 1261 } 1262 1263 /* 1264 * XXX delay 300 ms: though the standard defines that the Vcc set-up 1265 * time is 20 ms, some PC-Card bridge requires longer duration. 1266 */ 1267 delay(300 * 1000); 1268 1269 return 1; /* power changed correctly */ 1270 } 1271 1272 #if defined CB_PCMCIA_POLL 1273 struct cb_poll_str { 1274 void *arg; 1275 int (*func) __P((void *)); 1276 int level; 1277 pccard_chipset_tag_t ct; 1278 int count; 1279 }; 1280 1281 static struct cb_poll_str cb_poll[10]; 1282 static int cb_poll_n = 0; 1283 1284 void cb_pcmcia_poll __P((void *arg)); 1285 1286 void 1287 cb_pcmcia_poll(arg) 1288 void *arg; 1289 { 1290 struct cb_poll_str *poll = arg; 1291 struct cbb_pcmcia_softc *psc = (void *)poll->ct->v; 1292 struct pccbb_softc *sc = psc->cpc_parent; 1293 int s; 1294 u_int32_t spsr; /* socket present-state reg */ 1295 1296 timeout(cb_pcmcia_poll, arg, hz / 10); 1297 switch (poll->level) { 1298 case IPL_NET: 1299 s = splnet(); 1300 break; 1301 case IPL_BIO: 1302 s = splbio(); 1303 break; 1304 case IPL_TTY: /* fallthrough */ 1305 default: 1306 s = spltty(); 1307 break; 1308 } 1309 1310 spsr = 1311 bus_space_read_4(sc->sc_base_memt, sc->sc_base_memh, 1312 CB_SOCKET_STAT); 1313 1314 #if defined CB_PCMCIA_POLL_ONLY && defined LEVEL2 1315 if (!(spsr & 0x40)) { /* CINT low */ 1316 #else 1317 if (1) { 1318 #endif 1319 if ((*poll->func) (poll->arg) == 1) { 1320 ++poll->count; 1321 printf("intr: reported from poller, 0x%x\n", spsr); 1322 #if defined LEVEL2 1323 } else { 1324 printf("intr: miss! 0x%x\n", spsr); 1325 #endif 1326 } 1327 } 1328 splx(s); 1329 } 1330 #endif /* defined CB_PCMCIA_POLL */ 1331 1332 /* 1333 * int pccbb_detect_card(struct pccbb_softc *sc) 1334 * return value: 0 if no card exists. 1335 * 1 if 16-bit card exists. 1336 * 2 if cardbus card exists. 1337 */ 1338 int 1339 pccbb_detect_card(sc) 1340 struct pccbb_softc *sc; 1341 { 1342 bus_space_handle_t base_memh = sc->sc_base_memh; 1343 bus_space_tag_t base_memt = sc->sc_base_memt; 1344 u_int32_t sockstat = 1345 bus_space_read_4(base_memt, base_memh, CB_SOCKET_STAT); 1346 int retval = 0; 1347 1348 /* 1349 * The SCM Microsystems TI1225-based PCI-CardBus dock card that 1350 * ships with some Lucent WaveLAN cards has only one physical slot 1351 * but OpenBSD probes two. The phantom card in the second slot can 1352 * be ignored by punting on unsupported voltages. 1353 */ 1354 if (sockstat & CB_SOCKET_STAT_XVCARD) 1355 return 0; 1356 1357 /* CD1 and CD2 asserted */ 1358 if (0x00 == (sockstat & CB_SOCKET_STAT_CD)) { 1359 /* card must be present */ 1360 if (!(CB_SOCKET_STAT_NOTCARD & sockstat)) { 1361 /* NOTACARD DEASSERTED */ 1362 if (CB_SOCKET_STAT_CB & sockstat) { 1363 /* CardBus mode */ 1364 retval = 2; 1365 } else if (CB_SOCKET_STAT_16BIT & sockstat) { 1366 /* 16-bit mode */ 1367 retval = 1; 1368 } 1369 } 1370 } 1371 return retval; 1372 } 1373 1374 /* 1375 * int cb_reset(struct pccbb_softc *sc) 1376 * This function resets CardBus card. 1377 */ 1378 int 1379 cb_reset(sc) 1380 struct pccbb_softc *sc; 1381 { 1382 /* 1383 * Reset Assert at least 20 ms 1384 * Some machines request longer duration. 1385 */ 1386 int reset_duration = 1387 (sc->sc_chipset == CB_RX5C47X ? 400 * 1000 : 40 * 1000); 1388 u_int32_t bcr = pci_conf_read(sc->sc_pc, sc->sc_tag, PCI_BCR_INTR); 1389 1390 /* Reset bit Assert (bit 6 at 0x3E) */ 1391 bcr |= CB_BCR_RESET_ENABLE; 1392 pci_conf_write(sc->sc_pc, sc->sc_tag, PCI_BCR_INTR, bcr); 1393 delay(reset_duration); 1394 1395 if (CBB_CARDEXIST & sc->sc_flags) { /* A card exists. Reset it! */ 1396 /* Reset bit Deassert (bit 6 at 0x3E) */ 1397 bcr &= ~CB_BCR_RESET_ENABLE; 1398 pci_conf_write(sc->sc_pc, sc->sc_tag, PCI_BCR_INTR, bcr); 1399 delay(reset_duration); 1400 } 1401 /* No card found on the slot. Keep Reset. */ 1402 return 1; 1403 } 1404 1405 /* 1406 * int cb_detect_voltage(struct pccbb_softc *sc) 1407 * This function detect card Voltage. 1408 */ 1409 int 1410 cb_detect_voltage(sc) 1411 struct pccbb_softc *sc; 1412 { 1413 u_int32_t psr; /* socket present-state reg */ 1414 bus_space_tag_t iot = sc->sc_base_memt; 1415 bus_space_handle_t ioh = sc->sc_base_memh; 1416 int vol = PCCARD_VCC_UKN; /* set 0 */ 1417 1418 psr = bus_space_read_4(iot, ioh, CB_SOCKET_STAT); 1419 1420 if (0x400u & psr) { 1421 vol |= PCCARD_VCC_5V; 1422 } 1423 if (0x800u & psr) { 1424 vol |= PCCARD_VCC_3V; 1425 } 1426 1427 return vol; 1428 } 1429 1430 int 1431 cbbprint(aux, pcic) 1432 void *aux; 1433 const char *pcic; 1434 { 1435 /* 1436 struct cbslot_attach_args *cba = aux; 1437 1438 if (cba->cba_slot >= 0) { 1439 printf(" slot %d", cba->cba_slot); 1440 } 1441 */ 1442 return UNCONF; 1443 } 1444 1445 /* 1446 * int pccbb_cardenable(struct pccbb_softc *sc, int function) 1447 * This function enables and disables the card 1448 */ 1449 int 1450 pccbb_cardenable(sc, function) 1451 struct pccbb_softc *sc; 1452 int function; 1453 { 1454 u_int32_t command = 1455 pci_conf_read(sc->sc_pc, sc->sc_tag, PCI_COMMAND_STATUS_REG); 1456 1457 DPRINTF(("pccbb_cardenable:")); 1458 switch (function) { 1459 case CARDBUS_IO_ENABLE: 1460 command |= PCI_COMMAND_IO_ENABLE; 1461 break; 1462 case CARDBUS_IO_DISABLE: 1463 command &= ~PCI_COMMAND_IO_ENABLE; 1464 break; 1465 case CARDBUS_MEM_ENABLE: 1466 command |= PCI_COMMAND_MEM_ENABLE; 1467 break; 1468 case CARDBUS_MEM_DISABLE: 1469 command &= ~PCI_COMMAND_MEM_ENABLE; 1470 break; 1471 case CARDBUS_BM_ENABLE: 1472 command |= PCI_COMMAND_MASTER_ENABLE; 1473 break; 1474 case CARDBUS_BM_DISABLE: 1475 command &= ~PCI_COMMAND_MASTER_ENABLE; 1476 break; 1477 default: 1478 return 0; 1479 } 1480 1481 pci_conf_write(sc->sc_pc, sc->sc_tag, PCI_COMMAND_STATUS_REG, command); 1482 DPRINTF((" command reg 0x%x\n", command)); 1483 return 1; 1484 } 1485 1486 #if !rbus 1487 /* 1488 * int pccbb_io_open(cardbus_chipset_tag_t, int, u_int32_t, u_int32_t) 1489 */ 1490 int 1491 pccbb_io_open(ct, win, start, end) 1492 cardbus_chipset_tag_t ct; 1493 int win; 1494 u_int32_t start, end; 1495 { 1496 struct pccbb_softc *sc = (struct pccbb_softc *)ct; 1497 int basereg; 1498 int limitreg; 1499 1500 if ((win < 0) || (win > 2)) { 1501 #if defined DIAGNOSTIC 1502 printf("cardbus_io_open: window out of range %d\n", win); 1503 #endif 1504 return 0; 1505 } 1506 1507 basereg = win * 8 + 0x2c; 1508 limitreg = win * 8 + 0x30; 1509 1510 DPRINTF(("pccbb_io_open: 0x%x[0x%x] - 0x%x[0x%x]\n", 1511 start, basereg, end, limitreg)); 1512 1513 pci_conf_write(sc->sc_pc, sc->sc_tag, basereg, start); 1514 pci_conf_write(sc->sc_pc, sc->sc_tag, limitreg, end); 1515 return 1; 1516 } 1517 1518 /* 1519 * int pccbb_io_close(cardbus_chipset_tag_t, int) 1520 */ 1521 int 1522 pccbb_io_close(ct, win) 1523 cardbus_chipset_tag_t ct; 1524 int win; 1525 { 1526 struct pccbb_softc *sc = (struct pccbb_softc *)ct; 1527 int basereg; 1528 int limitreg; 1529 1530 if ((win < 0) || (win > 2)) { 1531 #if defined DIAGNOSTIC 1532 printf("cardbus_io_close: window out of range %d\n", win); 1533 #endif 1534 return 0; 1535 } 1536 1537 basereg = win * 8 + 0x2c; 1538 limitreg = win * 8 + 0x30; 1539 1540 pci_conf_write(sc->sc_pc, sc->sc_tag, basereg, 0); 1541 pci_conf_write(sc->sc_pc, sc->sc_tag, limitreg, 0); 1542 return 1; 1543 } 1544 1545 /* 1546 * int pccbb_mem_open(cardbus_chipset_tag_t, int, u_int32_t, u_int32_t) 1547 */ 1548 int 1549 pccbb_mem_open(ct, win, start, end) 1550 cardbus_chipset_tag_t ct; 1551 int win; 1552 u_int32_t start, end; 1553 { 1554 struct pccbb_softc *sc = (struct pccbb_softc *)ct; 1555 int basereg; 1556 int limitreg; 1557 1558 if ((win < 0) || (win > 2)) { 1559 #if defined DIAGNOSTIC 1560 printf("cardbus_mem_open: window out of range %d\n", win); 1561 #endif 1562 return 0; 1563 } 1564 1565 basereg = win * 8 + 0x1c; 1566 limitreg = win * 8 + 0x20; 1567 1568 pci_conf_write(sc->sc_pc, sc->sc_tag, basereg, start); 1569 pci_conf_write(sc->sc_pc, sc->sc_tag, limitreg, end); 1570 return 1; 1571 } 1572 1573 /* 1574 * int pccbb_mem_close(cardbus_chipset_tag_t, int) 1575 */ 1576 int 1577 pccbb_mem_close(ct, win) 1578 cardbus_chipset_tag_t ct; 1579 int win; 1580 { 1581 struct pccbb_softc *sc = (struct pccbb_softc *)ct; 1582 int basereg; 1583 int limitreg; 1584 1585 if ((win < 0) || (win > 2)) { 1586 #if defined DIAGNOSTIC 1587 printf("cardbus_mem_close: window out of range %d\n", win); 1588 #endif 1589 return 0; 1590 } 1591 1592 basereg = win * 8 + 0x1c; 1593 limitreg = win * 8 + 0x20; 1594 1595 pci_conf_write(sc->sc_pc, sc->sc_tag, basereg, 0); 1596 pci_conf_write(sc->sc_pc, sc->sc_tag, limitreg, 0); 1597 return 1; 1598 } 1599 #endif 1600 1601 /* 1602 * void *pccbb_cb_intr_establish(cardbus_chipset_tag_t ct, 1603 * int irq, 1604 * int level, 1605 * int (* func) __P((void *)), 1606 * void *arg) 1607 * 1608 * This function registers an interrupt handler at the bridge, in 1609 * order not to call the interrupt handlers of child devices when 1610 * a card-deletion interrupt occurs. 1611 * 1612 * The arguments irq is not used because pccbb selects intr vector. 1613 */ 1614 void * 1615 pccbb_cb_intr_establish(ct, irq, level, func, arg) 1616 cardbus_chipset_tag_t ct; 1617 int irq, level; 1618 int (*func) __P((void *)); 1619 void *arg; 1620 { 1621 struct pccbb_softc *sc = (struct pccbb_softc *)ct; 1622 1623 return pccbb_intr_establish(sc, irq, level, func, arg); 1624 } 1625 1626 1627 /* 1628 * void *pccbb_cb_intr_disestablish(cardbus_chipset_tag_t ct, 1629 * void *ih) 1630 * 1631 * This function removes an interrupt handler pointed by ih. 1632 */ 1633 void 1634 pccbb_cb_intr_disestablish(ct, ih) 1635 cardbus_chipset_tag_t ct; 1636 void *ih; 1637 { 1638 struct pccbb_softc *sc = (struct pccbb_softc *)ct; 1639 1640 pccbb_intr_disestablish(sc, ih); 1641 } 1642 1643 1644 /* 1645 * void *pccbb_intr_establish(struct pccbb_softc *sc, 1646 * int irq, 1647 * int level, 1648 * int (* func) __P((void *)), 1649 * void *arg) 1650 * 1651 * This function registers an interrupt handler at the bridge, in 1652 * order not to call the interrupt handlers of child devices when 1653 * a card-deletion interrupt occurs. 1654 * 1655 * The arguments irq and level are not used. 1656 */ 1657 void * 1658 pccbb_intr_establish(sc, irq, level, func, arg) 1659 struct pccbb_softc *sc; 1660 int irq, level; 1661 int (*func) __P((void *)); 1662 void *arg; 1663 { 1664 struct pccbb_intrhand_list *pil, *newpil; 1665 pcireg_t reg; 1666 1667 DPRINTF(("pccbb_intr_establish start. %p\n", sc->sc_pil)); 1668 1669 if (sc->sc_pil == NULL) { 1670 /* initialize bridge intr routing */ 1671 reg = pci_conf_read(sc->sc_pc, sc->sc_tag, PCI_BCR_INTR); 1672 reg &= ~CB_BCR_INTR_IREQ_ENABLE; 1673 pci_conf_write(sc->sc_pc, sc->sc_tag, PCI_BCR_INTR, reg); 1674 1675 switch (sc->sc_chipset) { 1676 case CB_TI113X: 1677 reg = pci_conf_read(sc->sc_pc, sc->sc_tag, PCI_CBCTRL); 1678 /* functional intr enabled */ 1679 reg |= PCI113X_CBCTRL_PCI_INTR; 1680 pci_conf_write(sc->sc_pc, sc->sc_tag, PCI_CBCTRL, reg); 1681 break; 1682 default: 1683 break; 1684 } 1685 } 1686 1687 /* 1688 * Allocate a room for interrupt handler structure. 1689 */ 1690 newpil = (struct pccbb_intrhand_list *) 1691 malloc(sizeof(struct pccbb_intrhand_list), M_DEVBUF, M_WAITOK); 1692 1693 newpil->pil_func = func; 1694 newpil->pil_arg = arg; 1695 newpil->pil_level = level; 1696 newpil->pil_next = NULL; 1697 1698 if (sc->sc_pil == NULL) { 1699 sc->sc_pil = newpil; 1700 } else { 1701 for (pil = sc->sc_pil; pil->pil_next != NULL; 1702 pil = pil->pil_next); 1703 pil->pil_next = newpil; 1704 } 1705 1706 DPRINTF(("pccbb_intr_establish add pil. %p\n", sc->sc_pil)); 1707 1708 return newpil; 1709 } 1710 1711 /* 1712 * void *pccbb_intr_disestablish(struct pccbb_softc *sc, 1713 * void *ih) 1714 * 1715 * This function removes an interrupt handler pointed by ih. 1716 */ 1717 void 1718 pccbb_intr_disestablish(sc, ih) 1719 struct pccbb_softc *sc; 1720 void *ih; 1721 { 1722 struct pccbb_intrhand_list *pil, **pil_prev; 1723 pcireg_t reg; 1724 1725 DPRINTF(("pccbb_intr_disestablish start. %p\n", sc->sc_pil)); 1726 1727 pil_prev = &sc->sc_pil; 1728 1729 for (pil = sc->sc_pil; pil != NULL; pil = pil->pil_next) { 1730 if (pil == ih) { 1731 *pil_prev = pil->pil_next; 1732 free(pil, M_DEVBUF); 1733 DPRINTF(("pccbb_intr_disestablish frees one pil\n")); 1734 break; 1735 } 1736 pil_prev = &pil->pil_next; 1737 } 1738 1739 if (sc->sc_pil == NULL) { 1740 /* No interrupt handlers */ 1741 1742 DPRINTF(("pccbb_intr_disestablish: no interrupt handler\n")); 1743 1744 /* stop routing PCI intr */ 1745 reg = pci_conf_read(sc->sc_pc, sc->sc_tag, PCI_BCR_INTR); 1746 reg |= CB_BCR_INTR_IREQ_ENABLE; 1747 pci_conf_write(sc->sc_pc, sc->sc_tag, PCI_BCR_INTR, reg); 1748 1749 switch (sc->sc_chipset) { 1750 case CB_TI113X: 1751 reg = pci_conf_read(sc->sc_pc, sc->sc_tag, PCI_CBCTRL); 1752 /* functional intr disabled */ 1753 reg &= ~PCI113X_CBCTRL_PCI_INTR; 1754 pci_conf_write(sc->sc_pc, sc->sc_tag, PCI_CBCTRL, reg); 1755 break; 1756 default: 1757 break; 1758 } 1759 } 1760 } 1761 1762 #if defined SHOW_REGS 1763 void 1764 cb_show_regs(pc, tag, memt, memh) 1765 pci_chipset_tag_t pc; 1766 pcitag_t tag; 1767 bus_space_tag_t memt; 1768 bus_space_handle_t memh; 1769 { 1770 int i; 1771 printf("PCI config regs:"); 1772 for (i = 0; i < 0x50; i += 4) { 1773 if (i % 16 == 0) { 1774 printf("\n 0x%02x:", i); 1775 } 1776 printf(" %08x", pci_conf_read(pc, tag, i)); 1777 } 1778 for (i = 0x80; i < 0xb0; i += 4) { 1779 if (i % 16 == 0) { 1780 printf("\n 0x%02x:", i); 1781 } 1782 printf(" %08x", pci_conf_read(pc, tag, i)); 1783 } 1784 1785 if (memh == 0) { 1786 printf("\n"); 1787 return; 1788 } 1789 1790 printf("\nsocket regs:"); 1791 for (i = 0; i <= 0x10; i += 0x04) { 1792 printf(" %08x", bus_space_read_4(memt, memh, i)); 1793 } 1794 printf("\nExCA regs:"); 1795 for (i = 0; i < 0x08; ++i) { 1796 printf(" %02x", bus_space_read_1(memt, memh, 0x800 + i)); 1797 } 1798 printf("\n"); 1799 return; 1800 } 1801 #endif 1802 1803 /* 1804 * cardbustag_t pccbb_make_tag(cardbus_chipset_tag_t cc, 1805 * int busno, int devno, int function) 1806 * This is the function to make a tag to access config space of 1807 * a CardBus Card. It works same as pci_conf_read. 1808 */ 1809 cardbustag_t 1810 pccbb_make_tag(cc, busno, devno, function) 1811 cardbus_chipset_tag_t cc; 1812 int busno, devno, function; 1813 { 1814 struct pccbb_softc *sc = (struct pccbb_softc *)cc; 1815 1816 return pci_make_tag(sc->sc_pc, busno, devno, function); 1817 } 1818 1819 void 1820 pccbb_free_tag(cc, tag) 1821 cardbus_chipset_tag_t cc; 1822 cardbustag_t tag; 1823 { 1824 } 1825 1826 /* 1827 * cardbusreg_t pccbb_conf_read(cardbus_chipset_tag_t cc, 1828 * cardbustag_t tag, int offset) 1829 * This is the function to read the config space of a CardBus Card. 1830 * It works same as pci_conf_read. 1831 */ 1832 cardbusreg_t 1833 pccbb_conf_read(cc, tag, offset) 1834 cardbus_chipset_tag_t cc; 1835 cardbustag_t tag; 1836 int offset; /* register offset */ 1837 { 1838 struct pccbb_softc *sc = (struct pccbb_softc *)cc; 1839 1840 return pci_conf_read(sc->sc_pc, tag, offset); 1841 } 1842 1843 /* 1844 * void pccbb_conf_write(cardbus_chipset_tag_t cc, cardbustag_t tag, 1845 * int offs, cardbusreg_t val) 1846 * This is the function to write the config space of a CardBus Card. 1847 * It works same as pci_conf_write. 1848 */ 1849 void 1850 pccbb_conf_write(cc, tag, reg, val) 1851 cardbus_chipset_tag_t cc; 1852 cardbustag_t tag; 1853 int reg; /* register offset */ 1854 cardbusreg_t val; 1855 { 1856 struct pccbb_softc *sc = (struct pccbb_softc *)cc; 1857 1858 pci_conf_write(sc->sc_pc, tag, reg, val); 1859 } 1860 1861 #if 0 1862 int 1863 pccbb_new_pcmcia_io_alloc(pcmcia_chipset_handle_t pch, 1864 bus_addr_t start, bus_size_t size, bus_size_t align, bus_addr_t mask, 1865 int speed, int flags, 1866 bus_space_handle_t * iohp) 1867 #endif 1868 /* 1869 * int pccbb_pcmcia_io_alloc(pcmcia_chipset_handle_t pch, 1870 * bus_addr_t start, bus_size_t size, 1871 * bus_size_t align, 1872 * struct pcmcia_io_handle *pcihp 1873 * 1874 * This function only allocates I/O region for pccard. This function 1875 * never maps the allocated region to pccard I/O area. 1876 * 1877 * XXX: The interface of this function is not very good, I believe. 1878 */ 1879 int 1880 pccbb_pcmcia_io_alloc(pch, start, size, align, pcihp) 1881 pcmcia_chipset_handle_t pch; 1882 bus_addr_t start; /* start address */ 1883 bus_size_t size; 1884 bus_size_t align; 1885 struct pcmcia_io_handle *pcihp; 1886 { 1887 struct pcic_handle *ph = (struct pcic_handle *)pch; 1888 bus_addr_t ioaddr; 1889 int flags = 0; 1890 bus_space_tag_t iot; 1891 bus_space_handle_t ioh; 1892 #if rbus 1893 rbus_tag_t rb; 1894 #endif 1895 if (align == 0) { 1896 align = size; /* XXX: funny??? */ 1897 } 1898 1899 /* 1900 * Allocate some arbitrary I/O space. 1901 */ 1902 1903 iot = ((struct pccbb_softc *)(ph->ph_parent))->sc_iot; 1904 1905 #if rbus 1906 rb = ((struct pccbb_softc *)(ph->ph_parent))->sc_rbus_iot; 1907 /* XXX: I assume all card decode lower 10 bits by its hardware */ 1908 if (rbus_space_alloc(rb, start, size, 0x3ff, align, 0, &ioaddr, &ioh)) { 1909 return 1; 1910 } 1911 #else 1912 if (start) { 1913 ioaddr = start; 1914 if (bus_space_map(iot, start, size, 0, &ioh)) { 1915 return 1; 1916 } 1917 DPRINTF(("pccbb_pcmcia_io_alloc map port %lx+%lx\n", 1918 (u_long) ioaddr, (u_long) size)); 1919 } else { 1920 flags |= PCMCIA_IO_ALLOCATED; 1921 if (bus_space_alloc(iot, 0x700 /* ph->sc->sc_iobase */ , 1922 0x800, /* ph->sc->sc_iobase + ph->sc->sc_iosize */ 1923 size, align, 0, 0, &ioaddr, &ioh)) { 1924 /* No room be able to be get. */ 1925 return 1; 1926 } 1927 DPRINTF(("pccbb_pcmmcia_io_alloc alloc port 0x%lx+0x%lx\n", 1928 (u_long) ioaddr, (u_long) size)); 1929 } 1930 #endif 1931 1932 pcihp->iot = iot; 1933 pcihp->ioh = ioh; 1934 pcihp->addr = ioaddr; 1935 pcihp->size = size; 1936 pcihp->flags = flags; 1937 1938 return 0; 1939 } 1940 1941 /* 1942 * int pccbb_pcmcia_io_free(pcmcia_chipset_handle_t pch, 1943 * struct pcmcia_io_handle *pcihp) 1944 * 1945 * This function only frees I/O region for pccard. 1946 * 1947 * XXX: The interface of this function is not very good, I believe. 1948 */ 1949 void 1950 pccbb_pcmcia_io_free(pch, pcihp) 1951 pcmcia_chipset_handle_t pch; 1952 struct pcmcia_io_handle *pcihp; 1953 { 1954 #if !rbus 1955 bus_space_tag_t iot = pcihp->iot; 1956 #endif 1957 bus_space_handle_t ioh = pcihp->ioh; 1958 bus_size_t size = pcihp->size; 1959 1960 #if rbus 1961 struct pccbb_softc *sc = 1962 (struct pccbb_softc *)((struct pcic_handle *)pch)->ph_parent; 1963 rbus_tag_t rb = sc->sc_rbus_iot; 1964 1965 rbus_space_free(rb, ioh, size, NULL); 1966 #else 1967 if (pcihp->flags & PCMCIA_IO_ALLOCATED) 1968 bus_space_free(iot, ioh, size); 1969 else 1970 bus_space_unmap(iot, ioh, size); 1971 #endif 1972 } 1973 1974 /* 1975 * int pccbb_pcmcia_io_map(pcmcia_chipset_handle_t pch, int width, 1976 * bus_addr_t offset, bus_size_t size, 1977 * struct pcmcia_io_handle *pcihp, 1978 * int *windowp) 1979 * 1980 * This function maps the allocated I/O region to pccard. This function 1981 * never allocates any I/O region for pccard I/O area. I don't 1982 * understand why the original authors of pcmciabus separated alloc and 1983 * map. I believe the two must be unite. 1984 * 1985 * XXX: no wait timing control? 1986 */ 1987 int 1988 pccbb_pcmcia_io_map(pch, width, offset, size, pcihp, windowp) 1989 pcmcia_chipset_handle_t pch; 1990 int width; 1991 bus_addr_t offset; 1992 bus_size_t size; 1993 struct pcmcia_io_handle *pcihp; 1994 int *windowp; 1995 { 1996 struct pcic_handle *ph = (struct pcic_handle *)pch; 1997 bus_addr_t ioaddr = pcihp->addr + offset; 1998 int i, win; 1999 #if defined CBB_DEBUG 2000 static char *width_names[] = { "dynamic", "io8", "io16" }; 2001 #endif 2002 2003 /* Sanity check I/O handle. */ 2004 2005 if (((struct pccbb_softc *)ph->ph_parent)->sc_iot != pcihp->iot) { 2006 panic("pccbb_pcmcia_io_map iot is bogus"); 2007 } 2008 2009 /* XXX Sanity check offset/size. */ 2010 2011 win = -1; 2012 for (i = 0; i < PCIC_IO_WINS; i++) { 2013 if ((ph->ioalloc & (1 << i)) == 0) { 2014 win = i; 2015 ph->ioalloc |= (1 << i); 2016 break; 2017 } 2018 } 2019 2020 if (win == -1) { 2021 return 1; 2022 } 2023 2024 *windowp = win; 2025 2026 /* XXX this is pretty gross */ 2027 2028 DPRINTF(("pccbb_pcmcia_io_map window %d %s port %lx+%lx\n", 2029 win, width_names[width], (u_long) ioaddr, (u_long) size)); 2030 2031 /* XXX wtf is this doing here? */ 2032 2033 #if 0 2034 printf(" port 0x%lx", (u_long) ioaddr); 2035 if (size > 1) { 2036 printf("-0x%lx", (u_long) ioaddr + (u_long) size - 1); 2037 } 2038 #endif 2039 2040 ph->io[win].addr = ioaddr; 2041 ph->io[win].size = size; 2042 ph->io[win].width = width; 2043 2044 /* actual dirty register-value changing in the function below. */ 2045 pccbb_pcmcia_do_io_map(ph, win); 2046 2047 return 0; 2048 } 2049 2050 /* 2051 * void pccbb_pcmcia_do_io_map(struct pcic_handle *h, int win) 2052 * 2053 * This function changes register-value to map I/O region for pccard. 2054 */ 2055 void 2056 pccbb_pcmcia_do_io_map(ph, win) 2057 struct pcic_handle *ph; 2058 int win; 2059 { 2060 static u_int8_t pcic_iowidth[3] = { 2061 PCIC_IOCTL_IO0_IOCS16SRC_CARD, 2062 PCIC_IOCTL_IO0_IOCS16SRC_DATASIZE | 2063 PCIC_IOCTL_IO0_DATASIZE_8BIT, 2064 PCIC_IOCTL_IO0_IOCS16SRC_DATASIZE | 2065 PCIC_IOCTL_IO0_DATASIZE_16BIT, 2066 }; 2067 2068 #define PCIC_SIA_START_LOW 0 2069 #define PCIC_SIA_START_HIGH 1 2070 #define PCIC_SIA_STOP_LOW 2 2071 #define PCIC_SIA_STOP_HIGH 3 2072 2073 int regbase_win = 0x8 + win * 0x04; 2074 u_int8_t ioctl, enable; 2075 2076 DPRINTF( 2077 ("pccbb_pcmcia_do_io_map win %d addr 0x%lx size 0x%lx width %d\n", 2078 win, (long)ph->io[win].addr, (long)ph->io[win].size, 2079 ph->io[win].width * 8)); 2080 2081 Pcic_write(ph, regbase_win + PCIC_SIA_START_LOW, 2082 ph->io[win].addr & 0xff); 2083 Pcic_write(ph, regbase_win + PCIC_SIA_START_HIGH, 2084 (ph->io[win].addr >> 8) & 0xff); 2085 2086 Pcic_write(ph, regbase_win + PCIC_SIA_STOP_LOW, 2087 (ph->io[win].addr + ph->io[win].size - 1) & 0xff); 2088 Pcic_write(ph, regbase_win + PCIC_SIA_STOP_HIGH, 2089 ((ph->io[win].addr + ph->io[win].size - 1) >> 8) & 0xff); 2090 2091 ioctl = Pcic_read(ph, PCIC_IOCTL); 2092 enable = Pcic_read(ph, PCIC_ADDRWIN_ENABLE); 2093 switch (win) { 2094 case 0: 2095 ioctl &= ~(PCIC_IOCTL_IO0_WAITSTATE | PCIC_IOCTL_IO0_ZEROWAIT | 2096 PCIC_IOCTL_IO0_IOCS16SRC_MASK | 2097 PCIC_IOCTL_IO0_DATASIZE_MASK); 2098 ioctl |= pcic_iowidth[ph->io[win].width]; 2099 enable |= PCIC_ADDRWIN_ENABLE_IO0; 2100 break; 2101 case 1: 2102 ioctl &= ~(PCIC_IOCTL_IO1_WAITSTATE | PCIC_IOCTL_IO1_ZEROWAIT | 2103 PCIC_IOCTL_IO1_IOCS16SRC_MASK | 2104 PCIC_IOCTL_IO1_DATASIZE_MASK); 2105 ioctl |= (pcic_iowidth[ph->io[win].width] << 4); 2106 enable |= PCIC_ADDRWIN_ENABLE_IO1; 2107 break; 2108 } 2109 Pcic_write(ph, PCIC_IOCTL, ioctl); 2110 Pcic_write(ph, PCIC_ADDRWIN_ENABLE, enable); 2111 #if defined CBB_DEBUG 2112 { 2113 u_int8_t start_low = 2114 Pcic_read(ph, regbase_win + PCIC_SIA_START_LOW); 2115 u_int8_t start_high = 2116 Pcic_read(ph, regbase_win + PCIC_SIA_START_HIGH); 2117 u_int8_t stop_low = 2118 Pcic_read(ph, regbase_win + PCIC_SIA_STOP_LOW); 2119 u_int8_t stop_high = 2120 Pcic_read(ph, regbase_win + PCIC_SIA_STOP_HIGH); 2121 printf 2122 (" start %02x %02x, stop %02x %02x, ioctl %02x enable %02x\n", 2123 start_low, start_high, stop_low, stop_high, ioctl, enable); 2124 } 2125 #endif 2126 } 2127 2128 /* 2129 * void pccbb_pcmcia_io_unmap(pcmcia_chipset_handle_t *h, int win) 2130 * 2131 * This function unmaps I/O region. No return value. 2132 */ 2133 void 2134 pccbb_pcmcia_io_unmap(pch, win) 2135 pcmcia_chipset_handle_t pch; 2136 int win; 2137 { 2138 struct pcic_handle *ph = (struct pcic_handle *)pch; 2139 int reg; 2140 2141 if (win >= PCIC_IO_WINS || win < 0) { 2142 panic("pccbb_pcmcia_io_unmap: window out of range"); 2143 } 2144 2145 reg = Pcic_read(ph, PCIC_ADDRWIN_ENABLE); 2146 switch (win) { 2147 case 0: 2148 reg &= ~PCIC_ADDRWIN_ENABLE_IO0; 2149 break; 2150 case 1: 2151 reg &= ~PCIC_ADDRWIN_ENABLE_IO1; 2152 break; 2153 } 2154 Pcic_write(ph, PCIC_ADDRWIN_ENABLE, reg); 2155 2156 ph->ioalloc &= ~(1 << win); 2157 } 2158 2159 /* 2160 * void pccbb_pcmcia_wait_ready(struct pcic_handle *ph) 2161 * 2162 * This function enables the card. All information is stored in 2163 * the first argument, pcmcia_chipset_handle_t. 2164 */ 2165 void 2166 pccbb_pcmcia_wait_ready(ph) 2167 struct pcic_handle *ph; 2168 { 2169 int i; 2170 2171 DPRINTF(("pccbb_pcmcia_wait_ready: status 0x%02x\n", 2172 Pcic_read(ph, PCIC_IF_STATUS))); 2173 2174 for (i = 0; i < 10000; i++) { 2175 if (Pcic_read(ph, PCIC_IF_STATUS) & PCIC_IF_STATUS_READY) { 2176 return; 2177 } 2178 delay(500); 2179 #ifdef CBB_DEBUG 2180 if ((i > 5000) && (i % 100 == 99)) 2181 printf("."); 2182 #endif 2183 } 2184 2185 #ifdef DIAGNOSTIC 2186 printf("pcic_wait_ready: ready never happened, status = %02x\n", 2187 Pcic_read(ph, PCIC_IF_STATUS)); 2188 #endif 2189 } 2190 2191 /* 2192 * void pccbb_pcmcia_socket_enable(pcmcia_chipset_handle_t pch) 2193 * 2194 * This function enables the card. All information is stored in 2195 * the first argument, pcmcia_chipset_handle_t. 2196 */ 2197 void 2198 pccbb_pcmcia_socket_enable(pch) 2199 pcmcia_chipset_handle_t pch; 2200 { 2201 struct pcic_handle *ph = (struct pcic_handle *)pch; 2202 struct pccbb_softc *sc = (struct pccbb_softc *)ph->ph_parent; 2203 int cardtype, win; 2204 u_int8_t power, intr; 2205 pcireg_t spsr; 2206 int voltage; 2207 2208 /* this bit is mostly stolen from pcic_attach_card */ 2209 2210 DPRINTF(("pccbb_pcmcia_socket_enable: ")); 2211 2212 /* get card Vcc info */ 2213 2214 spsr = 2215 bus_space_read_4(sc->sc_base_memt, sc->sc_base_memh, 2216 CB_SOCKET_STAT); 2217 if (spsr & CB_SOCKET_STAT_5VCARD) { 2218 DPRINTF(("5V card\n")); 2219 voltage = CARDBUS_VCC_5V | CARDBUS_VPP_VCC; 2220 } else if (spsr & CB_SOCKET_STAT_3VCARD) { 2221 DPRINTF(("3V card\n")); 2222 voltage = CARDBUS_VCC_3V | CARDBUS_VPP_VCC; 2223 } else { 2224 printf("?V card, 0x%x\n", spsr); /* XXX */ 2225 return; 2226 } 2227 2228 /* disable socket i/o: negate output enable bit */ 2229 2230 power = 0; 2231 Pcic_write(ph, PCIC_PWRCTL, power); 2232 2233 /* power down the socket to reset it, clear the card reset pin */ 2234 2235 pccbb_power(sc, CARDBUS_VCC_0V | CARDBUS_VPP_0V); 2236 2237 /* 2238 * wait 200ms until power fails (Tpf). Then, wait 100ms since 2239 * we are changing Vcc (Toff). 2240 */ 2241 /* delay(300*1000); too much */ 2242 2243 /* assert reset bit */ 2244 intr = Pcic_read(ph, PCIC_INTR); 2245 intr &= ~(PCIC_INTR_RESET | PCIC_INTR_CARDTYPE_MASK); 2246 Pcic_write(ph, PCIC_INTR, intr); 2247 2248 /* power up the socket and output enable */ 2249 power = Pcic_read(ph, PCIC_PWRCTL); 2250 power |= PCIC_PWRCTL_OE; 2251 Pcic_write(ph, PCIC_PWRCTL, power); 2252 pccbb_power(sc, voltage); 2253 2254 /* 2255 * hold RESET at least 10us. 2256 */ 2257 delay(10); 2258 delay(2 * 1000); /* XXX: TI1130 requires it. */ 2259 delay(20 * 1000); /* XXX: TI1130 requires it. */ 2260 2261 /* clear the reset flag */ 2262 2263 intr |= PCIC_INTR_RESET; 2264 Pcic_write(ph, PCIC_INTR, intr); 2265 2266 /* wait 20ms as per pc card standard (r2.01) section 4.3.6 */ 2267 2268 delay(20000); 2269 2270 /* wait for the chip to finish initializing */ 2271 2272 pccbb_pcmcia_wait_ready(ph); 2273 2274 /* zero out the address windows */ 2275 2276 Pcic_write(ph, PCIC_ADDRWIN_ENABLE, 0); 2277 2278 /* set the card type */ 2279 2280 cardtype = pcmcia_card_gettype(ph->pcmcia); 2281 2282 intr |= ((cardtype == PCMCIA_IFTYPE_IO) ? 2283 PCIC_INTR_CARDTYPE_IO : PCIC_INTR_CARDTYPE_MEM); 2284 Pcic_write(ph, PCIC_INTR, intr); 2285 2286 DPRINTF(("%s: pccbb_pcmcia_socket_enable %02x cardtype %s %02x\n", 2287 ph->ph_parent->dv_xname, ph->sock, 2288 ((cardtype == PCMCIA_IFTYPE_IO) ? "io" : "mem"), intr)); 2289 2290 /* reinstall all the memory and io mappings */ 2291 2292 for (win = 0; win < PCIC_MEM_WINS; ++win) { 2293 if (ph->memalloc & (1 << win)) { 2294 pccbb_pcmcia_do_mem_map(ph, win); 2295 } 2296 } 2297 2298 for (win = 0; win < PCIC_IO_WINS; ++win) { 2299 if (ph->ioalloc & (1 << win)) { 2300 pccbb_pcmcia_do_io_map(ph, win); 2301 } 2302 } 2303 } 2304 2305 /* 2306 * void pccbb_pcmcia_socket_disable(pcmcia_chipset_handle_t *ph) 2307 * 2308 * This function disables the card. All information is stored in 2309 * the first argument, pcmcia_chipset_handle_t. 2310 */ 2311 void 2312 pccbb_pcmcia_socket_disable(pch) 2313 pcmcia_chipset_handle_t pch; 2314 { 2315 struct pcic_handle *ph = (struct pcic_handle *)pch; 2316 struct pccbb_softc *sc = (struct pccbb_softc *)ph->ph_parent; 2317 u_int8_t power, intr; 2318 2319 DPRINTF(("pccbb_pcmcia_socket_disable\n")); 2320 2321 /* reset signal asserting... */ 2322 2323 intr = Pcic_read(ph, PCIC_INTR); 2324 intr &= ~(PCIC_INTR_CARDTYPE_MASK); 2325 Pcic_write(ph, PCIC_INTR, intr); 2326 delay(2 * 1000); 2327 2328 /* power down the socket */ 2329 power = Pcic_read(ph, PCIC_PWRCTL); 2330 power &= ~PCIC_PWRCTL_OE; 2331 Pcic_write(ph, PCIC_PWRCTL, power); 2332 pccbb_power(sc, CARDBUS_VCC_0V | CARDBUS_VPP_0V); 2333 /* 2334 * wait 300ms until power fails (Tpf). 2335 */ 2336 delay(300 * 1000); 2337 } 2338 2339 /* 2340 * int pccbb_pcmcia_card_detect(pcmcia_chipset_handle_t *ph) 2341 * 2342 * This function detects whether a card is in the slot or not. 2343 * If a card is inserted, return 1. Otherwise, return 0. 2344 */ 2345 int 2346 pccbb_pcmcia_card_detect(pch) 2347 pcmcia_chipset_handle_t pch; 2348 { 2349 struct pcic_handle *ph = (struct pcic_handle *)pch; 2350 struct pccbb_softc *sc = (struct pccbb_softc *)ph->ph_parent; 2351 2352 DPRINTF(("pccbb_pcmcia_card_detect\n")); 2353 return pccbb_detect_card(sc) == 1 ? 1 : 0; 2354 } 2355 2356 #if 0 2357 int 2358 pccbb_new_pcmcia_mem_alloc(pcmcia_chipset_handle_t pch, 2359 bus_addr_t start, bus_size_t size, bus_size_t align, int speed, int flags, 2360 bus_space_tag_t * memtp bus_space_handle_t * memhp) 2361 #endif 2362 /* 2363 * int pccbb_pcmcia_mem_alloc(pcmcia_chipset_handle_t pch, 2364 * bus_size_t size, 2365 * struct pcmcia_mem_handle *pcmhp) 2366 * 2367 * This function only allocates memory region for pccard. This 2368 * function never maps the allocated region to pccard memory area. 2369 * 2370 * XXX: Why the argument of start address is not in? 2371 */ 2372 int 2373 pccbb_pcmcia_mem_alloc(pch, size, pcmhp) 2374 pcmcia_chipset_handle_t pch; 2375 bus_size_t size; 2376 struct pcmcia_mem_handle *pcmhp; 2377 { 2378 struct pcic_handle *ph = (struct pcic_handle *)pch; 2379 bus_space_handle_t memh; 2380 bus_addr_t addr; 2381 bus_size_t sizepg; 2382 struct pccbb_softc *sc = (struct pccbb_softc *)ph->ph_parent; 2383 #if rbus 2384 rbus_tag_t rb; 2385 #endif 2386 2387 /* out of sc->memh, allocate as many pages as necessary */ 2388 2389 /* convert size to PCIC pages */ 2390 /* 2391 * This is not enough; when the requested region is on the page 2392 * boundaries, this may calculate wrong result. 2393 */ 2394 sizepg = (size + (PCIC_MEM_PAGESIZE - 1)) / PCIC_MEM_PAGESIZE; 2395 #if 0 2396 if (sizepg > PCIC_MAX_MEM_PAGES) { 2397 return 1; 2398 } 2399 #endif 2400 2401 if (!(sc->sc_pcmcia_flags & PCCBB_PCMCIA_MEM_32)) { 2402 return 1; 2403 } 2404 2405 addr = 0; /* XXX gcc -Wuninitialized */ 2406 2407 #if rbus 2408 rb = sc->sc_rbus_memt; 2409 if (rbus_space_alloc(rb, 0, sizepg * PCIC_MEM_PAGESIZE, 2410 sizepg * PCIC_MEM_PAGESIZE - 1, PCIC_MEM_PAGESIZE, 0, 2411 &addr, &memh)) { 2412 return 1; 2413 } 2414 #else 2415 if (bus_space_alloc(sc->sc_memt, sc->sc_mem_start, sc->sc_mem_end, 2416 sizepg * PCIC_MEM_PAGESIZE, PCIC_MEM_PAGESIZE, 2417 0, /* boundary */ 2418 0, /* flags */ 2419 &addr, &memh)) { 2420 return 1; 2421 } 2422 #endif 2423 2424 DPRINTF( 2425 ("pccbb_pcmcia_alloc_mem: addr 0x%lx size 0x%lx, realsize 0x%lx\n", 2426 addr, size, sizepg * PCIC_MEM_PAGESIZE)); 2427 2428 pcmhp->memt = sc->sc_memt; 2429 pcmhp->memh = memh; 2430 pcmhp->addr = addr; 2431 pcmhp->size = size; 2432 pcmhp->realsize = sizepg * PCIC_MEM_PAGESIZE; 2433 /* What is mhandle? I feel it is very dirty and it must go trush. */ 2434 pcmhp->mhandle = 0; 2435 /* No offset??? Funny. */ 2436 2437 return 0; 2438 } 2439 2440 /* 2441 * void pccbb_pcmcia_mem_free(pcmcia_chipset_handle_t pch, 2442 * struct pcmcia_mem_handle *pcmhp) 2443 * 2444 * This function release the memory space allocated by the function 2445 * pccbb_pcmcia_mem_alloc(). 2446 */ 2447 void 2448 pccbb_pcmcia_mem_free(pch, pcmhp) 2449 pcmcia_chipset_handle_t pch; 2450 struct pcmcia_mem_handle *pcmhp; 2451 { 2452 #if rbus 2453 struct pcic_handle *ph = (struct pcic_handle *)pch; 2454 struct pccbb_softc *sc = (struct pccbb_softc *)ph->ph_parent; 2455 2456 rbus_space_free(sc->sc_rbus_memt, pcmhp->memh, pcmhp->realsize, NULL); 2457 #else 2458 bus_space_free(pcmhp->memt, pcmhp->memh, pcmhp->realsize); 2459 #endif 2460 } 2461 2462 /* 2463 * void pccbb_pcmcia_do_mem_map(struct pcic_handle *ph, int win) 2464 * 2465 * This function release the memory space allocated by the function 2466 * pccbb_pcmcia_mem_alloc(). 2467 */ 2468 void 2469 pccbb_pcmcia_do_mem_map(ph, win) 2470 struct pcic_handle *ph; 2471 int win; 2472 { 2473 int regbase_win; 2474 bus_addr_t phys_addr; 2475 bus_addr_t phys_end; 2476 2477 #define PCIC_SMM_START_LOW 0 2478 #define PCIC_SMM_START_HIGH 1 2479 #define PCIC_SMM_STOP_LOW 2 2480 #define PCIC_SMM_STOP_HIGH 3 2481 #define PCIC_CMA_LOW 4 2482 #define PCIC_CMA_HIGH 5 2483 2484 u_int8_t start_low, start_high = 0; 2485 u_int8_t stop_low, stop_high; 2486 u_int8_t off_low, off_high; 2487 u_int8_t mem_window; 2488 int reg; 2489 2490 regbase_win = 0x10 + win * 0x08; 2491 2492 phys_addr = ph->mem[win].addr; 2493 phys_end = phys_addr + ph->mem[win].size; 2494 2495 DPRINTF(("pccbb_pcmcia_do_mem_map: start 0x%lx end 0x%lx off 0x%lx\n", 2496 phys_addr, phys_end, ph->mem[win].offset)); 2497 2498 #define PCIC_MEMREG_LSB_SHIFT PCIC_SYSMEM_ADDRX_SHIFT 2499 #define PCIC_MEMREG_MSB_SHIFT (PCIC_SYSMEM_ADDRX_SHIFT + 8) 2500 #define PCIC_MEMREG_WIN_SHIFT (PCIC_SYSMEM_ADDRX_SHIFT + 12) 2501 2502 /* bit 19:12 */ 2503 start_low = (phys_addr >> PCIC_MEMREG_LSB_SHIFT) & 0xff; 2504 /* bit 23:20 and bit 7 on */ 2505 start_high = ((phys_addr >> PCIC_MEMREG_MSB_SHIFT) & 0x0f) 2506 | PCIC_SYSMEM_ADDRX_START_MSB_DATASIZE_16BIT; /* bit 7 on */ 2507 /* bit 31:24, for 32-bit address */ 2508 mem_window = (phys_addr >> PCIC_MEMREG_WIN_SHIFT) & 0xff; 2509 2510 Pcic_write(ph, regbase_win + PCIC_SMM_START_LOW, start_low); 2511 Pcic_write(ph, regbase_win + PCIC_SMM_START_HIGH, start_high); 2512 2513 if (((struct pccbb_softc *)ph-> 2514 ph_parent)->sc_pcmcia_flags & PCCBB_PCMCIA_MEM_32) { 2515 Pcic_write(ph, 0x40 + win, mem_window); 2516 } 2517 2518 stop_low = (phys_end >> PCIC_MEMREG_LSB_SHIFT) & 0xff; 2519 stop_high = ((phys_end >> PCIC_MEMREG_MSB_SHIFT) & 0x0f) 2520 | PCIC_SYSMEM_ADDRX_STOP_MSB_WAIT2; /* wait 2 cycles */ 2521 /* XXX Geee, WAIT2!! Crazy!! I must rewrite this routine. */ 2522 2523 Pcic_write(ph, regbase_win + PCIC_SMM_STOP_LOW, stop_low); 2524 Pcic_write(ph, regbase_win + PCIC_SMM_STOP_HIGH, stop_high); 2525 2526 off_low = (ph->mem[win].offset >> PCIC_CARDMEM_ADDRX_SHIFT) & 0xff; 2527 off_high = ((ph->mem[win].offset >> (PCIC_CARDMEM_ADDRX_SHIFT + 8)) 2528 & PCIC_CARDMEM_ADDRX_MSB_ADDR_MASK) 2529 | ((ph->mem[win].kind == PCMCIA_MEM_ATTR) ? 2530 PCIC_CARDMEM_ADDRX_MSB_REGACTIVE_ATTR : 0); 2531 2532 Pcic_write(ph, regbase_win + PCIC_CMA_LOW, off_low); 2533 Pcic_write(ph, regbase_win + PCIC_CMA_HIGH, off_high); 2534 2535 reg = Pcic_read(ph, PCIC_ADDRWIN_ENABLE); 2536 reg |= ((1 << win) | PCIC_ADDRWIN_ENABLE_MEMCS16); 2537 Pcic_write(ph, PCIC_ADDRWIN_ENABLE, reg); 2538 2539 #if defined CBB_DEBUG 2540 { 2541 int r1, r2, r3, r4, r5, r6, r7 = 0; 2542 2543 r1 = Pcic_read(ph, regbase_win + PCIC_SMM_START_LOW); 2544 r2 = Pcic_read(ph, regbase_win + PCIC_SMM_START_HIGH); 2545 r3 = Pcic_read(ph, regbase_win + PCIC_SMM_STOP_LOW); 2546 r4 = Pcic_read(ph, regbase_win + PCIC_SMM_STOP_HIGH); 2547 r5 = Pcic_read(ph, regbase_win + PCIC_CMA_LOW); 2548 r6 = Pcic_read(ph, regbase_win + PCIC_CMA_HIGH); 2549 if (((struct pccbb_softc *)(ph-> 2550 ph_parent))->sc_pcmcia_flags & PCCBB_PCMCIA_MEM_32) { 2551 r7 = Pcic_read(ph, 0x40 + win); 2552 } 2553 2554 DPRINTF(("pccbb_pcmcia_do_mem_map window %d: %02x%02x %02x%02x " 2555 "%02x%02x", win, r1, r2, r3, r4, r5, r6)); 2556 if (((struct pccbb_softc *)(ph-> 2557 ph_parent))->sc_pcmcia_flags & PCCBB_PCMCIA_MEM_32) { 2558 DPRINTF((" %02x", r7)); 2559 } 2560 DPRINTF(("\n")); 2561 } 2562 #endif 2563 } 2564 2565 /* 2566 * int pccbb_pcmcia_mem_map(pcmcia_chipset_handle_t pch, int kind, 2567 * bus_addr_t card_addr, bus_size_t size, 2568 * struct pcmcia_mem_handle *pcmhp, 2569 * bus_addr_t *offsetp, int *windowp) 2570 * 2571 * This function maps memory space allocated by the function 2572 * pccbb_pcmcia_mem_alloc(). 2573 */ 2574 int 2575 pccbb_pcmcia_mem_map(pch, kind, card_addr, size, pcmhp, offsetp, windowp) 2576 pcmcia_chipset_handle_t pch; 2577 int kind; 2578 bus_addr_t card_addr; 2579 bus_size_t size; 2580 struct pcmcia_mem_handle *pcmhp; 2581 bus_addr_t *offsetp; 2582 int *windowp; 2583 { 2584 struct pcic_handle *ph = (struct pcic_handle *)pch; 2585 bus_addr_t busaddr; 2586 long card_offset; 2587 int win; 2588 2589 for (win = 0; win < PCIC_MEM_WINS; ++win) { 2590 if ((ph->memalloc & (1 << win)) == 0) { 2591 ph->memalloc |= (1 << win); 2592 break; 2593 } 2594 } 2595 2596 if (win == PCIC_MEM_WINS) { 2597 return 1; 2598 } 2599 2600 *windowp = win; 2601 2602 /* XXX this is pretty gross */ 2603 2604 if (((struct pccbb_softc *)ph->ph_parent)->sc_memt != pcmhp->memt) { 2605 panic("pccbb_pcmcia_mem_map memt is bogus"); 2606 } 2607 2608 busaddr = pcmhp->addr; 2609 2610 /* 2611 * compute the address offset to the pcmcia address space for the 2612 * pcic. this is intentionally signed. The masks and shifts below 2613 * will cause TRT to happen in the pcic registers. Deal with making 2614 * sure the address is aligned, and return the alignment offset. 2615 */ 2616 2617 *offsetp = card_addr % PCIC_MEM_PAGESIZE; 2618 card_addr -= *offsetp; 2619 2620 DPRINTF(("pccbb_pcmcia_mem_map window %d bus %lx+%lx+%lx at card addr " 2621 "%lx\n", win, (u_long) busaddr, (u_long) * offsetp, (u_long) size, 2622 (u_long) card_addr)); 2623 2624 /* 2625 * include the offset in the size, and decrement size by one, since 2626 * the hw wants start/stop 2627 */ 2628 size += *offsetp - 1; 2629 2630 card_offset = (((long)card_addr) - ((long)busaddr)); 2631 2632 ph->mem[win].addr = busaddr; 2633 ph->mem[win].size = size; 2634 ph->mem[win].offset = card_offset; 2635 ph->mem[win].kind = kind; 2636 2637 pccbb_pcmcia_do_mem_map(ph, win); 2638 2639 return 0; 2640 } 2641 2642 /* 2643 * int pccbb_pcmcia_mem_unmap(pcmcia_chipset_handle_t pch, 2644 * int window) 2645 * 2646 * This function unmaps memory space which mapped by the function 2647 * pccbb_pcmcia_mem_map(). 2648 */ 2649 void 2650 pccbb_pcmcia_mem_unmap(pch, window) 2651 pcmcia_chipset_handle_t pch; 2652 int window; 2653 { 2654 struct pcic_handle *ph = (struct pcic_handle *)pch; 2655 int reg; 2656 2657 if (window >= PCIC_MEM_WINS) { 2658 panic("pccbb_pcmcia_mem_unmap: window out of range"); 2659 } 2660 2661 reg = Pcic_read(ph, PCIC_ADDRWIN_ENABLE); 2662 reg &= ~(1 << window); 2663 Pcic_write(ph, PCIC_ADDRWIN_ENABLE, reg); 2664 2665 ph->memalloc &= ~(1 << window); 2666 } 2667 2668 #if defined PCCBB_PCMCIA_POLL 2669 struct pccbb_poll_str { 2670 void *arg; 2671 int (*func) __P((void *)); 2672 int level; 2673 struct pcic_handle *ph; 2674 int count; 2675 int num; 2676 }; 2677 2678 static struct pccbb_poll_str pccbb_poll[10]; 2679 static int pccbb_poll_n = 0; 2680 2681 void pccbb_pcmcia_poll __P((void *arg)); 2682 2683 void 2684 pccbb_pcmcia_poll(arg) 2685 void *arg; 2686 { 2687 struct pccbb_poll_str *poll = arg; 2688 struct pcic_handle *ph = poll->ph; 2689 struct pccbb_softc *sc = ph->sc; 2690 int s; 2691 u_int32_t spsr; /* socket present-state reg */ 2692 2693 timeout(pccbb_pcmcia_poll, arg, hz * 2); 2694 switch (poll->level) { 2695 case IPL_NET: 2696 s = splnet(); 2697 break; 2698 case IPL_BIO: 2699 s = splbio(); 2700 break; 2701 case IPL_TTY: /* fallthrough */ 2702 default: 2703 s = spltty(); 2704 break; 2705 } 2706 2707 spsr = 2708 bus_space_read_4(sc->sc_base_memt, sc->sc_base_memh, 2709 CB_SOCKET_STAT); 2710 2711 #if defined PCCBB_PCMCIA_POLL_ONLY && defined LEVEL2 2712 if (!(spsr & 0x40)) /* CINT low */ 2713 #else 2714 if (1) 2715 #endif 2716 { 2717 if ((*poll->func) (poll->arg) > 0) { 2718 ++poll->count; 2719 // printf("intr: reported from poller, 0x%x\n", spsr); 2720 #if defined LEVEL2 2721 } else { 2722 printf("intr: miss! 0x%x\n", spsr); 2723 #endif 2724 } 2725 } 2726 splx(s); 2727 } 2728 #endif /* defined CB_PCMCIA_POLL */ 2729 2730 /* 2731 * void *pccbb_pcmcia_intr_establish(pcmcia_chipset_handle_t pch, 2732 * struct pcmcia_function *pf, 2733 * int ipl, 2734 * int (*func)(void *), 2735 * void *arg); 2736 * 2737 * This function enables PC-Card interrupt. PCCBB uses PCI interrupt line. 2738 */ 2739 void * 2740 pccbb_pcmcia_intr_establish(pch, pf, ipl, func, arg) 2741 pcmcia_chipset_handle_t pch; 2742 struct pcmcia_function *pf; 2743 int ipl; 2744 int (*func) __P((void *)); 2745 void *arg; 2746 { 2747 struct pcic_handle *ph = (struct pcic_handle *)pch; 2748 struct pccbb_softc *sc = (struct pccbb_softc *)ph->ph_parent; 2749 2750 if (!(pf->cfe->flags & PCMCIA_CFE_IRQLEVEL)) { 2751 /* what should I do? */ 2752 if ((pf->cfe->flags & PCMCIA_CFE_IRQLEVEL)) { 2753 DPRINTF( 2754 ("%s does not provide edge nor pulse interrupt\n", 2755 sc->sc_dev.dv_xname)); 2756 return NULL; 2757 } 2758 /* 2759 * XXX Noooooo! The interrupt flag must set properly!! 2760 * dumb pcmcia driver!! 2761 */ 2762 } 2763 2764 return pccbb_intr_establish(sc, IST_LEVEL, ipl, func, arg); 2765 } 2766 2767 /* 2768 * void pccbb_pcmcia_intr_disestablish(pcmcia_chipset_handle_t pch, 2769 * void *ih) 2770 * 2771 * This function disables PC-Card interrupt. 2772 */ 2773 void 2774 pccbb_pcmcia_intr_disestablish(pch, ih) 2775 pcmcia_chipset_handle_t pch; 2776 void *ih; 2777 { 2778 struct pcic_handle *ph = (struct pcic_handle *)pch; 2779 struct pccbb_softc *sc = (struct pccbb_softc *)ph->ph_parent; 2780 2781 pccbb_intr_disestablish(sc, ih); 2782 } 2783 2784 #if rbus 2785 /* 2786 * int 2787 * pccbb_rbus_cb_space_alloc(cardbus_chipset_tag_t ct, rbus_tag_t rb, 2788 * bus_addr_t addr, bus_size_t size, 2789 * bus_addr_t mask, bus_size_t align, 2790 * int flags, bus_addr_t *addrp; 2791 * bus_space_handle_t *bshp) 2792 * 2793 * This function allocates a portion of memory or io space for 2794 * clients. This function is called from CardBus card drivers. 2795 */ 2796 int 2797 pccbb_rbus_cb_space_alloc(ct, rb, addr, size, mask, align, flags, addrp, bshp) 2798 cardbus_chipset_tag_t ct; 2799 rbus_tag_t rb; 2800 bus_addr_t addr; 2801 bus_size_t size; 2802 bus_addr_t mask; 2803 bus_size_t align; 2804 int flags; 2805 bus_addr_t *addrp; 2806 bus_space_handle_t *bshp; 2807 { 2808 struct pccbb_softc *sc = (struct pccbb_softc *)ct; 2809 2810 DPRINTF( 2811 ("pccbb_rbus_cb_space_alloc: adr %lx, size %lx, mask %lx, align %lx\n", 2812 addr, size, mask, align)); 2813 2814 if (align == 0) { 2815 align = size; 2816 } 2817 2818 if (rb->rb_bt == sc->sc_memt) { 2819 if (align < 16) { 2820 return 1; 2821 } 2822 } else if (rb->rb_bt == sc->sc_iot) { 2823 if (align < 4) { 2824 return 1; 2825 } 2826 /* XXX: hack for avoiding ISA image */ 2827 if (mask < 0x0100) { 2828 mask = 0x3ff; 2829 addr = 0x300; 2830 } 2831 2832 } else { 2833 DPRINTF( 2834 ("pccbb_rbus_cb_space_alloc: Bus space tag %x is NOT used.\n", 2835 rb->rb_bt)); 2836 return 1; 2837 /* XXX: panic here? */ 2838 } 2839 2840 if (rbus_space_alloc(rb, addr, size, mask, align, flags, addrp, bshp)) { 2841 printf("%s: <rbus> no bus space\n", sc->sc_dev.dv_xname); 2842 return 1; 2843 } 2844 2845 pccbb_open_win(sc, rb->rb_bt, *addrp, size, *bshp, 0); 2846 2847 return 0; 2848 } 2849 2850 /* 2851 * int 2852 * pccbb_rbus_cb_space_free(cardbus_chipset_tag_t *ct, rbus_tag_t rb, 2853 * bus_space_handle_t *bshp, bus_size_t size); 2854 * 2855 * This function is called from CardBus card drivers. 2856 */ 2857 int 2858 pccbb_rbus_cb_space_free(ct, rb, bsh, size) 2859 cardbus_chipset_tag_t ct; 2860 rbus_tag_t rb; 2861 bus_space_handle_t bsh; 2862 bus_size_t size; 2863 { 2864 struct pccbb_softc *sc = (struct pccbb_softc *)ct; 2865 bus_space_tag_t bt = rb->rb_bt; 2866 2867 pccbb_close_win(sc, bt, bsh, size); 2868 2869 if (bt == sc->sc_memt) { 2870 } else if (bt == sc->sc_iot) { 2871 } else { 2872 return 1; 2873 /* XXX: panic here? */ 2874 } 2875 2876 return rbus_space_free(rb, bsh, size, NULL); 2877 } 2878 #endif /* rbus */ 2879 2880 #if rbus 2881 2882 int 2883 pccbb_open_win(sc, bst, addr, size, bsh, flags) 2884 struct pccbb_softc *sc; 2885 bus_space_tag_t bst; 2886 bus_addr_t addr; 2887 bus_size_t size; 2888 bus_space_handle_t bsh; 2889 int flags; 2890 { 2891 struct pccbb_win_chain_head *head; 2892 bus_addr_t align; 2893 2894 head = &sc->sc_iowindow; 2895 align = 0x04; 2896 if (sc->sc_memt == bst) { 2897 head = &sc->sc_memwindow; 2898 align = 0x1000; 2899 DPRINTF(("using memory window, %x %x %x\n\n", 2900 sc->sc_iot, sc->sc_memt, bst)); 2901 } 2902 2903 if (pccbb_winlist_insert(head, addr, size, bsh, flags)) { 2904 printf("%s: pccbb_open_win: %s winlist insert failed\n", 2905 sc->sc_dev.dv_xname, 2906 (head == &sc->sc_memwindow) ? "mem" : "io"); 2907 } 2908 pccbb_winset(align, sc, bst); 2909 2910 return 0; 2911 } 2912 2913 int 2914 pccbb_close_win(sc, bst, bsh, size) 2915 struct pccbb_softc *sc; 2916 bus_space_tag_t bst; 2917 bus_space_handle_t bsh; 2918 bus_size_t size; 2919 { 2920 struct pccbb_win_chain_head *head; 2921 bus_addr_t align; 2922 2923 head = &sc->sc_iowindow; 2924 align = 0x04; 2925 if (sc->sc_memt == bst) { 2926 head = &sc->sc_memwindow; 2927 align = 0x1000; 2928 } 2929 2930 if (pccbb_winlist_delete(head, bsh, size)) { 2931 printf("%s: pccbb_close_win: %s winlist delete failed\n", 2932 sc->sc_dev.dv_xname, 2933 (head == &sc->sc_memwindow) ? "mem" : "io"); 2934 } 2935 pccbb_winset(align, sc, bst); 2936 2937 return 0; 2938 } 2939 2940 int 2941 pccbb_winlist_insert(head, start, size, bsh, flags) 2942 struct pccbb_win_chain_head *head; 2943 bus_addr_t start; 2944 bus_size_t size; 2945 bus_space_handle_t bsh; 2946 int flags; 2947 { 2948 struct pccbb_win_chain *chainp, *elem; 2949 2950 if ((elem = malloc(sizeof(struct pccbb_win_chain), M_DEVBUF, 2951 M_NOWAIT)) == NULL) 2952 return (1); /* fail */ 2953 2954 elem->wc_start = start; 2955 elem->wc_end = start + (size - 1); 2956 elem->wc_handle = bsh; 2957 elem->wc_flags = flags; 2958 2959 for (chainp = TAILQ_FIRST(head); chainp != NULL; 2960 chainp = TAILQ_NEXT(chainp, wc_list)) { 2961 if (chainp->wc_end < start) 2962 continue; 2963 TAILQ_INSERT_AFTER(head, chainp, elem, wc_list); 2964 return (0); 2965 } 2966 2967 TAILQ_INSERT_TAIL(head, elem, wc_list); 2968 return (0); 2969 } 2970 2971 int 2972 pccbb_winlist_delete(head, bsh, size) 2973 struct pccbb_win_chain_head *head; 2974 bus_space_handle_t bsh; 2975 bus_size_t size; 2976 { 2977 struct pccbb_win_chain *chainp; 2978 2979 for (chainp = TAILQ_FIRST(head); chainp != NULL; 2980 chainp = TAILQ_NEXT(chainp, wc_list)) { 2981 if (chainp->wc_handle != bsh) 2982 continue; 2983 if ((chainp->wc_end - chainp->wc_start) != (size - 1)) { 2984 printf("pccbb_winlist_delete: window 0x%lx size " 2985 "inconsistent: 0x%lx, 0x%lx\n", 2986 chainp->wc_start, 2987 chainp->wc_end - chainp->wc_start, 2988 size - 1); 2989 return 1; 2990 } 2991 2992 TAILQ_REMOVE(head, chainp, wc_list); 2993 free(chainp, M_DEVBUF); 2994 2995 return 0; 2996 } 2997 2998 return 1; /* fail: no candidate to remove */ 2999 } 3000 3001 void 3002 pccbb_winset(align, sc, bst) 3003 bus_addr_t align; 3004 struct pccbb_softc *sc; 3005 bus_space_tag_t bst; 3006 { 3007 pci_chipset_tag_t pc; 3008 pcitag_t tag; 3009 bus_addr_t mask = ~(align - 1); 3010 struct { 3011 cardbusreg_t win_start; 3012 cardbusreg_t win_limit; 3013 int win_flags; 3014 } win[2]; 3015 struct pccbb_win_chain *chainp; 3016 int offs; 3017 3018 win[0].win_start = 0xffffffff; 3019 win[0].win_limit = 0; 3020 win[1].win_start = 0xffffffff; 3021 win[1].win_limit = 0; 3022 3023 chainp = TAILQ_FIRST(&sc->sc_iowindow); 3024 offs = 0x2c; 3025 if (sc->sc_memt == bst) { 3026 chainp = TAILQ_FIRST(&sc->sc_memwindow); 3027 offs = 0x1c; 3028 } 3029 3030 if (chainp != NULL) { 3031 win[0].win_start = chainp->wc_start & mask; 3032 win[0].win_limit = chainp->wc_end & mask; 3033 win[0].win_flags = chainp->wc_flags; 3034 chainp = TAILQ_NEXT(chainp, wc_list); 3035 } 3036 3037 for (; chainp != NULL; chainp = TAILQ_NEXT(chainp, wc_list)) { 3038 if (win[1].win_start == 0xffffffff) { 3039 /* window 1 is not used */ 3040 if ((win[0].win_flags == chainp->wc_flags) && 3041 (win[0].win_limit + align >= 3042 (chainp->wc_start & mask))) { 3043 /* concatenate */ 3044 win[0].win_limit = chainp->wc_end & mask; 3045 } else { 3046 /* make new window */ 3047 win[1].win_start = chainp->wc_start & mask; 3048 win[1].win_limit = chainp->wc_end & mask; 3049 win[1].win_flags = chainp->wc_flags; 3050 } 3051 continue; 3052 } 3053 3054 /* Both windows are engaged. */ 3055 if (win[0].win_flags == win[1].win_flags) { 3056 /* same flags */ 3057 if (win[0].win_flags == chainp->wc_flags) { 3058 if (win[1].win_start - (win[0].win_limit + 3059 align) < 3060 (chainp->wc_start & mask) - 3061 ((chainp->wc_end & mask) + align)) { 3062 /* 3063 * merge window 0 and 1, and set win1 3064 * to chainp 3065 */ 3066 win[0].win_limit = win[1].win_limit; 3067 win[1].win_start = 3068 chainp->wc_start & mask; 3069 win[1].win_limit = 3070 chainp->wc_end & mask; 3071 } else { 3072 win[1].win_limit = 3073 chainp->wc_end & mask; 3074 } 3075 } else { 3076 /* different flags */ 3077 3078 /* concatenate win0 and win1 */ 3079 win[0].win_limit = win[1].win_limit; 3080 /* allocate win[1] to new space */ 3081 win[1].win_start = chainp->wc_start & mask; 3082 win[1].win_limit = chainp->wc_end & mask; 3083 win[1].win_flags = chainp->wc_flags; 3084 } 3085 } else { 3086 /* the flags of win[0] and win[1] is different */ 3087 if (win[0].win_flags == chainp->wc_flags) { 3088 win[0].win_limit = chainp->wc_end & mask; 3089 /* 3090 * XXX this creates overlapping windows, so 3091 * what should the poor bridge do if one is 3092 * cachable, and the other is not? 3093 */ 3094 printf("%s: overlapping windows\n", 3095 sc->sc_dev.dv_xname); 3096 } else { 3097 win[1].win_limit = chainp->wc_end & mask; 3098 } 3099 } 3100 } 3101 3102 pc = sc->sc_pc; 3103 tag = sc->sc_tag; 3104 pci_conf_write(pc, tag, offs, win[0].win_start); 3105 pci_conf_write(pc, tag, offs + 4, win[0].win_limit); 3106 pci_conf_write(pc, tag, offs + 8, win[1].win_start); 3107 pci_conf_write(pc, tag, offs + 12, win[1].win_limit); 3108 DPRINTF(("--pccbb_winset: win0 [%x, %lx), win1 [%x, %lx)\n", 3109 pci_conf_read(pc, tag, offs), 3110 pci_conf_read(pc, tag, offs + 4) + align, 3111 pci_conf_read(pc, tag, offs + 8), 3112 pci_conf_read(pc, tag, offs + 12) + align)); 3113 3114 if (bst == sc->sc_memt) { 3115 if (win[0].win_flags & PCCBB_MEM_CACHABLE) { 3116 pcireg_t bcr = pci_conf_read(pc, tag, PCI_BCR_INTR); 3117 bcr |= CB_BCR_PREFETCH_MEMWIN0; 3118 pci_conf_write(pc, tag, PCI_BCR_INTR, bcr); 3119 } 3120 if (win[1].win_flags & PCCBB_MEM_CACHABLE) { 3121 pcireg_t bcr = pci_conf_read(pc, tag, PCI_BCR_INTR); 3122 bcr |= CB_BCR_PREFETCH_MEMWIN1; 3123 pci_conf_write(pc, tag, PCI_BCR_INTR, bcr); 3124 } 3125 } 3126 } 3127 3128 #endif /* rbus */ 3129 3130 void 3131 pccbb_powerhook(why, arg) 3132 int why; 3133 void *arg; 3134 { 3135 struct pccbb_softc *sc = arg; 3136 u_int32_t reg; 3137 bus_space_tag_t base_memt = sc->sc_base_memt; /* socket regs memory */ 3138 bus_space_handle_t base_memh = sc->sc_base_memh; 3139 3140 DPRINTF(("%s: power: why %d\n", sc->sc_dev.dv_xname, why)); 3141 3142 if (why == PWR_SUSPEND || why == PWR_STANDBY) { 3143 DPRINTF(("%s: power: why %d stopping intr\n", 3144 sc->sc_dev.dv_xname, why)); 3145 if (sc->sc_pil_intr_enable) { 3146 (void)pccbbintr_function(sc); 3147 } 3148 sc->sc_pil_intr_enable = 0; 3149 3150 /* ToDo: deactivate or suspend child devices */ 3151 3152 } 3153 3154 if (why == PWR_RESUME) { 3155 if (pci_conf_read (sc->sc_pc, sc->sc_tag, PCI_SOCKBASE) == 0) 3156 /* BIOS did not recover this register */ 3157 pci_conf_write (sc->sc_pc, sc->sc_tag, 3158 PCI_SOCKBASE, sc->sc_sockbase); 3159 if (pci_conf_read (sc->sc_pc, sc->sc_tag, PCI_BUSNUM) == 0) 3160 /* BIOS did not recover this register */ 3161 pci_conf_write (sc->sc_pc, sc->sc_tag, 3162 PCI_BUSNUM, sc->sc_busnum); 3163 /* CSC Interrupt: Card detect interrupt on */ 3164 reg = bus_space_read_4(base_memt, base_memh, CB_SOCKET_MASK); 3165 /* Card detect intr is turned on. */ 3166 reg |= CB_SOCKET_MASK_CD; 3167 bus_space_write_4(base_memt, base_memh, CB_SOCKET_MASK, reg); 3168 /* reset interrupt */ 3169 reg = bus_space_read_4(base_memt, base_memh, CB_SOCKET_EVENT); 3170 bus_space_write_4(base_memt, base_memh, CB_SOCKET_EVENT, reg); 3171 3172 /* 3173 * check for card insertion or removal during suspend period. 3174 * XXX: the code can't cope with card swap (remove then 3175 * insert). how can we detect such situation? 3176 */ 3177 (void)pccbbintr(sc); 3178 3179 sc->sc_pil_intr_enable = 1; 3180 DPRINTF(("%s: power: RESUME enabling intr\n", 3181 sc->sc_dev.dv_xname)); 3182 3183 /* ToDo: activate or wakeup child devices */ 3184 } 3185 } 3186