1 /* $OpenBSD: pccbb.c,v 1.63 2008/10/15 19:12:18 blambert Exp $ */ 2 /* $NetBSD: pccbb.c,v 1.96 2004/03/28 09:49:31 nakayama Exp $ */ 3 4 /* 5 * Copyright (c) 1998, 1999 and 2000 6 * HAYAKAWA Koichi. All rights reserved. 7 * 8 * Redistribution and use in source and binary forms, with or without 9 * modification, are permitted provided that the following conditions 10 * are met: 11 * 1. Redistributions of source code must retain the above copyright 12 * notice, this list of conditions and the following disclaimer. 13 * 2. Redistributions in binary form must reproduce the above copyright 14 * notice, this list of conditions and the following disclaimer in the 15 * documentation and/or other materials provided with the distribution. 16 * 3. All advertising materials mentioning features or use of this software 17 * must display the following acknowledgement: 18 * This product includes software developed by HAYAKAWA Koichi. 19 * 4. The name of the author may not be used to endorse or promote products 20 * derived from this software without specific prior written permission. 21 * 22 * THIS SOFTWARE IS PROVIDED BY THE AUTHOR ``AS IS'' AND ANY EXPRESS OR 23 * IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED WARRANTIES 24 * OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE DISCLAIMED. 25 * IN NO EVENT SHALL THE AUTHOR BE LIABLE FOR ANY DIRECT, INDIRECT, 26 * INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT 27 * NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, 28 * DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY 29 * THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT 30 * (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE OF 31 * THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE. 32 */ 33 34 /* 35 #define CBB_DEBUG 36 #define SHOW_REGS 37 #define PCCBB_PCMCIA_POLL 38 */ 39 40 /* 41 #define CB_PCMCIA_POLL 42 #define CB_PCMCIA_POLL_ONLY 43 #define LEVEL2 44 */ 45 46 #include <sys/types.h> 47 #include <sys/param.h> 48 #include <sys/systm.h> 49 #include <sys/kernel.h> 50 #include <sys/errno.h> 51 #include <sys/evcount.h> 52 #include <sys/ioctl.h> 53 #include <sys/syslog.h> 54 #include <sys/device.h> 55 #include <sys/malloc.h> 56 #include <sys/proc.h> 57 58 #include <machine/intr.h> 59 #include <machine/bus.h> 60 61 #include <dev/pci/pcivar.h> 62 #include <dev/pci/pcireg.h> 63 #include <dev/pci/pcidevs.h> 64 65 #include <dev/pci/pccbbreg.h> 66 67 #include <dev/cardbus/cardslotvar.h> 68 69 #include <dev/cardbus/cardbusvar.h> 70 71 #include <dev/pcmcia/pcmciareg.h> 72 #include <dev/pcmcia/pcmciavar.h> 73 74 #include <dev/ic/i82365reg.h> 75 #include <dev/ic/i82365var.h> 76 #include <dev/pci/pccbbvar.h> 77 78 #ifndef __NetBSD_Version__ 79 struct cfdriver cbb_cd = { 80 NULL, "cbb", DV_DULL 81 }; 82 #endif 83 84 #if defined CBB_DEBUG 85 #define DPRINTF(x) printf x 86 #else 87 #define DPRINTF(x) 88 #endif 89 90 int pcicbbmatch(struct device *, void *, void *); 91 void pccbbattach(struct device *, struct device *, void *); 92 int pccbbintr(void *); 93 void pccbb_shutdown(void *); 94 void pci113x_insert(void *); 95 int pccbbintr_function(struct pccbb_softc *); 96 97 int pccbb_detect_card(struct pccbb_softc *); 98 99 void pccbb_pcmcia_write(struct pcic_handle *, int, int); 100 u_int8_t pccbb_pcmcia_read(struct pcic_handle *, int); 101 #define Pcic_read(ph, reg) ((ph)->ph_read((ph), (reg))) 102 #define Pcic_write(ph, reg, val) ((ph)->ph_write((ph), (reg), (val))) 103 104 int cb_reset(struct pccbb_softc *); 105 int cb_detect_voltage(struct pccbb_softc *); 106 int cbbprint(void *, const char *); 107 108 int cb_chipset(u_int32_t, int *); 109 void pccbb_pcmcia_attach_setup(struct pccbb_softc *, 110 struct pcmciabus_attach_args *); 111 #if 0 112 void pccbb_pcmcia_attach_card(struct pcic_handle *); 113 void pccbb_pcmcia_detach_card(struct pcic_handle *, int); 114 void pccbb_pcmcia_deactivate_card(struct pcic_handle *); 115 #endif 116 117 int pccbb_ctrl(cardbus_chipset_tag_t, int); 118 int pccbb_power(cardbus_chipset_tag_t, int); 119 int pccbb_cardenable(struct pccbb_softc * sc, int function); 120 void *pccbb_intr_establish(struct pccbb_softc *, int irq, int level, 121 int (*ih) (void *), void *sc, const char *); 122 void pccbb_intr_disestablish(struct pccbb_softc *, void *ih); 123 124 void *pccbb_cb_intr_establish(cardbus_chipset_tag_t, int irq, int level, 125 int (*ih) (void *), void *sc, const char *); 126 void pccbb_cb_intr_disestablish(cardbus_chipset_tag_t ct, void *ih); 127 128 cardbustag_t pccbb_make_tag(cardbus_chipset_tag_t, int, int, int); 129 void pccbb_free_tag(cardbus_chipset_tag_t, cardbustag_t); 130 cardbusreg_t pccbb_conf_read(cardbus_chipset_tag_t, cardbustag_t, int); 131 void pccbb_conf_write(cardbus_chipset_tag_t, cardbustag_t, int, 132 cardbusreg_t); 133 void pccbb_chipinit(struct pccbb_softc *); 134 135 int pccbb_pcmcia_mem_alloc(pcmcia_chipset_handle_t, bus_size_t, 136 struct pcmcia_mem_handle *); 137 void pccbb_pcmcia_mem_free(pcmcia_chipset_handle_t, 138 struct pcmcia_mem_handle *); 139 int pccbb_pcmcia_mem_map(pcmcia_chipset_handle_t, int, bus_addr_t, 140 bus_size_t, struct pcmcia_mem_handle *, bus_size_t *, int *); 141 void pccbb_pcmcia_mem_unmap(pcmcia_chipset_handle_t, int); 142 int pccbb_pcmcia_io_alloc(pcmcia_chipset_handle_t, bus_addr_t, 143 bus_size_t, bus_size_t, struct pcmcia_io_handle *); 144 void pccbb_pcmcia_io_free(pcmcia_chipset_handle_t, 145 struct pcmcia_io_handle *); 146 int pccbb_pcmcia_io_map(pcmcia_chipset_handle_t, int, bus_addr_t, 147 bus_size_t, struct pcmcia_io_handle *, int *); 148 void pccbb_pcmcia_io_unmap(pcmcia_chipset_handle_t, int); 149 void *pccbb_pcmcia_intr_establish(pcmcia_chipset_handle_t, 150 struct pcmcia_function *, int, int (*)(void *), void *, char *); 151 void pccbb_pcmcia_intr_disestablish(pcmcia_chipset_handle_t, void *); 152 const char *pccbb_pcmcia_intr_string(pcmcia_chipset_handle_t, void *); 153 void pccbb_pcmcia_socket_enable(pcmcia_chipset_handle_t); 154 void pccbb_pcmcia_socket_disable(pcmcia_chipset_handle_t); 155 int pccbb_pcmcia_card_detect(pcmcia_chipset_handle_t pch); 156 157 void pccbb_pcmcia_do_io_map(struct pcic_handle *, int); 158 void pccbb_pcmcia_wait_ready(struct pcic_handle *); 159 void pccbb_pcmcia_do_mem_map(struct pcic_handle *, int); 160 void pccbb_powerhook(int, void *); 161 162 /* bus-space allocation and deallocation functions */ 163 int pccbb_rbus_cb_space_alloc(cardbus_chipset_tag_t, rbus_tag_t, 164 bus_addr_t addr, bus_size_t size, bus_addr_t mask, bus_size_t align, 165 int flags, bus_addr_t * addrp, bus_space_handle_t * bshp); 166 int pccbb_rbus_cb_space_free(cardbus_chipset_tag_t, rbus_tag_t, 167 bus_space_handle_t, bus_size_t); 168 169 int pccbb_open_win(struct pccbb_softc *, bus_space_tag_t, 170 bus_addr_t, bus_size_t, bus_space_handle_t, int flags); 171 int pccbb_close_win(struct pccbb_softc *, bus_space_tag_t, 172 bus_space_handle_t, bus_size_t); 173 int pccbb_winlist_insert(struct pccbb_win_chain_head *, bus_addr_t, 174 bus_size_t, bus_space_handle_t, int); 175 int pccbb_winlist_delete(struct pccbb_win_chain_head *, 176 bus_space_handle_t, bus_size_t); 177 void pccbb_winset(bus_addr_t align, struct pccbb_softc *, 178 bus_space_tag_t); 179 void pccbb_winlist_show(struct pccbb_win_chain *); 180 181 /* for config_defer */ 182 void pccbb_pci_callback(struct device *); 183 184 #if defined SHOW_REGS 185 void cb_show_regs(pci_chipset_tag_t, pcitag_t, bus_space_tag_t, 186 bus_space_handle_t memh); 187 #endif 188 189 struct cfattach cbb_pci_ca = { 190 sizeof(struct pccbb_softc), pcicbbmatch, pccbbattach 191 }; 192 193 static struct pcmcia_chip_functions pccbb_pcmcia_funcs = { 194 pccbb_pcmcia_mem_alloc, 195 pccbb_pcmcia_mem_free, 196 pccbb_pcmcia_mem_map, 197 pccbb_pcmcia_mem_unmap, 198 pccbb_pcmcia_io_alloc, 199 pccbb_pcmcia_io_free, 200 pccbb_pcmcia_io_map, 201 pccbb_pcmcia_io_unmap, 202 pccbb_pcmcia_intr_establish, 203 pccbb_pcmcia_intr_disestablish, 204 pccbb_pcmcia_intr_string, 205 pccbb_pcmcia_socket_enable, 206 pccbb_pcmcia_socket_disable, 207 pccbb_pcmcia_card_detect 208 }; 209 210 static struct cardbus_functions pccbb_funcs = { 211 pccbb_rbus_cb_space_alloc, 212 pccbb_rbus_cb_space_free, 213 pccbb_cb_intr_establish, 214 pccbb_cb_intr_disestablish, 215 pccbb_ctrl, 216 pccbb_power, 217 pccbb_make_tag, 218 pccbb_free_tag, 219 pccbb_conf_read, 220 pccbb_conf_write, 221 }; 222 223 /* 224 * delay_ms() is wait in milliseconds. It should be used instead 225 * of delay() if you want to wait more than 1 ms. 226 */ 227 static inline void 228 delay_ms(int millis, void *param) 229 { 230 if (cold) 231 delay(millis * 1000); 232 else 233 tsleep(param, PWAIT, "pccbb", MAX(2, hz * millis / 1000)); 234 } 235 236 int 237 pcicbbmatch(parent, match, aux) 238 struct device *parent; 239 void *match; 240 void *aux; 241 { 242 struct pci_attach_args *pa = (struct pci_attach_args *)aux; 243 244 if (PCI_CLASS(pa->pa_class) == PCI_CLASS_BRIDGE && 245 PCI_SUBCLASS(pa->pa_class) == PCI_SUBCLASS_BRIDGE_CARDBUS && 246 PCI_INTERFACE(pa->pa_class) == 0) { 247 return 1; 248 } 249 250 return 0; 251 } 252 253 #define MAKEID(vendor, prod) (((vendor) << PCI_VENDOR_SHIFT) \ 254 | ((prod) << PCI_PRODUCT_SHIFT)) 255 256 struct yenta_chipinfo { 257 pcireg_t yc_id; /* vendor tag | product tag */ 258 int yc_chiptype; 259 int yc_flags; 260 } yc_chipsets[] = { 261 /* Texas Instruments chips */ 262 { MAKEID(PCI_VENDOR_TI, PCI_PRODUCT_TI_PCI1130), CB_TI113X, 263 PCCBB_PCMCIA_IO_RELOC | PCCBB_PCMCIA_MEM_32}, 264 { MAKEID(PCI_VENDOR_TI, PCI_PRODUCT_TI_PCI1131), CB_TI113X, 265 PCCBB_PCMCIA_IO_RELOC | PCCBB_PCMCIA_MEM_32}, 266 { MAKEID(PCI_VENDOR_TI, PCI_PRODUCT_TI_PCI1250), CB_TI125X, 267 PCCBB_PCMCIA_IO_RELOC | PCCBB_PCMCIA_MEM_32}, 268 { MAKEID(PCI_VENDOR_TI, PCI_PRODUCT_TI_PCI1220), CB_TI12XX, 269 PCCBB_PCMCIA_IO_RELOC | PCCBB_PCMCIA_MEM_32}, 270 { MAKEID(PCI_VENDOR_TI, PCI_PRODUCT_TI_PCI1221), CB_TI12XX, 271 PCCBB_PCMCIA_IO_RELOC | PCCBB_PCMCIA_MEM_32}, 272 { MAKEID(PCI_VENDOR_TI, PCI_PRODUCT_TI_PCI1225), CB_TI12XX, 273 PCCBB_PCMCIA_IO_RELOC | PCCBB_PCMCIA_MEM_32}, 274 { MAKEID(PCI_VENDOR_TI, PCI_PRODUCT_TI_PCI1251), CB_TI125X, 275 PCCBB_PCMCIA_IO_RELOC | PCCBB_PCMCIA_MEM_32}, 276 { MAKEID(PCI_VENDOR_TI, PCI_PRODUCT_TI_PCI1251B), CB_TI125X, 277 PCCBB_PCMCIA_IO_RELOC | PCCBB_PCMCIA_MEM_32}, 278 { MAKEID(PCI_VENDOR_TI, PCI_PRODUCT_TI_PCI1211), CB_TI12XX, 279 PCCBB_PCMCIA_IO_RELOC | PCCBB_PCMCIA_MEM_32}, 280 { MAKEID(PCI_VENDOR_TI, PCI_PRODUCT_TI_PCI1410), CB_TI12XX, 281 PCCBB_PCMCIA_IO_RELOC | PCCBB_PCMCIA_MEM_32}, 282 { MAKEID(PCI_VENDOR_TI, PCI_PRODUCT_TI_PCI1420), CB_TI12XX, 283 PCCBB_PCMCIA_IO_RELOC | PCCBB_PCMCIA_MEM_32}, 284 { MAKEID(PCI_VENDOR_TI, PCI_PRODUCT_TI_PCI1450), CB_TI125X, 285 PCCBB_PCMCIA_IO_RELOC | PCCBB_PCMCIA_MEM_32}, 286 { MAKEID(PCI_VENDOR_TI, PCI_PRODUCT_TI_PCI1451), CB_TI12XX, 287 PCCBB_PCMCIA_IO_RELOC | PCCBB_PCMCIA_MEM_32}, 288 { MAKEID(PCI_VENDOR_TI, PCI_PRODUCT_TI_PCI1510), CB_TI12XX, 289 PCCBB_PCMCIA_IO_RELOC | PCCBB_PCMCIA_MEM_32}, 290 { MAKEID(PCI_VENDOR_TI, PCI_PRODUCT_TI_PCI7XX1), CB_TI12XX, 291 PCCBB_PCMCIA_IO_RELOC | PCCBB_PCMCIA_MEM_32}, 292 293 /* Ricoh chips */ 294 { MAKEID(PCI_VENDOR_RICOH, PCI_PRODUCT_RICOH_RF5C475), CB_RX5C47X, 295 PCCBB_PCMCIA_MEM_32}, 296 { MAKEID(PCI_VENDOR_RICOH, PCI_PRODUCT_RICOH_RF5C476), CB_RX5C47X, 297 PCCBB_PCMCIA_MEM_32}, 298 { MAKEID(PCI_VENDOR_RICOH, PCI_PRODUCT_RICOH_RF5C477), CB_RX5C47X, 299 PCCBB_PCMCIA_MEM_32}, 300 { MAKEID(PCI_VENDOR_RICOH, PCI_PRODUCT_RICOH_RF5C478), CB_RX5C47X, 301 PCCBB_PCMCIA_MEM_32}, 302 { MAKEID(PCI_VENDOR_RICOH, PCI_PRODUCT_RICOH_RF5C465), CB_RX5C46X, 303 PCCBB_PCMCIA_MEM_32}, 304 { MAKEID(PCI_VENDOR_RICOH, PCI_PRODUCT_RICOH_RF5C466), CB_RX5C46X, 305 PCCBB_PCMCIA_MEM_32}, 306 307 /* Toshiba products */ 308 { MAKEID(PCI_VENDOR_TOSHIBA2, PCI_PRODUCT_TOSHIBA2_ToPIC95), 309 CB_TOPIC95, PCCBB_PCMCIA_MEM_32}, 310 { MAKEID(PCI_VENDOR_TOSHIBA2, PCI_PRODUCT_TOSHIBA2_ToPIC95B), 311 CB_TOPIC95B, PCCBB_PCMCIA_MEM_32}, 312 { MAKEID(PCI_VENDOR_TOSHIBA2, PCI_PRODUCT_TOSHIBA2_ToPIC97), 313 CB_TOPIC97, PCCBB_PCMCIA_MEM_32}, 314 { MAKEID(PCI_VENDOR_TOSHIBA2, PCI_PRODUCT_TOSHIBA2_ToPIC100), 315 CB_TOPIC97, PCCBB_PCMCIA_MEM_32}, 316 317 /* Cirrus Logic products */ 318 { MAKEID(PCI_VENDOR_CIRRUS, PCI_PRODUCT_CIRRUS_CL_PD6832), 319 CB_CIRRUS, PCCBB_PCMCIA_MEM_32}, 320 { MAKEID(PCI_VENDOR_CIRRUS, PCI_PRODUCT_CIRRUS_CL_PD6833), 321 CB_CIRRUS, PCCBB_PCMCIA_MEM_32}, 322 323 /* older O2Micro bridges */ 324 { MAKEID(PCI_VENDOR_O2MICRO, PCI_PRODUCT_O2MICRO_OZ6729), 325 CB_OLDO2MICRO, PCCBB_PCMCIA_MEM_32}, 326 { MAKEID(PCI_VENDOR_O2MICRO, PCI_PRODUCT_O2MICRO_OZ6730), 327 CB_OLDO2MICRO, PCCBB_PCMCIA_MEM_32}, 328 { MAKEID(PCI_VENDOR_O2MICRO, PCI_PRODUCT_O2MICRO_OZ6872), /* 68[71]2 */ 329 CB_OLDO2MICRO, PCCBB_PCMCIA_MEM_32}, 330 { MAKEID(PCI_VENDOR_O2MICRO, PCI_PRODUCT_O2MICRO_OZ6832), 331 CB_OLDO2MICRO, PCCBB_PCMCIA_MEM_32}, 332 { MAKEID(PCI_VENDOR_O2MICRO, PCI_PRODUCT_O2MICRO_OZ6836), 333 CB_OLDO2MICRO, PCCBB_PCMCIA_MEM_32}, 334 335 /* sentinel, or Generic chip */ 336 { 0 /* null id */ , CB_UNKNOWN, PCCBB_PCMCIA_MEM_32}, 337 }; 338 339 int 340 cb_chipset(pci_id, flagp) 341 u_int32_t pci_id; 342 int *flagp; 343 { 344 struct yenta_chipinfo *yc; 345 346 /* Loop over except the last default entry. */ 347 for (yc = yc_chipsets; yc < yc_chipsets + 348 sizeof(yc_chipsets) / sizeof(yc_chipsets[0]) - 1; yc++) 349 if (pci_id == yc->yc_id) 350 break; 351 352 if (flagp != NULL) 353 *flagp = yc->yc_flags; 354 355 return (yc->yc_chiptype); 356 } 357 358 void 359 pccbb_shutdown(void *arg) 360 { 361 struct pccbb_softc *sc = arg; 362 pcireg_t command; 363 364 DPRINTF(("%s: shutdown\n", sc->sc_dev.dv_xname)); 365 366 /* Nothing for us to do if we didn't map any registers. */ 367 if ((sc->sc_flags & CBB_MEMHMAPPED) == 0) 368 return; 369 370 /* turn off power */ 371 pccbb_power((cardbus_chipset_tag_t)sc, CARDBUS_VCC_0V | CARDBUS_VPP_0V); 372 373 bus_space_write_4(sc->sc_base_memt, sc->sc_base_memh, CB_SOCKET_MASK, 374 0); 375 376 command = pci_conf_read(sc->sc_pc, sc->sc_tag, PCI_COMMAND_STATUS_REG); 377 378 command &= ~(PCI_COMMAND_IO_ENABLE | PCI_COMMAND_MEM_ENABLE | 379 PCI_COMMAND_MASTER_ENABLE); 380 pci_conf_write(sc->sc_pc, sc->sc_tag, PCI_COMMAND_STATUS_REG, command); 381 } 382 383 void 384 pccbbattach(parent, self, aux) 385 struct device *parent; 386 struct device *self; 387 void *aux; 388 { 389 struct pccbb_softc *sc = (void *)self; 390 struct pci_attach_args *pa = aux; 391 pci_chipset_tag_t pc = pa->pa_pc; 392 pcireg_t busreg, reg, sock_base; 393 pci_intr_handle_t ih; 394 const char *intrstr = NULL; 395 bus_addr_t sockbase; 396 int flags; 397 398 pccbb_attach_hook(parent, self, pa); 399 400 sc->sc_chipset = cb_chipset(pa->pa_id, &flags); 401 sc->sc_id = pa->pa_id; 402 403 #ifdef CBB_DEBUG 404 printf(" (chipflags %x)", flags); 405 #endif 406 407 TAILQ_INIT(&sc->sc_memwindow); 408 TAILQ_INIT(&sc->sc_iowindow); 409 410 sc->sc_rbus_iot = rbus_pccbb_parent_io(self, pa); 411 sc->sc_rbus_memt = rbus_pccbb_parent_mem(self, pa); 412 413 sc->sc_flags &= ~CBB_MEMHMAPPED; 414 415 /* 416 * MAP socket registers and ExCA registers on memory-space 417 * When no valid address is set on socket base registers (on pci 418 * config space), get it not polite way. 419 */ 420 sock_base = pci_conf_read(pc, pa->pa_tag, PCI_SOCKBASE); 421 422 if (PCI_MAPREG_MEM_ADDR(sock_base) >= 0x100000 && 423 PCI_MAPREG_MEM_ADDR(sock_base) != 0xfffffff0) { 424 /* The address must be valid. */ 425 if (pci_mapreg_map(pa, PCI_SOCKBASE, PCI_MAPREG_TYPE_MEM, 0, 426 &sc->sc_base_memt, &sc->sc_base_memh, &sockbase, NULL, 0)) 427 { 428 printf("%s: can't map socket base address 0x%x\n", 429 sc->sc_dev.dv_xname, sock_base); 430 /* 431 * I think it's funny: socket base registers must be 432 * mapped on memory space, but ... 433 */ 434 if (pci_mapreg_map(pa, PCI_SOCKBASE, 435 PCI_MAPREG_TYPE_IO, 0, &sc->sc_base_memt, 436 &sc->sc_base_memh, &sockbase, NULL, 0)) { 437 printf("%s: can't map socket base address" 438 " 0x%lx: io mode\n", sc->sc_dev.dv_xname, 439 sockbase); 440 /* give up... allocate reg space via rbus. */ 441 pci_conf_write(pc, pa->pa_tag, PCI_SOCKBASE, 0); 442 } else 443 sc->sc_flags |= CBB_MEMHMAPPED; 444 } else { 445 DPRINTF(("%s: socket base address 0x%lx\n", 446 sc->sc_dev.dv_xname, sockbase)); 447 sc->sc_flags |= CBB_MEMHMAPPED; 448 } 449 } 450 451 sc->sc_mem_start = 0; /* XXX */ 452 sc->sc_mem_end = 0xffffffff; /* XXX */ 453 454 busreg = pci_conf_read(pc, pa->pa_tag, PCI_BUSNUM); 455 456 /* pccbb_machdep.c end */ 457 458 #if defined CBB_DEBUG 459 { 460 static char *intrname[5] = { "NON", "A", "B", "C", "D" }; 461 printf(": intrpin %s, line %d\n", 462 intrname[pa->pa_intrpin], pa->pa_intrline); 463 } 464 #endif 465 466 /* setup softc */ 467 sc->sc_pc = pc; 468 sc->sc_iot = pa->pa_iot; 469 sc->sc_memt = pa->pa_memt; 470 sc->sc_dmat = pa->pa_dmat; 471 sc->sc_tag = pa->pa_tag; 472 sc->sc_function = pa->pa_function; 473 sc->sc_sockbase = sock_base; 474 sc->sc_busnum = busreg; 475 sc->sc_intrtag = pa->pa_intrtag; 476 sc->sc_intrpin = pa->pa_intrpin; 477 478 sc->sc_pcmcia_flags = flags; /* set PCMCIA facility */ 479 480 /* Map and establish the interrupt. */ 481 if (pci_intr_map(pa, &ih)) { 482 printf(": couldn't map interrupt\n"); 483 return; 484 } 485 intrstr = pci_intr_string(pc, ih); 486 /* must do this after intr is mapped and established */ 487 sc->sc_intrline = pci_intr_line(ih); 488 489 /* 490 * XXX pccbbintr should be called under the priority lower 491 * than any other hard interrupts. 492 */ 493 sc->sc_ih = pci_intr_establish(pc, ih, IPL_BIO, pccbbintr, sc, 494 sc->sc_dev.dv_xname); 495 496 if (sc->sc_ih == NULL) { 497 printf(": couldn't establish interrupt"); 498 if (intrstr != NULL) { 499 printf(" at %s", intrstr); 500 } 501 printf("\n"); 502 return; 503 } 504 printf(": %s", intrstr); 505 506 /* 507 * When bus number isn't set correctly, give up using 32-bit CardBus 508 * mode. 509 */ 510 if (((busreg >> 8) & 0xff) == 0) { 511 printf(", CardBus support disabled"); 512 sc->sc_pcmcia_flags |= PCCBB_PCMCIA_16BITONLY; 513 } 514 515 printf("\n"); 516 517 shutdownhook_establish(pccbb_shutdown, sc); 518 519 /* Disable legacy register mapping. */ 520 switch (sc->sc_chipset) { 521 case CB_RX5C46X: /* fallthrough */ 522 #if 0 523 /* The RX5C47X-series requires writes to the PCI_LEGACY register. */ 524 case CB_RX5C47X: 525 #endif 526 /* 527 * The legacy pcic io-port on Ricoh RX5C46X CardBus bridges 528 * cannot be disabled by substituting 0 into PCI_LEGACY 529 * register. Ricoh CardBus bridges have special bits on Bridge 530 * control reg (addr 0x3e on PCI config space). 531 */ 532 reg = pci_conf_read(pc, pa->pa_tag, PCI_BCR_INTR); 533 reg &= ~(CB_BCRI_RL_3E0_ENA | CB_BCRI_RL_3E2_ENA); 534 pci_conf_write(pc, pa->pa_tag, PCI_BCR_INTR, reg); 535 break; 536 537 default: 538 /* XXX I don't know proper way to kill legacy I/O. */ 539 pci_conf_write(pc, pa->pa_tag, PCI_LEGACY, 0x0); 540 break; 541 } 542 543 timeout_set(&sc->sc_ins_tmo, pci113x_insert, sc); 544 config_defer(self, pccbb_pci_callback); 545 } 546 547 /* 548 * void pccbb_pci_callback(struct device *self) 549 * 550 * The actual attach routine: get memory space for YENTA register 551 * space, setup YENTA register and route interrupt. 552 * 553 * This function should be deferred because this device may obtain 554 * memory space dynamically. This function must avoid obtaining 555 * memory area which has already kept for another device. Also, 556 * this function MUST be done before ISA attach process because this 557 * function kills pcic compatible port used by ISA pcic. 558 */ 559 void 560 pccbb_pci_callback(self) 561 struct device *self; 562 { 563 struct pccbb_softc *sc = (void *)self; 564 pci_chipset_tag_t pc = sc->sc_pc; 565 bus_space_tag_t base_memt; 566 bus_space_handle_t base_memh; 567 u_int32_t maskreg; 568 bus_addr_t sockbase; 569 struct cbslot_attach_args cba; 570 struct pcmciabus_attach_args paa; 571 struct cardslot_attach_args caa; 572 struct cardslot_softc *csc; 573 u_int32_t sockstat; 574 575 if (!(sc->sc_flags & CBB_MEMHMAPPED)) { 576 /* The socket registers aren't mapped correctly. */ 577 if (rbus_space_alloc(sc->sc_rbus_memt, 0, 0x1000, 0x0fff, 578 (sc->sc_chipset == CB_RX5C47X 579 || sc->sc_chipset == CB_TI113X) ? 0x10000 : 0x1000, 580 0, &sockbase, &sc->sc_base_memh)) { 581 return; 582 } 583 sc->sc_base_memt = sc->sc_memt; 584 pci_conf_write(pc, sc->sc_tag, PCI_SOCKBASE, sockbase); 585 DPRINTF(("%s: CardBus register address 0x%lx -> 0x%x\n", 586 sc->sc_dev.dv_xname, sockbase, pci_conf_read(pc, sc->sc_tag, 587 PCI_SOCKBASE))); 588 sc->sc_flags |= CBB_MEMHMAPPED; 589 } 590 591 base_memt = sc->sc_base_memt; /* socket regs memory tag */ 592 base_memh = sc->sc_base_memh; /* socket regs memory handle */ 593 594 /* bus bridge initialization */ 595 pccbb_chipinit(sc); 596 597 /* clear data structure for child device interrupt handlers */ 598 sc->sc_pil = NULL; 599 sc->sc_pil_intr_enable = 1; 600 601 powerhook_establish(pccbb_powerhook, sc); 602 603 sockstat = bus_space_read_4(base_memt, base_memh, CB_SOCKET_STAT); 604 if ((sockstat & CB_SOCKET_STAT_CD) == 0) 605 sc->sc_flags |= CBB_CARDEXIST; 606 607 /* 608 * attach cardbus 609 */ 610 if (!(sc->sc_pcmcia_flags & PCCBB_PCMCIA_16BITONLY)) { 611 pcireg_t busreg = pci_conf_read(pc, sc->sc_tag, PCI_BUSNUM); 612 pcireg_t bhlc = pci_conf_read(pc, sc->sc_tag, PCI_BHLC_REG); 613 614 /* initialize cbslot_attach */ 615 cba.cba_busname = "cardbus"; 616 cba.cba_iot = sc->sc_iot; 617 cba.cba_memt = sc->sc_memt; 618 cba.cba_dmat = sc->sc_dmat; 619 cba.cba_bus = (busreg >> 8) & 0x0ff; 620 cba.cba_cc = (void *)sc; 621 cba.cba_cf = &pccbb_funcs; 622 cba.cba_intrline = sc->sc_intrline; 623 624 cba.cba_rbus_iot = sc->sc_rbus_iot; 625 cba.cba_rbus_memt = sc->sc_rbus_memt; 626 627 cba.cba_cacheline = PCI_CACHELINE(bhlc); 628 cba.cba_lattimer = PCI_CB_LATENCY(busreg); 629 630 #if defined CBB_DEBUG 631 printf("%s: cacheline 0x%x lattimer 0x%x\n", 632 sc->sc_dev.dv_xname, cba.cba_cacheline, cba.cba_lattimer); 633 printf("%s: bhlc 0x%x lscp 0x%x\n", sc->sc_dev.dv_xname, bhlc, 634 busreg); 635 #endif 636 #if defined SHOW_REGS 637 cb_show_regs(sc->sc_pc, sc->sc_tag, sc->sc_base_memt, 638 sc->sc_base_memh); 639 #endif 640 } 641 642 pccbb_pcmcia_attach_setup(sc, &paa); 643 caa.caa_cb_attach = NULL; 644 if (!(sc->sc_pcmcia_flags & PCCBB_PCMCIA_16BITONLY)) { 645 caa.caa_cb_attach = &cba; 646 } 647 caa.caa_16_attach = &paa; 648 caa.caa_ph = &sc->sc_pcmcia_h; 649 650 if (NULL != (csc = (void *)config_found(self, &caa, cbbprint))) { 651 DPRINTF(("pccbbattach: found cardslot\n")); 652 sc->sc_csc = csc; 653 } 654 655 sc->sc_ints_on = 1; 656 657 /* CSC Interrupt: Card detect interrupt on */ 658 maskreg = bus_space_read_4(base_memt, base_memh, CB_SOCKET_MASK); 659 maskreg |= CB_SOCKET_MASK_CD; /* Card detect intr is turned on. */ 660 bus_space_write_4(base_memt, base_memh, CB_SOCKET_MASK, maskreg); 661 /* reset interrupt */ 662 bus_space_write_4(base_memt, base_memh, CB_SOCKET_EVENT, 663 bus_space_read_4(base_memt, base_memh, CB_SOCKET_EVENT)); 664 665 return; 666 } 667 668 /* 669 * void pccbb_chipinit(struct pccbb_softc *sc) 670 * 671 * This function initialize YENTA chip registers listed below: 672 * 1) PCI command reg, 673 * 2) PCI and CardBus latency timer, 674 * 3) route PCI interrupt, 675 * 4) close all memory and io windows. 676 */ 677 void 678 pccbb_chipinit(sc) 679 struct pccbb_softc *sc; 680 { 681 pci_chipset_tag_t pc = sc->sc_pc; 682 pcitag_t tag = sc->sc_tag; 683 pcireg_t reg; 684 685 /* 686 * Set PCI command reg. 687 * Some laptop's BIOSes (i.e. TICO) do not enable CardBus chip. 688 */ 689 reg = pci_conf_read(pc, tag, PCI_COMMAND_STATUS_REG); 690 /* I believe it is harmless. */ 691 reg |= (PCI_COMMAND_IO_ENABLE | PCI_COMMAND_MEM_ENABLE | 692 PCI_COMMAND_MASTER_ENABLE); 693 pci_conf_write(pc, tag, PCI_COMMAND_STATUS_REG, reg); 694 695 /* 696 * Set CardBus latency timer. 697 */ 698 reg = pci_conf_read(pc, tag, PCI_CB_LSCP_REG); 699 if (PCI_CB_LATENCY(reg) < 0x20) { 700 reg &= ~(PCI_CB_LATENCY_MASK << PCI_CB_LATENCY_SHIFT); 701 reg |= (0x20 << PCI_CB_LATENCY_SHIFT); 702 pci_conf_write(pc, tag, PCI_CB_LSCP_REG, reg); 703 } 704 DPRINTF(("CardBus latency timer 0x%x (%x)\n", 705 PCI_CB_LATENCY(reg), pci_conf_read(pc, tag, PCI_CB_LSCP_REG))); 706 707 /* 708 * Set PCI latency timer. 709 */ 710 reg = pci_conf_read(pc, tag, PCI_BHLC_REG); 711 if (PCI_LATTIMER(reg) < 0x10) { 712 reg &= ~(PCI_LATTIMER_MASK << PCI_LATTIMER_SHIFT); 713 reg |= (0x10 << PCI_LATTIMER_SHIFT); 714 pci_conf_write(pc, tag, PCI_BHLC_REG, reg); 715 } 716 DPRINTF(("PCI latency timer 0x%x (%x)\n", 717 PCI_LATTIMER(reg), pci_conf_read(pc, tag, PCI_BHLC_REG))); 718 719 /* Route functional interrupts to PCI. */ 720 reg = pci_conf_read(pc, tag, PCI_BCR_INTR); 721 reg |= CB_BCR_INTR_IREQ_ENABLE; /* disable PCI Intr */ 722 reg |= CB_BCR_WRITE_POST_ENABLE; /* enable write post */ 723 reg |= CB_BCR_RESET_ENABLE; /* assert reset */ 724 pci_conf_write(pc, tag, PCI_BCR_INTR, reg); 725 726 switch (sc->sc_chipset) { 727 case CB_TI113X: 728 reg = pci_conf_read(pc, tag, PCI_CBCTRL); 729 /* This bit is shared, but may read as 0 on some chips, so set 730 it explicitly on both functions. */ 731 reg |= PCI113X_CBCTRL_PCI_IRQ_ENA; 732 /* CSC intr enable */ 733 reg |= PCI113X_CBCTRL_PCI_CSC; 734 /* functional intr prohibit | prohibit ISA routing */ 735 reg &= ~(PCI113X_CBCTRL_PCI_INTR | PCI113X_CBCTRL_INT_MASK); 736 pci_conf_write(pc, tag, PCI_CBCTRL, reg); 737 break; 738 739 case CB_TI12XX: 740 /* 741 * Some TI 12xx (and [14][45]xx) based pci cards 742 * sometimes have issues with the MFUNC register not 743 * being initialized due to a bad EEPROM on board. 744 * Laptops that this matters on have this register 745 * properly initialized. 746 * 747 * The TI125X parts have a different register. 748 */ 749 reg = pci_conf_read(pc, tag, PCI12XX_MFUNC); 750 if (reg == PCI12XX_MFUNC_DEFAULT) { 751 reg &= ~PCI12XX_MFUNC_PIN0; 752 reg |= PCI12XX_MFUNC_PIN0_INTA; 753 if ((pci_conf_read(pc, tag, PCI_SYSCTRL) & 754 PCI12XX_SYSCTRL_INTRTIE) == 0) { 755 reg &= ~PCI12XX_MFUNC_PIN1; 756 reg |= PCI12XX_MFUNC_PIN1_INTB; 757 } 758 pci_conf_write(pc, tag, PCI12XX_MFUNC, reg); 759 } 760 /* FALLTHROUGH */ 761 762 case CB_TI125X: 763 /* 764 * Disable zoom video. Some machines initialize this 765 * improperly and experience has shown that this helps 766 * prevent strange behavior. 767 */ 768 pci_conf_write(pc, tag, PCI12XX_MMCTRL, 0); 769 770 reg = pci_conf_read(pc, tag, PCI_SYSCTRL); 771 reg |= PCI12XX_SYSCTRL_VCCPROT; 772 pci_conf_write(pc, tag, PCI_SYSCTRL, reg); 773 reg = pci_conf_read(pc, tag, PCI_CBCTRL); 774 reg |= PCI12XX_CBCTRL_CSC; 775 pci_conf_write(pc, tag, PCI_CBCTRL, reg); 776 break; 777 778 case CB_TOPIC95B: 779 reg = pci_conf_read(pc, tag, TOPIC_SOCKET_CTRL); 780 reg |= TOPIC_SOCKET_CTRL_SCR_IRQSEL; 781 pci_conf_write(pc, tag, TOPIC_SOCKET_CTRL, reg); 782 783 reg = pci_conf_read(pc, tag, TOPIC_SLOT_CTRL); 784 DPRINTF(("%s: topic slot ctrl reg 0x%x -> ", 785 sc->sc_dev.dv_xname, reg)); 786 reg |= (TOPIC_SLOT_CTRL_SLOTON | TOPIC_SLOT_CTRL_SLOTEN | 787 TOPIC_SLOT_CTRL_ID_LOCK | TOPIC_SLOT_CTRL_CARDBUS); 788 reg &= ~TOPIC_SLOT_CTRL_SWDETECT; 789 DPRINTF(("0x%x\n", reg)); 790 pci_conf_write(pc, tag, TOPIC_SLOT_CTRL, reg); 791 break; 792 793 case CB_TOPIC97: 794 reg = pci_conf_read(pc, tag, TOPIC_SLOT_CTRL); 795 DPRINTF(("%s: topic slot ctrl reg 0x%x -> ", 796 sc->sc_dev.dv_xname, reg)); 797 reg |= (TOPIC_SLOT_CTRL_SLOTON | TOPIC_SLOT_CTRL_SLOTEN | 798 TOPIC_SLOT_CTRL_ID_LOCK | TOPIC_SLOT_CTRL_CARDBUS); 799 reg &= ~TOPIC_SLOT_CTRL_SWDETECT; 800 reg |= TOPIC97_SLOT_CTRL_PCIINT; 801 reg &= ~(TOPIC97_SLOT_CTRL_STSIRQP | TOPIC97_SLOT_CTRL_IRQP); 802 DPRINTF(("0x%x\n", reg)); 803 pci_conf_write(pc, tag, TOPIC_SLOT_CTRL, reg); 804 805 /* make sure to assert LV card support bits */ 806 bus_space_write_1(sc->sc_base_memt, sc->sc_base_memh, 807 0x800 + 0x3e, bus_space_read_1(sc->sc_base_memt, 808 sc->sc_base_memh, 0x800 + 0x3e) | 0x03); 809 810 /* Power on the controller if the BIOS didn't */ 811 reg = pci_conf_read(pc, tag, TOPIC100_PMCSR); 812 if ((reg & TOPIC100_PMCSR_MASK) != TOPIC100_PMCSR_D0) 813 pci_conf_write(pc, tag, TOPIC100_PMCSR, 814 (reg & ~TOPIC100_PMCSR_MASK) | TOPIC100_PMCSR_D0); 815 break; 816 817 case CB_OLDO2MICRO: 818 /* 819 * older bridges have problems with both read prefetch and 820 * write bursting depending on the combination of the chipset, 821 * bridge and the cardbus card. so disable them to be on the 822 * safe side. One example is O2Micro 6812 with Atheros AR5012 823 * chipsets 824 */ 825 DPRINTF(("%s: old O2Micro bridge found\n", 826 sc->sc_dev.dv_xname, reg)); 827 reg = pci_conf_read(pc, tag, O2MICRO_RESERVED1); 828 pci_conf_write(pc, tag, O2MICRO_RESERVED1, reg & 829 ~(O2MICRO_RES_READ_PREFETCH | O2MICRO_RES_WRITE_BURST)); 830 reg = pci_conf_read(pc, tag, O2MICRO_RESERVED2); 831 pci_conf_write(pc, tag, O2MICRO_RESERVED2, reg & 832 ~(O2MICRO_RES_READ_PREFETCH | O2MICRO_RES_WRITE_BURST)); 833 break; 834 } 835 836 /* Close all memory and I/O windows. */ 837 pci_conf_write(pc, tag, PCI_CB_MEMBASE0, 0xffffffff); 838 pci_conf_write(pc, tag, PCI_CB_MEMLIMIT0, 0); 839 pci_conf_write(pc, tag, PCI_CB_MEMBASE1, 0xffffffff); 840 pci_conf_write(pc, tag, PCI_CB_MEMLIMIT1, 0); 841 pci_conf_write(pc, tag, PCI_CB_IOBASE0, 0xffffffff); 842 pci_conf_write(pc, tag, PCI_CB_IOLIMIT0, 0); 843 pci_conf_write(pc, tag, PCI_CB_IOBASE1, 0xffffffff); 844 pci_conf_write(pc, tag, PCI_CB_IOLIMIT1, 0); 845 846 /* reset 16-bit pcmcia bus */ 847 bus_space_write_1(sc->sc_base_memt, sc->sc_base_memh, 848 0x800 + PCIC_INTR, 849 bus_space_read_1(sc->sc_base_memt, sc->sc_base_memh, 850 0x800 + PCIC_INTR) & ~PCIC_INTR_RESET); 851 852 /* turn off power */ 853 pccbb_power((cardbus_chipset_tag_t)sc, CARDBUS_VCC_0V | CARDBUS_VPP_0V); 854 } 855 856 857 858 859 /* 860 * void pccbb_pcmcia_attach_setup(struct pccbb_softc *sc, 861 * struct pcmciabus_attach_args *paa) 862 * 863 * This function attaches 16-bit PCcard bus. 864 */ 865 void 866 pccbb_pcmcia_attach_setup(sc, paa) 867 struct pccbb_softc *sc; 868 struct pcmciabus_attach_args *paa; 869 { 870 struct pcic_handle *ph = &sc->sc_pcmcia_h; 871 rbus_tag_t rb; 872 873 /* initialize pcmcia part in pccbb_softc */ 874 ph->ph_parent = (struct device *)sc; 875 ph->sock = sc->sc_function; 876 ph->flags = 0; 877 ph->shutdown = 0; 878 ph->ih_irq = sc->sc_intrline; 879 ph->ph_bus_t = sc->sc_base_memt; 880 ph->ph_bus_h = sc->sc_base_memh; 881 ph->ph_read = pccbb_pcmcia_read; 882 ph->ph_write = pccbb_pcmcia_write; 883 sc->sc_pct = &pccbb_pcmcia_funcs; 884 885 /* 886 * We need to do a few things here: 887 * 1) Disable routing of CSC and functional interrupts to ISA IRQs by 888 * setting the IRQ numbers to 0. 889 * 2) Set bit 4 of PCIC_INTR, which is needed on some chips to enable 890 * routing of CSC interrupts (e.g. card removal) to PCI while in 891 * PCMCIA mode. We just leave this set all the time. 892 * 3) Enable card insertion/removal interrupts in case the chip also 893 * needs that while in PCMCIA mode. 894 * 4) Clear any pending CSC interrupt. 895 */ 896 Pcic_write(ph, PCIC_INTR, PCIC_INTR_ENABLE | PCIC_INTR_RESET); 897 if (sc->sc_chipset == CB_TI113X) { 898 Pcic_write(ph, PCIC_CSC_INTR, 0); 899 } else { 900 Pcic_write(ph, PCIC_CSC_INTR, PCIC_CSC_INTR_CD_ENABLE); 901 Pcic_read(ph, PCIC_CSC); 902 } 903 904 /* initialize pcmcia bus attachment */ 905 paa->paa_busname = "pcmcia"; 906 paa->pct = sc->sc_pct; 907 paa->pch = ph; 908 paa->iobase = 0; /* I don't use them */ 909 paa->iosize = 0; 910 rb = ((struct pccbb_softc *)(ph->ph_parent))->sc_rbus_iot; 911 paa->iobase = rb->rb_start + rb->rb_offset; 912 paa->iosize = rb->rb_end - rb->rb_start; 913 914 return; 915 } 916 917 #if 0 918 void 919 pccbb_pcmcia_attach_card(ph) 920 struct pcic_handle *ph; 921 { 922 if (ph->flags & PCIC_FLAG_CARDP) { 923 panic("pccbb_pcmcia_attach_card: already attached"); 924 } 925 926 /* call the MI attach function */ 927 pcmcia_card_attach(ph->pcmcia); 928 929 ph->flags |= PCIC_FLAG_CARDP; 930 } 931 932 void 933 pccbb_pcmcia_detach_card(ph, flags) 934 struct pcic_handle *ph; 935 int flags; 936 { 937 if (!(ph->flags & PCIC_FLAG_CARDP)) { 938 panic("pccbb_pcmcia_detach_card: already detached"); 939 } 940 941 ph->flags &= ~PCIC_FLAG_CARDP; 942 943 /* call the MI detach function */ 944 pcmcia_card_detach(ph->pcmcia, flags); 945 } 946 #endif 947 948 /* 949 * int pccbbintr(arg) 950 * void *arg; 951 * This routine handles the interrupt from Yenta PCI-CardBus bridge 952 * itself. 953 */ 954 int 955 pccbbintr(arg) 956 void *arg; 957 { 958 struct pccbb_softc *sc = (struct pccbb_softc *)arg; 959 u_int32_t sockevent, sockstate; 960 bus_space_tag_t memt = sc->sc_base_memt; 961 bus_space_handle_t memh = sc->sc_base_memh; 962 struct pcic_handle *ph = &sc->sc_pcmcia_h; 963 964 if (!sc->sc_ints_on) 965 return 0; 966 967 sockevent = bus_space_read_4(memt, memh, CB_SOCKET_EVENT); 968 bus_space_write_4(memt, memh, CB_SOCKET_EVENT, sockevent); 969 Pcic_read(ph, PCIC_CSC); 970 971 if (sockevent == 0) { 972 /* This intr is not for me: it may be for my child devices. */ 973 if (sc->sc_pil_intr_enable) { 974 return pccbbintr_function(sc); 975 } else { 976 return 0; 977 } 978 } 979 980 if (sockevent & CB_SOCKET_EVENT_CD) { 981 sockstate = bus_space_read_4(memt, memh, CB_SOCKET_STAT); 982 if ((sockstate & CB_SOCKET_STAT_CD) != 0) { 983 /* A card should be removed. */ 984 if (sc->sc_flags & CBB_CARDEXIST) { 985 DPRINTF(("%s: 0x%08x", sc->sc_dev.dv_xname, 986 sockevent)); 987 DPRINTF((" card removed, 0x%08x\n", sockstate)); 988 sc->sc_flags &= ~CBB_CARDEXIST; 989 if (sc->sc_csc->sc_status & 990 CARDSLOT_STATUS_CARD_16) { 991 #if 0 992 struct pcic_handle *ph = 993 &sc->sc_pcmcia_h; 994 995 pcmcia_card_deactivate(ph->pcmcia); 996 pccbb_pcmcia_socket_disable(ph); 997 pccbb_pcmcia_detach_card(ph, 998 DETACH_FORCE); 999 #endif 1000 cardslot_event_throw(sc->sc_csc, 1001 CARDSLOT_EVENT_REMOVAL_16); 1002 } else if (sc->sc_csc->sc_status & 1003 CARDSLOT_STATUS_CARD_CB) { 1004 /* Cardbus intr removed */ 1005 cardslot_event_throw(sc->sc_csc, 1006 CARDSLOT_EVENT_REMOVAL_CB); 1007 } 1008 } 1009 } else if ((sockstate & CB_SOCKET_STAT_CD) == 0 && 1010 /* 1011 * The pccbbintr may called from powerdown hook when 1012 * the system resumed, to detect the card 1013 * insertion/removal during suspension. 1014 */ 1015 (sc->sc_flags & CBB_CARDEXIST) == 0) { 1016 timeout_add(&sc->sc_ins_tmo, hz / 10); 1017 sc->sc_flags |= CBB_INSERTING; 1018 } 1019 return (1); 1020 } 1021 1022 return (0); 1023 } 1024 1025 /* 1026 * int pccbbintr_function(struct pccbb_softc *sc) 1027 * 1028 * This function calls each interrupt handler registered at the 1029 * bridge. The interrupt handlers are called in registered order. 1030 */ 1031 int 1032 pccbbintr_function(sc) 1033 struct pccbb_softc *sc; 1034 { 1035 int retval = 0, val; 1036 struct pccbb_intrhand_list *pil; 1037 int s, splchanged; 1038 1039 for (pil = sc->sc_pil; pil != NULL; pil = pil->pil_next) { 1040 /* 1041 * XXX priority change. gross. I use if-else 1042 * sentense instead of switch-case sentense because of 1043 * avoiding duplicate case value error. More than one 1044 * IPL_XXX use same value. It depends on 1045 * implementation. 1046 */ 1047 splchanged = 1; 1048 #if 0 1049 if (pil->pil_level == IPL_SERIAL) { 1050 s = splserial(); 1051 } else if (pil->pil_level == IPL_HIGH) { 1052 #endif 1053 if (pil->pil_level == IPL_HIGH) { 1054 s = splhigh(); 1055 } else if (pil->pil_level == IPL_CLOCK) { 1056 s = splclock(); 1057 } else if (pil->pil_level == IPL_AUDIO) { 1058 s = splaudio(); 1059 } else if (pil->pil_level == IPL_VM) { 1060 s = splvm(); 1061 } else if (pil->pil_level == IPL_TTY) { 1062 s = spltty(); 1063 #if 0 1064 } else if (pil->pil_level == IPL_SOFTSERIAL) { 1065 s = splsoftserial(); 1066 #endif 1067 } else if (pil->pil_level == IPL_NET) { 1068 s = splnet(); 1069 } else { 1070 splchanged = 0; 1071 /* XXX: ih lower than IPL_BIO runs w/ IPL_BIO. */ 1072 } 1073 1074 val = (*pil->pil_func)(pil->pil_arg); 1075 if (val != 0) 1076 pil->pil_count.ec_count++; 1077 1078 if (splchanged != 0) { 1079 splx(s); 1080 } 1081 1082 retval = retval == 1 ? 1 : 1083 retval == 0 ? val : val != 0 ? val : retval; 1084 } 1085 1086 return retval; 1087 } 1088 1089 void 1090 pci113x_insert(arg) 1091 void *arg; 1092 { 1093 struct pccbb_softc *sc = (struct pccbb_softc *)arg; 1094 u_int32_t sockevent, sockstate; 1095 1096 sockevent = bus_space_read_4(sc->sc_base_memt, sc->sc_base_memh, 1097 CB_SOCKET_EVENT); 1098 sockstate = bus_space_read_4(sc->sc_base_memt, sc->sc_base_memh, 1099 CB_SOCKET_STAT); 1100 1101 if (0 == (sockstate & CB_SOCKET_STAT_CD)) { /* card exist */ 1102 DPRINTF(("%s: 0x%08x", sc->sc_dev.dv_xname, sockevent)); 1103 DPRINTF((" card inserted, 0x%08x\n", sockstate)); 1104 sc->sc_flags |= CBB_CARDEXIST; 1105 /* call pccard interrupt handler here */ 1106 if (sockstate & CB_SOCKET_STAT_16BIT) { 1107 /* 16-bit card found */ 1108 /* pccbb_pcmcia_attach_card(&sc->sc_pcmcia_h); */ 1109 cardslot_event_throw(sc->sc_csc, 1110 CARDSLOT_EVENT_INSERTION_16); 1111 } else if (sockstate & CB_SOCKET_STAT_CB) { 1112 /* cardbus card found */ 1113 /* cardbus_attach_card(sc->sc_csc); */ 1114 cardslot_event_throw(sc->sc_csc, 1115 CARDSLOT_EVENT_INSERTION_CB); 1116 } else { 1117 /* who are you? */ 1118 } 1119 } else { 1120 timeout_add(&sc->sc_ins_tmo, hz / 10); 1121 } 1122 } 1123 1124 #define PCCBB_PCMCIA_OFFSET 0x800 1125 u_int8_t 1126 pccbb_pcmcia_read(ph, reg) 1127 struct pcic_handle *ph; 1128 int reg; 1129 { 1130 bus_space_barrier(ph->ph_bus_t, ph->ph_bus_h, 1131 PCCBB_PCMCIA_OFFSET + reg, 1, BUS_SPACE_BARRIER_READ); 1132 1133 return bus_space_read_1(ph->ph_bus_t, ph->ph_bus_h, 1134 PCCBB_PCMCIA_OFFSET + reg); 1135 } 1136 1137 void 1138 pccbb_pcmcia_write(ph, reg, val) 1139 struct pcic_handle *ph; 1140 int reg; 1141 u_int8_t val; 1142 { 1143 bus_space_barrier(ph->ph_bus_t, ph->ph_bus_h, 1144 PCCBB_PCMCIA_OFFSET + reg, 1, BUS_SPACE_BARRIER_WRITE); 1145 1146 bus_space_write_1(ph->ph_bus_t, ph->ph_bus_h, PCCBB_PCMCIA_OFFSET + reg, 1147 val); 1148 } 1149 1150 /* 1151 * int pccbb_ctrl(cardbus_chipset_tag_t, int) 1152 */ 1153 int 1154 pccbb_ctrl(ct, command) 1155 cardbus_chipset_tag_t ct; 1156 int command; 1157 { 1158 struct pccbb_softc *sc = (struct pccbb_softc *)ct; 1159 1160 switch (command) { 1161 case CARDBUS_CD: 1162 if (2 == pccbb_detect_card(sc)) { 1163 int retval = 0; 1164 int status = cb_detect_voltage(sc); 1165 if (PCCARD_VCC_5V & status) { 1166 retval |= CARDBUS_5V_CARD; 1167 } 1168 if (PCCARD_VCC_3V & status) { 1169 retval |= CARDBUS_3V_CARD; 1170 } 1171 if (PCCARD_VCC_XV & status) { 1172 retval |= CARDBUS_XV_CARD; 1173 } 1174 if (PCCARD_VCC_YV & status) { 1175 retval |= CARDBUS_YV_CARD; 1176 } 1177 return retval; 1178 } else { 1179 return 0; 1180 } 1181 break; 1182 case CARDBUS_RESET: 1183 return cb_reset(sc); 1184 break; 1185 case CARDBUS_IO_ENABLE: /* fallthrough */ 1186 case CARDBUS_IO_DISABLE: /* fallthrough */ 1187 case CARDBUS_MEM_ENABLE: /* fallthrough */ 1188 case CARDBUS_MEM_DISABLE: /* fallthrough */ 1189 case CARDBUS_BM_ENABLE: /* fallthrough */ 1190 case CARDBUS_BM_DISABLE: /* fallthrough */ 1191 return pccbb_cardenable(sc, command); 1192 break; 1193 } 1194 1195 return 0; 1196 } 1197 1198 /* 1199 * int pccbb_power(cardbus_chipset_tag_t, int) 1200 * This function returns true when it succeeds and returns false when 1201 * it fails. 1202 */ 1203 int 1204 pccbb_power(ct, command) 1205 cardbus_chipset_tag_t ct; 1206 int command; 1207 { 1208 struct pccbb_softc *sc = (struct pccbb_softc *)ct; 1209 1210 u_int32_t status, sock_ctrl; 1211 bus_space_tag_t memt = sc->sc_base_memt; 1212 bus_space_handle_t memh = sc->sc_base_memh; 1213 1214 DPRINTF(("pccbb_power: %s and %s [%x]\n", 1215 (command & CARDBUS_VCCMASK) == CARDBUS_VCC_UC ? "CARDBUS_VCC_UC" : 1216 (command & CARDBUS_VCCMASK) == CARDBUS_VCC_5V ? "CARDBUS_VCC_5V" : 1217 (command & CARDBUS_VCCMASK) == CARDBUS_VCC_3V ? "CARDBUS_VCC_3V" : 1218 (command & CARDBUS_VCCMASK) == CARDBUS_VCC_XV ? "CARDBUS_VCC_XV" : 1219 (command & CARDBUS_VCCMASK) == CARDBUS_VCC_YV ? "CARDBUS_VCC_YV" : 1220 (command & CARDBUS_VCCMASK) == CARDBUS_VCC_0V ? "CARDBUS_VCC_0V" : 1221 "UNKNOWN", 1222 (command & CARDBUS_VPPMASK) == CARDBUS_VPP_UC ? "CARDBUS_VPP_UC" : 1223 (command & CARDBUS_VPPMASK) == CARDBUS_VPP_12V ? "CARDBUS_VPP_12V" : 1224 (command & CARDBUS_VPPMASK) == CARDBUS_VPP_VCC ? "CARDBUS_VPP_VCC" : 1225 (command & CARDBUS_VPPMASK) == CARDBUS_VPP_0V ? "CARDBUS_VPP_0V" : 1226 "UNKNOWN", command)); 1227 1228 status = bus_space_read_4(memt, memh, CB_SOCKET_STAT); 1229 sock_ctrl = bus_space_read_4(memt, memh, CB_SOCKET_CTRL); 1230 1231 switch (command & CARDBUS_VCCMASK) { 1232 case CARDBUS_VCC_UC: 1233 break; 1234 case CARDBUS_VCC_5V: 1235 if (CB_SOCKET_STAT_5VCARD & status) { /* check 5 V card */ 1236 sock_ctrl &= ~CB_SOCKET_CTRL_VCCMASK; 1237 sock_ctrl |= CB_SOCKET_CTRL_VCC_5V; 1238 } else { 1239 printf("%s: BAD voltage request: no 5 V card\n", 1240 sc->sc_dev.dv_xname); 1241 } 1242 break; 1243 case CARDBUS_VCC_3V: 1244 if (CB_SOCKET_STAT_3VCARD & status) { 1245 sock_ctrl &= ~CB_SOCKET_CTRL_VCCMASK; 1246 sock_ctrl |= CB_SOCKET_CTRL_VCC_3V; 1247 } else { 1248 printf("%s: BAD voltage request: no 3.3 V card\n", 1249 sc->sc_dev.dv_xname); 1250 } 1251 break; 1252 case CARDBUS_VCC_0V: 1253 sock_ctrl &= ~CB_SOCKET_CTRL_VCCMASK; 1254 break; 1255 default: 1256 return 0; /* power NEVER changed */ 1257 break; 1258 } 1259 1260 switch (command & CARDBUS_VPPMASK) { 1261 case CARDBUS_VPP_UC: 1262 break; 1263 case CARDBUS_VPP_0V: 1264 sock_ctrl &= ~CB_SOCKET_CTRL_VPPMASK; 1265 break; 1266 case CARDBUS_VPP_VCC: 1267 sock_ctrl &= ~CB_SOCKET_CTRL_VPPMASK; 1268 sock_ctrl |= ((sock_ctrl >> 4) & 0x07); 1269 break; 1270 case CARDBUS_VPP_12V: 1271 sock_ctrl &= ~CB_SOCKET_CTRL_VPPMASK; 1272 sock_ctrl |= CB_SOCKET_CTRL_VPP_12V; 1273 break; 1274 } 1275 1276 #if 0 1277 DPRINTF(("sock_ctrl: %x\n", sock_ctrl)); 1278 #endif 1279 bus_space_write_4(memt, memh, CB_SOCKET_CTRL, sock_ctrl); 1280 status = bus_space_read_4(memt, memh, CB_SOCKET_STAT); 1281 1282 if (status & CB_SOCKET_STAT_BADVCC) { /* bad Vcc request */ 1283 printf 1284 ("%s: bad Vcc request. sock_ctrl 0x%x, sock_status 0x%x\n", 1285 sc->sc_dev.dv_xname, sock_ctrl, status); 1286 DPRINTF(("pccbb_power: %s and %s [%x]\n", 1287 (command & CARDBUS_VCCMASK) == 1288 CARDBUS_VCC_UC ? "CARDBUS_VCC_UC" : (command & 1289 CARDBUS_VCCMASK) == 1290 CARDBUS_VCC_5V ? "CARDBUS_VCC_5V" : (command & 1291 CARDBUS_VCCMASK) == 1292 CARDBUS_VCC_3V ? "CARDBUS_VCC_3V" : (command & 1293 CARDBUS_VCCMASK) == 1294 CARDBUS_VCC_XV ? "CARDBUS_VCC_XV" : (command & 1295 CARDBUS_VCCMASK) == 1296 CARDBUS_VCC_YV ? "CARDBUS_VCC_YV" : (command & 1297 CARDBUS_VCCMASK) == 1298 CARDBUS_VCC_0V ? "CARDBUS_VCC_0V" : "UNKNOWN", 1299 (command & CARDBUS_VPPMASK) == 1300 CARDBUS_VPP_UC ? "CARDBUS_VPP_UC" : (command & 1301 CARDBUS_VPPMASK) == 1302 CARDBUS_VPP_12V ? "CARDBUS_VPP_12V" : (command & 1303 CARDBUS_VPPMASK) == 1304 CARDBUS_VPP_VCC ? "CARDBUS_VPP_VCC" : (command & 1305 CARDBUS_VPPMASK) == 1306 CARDBUS_VPP_0V ? "CARDBUS_VPP_0V" : "UNKNOWN", command)); 1307 #if 0 1308 if (command == (CARDBUS_VCC_0V | CARDBUS_VPP_0V)) { 1309 u_int32_t force = 1310 bus_space_read_4(memt, memh, CB_SOCKET_FORCE); 1311 /* Reset Bad Vcc request */ 1312 force &= ~CB_SOCKET_FORCE_BADVCC; 1313 bus_space_write_4(memt, memh, CB_SOCKET_FORCE, force); 1314 printf("new status 0x%x\n", bus_space_read_4(memt, memh, 1315 CB_SOCKET_STAT)); 1316 return 1; 1317 } 1318 #endif 1319 return 0; 1320 } 1321 1322 /* 1323 * XXX delay 300 ms: though the standard defines that the Vcc set-up 1324 * time is 20 ms, some PC-Card bridge requires longer duration. 1325 */ 1326 delay(300 * 1000); 1327 1328 return 1; /* power changed correctly */ 1329 } 1330 1331 #if defined CB_PCMCIA_POLL 1332 struct cb_poll_str { 1333 void *arg; 1334 int (*func)(void *); 1335 int level; 1336 pccard_chipset_tag_t ct; 1337 int count; 1338 }; 1339 1340 static struct cb_poll_str cb_poll[10]; 1341 static int cb_poll_n = 0; 1342 static struct timeout cb_poll_timeout; 1343 1344 void cb_pcmcia_poll(void *arg); 1345 1346 void 1347 cb_pcmcia_poll(arg) 1348 void *arg; 1349 { 1350 struct cb_poll_str *poll = arg; 1351 struct cbb_pcmcia_softc *psc = (void *)poll->ct->v; 1352 struct pccbb_softc *sc = psc->cpc_parent; 1353 int s; 1354 u_int32_t spsr; /* socket present-state reg */ 1355 1356 timeout_set(&cb_poll_timeout, cb_pcmcia_poll, arg); 1357 timeout_add(&cb_poll_timeout, hz / 10); 1358 switch (poll->level) { 1359 case IPL_NET: 1360 s = splnet(); 1361 break; 1362 case IPL_BIO: 1363 s = splbio(); 1364 break; 1365 case IPL_TTY: /* fallthrough */ 1366 default: 1367 s = spltty(); 1368 break; 1369 } 1370 1371 spsr = 1372 bus_space_read_4(sc->sc_base_memt, sc->sc_base_memh, 1373 CB_SOCKET_STAT); 1374 1375 #if defined CB_PCMCIA_POLL_ONLY && defined LEVEL2 1376 if (!(spsr & 0x40)) { /* CINT low */ 1377 #else 1378 if (1) { 1379 #endif 1380 if ((*poll->func) (poll->arg) == 1) { 1381 ++poll->count; 1382 printf("intr: reported from poller, 0x%x\n", spsr); 1383 #if defined LEVEL2 1384 } else { 1385 printf("intr: miss! 0x%x\n", spsr); 1386 #endif 1387 } 1388 } 1389 splx(s); 1390 } 1391 #endif /* defined CB_PCMCIA_POLL */ 1392 1393 /* 1394 * int pccbb_detect_card(struct pccbb_softc *sc) 1395 * return value: 0 if no card exists. 1396 * 1 if 16-bit card exists. 1397 * 2 if cardbus card exists. 1398 */ 1399 int 1400 pccbb_detect_card(sc) 1401 struct pccbb_softc *sc; 1402 { 1403 bus_space_handle_t base_memh = sc->sc_base_memh; 1404 bus_space_tag_t base_memt = sc->sc_base_memt; 1405 u_int32_t sockstat = 1406 bus_space_read_4(base_memt, base_memh, CB_SOCKET_STAT); 1407 int retval = 0; 1408 1409 /* 1410 * The SCM Microsystems TI1225-based PCI-CardBus dock card that 1411 * ships with some Lucent WaveLAN cards has only one physical slot 1412 * but OpenBSD probes two. The phantom card in the second slot can 1413 * be ignored by punting on unsupported voltages. 1414 */ 1415 if (sockstat & CB_SOCKET_STAT_XVCARD) 1416 return 0; 1417 1418 /* CD1 and CD2 asserted */ 1419 if (0x00 == (sockstat & CB_SOCKET_STAT_CD)) { 1420 /* card must be present */ 1421 if (!(CB_SOCKET_STAT_NOTCARD & sockstat)) { 1422 /* NOTACARD DEASSERTED */ 1423 if (CB_SOCKET_STAT_CB & sockstat) { 1424 /* CardBus mode */ 1425 retval = 2; 1426 } else if (CB_SOCKET_STAT_16BIT & sockstat) { 1427 /* 16-bit mode */ 1428 retval = 1; 1429 } 1430 } 1431 } 1432 return retval; 1433 } 1434 1435 /* 1436 * int cb_reset(struct pccbb_softc *sc) 1437 * This function resets CardBus card. 1438 */ 1439 int 1440 cb_reset(sc) 1441 struct pccbb_softc *sc; 1442 { 1443 /* 1444 * Reset Assert at least 20 ms 1445 * Some machines request longer duration. 1446 */ 1447 int reset_duration = (sc->sc_chipset == CB_RX5C47X ? 400 : 50); 1448 u_int32_t bcr = pci_conf_read(sc->sc_pc, sc->sc_tag, PCI_BCR_INTR); 1449 1450 /* Reset bit Assert (bit 6 at 0x3E) */ 1451 bcr |= CB_BCR_RESET_ENABLE; 1452 pci_conf_write(sc->sc_pc, sc->sc_tag, PCI_BCR_INTR, bcr); 1453 delay_ms(reset_duration, sc); 1454 1455 if (CBB_CARDEXIST & sc->sc_flags) { /* A card exists. Reset it! */ 1456 /* Reset bit Deassert (bit 6 at 0x3E) */ 1457 bcr &= ~CB_BCR_RESET_ENABLE; 1458 pci_conf_write(sc->sc_pc, sc->sc_tag, PCI_BCR_INTR, bcr); 1459 delay_ms(reset_duration, sc); 1460 } 1461 /* No card found on the slot. Keep Reset. */ 1462 return 1; 1463 } 1464 1465 /* 1466 * int cb_detect_voltage(struct pccbb_softc *sc) 1467 * This function detect card Voltage. 1468 */ 1469 int 1470 cb_detect_voltage(sc) 1471 struct pccbb_softc *sc; 1472 { 1473 u_int32_t psr; /* socket present-state reg */ 1474 bus_space_tag_t iot = sc->sc_base_memt; 1475 bus_space_handle_t ioh = sc->sc_base_memh; 1476 int vol = PCCARD_VCC_UKN; /* set 0 */ 1477 1478 psr = bus_space_read_4(iot, ioh, CB_SOCKET_STAT); 1479 1480 if (0x400u & psr) { 1481 vol |= PCCARD_VCC_5V; 1482 } 1483 if (0x800u & psr) { 1484 vol |= PCCARD_VCC_3V; 1485 } 1486 1487 return vol; 1488 } 1489 1490 int 1491 cbbprint(aux, pcic) 1492 void *aux; 1493 const char *pcic; 1494 { 1495 /* 1496 struct cbslot_attach_args *cba = aux; 1497 1498 if (cba->cba_slot >= 0) { 1499 printf(" slot %d", cba->cba_slot); 1500 } 1501 */ 1502 return UNCONF; 1503 } 1504 1505 /* 1506 * int pccbb_cardenable(struct pccbb_softc *sc, int function) 1507 * This function enables and disables the card 1508 */ 1509 int 1510 pccbb_cardenable(sc, function) 1511 struct pccbb_softc *sc; 1512 int function; 1513 { 1514 u_int32_t command = 1515 pci_conf_read(sc->sc_pc, sc->sc_tag, PCI_COMMAND_STATUS_REG); 1516 1517 DPRINTF(("pccbb_cardenable:")); 1518 switch (function) { 1519 case CARDBUS_IO_ENABLE: 1520 command |= PCI_COMMAND_IO_ENABLE; 1521 break; 1522 case CARDBUS_IO_DISABLE: 1523 command &= ~PCI_COMMAND_IO_ENABLE; 1524 break; 1525 case CARDBUS_MEM_ENABLE: 1526 command |= PCI_COMMAND_MEM_ENABLE; 1527 break; 1528 case CARDBUS_MEM_DISABLE: 1529 command &= ~PCI_COMMAND_MEM_ENABLE; 1530 break; 1531 case CARDBUS_BM_ENABLE: 1532 command |= PCI_COMMAND_MASTER_ENABLE; 1533 break; 1534 case CARDBUS_BM_DISABLE: 1535 command &= ~PCI_COMMAND_MASTER_ENABLE; 1536 break; 1537 default: 1538 return 0; 1539 } 1540 1541 pci_conf_write(sc->sc_pc, sc->sc_tag, PCI_COMMAND_STATUS_REG, command); 1542 DPRINTF((" command reg 0x%x\n", command)); 1543 return 1; 1544 } 1545 1546 /* 1547 * void *pccbb_cb_intr_establish(cardbus_chipset_tag_t ct, 1548 * int irq, 1549 * int level, 1550 * int (* func)(void *), 1551 * void *arg, 1552 * const char *name) 1553 * 1554 * This function registers an interrupt handler at the bridge, in 1555 * order not to call the interrupt handlers of child devices when 1556 * a card-deletion interrupt occurs. 1557 * 1558 * The arguments irq is not used because pccbb selects intr vector. 1559 */ 1560 void * 1561 pccbb_cb_intr_establish(ct, irq, level, func, arg, name) 1562 cardbus_chipset_tag_t ct; 1563 int irq, level; 1564 int (*func)(void *); 1565 void *arg; 1566 const char *name; 1567 { 1568 struct pccbb_softc *sc = (struct pccbb_softc *)ct; 1569 1570 return pccbb_intr_establish(sc, irq, level, func, arg, name); 1571 } 1572 1573 1574 /* 1575 * void *pccbb_cb_intr_disestablish(cardbus_chipset_tag_t ct, 1576 * void *ih) 1577 * 1578 * This function removes an interrupt handler pointed by ih. 1579 */ 1580 void 1581 pccbb_cb_intr_disestablish(ct, ih) 1582 cardbus_chipset_tag_t ct; 1583 void *ih; 1584 { 1585 struct pccbb_softc *sc = (struct pccbb_softc *)ct; 1586 1587 pccbb_intr_disestablish(sc, ih); 1588 } 1589 1590 1591 /* 1592 * void *pccbb_intr_establish(struct pccbb_softc *sc, 1593 * int irq, 1594 * int level, 1595 * int (* func)(void *), 1596 * void *arg, 1597 * const char *name) 1598 * 1599 * This function registers an interrupt handler at the bridge, in 1600 * order not to call the interrupt handlers of child devices when 1601 * a card-deletion interrupt occurs. 1602 * 1603 * The arguments irq and level are not used. 1604 */ 1605 void * 1606 pccbb_intr_establish(sc, irq, level, func, arg, name) 1607 struct pccbb_softc *sc; 1608 int irq, level; 1609 int (*func)(void *); 1610 void *arg; 1611 const char *name; 1612 { 1613 struct pccbb_intrhand_list *pil, *newpil; 1614 pcireg_t reg; 1615 1616 DPRINTF(("pccbb_intr_establish start. %p\n", sc->sc_pil)); 1617 1618 if (sc->sc_pil == NULL) { 1619 /* initialize bridge intr routing */ 1620 reg = pci_conf_read(sc->sc_pc, sc->sc_tag, PCI_BCR_INTR); 1621 reg &= ~CB_BCR_INTR_IREQ_ENABLE; 1622 pci_conf_write(sc->sc_pc, sc->sc_tag, PCI_BCR_INTR, reg); 1623 1624 switch (sc->sc_chipset) { 1625 case CB_TI113X: 1626 reg = pci_conf_read(sc->sc_pc, sc->sc_tag, PCI_CBCTRL); 1627 /* functional intr enabled */ 1628 reg |= PCI113X_CBCTRL_PCI_INTR; 1629 pci_conf_write(sc->sc_pc, sc->sc_tag, PCI_CBCTRL, reg); 1630 break; 1631 default: 1632 break; 1633 } 1634 } 1635 1636 /* 1637 * Allocate a room for interrupt handler structure. 1638 */ 1639 newpil = (struct pccbb_intrhand_list *) 1640 malloc(sizeof(struct pccbb_intrhand_list), M_DEVBUF, M_WAITOK); 1641 1642 newpil->pil_func = func; 1643 newpil->pil_arg = arg; 1644 newpil->pil_level = level; 1645 evcount_attach(&newpil->pil_count, name, &sc->sc_intrline, 1646 &evcount_intr); 1647 newpil->pil_next = NULL; 1648 1649 if (sc->sc_pil == NULL) { 1650 sc->sc_pil = newpil; 1651 } else { 1652 for (pil = sc->sc_pil; pil->pil_next != NULL; 1653 pil = pil->pil_next); 1654 pil->pil_next = newpil; 1655 } 1656 1657 DPRINTF(("pccbb_intr_establish add pil. %p\n", sc->sc_pil)); 1658 1659 return newpil; 1660 } 1661 1662 /* 1663 * void *pccbb_intr_disestablish(struct pccbb_softc *sc, 1664 * void *ih) 1665 * 1666 * This function removes an interrupt handler pointed by ih. 1667 */ 1668 void 1669 pccbb_intr_disestablish(sc, ih) 1670 struct pccbb_softc *sc; 1671 void *ih; 1672 { 1673 struct pccbb_intrhand_list *pil, **pil_prev; 1674 pcireg_t reg; 1675 1676 DPRINTF(("pccbb_intr_disestablish start. %p\n", sc->sc_pil)); 1677 1678 pil_prev = &sc->sc_pil; 1679 1680 for (pil = sc->sc_pil; pil != NULL; pil = pil->pil_next) { 1681 if (pil == ih) { 1682 evcount_detach(&pil->pil_count); 1683 *pil_prev = pil->pil_next; 1684 free(pil, M_DEVBUF); 1685 DPRINTF(("pccbb_intr_disestablish frees one pil\n")); 1686 break; 1687 } 1688 pil_prev = &pil->pil_next; 1689 } 1690 1691 if (sc->sc_pil == NULL) { 1692 /* No interrupt handlers */ 1693 1694 DPRINTF(("pccbb_intr_disestablish: no interrupt handler\n")); 1695 1696 /* stop routing PCI intr */ 1697 reg = pci_conf_read(sc->sc_pc, sc->sc_tag, PCI_BCR_INTR); 1698 reg |= CB_BCR_INTR_IREQ_ENABLE; 1699 pci_conf_write(sc->sc_pc, sc->sc_tag, PCI_BCR_INTR, reg); 1700 1701 switch (sc->sc_chipset) { 1702 case CB_TI113X: 1703 reg = pci_conf_read(sc->sc_pc, sc->sc_tag, PCI_CBCTRL); 1704 /* functional intr disabled */ 1705 reg &= ~PCI113X_CBCTRL_PCI_INTR; 1706 pci_conf_write(sc->sc_pc, sc->sc_tag, PCI_CBCTRL, reg); 1707 break; 1708 default: 1709 break; 1710 } 1711 } 1712 } 1713 1714 #if defined SHOW_REGS 1715 void 1716 cb_show_regs(pc, tag, memt, memh) 1717 pci_chipset_tag_t pc; 1718 pcitag_t tag; 1719 bus_space_tag_t memt; 1720 bus_space_handle_t memh; 1721 { 1722 int i; 1723 printf("PCI config regs:"); 1724 for (i = 0; i < 0x50; i += 4) { 1725 if (i % 16 == 0) { 1726 printf("\n 0x%02x:", i); 1727 } 1728 printf(" %08x", pci_conf_read(pc, tag, i)); 1729 } 1730 for (i = 0x80; i < 0xb0; i += 4) { 1731 if (i % 16 == 0) { 1732 printf("\n 0x%02x:", i); 1733 } 1734 printf(" %08x", pci_conf_read(pc, tag, i)); 1735 } 1736 1737 if (memh == 0) { 1738 printf("\n"); 1739 return; 1740 } 1741 1742 printf("\nsocket regs:"); 1743 for (i = 0; i <= 0x10; i += 0x04) { 1744 printf(" %08x", bus_space_read_4(memt, memh, i)); 1745 } 1746 printf("\nExCA regs:"); 1747 for (i = 0; i < 0x08; ++i) { 1748 printf(" %02x", bus_space_read_1(memt, memh, 0x800 + i)); 1749 } 1750 printf("\n"); 1751 return; 1752 } 1753 #endif 1754 1755 /* 1756 * cardbustag_t pccbb_make_tag(cardbus_chipset_tag_t cc, 1757 * int busno, int devno, int function) 1758 * This is the function to make a tag to access config space of 1759 * a CardBus Card. It works same as pci_conf_read. 1760 */ 1761 cardbustag_t 1762 pccbb_make_tag(cc, busno, devno, function) 1763 cardbus_chipset_tag_t cc; 1764 int busno, devno, function; 1765 { 1766 struct pccbb_softc *sc = (struct pccbb_softc *)cc; 1767 1768 return pci_make_tag(sc->sc_pc, busno, devno, function); 1769 } 1770 1771 void 1772 pccbb_free_tag(cc, tag) 1773 cardbus_chipset_tag_t cc; 1774 cardbustag_t tag; 1775 { 1776 } 1777 1778 /* 1779 * cardbusreg_t pccbb_conf_read(cardbus_chipset_tag_t cc, 1780 * cardbustag_t tag, int offset) 1781 * This is the function to read the config space of a CardBus Card. 1782 * It works same as pci_conf_read. 1783 */ 1784 cardbusreg_t 1785 pccbb_conf_read(cc, tag, offset) 1786 cardbus_chipset_tag_t cc; 1787 cardbustag_t tag; 1788 int offset; /* register offset */ 1789 { 1790 struct pccbb_softc *sc = (struct pccbb_softc *)cc; 1791 1792 return pci_conf_read(sc->sc_pc, tag, offset); 1793 } 1794 1795 /* 1796 * void pccbb_conf_write(cardbus_chipset_tag_t cc, cardbustag_t tag, 1797 * int offs, cardbusreg_t val) 1798 * This is the function to write the config space of a CardBus Card. 1799 * It works same as pci_conf_write. 1800 */ 1801 void 1802 pccbb_conf_write(cc, tag, reg, val) 1803 cardbus_chipset_tag_t cc; 1804 cardbustag_t tag; 1805 int reg; /* register offset */ 1806 cardbusreg_t val; 1807 { 1808 struct pccbb_softc *sc = (struct pccbb_softc *)cc; 1809 1810 pci_conf_write(sc->sc_pc, tag, reg, val); 1811 } 1812 1813 #if 0 1814 int 1815 pccbb_new_pcmcia_io_alloc(pcmcia_chipset_handle_t pch, 1816 bus_addr_t start, bus_size_t size, bus_size_t align, bus_addr_t mask, 1817 int speed, int flags, 1818 bus_space_handle_t * iohp) 1819 #endif 1820 /* 1821 * int pccbb_pcmcia_io_alloc(pcmcia_chipset_handle_t pch, 1822 * bus_addr_t start, bus_size_t size, 1823 * bus_size_t align, 1824 * struct pcmcia_io_handle *pcihp 1825 * 1826 * This function only allocates I/O region for pccard. This function 1827 * never maps the allocated region to pccard I/O area. 1828 * 1829 * XXX: The interface of this function is not very good, I believe. 1830 */ 1831 int 1832 pccbb_pcmcia_io_alloc(pch, start, size, align, pcihp) 1833 pcmcia_chipset_handle_t pch; 1834 bus_addr_t start; /* start address */ 1835 bus_size_t size; 1836 bus_size_t align; 1837 struct pcmcia_io_handle *pcihp; 1838 { 1839 struct pcic_handle *ph = (struct pcic_handle *)pch; 1840 bus_addr_t ioaddr; 1841 int flags = 0; 1842 bus_space_tag_t iot; 1843 bus_space_handle_t ioh; 1844 bus_addr_t mask; 1845 rbus_tag_t rb; 1846 1847 if (align == 0) { 1848 align = size; /* XXX: funny??? */ 1849 } 1850 1851 if (start != 0) { 1852 /* XXX: assume all card decode lower 10 bits by its hardware */ 1853 mask = 0x3ff; 1854 /* enforce to use only masked address */ 1855 start &= mask; 1856 } else { 1857 /* 1858 * calculate mask: 1859 * 1. get the most significant bit of size (call it msb). 1860 * 2. compare msb with the value of size. 1861 * 3. if size is larger, shift msb left once. 1862 * 4. obtain mask value to decrement msb. 1863 */ 1864 bus_size_t size_tmp = size; 1865 int shifts = 0; 1866 1867 while (size_tmp) { 1868 ++shifts; 1869 size_tmp >>= 1; 1870 } 1871 mask = (1 << shifts); 1872 if (mask < size) { 1873 mask <<= 1; 1874 } 1875 mask--; 1876 } 1877 1878 /* 1879 * Allocate some arbitrary I/O space. 1880 */ 1881 1882 iot = ((struct pccbb_softc *)(ph->ph_parent))->sc_iot; 1883 1884 rb = ((struct pccbb_softc *)(ph->ph_parent))->sc_rbus_iot; 1885 if (rbus_space_alloc(rb, start, size, mask, align, 0, &ioaddr, &ioh)) { 1886 return 1; 1887 } 1888 1889 pcihp->iot = iot; 1890 pcihp->ioh = ioh; 1891 pcihp->addr = ioaddr; 1892 pcihp->size = size; 1893 pcihp->flags = flags; 1894 1895 return 0; 1896 } 1897 1898 /* 1899 * int pccbb_pcmcia_io_free(pcmcia_chipset_handle_t pch, 1900 * struct pcmcia_io_handle *pcihp) 1901 * 1902 * This function only frees I/O region for pccard. 1903 * 1904 * XXX: The interface of this function is not very good, I believe. 1905 */ 1906 void 1907 pccbb_pcmcia_io_free(pch, pcihp) 1908 pcmcia_chipset_handle_t pch; 1909 struct pcmcia_io_handle *pcihp; 1910 { 1911 bus_space_handle_t ioh = pcihp->ioh; 1912 bus_size_t size = pcihp->size; 1913 1914 struct pccbb_softc *sc = 1915 (struct pccbb_softc *)((struct pcic_handle *)pch)->ph_parent; 1916 rbus_tag_t rb = sc->sc_rbus_iot; 1917 1918 rbus_space_free(rb, ioh, size, NULL); 1919 } 1920 1921 /* 1922 * int pccbb_pcmcia_io_map(pcmcia_chipset_handle_t pch, int width, 1923 * bus_addr_t offset, bus_size_t size, 1924 * struct pcmcia_io_handle *pcihp, 1925 * int *windowp) 1926 * 1927 * This function maps the allocated I/O region to pccard. This function 1928 * never allocates any I/O region for pccard I/O area. I don't 1929 * understand why the original authors of pcmciabus separated alloc and 1930 * map. I believe the two must be unite. 1931 * 1932 * XXX: no wait timing control? 1933 */ 1934 int 1935 pccbb_pcmcia_io_map(pch, width, offset, size, pcihp, windowp) 1936 pcmcia_chipset_handle_t pch; 1937 int width; 1938 bus_addr_t offset; 1939 bus_size_t size; 1940 struct pcmcia_io_handle *pcihp; 1941 int *windowp; 1942 { 1943 struct pcic_handle *ph = (struct pcic_handle *)pch; 1944 bus_addr_t ioaddr = pcihp->addr + offset; 1945 int i, win; 1946 #if defined CBB_DEBUG 1947 static char *width_names[] = { "dynamic", "io8", "io16" }; 1948 #endif 1949 1950 /* Sanity check I/O handle. */ 1951 1952 if (((struct pccbb_softc *)ph->ph_parent)->sc_iot != pcihp->iot) { 1953 panic("pccbb_pcmcia_io_map iot is bogus"); 1954 } 1955 1956 /* XXX Sanity check offset/size. */ 1957 1958 win = -1; 1959 for (i = 0; i < PCIC_IO_WINS; i++) { 1960 if ((ph->ioalloc & (1 << i)) == 0) { 1961 win = i; 1962 ph->ioalloc |= (1 << i); 1963 break; 1964 } 1965 } 1966 1967 if (win == -1) { 1968 return 1; 1969 } 1970 1971 *windowp = win; 1972 1973 /* XXX this is pretty gross */ 1974 1975 DPRINTF(("pccbb_pcmcia_io_map window %d %s port %lx+%lx\n", 1976 win, width_names[width], (u_long) ioaddr, (u_long) size)); 1977 1978 /* XXX wtf is this doing here? */ 1979 1980 #if 0 1981 printf(" port 0x%lx", (u_long) ioaddr); 1982 if (size > 1) { 1983 printf("-0x%lx", (u_long) ioaddr + (u_long) size - 1); 1984 } 1985 #endif 1986 1987 ph->io[win].addr = ioaddr; 1988 ph->io[win].size = size; 1989 ph->io[win].width = width; 1990 1991 /* actual dirty register-value changing in the function below. */ 1992 pccbb_pcmcia_do_io_map(ph, win); 1993 1994 return 0; 1995 } 1996 1997 /* 1998 * void pccbb_pcmcia_do_io_map(struct pcic_handle *h, int win) 1999 * 2000 * This function changes register-value to map I/O region for pccard. 2001 */ 2002 void 2003 pccbb_pcmcia_do_io_map(ph, win) 2004 struct pcic_handle *ph; 2005 int win; 2006 { 2007 static u_int8_t pcic_iowidth[3] = { 2008 PCIC_IOCTL_IO0_IOCS16SRC_CARD, 2009 PCIC_IOCTL_IO0_IOCS16SRC_DATASIZE | 2010 PCIC_IOCTL_IO0_DATASIZE_8BIT, 2011 PCIC_IOCTL_IO0_IOCS16SRC_DATASIZE | 2012 PCIC_IOCTL_IO0_DATASIZE_16BIT, 2013 }; 2014 2015 #define PCIC_SIA_START_LOW 0 2016 #define PCIC_SIA_START_HIGH 1 2017 #define PCIC_SIA_STOP_LOW 2 2018 #define PCIC_SIA_STOP_HIGH 3 2019 2020 int regbase_win = 0x8 + win * 0x04; 2021 u_int8_t ioctl, enable; 2022 2023 DPRINTF( 2024 ("pccbb_pcmcia_do_io_map win %d addr 0x%lx size 0x%lx width %d\n", 2025 win, (long)ph->io[win].addr, (long)ph->io[win].size, 2026 ph->io[win].width * 8)); 2027 2028 Pcic_write(ph, regbase_win + PCIC_SIA_START_LOW, 2029 ph->io[win].addr & 0xff); 2030 Pcic_write(ph, regbase_win + PCIC_SIA_START_HIGH, 2031 (ph->io[win].addr >> 8) & 0xff); 2032 2033 Pcic_write(ph, regbase_win + PCIC_SIA_STOP_LOW, 2034 (ph->io[win].addr + ph->io[win].size - 1) & 0xff); 2035 Pcic_write(ph, regbase_win + PCIC_SIA_STOP_HIGH, 2036 ((ph->io[win].addr + ph->io[win].size - 1) >> 8) & 0xff); 2037 2038 ioctl = Pcic_read(ph, PCIC_IOCTL); 2039 enable = Pcic_read(ph, PCIC_ADDRWIN_ENABLE); 2040 switch (win) { 2041 case 0: 2042 ioctl &= ~(PCIC_IOCTL_IO0_WAITSTATE | PCIC_IOCTL_IO0_ZEROWAIT | 2043 PCIC_IOCTL_IO0_IOCS16SRC_MASK | 2044 PCIC_IOCTL_IO0_DATASIZE_MASK); 2045 ioctl |= pcic_iowidth[ph->io[win].width]; 2046 enable |= PCIC_ADDRWIN_ENABLE_IO0; 2047 break; 2048 case 1: 2049 ioctl &= ~(PCIC_IOCTL_IO1_WAITSTATE | PCIC_IOCTL_IO1_ZEROWAIT | 2050 PCIC_IOCTL_IO1_IOCS16SRC_MASK | 2051 PCIC_IOCTL_IO1_DATASIZE_MASK); 2052 ioctl |= (pcic_iowidth[ph->io[win].width] << 4); 2053 enable |= PCIC_ADDRWIN_ENABLE_IO1; 2054 break; 2055 } 2056 Pcic_write(ph, PCIC_IOCTL, ioctl); 2057 Pcic_write(ph, PCIC_ADDRWIN_ENABLE, enable); 2058 #if defined CBB_DEBUG 2059 { 2060 u_int8_t start_low = 2061 Pcic_read(ph, regbase_win + PCIC_SIA_START_LOW); 2062 u_int8_t start_high = 2063 Pcic_read(ph, regbase_win + PCIC_SIA_START_HIGH); 2064 u_int8_t stop_low = 2065 Pcic_read(ph, regbase_win + PCIC_SIA_STOP_LOW); 2066 u_int8_t stop_high = 2067 Pcic_read(ph, regbase_win + PCIC_SIA_STOP_HIGH); 2068 printf 2069 (" start %02x %02x, stop %02x %02x, ioctl %02x enable %02x\n", 2070 start_low, start_high, stop_low, stop_high, ioctl, enable); 2071 } 2072 #endif 2073 } 2074 2075 /* 2076 * void pccbb_pcmcia_io_unmap(pcmcia_chipset_handle_t *h, int win) 2077 * 2078 * This function unmaps I/O region. No return value. 2079 */ 2080 void 2081 pccbb_pcmcia_io_unmap(pch, win) 2082 pcmcia_chipset_handle_t pch; 2083 int win; 2084 { 2085 struct pcic_handle *ph = (struct pcic_handle *)pch; 2086 int reg; 2087 2088 if (win >= PCIC_IO_WINS || win < 0) { 2089 panic("pccbb_pcmcia_io_unmap: window out of range"); 2090 } 2091 2092 reg = Pcic_read(ph, PCIC_ADDRWIN_ENABLE); 2093 switch (win) { 2094 case 0: 2095 reg &= ~PCIC_ADDRWIN_ENABLE_IO0; 2096 break; 2097 case 1: 2098 reg &= ~PCIC_ADDRWIN_ENABLE_IO1; 2099 break; 2100 } 2101 Pcic_write(ph, PCIC_ADDRWIN_ENABLE, reg); 2102 2103 ph->ioalloc &= ~(1 << win); 2104 } 2105 2106 /* 2107 * void pccbb_pcmcia_wait_ready(struct pcic_handle *ph) 2108 * 2109 * This function enables the card. All information is stored in 2110 * the first argument, pcmcia_chipset_handle_t. 2111 */ 2112 void 2113 pccbb_pcmcia_wait_ready(ph) 2114 struct pcic_handle *ph; 2115 { 2116 int i; 2117 2118 DPRINTF(("pccbb_pcmcia_wait_ready: status 0x%02x\n", 2119 Pcic_read(ph, PCIC_IF_STATUS))); 2120 2121 for (i = 0; i < 10000; i++) { 2122 if (Pcic_read(ph, PCIC_IF_STATUS) & PCIC_IF_STATUS_READY) { 2123 return; 2124 } 2125 delay(500); 2126 #ifdef CBB_DEBUG 2127 if ((i > 5000) && (i % 100 == 99)) 2128 printf("."); 2129 #endif 2130 } 2131 2132 #ifdef DIAGNOSTIC 2133 printf("pcic_wait_ready: ready never happened, status = %02x\n", 2134 Pcic_read(ph, PCIC_IF_STATUS)); 2135 #endif 2136 } 2137 2138 /* 2139 * void pccbb_pcmcia_socket_enable(pcmcia_chipset_handle_t pch) 2140 * 2141 * This function enables the card. All information is stored in 2142 * the first argument, pcmcia_chipset_handle_t. 2143 */ 2144 void 2145 pccbb_pcmcia_socket_enable(pch) 2146 pcmcia_chipset_handle_t pch; 2147 { 2148 struct pcic_handle *ph = (struct pcic_handle *)pch; 2149 struct pccbb_softc *sc = (struct pccbb_softc *)ph->ph_parent; 2150 int cardtype, win; 2151 u_int8_t power, intr; 2152 pcireg_t spsr; 2153 int voltage; 2154 2155 /* this bit is mostly stolen from pcic_attach_card */ 2156 2157 DPRINTF(("pccbb_pcmcia_socket_enable: ")); 2158 2159 /* get card Vcc info */ 2160 2161 spsr = 2162 bus_space_read_4(sc->sc_base_memt, sc->sc_base_memh, 2163 CB_SOCKET_STAT); 2164 if (spsr & CB_SOCKET_STAT_5VCARD) { 2165 DPRINTF(("5V card\n")); 2166 voltage = CARDBUS_VCC_5V | CARDBUS_VPP_VCC; 2167 } else if (spsr & CB_SOCKET_STAT_3VCARD) { 2168 DPRINTF(("3V card\n")); 2169 voltage = CARDBUS_VCC_3V | CARDBUS_VPP_VCC; 2170 } else { 2171 DPRINTF(("?V card, 0x%x\n", spsr)); /* XXX */ 2172 return; 2173 } 2174 2175 /* disable socket i/o: negate output enable bit */ 2176 2177 power = 0; 2178 Pcic_write(ph, PCIC_PWRCTL, power); 2179 2180 /* power down the socket to reset it, clear the card reset pin */ 2181 2182 pccbb_power(sc, CARDBUS_VCC_0V | CARDBUS_VPP_0V); 2183 2184 /* 2185 * wait 200ms until power fails (Tpf). Then, wait 100ms since 2186 * we are changing Vcc (Toff). 2187 */ 2188 /* delay(300*1000); too much */ 2189 2190 /* assert reset bit */ 2191 intr = Pcic_read(ph, PCIC_INTR); 2192 intr &= ~(PCIC_INTR_RESET | PCIC_INTR_CARDTYPE_MASK); 2193 Pcic_write(ph, PCIC_INTR, intr); 2194 2195 /* Power up the socket. */ 2196 power = Pcic_read(ph, PCIC_PWRCTL); 2197 Pcic_write(ph, PCIC_PWRCTL, (power & ~PCIC_PWRCTL_OE)); 2198 pccbb_power(sc, voltage); 2199 2200 /* Now output enable */ 2201 power = Pcic_read(ph, PCIC_PWRCTL); 2202 Pcic_write(ph, PCIC_PWRCTL, power | PCIC_PWRCTL_OE); 2203 2204 /* 2205 * hold RESET at least 10us. 2206 */ 2207 delay(10); 2208 delay(2 * 1000); /* XXX: TI1130 requires it. */ 2209 delay(20 * 1000); /* XXX: TI1130 requires it. */ 2210 2211 /* clear the reset flag */ 2212 2213 intr |= PCIC_INTR_RESET; 2214 Pcic_write(ph, PCIC_INTR, intr); 2215 2216 /* wait 20ms as per pc card standard (r2.01) section 4.3.6 */ 2217 2218 delay(20000); 2219 2220 /* wait for the chip to finish initializing */ 2221 2222 pccbb_pcmcia_wait_ready(ph); 2223 2224 /* zero out the address windows */ 2225 2226 Pcic_write(ph, PCIC_ADDRWIN_ENABLE, 0); 2227 2228 /* set the card type */ 2229 2230 cardtype = pcmcia_card_gettype(ph->pcmcia); 2231 2232 intr |= ((cardtype == PCMCIA_IFTYPE_IO) ? 2233 PCIC_INTR_CARDTYPE_IO : PCIC_INTR_CARDTYPE_MEM); 2234 Pcic_write(ph, PCIC_INTR, intr); 2235 2236 DPRINTF(("%s: pccbb_pcmcia_socket_enable %02x cardtype %s %02x\n", 2237 ph->ph_parent->dv_xname, ph->sock, 2238 ((cardtype == PCMCIA_IFTYPE_IO) ? "io" : "mem"), intr)); 2239 2240 /* reinstall all the memory and io mappings */ 2241 2242 for (win = 0; win < PCIC_MEM_WINS; ++win) { 2243 if (ph->memalloc & (1 << win)) { 2244 pccbb_pcmcia_do_mem_map(ph, win); 2245 } 2246 } 2247 2248 for (win = 0; win < PCIC_IO_WINS; ++win) { 2249 if (ph->ioalloc & (1 << win)) { 2250 pccbb_pcmcia_do_io_map(ph, win); 2251 } 2252 } 2253 } 2254 2255 /* 2256 * void pccbb_pcmcia_socket_disable(pcmcia_chipset_handle_t *ph) 2257 * 2258 * This function disables the card. All information is stored in 2259 * the first argument, pcmcia_chipset_handle_t. 2260 */ 2261 void 2262 pccbb_pcmcia_socket_disable(pch) 2263 pcmcia_chipset_handle_t pch; 2264 { 2265 struct pcic_handle *ph = (struct pcic_handle *)pch; 2266 struct pccbb_softc *sc = (struct pccbb_softc *)ph->ph_parent; 2267 u_int8_t power, intr; 2268 2269 DPRINTF(("pccbb_pcmcia_socket_disable\n")); 2270 2271 /* reset signal asserting... */ 2272 2273 intr = Pcic_read(ph, PCIC_INTR); 2274 intr &= ~(PCIC_INTR_CARDTYPE_MASK); 2275 Pcic_write(ph, PCIC_INTR, intr); 2276 delay(2 * 1000); 2277 2278 /* power down the socket */ 2279 power = Pcic_read(ph, PCIC_PWRCTL); 2280 power &= ~PCIC_PWRCTL_OE; 2281 Pcic_write(ph, PCIC_PWRCTL, power); 2282 pccbb_power(sc, CARDBUS_VCC_0V | CARDBUS_VPP_0V); 2283 /* 2284 * wait 300ms until power fails (Tpf). 2285 */ 2286 delay(300 * 1000); 2287 } 2288 2289 /* 2290 * int pccbb_pcmcia_card_detect(pcmcia_chipset_handle_t *ph) 2291 * 2292 * This function detects whether a card is in the slot or not. 2293 * If a card is inserted, return 1. Otherwise, return 0. 2294 */ 2295 int 2296 pccbb_pcmcia_card_detect(pch) 2297 pcmcia_chipset_handle_t pch; 2298 { 2299 struct pcic_handle *ph = (struct pcic_handle *)pch; 2300 struct pccbb_softc *sc = (struct pccbb_softc *)ph->ph_parent; 2301 2302 DPRINTF(("pccbb_pcmcia_card_detect\n")); 2303 return pccbb_detect_card(sc) == 1 ? 1 : 0; 2304 } 2305 2306 #if 0 2307 int 2308 pccbb_new_pcmcia_mem_alloc(pcmcia_chipset_handle_t pch, 2309 bus_addr_t start, bus_size_t size, bus_size_t align, int speed, int flags, 2310 bus_space_tag_t * memtp bus_space_handle_t * memhp) 2311 #endif 2312 /* 2313 * int pccbb_pcmcia_mem_alloc(pcmcia_chipset_handle_t pch, 2314 * bus_size_t size, 2315 * struct pcmcia_mem_handle *pcmhp) 2316 * 2317 * This function only allocates memory region for pccard. This 2318 * function never maps the allocated region to pccard memory area. 2319 * 2320 * XXX: Why the argument of start address is not in? 2321 */ 2322 int 2323 pccbb_pcmcia_mem_alloc(pch, size, pcmhp) 2324 pcmcia_chipset_handle_t pch; 2325 bus_size_t size; 2326 struct pcmcia_mem_handle *pcmhp; 2327 { 2328 struct pcic_handle *ph = (struct pcic_handle *)pch; 2329 bus_space_handle_t memh; 2330 bus_addr_t addr; 2331 bus_size_t sizepg; 2332 struct pccbb_softc *sc = (struct pccbb_softc *)ph->ph_parent; 2333 rbus_tag_t rb; 2334 2335 /* out of sc->memh, allocate as many pages as necessary */ 2336 2337 /* convert size to PCIC pages */ 2338 /* 2339 * This is not enough; when the requested region is on the page 2340 * boundaries, this may calculate wrong result. 2341 */ 2342 sizepg = (size + (PCIC_MEM_PAGESIZE - 1)) / PCIC_MEM_PAGESIZE; 2343 #if 0 2344 if (sizepg > PCIC_MAX_MEM_PAGES) { 2345 return 1; 2346 } 2347 #endif 2348 2349 if (!(sc->sc_pcmcia_flags & PCCBB_PCMCIA_MEM_32)) { 2350 return 1; 2351 } 2352 2353 addr = 0; /* XXX gcc -Wuninitialized */ 2354 2355 rb = sc->sc_rbus_memt; 2356 if (rbus_space_alloc(rb, 0, sizepg * PCIC_MEM_PAGESIZE, 2357 sizepg * PCIC_MEM_PAGESIZE - 1, PCIC_MEM_PAGESIZE, 0, 2358 &addr, &memh)) { 2359 return 1; 2360 } 2361 2362 DPRINTF( 2363 ("pccbb_pcmcia_alloc_mem: addr 0x%lx size 0x%lx, realsize 0x%lx\n", 2364 addr, size, sizepg * PCIC_MEM_PAGESIZE)); 2365 2366 pcmhp->memt = sc->sc_memt; 2367 pcmhp->memh = memh; 2368 pcmhp->addr = addr; 2369 pcmhp->size = size; 2370 pcmhp->realsize = sizepg * PCIC_MEM_PAGESIZE; 2371 /* What is mhandle? I feel it is very dirty and it must go trush. */ 2372 pcmhp->mhandle = 0; 2373 /* No offset??? Funny. */ 2374 2375 return 0; 2376 } 2377 2378 /* 2379 * void pccbb_pcmcia_mem_free(pcmcia_chipset_handle_t pch, 2380 * struct pcmcia_mem_handle *pcmhp) 2381 * 2382 * This function release the memory space allocated by the function 2383 * pccbb_pcmcia_mem_alloc(). 2384 */ 2385 void 2386 pccbb_pcmcia_mem_free(pch, pcmhp) 2387 pcmcia_chipset_handle_t pch; 2388 struct pcmcia_mem_handle *pcmhp; 2389 { 2390 struct pcic_handle *ph = (struct pcic_handle *)pch; 2391 struct pccbb_softc *sc = (struct pccbb_softc *)ph->ph_parent; 2392 2393 rbus_space_free(sc->sc_rbus_memt, pcmhp->memh, pcmhp->realsize, NULL); 2394 } 2395 2396 /* 2397 * void pccbb_pcmcia_do_mem_map(struct pcic_handle *ph, int win) 2398 * 2399 * This function release the memory space allocated by the function 2400 * pccbb_pcmcia_mem_alloc(). 2401 */ 2402 void 2403 pccbb_pcmcia_do_mem_map(ph, win) 2404 struct pcic_handle *ph; 2405 int win; 2406 { 2407 int regbase_win; 2408 bus_addr_t phys_addr; 2409 bus_addr_t phys_end; 2410 2411 #define PCIC_SMM_START_LOW 0 2412 #define PCIC_SMM_START_HIGH 1 2413 #define PCIC_SMM_STOP_LOW 2 2414 #define PCIC_SMM_STOP_HIGH 3 2415 #define PCIC_CMA_LOW 4 2416 #define PCIC_CMA_HIGH 5 2417 2418 u_int8_t start_low, start_high = 0; 2419 u_int8_t stop_low, stop_high; 2420 u_int8_t off_low, off_high; 2421 u_int8_t mem_window; 2422 int reg; 2423 2424 regbase_win = 0x10 + win * 0x08; 2425 2426 phys_addr = ph->mem[win].addr; 2427 phys_end = phys_addr + ph->mem[win].size; 2428 2429 DPRINTF(("pccbb_pcmcia_do_mem_map: start 0x%lx end 0x%lx off 0x%lx\n", 2430 phys_addr, phys_end, ph->mem[win].offset)); 2431 2432 #define PCIC_MEMREG_LSB_SHIFT PCIC_SYSMEM_ADDRX_SHIFT 2433 #define PCIC_MEMREG_MSB_SHIFT (PCIC_SYSMEM_ADDRX_SHIFT + 8) 2434 #define PCIC_MEMREG_WIN_SHIFT (PCIC_SYSMEM_ADDRX_SHIFT + 12) 2435 2436 /* bit 19:12 */ 2437 start_low = (phys_addr >> PCIC_MEMREG_LSB_SHIFT) & 0xff; 2438 /* bit 23:20 and bit 7 on */ 2439 start_high = ((phys_addr >> PCIC_MEMREG_MSB_SHIFT) & 0x0f) 2440 | PCIC_SYSMEM_ADDRX_START_MSB_DATASIZE_16BIT; /* bit 7 on */ 2441 /* bit 31:24, for 32-bit address */ 2442 mem_window = (phys_addr >> PCIC_MEMREG_WIN_SHIFT) & 0xff; 2443 2444 Pcic_write(ph, regbase_win + PCIC_SMM_START_LOW, start_low); 2445 Pcic_write(ph, regbase_win + PCIC_SMM_START_HIGH, start_high); 2446 2447 if (((struct pccbb_softc *)ph-> 2448 ph_parent)->sc_pcmcia_flags & PCCBB_PCMCIA_MEM_32) { 2449 Pcic_write(ph, 0x40 + win, mem_window); 2450 } 2451 2452 stop_low = (phys_end >> PCIC_MEMREG_LSB_SHIFT) & 0xff; 2453 stop_high = ((phys_end >> PCIC_MEMREG_MSB_SHIFT) & 0x0f) 2454 | PCIC_SYSMEM_ADDRX_STOP_MSB_WAIT2; /* wait 2 cycles */ 2455 /* XXX Geee, WAIT2!! Crazy!! I must rewrite this routine. */ 2456 2457 Pcic_write(ph, regbase_win + PCIC_SMM_STOP_LOW, stop_low); 2458 Pcic_write(ph, regbase_win + PCIC_SMM_STOP_HIGH, stop_high); 2459 2460 off_low = (ph->mem[win].offset >> PCIC_CARDMEM_ADDRX_SHIFT) & 0xff; 2461 off_high = ((ph->mem[win].offset >> (PCIC_CARDMEM_ADDRX_SHIFT + 8)) 2462 & PCIC_CARDMEM_ADDRX_MSB_ADDR_MASK) 2463 | ((ph->mem[win].kind == PCMCIA_MEM_ATTR) ? 2464 PCIC_CARDMEM_ADDRX_MSB_REGACTIVE_ATTR : 0); 2465 2466 Pcic_write(ph, regbase_win + PCIC_CMA_LOW, off_low); 2467 Pcic_write(ph, regbase_win + PCIC_CMA_HIGH, off_high); 2468 2469 reg = Pcic_read(ph, PCIC_ADDRWIN_ENABLE); 2470 reg |= ((1 << win) | PCIC_ADDRWIN_ENABLE_MEMCS16); 2471 Pcic_write(ph, PCIC_ADDRWIN_ENABLE, reg); 2472 2473 #if defined CBB_DEBUG 2474 { 2475 int r1, r2, r3, r4, r5, r6, r7 = 0; 2476 2477 r1 = Pcic_read(ph, regbase_win + PCIC_SMM_START_LOW); 2478 r2 = Pcic_read(ph, regbase_win + PCIC_SMM_START_HIGH); 2479 r3 = Pcic_read(ph, regbase_win + PCIC_SMM_STOP_LOW); 2480 r4 = Pcic_read(ph, regbase_win + PCIC_SMM_STOP_HIGH); 2481 r5 = Pcic_read(ph, regbase_win + PCIC_CMA_LOW); 2482 r6 = Pcic_read(ph, regbase_win + PCIC_CMA_HIGH); 2483 if (((struct pccbb_softc *)(ph-> 2484 ph_parent))->sc_pcmcia_flags & PCCBB_PCMCIA_MEM_32) { 2485 r7 = Pcic_read(ph, 0x40 + win); 2486 } 2487 2488 DPRINTF(("pccbb_pcmcia_do_mem_map window %d: %02x%02x %02x%02x " 2489 "%02x%02x", win, r1, r2, r3, r4, r5, r6)); 2490 if (((struct pccbb_softc *)(ph-> 2491 ph_parent))->sc_pcmcia_flags & PCCBB_PCMCIA_MEM_32) { 2492 DPRINTF((" %02x", r7)); 2493 } 2494 DPRINTF(("\n")); 2495 } 2496 #endif 2497 } 2498 2499 /* 2500 * int pccbb_pcmcia_mem_map(pcmcia_chipset_handle_t pch, int kind, 2501 * bus_addr_t card_addr, bus_size_t size, 2502 * struct pcmcia_mem_handle *pcmhp, 2503 * bus_size_t *offsetp, int *windowp) 2504 * 2505 * This function maps memory space allocated by the function 2506 * pccbb_pcmcia_mem_alloc(). 2507 */ 2508 int 2509 pccbb_pcmcia_mem_map(pch, kind, card_addr, size, pcmhp, offsetp, windowp) 2510 pcmcia_chipset_handle_t pch; 2511 int kind; 2512 bus_addr_t card_addr; 2513 bus_size_t size; 2514 struct pcmcia_mem_handle *pcmhp; 2515 bus_size_t *offsetp; 2516 int *windowp; 2517 { 2518 struct pcic_handle *ph = (struct pcic_handle *)pch; 2519 bus_addr_t busaddr; 2520 long card_offset; 2521 int win; 2522 2523 for (win = 0; win < PCIC_MEM_WINS; ++win) { 2524 if ((ph->memalloc & (1 << win)) == 0) { 2525 ph->memalloc |= (1 << win); 2526 break; 2527 } 2528 } 2529 2530 if (win == PCIC_MEM_WINS) { 2531 return 1; 2532 } 2533 2534 *windowp = win; 2535 2536 /* XXX this is pretty gross */ 2537 2538 if (((struct pccbb_softc *)ph->ph_parent)->sc_memt != pcmhp->memt) { 2539 panic("pccbb_pcmcia_mem_map memt is bogus"); 2540 } 2541 2542 busaddr = pcmhp->addr; 2543 2544 /* 2545 * compute the address offset to the pcmcia address space for the 2546 * pcic. this is intentionally signed. The masks and shifts below 2547 * will cause TRT to happen in the pcic registers. Deal with making 2548 * sure the address is aligned, and return the alignment offset. 2549 */ 2550 2551 *offsetp = card_addr % PCIC_MEM_PAGESIZE; 2552 card_addr -= *offsetp; 2553 2554 DPRINTF(("pccbb_pcmcia_mem_map window %d bus %lx+%lx+%lx at card addr " 2555 "%lx\n", win, (u_long) busaddr, (u_long) * offsetp, (u_long) size, 2556 (u_long) card_addr)); 2557 2558 /* 2559 * include the offset in the size, and decrement size by one, since 2560 * the hw wants start/stop 2561 */ 2562 size += *offsetp - 1; 2563 2564 card_offset = (((long)card_addr) - ((long)busaddr)); 2565 2566 ph->mem[win].addr = busaddr; 2567 ph->mem[win].size = size; 2568 ph->mem[win].offset = card_offset; 2569 ph->mem[win].kind = kind; 2570 2571 pccbb_pcmcia_do_mem_map(ph, win); 2572 2573 return 0; 2574 } 2575 2576 /* 2577 * int pccbb_pcmcia_mem_unmap(pcmcia_chipset_handle_t pch, 2578 * int window) 2579 * 2580 * This function unmaps memory space which mapped by the function 2581 * pccbb_pcmcia_mem_map(). 2582 */ 2583 void 2584 pccbb_pcmcia_mem_unmap(pch, window) 2585 pcmcia_chipset_handle_t pch; 2586 int window; 2587 { 2588 struct pcic_handle *ph = (struct pcic_handle *)pch; 2589 int reg; 2590 2591 if (window >= PCIC_MEM_WINS) { 2592 panic("pccbb_pcmcia_mem_unmap: window out of range"); 2593 } 2594 2595 reg = Pcic_read(ph, PCIC_ADDRWIN_ENABLE); 2596 reg &= ~(1 << window); 2597 Pcic_write(ph, PCIC_ADDRWIN_ENABLE, reg); 2598 2599 ph->memalloc &= ~(1 << window); 2600 } 2601 2602 #if defined PCCBB_PCMCIA_POLL 2603 struct pccbb_poll_str { 2604 void *arg; 2605 int (*func)(void *); 2606 int level; 2607 struct pcic_handle *ph; 2608 int count; 2609 int num; 2610 }; 2611 2612 static struct pccbb_poll_str pccbb_poll[10]; 2613 static int pccbb_poll_n = 0; 2614 static struct timeout pccbb_poll_timeout; 2615 2616 void pccbb_pcmcia_poll(void *arg); 2617 2618 void 2619 pccbb_pcmcia_poll(arg) 2620 void *arg; 2621 { 2622 struct pccbb_poll_str *poll = arg; 2623 struct pcic_handle *ph = poll->ph; 2624 struct pccbb_softc *sc = ph->sc; 2625 int s; 2626 u_int32_t spsr; /* socket present-state reg */ 2627 2628 timeout_set(&pccbb_poll_timeout, pccbb_pcmcia_poll, arg); 2629 timeout_add_sec(&pccbb_poll_timeout, 2); 2630 switch (poll->level) { 2631 case IPL_NET: 2632 s = splnet(); 2633 break; 2634 case IPL_BIO: 2635 s = splbio(); 2636 break; 2637 case IPL_TTY: /* fallthrough */ 2638 default: 2639 s = spltty(); 2640 break; 2641 } 2642 2643 spsr = 2644 bus_space_read_4(sc->sc_base_memt, sc->sc_base_memh, 2645 CB_SOCKET_STAT); 2646 2647 #if defined PCCBB_PCMCIA_POLL_ONLY && defined LEVEL2 2648 if (!(spsr & 0x40)) /* CINT low */ 2649 #else 2650 if (1) 2651 #endif 2652 { 2653 if ((*poll->func) (poll->arg) > 0) { 2654 ++poll->count; 2655 /* printf("intr: reported from poller, 0x%x\n", spsr); */ 2656 #if defined LEVEL2 2657 } else { 2658 printf("intr: miss! 0x%x\n", spsr); 2659 #endif 2660 } 2661 } 2662 splx(s); 2663 } 2664 #endif /* defined CB_PCMCIA_POLL */ 2665 2666 /* 2667 * void *pccbb_pcmcia_intr_establish(pcmcia_chipset_handle_t pch, 2668 * struct pcmcia_function *pf, 2669 * int ipl, 2670 * int (*func)(void *), 2671 * void *arg); 2672 * 2673 * This function enables PC-Card interrupt. PCCBB uses PCI interrupt line. 2674 */ 2675 void * 2676 pccbb_pcmcia_intr_establish(pch, pf, ipl, func, arg, xname) 2677 pcmcia_chipset_handle_t pch; 2678 struct pcmcia_function *pf; 2679 int ipl; 2680 int (*func)(void *); 2681 void *arg; 2682 char *xname; 2683 { 2684 struct pcic_handle *ph = (struct pcic_handle *)pch; 2685 struct pccbb_softc *sc = (struct pccbb_softc *)ph->ph_parent; 2686 2687 if (!(pf->cfe->flags & PCMCIA_CFE_IRQLEVEL)) { 2688 /* what should I do? */ 2689 if ((pf->cfe->flags & PCMCIA_CFE_IRQLEVEL)) { 2690 DPRINTF( 2691 ("%s does not provide edge nor pulse interrupt\n", 2692 sc->sc_dev.dv_xname)); 2693 return NULL; 2694 } 2695 /* 2696 * XXX Noooooo! The interrupt flag must set properly!! 2697 * dumb pcmcia driver!! 2698 */ 2699 } 2700 2701 return pccbb_intr_establish(sc, -1, ipl, func, arg, xname); 2702 } 2703 2704 /* 2705 * void pccbb_pcmcia_intr_disestablish(pcmcia_chipset_handle_t pch, 2706 * void *ih) 2707 * 2708 * This function disables PC-Card interrupt. 2709 */ 2710 void 2711 pccbb_pcmcia_intr_disestablish(pch, ih) 2712 pcmcia_chipset_handle_t pch; 2713 void *ih; 2714 { 2715 struct pcic_handle *ph = (struct pcic_handle *)pch; 2716 struct pccbb_softc *sc = (struct pccbb_softc *)ph->ph_parent; 2717 2718 pccbb_intr_disestablish(sc, ih); 2719 } 2720 2721 const char * 2722 pccbb_pcmcia_intr_string(pch, ih) 2723 pcmcia_chipset_handle_t pch; 2724 void *ih; 2725 { 2726 if (ih == NULL) 2727 return "couldn't establish interrupt"; 2728 else 2729 return ""; /* card shares interrupt of the bridge */ 2730 } 2731 2732 /* 2733 * int 2734 * pccbb_rbus_cb_space_alloc(cardbus_chipset_tag_t ct, rbus_tag_t rb, 2735 * bus_addr_t addr, bus_size_t size, 2736 * bus_addr_t mask, bus_size_t align, 2737 * int flags, bus_addr_t *addrp; 2738 * bus_space_handle_t *bshp) 2739 * 2740 * This function allocates a portion of memory or io space for 2741 * clients. This function is called from CardBus card drivers. 2742 */ 2743 int 2744 pccbb_rbus_cb_space_alloc(ct, rb, addr, size, mask, align, flags, addrp, bshp) 2745 cardbus_chipset_tag_t ct; 2746 rbus_tag_t rb; 2747 bus_addr_t addr; 2748 bus_size_t size; 2749 bus_addr_t mask; 2750 bus_size_t align; 2751 int flags; 2752 bus_addr_t *addrp; 2753 bus_space_handle_t *bshp; 2754 { 2755 struct pccbb_softc *sc = (struct pccbb_softc *)ct; 2756 2757 DPRINTF( 2758 ("pccbb_rbus_cb_space_alloc: adr %lx, size %lx, mask %lx, align %lx\n", 2759 addr, size, mask, align)); 2760 2761 if (align == 0) { 2762 align = size; 2763 } 2764 2765 if (rb->rb_bt == sc->sc_memt) { 2766 if (align < 16) { 2767 return 1; 2768 } 2769 } else if (rb->rb_bt == sc->sc_iot) { 2770 if (align < 4) { 2771 return 1; 2772 } 2773 /* XXX: hack for avoiding ISA image */ 2774 if (mask < 0x0100) { 2775 mask = 0x3ff; 2776 addr = 0x300; 2777 } 2778 2779 } else { 2780 DPRINTF( 2781 ("pccbb_rbus_cb_space_alloc: Bus space tag %x is NOT used.\n", 2782 rb->rb_bt)); 2783 return 1; 2784 /* XXX: panic here? */ 2785 } 2786 2787 if (rbus_space_alloc(rb, addr, size, mask, align, flags, addrp, bshp)) { 2788 printf("%s: <rbus> no bus space\n", sc->sc_dev.dv_xname); 2789 return 1; 2790 } 2791 2792 pccbb_open_win(sc, rb->rb_bt, *addrp, size, *bshp, 0); 2793 2794 return 0; 2795 } 2796 2797 /* 2798 * int 2799 * pccbb_rbus_cb_space_free(cardbus_chipset_tag_t *ct, rbus_tag_t rb, 2800 * bus_space_handle_t *bshp, bus_size_t size); 2801 * 2802 * This function is called from CardBus card drivers. 2803 */ 2804 int 2805 pccbb_rbus_cb_space_free(ct, rb, bsh, size) 2806 cardbus_chipset_tag_t ct; 2807 rbus_tag_t rb; 2808 bus_space_handle_t bsh; 2809 bus_size_t size; 2810 { 2811 struct pccbb_softc *sc = (struct pccbb_softc *)ct; 2812 bus_space_tag_t bt = rb->rb_bt; 2813 2814 pccbb_close_win(sc, bt, bsh, size); 2815 2816 if (bt == sc->sc_memt) { 2817 } else if (bt == sc->sc_iot) { 2818 } else { 2819 return 1; 2820 /* XXX: panic here? */ 2821 } 2822 2823 return rbus_space_free(rb, bsh, size, NULL); 2824 } 2825 2826 int 2827 pccbb_open_win(sc, bst, addr, size, bsh, flags) 2828 struct pccbb_softc *sc; 2829 bus_space_tag_t bst; 2830 bus_addr_t addr; 2831 bus_size_t size; 2832 bus_space_handle_t bsh; 2833 int flags; 2834 { 2835 struct pccbb_win_chain_head *head; 2836 bus_addr_t align; 2837 2838 head = &sc->sc_iowindow; 2839 align = 0x04; 2840 if (sc->sc_memt == bst) { 2841 head = &sc->sc_memwindow; 2842 align = 0x1000; 2843 DPRINTF(("using memory window, %x %x %x\n\n", 2844 sc->sc_iot, sc->sc_memt, bst)); 2845 } 2846 2847 if (pccbb_winlist_insert(head, addr, size, bsh, flags)) { 2848 printf("%s: pccbb_open_win: %s winlist insert failed\n", 2849 sc->sc_dev.dv_xname, 2850 (head == &sc->sc_memwindow) ? "mem" : "io"); 2851 } 2852 pccbb_winset(align, sc, bst); 2853 2854 return 0; 2855 } 2856 2857 int 2858 pccbb_close_win(sc, bst, bsh, size) 2859 struct pccbb_softc *sc; 2860 bus_space_tag_t bst; 2861 bus_space_handle_t bsh; 2862 bus_size_t size; 2863 { 2864 struct pccbb_win_chain_head *head; 2865 bus_addr_t align; 2866 2867 head = &sc->sc_iowindow; 2868 align = 0x04; 2869 if (sc->sc_memt == bst) { 2870 head = &sc->sc_memwindow; 2871 align = 0x1000; 2872 } 2873 2874 if (pccbb_winlist_delete(head, bsh, size)) { 2875 printf("%s: pccbb_close_win: %s winlist delete failed\n", 2876 sc->sc_dev.dv_xname, 2877 (head == &sc->sc_memwindow) ? "mem" : "io"); 2878 } 2879 pccbb_winset(align, sc, bst); 2880 2881 return 0; 2882 } 2883 2884 int 2885 pccbb_winlist_insert(head, start, size, bsh, flags) 2886 struct pccbb_win_chain_head *head; 2887 bus_addr_t start; 2888 bus_size_t size; 2889 bus_space_handle_t bsh; 2890 int flags; 2891 { 2892 struct pccbb_win_chain *chainp, *elem; 2893 2894 if ((elem = malloc(sizeof(struct pccbb_win_chain), M_DEVBUF, 2895 M_NOWAIT)) == NULL) 2896 return (1); /* fail */ 2897 2898 elem->wc_start = start; 2899 elem->wc_end = start + (size - 1); 2900 elem->wc_handle = bsh; 2901 elem->wc_flags = flags; 2902 2903 for (chainp = TAILQ_FIRST(head); chainp != NULL; 2904 chainp = TAILQ_NEXT(chainp, wc_list)) { 2905 if (chainp->wc_end < start) 2906 continue; 2907 TAILQ_INSERT_AFTER(head, chainp, elem, wc_list); 2908 return (0); 2909 } 2910 2911 TAILQ_INSERT_TAIL(head, elem, wc_list); 2912 return (0); 2913 } 2914 2915 int 2916 pccbb_winlist_delete(head, bsh, size) 2917 struct pccbb_win_chain_head *head; 2918 bus_space_handle_t bsh; 2919 bus_size_t size; 2920 { 2921 struct pccbb_win_chain *chainp; 2922 2923 for (chainp = TAILQ_FIRST(head); chainp != NULL; 2924 chainp = TAILQ_NEXT(chainp, wc_list)) { 2925 if (memcmp(&chainp->wc_handle, &bsh, sizeof(bsh))) 2926 continue; 2927 if ((chainp->wc_end - chainp->wc_start) != (size - 1)) { 2928 printf("pccbb_winlist_delete: window 0x%lx size " 2929 "inconsistent: 0x%lx, 0x%lx\n", 2930 chainp->wc_start, 2931 chainp->wc_end - chainp->wc_start, 2932 size - 1); 2933 return 1; 2934 } 2935 2936 TAILQ_REMOVE(head, chainp, wc_list); 2937 free(chainp, M_DEVBUF); 2938 2939 return 0; 2940 } 2941 2942 return 1; /* fail: no candidate to remove */ 2943 } 2944 2945 void 2946 pccbb_winset(align, sc, bst) 2947 bus_addr_t align; 2948 struct pccbb_softc *sc; 2949 bus_space_tag_t bst; 2950 { 2951 pci_chipset_tag_t pc; 2952 pcitag_t tag; 2953 bus_addr_t mask = ~(align - 1); 2954 struct { 2955 cardbusreg_t win_start; 2956 cardbusreg_t win_limit; 2957 int win_flags; 2958 } win[2]; 2959 struct pccbb_win_chain *chainp; 2960 int offs; 2961 2962 win[0].win_start = win[1].win_start = 0xffffffff; 2963 win[0].win_limit = win[1].win_limit = 0; 2964 win[0].win_flags = win[1].win_flags = 0; 2965 2966 chainp = TAILQ_FIRST(&sc->sc_iowindow); 2967 offs = 0x2c; 2968 if (sc->sc_memt == bst) { 2969 chainp = TAILQ_FIRST(&sc->sc_memwindow); 2970 offs = 0x1c; 2971 } 2972 2973 if (chainp != NULL) { 2974 win[0].win_start = chainp->wc_start & mask; 2975 win[0].win_limit = chainp->wc_end & mask; 2976 win[0].win_flags = chainp->wc_flags; 2977 chainp = TAILQ_NEXT(chainp, wc_list); 2978 } 2979 2980 for (; chainp != NULL; chainp = TAILQ_NEXT(chainp, wc_list)) { 2981 if (win[1].win_start == 0xffffffff) { 2982 /* window 1 is not used */ 2983 if ((win[0].win_flags == chainp->wc_flags) && 2984 (win[0].win_limit + align >= 2985 (chainp->wc_start & mask))) { 2986 /* concatenate */ 2987 win[0].win_limit = chainp->wc_end & mask; 2988 } else { 2989 /* make new window */ 2990 win[1].win_start = chainp->wc_start & mask; 2991 win[1].win_limit = chainp->wc_end & mask; 2992 win[1].win_flags = chainp->wc_flags; 2993 } 2994 continue; 2995 } 2996 2997 /* Both windows are engaged. */ 2998 if (win[0].win_flags == win[1].win_flags) { 2999 /* same flags */ 3000 if (win[0].win_flags == chainp->wc_flags) { 3001 if (win[1].win_start - (win[0].win_limit + 3002 align) < 3003 (chainp->wc_start & mask) - 3004 ((chainp->wc_end & mask) + align)) { 3005 /* 3006 * merge window 0 and 1, and set win1 3007 * to chainp 3008 */ 3009 win[0].win_limit = win[1].win_limit; 3010 win[1].win_start = 3011 chainp->wc_start & mask; 3012 win[1].win_limit = 3013 chainp->wc_end & mask; 3014 } else { 3015 win[1].win_limit = 3016 chainp->wc_end & mask; 3017 } 3018 } else { 3019 /* different flags */ 3020 3021 /* concatenate win0 and win1 */ 3022 win[0].win_limit = win[1].win_limit; 3023 /* allocate win[1] to new space */ 3024 win[1].win_start = chainp->wc_start & mask; 3025 win[1].win_limit = chainp->wc_end & mask; 3026 win[1].win_flags = chainp->wc_flags; 3027 } 3028 } else { 3029 /* the flags of win[0] and win[1] is different */ 3030 if (win[0].win_flags == chainp->wc_flags) { 3031 win[0].win_limit = chainp->wc_end & mask; 3032 /* 3033 * XXX this creates overlapping windows, so 3034 * what should the poor bridge do if one is 3035 * cachable, and the other is not? 3036 */ 3037 printf("%s: overlapping windows\n", 3038 sc->sc_dev.dv_xname); 3039 } else { 3040 win[1].win_limit = chainp->wc_end & mask; 3041 } 3042 } 3043 } 3044 3045 pc = sc->sc_pc; 3046 tag = sc->sc_tag; 3047 pci_conf_write(pc, tag, offs, win[0].win_start); 3048 pci_conf_write(pc, tag, offs + 4, win[0].win_limit); 3049 pci_conf_write(pc, tag, offs + 8, win[1].win_start); 3050 pci_conf_write(pc, tag, offs + 12, win[1].win_limit); 3051 DPRINTF(("--pccbb_winset: win0 [%x, %lx), win1 [%x, %lx)\n", 3052 pci_conf_read(pc, tag, offs), 3053 pci_conf_read(pc, tag, offs + 4) + align, 3054 pci_conf_read(pc, tag, offs + 8), 3055 pci_conf_read(pc, tag, offs + 12) + align)); 3056 3057 if (bst == sc->sc_memt) { 3058 pcireg_t bcr = pci_conf_read(pc, tag, PCI_BCR_INTR); 3059 3060 bcr &= ~(CB_BCR_PREFETCH_MEMWIN0 | CB_BCR_PREFETCH_MEMWIN1); 3061 if (win[0].win_flags & PCCBB_MEM_CACHABLE) 3062 bcr |= CB_BCR_PREFETCH_MEMWIN0; 3063 if (win[1].win_flags & PCCBB_MEM_CACHABLE) 3064 bcr |= CB_BCR_PREFETCH_MEMWIN1; 3065 pci_conf_write(pc, tag, PCI_BCR_INTR, bcr); 3066 } 3067 } 3068 3069 void 3070 pccbb_powerhook(why, arg) 3071 int why; 3072 void *arg; 3073 { 3074 struct pccbb_softc *sc = arg; 3075 u_int32_t reg; 3076 bus_space_tag_t base_memt = sc->sc_base_memt; /* socket regs memory */ 3077 bus_space_handle_t base_memh = sc->sc_base_memh; 3078 3079 DPRINTF(("%s: power: why %d\n", sc->sc_dev.dv_xname, why)); 3080 3081 if (why == PWR_SUSPEND || why == PWR_STANDBY) { 3082 DPRINTF(("%s: power: why %d stopping intr\n", 3083 sc->sc_dev.dv_xname, why)); 3084 if (sc->sc_pil_intr_enable) { 3085 (void)pccbbintr_function(sc); 3086 } 3087 sc->sc_pil_intr_enable = 0; 3088 3089 /* ToDo: deactivate or suspend child devices */ 3090 3091 } 3092 3093 if (why == PWR_RESUME) { 3094 if (pci_conf_read (sc->sc_pc, sc->sc_tag, PCI_SOCKBASE) == 0) 3095 /* BIOS did not recover this register */ 3096 pci_conf_write (sc->sc_pc, sc->sc_tag, 3097 PCI_SOCKBASE, sc->sc_sockbase); 3098 if (pci_conf_read (sc->sc_pc, sc->sc_tag, PCI_BUSNUM) == 0) 3099 /* BIOS did not recover this register */ 3100 pci_conf_write (sc->sc_pc, sc->sc_tag, 3101 PCI_BUSNUM, sc->sc_busnum); 3102 /* CSC Interrupt: Card detect interrupt on */ 3103 reg = bus_space_read_4(base_memt, base_memh, CB_SOCKET_MASK); 3104 /* Card detect intr is turned on. */ 3105 reg |= CB_SOCKET_MASK_CD; 3106 bus_space_write_4(base_memt, base_memh, CB_SOCKET_MASK, reg); 3107 /* reset interrupt */ 3108 reg = bus_space_read_4(base_memt, base_memh, CB_SOCKET_EVENT); 3109 bus_space_write_4(base_memt, base_memh, CB_SOCKET_EVENT, reg); 3110 3111 /* 3112 * check for card insertion or removal during suspend period. 3113 * XXX: the code can't cope with card swap (remove then 3114 * insert). how can we detect such situation? 3115 */ 3116 (void)pccbbintr(sc); 3117 3118 sc->sc_pil_intr_enable = 1; 3119 DPRINTF(("%s: power: RESUME enabling intr\n", 3120 sc->sc_dev.dv_xname)); 3121 3122 /* ToDo: activate or wakeup child devices */ 3123 } 3124 } 3125