1 /* $OpenBSD: pccbb.c,v 1.92 2014/07/12 18:48:52 tedu Exp $ */ 2 /* $NetBSD: pccbb.c,v 1.96 2004/03/28 09:49:31 nakayama Exp $ */ 3 4 /* 5 * Copyright (c) 1998, 1999 and 2000 6 * HAYAKAWA Koichi. All rights reserved. 7 * 8 * Redistribution and use in source and binary forms, with or without 9 * modification, are permitted provided that the following conditions 10 * are met: 11 * 1. Redistributions of source code must retain the above copyright 12 * notice, this list of conditions and the following disclaimer. 13 * 2. Redistributions in binary form must reproduce the above copyright 14 * notice, this list of conditions and the following disclaimer in the 15 * documentation and/or other materials provided with the distribution. 16 * 17 * THIS SOFTWARE IS PROVIDED BY THE AUTHOR ``AS IS'' AND ANY EXPRESS OR 18 * IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED WARRANTIES 19 * OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE DISCLAIMED. 20 * IN NO EVENT SHALL THE AUTHOR BE LIABLE FOR ANY DIRECT, INDIRECT, 21 * INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT 22 * NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, 23 * DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY 24 * THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT 25 * (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE OF 26 * THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE. 27 */ 28 29 /* 30 #define CBB_DEBUG 31 #define SHOW_REGS 32 #define PCCBB_PCMCIA_POLL 33 */ 34 35 /* 36 #define CB_PCMCIA_POLL 37 #define CB_PCMCIA_POLL_ONLY 38 #define LEVEL2 39 */ 40 41 #include <sys/types.h> 42 #include <sys/param.h> 43 #include <sys/systm.h> 44 #include <sys/kernel.h> 45 #include <sys/errno.h> 46 #include <sys/evcount.h> 47 #include <sys/ioctl.h> 48 #include <sys/syslog.h> 49 #include <sys/device.h> 50 #include <sys/malloc.h> 51 #include <sys/task.h> 52 53 #include <machine/intr.h> 54 #include <machine/bus.h> 55 56 #include <dev/pci/pcivar.h> 57 #include <dev/pci/pcireg.h> 58 #include <dev/pci/pcidevs.h> 59 60 #include <dev/pci/pccbbreg.h> 61 62 #include <dev/cardbus/cardslotvar.h> 63 64 #include <dev/cardbus/cardbusvar.h> 65 66 #include <dev/pcmcia/pcmciareg.h> 67 #include <dev/pcmcia/pcmciavar.h> 68 69 #include <dev/ic/i82365reg.h> 70 #include <dev/ic/i82365var.h> 71 #include <dev/pci/pccbbvar.h> 72 73 #ifndef __NetBSD_Version__ 74 struct cfdriver cbb_cd = { 75 NULL, "cbb", DV_DULL 76 }; 77 #endif 78 79 #if defined CBB_DEBUG 80 #define DPRINTF(x) printf x 81 #else 82 #define DPRINTF(x) 83 #endif 84 85 int pcicbbmatch(struct device *, void *, void *); 86 void pccbbattach(struct device *, struct device *, void *); 87 int pccbbactivate(struct device *, int); 88 int pccbbintr(void *); 89 void pccbb_shutdown(void *); 90 void pci113x_insert(void *); 91 int pccbbintr_function(struct pccbb_softc *); 92 93 int pccbb_checksockstat(struct pccbb_softc *); 94 int pccbb_detect_card(struct pccbb_softc *); 95 96 void pccbb_pcmcia_write(struct pcic_handle *, int, int); 97 u_int8_t pccbb_pcmcia_read(struct pcic_handle *, int); 98 #define Pcic_read(ph, reg) ((ph)->ph_read((ph), (reg))) 99 #define Pcic_write(ph, reg, val) ((ph)->ph_write((ph), (reg), (val))) 100 101 int cb_reset(struct pccbb_softc *); 102 int cb_detect_voltage(struct pccbb_softc *); 103 int cbbprint(void *, const char *); 104 105 int cb_chipset(u_int32_t, int *); 106 void pccbb_pcmcia_attach_setup(struct pccbb_softc *, 107 struct pcmciabus_attach_args *); 108 #if 0 109 void pccbb_pcmcia_attach_card(struct pcic_handle *); 110 void pccbb_pcmcia_detach_card(struct pcic_handle *, int); 111 void pccbb_pcmcia_deactivate_card(struct pcic_handle *); 112 #endif 113 114 int pccbb_ctrl(cardbus_chipset_tag_t, int); 115 int pccbb_power(cardbus_chipset_tag_t, int); 116 int pccbb_cardenable(struct pccbb_softc * sc, int function); 117 void *pccbb_intr_establish(struct pccbb_softc *, int irq, int level, 118 int (*ih) (void *), void *sc, const char *); 119 void pccbb_intr_disestablish(struct pccbb_softc *, void *ih); 120 121 void *pccbb_cb_intr_establish(cardbus_chipset_tag_t, int irq, int level, 122 int (*ih) (void *), void *sc, const char *); 123 void pccbb_cb_intr_disestablish(cardbus_chipset_tag_t ct, void *ih); 124 125 void pccbb_legacy_disable(struct pccbb_softc *sc); 126 void pccbb_chipinit(struct pccbb_softc *); 127 128 int pccbb_pcmcia_mem_alloc(pcmcia_chipset_handle_t, bus_size_t, 129 struct pcmcia_mem_handle *); 130 void pccbb_pcmcia_mem_free(pcmcia_chipset_handle_t, 131 struct pcmcia_mem_handle *); 132 int pccbb_pcmcia_mem_map(pcmcia_chipset_handle_t, int, bus_addr_t, 133 bus_size_t, struct pcmcia_mem_handle *, bus_size_t *, int *); 134 void pccbb_pcmcia_mem_unmap(pcmcia_chipset_handle_t, int); 135 int pccbb_pcmcia_io_alloc(pcmcia_chipset_handle_t, bus_addr_t, 136 bus_size_t, bus_size_t, struct pcmcia_io_handle *); 137 void pccbb_pcmcia_io_free(pcmcia_chipset_handle_t, 138 struct pcmcia_io_handle *); 139 int pccbb_pcmcia_io_map(pcmcia_chipset_handle_t, int, bus_addr_t, 140 bus_size_t, struct pcmcia_io_handle *, int *); 141 void pccbb_pcmcia_io_unmap(pcmcia_chipset_handle_t, int); 142 void *pccbb_pcmcia_intr_establish(pcmcia_chipset_handle_t, 143 struct pcmcia_function *, int, int (*)(void *), void *, char *); 144 void pccbb_pcmcia_intr_disestablish(pcmcia_chipset_handle_t, void *); 145 const char *pccbb_pcmcia_intr_string(pcmcia_chipset_handle_t, void *); 146 void pccbb_pcmcia_socket_enable(pcmcia_chipset_handle_t); 147 void pccbb_pcmcia_socket_disable(pcmcia_chipset_handle_t); 148 int pccbb_pcmcia_card_detect(pcmcia_chipset_handle_t pch); 149 150 void pccbb_pcmcia_do_io_map(struct pcic_handle *, int); 151 void pccbb_pcmcia_wait_ready(struct pcic_handle *); 152 void pccbb_pcmcia_do_mem_map(struct pcic_handle *, int); 153 154 /* bus-space allocation and deallocation functions */ 155 int pccbb_rbus_cb_space_alloc(cardbus_chipset_tag_t, rbus_tag_t, 156 bus_addr_t addr, bus_size_t size, bus_addr_t mask, bus_size_t align, 157 int flags, bus_addr_t * addrp, bus_space_handle_t * bshp); 158 int pccbb_rbus_cb_space_free(cardbus_chipset_tag_t, rbus_tag_t, 159 bus_space_handle_t, bus_size_t); 160 161 int pccbb_open_win(struct pccbb_softc *, bus_space_tag_t, 162 bus_addr_t, bus_size_t, bus_space_handle_t, int flags); 163 int pccbb_close_win(struct pccbb_softc *, bus_space_tag_t, 164 bus_space_handle_t, bus_size_t); 165 int pccbb_winlist_insert(struct pccbb_win_chain_head *, bus_addr_t, 166 bus_size_t, bus_space_handle_t, int); 167 int pccbb_winlist_delete(struct pccbb_win_chain_head *, 168 bus_space_handle_t, bus_size_t); 169 void pccbb_winset(bus_addr_t align, struct pccbb_softc *, 170 bus_space_tag_t); 171 void pccbb_winlist_show(struct pccbb_win_chain *); 172 173 /* for config_defer */ 174 void pccbb_pci_callback(struct device *); 175 176 #if defined SHOW_REGS 177 void cb_show_regs(pci_chipset_tag_t, pcitag_t, bus_space_tag_t, 178 bus_space_handle_t memh); 179 #endif 180 181 struct cfattach cbb_pci_ca = { 182 sizeof(struct pccbb_softc), pcicbbmatch, pccbbattach, NULL, 183 pccbbactivate 184 }; 185 186 static struct pcmcia_chip_functions pccbb_pcmcia_funcs = { 187 pccbb_pcmcia_mem_alloc, 188 pccbb_pcmcia_mem_free, 189 pccbb_pcmcia_mem_map, 190 pccbb_pcmcia_mem_unmap, 191 pccbb_pcmcia_io_alloc, 192 pccbb_pcmcia_io_free, 193 pccbb_pcmcia_io_map, 194 pccbb_pcmcia_io_unmap, 195 pccbb_pcmcia_intr_establish, 196 pccbb_pcmcia_intr_disestablish, 197 pccbb_pcmcia_intr_string, 198 pccbb_pcmcia_socket_enable, 199 pccbb_pcmcia_socket_disable, 200 pccbb_pcmcia_card_detect 201 }; 202 203 static struct cardbus_functions pccbb_funcs = { 204 pccbb_rbus_cb_space_alloc, 205 pccbb_rbus_cb_space_free, 206 pccbb_cb_intr_establish, 207 pccbb_cb_intr_disestablish, 208 pccbb_ctrl, 209 pccbb_power, 210 }; 211 212 /* 213 * delay_ms() is wait in milliseconds. It should be used instead 214 * of delay() if you want to wait more than 1 ms. 215 */ 216 static inline void 217 delay_ms(int millis, void *param) 218 { 219 if (cold) 220 delay(millis * 1000); 221 else 222 tsleep(param, PWAIT, "pccbb", MAX(2, hz * millis / 1000)); 223 } 224 225 int 226 pcicbbmatch(parent, match, aux) 227 struct device *parent; 228 void *match; 229 void *aux; 230 { 231 struct pci_attach_args *pa = (struct pci_attach_args *)aux; 232 233 if (PCI_CLASS(pa->pa_class) == PCI_CLASS_BRIDGE && 234 PCI_SUBCLASS(pa->pa_class) == PCI_SUBCLASS_BRIDGE_CARDBUS && 235 PCI_INTERFACE(pa->pa_class) == 0) { 236 return 1; 237 } 238 239 return 0; 240 } 241 242 #define MAKEID(vendor, prod) (((vendor) << PCI_VENDOR_SHIFT) \ 243 | ((prod) << PCI_PRODUCT_SHIFT)) 244 245 struct yenta_chipinfo { 246 pcireg_t yc_id; /* vendor tag | product tag */ 247 int yc_chiptype; 248 int yc_flags; 249 } yc_chipsets[] = { 250 /* Texas Instruments chips */ 251 { MAKEID(PCI_VENDOR_TI, PCI_PRODUCT_TI_PCI1130), CB_TI113X, 252 PCCBB_PCMCIA_IO_RELOC | PCCBB_PCMCIA_MEM_32}, 253 { MAKEID(PCI_VENDOR_TI, PCI_PRODUCT_TI_PCI1131), CB_TI113X, 254 PCCBB_PCMCIA_IO_RELOC | PCCBB_PCMCIA_MEM_32}, 255 { MAKEID(PCI_VENDOR_TI, PCI_PRODUCT_TI_PCI1250), CB_TI125X, 256 PCCBB_PCMCIA_IO_RELOC | PCCBB_PCMCIA_MEM_32}, 257 { MAKEID(PCI_VENDOR_TI, PCI_PRODUCT_TI_PCI1220), CB_TI12XX, 258 PCCBB_PCMCIA_IO_RELOC | PCCBB_PCMCIA_MEM_32}, 259 { MAKEID(PCI_VENDOR_TI, PCI_PRODUCT_TI_PCI1221), CB_TI12XX, 260 PCCBB_PCMCIA_IO_RELOC | PCCBB_PCMCIA_MEM_32}, 261 { MAKEID(PCI_VENDOR_TI, PCI_PRODUCT_TI_PCI1225), CB_TI12XX, 262 PCCBB_PCMCIA_IO_RELOC | PCCBB_PCMCIA_MEM_32}, 263 { MAKEID(PCI_VENDOR_TI, PCI_PRODUCT_TI_PCI1251), CB_TI125X, 264 PCCBB_PCMCIA_IO_RELOC | PCCBB_PCMCIA_MEM_32}, 265 { MAKEID(PCI_VENDOR_TI, PCI_PRODUCT_TI_PCI1251B), CB_TI125X, 266 PCCBB_PCMCIA_IO_RELOC | PCCBB_PCMCIA_MEM_32}, 267 { MAKEID(PCI_VENDOR_TI, PCI_PRODUCT_TI_PCI1211), CB_TI12XX, 268 PCCBB_PCMCIA_IO_RELOC | PCCBB_PCMCIA_MEM_32}, 269 { MAKEID(PCI_VENDOR_TI, PCI_PRODUCT_TI_PCI1410), CB_TI12XX, 270 PCCBB_PCMCIA_IO_RELOC | PCCBB_PCMCIA_MEM_32}, 271 { MAKEID(PCI_VENDOR_TI, PCI_PRODUCT_TI_PCI1420), CB_TI12XX, 272 PCCBB_PCMCIA_IO_RELOC | PCCBB_PCMCIA_MEM_32}, 273 { MAKEID(PCI_VENDOR_TI, PCI_PRODUCT_TI_PCI1450), CB_TI125X, 274 PCCBB_PCMCIA_IO_RELOC | PCCBB_PCMCIA_MEM_32}, 275 { MAKEID(PCI_VENDOR_TI, PCI_PRODUCT_TI_PCI1451), CB_TI12XX, 276 PCCBB_PCMCIA_IO_RELOC | PCCBB_PCMCIA_MEM_32}, 277 { MAKEID(PCI_VENDOR_TI, PCI_PRODUCT_TI_PCI1510), CB_TI12XX, 278 PCCBB_PCMCIA_IO_RELOC | PCCBB_PCMCIA_MEM_32}, 279 { MAKEID(PCI_VENDOR_TI, PCI_PRODUCT_TI_PCI7XX1), CB_TI12XX, 280 PCCBB_PCMCIA_IO_RELOC | PCCBB_PCMCIA_MEM_32}, 281 282 /* Ricoh chips */ 283 { MAKEID(PCI_VENDOR_RICOH, PCI_PRODUCT_RICOH_RF5C475), CB_RX5C47X, 284 PCCBB_PCMCIA_MEM_32}, 285 { MAKEID(PCI_VENDOR_RICOH, PCI_PRODUCT_RICOH_RF5C476), CB_RX5C47X, 286 PCCBB_PCMCIA_MEM_32}, 287 { MAKEID(PCI_VENDOR_RICOH, PCI_PRODUCT_RICOH_RF5C477), CB_RX5C47X, 288 PCCBB_PCMCIA_MEM_32}, 289 { MAKEID(PCI_VENDOR_RICOH, PCI_PRODUCT_RICOH_RF5C478), CB_RX5C47X, 290 PCCBB_PCMCIA_MEM_32}, 291 { MAKEID(PCI_VENDOR_RICOH, PCI_PRODUCT_RICOH_RF5C465), CB_RX5C46X, 292 PCCBB_PCMCIA_MEM_32}, 293 { MAKEID(PCI_VENDOR_RICOH, PCI_PRODUCT_RICOH_RF5C466), CB_RX5C46X, 294 PCCBB_PCMCIA_MEM_32}, 295 296 /* Toshiba products */ 297 { MAKEID(PCI_VENDOR_TOSHIBA2, PCI_PRODUCT_TOSHIBA2_ToPIC95), 298 CB_TOPIC95, PCCBB_PCMCIA_MEM_32}, 299 { MAKEID(PCI_VENDOR_TOSHIBA2, PCI_PRODUCT_TOSHIBA2_ToPIC95B), 300 CB_TOPIC95B, PCCBB_PCMCIA_MEM_32}, 301 { MAKEID(PCI_VENDOR_TOSHIBA2, PCI_PRODUCT_TOSHIBA2_ToPIC97), 302 CB_TOPIC97, PCCBB_PCMCIA_MEM_32}, 303 { MAKEID(PCI_VENDOR_TOSHIBA2, PCI_PRODUCT_TOSHIBA2_ToPIC100), 304 CB_TOPIC97, PCCBB_PCMCIA_MEM_32}, 305 306 /* Cirrus Logic products */ 307 { MAKEID(PCI_VENDOR_CIRRUS, PCI_PRODUCT_CIRRUS_CL_PD6832), 308 CB_CIRRUS, PCCBB_PCMCIA_MEM_32}, 309 { MAKEID(PCI_VENDOR_CIRRUS, PCI_PRODUCT_CIRRUS_CL_PD6833), 310 CB_CIRRUS, PCCBB_PCMCIA_MEM_32}, 311 312 /* older O2Micro bridges */ 313 { MAKEID(PCI_VENDOR_O2MICRO, PCI_PRODUCT_O2MICRO_OZ6729), 314 CB_OLDO2MICRO, PCCBB_PCMCIA_MEM_32}, 315 { MAKEID(PCI_VENDOR_O2MICRO, PCI_PRODUCT_O2MICRO_OZ6730), 316 CB_OLDO2MICRO, PCCBB_PCMCIA_MEM_32}, 317 { MAKEID(PCI_VENDOR_O2MICRO, PCI_PRODUCT_O2MICRO_OZ6872), /* 68[71]2 */ 318 CB_OLDO2MICRO, PCCBB_PCMCIA_MEM_32}, 319 { MAKEID(PCI_VENDOR_O2MICRO, PCI_PRODUCT_O2MICRO_OZ6832), 320 CB_OLDO2MICRO, PCCBB_PCMCIA_MEM_32}, 321 { MAKEID(PCI_VENDOR_O2MICRO, PCI_PRODUCT_O2MICRO_OZ6836), 322 CB_OLDO2MICRO, PCCBB_PCMCIA_MEM_32}, 323 324 /* sentinel, or Generic chip */ 325 { 0 /* null id */ , CB_UNKNOWN, PCCBB_PCMCIA_MEM_32}, 326 }; 327 328 int 329 cb_chipset(pci_id, flagp) 330 u_int32_t pci_id; 331 int *flagp; 332 { 333 struct yenta_chipinfo *yc; 334 335 /* Loop over except the last default entry. */ 336 for (yc = yc_chipsets; yc < yc_chipsets + 337 sizeof(yc_chipsets) / sizeof(yc_chipsets[0]) - 1; yc++) 338 if (pci_id == yc->yc_id) 339 break; 340 341 if (flagp != NULL) 342 *flagp = yc->yc_flags; 343 344 return (yc->yc_chiptype); 345 } 346 347 void 348 pccbb_shutdown(void *arg) 349 { 350 struct pccbb_softc *sc = arg; 351 pcireg_t command; 352 353 DPRINTF(("%s: shutdown\n", sc->sc_dev.dv_xname)); 354 355 /* turn off power */ 356 pccbb_power((cardbus_chipset_tag_t)sc, CARDBUS_VCC_0V | CARDBUS_VPP_0V); 357 358 bus_space_write_4(sc->sc_base_memt, sc->sc_base_memh, CB_SOCKET_MASK, 359 0); 360 361 command = pci_conf_read(sc->sc_pc, sc->sc_tag, PCI_COMMAND_STATUS_REG); 362 363 command &= ~(PCI_COMMAND_IO_ENABLE | PCI_COMMAND_MEM_ENABLE | 364 PCI_COMMAND_MASTER_ENABLE); 365 pci_conf_write(sc->sc_pc, sc->sc_tag, PCI_COMMAND_STATUS_REG, command); 366 } 367 368 void 369 pccbbattach(struct device *parent, struct device *self, void *aux) 370 { 371 struct pccbb_softc *sc = (void *)self; 372 struct pci_attach_args *pa = aux; 373 pci_chipset_tag_t pc = pa->pa_pc; 374 pci_intr_handle_t ih; 375 const char *intrstr = NULL; 376 int flags; 377 378 pccbb_attach_hook(parent, self, pa); 379 380 sc->sc_chipset = cb_chipset(pa->pa_id, &flags); 381 sc->sc_id = pa->pa_id; 382 383 #ifdef CBB_DEBUG 384 printf(" (chipflags %x)", flags); 385 #endif 386 387 TAILQ_INIT(&sc->sc_memwindow); 388 TAILQ_INIT(&sc->sc_iowindow); 389 390 sc->sc_rbus_iot = rbus_pccbb_parent_io(self, pa); 391 sc->sc_rbus_memt = rbus_pccbb_parent_mem(self, pa); 392 393 /* 394 * MAP socket registers and ExCA registers on memory-space 395 */ 396 if (pci_mapreg_map(pa, PCI_SOCKBASE, PCI_MAPREG_TYPE_MEM, 0, 397 &sc->sc_base_memt, &sc->sc_base_memh, NULL, NULL, 0)) { 398 printf("can't map registers\n"); 399 return; 400 } 401 402 sc->sc_busnum = pci_conf_read(pc, pa->pa_tag, PCI_BUSNUM); 403 404 #if defined CBB_DEBUG 405 { 406 static char *intrname[5] = { "NON", "A", "B", "C", "D" }; 407 printf(": intrpin %s, line %d\n", 408 intrname[pa->pa_intrpin], pa->pa_intrline); 409 } 410 #endif 411 412 /* setup softc */ 413 sc->sc_pc = pc; 414 sc->sc_iot = pa->pa_iot; 415 sc->sc_memt = pa->pa_memt; 416 sc->sc_dmat = pa->pa_dmat; 417 sc->sc_tag = pa->pa_tag; 418 sc->sc_function = pa->pa_function; 419 sc->sc_intrtag = pa->pa_intrtag; 420 sc->sc_intrpin = pa->pa_intrpin; 421 422 sc->sc_pcmcia_flags = flags; /* set PCMCIA facility */ 423 424 /* Map and establish the interrupt. */ 425 if (pci_intr_map(pa, &ih)) { 426 printf(": couldn't map interrupt\n"); 427 return; 428 } 429 intrstr = pci_intr_string(pc, ih); 430 /* must do this after intr is mapped and established */ 431 sc->sc_intrline = pci_intr_line(pc, ih); 432 433 /* 434 * XXX pccbbintr should be called under the priority lower 435 * than any other hard interrupts. 436 */ 437 sc->sc_ih = pci_intr_establish(pc, ih, IPL_BIO, pccbbintr, sc, 438 sc->sc_dev.dv_xname); 439 440 if (sc->sc_ih == NULL) { 441 printf(": couldn't establish interrupt"); 442 if (intrstr != NULL) { 443 printf(" at %s", intrstr); 444 } 445 printf("\n"); 446 return; 447 } 448 printf(": %s", intrstr); 449 450 /* 451 * When bus number isn't set correctly, give up using 32-bit CardBus 452 * mode. 453 */ 454 if (((sc->sc_busnum >> 8) & 0xff) == 0) { 455 printf(", CardBus support disabled"); 456 sc->sc_pcmcia_flags |= PCCBB_PCMCIA_16BITONLY; 457 } 458 459 printf("\n"); 460 461 /* Disable legacy register mapping. */ 462 pccbb_legacy_disable(sc); 463 464 timeout_set(&sc->sc_ins_tmo, pci113x_insert, sc); 465 config_defer(self, pccbb_pci_callback); 466 } 467 468 /* 469 * void pccbb_pci_callback(struct device *self) 470 * 471 * The actual attach routine: get memory space for YENTA register 472 * space, setup YENTA register and route interrupt. 473 * 474 * This function should be deferred because this device may obtain 475 * memory space dynamically. This function must avoid obtaining 476 * memory area which has already kept for another device. Also, 477 * this function MUST be done before ISA attach process because this 478 * function kills pcic compatible port used by ISA pcic. 479 */ 480 void 481 pccbb_pci_callback(struct device *self) 482 { 483 struct pccbb_softc *sc = (void *)self; 484 pci_chipset_tag_t pc = sc->sc_pc; 485 bus_space_tag_t base_memt; 486 bus_space_handle_t base_memh; 487 u_int32_t maskreg; 488 struct cbslot_attach_args cba; 489 struct pcmciabus_attach_args paa; 490 struct cardslot_attach_args caa; 491 struct cardslot_softc *csc; 492 u_int32_t sockstat; 493 494 base_memt = sc->sc_base_memt; /* socket regs memory tag */ 495 base_memh = sc->sc_base_memh; /* socket regs memory handle */ 496 497 /* bus bridge initialization */ 498 pccbb_chipinit(sc); 499 500 /* clear data structure for child device interrupt handlers */ 501 sc->sc_pil = NULL; 502 sc->sc_pil_intr_enable = 1; 503 504 sockstat = bus_space_read_4(base_memt, base_memh, CB_SOCKET_STAT); 505 if ((sockstat & CB_SOCKET_STAT_CD) == 0) 506 sc->sc_flags |= CBB_CARDEXIST; 507 508 /* 509 * attach cardbus 510 */ 511 if (!(sc->sc_pcmcia_flags & PCCBB_PCMCIA_16BITONLY)) { 512 pcireg_t busreg = pci_conf_read(pc, sc->sc_tag, PCI_BUSNUM); 513 pcireg_t bhlc = pci_conf_read(pc, sc->sc_tag, PCI_BHLC_REG); 514 515 /* initialize cbslot_attach */ 516 cba.cba_busname = "cardbus"; 517 cba.cba_iot = sc->sc_iot; 518 cba.cba_memt = sc->sc_memt; 519 cba.cba_dmat = sc->sc_dmat; 520 cba.cba_bus = (busreg >> 8) & 0x0ff; 521 cba.cba_cc = (void *)sc; 522 cba.cba_pc = sc->sc_pc; 523 cba.cba_cf = &pccbb_funcs; 524 cba.cba_intrline = sc->sc_intrline; 525 526 cba.cba_rbus_iot = sc->sc_rbus_iot; 527 cba.cba_rbus_memt = sc->sc_rbus_memt; 528 529 cba.cba_cacheline = PCI_CACHELINE(bhlc); 530 cba.cba_lattimer = PCI_CB_LATENCY(busreg); 531 532 #if defined CBB_DEBUG 533 printf("%s: cacheline 0x%x lattimer 0x%x\n", 534 sc->sc_dev.dv_xname, cba.cba_cacheline, cba.cba_lattimer); 535 printf("%s: bhlc 0x%x lscp 0x%x\n", sc->sc_dev.dv_xname, bhlc, 536 busreg); 537 #endif 538 #if defined SHOW_REGS 539 cb_show_regs(sc->sc_pc, sc->sc_tag, sc->sc_base_memt, 540 sc->sc_base_memh); 541 #endif 542 } 543 544 pccbb_pcmcia_attach_setup(sc, &paa); 545 caa.caa_cb_attach = NULL; 546 if (!(sc->sc_pcmcia_flags & PCCBB_PCMCIA_16BITONLY)) { 547 caa.caa_cb_attach = &cba; 548 } 549 caa.caa_16_attach = &paa; 550 caa.caa_ph = &sc->sc_pcmcia_h; 551 552 if (NULL != (csc = (void *)config_found(self, &caa, cbbprint))) { 553 DPRINTF(("pccbbattach: found cardslot\n")); 554 sc->sc_csc = csc; 555 } 556 557 sc->sc_ints_on = 1; 558 559 /* CSC Interrupt: Card detect interrupt on */ 560 maskreg = bus_space_read_4(base_memt, base_memh, CB_SOCKET_MASK); 561 maskreg |= CB_SOCKET_MASK_CD; /* Card detect intr is turned on. */ 562 bus_space_write_4(base_memt, base_memh, CB_SOCKET_MASK, maskreg); 563 /* reset interrupt */ 564 bus_space_write_4(base_memt, base_memh, CB_SOCKET_EVENT, 565 bus_space_read_4(base_memt, base_memh, CB_SOCKET_EVENT)); 566 567 return; 568 } 569 570 void 571 pccbb_legacy_disable(struct pccbb_softc *sc) 572 { 573 pcireg_t reg; 574 575 switch (sc->sc_chipset) { 576 case CB_RX5C46X: 577 /* 578 * The legacy pcic io-port on Ricoh RX5C46X CardBus bridges 579 * cannot be disabled by substituting 0 into PCI_LEGACY 580 * register. Ricoh CardBus bridges have special bits on Bridge 581 * control reg (addr 0x3e on PCI config space). 582 */ 583 reg = pci_conf_read(sc->sc_pc, sc->sc_tag, PCI_BCR_INTR); 584 reg &= ~(CB_BCRI_RL_3E0_ENA | CB_BCRI_RL_3E2_ENA); 585 pci_conf_write(sc->sc_pc, sc->sc_tag, PCI_BCR_INTR, reg); 586 break; 587 588 default: 589 pci_conf_write(sc->sc_pc, sc->sc_tag, PCI_LEGACY, 0x0); 590 break; 591 } 592 } 593 594 /* 595 * void pccbb_chipinit(struct pccbb_softc *sc) 596 * 597 * This function initialize YENTA chip registers listed below: 598 * 1) PCI command reg, 599 * 2) PCI and CardBus latency timer, 600 * 3) route PCI interrupt, 601 * 4) close all memory and io windows. 602 */ 603 void 604 pccbb_chipinit(struct pccbb_softc *sc) 605 { 606 pci_chipset_tag_t pc = sc->sc_pc; 607 pcitag_t tag = sc->sc_tag; 608 pcireg_t reg; 609 610 /* Power on the controller if the BIOS didn't */ 611 pci_set_powerstate(pc, tag, PCI_PMCSR_STATE_D0); 612 613 /* 614 * Set PCI command reg. 615 * Some laptop's BIOSes (i.e. TICO) do not enable CardBus chip. 616 */ 617 reg = pci_conf_read(pc, tag, PCI_COMMAND_STATUS_REG); 618 /* I believe it is harmless. */ 619 reg |= (PCI_COMMAND_IO_ENABLE | PCI_COMMAND_MEM_ENABLE | 620 PCI_COMMAND_MASTER_ENABLE); 621 pci_conf_write(pc, tag, PCI_COMMAND_STATUS_REG, reg); 622 623 /* 624 * Set CardBus latency timer. 625 */ 626 reg = pci_conf_read(pc, tag, PCI_CB_LSCP_REG); 627 if (PCI_CB_LATENCY(reg) < 0x20) { 628 reg &= ~(PCI_CB_LATENCY_MASK << PCI_CB_LATENCY_SHIFT); 629 reg |= (0x20 << PCI_CB_LATENCY_SHIFT); 630 pci_conf_write(pc, tag, PCI_CB_LSCP_REG, reg); 631 } 632 DPRINTF(("CardBus latency timer 0x%x (%x)\n", 633 PCI_CB_LATENCY(reg), pci_conf_read(pc, tag, PCI_CB_LSCP_REG))); 634 635 /* 636 * Set PCI latency timer. 637 */ 638 reg = pci_conf_read(pc, tag, PCI_BHLC_REG); 639 if (PCI_LATTIMER(reg) < 0x10) { 640 reg &= ~(PCI_LATTIMER_MASK << PCI_LATTIMER_SHIFT); 641 reg |= (0x10 << PCI_LATTIMER_SHIFT); 642 pci_conf_write(pc, tag, PCI_BHLC_REG, reg); 643 } 644 DPRINTF(("PCI latency timer 0x%x (%x)\n", 645 PCI_LATTIMER(reg), pci_conf_read(pc, tag, PCI_BHLC_REG))); 646 647 /* Route functional interrupts to PCI. */ 648 reg = pci_conf_read(pc, tag, PCI_BCR_INTR); 649 reg |= CB_BCR_INTR_IREQ_ENABLE; /* disable PCI Intr */ 650 reg |= CB_BCR_WRITE_POST_ENABLE; /* enable write post */ 651 reg |= CB_BCR_RESET_ENABLE; /* assert reset */ 652 pci_conf_write(pc, tag, PCI_BCR_INTR, reg); 653 654 switch (sc->sc_chipset) { 655 case CB_TI113X: 656 reg = pci_conf_read(pc, tag, PCI_CBCTRL); 657 /* This bit is shared, but may read as 0 on some chips, so set 658 it explicitly on both functions. */ 659 reg |= PCI113X_CBCTRL_PCI_IRQ_ENA; 660 /* CSC intr enable */ 661 reg |= PCI113X_CBCTRL_PCI_CSC; 662 /* functional intr prohibit | prohibit ISA routing */ 663 reg &= ~(PCI113X_CBCTRL_PCI_INTR | PCI113X_CBCTRL_INT_MASK); 664 pci_conf_write(pc, tag, PCI_CBCTRL, reg); 665 break; 666 667 case CB_TI12XX: 668 /* 669 * Some TI 12xx (and [14][45]xx) based pci cards 670 * sometimes have issues with the MFUNC register not 671 * being initialized due to a bad EEPROM on board. 672 * Laptops that this matters on have this register 673 * properly initialized. 674 * 675 * The TI125X parts have a different register. 676 */ 677 reg = pci_conf_read(pc, tag, PCI12XX_MFUNC); 678 if (reg == PCI12XX_MFUNC_DEFAULT) { 679 reg &= ~PCI12XX_MFUNC_PIN0; 680 reg |= PCI12XX_MFUNC_PIN0_INTA; 681 if ((pci_conf_read(pc, tag, PCI_SYSCTRL) & 682 PCI12XX_SYSCTRL_INTRTIE) == 0) { 683 reg &= ~PCI12XX_MFUNC_PIN1; 684 reg |= PCI12XX_MFUNC_PIN1_INTB; 685 } 686 pci_conf_write(pc, tag, PCI12XX_MFUNC, reg); 687 } 688 /* FALLTHROUGH */ 689 690 case CB_TI125X: 691 /* 692 * Disable zoom video. Some machines initialize this 693 * improperly and experience has shown that this helps 694 * prevent strange behavior. 695 */ 696 pci_conf_write(pc, tag, PCI12XX_MMCTRL, 0); 697 698 reg = pci_conf_read(pc, tag, PCI_SYSCTRL); 699 reg |= PCI12XX_SYSCTRL_VCCPROT; 700 pci_conf_write(pc, tag, PCI_SYSCTRL, reg); 701 reg = pci_conf_read(pc, tag, PCI_CBCTRL); 702 reg |= PCI12XX_CBCTRL_CSC; 703 pci_conf_write(pc, tag, PCI_CBCTRL, reg); 704 break; 705 706 case CB_TOPIC95B: 707 reg = pci_conf_read(pc, tag, TOPIC_SOCKET_CTRL); 708 reg |= TOPIC_SOCKET_CTRL_SCR_IRQSEL; 709 pci_conf_write(pc, tag, TOPIC_SOCKET_CTRL, reg); 710 711 reg = pci_conf_read(pc, tag, TOPIC_SLOT_CTRL); 712 DPRINTF(("%s: topic slot ctrl reg 0x%x -> ", 713 sc->sc_dev.dv_xname, reg)); 714 reg |= (TOPIC_SLOT_CTRL_SLOTON | TOPIC_SLOT_CTRL_SLOTEN | 715 TOPIC_SLOT_CTRL_ID_LOCK | TOPIC_SLOT_CTRL_CARDBUS); 716 reg &= ~TOPIC_SLOT_CTRL_SWDETECT; 717 DPRINTF(("0x%x\n", reg)); 718 pci_conf_write(pc, tag, TOPIC_SLOT_CTRL, reg); 719 break; 720 721 case CB_TOPIC97: 722 reg = pci_conf_read(pc, tag, TOPIC_SLOT_CTRL); 723 DPRINTF(("%s: topic slot ctrl reg 0x%x -> ", 724 sc->sc_dev.dv_xname, reg)); 725 reg |= (TOPIC_SLOT_CTRL_SLOTON | TOPIC_SLOT_CTRL_SLOTEN | 726 TOPIC_SLOT_CTRL_ID_LOCK | TOPIC_SLOT_CTRL_CARDBUS); 727 reg &= ~TOPIC_SLOT_CTRL_SWDETECT; 728 reg |= TOPIC97_SLOT_CTRL_PCIINT; 729 reg &= ~(TOPIC97_SLOT_CTRL_STSIRQP | TOPIC97_SLOT_CTRL_IRQP); 730 DPRINTF(("0x%x\n", reg)); 731 pci_conf_write(pc, tag, TOPIC_SLOT_CTRL, reg); 732 733 /* make sure to assert LV card support bits */ 734 bus_space_write_1(sc->sc_base_memt, sc->sc_base_memh, 735 0x800 + 0x3e, bus_space_read_1(sc->sc_base_memt, 736 sc->sc_base_memh, 0x800 + 0x3e) | 0x03); 737 break; 738 739 case CB_OLDO2MICRO: 740 /* 741 * older bridges have problems with both read prefetch and 742 * write bursting depending on the combination of the chipset, 743 * bridge and the cardbus card. so disable them to be on the 744 * safe side. One example is O2Micro 6812 with Atheros AR5012 745 * chipsets 746 */ 747 DPRINTF(("%s: old O2Micro bridge found\n", 748 sc->sc_dev.dv_xname, reg)); 749 reg = pci_conf_read(pc, tag, O2MICRO_RESERVED1); 750 pci_conf_write(pc, tag, O2MICRO_RESERVED1, reg & 751 ~(O2MICRO_RES_READ_PREFETCH | O2MICRO_RES_WRITE_BURST)); 752 reg = pci_conf_read(pc, tag, O2MICRO_RESERVED2); 753 pci_conf_write(pc, tag, O2MICRO_RESERVED2, reg & 754 ~(O2MICRO_RES_READ_PREFETCH | O2MICRO_RES_WRITE_BURST)); 755 break; 756 } 757 758 /* Close all memory and I/O windows. */ 759 pci_conf_write(pc, tag, PCI_CB_MEMBASE0, 0xffffffff); 760 pci_conf_write(pc, tag, PCI_CB_MEMLIMIT0, 0); 761 pci_conf_write(pc, tag, PCI_CB_MEMBASE1, 0xffffffff); 762 pci_conf_write(pc, tag, PCI_CB_MEMLIMIT1, 0); 763 pci_conf_write(pc, tag, PCI_CB_IOBASE0, 0xffffffff); 764 pci_conf_write(pc, tag, PCI_CB_IOLIMIT0, 0); 765 pci_conf_write(pc, tag, PCI_CB_IOBASE1, 0xffffffff); 766 pci_conf_write(pc, tag, PCI_CB_IOLIMIT1, 0); 767 768 /* reset 16-bit pcmcia bus */ 769 bus_space_write_1(sc->sc_base_memt, sc->sc_base_memh, 770 0x800 + PCIC_INTR, 771 bus_space_read_1(sc->sc_base_memt, sc->sc_base_memh, 772 0x800 + PCIC_INTR) & ~PCIC_INTR_RESET); 773 774 /* turn off power */ 775 pccbb_power((cardbus_chipset_tag_t)sc, CARDBUS_VCC_0V | CARDBUS_VPP_0V); 776 } 777 778 779 780 781 /* 782 * void pccbb_pcmcia_attach_setup(struct pccbb_softc *sc, 783 * struct pcmciabus_attach_args *paa) 784 * 785 * This function attaches 16-bit PCcard bus. 786 */ 787 void 788 pccbb_pcmcia_attach_setup(struct pccbb_softc *sc, 789 struct pcmciabus_attach_args *paa) 790 { 791 struct pcic_handle *ph = &sc->sc_pcmcia_h; 792 rbus_tag_t rb; 793 794 /* initialize pcmcia part in pccbb_softc */ 795 ph->ph_parent = (struct device *)sc; 796 ph->sock = sc->sc_function; 797 ph->flags = 0; 798 ph->shutdown = 0; 799 ph->ih_irq = sc->sc_intrline; 800 ph->ph_bus_t = sc->sc_base_memt; 801 ph->ph_bus_h = sc->sc_base_memh; 802 ph->ph_read = pccbb_pcmcia_read; 803 ph->ph_write = pccbb_pcmcia_write; 804 sc->sc_pct = &pccbb_pcmcia_funcs; 805 806 /* 807 * We need to do a few things here: 808 * 1) Disable routing of CSC and functional interrupts to ISA IRQs by 809 * setting the IRQ numbers to 0. 810 * 2) Set bit 4 of PCIC_INTR, which is needed on some chips to enable 811 * routing of CSC interrupts (e.g. card removal) to PCI while in 812 * PCMCIA mode. We just leave this set all the time. 813 * 3) Enable card insertion/removal interrupts in case the chip also 814 * needs that while in PCMCIA mode. 815 * 4) Clear any pending CSC interrupt. 816 */ 817 Pcic_write(ph, PCIC_INTR, PCIC_INTR_ENABLE | PCIC_INTR_RESET); 818 if (sc->sc_chipset == CB_TI113X) { 819 Pcic_write(ph, PCIC_CSC_INTR, 0); 820 } else { 821 Pcic_write(ph, PCIC_CSC_INTR, PCIC_CSC_INTR_CD_ENABLE); 822 Pcic_read(ph, PCIC_CSC); 823 } 824 825 /* initialize pcmcia bus attachment */ 826 paa->paa_busname = "pcmcia"; 827 paa->pct = sc->sc_pct; 828 paa->pch = ph; 829 paa->iobase = 0; /* I don't use them */ 830 paa->iosize = 0; 831 rb = ((struct pccbb_softc *)(ph->ph_parent))->sc_rbus_iot; 832 paa->iobase = rb->rb_start + rb->rb_offset; 833 paa->iosize = rb->rb_end - rb->rb_start; 834 835 return; 836 } 837 838 #if 0 839 void 840 pccbb_pcmcia_attach_card(struct pcic_handle *ph) 841 { 842 if (ph->flags & PCIC_FLAG_CARDP) { 843 panic("pccbb_pcmcia_attach_card: already attached"); 844 } 845 846 /* call the MI attach function */ 847 pcmcia_card_attach(ph->pcmcia); 848 849 ph->flags |= PCIC_FLAG_CARDP; 850 } 851 852 void 853 pccbb_pcmcia_detach_card(struct pcic_handle *ph, int flags) 854 { 855 if (!(ph->flags & PCIC_FLAG_CARDP)) { 856 panic("pccbb_pcmcia_detach_card: already detached"); 857 } 858 859 ph->flags &= ~PCIC_FLAG_CARDP; 860 861 /* call the MI detach function */ 862 pcmcia_card_detach(ph->pcmcia, flags); 863 } 864 #endif 865 866 int 867 pccbb_checksockstat(struct pccbb_softc *sc) 868 { 869 u_int32_t sockstate; 870 871 sockstate = bus_space_read_4(sc->sc_base_memt, sc->sc_base_memh, 872 CB_SOCKET_STAT); 873 874 if ((sockstate & CB_SOCKET_STAT_CD) != 0) { 875 /* A card should be removed. */ 876 if (sc->sc_flags & CBB_CARDEXIST) { 877 DPRINTF(("%s: card removed, 0x%08x\n", 878 sc->sc_dev.dv_xname, sockstate)); 879 sc->sc_flags &= ~CBB_CARDEXIST; 880 if (sc->sc_csc->sc_status & CARDSLOT_STATUS_CARD_16) { 881 #if 0 882 struct pcic_handle *ph = 883 &sc->sc_pcmcia_h; 884 885 pcmcia_card_deactivate(ph->pcmcia); 886 pccbb_pcmcia_socket_disable(ph); 887 pccbb_pcmcia_detach_card(ph, 888 DETACH_FORCE); 889 #endif 890 cardslot_event_throw(sc->sc_csc, 891 CARDSLOT_EVENT_REMOVAL_16); 892 } else if (sc->sc_csc->sc_status & 893 CARDSLOT_STATUS_CARD_CB) { 894 /* Cardbus intr removed */ 895 cardslot_event_throw(sc->sc_csc, 896 CARDSLOT_EVENT_REMOVAL_CB); 897 } 898 } 899 return (1); 900 } else if ((sockstate & CB_SOCKET_STAT_CD) == 0 && 901 (sc->sc_flags & CBB_CARDEXIST) == 0) { 902 timeout_add_msec(&sc->sc_ins_tmo, 100); 903 sc->sc_flags |= CBB_INSERTING; 904 return (1); 905 } 906 return (0); 907 } 908 909 /* 910 * int pccbbintr(arg) 911 * void *arg; 912 * This routine handles the interrupt from Yenta PCI-CardBus bridge 913 * itself. 914 */ 915 int 916 pccbbintr(void *arg) 917 { 918 struct pccbb_softc *sc = (struct pccbb_softc *)arg; 919 u_int32_t sockevent; 920 struct pcic_handle *ph = &sc->sc_pcmcia_h; 921 922 if (!sc->sc_ints_on) 923 return 0; 924 925 sockevent = bus_space_read_4(sc->sc_base_memt, sc->sc_base_memh, 926 CB_SOCKET_EVENT); 927 bus_space_write_4(sc->sc_base_memt, sc->sc_base_memh, 928 CB_SOCKET_EVENT, sockevent); 929 Pcic_read(ph, PCIC_CSC); 930 931 if (sockevent & CB_SOCKET_EVENT_CD) { 932 if (pccbb_checksockstat(sc)) 933 return (1); 934 } 935 936 if (sc->sc_pil_intr_enable) 937 return pccbbintr_function(sc); 938 return (0); 939 } 940 941 /* 942 * int pccbbintr_function(struct pccbb_softc *sc) 943 * 944 * This function calls each interrupt handler registered at the 945 * bridge. The interrupt handlers are called in registered order. 946 */ 947 int 948 pccbbintr_function(struct pccbb_softc *sc) 949 { 950 int retval = 0, val; 951 struct pccbb_intrhand_list *pil; 952 int s, splchanged; 953 954 for (pil = sc->sc_pil; pil != NULL; pil = pil->pil_next) { 955 /* 956 * XXX priority change. gross. I use if-else 957 * sentences instead of switch-case sentences in order 958 * to avoid duplicate case value error. More than one 959 * IPL_XXX may use the same value. It depends on the 960 * implementation. 961 */ 962 splchanged = 1; 963 #if 0 964 if (pil->pil_level == IPL_SERIAL) { 965 s = splserial(); 966 } else if (pil->pil_level == IPL_HIGH) { 967 #endif 968 if (pil->pil_level == IPL_HIGH) { 969 s = splhigh(); 970 } else if (pil->pil_level == IPL_CLOCK) { 971 s = splclock(); 972 } else if (pil->pil_level == IPL_AUDIO) { 973 s = splaudio(); 974 } else if (pil->pil_level == IPL_VM) { 975 s = splvm(); 976 } else if (pil->pil_level == IPL_TTY) { 977 s = spltty(); 978 #if 0 979 } else if (pil->pil_level == IPL_SOFTSERIAL) { 980 s = splsoftserial(); 981 #endif 982 } else if (pil->pil_level == IPL_NET) { 983 s = splnet(); 984 } else { 985 splchanged = 0; 986 /* XXX: ih lower than IPL_BIO runs w/ IPL_BIO. */ 987 } 988 989 val = (*pil->pil_func)(pil->pil_arg); 990 if (val != 0) 991 pil->pil_count.ec_count++; 992 993 if (splchanged != 0) { 994 splx(s); 995 } 996 997 retval = retval == 1 ? 1 : 998 retval == 0 ? val : val != 0 ? val : retval; 999 } 1000 1001 return retval; 1002 } 1003 1004 void 1005 pci113x_insert(void *arg) 1006 { 1007 struct pccbb_softc *sc = (struct pccbb_softc *)arg; 1008 u_int32_t sockevent, sockstate; 1009 1010 sockevent = bus_space_read_4(sc->sc_base_memt, sc->sc_base_memh, 1011 CB_SOCKET_EVENT); 1012 sockstate = bus_space_read_4(sc->sc_base_memt, sc->sc_base_memh, 1013 CB_SOCKET_STAT); 1014 1015 if (0 == (sockstate & CB_SOCKET_STAT_CD)) { /* card exist */ 1016 DPRINTF(("%s: 0x%08x", sc->sc_dev.dv_xname, sockevent)); 1017 DPRINTF((" card inserted, 0x%08x\n", sockstate)); 1018 sc->sc_flags |= CBB_CARDEXIST; 1019 /* call pccard interrupt handler here */ 1020 if (sockstate & CB_SOCKET_STAT_16BIT) { 1021 /* 16-bit card found */ 1022 /* pccbb_pcmcia_attach_card(&sc->sc_pcmcia_h); */ 1023 cardslot_event_throw(sc->sc_csc, 1024 CARDSLOT_EVENT_INSERTION_16); 1025 } else if (sockstate & CB_SOCKET_STAT_CB) { 1026 /* cardbus card found */ 1027 /* cardbus_attach_card(sc->sc_csc); */ 1028 cardslot_event_throw(sc->sc_csc, 1029 CARDSLOT_EVENT_INSERTION_CB); 1030 } else { 1031 /* who are you? */ 1032 } 1033 } else { 1034 timeout_add_msec(&sc->sc_ins_tmo, 100); 1035 } 1036 } 1037 1038 #define PCCBB_PCMCIA_OFFSET 0x800 1039 u_int8_t 1040 pccbb_pcmcia_read(struct pcic_handle *ph, int reg) 1041 { 1042 bus_space_barrier(ph->ph_bus_t, ph->ph_bus_h, 1043 PCCBB_PCMCIA_OFFSET + reg, 1, BUS_SPACE_BARRIER_READ); 1044 1045 return bus_space_read_1(ph->ph_bus_t, ph->ph_bus_h, 1046 PCCBB_PCMCIA_OFFSET + reg); 1047 } 1048 1049 void 1050 pccbb_pcmcia_write(struct pcic_handle *ph, int reg, int val) 1051 { 1052 bus_space_barrier(ph->ph_bus_t, ph->ph_bus_h, 1053 PCCBB_PCMCIA_OFFSET + reg, 1, BUS_SPACE_BARRIER_WRITE); 1054 1055 bus_space_write_1(ph->ph_bus_t, ph->ph_bus_h, PCCBB_PCMCIA_OFFSET + reg, 1056 val); 1057 } 1058 1059 /* 1060 * int pccbb_ctrl(cardbus_chipset_tag_t, int) 1061 */ 1062 int 1063 pccbb_ctrl(cardbus_chipset_tag_t ct, int command) 1064 { 1065 struct pccbb_softc *sc = (struct pccbb_softc *)ct; 1066 1067 switch (command) { 1068 case CARDBUS_CD: 1069 if (2 == pccbb_detect_card(sc)) { 1070 int retval = 0; 1071 int status = cb_detect_voltage(sc); 1072 if (PCCARD_VCC_5V & status) { 1073 retval |= CARDBUS_5V_CARD; 1074 } 1075 if (PCCARD_VCC_3V & status) { 1076 retval |= CARDBUS_3V_CARD; 1077 } 1078 if (PCCARD_VCC_XV & status) { 1079 retval |= CARDBUS_XV_CARD; 1080 } 1081 if (PCCARD_VCC_YV & status) { 1082 retval |= CARDBUS_YV_CARD; 1083 } 1084 return retval; 1085 } else { 1086 return 0; 1087 } 1088 break; 1089 case CARDBUS_RESET: 1090 return cb_reset(sc); 1091 break; 1092 case CARDBUS_IO_ENABLE: /* fallthrough */ 1093 case CARDBUS_IO_DISABLE: /* fallthrough */ 1094 case CARDBUS_MEM_ENABLE: /* fallthrough */ 1095 case CARDBUS_MEM_DISABLE: /* fallthrough */ 1096 case CARDBUS_BM_ENABLE: /* fallthrough */ 1097 case CARDBUS_BM_DISABLE: /* fallthrough */ 1098 return pccbb_cardenable(sc, command); 1099 break; 1100 } 1101 1102 return 0; 1103 } 1104 1105 /* 1106 * int pccbb_power(cardbus_chipset_tag_t, int) 1107 * This function returns true when it succeeds and returns false when 1108 * it fails. 1109 */ 1110 int 1111 pccbb_power(cardbus_chipset_tag_t ct, int command) 1112 { 1113 struct pccbb_softc *sc = (struct pccbb_softc *)ct; 1114 1115 u_int32_t status, sock_ctrl; 1116 bus_space_tag_t memt = sc->sc_base_memt; 1117 bus_space_handle_t memh = sc->sc_base_memh; 1118 1119 DPRINTF(("pccbb_power: %s and %s [%x]\n", 1120 (command & CARDBUS_VCCMASK) == CARDBUS_VCC_UC ? "CARDBUS_VCC_UC" : 1121 (command & CARDBUS_VCCMASK) == CARDBUS_VCC_5V ? "CARDBUS_VCC_5V" : 1122 (command & CARDBUS_VCCMASK) == CARDBUS_VCC_3V ? "CARDBUS_VCC_3V" : 1123 (command & CARDBUS_VCCMASK) == CARDBUS_VCC_XV ? "CARDBUS_VCC_XV" : 1124 (command & CARDBUS_VCCMASK) == CARDBUS_VCC_YV ? "CARDBUS_VCC_YV" : 1125 (command & CARDBUS_VCCMASK) == CARDBUS_VCC_0V ? "CARDBUS_VCC_0V" : 1126 "UNKNOWN", 1127 (command & CARDBUS_VPPMASK) == CARDBUS_VPP_UC ? "CARDBUS_VPP_UC" : 1128 (command & CARDBUS_VPPMASK) == CARDBUS_VPP_12V ? "CARDBUS_VPP_12V" : 1129 (command & CARDBUS_VPPMASK) == CARDBUS_VPP_VCC ? "CARDBUS_VPP_VCC" : 1130 (command & CARDBUS_VPPMASK) == CARDBUS_VPP_0V ? "CARDBUS_VPP_0V" : 1131 "UNKNOWN", command)); 1132 1133 status = bus_space_read_4(memt, memh, CB_SOCKET_STAT); 1134 sock_ctrl = bus_space_read_4(memt, memh, CB_SOCKET_CTRL); 1135 1136 switch (command & CARDBUS_VCCMASK) { 1137 case CARDBUS_VCC_UC: 1138 break; 1139 case CARDBUS_VCC_5V: 1140 if (CB_SOCKET_STAT_5VCARD & status) { /* check 5 V card */ 1141 sock_ctrl &= ~CB_SOCKET_CTRL_VCCMASK; 1142 sock_ctrl |= CB_SOCKET_CTRL_VCC_5V; 1143 } else { 1144 printf("%s: BAD voltage request: no 5 V card\n", 1145 sc->sc_dev.dv_xname); 1146 } 1147 break; 1148 case CARDBUS_VCC_3V: 1149 if (CB_SOCKET_STAT_3VCARD & status) { 1150 sock_ctrl &= ~CB_SOCKET_CTRL_VCCMASK; 1151 sock_ctrl |= CB_SOCKET_CTRL_VCC_3V; 1152 } else { 1153 printf("%s: BAD voltage request: no 3.3 V card\n", 1154 sc->sc_dev.dv_xname); 1155 } 1156 break; 1157 case CARDBUS_VCC_0V: 1158 sock_ctrl &= ~CB_SOCKET_CTRL_VCCMASK; 1159 break; 1160 default: 1161 return 0; /* power NEVER changed */ 1162 break; 1163 } 1164 1165 switch (command & CARDBUS_VPPMASK) { 1166 case CARDBUS_VPP_UC: 1167 break; 1168 case CARDBUS_VPP_0V: 1169 sock_ctrl &= ~CB_SOCKET_CTRL_VPPMASK; 1170 break; 1171 case CARDBUS_VPP_VCC: 1172 sock_ctrl &= ~CB_SOCKET_CTRL_VPPMASK; 1173 sock_ctrl |= ((sock_ctrl >> 4) & 0x07); 1174 break; 1175 case CARDBUS_VPP_12V: 1176 sock_ctrl &= ~CB_SOCKET_CTRL_VPPMASK; 1177 sock_ctrl |= CB_SOCKET_CTRL_VPP_12V; 1178 break; 1179 } 1180 1181 #if 0 1182 DPRINTF(("sock_ctrl: %x\n", sock_ctrl)); 1183 #endif 1184 bus_space_write_4(memt, memh, CB_SOCKET_CTRL, sock_ctrl); 1185 status = bus_space_read_4(memt, memh, CB_SOCKET_STAT); 1186 1187 if (status & CB_SOCKET_STAT_BADVCC) { /* bad Vcc request */ 1188 printf 1189 ("%s: bad Vcc request. sock_ctrl 0x%x, sock_status 0x%x\n", 1190 sc->sc_dev.dv_xname, sock_ctrl, status); 1191 DPRINTF(("pccbb_power: %s and %s [%x]\n", 1192 (command & CARDBUS_VCCMASK) == 1193 CARDBUS_VCC_UC ? "CARDBUS_VCC_UC" : (command & 1194 CARDBUS_VCCMASK) == 1195 CARDBUS_VCC_5V ? "CARDBUS_VCC_5V" : (command & 1196 CARDBUS_VCCMASK) == 1197 CARDBUS_VCC_3V ? "CARDBUS_VCC_3V" : (command & 1198 CARDBUS_VCCMASK) == 1199 CARDBUS_VCC_XV ? "CARDBUS_VCC_XV" : (command & 1200 CARDBUS_VCCMASK) == 1201 CARDBUS_VCC_YV ? "CARDBUS_VCC_YV" : (command & 1202 CARDBUS_VCCMASK) == 1203 CARDBUS_VCC_0V ? "CARDBUS_VCC_0V" : "UNKNOWN", 1204 (command & CARDBUS_VPPMASK) == 1205 CARDBUS_VPP_UC ? "CARDBUS_VPP_UC" : (command & 1206 CARDBUS_VPPMASK) == 1207 CARDBUS_VPP_12V ? "CARDBUS_VPP_12V" : (command & 1208 CARDBUS_VPPMASK) == 1209 CARDBUS_VPP_VCC ? "CARDBUS_VPP_VCC" : (command & 1210 CARDBUS_VPPMASK) == 1211 CARDBUS_VPP_0V ? "CARDBUS_VPP_0V" : "UNKNOWN", command)); 1212 #if 0 1213 if (command == (CARDBUS_VCC_0V | CARDBUS_VPP_0V)) { 1214 u_int32_t force = 1215 bus_space_read_4(memt, memh, CB_SOCKET_FORCE); 1216 /* Reset Bad Vcc request */ 1217 force &= ~CB_SOCKET_FORCE_BADVCC; 1218 bus_space_write_4(memt, memh, CB_SOCKET_FORCE, force); 1219 printf("new status 0x%x\n", bus_space_read_4(memt, memh, 1220 CB_SOCKET_STAT)); 1221 return 1; 1222 } 1223 #endif 1224 return 0; 1225 } 1226 1227 /* 1228 * XXX delay 300 ms: though the standard defines that the Vcc set-up 1229 * time is 20 ms, some PC-Card bridge requires longer duration. 1230 */ 1231 delay(300 * 1000); 1232 1233 return 1; /* power changed correctly */ 1234 } 1235 1236 #if defined CB_PCMCIA_POLL 1237 struct cb_poll_str { 1238 void *arg; 1239 int (*func)(void *); 1240 int level; 1241 pccard_chipset_tag_t ct; 1242 int count; 1243 }; 1244 1245 static struct cb_poll_str cb_poll[10]; 1246 static int cb_poll_n = 0; 1247 static struct timeout cb_poll_timeout; 1248 1249 void cb_pcmcia_poll(void *arg); 1250 1251 void 1252 cb_pcmcia_poll(void *arg) 1253 { 1254 struct cb_poll_str *poll = arg; 1255 struct cbb_pcmcia_softc *psc = (void *)poll->ct->v; 1256 struct pccbb_softc *sc = psc->cpc_parent; 1257 int s; 1258 u_int32_t spsr; /* socket present-state reg */ 1259 1260 timeout_set(&cb_poll_timeout, cb_pcmcia_poll, arg); 1261 timeout_add(&cb_poll_timeout, hz / 10); 1262 switch (poll->level) { 1263 case IPL_NET: 1264 s = splnet(); 1265 break; 1266 case IPL_BIO: 1267 s = splbio(); 1268 break; 1269 case IPL_TTY: /* fallthrough */ 1270 default: 1271 s = spltty(); 1272 break; 1273 } 1274 1275 spsr = 1276 bus_space_read_4(sc->sc_base_memt, sc->sc_base_memh, 1277 CB_SOCKET_STAT); 1278 1279 #if defined CB_PCMCIA_POLL_ONLY && defined LEVEL2 1280 if (!(spsr & 0x40)) { /* CINT low */ 1281 #else 1282 if (1) { 1283 #endif 1284 if ((*poll->func) (poll->arg) == 1) { 1285 ++poll->count; 1286 printf("intr: reported from poller, 0x%x\n", spsr); 1287 #if defined LEVEL2 1288 } else { 1289 printf("intr: miss! 0x%x\n", spsr); 1290 #endif 1291 } 1292 } 1293 splx(s); 1294 } 1295 #endif /* defined CB_PCMCIA_POLL */ 1296 1297 /* 1298 * int pccbb_detect_card(struct pccbb_softc *sc) 1299 * return value: 0 if no card exists. 1300 * 1 if 16-bit card exists. 1301 * 2 if cardbus card exists. 1302 */ 1303 int 1304 pccbb_detect_card(struct pccbb_softc *sc) 1305 { 1306 bus_space_handle_t base_memh = sc->sc_base_memh; 1307 bus_space_tag_t base_memt = sc->sc_base_memt; 1308 u_int32_t sockstat = 1309 bus_space_read_4(base_memt, base_memh, CB_SOCKET_STAT); 1310 int retval = 0; 1311 1312 /* 1313 * The SCM Microsystems TI1225-based PCI-CardBus dock card that 1314 * ships with some Lucent WaveLAN cards has only one physical slot 1315 * but OpenBSD probes two. The phantom card in the second slot can 1316 * be ignored by punting on unsupported voltages. 1317 */ 1318 if (sockstat & CB_SOCKET_STAT_XVCARD) 1319 return 0; 1320 1321 /* CD1 and CD2 asserted */ 1322 if (0x00 == (sockstat & CB_SOCKET_STAT_CD)) { 1323 /* card must be present */ 1324 if (!(CB_SOCKET_STAT_NOTCARD & sockstat)) { 1325 /* NOTACARD DEASSERTED */ 1326 if (CB_SOCKET_STAT_CB & sockstat) { 1327 /* CardBus mode */ 1328 retval = 2; 1329 } else if (CB_SOCKET_STAT_16BIT & sockstat) { 1330 /* 16-bit mode */ 1331 retval = 1; 1332 } 1333 } 1334 } 1335 return retval; 1336 } 1337 1338 /* 1339 * int cb_reset(struct pccbb_softc *sc) 1340 * This function resets CardBus card. 1341 */ 1342 int 1343 cb_reset(struct pccbb_softc *sc) 1344 { 1345 /* 1346 * Reset Assert at least 20 ms 1347 * Some machines request longer duration. 1348 */ 1349 int reset_duration = (sc->sc_chipset == CB_RX5C47X ? 400 : 50); 1350 u_int32_t bcr = pci_conf_read(sc->sc_pc, sc->sc_tag, PCI_BCR_INTR); 1351 1352 /* Reset bit Assert (bit 6 at 0x3E) */ 1353 bcr |= CB_BCR_RESET_ENABLE; 1354 pci_conf_write(sc->sc_pc, sc->sc_tag, PCI_BCR_INTR, bcr); 1355 delay_ms(reset_duration, sc); 1356 1357 if (CBB_CARDEXIST & sc->sc_flags) { /* A card exists. Reset it! */ 1358 /* Reset bit Deassert (bit 6 at 0x3E) */ 1359 bcr &= ~CB_BCR_RESET_ENABLE; 1360 pci_conf_write(sc->sc_pc, sc->sc_tag, PCI_BCR_INTR, bcr); 1361 delay_ms(reset_duration, sc); 1362 } 1363 /* No card found on the slot. Keep Reset. */ 1364 return 1; 1365 } 1366 1367 /* 1368 * int cb_detect_voltage(struct pccbb_softc *sc) 1369 * This function detect card Voltage. 1370 */ 1371 int 1372 cb_detect_voltage(struct pccbb_softc *sc) 1373 { 1374 u_int32_t psr; /* socket present-state reg */ 1375 bus_space_tag_t iot = sc->sc_base_memt; 1376 bus_space_handle_t ioh = sc->sc_base_memh; 1377 int vol = PCCARD_VCC_UKN; /* set 0 */ 1378 1379 psr = bus_space_read_4(iot, ioh, CB_SOCKET_STAT); 1380 1381 if (0x400u & psr) { 1382 vol |= PCCARD_VCC_5V; 1383 } 1384 if (0x800u & psr) { 1385 vol |= PCCARD_VCC_3V; 1386 } 1387 1388 return vol; 1389 } 1390 1391 int 1392 cbbprint(void *aux, const char *pcic) 1393 { 1394 /* 1395 struct cbslot_attach_args *cba = aux; 1396 1397 if (cba->cba_slot >= 0) { 1398 printf(" slot %d", cba->cba_slot); 1399 } 1400 */ 1401 return UNCONF; 1402 } 1403 1404 /* 1405 * int pccbb_cardenable(struct pccbb_softc *sc, int function) 1406 * This function enables and disables the card 1407 */ 1408 int 1409 pccbb_cardenable(struct pccbb_softc *sc, int function) 1410 { 1411 u_int32_t command = 1412 pci_conf_read(sc->sc_pc, sc->sc_tag, PCI_COMMAND_STATUS_REG); 1413 1414 DPRINTF(("pccbb_cardenable:")); 1415 switch (function) { 1416 case CARDBUS_IO_ENABLE: 1417 command |= PCI_COMMAND_IO_ENABLE; 1418 break; 1419 case CARDBUS_IO_DISABLE: 1420 command &= ~PCI_COMMAND_IO_ENABLE; 1421 break; 1422 case CARDBUS_MEM_ENABLE: 1423 command |= PCI_COMMAND_MEM_ENABLE; 1424 break; 1425 case CARDBUS_MEM_DISABLE: 1426 command &= ~PCI_COMMAND_MEM_ENABLE; 1427 break; 1428 case CARDBUS_BM_ENABLE: 1429 command |= PCI_COMMAND_MASTER_ENABLE; 1430 break; 1431 case CARDBUS_BM_DISABLE: 1432 command &= ~PCI_COMMAND_MASTER_ENABLE; 1433 break; 1434 default: 1435 return 0; 1436 } 1437 1438 pci_conf_write(sc->sc_pc, sc->sc_tag, PCI_COMMAND_STATUS_REG, command); 1439 DPRINTF((" command reg 0x%x\n", command)); 1440 return 1; 1441 } 1442 1443 /* 1444 * void *pccbb_cb_intr_establish(cardbus_chipset_tag_t ct, 1445 * int irq, 1446 * int level, 1447 * int (* func)(void *), 1448 * void *arg, 1449 * const char *name) 1450 * 1451 * This function registers an interrupt handler at the bridge, in 1452 * order not to call the interrupt handlers of child devices when 1453 * a card-deletion interrupt occurs. 1454 * 1455 * The arguments irq is not used because pccbb selects intr vector. 1456 */ 1457 void * 1458 pccbb_cb_intr_establish(cardbus_chipset_tag_t ct, int irq, int level, 1459 int (*func)(void *), void *arg, const char *name) 1460 { 1461 struct pccbb_softc *sc = (struct pccbb_softc *)ct; 1462 1463 return pccbb_intr_establish(sc, irq, level, func, arg, name); 1464 } 1465 1466 1467 /* 1468 * void *pccbb_cb_intr_disestablish(cardbus_chipset_tag_t ct, 1469 * void *ih) 1470 * 1471 * This function removes an interrupt handler pointed by ih. 1472 */ 1473 void 1474 pccbb_cb_intr_disestablish(cardbus_chipset_tag_t ct, void *ih) 1475 { 1476 struct pccbb_softc *sc = (struct pccbb_softc *)ct; 1477 1478 pccbb_intr_disestablish(sc, ih); 1479 } 1480 1481 1482 /* 1483 * void *pccbb_intr_establish(struct pccbb_softc *sc, 1484 * int irq, 1485 * int level, 1486 * int (* func)(void *), 1487 * void *arg, 1488 * const char *name) 1489 * 1490 * This function registers an interrupt handler at the bridge, in 1491 * order not to call the interrupt handlers of child devices when 1492 * a card-deletion interrupt occurs. 1493 * 1494 * The arguments irq and level are not used. 1495 */ 1496 void * 1497 pccbb_intr_establish(struct pccbb_softc *sc, int irq, int level, 1498 int (*func)(void *), void *arg, const char *name) 1499 { 1500 struct pccbb_intrhand_list *pil, *newpil; 1501 pcireg_t reg; 1502 1503 DPRINTF(("pccbb_intr_establish start. %p\n", sc->sc_pil)); 1504 1505 if (sc->sc_pil == NULL) { 1506 /* initialize bridge intr routing */ 1507 reg = pci_conf_read(sc->sc_pc, sc->sc_tag, PCI_BCR_INTR); 1508 reg &= ~CB_BCR_INTR_IREQ_ENABLE; 1509 pci_conf_write(sc->sc_pc, sc->sc_tag, PCI_BCR_INTR, reg); 1510 1511 switch (sc->sc_chipset) { 1512 case CB_TI113X: 1513 reg = pci_conf_read(sc->sc_pc, sc->sc_tag, PCI_CBCTRL); 1514 /* functional intr enabled */ 1515 reg |= PCI113X_CBCTRL_PCI_INTR; 1516 pci_conf_write(sc->sc_pc, sc->sc_tag, PCI_CBCTRL, reg); 1517 break; 1518 default: 1519 break; 1520 } 1521 } 1522 1523 /* 1524 * Allocate a room for interrupt handler structure. 1525 */ 1526 newpil = (struct pccbb_intrhand_list *) 1527 malloc(sizeof(struct pccbb_intrhand_list), M_DEVBUF, M_WAITOK); 1528 1529 newpil->pil_func = func; 1530 newpil->pil_arg = arg; 1531 newpil->pil_level = level; 1532 evcount_attach(&newpil->pil_count, name, &sc->sc_intrline); 1533 newpil->pil_next = NULL; 1534 1535 if (sc->sc_pil == NULL) { 1536 sc->sc_pil = newpil; 1537 } else { 1538 for (pil = sc->sc_pil; pil->pil_next != NULL; 1539 pil = pil->pil_next); 1540 pil->pil_next = newpil; 1541 } 1542 1543 DPRINTF(("pccbb_intr_establish add pil. %p\n", sc->sc_pil)); 1544 1545 return newpil; 1546 } 1547 1548 /* 1549 * void *pccbb_intr_disestablish(struct pccbb_softc *sc, 1550 * void *ih) 1551 * 1552 * This function removes an interrupt handler pointed by ih. 1553 */ 1554 void 1555 pccbb_intr_disestablish(struct pccbb_softc *sc, void *ih) 1556 { 1557 struct pccbb_intrhand_list *pil, **pil_prev; 1558 pcireg_t reg; 1559 1560 DPRINTF(("pccbb_intr_disestablish start. %p\n", sc->sc_pil)); 1561 1562 pil_prev = &sc->sc_pil; 1563 1564 for (pil = sc->sc_pil; pil != NULL; pil = pil->pil_next) { 1565 if (pil == ih) { 1566 evcount_detach(&pil->pil_count); 1567 *pil_prev = pil->pil_next; 1568 free(pil, M_DEVBUF, 0); 1569 DPRINTF(("pccbb_intr_disestablish frees one pil\n")); 1570 break; 1571 } 1572 pil_prev = &pil->pil_next; 1573 } 1574 1575 if (sc->sc_pil == NULL) { 1576 /* No interrupt handlers */ 1577 1578 DPRINTF(("pccbb_intr_disestablish: no interrupt handler\n")); 1579 1580 /* stop routing PCI intr */ 1581 reg = pci_conf_read(sc->sc_pc, sc->sc_tag, PCI_BCR_INTR); 1582 reg |= CB_BCR_INTR_IREQ_ENABLE; 1583 pci_conf_write(sc->sc_pc, sc->sc_tag, PCI_BCR_INTR, reg); 1584 1585 switch (sc->sc_chipset) { 1586 case CB_TI113X: 1587 reg = pci_conf_read(sc->sc_pc, sc->sc_tag, PCI_CBCTRL); 1588 /* functional intr disabled */ 1589 reg &= ~PCI113X_CBCTRL_PCI_INTR; 1590 pci_conf_write(sc->sc_pc, sc->sc_tag, PCI_CBCTRL, reg); 1591 break; 1592 default: 1593 break; 1594 } 1595 } 1596 } 1597 1598 #if defined SHOW_REGS 1599 void 1600 cb_show_regs(pci_chipset_tag_t pc, pcitag_t tag, bus_space_tag_t memt, 1601 bus_space_handle_t memh) 1602 { 1603 int i; 1604 printf("PCI config regs:"); 1605 for (i = 0; i < 0x50; i += 4) { 1606 if (i % 16 == 0) { 1607 printf("\n 0x%02x:", i); 1608 } 1609 printf(" %08x", pci_conf_read(pc, tag, i)); 1610 } 1611 for (i = 0x80; i < 0xb0; i += 4) { 1612 if (i % 16 == 0) { 1613 printf("\n 0x%02x:", i); 1614 } 1615 printf(" %08x", pci_conf_read(pc, tag, i)); 1616 } 1617 1618 if (memh == 0) { 1619 printf("\n"); 1620 return; 1621 } 1622 1623 printf("\nsocket regs:"); 1624 for (i = 0; i <= 0x10; i += 0x04) { 1625 printf(" %08x", bus_space_read_4(memt, memh, i)); 1626 } 1627 printf("\nExCA regs:"); 1628 for (i = 0; i < 0x08; ++i) { 1629 printf(" %02x", bus_space_read_1(memt, memh, 0x800 + i)); 1630 } 1631 printf("\n"); 1632 return; 1633 } 1634 #endif 1635 1636 /* 1637 * int pccbb_pcmcia_io_alloc(pcmcia_chipset_handle_t pch, 1638 * bus_addr_t start, bus_size_t size, 1639 * bus_size_t align, 1640 * struct pcmcia_io_handle *pcihp 1641 * 1642 * This function only allocates I/O region for pccard. This function 1643 * never maps the allocated region to pccard I/O area. 1644 * 1645 * XXX: The interface of this function is not very good, I believe. 1646 */ 1647 int 1648 pccbb_pcmcia_io_alloc(pcmcia_chipset_handle_t pch, bus_addr_t start, 1649 bus_size_t size, bus_size_t align, struct pcmcia_io_handle *pcihp) 1650 { 1651 struct pcic_handle *ph = (struct pcic_handle *)pch; 1652 bus_addr_t ioaddr; 1653 int flags = 0; 1654 bus_space_tag_t iot; 1655 bus_space_handle_t ioh; 1656 bus_addr_t mask; 1657 rbus_tag_t rb; 1658 1659 if (align == 0) { 1660 align = size; /* XXX: funny??? */ 1661 } 1662 1663 if (start != 0) { 1664 /* XXX: assume all card decode lower 10 bits by its hardware */ 1665 mask = 0x3ff; 1666 /* enforce to use only masked address */ 1667 start &= mask; 1668 } else { 1669 /* 1670 * calculate mask: 1671 * 1. get the most significant bit of size (call it msb). 1672 * 2. compare msb with the value of size. 1673 * 3. if size is larger, shift msb left once. 1674 * 4. obtain mask value to decrement msb. 1675 */ 1676 bus_size_t size_tmp = size; 1677 int shifts = 0; 1678 1679 while (size_tmp) { 1680 ++shifts; 1681 size_tmp >>= 1; 1682 } 1683 mask = (1 << shifts); 1684 if (mask < size) { 1685 mask <<= 1; 1686 } 1687 mask--; 1688 } 1689 1690 /* 1691 * Allocate some arbitrary I/O space. 1692 */ 1693 1694 iot = ((struct pccbb_softc *)(ph->ph_parent))->sc_iot; 1695 1696 rb = ((struct pccbb_softc *)(ph->ph_parent))->sc_rbus_iot; 1697 if (rbus_space_alloc(rb, start, size, mask, align, 0, &ioaddr, &ioh)) { 1698 return 1; 1699 } 1700 1701 pcihp->iot = iot; 1702 pcihp->ioh = ioh; 1703 pcihp->addr = ioaddr; 1704 pcihp->size = size; 1705 pcihp->flags = flags; 1706 1707 return 0; 1708 } 1709 1710 /* 1711 * int pccbb_pcmcia_io_free(pcmcia_chipset_handle_t pch, 1712 * struct pcmcia_io_handle *pcihp) 1713 * 1714 * This function only frees I/O region for pccard. 1715 * 1716 * XXX: The interface of this function is not very good, I believe. 1717 */ 1718 void 1719 pccbb_pcmcia_io_free(pcmcia_chipset_handle_t pch, 1720 struct pcmcia_io_handle *pcihp) 1721 { 1722 bus_space_handle_t ioh = pcihp->ioh; 1723 bus_size_t size = pcihp->size; 1724 1725 struct pccbb_softc *sc = 1726 (struct pccbb_softc *)((struct pcic_handle *)pch)->ph_parent; 1727 rbus_tag_t rb = sc->sc_rbus_iot; 1728 1729 rbus_space_free(rb, ioh, size, NULL); 1730 } 1731 1732 /* 1733 * int pccbb_pcmcia_io_map(pcmcia_chipset_handle_t pch, int width, 1734 * bus_addr_t offset, bus_size_t size, 1735 * struct pcmcia_io_handle *pcihp, 1736 * int *windowp) 1737 * 1738 * This function maps the allocated I/O region to pccard. This function 1739 * never allocates any I/O region for pccard I/O area. I don't 1740 * understand why the original authors of pcmciabus separated alloc and 1741 * map. I believe the two must be unite. 1742 * 1743 * XXX: no wait timing control? 1744 */ 1745 int 1746 pccbb_pcmcia_io_map(pcmcia_chipset_handle_t pch, int width, bus_addr_t offset, 1747 bus_size_t size, struct pcmcia_io_handle *pcihp, int *windowp) 1748 { 1749 struct pcic_handle *ph = (struct pcic_handle *)pch; 1750 bus_addr_t ioaddr = pcihp->addr + offset; 1751 int i, win; 1752 #if defined CBB_DEBUG 1753 static char *width_names[] = { "dynamic", "io8", "io16" }; 1754 #endif 1755 1756 /* Sanity check I/O handle. */ 1757 1758 if (((struct pccbb_softc *)ph->ph_parent)->sc_iot != pcihp->iot) { 1759 panic("pccbb_pcmcia_io_map iot is bogus"); 1760 } 1761 1762 /* XXX Sanity check offset/size. */ 1763 1764 win = -1; 1765 for (i = 0; i < PCIC_IO_WINS; i++) { 1766 if ((ph->ioalloc & (1 << i)) == 0) { 1767 win = i; 1768 ph->ioalloc |= (1 << i); 1769 break; 1770 } 1771 } 1772 1773 if (win == -1) { 1774 return 1; 1775 } 1776 1777 *windowp = win; 1778 1779 /* XXX this is pretty gross */ 1780 1781 DPRINTF(("pccbb_pcmcia_io_map window %d %s port %lx+%lx\n", 1782 win, width_names[width], (u_long) ioaddr, (u_long) size)); 1783 1784 /* XXX wtf is this doing here? */ 1785 1786 #if 0 1787 printf(" port 0x%lx", (u_long) ioaddr); 1788 if (size > 1) { 1789 printf("-0x%lx", (u_long) ioaddr + (u_long) size - 1); 1790 } 1791 #endif 1792 1793 ph->io[win].addr = ioaddr; 1794 ph->io[win].size = size; 1795 ph->io[win].width = width; 1796 1797 /* actual dirty register-value changing in the function below. */ 1798 pccbb_pcmcia_do_io_map(ph, win); 1799 1800 return 0; 1801 } 1802 1803 /* 1804 * void pccbb_pcmcia_do_io_map(struct pcic_handle *h, int win) 1805 * 1806 * This function changes register-value to map I/O region for pccard. 1807 */ 1808 void 1809 pccbb_pcmcia_do_io_map(struct pcic_handle *ph, int win) 1810 { 1811 static u_int8_t pcic_iowidth[3] = { 1812 PCIC_IOCTL_IO0_IOCS16SRC_CARD, 1813 PCIC_IOCTL_IO0_IOCS16SRC_DATASIZE | 1814 PCIC_IOCTL_IO0_DATASIZE_8BIT, 1815 PCIC_IOCTL_IO0_IOCS16SRC_DATASIZE | 1816 PCIC_IOCTL_IO0_DATASIZE_16BIT, 1817 }; 1818 1819 #define PCIC_SIA_START_LOW 0 1820 #define PCIC_SIA_START_HIGH 1 1821 #define PCIC_SIA_STOP_LOW 2 1822 #define PCIC_SIA_STOP_HIGH 3 1823 1824 int regbase_win = 0x8 + win * 0x04; 1825 u_int8_t ioctl, enable; 1826 1827 DPRINTF( 1828 ("pccbb_pcmcia_do_io_map win %d addr 0x%lx size 0x%lx width %d\n", 1829 win, (long)ph->io[win].addr, (long)ph->io[win].size, 1830 ph->io[win].width * 8)); 1831 1832 Pcic_write(ph, regbase_win + PCIC_SIA_START_LOW, 1833 ph->io[win].addr & 0xff); 1834 Pcic_write(ph, regbase_win + PCIC_SIA_START_HIGH, 1835 (ph->io[win].addr >> 8) & 0xff); 1836 1837 Pcic_write(ph, regbase_win + PCIC_SIA_STOP_LOW, 1838 (ph->io[win].addr + ph->io[win].size - 1) & 0xff); 1839 Pcic_write(ph, regbase_win + PCIC_SIA_STOP_HIGH, 1840 ((ph->io[win].addr + ph->io[win].size - 1) >> 8) & 0xff); 1841 1842 ioctl = Pcic_read(ph, PCIC_IOCTL); 1843 enable = Pcic_read(ph, PCIC_ADDRWIN_ENABLE); 1844 switch (win) { 1845 case 0: 1846 ioctl &= ~(PCIC_IOCTL_IO0_WAITSTATE | PCIC_IOCTL_IO0_ZEROWAIT | 1847 PCIC_IOCTL_IO0_IOCS16SRC_MASK | 1848 PCIC_IOCTL_IO0_DATASIZE_MASK); 1849 ioctl |= pcic_iowidth[ph->io[win].width]; 1850 enable |= PCIC_ADDRWIN_ENABLE_IO0; 1851 break; 1852 case 1: 1853 ioctl &= ~(PCIC_IOCTL_IO1_WAITSTATE | PCIC_IOCTL_IO1_ZEROWAIT | 1854 PCIC_IOCTL_IO1_IOCS16SRC_MASK | 1855 PCIC_IOCTL_IO1_DATASIZE_MASK); 1856 ioctl |= (pcic_iowidth[ph->io[win].width] << 4); 1857 enable |= PCIC_ADDRWIN_ENABLE_IO1; 1858 break; 1859 } 1860 Pcic_write(ph, PCIC_IOCTL, ioctl); 1861 Pcic_write(ph, PCIC_ADDRWIN_ENABLE, enable); 1862 #if defined CBB_DEBUG 1863 { 1864 u_int8_t start_low = 1865 Pcic_read(ph, regbase_win + PCIC_SIA_START_LOW); 1866 u_int8_t start_high = 1867 Pcic_read(ph, regbase_win + PCIC_SIA_START_HIGH); 1868 u_int8_t stop_low = 1869 Pcic_read(ph, regbase_win + PCIC_SIA_STOP_LOW); 1870 u_int8_t stop_high = 1871 Pcic_read(ph, regbase_win + PCIC_SIA_STOP_HIGH); 1872 printf 1873 (" start %02x %02x, stop %02x %02x, ioctl %02x enable %02x\n", 1874 start_low, start_high, stop_low, stop_high, ioctl, enable); 1875 } 1876 #endif 1877 } 1878 1879 /* 1880 * void pccbb_pcmcia_io_unmap(pcmcia_chipset_handle_t *h, int win) 1881 * 1882 * This function unmaps I/O region. No return value. 1883 */ 1884 void 1885 pccbb_pcmcia_io_unmap(pcmcia_chipset_handle_t pch, int win) 1886 { 1887 struct pcic_handle *ph = (struct pcic_handle *)pch; 1888 int reg; 1889 1890 if (win >= PCIC_IO_WINS || win < 0) { 1891 panic("pccbb_pcmcia_io_unmap: window out of range"); 1892 } 1893 1894 reg = Pcic_read(ph, PCIC_ADDRWIN_ENABLE); 1895 switch (win) { 1896 case 0: 1897 reg &= ~PCIC_ADDRWIN_ENABLE_IO0; 1898 break; 1899 case 1: 1900 reg &= ~PCIC_ADDRWIN_ENABLE_IO1; 1901 break; 1902 } 1903 Pcic_write(ph, PCIC_ADDRWIN_ENABLE, reg); 1904 1905 ph->ioalloc &= ~(1 << win); 1906 } 1907 1908 /* 1909 * void pccbb_pcmcia_wait_ready(struct pcic_handle *ph) 1910 * 1911 * This function enables the card. All information is stored in 1912 * the first argument, pcmcia_chipset_handle_t. 1913 */ 1914 void 1915 pccbb_pcmcia_wait_ready(struct pcic_handle *ph) 1916 { 1917 int i; 1918 1919 DPRINTF(("pccbb_pcmcia_wait_ready: status 0x%02x\n", 1920 Pcic_read(ph, PCIC_IF_STATUS))); 1921 1922 for (i = 0; i < 10000; i++) { 1923 if (Pcic_read(ph, PCIC_IF_STATUS) & PCIC_IF_STATUS_READY) { 1924 return; 1925 } 1926 delay(500); 1927 #ifdef CBB_DEBUG 1928 if ((i > 5000) && (i % 100 == 99)) 1929 printf("."); 1930 #endif 1931 } 1932 1933 #ifdef DIAGNOSTIC 1934 printf("pcic_wait_ready: ready never happened, status = %02x\n", 1935 Pcic_read(ph, PCIC_IF_STATUS)); 1936 #endif 1937 } 1938 1939 /* 1940 * void pccbb_pcmcia_socket_enable(pcmcia_chipset_handle_t pch) 1941 * 1942 * This function enables the card. All information is stored in 1943 * the first argument, pcmcia_chipset_handle_t. 1944 */ 1945 void 1946 pccbb_pcmcia_socket_enable(pcmcia_chipset_handle_t pch) 1947 { 1948 struct pcic_handle *ph = (struct pcic_handle *)pch; 1949 struct pccbb_softc *sc = (struct pccbb_softc *)ph->ph_parent; 1950 int cardtype, win; 1951 u_int8_t power, intr; 1952 pcireg_t spsr; 1953 int voltage; 1954 1955 /* this bit is mostly stolen from pcic_attach_card */ 1956 1957 DPRINTF(("pccbb_pcmcia_socket_enable: ")); 1958 1959 /* get card Vcc info */ 1960 1961 spsr = 1962 bus_space_read_4(sc->sc_base_memt, sc->sc_base_memh, 1963 CB_SOCKET_STAT); 1964 if (spsr & CB_SOCKET_STAT_5VCARD) { 1965 DPRINTF(("5V card\n")); 1966 voltage = CARDBUS_VCC_5V | CARDBUS_VPP_VCC; 1967 } else if (spsr & CB_SOCKET_STAT_3VCARD) { 1968 DPRINTF(("3V card\n")); 1969 voltage = CARDBUS_VCC_3V | CARDBUS_VPP_VCC; 1970 } else { 1971 DPRINTF(("?V card, 0x%x\n", spsr)); /* XXX */ 1972 return; 1973 } 1974 1975 /* disable socket i/o: negate output enable bit */ 1976 1977 power = 0; 1978 Pcic_write(ph, PCIC_PWRCTL, power); 1979 1980 /* power down the socket to reset it, clear the card reset pin */ 1981 1982 pccbb_power((cardbus_chipset_tag_t)sc, CARDBUS_VCC_0V | CARDBUS_VPP_0V); 1983 1984 /* 1985 * wait 200ms until power fails (Tpf). Then, wait 100ms since 1986 * we are changing Vcc (Toff). 1987 */ 1988 /* delay(300*1000); too much */ 1989 1990 /* assert reset bit */ 1991 intr = Pcic_read(ph, PCIC_INTR); 1992 intr &= ~(PCIC_INTR_RESET | PCIC_INTR_CARDTYPE_MASK); 1993 Pcic_write(ph, PCIC_INTR, intr); 1994 1995 /* Power up the socket. */ 1996 power = Pcic_read(ph, PCIC_PWRCTL); 1997 Pcic_write(ph, PCIC_PWRCTL, (power & ~PCIC_PWRCTL_OE)); 1998 pccbb_power((cardbus_chipset_tag_t)sc, voltage); 1999 2000 /* Now output enable */ 2001 power = Pcic_read(ph, PCIC_PWRCTL); 2002 Pcic_write(ph, PCIC_PWRCTL, power | PCIC_PWRCTL_OE); 2003 2004 /* 2005 * hold RESET at least 10us. 2006 */ 2007 delay(10); 2008 delay(2 * 1000); /* XXX: TI1130 requires it. */ 2009 delay(20 * 1000); /* XXX: TI1130 requires it. */ 2010 2011 /* clear the reset flag */ 2012 2013 intr |= PCIC_INTR_RESET; 2014 Pcic_write(ph, PCIC_INTR, intr); 2015 2016 /* wait 20ms as per pc card standard (r2.01) section 4.3.6 */ 2017 2018 delay(20000); 2019 2020 /* wait for the chip to finish initializing */ 2021 2022 pccbb_pcmcia_wait_ready(ph); 2023 2024 /* zero out the address windows */ 2025 2026 Pcic_write(ph, PCIC_ADDRWIN_ENABLE, 0); 2027 2028 /* set the card type */ 2029 2030 cardtype = pcmcia_card_gettype(ph->pcmcia); 2031 2032 intr |= ((cardtype == PCMCIA_IFTYPE_IO) ? 2033 PCIC_INTR_CARDTYPE_IO : PCIC_INTR_CARDTYPE_MEM); 2034 Pcic_write(ph, PCIC_INTR, intr); 2035 2036 DPRINTF(("%s: pccbb_pcmcia_socket_enable %02x cardtype %s %02x\n", 2037 ph->ph_parent->dv_xname, ph->sock, 2038 ((cardtype == PCMCIA_IFTYPE_IO) ? "io" : "mem"), intr)); 2039 2040 /* reinstall all the memory and io mappings */ 2041 2042 for (win = 0; win < PCIC_MEM_WINS; ++win) { 2043 if (ph->memalloc & (1 << win)) { 2044 pccbb_pcmcia_do_mem_map(ph, win); 2045 } 2046 } 2047 2048 for (win = 0; win < PCIC_IO_WINS; ++win) { 2049 if (ph->ioalloc & (1 << win)) { 2050 pccbb_pcmcia_do_io_map(ph, win); 2051 } 2052 } 2053 } 2054 2055 /* 2056 * void pccbb_pcmcia_socket_disable(pcmcia_chipset_handle_t *ph) 2057 * 2058 * This function disables the card. All information is stored in 2059 * the first argument, pcmcia_chipset_handle_t. 2060 */ 2061 void 2062 pccbb_pcmcia_socket_disable(pcmcia_chipset_handle_t pch) 2063 { 2064 struct pcic_handle *ph = (struct pcic_handle *)pch; 2065 struct pccbb_softc *sc = (struct pccbb_softc *)ph->ph_parent; 2066 u_int8_t power, intr; 2067 2068 DPRINTF(("pccbb_pcmcia_socket_disable\n")); 2069 2070 /* reset signal asserting... */ 2071 2072 intr = Pcic_read(ph, PCIC_INTR); 2073 intr &= ~(PCIC_INTR_CARDTYPE_MASK); 2074 Pcic_write(ph, PCIC_INTR, intr); 2075 delay(2 * 1000); 2076 2077 /* power down the socket */ 2078 power = Pcic_read(ph, PCIC_PWRCTL); 2079 power &= ~PCIC_PWRCTL_OE; 2080 Pcic_write(ph, PCIC_PWRCTL, power); 2081 pccbb_power((cardbus_chipset_tag_t)sc, CARDBUS_VCC_0V | CARDBUS_VPP_0V); 2082 /* 2083 * wait 300ms until power fails (Tpf). 2084 */ 2085 delay(300 * 1000); 2086 } 2087 2088 /* 2089 * int pccbb_pcmcia_card_detect(pcmcia_chipset_handle_t *ph) 2090 * 2091 * This function detects whether a card is in the slot or not. 2092 * If a card is inserted, return 1. Otherwise, return 0. 2093 */ 2094 int 2095 pccbb_pcmcia_card_detect(pcmcia_chipset_handle_t pch) 2096 { 2097 struct pcic_handle *ph = (struct pcic_handle *)pch; 2098 struct pccbb_softc *sc = (struct pccbb_softc *)ph->ph_parent; 2099 2100 DPRINTF(("pccbb_pcmcia_card_detect\n")); 2101 return pccbb_detect_card(sc) == 1 ? 1 : 0; 2102 } 2103 2104 /* 2105 * int pccbb_pcmcia_mem_alloc(pcmcia_chipset_handle_t pch, 2106 * bus_size_t size, 2107 * struct pcmcia_mem_handle *pcmhp) 2108 * 2109 * This function only allocates memory region for pccard. This 2110 * function never maps the allocated region to pccard memory area. 2111 * 2112 * XXX: Why the argument of start address is not in? 2113 */ 2114 int 2115 pccbb_pcmcia_mem_alloc(pcmcia_chipset_handle_t pch, bus_size_t size, 2116 struct pcmcia_mem_handle *pcmhp) 2117 { 2118 struct pcic_handle *ph = (struct pcic_handle *)pch; 2119 bus_space_handle_t memh; 2120 bus_addr_t addr; 2121 bus_size_t sizepg; 2122 struct pccbb_softc *sc = (struct pccbb_softc *)ph->ph_parent; 2123 rbus_tag_t rb; 2124 2125 /* out of sc->memh, allocate as many pages as necessary */ 2126 2127 /* convert size to PCIC pages */ 2128 /* 2129 * This is not enough; when the requested region is on the page 2130 * boundaries, this may calculate wrong result. 2131 */ 2132 sizepg = (size + (PCIC_MEM_PAGESIZE - 1)) / PCIC_MEM_PAGESIZE; 2133 #if 0 2134 if (sizepg > PCIC_MAX_MEM_PAGES) { 2135 return 1; 2136 } 2137 #endif 2138 2139 if (!(sc->sc_pcmcia_flags & PCCBB_PCMCIA_MEM_32)) { 2140 return 1; 2141 } 2142 2143 addr = 0; /* XXX gcc -Wuninitialized */ 2144 2145 rb = sc->sc_rbus_memt; 2146 if (rbus_space_alloc(rb, 0, sizepg * PCIC_MEM_PAGESIZE, 2147 sizepg * PCIC_MEM_PAGESIZE - 1, PCIC_MEM_PAGESIZE, 0, 2148 &addr, &memh)) { 2149 return 1; 2150 } 2151 2152 DPRINTF( 2153 ("pccbb_pcmcia_alloc_mem: addr 0x%lx size 0x%lx, realsize 0x%lx\n", 2154 addr, size, sizepg * PCIC_MEM_PAGESIZE)); 2155 2156 pcmhp->memt = sc->sc_memt; 2157 pcmhp->memh = memh; 2158 pcmhp->addr = addr; 2159 pcmhp->size = size; 2160 pcmhp->realsize = sizepg * PCIC_MEM_PAGESIZE; 2161 /* What is mhandle? I feel it is very dirty and it must go trush. */ 2162 pcmhp->mhandle = 0; 2163 /* No offset??? Funny. */ 2164 2165 return 0; 2166 } 2167 2168 /* 2169 * void pccbb_pcmcia_mem_free(pcmcia_chipset_handle_t pch, 2170 * struct pcmcia_mem_handle *pcmhp) 2171 * 2172 * This function release the memory space allocated by the function 2173 * pccbb_pcmcia_mem_alloc(). 2174 */ 2175 void 2176 pccbb_pcmcia_mem_free(pcmcia_chipset_handle_t pch, 2177 struct pcmcia_mem_handle *pcmhp) 2178 { 2179 struct pcic_handle *ph = (struct pcic_handle *)pch; 2180 struct pccbb_softc *sc = (struct pccbb_softc *)ph->ph_parent; 2181 2182 rbus_space_free(sc->sc_rbus_memt, pcmhp->memh, pcmhp->realsize, NULL); 2183 } 2184 2185 /* 2186 * void pccbb_pcmcia_do_mem_map(struct pcic_handle *ph, int win) 2187 * 2188 * This function release the memory space allocated by the function 2189 * pccbb_pcmcia_mem_alloc(). 2190 */ 2191 void 2192 pccbb_pcmcia_do_mem_map(struct pcic_handle *ph, int win) 2193 { 2194 int regbase_win; 2195 bus_addr_t phys_addr; 2196 bus_addr_t phys_end; 2197 2198 #define PCIC_SMM_START_LOW 0 2199 #define PCIC_SMM_START_HIGH 1 2200 #define PCIC_SMM_STOP_LOW 2 2201 #define PCIC_SMM_STOP_HIGH 3 2202 #define PCIC_CMA_LOW 4 2203 #define PCIC_CMA_HIGH 5 2204 2205 u_int8_t start_low, start_high = 0; 2206 u_int8_t stop_low, stop_high; 2207 u_int8_t off_low, off_high; 2208 u_int8_t mem_window; 2209 int reg; 2210 2211 regbase_win = 0x10 + win * 0x08; 2212 2213 phys_addr = ph->mem[win].addr; 2214 phys_end = phys_addr + ph->mem[win].size; 2215 2216 DPRINTF(("pccbb_pcmcia_do_mem_map: start 0x%lx end 0x%lx off 0x%lx\n", 2217 phys_addr, phys_end, ph->mem[win].offset)); 2218 2219 #define PCIC_MEMREG_LSB_SHIFT PCIC_SYSMEM_ADDRX_SHIFT 2220 #define PCIC_MEMREG_MSB_SHIFT (PCIC_SYSMEM_ADDRX_SHIFT + 8) 2221 #define PCIC_MEMREG_WIN_SHIFT (PCIC_SYSMEM_ADDRX_SHIFT + 12) 2222 2223 /* bit 19:12 */ 2224 start_low = (phys_addr >> PCIC_MEMREG_LSB_SHIFT) & 0xff; 2225 /* bit 23:20 and bit 7 on */ 2226 start_high = ((phys_addr >> PCIC_MEMREG_MSB_SHIFT) & 0x0f) 2227 | PCIC_SYSMEM_ADDRX_START_MSB_DATASIZE_16BIT; /* bit 7 on */ 2228 /* bit 31:24, for 32-bit address */ 2229 mem_window = (phys_addr >> PCIC_MEMREG_WIN_SHIFT) & 0xff; 2230 2231 Pcic_write(ph, regbase_win + PCIC_SMM_START_LOW, start_low); 2232 Pcic_write(ph, regbase_win + PCIC_SMM_START_HIGH, start_high); 2233 2234 if (((struct pccbb_softc *)ph-> 2235 ph_parent)->sc_pcmcia_flags & PCCBB_PCMCIA_MEM_32) { 2236 Pcic_write(ph, 0x40 + win, mem_window); 2237 } 2238 2239 stop_low = (phys_end >> PCIC_MEMREG_LSB_SHIFT) & 0xff; 2240 stop_high = ((phys_end >> PCIC_MEMREG_MSB_SHIFT) & 0x0f) 2241 | PCIC_SYSMEM_ADDRX_STOP_MSB_WAIT2; /* wait 2 cycles */ 2242 /* XXX Geee, WAIT2!! Crazy!! I must rewrite this routine. */ 2243 2244 Pcic_write(ph, regbase_win + PCIC_SMM_STOP_LOW, stop_low); 2245 Pcic_write(ph, regbase_win + PCIC_SMM_STOP_HIGH, stop_high); 2246 2247 off_low = (ph->mem[win].offset >> PCIC_CARDMEM_ADDRX_SHIFT) & 0xff; 2248 off_high = ((ph->mem[win].offset >> (PCIC_CARDMEM_ADDRX_SHIFT + 8)) 2249 & PCIC_CARDMEM_ADDRX_MSB_ADDR_MASK) 2250 | ((ph->mem[win].kind == PCMCIA_MEM_ATTR) ? 2251 PCIC_CARDMEM_ADDRX_MSB_REGACTIVE_ATTR : 0); 2252 2253 Pcic_write(ph, regbase_win + PCIC_CMA_LOW, off_low); 2254 Pcic_write(ph, regbase_win + PCIC_CMA_HIGH, off_high); 2255 2256 reg = Pcic_read(ph, PCIC_ADDRWIN_ENABLE); 2257 reg |= ((1 << win) | PCIC_ADDRWIN_ENABLE_MEMCS16); 2258 Pcic_write(ph, PCIC_ADDRWIN_ENABLE, reg); 2259 2260 #if defined CBB_DEBUG 2261 { 2262 int r1, r2, r3, r4, r5, r6, r7 = 0; 2263 2264 r1 = Pcic_read(ph, regbase_win + PCIC_SMM_START_LOW); 2265 r2 = Pcic_read(ph, regbase_win + PCIC_SMM_START_HIGH); 2266 r3 = Pcic_read(ph, regbase_win + PCIC_SMM_STOP_LOW); 2267 r4 = Pcic_read(ph, regbase_win + PCIC_SMM_STOP_HIGH); 2268 r5 = Pcic_read(ph, regbase_win + PCIC_CMA_LOW); 2269 r6 = Pcic_read(ph, regbase_win + PCIC_CMA_HIGH); 2270 if (((struct pccbb_softc *)(ph-> 2271 ph_parent))->sc_pcmcia_flags & PCCBB_PCMCIA_MEM_32) { 2272 r7 = Pcic_read(ph, 0x40 + win); 2273 } 2274 2275 DPRINTF(("pccbb_pcmcia_do_mem_map window %d: %02x%02x %02x%02x " 2276 "%02x%02x", win, r1, r2, r3, r4, r5, r6)); 2277 if (((struct pccbb_softc *)(ph-> 2278 ph_parent))->sc_pcmcia_flags & PCCBB_PCMCIA_MEM_32) { 2279 DPRINTF((" %02x", r7)); 2280 } 2281 DPRINTF(("\n")); 2282 } 2283 #endif 2284 } 2285 2286 /* 2287 * int pccbb_pcmcia_mem_map(pcmcia_chipset_handle_t pch, int kind, 2288 * bus_addr_t card_addr, bus_size_t size, 2289 * struct pcmcia_mem_handle *pcmhp, 2290 * bus_size_t *offsetp, int *windowp) 2291 * 2292 * This function maps memory space allocated by the function 2293 * pccbb_pcmcia_mem_alloc(). 2294 */ 2295 int 2296 pccbb_pcmcia_mem_map(pcmcia_chipset_handle_t pch, int kind, 2297 bus_addr_t card_addr, bus_size_t size, struct pcmcia_mem_handle *pcmhp, 2298 bus_size_t *offsetp, int *windowp) 2299 { 2300 struct pcic_handle *ph = (struct pcic_handle *)pch; 2301 bus_addr_t busaddr; 2302 long card_offset; 2303 int win; 2304 2305 for (win = 0; win < PCIC_MEM_WINS; ++win) { 2306 if ((ph->memalloc & (1 << win)) == 0) { 2307 ph->memalloc |= (1 << win); 2308 break; 2309 } 2310 } 2311 2312 if (win == PCIC_MEM_WINS) { 2313 return 1; 2314 } 2315 2316 *windowp = win; 2317 2318 /* XXX this is pretty gross */ 2319 2320 if (((struct pccbb_softc *)ph->ph_parent)->sc_memt != pcmhp->memt) { 2321 panic("pccbb_pcmcia_mem_map memt is bogus"); 2322 } 2323 2324 busaddr = pcmhp->addr; 2325 2326 /* 2327 * compute the address offset to the pcmcia address space for the 2328 * pcic. this is intentionally signed. The masks and shifts below 2329 * will cause TRT to happen in the pcic registers. Deal with making 2330 * sure the address is aligned, and return the alignment offset. 2331 */ 2332 2333 *offsetp = card_addr % PCIC_MEM_PAGESIZE; 2334 card_addr -= *offsetp; 2335 2336 DPRINTF(("pccbb_pcmcia_mem_map window %d bus %lx+%lx+%lx at card addr " 2337 "%lx\n", win, (u_long) busaddr, (u_long) * offsetp, (u_long) size, 2338 (u_long) card_addr)); 2339 2340 /* 2341 * include the offset in the size, and decrement size by one, since 2342 * the hw wants start/stop 2343 */ 2344 size += *offsetp - 1; 2345 2346 card_offset = (((long)card_addr) - ((long)busaddr)); 2347 2348 ph->mem[win].addr = busaddr; 2349 ph->mem[win].size = size; 2350 ph->mem[win].offset = card_offset; 2351 ph->mem[win].kind = kind; 2352 2353 pccbb_pcmcia_do_mem_map(ph, win); 2354 2355 return 0; 2356 } 2357 2358 /* 2359 * int pccbb_pcmcia_mem_unmap(pcmcia_chipset_handle_t pch, 2360 * int window) 2361 * 2362 * This function unmaps memory space which mapped by the function 2363 * pccbb_pcmcia_mem_map(). 2364 */ 2365 void 2366 pccbb_pcmcia_mem_unmap(pcmcia_chipset_handle_t pch, int window) 2367 { 2368 struct pcic_handle *ph = (struct pcic_handle *)pch; 2369 int reg; 2370 2371 if (window >= PCIC_MEM_WINS) { 2372 panic("pccbb_pcmcia_mem_unmap: window out of range"); 2373 } 2374 2375 reg = Pcic_read(ph, PCIC_ADDRWIN_ENABLE); 2376 reg &= ~(1 << window); 2377 Pcic_write(ph, PCIC_ADDRWIN_ENABLE, reg); 2378 2379 ph->memalloc &= ~(1 << window); 2380 } 2381 2382 #if defined PCCBB_PCMCIA_POLL 2383 struct pccbb_poll_str { 2384 void *arg; 2385 int (*func)(void *); 2386 int level; 2387 struct pcic_handle *ph; 2388 int count; 2389 int num; 2390 }; 2391 2392 static struct pccbb_poll_str pccbb_poll[10]; 2393 static int pccbb_poll_n = 0; 2394 static struct timeout pccbb_poll_timeout; 2395 2396 void pccbb_pcmcia_poll(void *arg); 2397 2398 void 2399 pccbb_pcmcia_poll(void *arg) 2400 { 2401 struct pccbb_poll_str *poll = arg; 2402 struct pcic_handle *ph = poll->ph; 2403 struct pccbb_softc *sc = ph->sc; 2404 int s; 2405 u_int32_t spsr; /* socket present-state reg */ 2406 2407 timeout_set(&pccbb_poll_timeout, pccbb_pcmcia_poll, arg); 2408 timeout_add_sec(&pccbb_poll_timeout, 2); 2409 switch (poll->level) { 2410 case IPL_NET: 2411 s = splnet(); 2412 break; 2413 case IPL_BIO: 2414 s = splbio(); 2415 break; 2416 case IPL_TTY: /* fallthrough */ 2417 default: 2418 s = spltty(); 2419 break; 2420 } 2421 2422 spsr = 2423 bus_space_read_4(sc->sc_base_memt, sc->sc_base_memh, 2424 CB_SOCKET_STAT); 2425 2426 #if defined PCCBB_PCMCIA_POLL_ONLY && defined LEVEL2 2427 if (!(spsr & 0x40)) /* CINT low */ 2428 #else 2429 if (1) 2430 #endif 2431 { 2432 if ((*poll->func) (poll->arg) > 0) { 2433 ++poll->count; 2434 /* printf("intr: reported from poller, 0x%x\n", spsr); */ 2435 #if defined LEVEL2 2436 } else { 2437 printf("intr: miss! 0x%x\n", spsr); 2438 #endif 2439 } 2440 } 2441 splx(s); 2442 } 2443 #endif /* defined CB_PCMCIA_POLL */ 2444 2445 /* 2446 * void *pccbb_pcmcia_intr_establish(pcmcia_chipset_handle_t pch, 2447 * struct pcmcia_function *pf, 2448 * int ipl, 2449 * int (*func)(void *), 2450 * void *arg); 2451 * 2452 * This function enables PC-Card interrupt. PCCBB uses PCI interrupt line. 2453 */ 2454 void * 2455 pccbb_pcmcia_intr_establish(pcmcia_chipset_handle_t pch, 2456 struct pcmcia_function *pf, int ipl, int (*func)(void *), void *arg, 2457 char *xname) 2458 { 2459 struct pcic_handle *ph = (struct pcic_handle *)pch; 2460 struct pccbb_softc *sc = (struct pccbb_softc *)ph->ph_parent; 2461 2462 if (!(pf->cfe->flags & PCMCIA_CFE_IRQLEVEL)) { 2463 /* what should I do? */ 2464 if ((pf->cfe->flags & PCMCIA_CFE_IRQLEVEL)) { 2465 DPRINTF( 2466 ("%s does not provide edge nor pulse interrupt\n", 2467 sc->sc_dev.dv_xname)); 2468 return NULL; 2469 } 2470 /* 2471 * XXX Noooooo! The interrupt flag must set properly!! 2472 * dumb pcmcia driver!! 2473 */ 2474 } 2475 2476 return pccbb_intr_establish(sc, -1, ipl, func, arg, xname); 2477 } 2478 2479 /* 2480 * void pccbb_pcmcia_intr_disestablish(pcmcia_chipset_handle_t pch, 2481 * void *ih) 2482 * 2483 * This function disables PC-Card interrupt. 2484 */ 2485 void 2486 pccbb_pcmcia_intr_disestablish(pcmcia_chipset_handle_t pch, void *ih) 2487 { 2488 struct pcic_handle *ph = (struct pcic_handle *)pch; 2489 struct pccbb_softc *sc = (struct pccbb_softc *)ph->ph_parent; 2490 2491 pccbb_intr_disestablish(sc, ih); 2492 } 2493 2494 const char * 2495 pccbb_pcmcia_intr_string(pcmcia_chipset_handle_t pch, void *ih) 2496 { 2497 if (ih == NULL) 2498 return "couldn't establish interrupt"; 2499 else 2500 return ""; /* card shares interrupt of the bridge */ 2501 } 2502 2503 /* 2504 * int 2505 * pccbb_rbus_cb_space_alloc(cardbus_chipset_tag_t ct, rbus_tag_t rb, 2506 * bus_addr_t addr, bus_size_t size, 2507 * bus_addr_t mask, bus_size_t align, 2508 * int flags, bus_addr_t *addrp; 2509 * bus_space_handle_t *bshp) 2510 * 2511 * This function allocates a portion of memory or io space for 2512 * clients. This function is called from CardBus card drivers. 2513 */ 2514 int 2515 pccbb_rbus_cb_space_alloc(cardbus_chipset_tag_t ct, rbus_tag_t rb, 2516 bus_addr_t addr, bus_size_t size, bus_addr_t mask, bus_size_t align, 2517 int flags, bus_addr_t *addrp, bus_space_handle_t *bshp) 2518 { 2519 struct pccbb_softc *sc = (struct pccbb_softc *)ct; 2520 2521 DPRINTF( 2522 ("pccbb_rbus_cb_space_alloc: adr %lx, size %lx, mask %lx, align %lx\n", 2523 addr, size, mask, align)); 2524 2525 align = max(align, 4); 2526 mask = max(mask, (4 - 1)); 2527 if (rb->rb_bt == sc->sc_memt) { 2528 align = max(align, 0x1000); 2529 mask = max(mask, (0x1000 - 1)); 2530 } 2531 2532 if (rb->rb_bt == sc->sc_iot) { 2533 /* XXX: hack for avoiding ISA image */ 2534 if (mask < 0x0100) { 2535 mask = 0x3ff; 2536 addr = 0x300; 2537 } 2538 } 2539 2540 if (rbus_space_alloc(rb, addr, size, mask, align, flags, addrp, bshp)) { 2541 printf("%s: <rbus> no bus space\n", sc->sc_dev.dv_xname); 2542 return 1; 2543 } 2544 2545 pccbb_open_win(sc, rb->rb_bt, *addrp, size, *bshp, 0); 2546 2547 return 0; 2548 } 2549 2550 /* 2551 * int 2552 * pccbb_rbus_cb_space_free(cardbus_chipset_tag_t *ct, rbus_tag_t rb, 2553 * bus_space_handle_t *bshp, bus_size_t size); 2554 * 2555 * This function is called from CardBus card drivers. 2556 */ 2557 int 2558 pccbb_rbus_cb_space_free(cardbus_chipset_tag_t ct, rbus_tag_t rb, 2559 bus_space_handle_t bsh, bus_size_t size) 2560 { 2561 struct pccbb_softc *sc = (struct pccbb_softc *)ct; 2562 bus_space_tag_t bt = rb->rb_bt; 2563 2564 pccbb_close_win(sc, bt, bsh, size); 2565 2566 if (bt == sc->sc_memt) { 2567 } else if (bt == sc->sc_iot) { 2568 } else { 2569 return 1; 2570 /* XXX: panic here? */ 2571 } 2572 2573 return rbus_space_free(rb, bsh, size, NULL); 2574 } 2575 2576 int 2577 pccbb_open_win(struct pccbb_softc *sc, bus_space_tag_t bst, bus_addr_t addr, 2578 bus_size_t size, bus_space_handle_t bsh, int flags) 2579 { 2580 struct pccbb_win_chain_head *head; 2581 bus_addr_t align; 2582 2583 head = &sc->sc_iowindow; 2584 align = 0x04; 2585 if (sc->sc_memt == bst) { 2586 head = &sc->sc_memwindow; 2587 align = 0x1000; 2588 DPRINTF(("using memory window, %x %x %x\n\n", 2589 sc->sc_iot, sc->sc_memt, bst)); 2590 } 2591 2592 if (pccbb_winlist_insert(head, addr, size, bsh, flags)) { 2593 printf("%s: pccbb_open_win: %s winlist insert failed\n", 2594 sc->sc_dev.dv_xname, 2595 (head == &sc->sc_memwindow) ? "mem" : "io"); 2596 } 2597 pccbb_winset(align, sc, bst); 2598 2599 return 0; 2600 } 2601 2602 int 2603 pccbb_close_win(struct pccbb_softc *sc, bus_space_tag_t bst, 2604 bus_space_handle_t bsh, bus_size_t size) 2605 { 2606 struct pccbb_win_chain_head *head; 2607 bus_addr_t align; 2608 2609 head = &sc->sc_iowindow; 2610 align = 0x04; 2611 if (sc->sc_memt == bst) { 2612 head = &sc->sc_memwindow; 2613 align = 0x1000; 2614 } 2615 2616 if (pccbb_winlist_delete(head, bsh, size)) { 2617 printf("%s: pccbb_close_win: %s winlist delete failed\n", 2618 sc->sc_dev.dv_xname, 2619 (head == &sc->sc_memwindow) ? "mem" : "io"); 2620 } 2621 pccbb_winset(align, sc, bst); 2622 2623 return 0; 2624 } 2625 2626 int 2627 pccbb_winlist_insert(struct pccbb_win_chain_head *head, bus_addr_t start, 2628 bus_size_t size, bus_space_handle_t bsh, int flags) 2629 { 2630 struct pccbb_win_chain *chainp, *elem; 2631 2632 if ((elem = malloc(sizeof(struct pccbb_win_chain), M_DEVBUF, 2633 M_NOWAIT)) == NULL) 2634 return (1); /* fail */ 2635 2636 elem->wc_start = start; 2637 elem->wc_end = start + (size - 1); 2638 elem->wc_handle = bsh; 2639 elem->wc_flags = flags; 2640 2641 for (chainp = TAILQ_FIRST(head); chainp != NULL; 2642 chainp = TAILQ_NEXT(chainp, wc_list)) { 2643 if (chainp->wc_end < start) 2644 continue; 2645 TAILQ_INSERT_AFTER(head, chainp, elem, wc_list); 2646 return (0); 2647 } 2648 2649 TAILQ_INSERT_TAIL(head, elem, wc_list); 2650 return (0); 2651 } 2652 2653 int 2654 pccbb_winlist_delete(struct pccbb_win_chain_head *head, bus_space_handle_t bsh, 2655 bus_size_t size) 2656 { 2657 struct pccbb_win_chain *chainp; 2658 2659 for (chainp = TAILQ_FIRST(head); chainp != NULL; 2660 chainp = TAILQ_NEXT(chainp, wc_list)) { 2661 if (memcmp(&chainp->wc_handle, &bsh, sizeof(bsh))) 2662 continue; 2663 if ((chainp->wc_end - chainp->wc_start) != (size - 1)) { 2664 printf("pccbb_winlist_delete: window 0x%lx size " 2665 "inconsistent: 0x%lx, 0x%lx\n", 2666 chainp->wc_start, 2667 chainp->wc_end - chainp->wc_start, 2668 size - 1); 2669 return 1; 2670 } 2671 2672 TAILQ_REMOVE(head, chainp, wc_list); 2673 free(chainp, M_DEVBUF, 0); 2674 2675 return 0; 2676 } 2677 2678 return 1; /* fail: no candidate to remove */ 2679 } 2680 2681 void 2682 pccbb_winset(bus_addr_t align, struct pccbb_softc *sc, bus_space_tag_t bst) 2683 { 2684 pci_chipset_tag_t pc; 2685 pcitag_t tag; 2686 bus_addr_t mask = ~(align - 1); 2687 struct { 2688 pcireg_t win_start; 2689 pcireg_t win_limit; 2690 int win_flags; 2691 } win[2]; 2692 struct pccbb_win_chain *chainp; 2693 int offs; 2694 2695 win[0].win_start = win[1].win_start = 0xffffffff; 2696 win[0].win_limit = win[1].win_limit = 0; 2697 win[0].win_flags = win[1].win_flags = 0; 2698 2699 chainp = TAILQ_FIRST(&sc->sc_iowindow); 2700 offs = PCI_CB_IOBASE0; 2701 if (sc->sc_memt == bst) { 2702 chainp = TAILQ_FIRST(&sc->sc_memwindow); 2703 offs = PCI_CB_MEMBASE0; 2704 } 2705 2706 if (chainp != NULL) { 2707 win[0].win_start = chainp->wc_start & mask; 2708 win[0].win_limit = chainp->wc_end & mask; 2709 win[0].win_flags = chainp->wc_flags; 2710 chainp = TAILQ_NEXT(chainp, wc_list); 2711 } 2712 2713 for (; chainp != NULL; chainp = TAILQ_NEXT(chainp, wc_list)) { 2714 if (win[1].win_start == 0xffffffff) { 2715 /* window 1 is not used */ 2716 if ((win[0].win_flags == chainp->wc_flags) && 2717 (win[0].win_limit + align >= 2718 (chainp->wc_start & mask))) { 2719 /* concatenate */ 2720 win[0].win_limit = chainp->wc_end & mask; 2721 } else { 2722 /* make new window */ 2723 win[1].win_start = chainp->wc_start & mask; 2724 win[1].win_limit = chainp->wc_end & mask; 2725 win[1].win_flags = chainp->wc_flags; 2726 } 2727 continue; 2728 } 2729 2730 /* Both windows are engaged. */ 2731 if (win[0].win_flags == win[1].win_flags) { 2732 /* same flags */ 2733 if (win[0].win_flags == chainp->wc_flags) { 2734 if (win[1].win_start - (win[0].win_limit + 2735 align) < 2736 (chainp->wc_start & mask) - 2737 ((chainp->wc_end & mask) + align)) { 2738 /* 2739 * merge window 0 and 1, and set win1 2740 * to chainp 2741 */ 2742 win[0].win_limit = win[1].win_limit; 2743 win[1].win_start = 2744 chainp->wc_start & mask; 2745 win[1].win_limit = 2746 chainp->wc_end & mask; 2747 } else { 2748 win[1].win_limit = 2749 chainp->wc_end & mask; 2750 } 2751 } else { 2752 /* different flags */ 2753 2754 /* concatenate win0 and win1 */ 2755 win[0].win_limit = win[1].win_limit; 2756 /* allocate win[1] to new space */ 2757 win[1].win_start = chainp->wc_start & mask; 2758 win[1].win_limit = chainp->wc_end & mask; 2759 win[1].win_flags = chainp->wc_flags; 2760 } 2761 } else { 2762 /* the flags of win[0] and win[1] are different */ 2763 if (win[0].win_flags == chainp->wc_flags) { 2764 win[0].win_limit = chainp->wc_end & mask; 2765 /* 2766 * XXX this creates overlapping windows, so 2767 * what should the poor bridge do if one is 2768 * cachable, and the other is not? 2769 */ 2770 printf("%s: overlapping windows\n", 2771 sc->sc_dev.dv_xname); 2772 } else { 2773 win[1].win_limit = chainp->wc_end & mask; 2774 } 2775 } 2776 } 2777 2778 pc = sc->sc_pc; 2779 tag = sc->sc_tag; 2780 pci_conf_write(pc, tag, offs, win[0].win_start); 2781 pci_conf_write(pc, tag, offs + 4, win[0].win_limit); 2782 pci_conf_write(pc, tag, offs + 8, win[1].win_start); 2783 pci_conf_write(pc, tag, offs + 12, win[1].win_limit); 2784 DPRINTF(("--pccbb_winset: win0 [%x, %lx), win1 [%x, %lx)\n", 2785 pci_conf_read(pc, tag, offs), 2786 pci_conf_read(pc, tag, offs + 4) + align, 2787 pci_conf_read(pc, tag, offs + 8), 2788 pci_conf_read(pc, tag, offs + 12) + align)); 2789 2790 if (bst == sc->sc_memt) { 2791 pcireg_t bcr = pci_conf_read(pc, tag, PCI_BCR_INTR); 2792 2793 bcr &= ~(CB_BCR_PREFETCH_MEMWIN0 | CB_BCR_PREFETCH_MEMWIN1); 2794 if (win[0].win_flags & PCCBB_MEM_CACHABLE) 2795 bcr |= CB_BCR_PREFETCH_MEMWIN0; 2796 if (win[1].win_flags & PCCBB_MEM_CACHABLE) 2797 bcr |= CB_BCR_PREFETCH_MEMWIN1; 2798 pci_conf_write(pc, tag, PCI_BCR_INTR, bcr); 2799 } 2800 } 2801 2802 int 2803 pccbbactivate(struct device *self, int act) 2804 { 2805 struct pccbb_softc *sc = (struct pccbb_softc *)self; 2806 pci_chipset_tag_t pc = sc->sc_pc; 2807 pcitag_t tag = sc->sc_tag; 2808 pcireg_t csr; 2809 u_int32_t reg; 2810 bus_space_tag_t base_memt = sc->sc_base_memt; /* socket regs memory */ 2811 bus_space_handle_t base_memh = sc->sc_base_memh; 2812 int rv = 0; 2813 2814 switch (act) { 2815 case DVACT_SUSPEND: 2816 rv = config_activate_children(self, act); 2817 2818 sc->sc_pil_intr_enable = 0; 2819 2820 /* Save registers that may get lost. */ 2821 sc->sc_csr = pci_conf_read(pc, tag, PCI_COMMAND_STATUS_REG); 2822 sc->sc_bhlcr = pci_conf_read(pc, tag, PCI_BHLC_REG); 2823 sc->sc_int = pci_conf_read(pc, tag, PCI_INTERRUPT_REG); 2824 2825 sc->sc_sockbase = pci_conf_read(pc, tag, PCI_SOCKBASE); 2826 sc->sc_busnum = pci_conf_read(pc, tag, PCI_BUSNUM); 2827 2828 sc->sc_membase[0] = pci_conf_read(pc, tag, PCI_CB_MEMBASE0); 2829 sc->sc_memlimit[0] = pci_conf_read(pc, tag, PCI_CB_MEMLIMIT0); 2830 sc->sc_membase[1] = pci_conf_read(pc, tag, PCI_CB_MEMBASE1); 2831 sc->sc_memlimit[1] = pci_conf_read(pc, tag, PCI_CB_MEMLIMIT1); 2832 sc->sc_iobase[0] = pci_conf_read(pc, tag, PCI_CB_IOBASE0); 2833 sc->sc_iolimit[0] = pci_conf_read(pc, tag, PCI_CB_IOLIMIT0); 2834 sc->sc_iobase[1] = pci_conf_read(pc, tag, PCI_CB_IOBASE1); 2835 sc->sc_iolimit[1] = pci_conf_read(pc, tag, PCI_CB_IOLIMIT1); 2836 break; 2837 case DVACT_RESUME: 2838 /* Restore the registers saved above. */ 2839 pci_conf_write(pc, tag, PCI_BHLC_REG, sc->sc_bhlcr); 2840 pci_conf_write(pc, tag, PCI_INTERRUPT_REG, sc->sc_int); 2841 2842 pci_conf_write(pc, tag, PCI_SOCKBASE, sc->sc_sockbase); 2843 pci_conf_write(pc, tag, PCI_BUSNUM, sc->sc_busnum); 2844 2845 pci_conf_write(pc, tag, PCI_CB_MEMBASE0, sc->sc_membase[0]); 2846 pci_conf_write(pc, tag, PCI_CB_MEMLIMIT0, sc->sc_memlimit[0]); 2847 pci_conf_write(pc, tag, PCI_CB_MEMBASE1, sc->sc_membase[1]); 2848 pci_conf_write(pc, tag, PCI_CB_MEMLIMIT1, sc->sc_memlimit[1]); 2849 pci_conf_write(pc, tag, PCI_CB_IOBASE0, sc->sc_iobase[0]); 2850 pci_conf_write(pc, tag, PCI_CB_IOLIMIT0, sc->sc_iolimit[0]); 2851 pci_conf_write(pc, tag, PCI_CB_IOBASE1, sc->sc_iobase[1]); 2852 pci_conf_write(pc, tag, PCI_CB_IOLIMIT1, sc->sc_iolimit[1]); 2853 2854 /* Disable legacy register mapping. */ 2855 pccbb_legacy_disable(sc); 2856 2857 /* 2858 * Restore command register last to avoid exposing 2859 * uninitialised windows. 2860 */ 2861 csr = pci_conf_read(pc, tag, PCI_COMMAND_STATUS_REG); 2862 pci_conf_write(pc, tag, PCI_COMMAND_STATUS_REG, 2863 (csr & 0xffff0000) | (sc->sc_csr & 0x0000ffff)); 2864 2865 /* CSC Interrupt: Card detect interrupt on */ 2866 reg = bus_space_read_4(base_memt, base_memh, CB_SOCKET_MASK); 2867 /* Card detect intr is turned on. */ 2868 reg |= CB_SOCKET_MASK_CD; 2869 bus_space_write_4(base_memt, base_memh, CB_SOCKET_MASK, reg); 2870 2871 /* reset interrupt */ 2872 reg = bus_space_read_4(base_memt, base_memh, CB_SOCKET_EVENT); 2873 bus_space_write_4(base_memt, base_memh, CB_SOCKET_EVENT, reg); 2874 2875 /* re-check all cards */ 2876 pccbb_checksockstat(sc); 2877 2878 /* 2879 * XXX Because the cardslot stuff is so obfuscated with threads, 2880 * here we are activating children which may have been 2881 * ejected while we were asleep. This needs to be solved. 2882 */ 2883 rv = config_activate_children(self, act); 2884 2885 sc->sc_pil_intr_enable = 1; 2886 break; 2887 case DVACT_POWERDOWN: 2888 rv = config_activate_children(self, act); 2889 pccbb_shutdown(self); 2890 break; 2891 default: 2892 rv = config_activate_children(self, act); 2893 break; 2894 } 2895 return (rv); 2896 } 2897