1 /* $OpenBSD: pccbb.c,v 1.27 2001/12/24 18:21:42 mickey Exp $ */ 2 /* $NetBSD: pccbb.c,v 1.42 2000/06/16 23:41:35 cgd Exp $ */ 3 4 /* 5 * Copyright (c) 1998, 1999 and 2000 6 * HAYAKAWA Koichi. All rights reserved. 7 * 8 * Redistribution and use in source and binary forms, with or without 9 * modification, are permitted provided that the following conditions 10 * are met: 11 * 1. Redistributions of source code must retain the above copyright 12 * notice, this list of conditions and the following disclaimer. 13 * 2. Redistributions in binary form must reproduce the above copyright 14 * notice, this list of conditions and the following disclaimer in the 15 * documentation and/or other materials provided with the distribution. 16 * 3. All advertising materials mentioning features or use of this software 17 * must display the following acknowledgement: 18 * This product includes software developed by HAYAKAWA Koichi. 19 * 4. The name of the author may not be used to endorse or promote products 20 * derived from this software without specific prior written permission. 21 * 22 * THIS SOFTWARE IS PROVIDED BY THE AUTHOR ``AS IS'' AND ANY EXPRESS OR 23 * IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED WARRANTIES 24 * OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE DISCLAIMED. 25 * IN NO EVENT SHALL THE AUTHOR BE LIABLE FOR ANY DIRECT, INDIRECT, 26 * INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT 27 * NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, 28 * DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY 29 * THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT 30 * (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE OF 31 * THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE. 32 */ 33 34 /* 35 #define CBB_DEBUG 36 #define SHOW_REGS 37 #define PCCBB_PCMCIA_POLL 38 */ 39 /* #define CBB_DEBUG */ 40 41 /* 42 #define CB_PCMCIA_POLL 43 #define CB_PCMCIA_POLL_ONLY 44 #define LEVEL2 45 */ 46 47 #include <sys/types.h> 48 #include <sys/param.h> 49 #include <sys/systm.h> 50 #include <sys/kernel.h> 51 #include <sys/errno.h> 52 #include <sys/ioctl.h> 53 #include <sys/syslog.h> 54 #include <sys/device.h> 55 #include <sys/malloc.h> 56 57 #include <machine/intr.h> 58 #include <machine/bus.h> 59 60 #include <dev/pci/pcivar.h> 61 #include <dev/pci/pcireg.h> 62 #include <dev/pci/pcidevs.h> 63 64 #include <dev/pci/pccbbreg.h> 65 66 #include <dev/cardbus/cardslotvar.h> 67 68 #include <dev/cardbus/cardbusvar.h> 69 70 #include <dev/pcmcia/pcmciareg.h> 71 #include <dev/pcmcia/pcmciavar.h> 72 73 #include <dev/ic/i82365reg.h> 74 #include <dev/ic/i82365var.h> 75 #include <dev/pci/pccbbvar.h> 76 77 #ifndef __NetBSD_Version__ 78 struct cfdriver cbb_cd = { 79 NULL, "cbb", DV_DULL 80 }; 81 #endif 82 83 #if defined CBB_DEBUG 84 #define DPRINTF(x) printf x 85 #else 86 #define DPRINTF(x) 87 #endif 88 89 int pcicbbmatch __P((struct device *, void *, void *)); 90 void pccbbattach __P((struct device *, struct device *, void *)); 91 int pccbbintr __P((void *)); 92 void pccbb_shutdown __P((void *)); 93 void pci113x_insert __P((void *)); 94 int pccbbintr_function __P((struct pccbb_softc *)); 95 96 int pccbb_detect_card __P((struct pccbb_softc *)); 97 98 void pccbb_pcmcia_write __P((struct pcic_handle *, int, int)); 99 u_int8_t pccbb_pcmcia_read __P((struct pcic_handle *, int)); 100 #define Pcic_read(ph, reg) ((ph)->ph_read((ph), (reg))) 101 #define Pcic_write(ph, reg, val) ((ph)->ph_write((ph), (reg), (val))) 102 103 int cb_reset __P((struct pccbb_softc *)); 104 int cb_detect_voltage __P((struct pccbb_softc *)); 105 int cbbprint __P((void *, const char *)); 106 107 int cb_chipset __P((u_int32_t, int *)); 108 void pccbb_pcmcia_attach_setup __P((struct pccbb_softc *, 109 struct pcmciabus_attach_args *)); 110 #if 0 111 void pccbb_pcmcia_attach_card __P((struct pcic_handle *)); 112 void pccbb_pcmcia_detach_card __P((struct pcic_handle *, int)); 113 void pccbb_pcmcia_deactivate_card __P((struct pcic_handle *)); 114 #endif 115 116 int pccbb_ctrl __P((cardbus_chipset_tag_t, int)); 117 int pccbb_power __P((cardbus_chipset_tag_t, int)); 118 int pccbb_cardenable __P((struct pccbb_softc * sc, int function)); 119 #if !rbus 120 int pccbb_io_open __P((cardbus_chipset_tag_t, int, u_int32_t, u_int32_t)); 121 int pccbb_io_close __P((cardbus_chipset_tag_t, int)); 122 int pccbb_mem_open __P((cardbus_chipset_tag_t, int, u_int32_t, u_int32_t)); 123 int pccbb_mem_close __P((cardbus_chipset_tag_t, int)); 124 #endif /* !rbus */ 125 void *pccbb_intr_establish __P((struct pccbb_softc *, int irq, int level, 126 int (*ih) (void *), void *sc)); 127 void pccbb_intr_disestablish __P((struct pccbb_softc *, void *ih)); 128 129 void *pccbb_cb_intr_establish __P((cardbus_chipset_tag_t, int irq, int level, 130 int (*ih) (void *), void *sc)); 131 void pccbb_cb_intr_disestablish __P((cardbus_chipset_tag_t ct, void *ih)); 132 133 cardbustag_t pccbb_make_tag __P((cardbus_chipset_tag_t, int, int, int)); 134 void pccbb_free_tag __P((cardbus_chipset_tag_t, cardbustag_t)); 135 cardbusreg_t pccbb_conf_read __P((cardbus_chipset_tag_t, cardbustag_t, int)); 136 void pccbb_conf_write __P((cardbus_chipset_tag_t, cardbustag_t, int, 137 cardbusreg_t)); 138 void pccbb_chipinit __P((struct pccbb_softc *)); 139 140 int pccbb_pcmcia_mem_alloc __P((pcmcia_chipset_handle_t, bus_size_t, 141 struct pcmcia_mem_handle *)); 142 void pccbb_pcmcia_mem_free __P((pcmcia_chipset_handle_t, 143 struct pcmcia_mem_handle *)); 144 int pccbb_pcmcia_mem_map __P((pcmcia_chipset_handle_t, int, bus_addr_t, 145 bus_size_t, struct pcmcia_mem_handle *, bus_addr_t *, int *)); 146 void pccbb_pcmcia_mem_unmap __P((pcmcia_chipset_handle_t, int)); 147 int pccbb_pcmcia_io_alloc __P((pcmcia_chipset_handle_t, bus_addr_t, 148 bus_size_t, bus_size_t, struct pcmcia_io_handle *)); 149 void pccbb_pcmcia_io_free __P((pcmcia_chipset_handle_t, 150 struct pcmcia_io_handle *)); 151 int pccbb_pcmcia_io_map __P((pcmcia_chipset_handle_t, int, bus_addr_t, 152 bus_size_t, struct pcmcia_io_handle *, int *)); 153 void pccbb_pcmcia_io_unmap __P((pcmcia_chipset_handle_t, int)); 154 void *pccbb_pcmcia_intr_establish __P((pcmcia_chipset_handle_t, 155 struct pcmcia_function *, int, int (*)(void *), void *, char *)); 156 void pccbb_pcmcia_intr_disestablish __P((pcmcia_chipset_handle_t, 157 void *)); 158 void pccbb_pcmcia_socket_enable __P((pcmcia_chipset_handle_t)); 159 void pccbb_pcmcia_socket_disable __P((pcmcia_chipset_handle_t)); 160 int pccbb_pcmcia_card_detect __P((pcmcia_chipset_handle_t pch)); 161 162 void pccbb_pcmcia_do_io_map __P((struct pcic_handle *, int)); 163 void pccbb_pcmcia_wait_ready __P((struct pcic_handle *)); 164 void pccbb_pcmcia_do_mem_map __P((struct pcic_handle *, int)); 165 void pccbb_powerhook __P((int, void *)); 166 167 /* bus-space allocation and deallocation functions */ 168 #if rbus 169 170 int pccbb_rbus_cb_space_alloc __P((cardbus_chipset_tag_t, rbus_tag_t, 171 bus_addr_t addr, bus_size_t size, bus_addr_t mask, bus_size_t align, 172 int flags, bus_addr_t * addrp, bus_space_handle_t * bshp)); 173 int pccbb_rbus_cb_space_free __P((cardbus_chipset_tag_t, rbus_tag_t, 174 bus_space_handle_t, bus_size_t)); 175 176 #endif /* rbus */ 177 178 #if rbus 179 180 int pccbb_open_win __P((struct pccbb_softc *, bus_space_tag_t, 181 bus_addr_t, bus_size_t, bus_space_handle_t, int flags)); 182 int pccbb_close_win __P((struct pccbb_softc *, bus_space_tag_t, 183 bus_space_handle_t, bus_size_t)); 184 int pccbb_winlist_insert __P((struct pccbb_win_chain_head *, bus_addr_t, 185 bus_size_t, bus_space_handle_t, int)); 186 int pccbb_winlist_delete __P((struct pccbb_win_chain_head *, 187 bus_space_handle_t, bus_size_t)); 188 void pccbb_winset __P((bus_addr_t align, struct pccbb_softc *, 189 bus_space_tag_t)); 190 void pccbb_winlist_show(struct pccbb_win_chain *); 191 192 #endif /* rbus */ 193 194 /* for config_defer */ 195 void pccbb_pci_callback __P((struct device *)); 196 197 #if defined SHOW_REGS 198 void cb_show_regs __P((pci_chipset_tag_t, pcitag_t, bus_space_tag_t, 199 bus_space_handle_t memh)); 200 #endif 201 202 struct cfattach cbb_pci_ca = { 203 sizeof(struct pccbb_softc), pcicbbmatch, pccbbattach 204 }; 205 206 static struct pcmcia_chip_functions pccbb_pcmcia_funcs = { 207 pccbb_pcmcia_mem_alloc, 208 pccbb_pcmcia_mem_free, 209 pccbb_pcmcia_mem_map, 210 pccbb_pcmcia_mem_unmap, 211 pccbb_pcmcia_io_alloc, 212 pccbb_pcmcia_io_free, 213 pccbb_pcmcia_io_map, 214 pccbb_pcmcia_io_unmap, 215 pccbb_pcmcia_intr_establish, 216 pccbb_pcmcia_intr_disestablish, 217 pccbb_pcmcia_socket_enable, 218 pccbb_pcmcia_socket_disable, 219 pccbb_pcmcia_card_detect 220 }; 221 222 #if rbus 223 static struct cardbus_functions pccbb_funcs = { 224 pccbb_rbus_cb_space_alloc, 225 pccbb_rbus_cb_space_free, 226 pccbb_cb_intr_establish, 227 pccbb_cb_intr_disestablish, 228 pccbb_ctrl, 229 pccbb_power, 230 pccbb_make_tag, 231 pccbb_free_tag, 232 pccbb_conf_read, 233 pccbb_conf_write, 234 }; 235 #else 236 static struct cardbus_functions pccbb_funcs = { 237 pccbb_ctrl, 238 pccbb_power, 239 pccbb_mem_open, 240 pccbb_mem_close, 241 pccbb_io_open, 242 pccbb_io_close, 243 pccbb_cb_intr_establish, 244 pccbb_cb_intr_disestablish, 245 pccbb_make_tag, 246 pccbb_conf_read, 247 pccbb_conf_write, 248 }; 249 #endif 250 251 int 252 pcicbbmatch(parent, match, aux) 253 struct device *parent; 254 void *match; 255 void *aux; 256 { 257 struct pci_attach_args *pa = (struct pci_attach_args *)aux; 258 259 if (PCI_CLASS(pa->pa_class) == PCI_CLASS_BRIDGE && 260 PCI_SUBCLASS(pa->pa_class) == PCI_SUBCLASS_BRIDGE_CARDBUS && 261 PCI_INTERFACE(pa->pa_class) == 0) { 262 return 1; 263 } 264 265 return 0; 266 } 267 268 #define MAKEID(vendor, prod) (((vendor) << PCI_VENDOR_SHIFT) \ 269 | ((prod) << PCI_PRODUCT_SHIFT)) 270 271 struct yenta_chipinfo { 272 pcireg_t yc_id; /* vendor tag | product tag */ 273 int yc_chiptype; 274 int yc_flags; 275 } yc_chipsets[] = { 276 /* Texas Instruments chips */ 277 { MAKEID(PCI_VENDOR_TI, PCI_PRODUCT_TI_PCI1130), CB_TI113X, 278 PCCBB_PCMCIA_IO_RELOC | PCCBB_PCMCIA_MEM_32}, 279 { MAKEID(PCI_VENDOR_TI, PCI_PRODUCT_TI_PCI1131), CB_TI113X, 280 PCCBB_PCMCIA_IO_RELOC | PCCBB_PCMCIA_MEM_32}, 281 { MAKEID(PCI_VENDOR_TI, PCI_PRODUCT_TI_PCI1250), CB_TI12XX, 282 PCCBB_PCMCIA_IO_RELOC | PCCBB_PCMCIA_MEM_32}, 283 { MAKEID(PCI_VENDOR_TI, PCI_PRODUCT_TI_PCI1220), CB_TI12XX, 284 PCCBB_PCMCIA_IO_RELOC | PCCBB_PCMCIA_MEM_32}, 285 { MAKEID(PCI_VENDOR_TI, PCI_PRODUCT_TI_PCI1221), CB_TI12XX, 286 PCCBB_PCMCIA_IO_RELOC | PCCBB_PCMCIA_MEM_32}, 287 { MAKEID(PCI_VENDOR_TI, PCI_PRODUCT_TI_PCI1225), CB_TI12XX, 288 PCCBB_PCMCIA_IO_RELOC | PCCBB_PCMCIA_MEM_32}, 289 { MAKEID(PCI_VENDOR_TI, PCI_PRODUCT_TI_PCI1251), CB_TI12XX, 290 PCCBB_PCMCIA_IO_RELOC | PCCBB_PCMCIA_MEM_32}, 291 { MAKEID(PCI_VENDOR_TI, PCI_PRODUCT_TI_PCI1251B), CB_TI12XX, 292 PCCBB_PCMCIA_IO_RELOC | PCCBB_PCMCIA_MEM_32}, 293 { MAKEID(PCI_VENDOR_TI, PCI_PRODUCT_TI_PCI1211), CB_TI12XX, 294 PCCBB_PCMCIA_IO_RELOC | PCCBB_PCMCIA_MEM_32}, 295 { MAKEID(PCI_VENDOR_TI, PCI_PRODUCT_TI_PCI1420), CB_TI12XX, 296 PCCBB_PCMCIA_IO_RELOC | PCCBB_PCMCIA_MEM_32}, 297 { MAKEID(PCI_VENDOR_TI, PCI_PRODUCT_TI_PCI1450), CB_TI12XX, 298 PCCBB_PCMCIA_IO_RELOC | PCCBB_PCMCIA_MEM_32}, 299 { MAKEID(PCI_VENDOR_TI, PCI_PRODUCT_TI_PCI1451), CB_TI12XX, 300 PCCBB_PCMCIA_IO_RELOC | PCCBB_PCMCIA_MEM_32}, 301 302 /* Ricoh chips */ 303 { MAKEID(PCI_VENDOR_RICOH, PCI_PRODUCT_RICOH_RF5C475), CB_RX5C47X, 304 PCCBB_PCMCIA_MEM_32}, 305 { MAKEID(PCI_VENDOR_RICOH, PCI_PRODUCT_RICOH_RF5C476), CB_RX5C47X, 306 PCCBB_PCMCIA_MEM_32}, 307 { MAKEID(PCI_VENDOR_RICOH, PCI_PRODUCT_RICOH_RF5C477), CB_RX5C47X, 308 PCCBB_PCMCIA_MEM_32}, 309 { MAKEID(PCI_VENDOR_RICOH, PCI_PRODUCT_RICOH_RF5C478), CB_RX5C47X, 310 PCCBB_PCMCIA_MEM_32}, 311 { MAKEID(PCI_VENDOR_RICOH, PCI_PRODUCT_RICOH_RF5C465), CB_RX5C46X, 312 PCCBB_PCMCIA_MEM_32}, 313 { MAKEID(PCI_VENDOR_RICOH, PCI_PRODUCT_RICOH_RF5C466), CB_RX5C46X, 314 PCCBB_PCMCIA_MEM_32}, 315 316 /* Toshiba products */ 317 { MAKEID(PCI_VENDOR_TOSHIBA2, PCI_PRODUCT_TOSHIBA2_ToPIC95), 318 CB_TOPIC95, PCCBB_PCMCIA_MEM_32}, 319 { MAKEID(PCI_VENDOR_TOSHIBA2, PCI_PRODUCT_TOSHIBA2_ToPIC95B), 320 CB_TOPIC95B, PCCBB_PCMCIA_MEM_32}, 321 { MAKEID(PCI_VENDOR_TOSHIBA2, PCI_PRODUCT_TOSHIBA2_ToPIC97), 322 CB_TOPIC97, PCCBB_PCMCIA_MEM_32}, 323 { MAKEID(PCI_VENDOR_TOSHIBA2, PCI_PRODUCT_TOSHIBA2_ToPIC100), 324 CB_TOPIC97, PCCBB_PCMCIA_MEM_32}, 325 326 /* Cirrus Logic products */ 327 { MAKEID(PCI_VENDOR_CIRRUS, PCI_PRODUCT_CIRRUS_CL_PD6832), 328 CB_CIRRUS, PCCBB_PCMCIA_MEM_32}, 329 { MAKEID(PCI_VENDOR_CIRRUS, PCI_PRODUCT_CIRRUS_CL_PD6833), 330 CB_CIRRUS, PCCBB_PCMCIA_MEM_32}, 331 332 /* sentinel, or Generic chip */ 333 { 0 /* null id */ , CB_UNKNOWN, PCCBB_PCMCIA_MEM_32}, 334 }; 335 336 int 337 cb_chipset(pci_id, flagp) 338 u_int32_t pci_id; 339 int *flagp; 340 { 341 struct yenta_chipinfo *yc; 342 343 /* Loop over except the last default entry. */ 344 for (yc = yc_chipsets; yc < yc_chipsets + 345 sizeof(yc_chipsets) / sizeof(yc_chipsets[0]) - 1; yc++) 346 if (pci_id == yc->yc_id) 347 break; 348 349 if (flagp != NULL) 350 *flagp = yc->yc_flags; 351 352 return (yc->yc_chiptype); 353 } 354 355 void 356 pccbb_shutdown(void *arg) 357 { 358 struct pccbb_softc *sc = arg; 359 pcireg_t command; 360 361 DPRINTF(("%s: shutdown\n", sc->sc_dev.dv_xname)); 362 363 /* turn off power */ 364 pccbb_power((cardbus_chipset_tag_t)sc, CARDBUS_VCC_0V | CARDBUS_VPP_0V); 365 366 bus_space_write_4(sc->sc_base_memt, sc->sc_base_memh, CB_SOCKET_MASK, 367 0); 368 369 command = pci_conf_read(sc->sc_pc, sc->sc_tag, PCI_COMMAND_STATUS_REG); 370 371 command &= ~(PCI_COMMAND_IO_ENABLE | PCI_COMMAND_MEM_ENABLE | 372 PCI_COMMAND_MASTER_ENABLE); 373 pci_conf_write(sc->sc_pc, sc->sc_tag, PCI_COMMAND_STATUS_REG, command); 374 } 375 376 void 377 pccbbattach(parent, self, aux) 378 struct device *parent; 379 struct device *self; 380 void *aux; 381 { 382 struct pccbb_softc *sc = (void *)self; 383 struct pci_attach_args *pa = aux; 384 pci_chipset_tag_t pc = pa->pa_pc; 385 pcireg_t busreg, reg, sock_base; 386 pci_intr_handle_t ih; 387 const char *intrstr = NULL; 388 bus_addr_t sockbase; 389 int flags; 390 391 sc->sc_chipset = cb_chipset(pa->pa_id, &flags); 392 393 #ifdef CBB_DEBUG 394 printf(" (chipflags %x)", flags); 395 #endif 396 397 TAILQ_INIT(&sc->sc_memwindow); 398 TAILQ_INIT(&sc->sc_iowindow); 399 400 #if rbus 401 sc->sc_rbus_iot = rbus_pccbb_parent_io(pa); 402 sc->sc_rbus_memt = rbus_pccbb_parent_mem(pa); 403 #endif /* rbus */ 404 405 sc->sc_base_memh = 0; 406 407 /* 408 * MAP socket registers and ExCA registers on memory-space 409 * When no valid address is set on socket base registers (on pci 410 * config space), get it not polite way. 411 */ 412 sock_base = pci_conf_read(pc, pa->pa_tag, PCI_SOCKBASE); 413 414 if (PCI_MAPREG_MEM_ADDR(sock_base) >= 0x100000 && 415 PCI_MAPREG_MEM_ADDR(sock_base) != 0xfffffff0) { 416 /* The address must be valid. */ 417 if (pci_mapreg_map(pa, PCI_SOCKBASE, PCI_MAPREG_TYPE_MEM, 0, 418 &sc->sc_base_memt, &sc->sc_base_memh, &sockbase, NULL, 0)) 419 { 420 printf("%s: can't map socket base address 0x%x\n", 421 sc->sc_dev.dv_xname, sock_base); 422 /* 423 * I think it's funny: socket base registers must be 424 * mapped on memory space, but ... 425 */ 426 if (pci_mapreg_map(pa, PCI_SOCKBASE, 427 PCI_MAPREG_TYPE_IO, 0, &sc->sc_base_memt, 428 &sc->sc_base_memh, &sockbase, NULL, 0)) { 429 printf("%s: can't map socket base address" 430 " 0x%lx: io mode\n", sc->sc_dev.dv_xname, 431 sockbase); 432 /* give up... allocate reg space via rbus. */ 433 sc->sc_base_memh = 0; 434 pci_conf_write(pc, pa->pa_tag, PCI_SOCKBASE, 0); 435 } 436 } else { 437 DPRINTF(("%s: socket base address 0x%lx\n", 438 sc->sc_dev.dv_xname, sockbase)); 439 } 440 } 441 442 sc->sc_mem_start = 0; /* XXX */ 443 sc->sc_mem_end = 0xffffffff; /* XXX */ 444 445 /* 446 * When bus number isn't set correctly, give up using 32-bit CardBus 447 * mode. 448 */ 449 busreg = pci_conf_read(pc, pa->pa_tag, PCI_BUSNUM); 450 #if notyet 451 if (((busreg >> 8) & 0xff) == 0) { 452 printf(": CardBus support disabled because of unconfigured bus number\n"); 453 flags |= PCCBB_PCMCIA_16BITONLY; 454 } 455 #endif 456 457 /* pccbb_machdep.c end */ 458 459 #if defined CBB_DEBUG 460 { 461 static char *intrname[5] = { "NON", "A", "B", "C", "D" }; 462 printf(": intrpin %s, intrtag %d\n", 463 intrname[pa->pa_intrpin], pa->pa_intrline); 464 } 465 #endif 466 467 /* setup softc */ 468 sc->sc_pc = pc; 469 sc->sc_iot = pa->pa_iot; 470 sc->sc_memt = pa->pa_memt; 471 sc->sc_dmat = pa->pa_dmat; 472 sc->sc_tag = pa->pa_tag; 473 sc->sc_function = pa->pa_function; 474 sc->sc_sockbase = sock_base; 475 sc->sc_busnum = busreg; 476 sc->sc_intrtag = pa->pa_intrtag; 477 sc->sc_intrpin = pa->pa_intrpin; 478 479 sc->sc_pcmcia_flags = flags; /* set PCMCIA facility */ 480 481 /* Map and establish the interrupt. */ 482 if (pci_intr_map(pa, &ih)) { 483 printf(": couldn't map interrupt\n"); 484 return; 485 } 486 intrstr = pci_intr_string(pc, ih); 487 /* must do this after intr is mapped and established */ 488 sc->sc_intrline = pci_intr_line(ih); 489 490 /* 491 * XXX pccbbintr should be called under the priority lower 492 * than any other hard interrputs. 493 */ 494 sc->sc_ih = pci_intr_establish(pc, ih, IPL_BIO, pccbbintr, sc, 495 sc->sc_dev.dv_xname); 496 497 if (sc->sc_ih == NULL) { 498 printf(": couldn't establish interrupt"); 499 if (intrstr != NULL) { 500 printf(" at %s", intrstr); 501 } 502 printf("\n"); 503 return; 504 } 505 printf(": %s\n", intrstr); 506 507 shutdownhook_establish(pccbb_shutdown, sc); 508 509 /* Disable legacy register mapping. */ 510 switch (sc->sc_chipset) { 511 case CB_RX5C46X: /* fallthrough */ 512 #if 0 513 /* The RX5C47X-series requires writes to the PCI_LEGACY register. */ 514 case CB_RX5C47X: 515 #endif 516 /* 517 * The legacy pcic io-port on Ricoh RX5C46X CardBus bridges 518 * cannot be disabled by substituting 0 into PCI_LEGACY 519 * register. Ricoh CardBus bridges have special bits on Bridge 520 * control reg (addr 0x3e on PCI config space). 521 */ 522 reg = pci_conf_read(pc, pa->pa_tag, PCI_BCR_INTR); 523 reg &= ~(CB_BCRI_RL_3E0_ENA | CB_BCRI_RL_3E2_ENA); 524 pci_conf_write(pc, pa->pa_tag, PCI_BCR_INTR, reg); 525 break; 526 527 default: 528 /* XXX I don't know proper way to kill legacy I/O. */ 529 pci_conf_write(pc, pa->pa_tag, PCI_LEGACY, 0x0); 530 break; 531 } 532 533 timeout_set(&sc->sc_ins_tmo, pci113x_insert, sc); 534 config_defer(self, pccbb_pci_callback); 535 } 536 537 538 539 540 /* 541 * void pccbb_pci_callback(struct device *self) 542 * 543 * The actual attach routine: get memory space for YENTA register 544 * space, setup YENTA register and route interrupt. 545 * 546 * This function should be deferred because this device may obtain 547 * memory space dynamically. This function must avoid obtaining 548 * memory area which has already kept for another device. Also, 549 * this function MUST be done before ISA attach process because this 550 * function kills pcic compatible port used by ISA pcic. 551 */ 552 void 553 pccbb_pci_callback(self) 554 struct device *self; 555 { 556 struct pccbb_softc *sc = (void *)self; 557 pci_chipset_tag_t pc = sc->sc_pc; 558 bus_space_tag_t base_memt; 559 bus_space_handle_t base_memh; 560 u_int32_t maskreg; 561 bus_addr_t sockbase; 562 struct cbslot_attach_args cba; 563 struct pcmciabus_attach_args paa; 564 struct cardslot_attach_args caa; 565 struct cardslot_softc *csc; 566 567 if (0 == sc->sc_base_memh) { 568 /* The socket registers aren't mapped correctly. */ 569 #if rbus 570 if (rbus_space_alloc(sc->sc_rbus_memt, 0, 0x1000, 0x0fff, 571 (sc->sc_chipset == CB_RX5C47X 572 || sc->sc_chipset == CB_TI113X) ? 0x10000 : 0x1000, 573 0, &sockbase, &sc->sc_base_memh)) { 574 return; 575 } 576 sc->sc_base_memt = sc->sc_memt; 577 pci_conf_write(pc, sc->sc_tag, PCI_SOCKBASE, sockbase); 578 DPRINTF(("%s: CardBus resister address 0x%lx -> 0x%x\n", 579 sc->sc_dev.dv_xname, sockbase, pci_conf_read(pc, sc->sc_tag, 580 PCI_SOCKBASE))); 581 #else 582 sc->sc_base_memt = sc->sc_memt; 583 #if !defined CBB_PCI_BASE 584 #define CBB_PCI_BASE 0x20000000 585 #endif 586 if (bus_space_alloc(sc->sc_base_memt, CBB_PCI_BASE, 0xffffffff, 587 0x1000, 0x1000, 0, 0, &sockbase, &sc->sc_base_memh)) { 588 /* cannot allocate memory space */ 589 return; 590 } 591 pci_conf_write(pc, sc->sc_tag, PCI_SOCKBASE, sockbase); 592 DPRINTF(("%s: CardBus resister address 0x%x -> 0x%x\n", 593 sc->sc_dev.dv_xname, sock_base, pci_conf_read(pc, 594 sc->sc_tag, PCI_SOCKBASE))); 595 #endif 596 } 597 598 /* bus bridge initialization */ 599 pccbb_chipinit(sc); 600 601 base_memt = sc->sc_base_memt; /* socket regs memory tag */ 602 base_memh = sc->sc_base_memh; /* socket regs memory handle */ 603 604 /* clear data structure for child device interrupt handlers */ 605 sc->sc_pil = NULL; 606 sc->sc_pil_intr_enable = 1; 607 608 powerhook_establish(pccbb_powerhook, sc); 609 610 { 611 u_int32_t sockstat = 612 bus_space_read_4(base_memt, base_memh, CB_SOCKET_STAT); 613 if (0 == (sockstat & CB_SOCKET_STAT_CD)) { 614 sc->sc_flags |= CBB_CARDEXIST; 615 } 616 } 617 618 /* 619 * attach cardbus 620 */ 621 if (!(sc->sc_pcmcia_flags & PCCBB_PCMCIA_16BITONLY)) { 622 pcireg_t busreg = pci_conf_read(pc, sc->sc_tag, PCI_BUSNUM); 623 pcireg_t bhlc = pci_conf_read(pc, sc->sc_tag, PCI_BHLC_REG); 624 625 /* initialize cbslot_attach */ 626 cba.cba_busname = "cardbus"; 627 cba.cba_iot = sc->sc_iot; 628 cba.cba_memt = sc->sc_memt; 629 cba.cba_dmat = sc->sc_dmat; 630 cba.cba_bus = (busreg >> 8) & 0x0ff; 631 cba.cba_cc = (void *)sc; 632 cba.cba_cf = &pccbb_funcs; 633 cba.cba_intrline = sc->sc_intrline; 634 635 #if rbus 636 cba.cba_rbus_iot = sc->sc_rbus_iot; 637 cba.cba_rbus_memt = sc->sc_rbus_memt; 638 #endif 639 640 cba.cba_cacheline = PCI_CACHELINE(bhlc); 641 cba.cba_lattimer = PCI_CB_LATENCY(busreg); 642 643 #if defined CBB_DEBUG 644 printf("%s: cacheline 0x%x lattimer 0x%x\n", 645 sc->sc_dev.dv_xname, cba.cba_cacheline, cba.cba_lattimer); 646 printf("%s: bhlc 0x%x lscp 0x%x\n", sc->sc_dev.dv_xname, bhlc, 647 busreg); 648 #endif 649 #if defined SHOW_REGS 650 cb_show_regs(sc->sc_pc, sc->sc_tag, sc->sc_base_memt, 651 sc->sc_base_memh); 652 #endif 653 } 654 655 pccbb_pcmcia_attach_setup(sc, &paa); 656 caa.caa_cb_attach = NULL; 657 if (!(sc->sc_pcmcia_flags & PCCBB_PCMCIA_16BITONLY)) { 658 caa.caa_cb_attach = &cba; 659 } 660 caa.caa_16_attach = &paa; 661 caa.caa_ph = &sc->sc_pcmcia_h; 662 663 if (NULL != (csc = (void *)config_found(self, &caa, cbbprint))) { 664 DPRINTF(("pccbbattach: found cardslot\n")); 665 sc->sc_csc = csc; 666 } 667 668 sc->sc_ints_on = 1; 669 670 /* CSC Interrupt: Card detect interrupt on */ 671 maskreg = bus_space_read_4(base_memt, base_memh, CB_SOCKET_MASK); 672 maskreg |= CB_SOCKET_MASK_CD; /* Card detect intr is turned on. */ 673 bus_space_write_4(base_memt, base_memh, CB_SOCKET_MASK, maskreg); 674 /* reset interrupt */ 675 bus_space_write_4(base_memt, base_memh, CB_SOCKET_EVENT, 676 bus_space_read_4(base_memt, base_memh, CB_SOCKET_EVENT)); 677 678 return; 679 } 680 681 682 683 684 685 /* 686 * void pccbb_chipinit(struct pccbb_softc *sc) 687 * 688 * This function initialize YENTA chip registers listed below: 689 * 1) PCI command reg, 690 * 2) PCI and CardBus latency timer, 691 * 3) route PCI interrupt, 692 * 4) close all memory and io windows. 693 */ 694 void 695 pccbb_chipinit(sc) 696 struct pccbb_softc *sc; 697 { 698 pci_chipset_tag_t pc = sc->sc_pc; 699 pcitag_t tag = sc->sc_tag; 700 pcireg_t reg; 701 702 /* 703 * Set PCI command reg. 704 * Some laptop's BIOSes (i.e. TICO) do not enable CardBus chip. 705 */ 706 reg = pci_conf_read(pc, tag, PCI_COMMAND_STATUS_REG); 707 /* I believe it is harmless. */ 708 reg |= (PCI_COMMAND_IO_ENABLE | PCI_COMMAND_MEM_ENABLE | 709 PCI_COMMAND_MASTER_ENABLE); 710 pci_conf_write(pc, tag, PCI_COMMAND_STATUS_REG, reg); 711 712 /* 713 * Set CardBus latency timer. 714 */ 715 reg = pci_conf_read(pc, tag, PCI_CB_LSCP_REG); 716 if (PCI_CB_LATENCY(reg) < 0x20) { 717 reg &= ~(PCI_CB_LATENCY_MASK << PCI_CB_LATENCY_SHIFT); 718 reg |= (0x20 << PCI_CB_LATENCY_SHIFT); 719 pci_conf_write(pc, tag, PCI_CB_LSCP_REG, reg); 720 } 721 DPRINTF(("CardBus latency timer 0x%x (%x)\n", 722 PCI_CB_LATENCY(reg), pci_conf_read(pc, tag, PCI_CB_LSCP_REG))); 723 724 /* 725 * Set PCI latency timer. 726 */ 727 reg = pci_conf_read(pc, tag, PCI_BHLC_REG); 728 if (PCI_LATTIMER(reg) < 0x10) { 729 reg &= ~(PCI_LATTIMER_MASK << PCI_LATTIMER_SHIFT); 730 reg |= (0x10 << PCI_LATTIMER_SHIFT); 731 pci_conf_write(pc, tag, PCI_BHLC_REG, reg); 732 } 733 DPRINTF(("PCI latency timer 0x%x (%x)\n", 734 PCI_LATTIMER(reg), pci_conf_read(pc, tag, PCI_BHLC_REG))); 735 736 /* Route functional interrupts to PCI. */ 737 reg = pci_conf_read(pc, tag, PCI_BCR_INTR); 738 reg |= CB_BCR_INTR_IREQ_ENABLE; /* disable PCI Intr */ 739 reg |= CB_BCR_WRITE_POST_ENABLE; /* enable write post */ 740 reg |= CB_BCR_RESET_ENABLE; /* assert reset */ 741 pci_conf_write(pc, tag, PCI_BCR_INTR, reg); 742 743 switch (sc->sc_chipset) { 744 case CB_TI113X: 745 reg = pci_conf_read(pc, tag, PCI_CBCTRL); 746 /* This bit is shared, but may read as 0 on some chips, so set 747 it explicitly on both functions. */ 748 reg |= PCI113X_CBCTRL_PCI_IRQ_ENA; 749 /* CSC intr enable */ 750 reg |= PCI113X_CBCTRL_PCI_CSC; 751 /* functional intr prohibit | prohibit ISA routing */ 752 reg &= ~(PCI113X_CBCTRL_PCI_INTR | PCI113X_CBCTRL_INT_MASK); 753 pci_conf_write(pc, tag, PCI_CBCTRL, reg); 754 break; 755 756 case CB_TOPIC95B: 757 reg = pci_conf_read(pc, tag, TOPIC_SOCKET_CTRL); 758 reg |= TOPIC_SOCKET_CTRL_SCR_IRQSEL; 759 pci_conf_write(pc, tag, TOPIC_SOCKET_CTRL, reg); 760 761 reg = pci_conf_read(pc, tag, TOPIC_SLOT_CTRL); 762 DPRINTF(("%s: topic slot ctrl reg 0x%x -> ", 763 sc->sc_dev.dv_xname, reg)); 764 reg |= (TOPIC_SLOT_CTRL_SLOTON | TOPIC_SLOT_CTRL_SLOTEN | 765 TOPIC_SLOT_CTRL_ID_LOCK | TOPIC_SLOT_CTRL_CARDBUS); 766 reg &= ~TOPIC_SLOT_CTRL_SWDETECT; 767 DPRINTF(("0x%x\n", reg)); 768 pci_conf_write(pc, tag, TOPIC_SLOT_CTRL, reg); 769 break; 770 } 771 772 /* Close all memory and I/O windows. */ 773 pci_conf_write(pc, tag, PCI_CB_MEMBASE0, 0xffffffff); 774 pci_conf_write(pc, tag, PCI_CB_MEMLIMIT0, 0); 775 pci_conf_write(pc, tag, PCI_CB_MEMBASE1, 0xffffffff); 776 pci_conf_write(pc, tag, PCI_CB_MEMLIMIT1, 0); 777 pci_conf_write(pc, tag, PCI_CB_IOBASE0, 0xffffffff); 778 pci_conf_write(pc, tag, PCI_CB_IOLIMIT0, 0); 779 pci_conf_write(pc, tag, PCI_CB_IOBASE1, 0xffffffff); 780 pci_conf_write(pc, tag, PCI_CB_IOLIMIT1, 0); 781 782 /* reset 16-bit pcmcia bus */ 783 bus_space_write_1(sc->sc_base_memt, sc->sc_base_memh, 784 0x800 + PCIC_INTR, 785 bus_space_read_1(sc->sc_base_memt, sc->sc_base_memh, 786 0x800 + PCIC_INTR) & ~PCIC_INTR_RESET); 787 788 /* turn off power */ 789 pccbb_power((cardbus_chipset_tag_t)sc, CARDBUS_VCC_0V | CARDBUS_VPP_0V); 790 } 791 792 793 794 795 /* 796 * void pccbb_pcmcia_attach_setup(struct pccbb_softc *sc, 797 * struct pcmciabus_attach_args *paa) 798 * 799 * This function attaches 16-bit PCcard bus. 800 */ 801 void 802 pccbb_pcmcia_attach_setup(sc, paa) 803 struct pccbb_softc *sc; 804 struct pcmciabus_attach_args *paa; 805 { 806 struct pcic_handle *ph = &sc->sc_pcmcia_h; 807 #if rbus 808 rbus_tag_t rb; 809 #endif 810 811 /* initialize pcmcia part in pccbb_softc */ 812 ph->ph_parent = (struct device *)sc; 813 ph->sock = sc->sc_function; 814 ph->flags = 0; 815 ph->shutdown = 0; 816 ph->ih_irq = sc->sc_intrline; 817 ph->ph_bus_t = sc->sc_base_memt; 818 ph->ph_bus_h = sc->sc_base_memh; 819 ph->ph_read = pccbb_pcmcia_read; 820 ph->ph_write = pccbb_pcmcia_write; 821 sc->sc_pct = &pccbb_pcmcia_funcs; 822 823 /* 824 * We need to do a few things here: 825 * 1) Disable routing of CSC and functional interrupts to ISA IRQs by 826 * setting the IRQ numbers to 0. 827 * 2) Set bit 4 of PCIC_INTR, which is needed on some chips to enable 828 * routing of CSC interrupts (e.g. card removal) to PCI while in 829 * PCMCIA mode. We just leave this set all the time. 830 * 3) Enable card insertion/removal interrupts in case the chip also 831 * needs that while in PCMCIA mode. 832 * 4) Clear any pending CSC interrupt. 833 */ 834 Pcic_write(ph, PCIC_INTR, PCIC_INTR_ENABLE | PCIC_INTR_RESET); 835 if (sc->sc_chipset == CB_TI113X) { 836 Pcic_write(ph, PCIC_CSC_INTR, 0); 837 } else { 838 Pcic_write(ph, PCIC_CSC_INTR, PCIC_CSC_INTR_CD_ENABLE); 839 Pcic_read(ph, PCIC_CSC); 840 } 841 842 /* initialize pcmcia bus attachment */ 843 paa->paa_busname = "pcmcia"; 844 paa->pct = sc->sc_pct; 845 paa->pch = ph; 846 paa->iobase = 0; /* I don't use them */ 847 paa->iosize = 0; 848 #if rbus 849 rb = ((struct pccbb_softc *)(ph->ph_parent))->sc_rbus_iot; 850 paa->iobase = rb->rb_start + rb->rb_offset; 851 paa->iosize = rb->rb_end - rb->rb_start; 852 #endif 853 854 return; 855 } 856 857 #if 0 858 void 859 pccbb_pcmcia_attach_card(ph) 860 struct pcic_handle *ph; 861 { 862 if (ph->flags & PCIC_FLAG_CARDP) { 863 panic("pccbb_pcmcia_attach_card: already attached"); 864 } 865 866 /* call the MI attach function */ 867 pcmcia_card_attach(ph->pcmcia); 868 869 ph->flags |= PCIC_FLAG_CARDP; 870 } 871 872 void 873 pccbb_pcmcia_detach_card(ph, flags) 874 struct pcic_handle *ph; 875 int flags; 876 { 877 if (!(ph->flags & PCIC_FLAG_CARDP)) { 878 panic("pccbb_pcmcia_detach_card: already detached"); 879 } 880 881 ph->flags &= ~PCIC_FLAG_CARDP; 882 883 /* call the MI detach function */ 884 pcmcia_card_detach(ph->pcmcia, flags); 885 } 886 #endif 887 888 /* 889 * int pccbbintr(arg) 890 * void *arg; 891 * This routine handles the interrupt from Yenta PCI-CardBus bridge 892 * itself. 893 */ 894 int 895 pccbbintr(arg) 896 void *arg; 897 { 898 struct pccbb_softc *sc = (struct pccbb_softc *)arg; 899 u_int32_t sockevent, sockstate; 900 bus_space_tag_t memt = sc->sc_base_memt; 901 bus_space_handle_t memh = sc->sc_base_memh; 902 struct pcic_handle *ph = &sc->sc_pcmcia_h; 903 904 if (!sc->sc_ints_on) 905 return 0; 906 907 sockevent = bus_space_read_4(memt, memh, CB_SOCKET_EVENT); 908 bus_space_write_4(memt, memh, CB_SOCKET_EVENT, sockevent); 909 Pcic_read(ph, PCIC_CSC); 910 911 if (sockevent == 0) { 912 /* This intr is not for me: it may be for my child devices. */ 913 if (sc->sc_pil_intr_enable) { 914 return pccbbintr_function(sc); 915 } else { 916 return 0; 917 } 918 } 919 920 if (sockevent & CB_SOCKET_EVENT_CD) { 921 sockstate = bus_space_read_4(memt, memh, CB_SOCKET_STAT); 922 if (CB_SOCKET_STAT_CD == (sockstate & CB_SOCKET_STAT_CD)) { 923 /* A card should be removed. */ 924 if (sc->sc_flags & CBB_CARDEXIST) { 925 DPRINTF(("%s: 0x%08x", sc->sc_dev.dv_xname, 926 sockevent)); 927 DPRINTF((" card removed, 0x%08x\n", sockstate)); 928 sc->sc_flags &= ~CBB_CARDEXIST; 929 if (sc->sc_csc->sc_status & 930 CARDSLOT_STATUS_CARD_16) { 931 #if 0 932 struct pcic_handle *ph = 933 &sc->sc_pcmcia_h; 934 935 pcmcia_card_deactivate(ph->pcmcia); 936 pccbb_pcmcia_socket_disable(ph); 937 pccbb_pcmcia_detach_card(ph, 938 DETACH_FORCE); 939 #endif 940 cardslot_event_throw(sc->sc_csc, 941 CARDSLOT_EVENT_REMOVAL_16); 942 } else if (sc->sc_csc->sc_status & 943 CARDSLOT_STATUS_CARD_CB) { 944 /* Cardbus intr removed */ 945 cardslot_event_throw(sc->sc_csc, 946 CARDSLOT_EVENT_REMOVAL_CB); 947 } 948 } 949 } else if (0x00 == (sockstate & CB_SOCKET_STAT_CD) && 950 /* 951 * The pccbbintr may called from powerdown hook when 952 * the system resumed, to detect the card 953 * insertion/removal during suspension. 954 */ 955 (sc->sc_flags & CBB_CARDEXIST) == 0) { 956 if (sc->sc_flags & CBB_INSERTING) { 957 timeout_del(&sc->sc_ins_tmo); 958 } 959 timeout_add(&sc->sc_ins_tmo, hz / 10); 960 sc->sc_flags |= CBB_INSERTING; 961 } 962 } 963 964 return (1); 965 } 966 967 /* 968 * int pccbbintr_function(struct pccbb_softc *sc) 969 * 970 * This function calls each interrupt handler registered at the 971 * bridge. The interrupt handlers are called in registered order. 972 */ 973 int 974 pccbbintr_function(sc) 975 struct pccbb_softc *sc; 976 { 977 int retval = 0, val; 978 struct pccbb_intrhand_list *pil; 979 int s, splchanged; 980 981 for (pil = sc->sc_pil; pil != NULL; pil = pil->pil_next) { 982 /* 983 * XXX priority change. gross. I use if-else 984 * sentense instead of switch-case sentense because of 985 * avoiding duplicate case value error. More than one 986 * IPL_XXX use same value. It depends on 987 * implementation. 988 */ 989 splchanged = 1; 990 #if 0 991 if (pil->pil_level == IPL_SERIAL) { 992 s = splserial(); 993 } else if (pil->pil_level == IPL_HIGH) { 994 #endif 995 if (pil->pil_level == IPL_HIGH) { 996 s = splhigh(); 997 } else if (pil->pil_level == IPL_CLOCK) { 998 s = splclock(); 999 } else if (pil->pil_level == IPL_AUDIO) { 1000 s = splaudio(); 1001 } else if (pil->pil_level == IPL_IMP) { 1002 s = splimp(); 1003 } else if (pil->pil_level == IPL_TTY) { 1004 s = spltty(); 1005 #if 0 1006 } else if (pil->pil_level == IPL_SOFTSERIAL) { 1007 s = splsoftserial(); 1008 #endif 1009 } else if (pil->pil_level == IPL_NET) { 1010 s = splnet(); 1011 } else { 1012 splchanged = 0; 1013 /* XXX: ih lower than IPL_BIO runs w/ IPL_BIO. */ 1014 } 1015 1016 val = (*pil->pil_func)(pil->pil_arg); 1017 1018 if (splchanged != 0) { 1019 splx(s); 1020 } 1021 1022 retval = retval == 1 ? 1 : 1023 retval == 0 ? val : val != 0 ? val : retval; 1024 } 1025 1026 return retval; 1027 } 1028 1029 void 1030 pci113x_insert(arg) 1031 void *arg; 1032 { 1033 struct pccbb_softc *sc = (struct pccbb_softc *)arg; 1034 u_int32_t sockevent, sockstate; 1035 1036 sockevent = bus_space_read_4(sc->sc_base_memt, sc->sc_base_memh, 1037 CB_SOCKET_EVENT); 1038 sockstate = bus_space_read_4(sc->sc_base_memt, sc->sc_base_memh, 1039 CB_SOCKET_STAT); 1040 1041 if (0 == (sockstate & CB_SOCKET_STAT_CD)) { /* card exist */ 1042 DPRINTF(("%s: 0x%08x", sc->sc_dev.dv_xname, sockevent)); 1043 DPRINTF((" card inserted, 0x%08x\n", sockstate)); 1044 sc->sc_flags |= CBB_CARDEXIST; 1045 /* call pccard interrupt handler here */ 1046 if (sockstate & CB_SOCKET_STAT_16BIT) { 1047 /* 16-bit card found */ 1048 /* pccbb_pcmcia_attach_card(&sc->sc_pcmcia_h); */ 1049 cardslot_event_throw(sc->sc_csc, 1050 CARDSLOT_EVENT_INSERTION_16); 1051 } else if (sockstate & CB_SOCKET_STAT_CB) { 1052 /* cardbus card found */ 1053 /* cardbus_attach_card(sc->sc_csc); */ 1054 cardslot_event_throw(sc->sc_csc, 1055 CARDSLOT_EVENT_INSERTION_CB); 1056 } else { 1057 /* who are you? */ 1058 } 1059 } else { 1060 timeout_add(&sc->sc_ins_tmo, hz / 10); 1061 } 1062 } 1063 1064 #define PCCBB_PCMCIA_OFFSET 0x800 1065 u_int8_t 1066 pccbb_pcmcia_read(ph, reg) 1067 struct pcic_handle *ph; 1068 int reg; 1069 { 1070 bus_space_barrier(ph->ph_bus_t, ph->ph_bus_h, 1071 PCCBB_PCMCIA_OFFSET + reg, 1, BUS_SPACE_BARRIER_READ); 1072 1073 return bus_space_read_1(ph->ph_bus_t, ph->ph_bus_h, 1074 PCCBB_PCMCIA_OFFSET + reg); 1075 } 1076 1077 void 1078 pccbb_pcmcia_write(ph, reg, val) 1079 struct pcic_handle *ph; 1080 int reg; 1081 u_int8_t val; 1082 { 1083 bus_space_barrier(ph->ph_bus_t, ph->ph_bus_h, 1084 PCCBB_PCMCIA_OFFSET + reg, 1, BUS_SPACE_BARRIER_WRITE); 1085 1086 bus_space_write_1(ph->ph_bus_t, ph->ph_bus_h, PCCBB_PCMCIA_OFFSET + reg, 1087 val); 1088 } 1089 1090 /* 1091 * int pccbb_ctrl(cardbus_chipset_tag_t, int) 1092 */ 1093 int 1094 pccbb_ctrl(ct, command) 1095 cardbus_chipset_tag_t ct; 1096 int command; 1097 { 1098 struct pccbb_softc *sc = (struct pccbb_softc *)ct; 1099 1100 switch (command) { 1101 case CARDBUS_CD: 1102 if (2 == pccbb_detect_card(sc)) { 1103 int retval = 0; 1104 int status = cb_detect_voltage(sc); 1105 if (PCCARD_VCC_5V & status) { 1106 retval |= CARDBUS_5V_CARD; 1107 } 1108 if (PCCARD_VCC_3V & status) { 1109 retval |= CARDBUS_3V_CARD; 1110 } 1111 if (PCCARD_VCC_XV & status) { 1112 retval |= CARDBUS_XV_CARD; 1113 } 1114 if (PCCARD_VCC_YV & status) { 1115 retval |= CARDBUS_YV_CARD; 1116 } 1117 return retval; 1118 } else { 1119 return 0; 1120 } 1121 break; 1122 case CARDBUS_RESET: 1123 return cb_reset(sc); 1124 break; 1125 case CARDBUS_IO_ENABLE: /* fallthrough */ 1126 case CARDBUS_IO_DISABLE: /* fallthrough */ 1127 case CARDBUS_MEM_ENABLE: /* fallthrough */ 1128 case CARDBUS_MEM_DISABLE: /* fallthrough */ 1129 case CARDBUS_BM_ENABLE: /* fallthrough */ 1130 case CARDBUS_BM_DISABLE: /* fallthrough */ 1131 return pccbb_cardenable(sc, command); 1132 break; 1133 } 1134 1135 return 0; 1136 } 1137 1138 /* 1139 * int pccbb_power(cardbus_chipset_tag_t, int) 1140 * This function returns true when it succeeds and returns false when 1141 * it fails. 1142 */ 1143 int 1144 pccbb_power(ct, command) 1145 cardbus_chipset_tag_t ct; 1146 int command; 1147 { 1148 struct pccbb_softc *sc = (struct pccbb_softc *)ct; 1149 1150 u_int32_t status, sock_ctrl; 1151 bus_space_tag_t memt = sc->sc_base_memt; 1152 bus_space_handle_t memh = sc->sc_base_memh; 1153 1154 DPRINTF(("pccbb_power: %s and %s [%x]\n", 1155 (command & CARDBUS_VCCMASK) == CARDBUS_VCC_UC ? "CARDBUS_VCC_UC" : 1156 (command & CARDBUS_VCCMASK) == CARDBUS_VCC_5V ? "CARDBUS_VCC_5V" : 1157 (command & CARDBUS_VCCMASK) == CARDBUS_VCC_3V ? "CARDBUS_VCC_3V" : 1158 (command & CARDBUS_VCCMASK) == CARDBUS_VCC_XV ? "CARDBUS_VCC_XV" : 1159 (command & CARDBUS_VCCMASK) == CARDBUS_VCC_YV ? "CARDBUS_VCC_YV" : 1160 (command & CARDBUS_VCCMASK) == CARDBUS_VCC_0V ? "CARDBUS_VCC_0V" : 1161 "UNKNOWN", 1162 (command & CARDBUS_VPPMASK) == CARDBUS_VPP_UC ? "CARDBUS_VPP_UC" : 1163 (command & CARDBUS_VPPMASK) == CARDBUS_VPP_12V ? "CARDBUS_VPP_12V" : 1164 (command & CARDBUS_VPPMASK) == CARDBUS_VPP_VCC ? "CARDBUS_VPP_VCC" : 1165 (command & CARDBUS_VPPMASK) == CARDBUS_VPP_0V ? "CARDBUS_VPP_0V" : 1166 "UNKNOWN", command)); 1167 1168 status = bus_space_read_4(memt, memh, CB_SOCKET_STAT); 1169 sock_ctrl = bus_space_read_4(memt, memh, CB_SOCKET_CTRL); 1170 1171 switch (command & CARDBUS_VCCMASK) { 1172 case CARDBUS_VCC_UC: 1173 break; 1174 case CARDBUS_VCC_5V: 1175 if (CB_SOCKET_STAT_5VCARD & status) { /* check 5 V card */ 1176 sock_ctrl &= ~CB_SOCKET_CTRL_VCCMASK; 1177 sock_ctrl |= CB_SOCKET_CTRL_VCC_5V; 1178 } else { 1179 printf("%s: BAD voltage request: no 5 V card\n", 1180 sc->sc_dev.dv_xname); 1181 } 1182 break; 1183 case CARDBUS_VCC_3V: 1184 if (CB_SOCKET_STAT_3VCARD & status) { 1185 sock_ctrl &= ~CB_SOCKET_CTRL_VCCMASK; 1186 sock_ctrl |= CB_SOCKET_CTRL_VCC_3V; 1187 } else { 1188 printf("%s: BAD voltage request: no 3.3 V card\n", 1189 sc->sc_dev.dv_xname); 1190 } 1191 break; 1192 case CARDBUS_VCC_0V: 1193 sock_ctrl &= ~CB_SOCKET_CTRL_VCCMASK; 1194 break; 1195 default: 1196 return 0; /* power NEVER changed */ 1197 break; 1198 } 1199 1200 switch (command & CARDBUS_VPPMASK) { 1201 case CARDBUS_VPP_UC: 1202 break; 1203 case CARDBUS_VPP_0V: 1204 sock_ctrl &= ~CB_SOCKET_CTRL_VPPMASK; 1205 break; 1206 case CARDBUS_VPP_VCC: 1207 sock_ctrl &= ~CB_SOCKET_CTRL_VPPMASK; 1208 sock_ctrl |= ((sock_ctrl >> 4) & 0x07); 1209 break; 1210 case CARDBUS_VPP_12V: 1211 sock_ctrl &= ~CB_SOCKET_CTRL_VPPMASK; 1212 sock_ctrl |= CB_SOCKET_CTRL_VPP_12V; 1213 break; 1214 } 1215 1216 #if 0 1217 DPRINTF(("sock_ctrl: %x\n", sock_ctrl)); 1218 #endif 1219 bus_space_write_4(memt, memh, CB_SOCKET_CTRL, sock_ctrl); 1220 status = bus_space_read_4(memt, memh, CB_SOCKET_STAT); 1221 1222 if (status & CB_SOCKET_STAT_BADVCC) { /* bad Vcc request */ 1223 printf 1224 ("%s: bad Vcc request. sock_ctrl 0x%x, sock_status 0x%x\n", 1225 sc->sc_dev.dv_xname, sock_ctrl, status); 1226 DPRINTF(("pccbb_power: %s and %s [%x]\n", 1227 (command & CARDBUS_VCCMASK) == 1228 CARDBUS_VCC_UC ? "CARDBUS_VCC_UC" : (command & 1229 CARDBUS_VCCMASK) == 1230 CARDBUS_VCC_5V ? "CARDBUS_VCC_5V" : (command & 1231 CARDBUS_VCCMASK) == 1232 CARDBUS_VCC_3V ? "CARDBUS_VCC_3V" : (command & 1233 CARDBUS_VCCMASK) == 1234 CARDBUS_VCC_XV ? "CARDBUS_VCC_XV" : (command & 1235 CARDBUS_VCCMASK) == 1236 CARDBUS_VCC_YV ? "CARDBUS_VCC_YV" : (command & 1237 CARDBUS_VCCMASK) == 1238 CARDBUS_VCC_0V ? "CARDBUS_VCC_0V" : "UNKNOWN", 1239 (command & CARDBUS_VPPMASK) == 1240 CARDBUS_VPP_UC ? "CARDBUS_VPP_UC" : (command & 1241 CARDBUS_VPPMASK) == 1242 CARDBUS_VPP_12V ? "CARDBUS_VPP_12V" : (command & 1243 CARDBUS_VPPMASK) == 1244 CARDBUS_VPP_VCC ? "CARDBUS_VPP_VCC" : (command & 1245 CARDBUS_VPPMASK) == 1246 CARDBUS_VPP_0V ? "CARDBUS_VPP_0V" : "UNKNOWN", command)); 1247 #if 0 1248 if (command == (CARDBUS_VCC_0V | CARDBUS_VPP_0V)) { 1249 u_int32_t force = 1250 bus_space_read_4(memt, memh, CB_SOCKET_FORCE); 1251 /* Reset Bad Vcc request */ 1252 force &= ~CB_SOCKET_FORCE_BADVCC; 1253 bus_space_write_4(memt, memh, CB_SOCKET_FORCE, force); 1254 printf("new status 0x%x\n", bus_space_read_4(memt, memh, 1255 CB_SOCKET_STAT)); 1256 return 1; 1257 } 1258 #endif 1259 return 0; 1260 } 1261 1262 /* 1263 * XXX delay 300 ms: though the standard defines that the Vcc set-up 1264 * time is 20 ms, some PC-Card bridge requires longer duration. 1265 */ 1266 delay(300 * 1000); 1267 1268 return 1; /* power changed correctly */ 1269 } 1270 1271 #if defined CB_PCMCIA_POLL 1272 struct cb_poll_str { 1273 void *arg; 1274 int (*func) __P((void *)); 1275 int level; 1276 pccard_chipset_tag_t ct; 1277 int count; 1278 }; 1279 1280 static struct cb_poll_str cb_poll[10]; 1281 static int cb_poll_n = 0; 1282 static struct timeout cb_poll_timeout; 1283 1284 void cb_pcmcia_poll __P((void *arg)); 1285 1286 void 1287 cb_pcmcia_poll(arg) 1288 void *arg; 1289 { 1290 struct cb_poll_str *poll = arg; 1291 struct cbb_pcmcia_softc *psc = (void *)poll->ct->v; 1292 struct pccbb_softc *sc = psc->cpc_parent; 1293 int s; 1294 u_int32_t spsr; /* socket present-state reg */ 1295 1296 timeout_set(&cb_poll_timeout, cb_pcmcia_poll, arg); 1297 timeout_add(&cb_poll_timeout, hz / 10); 1298 switch (poll->level) { 1299 case IPL_NET: 1300 s = splnet(); 1301 break; 1302 case IPL_BIO: 1303 s = splbio(); 1304 break; 1305 case IPL_TTY: /* fallthrough */ 1306 default: 1307 s = spltty(); 1308 break; 1309 } 1310 1311 spsr = 1312 bus_space_read_4(sc->sc_base_memt, sc->sc_base_memh, 1313 CB_SOCKET_STAT); 1314 1315 #if defined CB_PCMCIA_POLL_ONLY && defined LEVEL2 1316 if (!(spsr & 0x40)) { /* CINT low */ 1317 #else 1318 if (1) { 1319 #endif 1320 if ((*poll->func) (poll->arg) == 1) { 1321 ++poll->count; 1322 printf("intr: reported from poller, 0x%x\n", spsr); 1323 #if defined LEVEL2 1324 } else { 1325 printf("intr: miss! 0x%x\n", spsr); 1326 #endif 1327 } 1328 } 1329 splx(s); 1330 } 1331 #endif /* defined CB_PCMCIA_POLL */ 1332 1333 /* 1334 * int pccbb_detect_card(struct pccbb_softc *sc) 1335 * return value: 0 if no card exists. 1336 * 1 if 16-bit card exists. 1337 * 2 if cardbus card exists. 1338 */ 1339 int 1340 pccbb_detect_card(sc) 1341 struct pccbb_softc *sc; 1342 { 1343 bus_space_handle_t base_memh = sc->sc_base_memh; 1344 bus_space_tag_t base_memt = sc->sc_base_memt; 1345 u_int32_t sockstat = 1346 bus_space_read_4(base_memt, base_memh, CB_SOCKET_STAT); 1347 int retval = 0; 1348 1349 /* 1350 * The SCM Microsystems TI1225-based PCI-CardBus dock card that 1351 * ships with some Lucent WaveLAN cards has only one physical slot 1352 * but OpenBSD probes two. The phantom card in the second slot can 1353 * be ignored by punting on unsupported voltages. 1354 */ 1355 if (sockstat & CB_SOCKET_STAT_XVCARD) 1356 return 0; 1357 1358 /* CD1 and CD2 asserted */ 1359 if (0x00 == (sockstat & CB_SOCKET_STAT_CD)) { 1360 /* card must be present */ 1361 if (!(CB_SOCKET_STAT_NOTCARD & sockstat)) { 1362 /* NOTACARD DEASSERTED */ 1363 if (CB_SOCKET_STAT_CB & sockstat) { 1364 /* CardBus mode */ 1365 retval = 2; 1366 } else if (CB_SOCKET_STAT_16BIT & sockstat) { 1367 /* 16-bit mode */ 1368 retval = 1; 1369 } 1370 } 1371 } 1372 return retval; 1373 } 1374 1375 /* 1376 * int cb_reset(struct pccbb_softc *sc) 1377 * This function resets CardBus card. 1378 */ 1379 int 1380 cb_reset(sc) 1381 struct pccbb_softc *sc; 1382 { 1383 /* 1384 * Reset Assert at least 20 ms 1385 * Some machines request longer duration. 1386 */ 1387 int reset_duration = 1388 (sc->sc_chipset == CB_RX5C47X ? 400 * 1000 : 40 * 1000); 1389 u_int32_t bcr = pci_conf_read(sc->sc_pc, sc->sc_tag, PCI_BCR_INTR); 1390 1391 /* Reset bit Assert (bit 6 at 0x3E) */ 1392 bcr |= CB_BCR_RESET_ENABLE; 1393 pci_conf_write(sc->sc_pc, sc->sc_tag, PCI_BCR_INTR, bcr); 1394 delay(reset_duration); 1395 1396 if (CBB_CARDEXIST & sc->sc_flags) { /* A card exists. Reset it! */ 1397 /* Reset bit Deassert (bit 6 at 0x3E) */ 1398 bcr &= ~CB_BCR_RESET_ENABLE; 1399 pci_conf_write(sc->sc_pc, sc->sc_tag, PCI_BCR_INTR, bcr); 1400 delay(reset_duration); 1401 } 1402 /* No card found on the slot. Keep Reset. */ 1403 return 1; 1404 } 1405 1406 /* 1407 * int cb_detect_voltage(struct pccbb_softc *sc) 1408 * This function detect card Voltage. 1409 */ 1410 int 1411 cb_detect_voltage(sc) 1412 struct pccbb_softc *sc; 1413 { 1414 u_int32_t psr; /* socket present-state reg */ 1415 bus_space_tag_t iot = sc->sc_base_memt; 1416 bus_space_handle_t ioh = sc->sc_base_memh; 1417 int vol = PCCARD_VCC_UKN; /* set 0 */ 1418 1419 psr = bus_space_read_4(iot, ioh, CB_SOCKET_STAT); 1420 1421 if (0x400u & psr) { 1422 vol |= PCCARD_VCC_5V; 1423 } 1424 if (0x800u & psr) { 1425 vol |= PCCARD_VCC_3V; 1426 } 1427 1428 return vol; 1429 } 1430 1431 int 1432 cbbprint(aux, pcic) 1433 void *aux; 1434 const char *pcic; 1435 { 1436 /* 1437 struct cbslot_attach_args *cba = aux; 1438 1439 if (cba->cba_slot >= 0) { 1440 printf(" slot %d", cba->cba_slot); 1441 } 1442 */ 1443 return UNCONF; 1444 } 1445 1446 /* 1447 * int pccbb_cardenable(struct pccbb_softc *sc, int function) 1448 * This function enables and disables the card 1449 */ 1450 int 1451 pccbb_cardenable(sc, function) 1452 struct pccbb_softc *sc; 1453 int function; 1454 { 1455 u_int32_t command = 1456 pci_conf_read(sc->sc_pc, sc->sc_tag, PCI_COMMAND_STATUS_REG); 1457 1458 DPRINTF(("pccbb_cardenable:")); 1459 switch (function) { 1460 case CARDBUS_IO_ENABLE: 1461 command |= PCI_COMMAND_IO_ENABLE; 1462 break; 1463 case CARDBUS_IO_DISABLE: 1464 command &= ~PCI_COMMAND_IO_ENABLE; 1465 break; 1466 case CARDBUS_MEM_ENABLE: 1467 command |= PCI_COMMAND_MEM_ENABLE; 1468 break; 1469 case CARDBUS_MEM_DISABLE: 1470 command &= ~PCI_COMMAND_MEM_ENABLE; 1471 break; 1472 case CARDBUS_BM_ENABLE: 1473 command |= PCI_COMMAND_MASTER_ENABLE; 1474 break; 1475 case CARDBUS_BM_DISABLE: 1476 command &= ~PCI_COMMAND_MASTER_ENABLE; 1477 break; 1478 default: 1479 return 0; 1480 } 1481 1482 pci_conf_write(sc->sc_pc, sc->sc_tag, PCI_COMMAND_STATUS_REG, command); 1483 DPRINTF((" command reg 0x%x\n", command)); 1484 return 1; 1485 } 1486 1487 #if !rbus 1488 /* 1489 * int pccbb_io_open(cardbus_chipset_tag_t, int, u_int32_t, u_int32_t) 1490 */ 1491 int 1492 pccbb_io_open(ct, win, start, end) 1493 cardbus_chipset_tag_t ct; 1494 int win; 1495 u_int32_t start, end; 1496 { 1497 struct pccbb_softc *sc = (struct pccbb_softc *)ct; 1498 int basereg; 1499 int limitreg; 1500 1501 if ((win < 0) || (win > 2)) { 1502 #if defined DIAGNOSTIC 1503 printf("cardbus_io_open: window out of range %d\n", win); 1504 #endif 1505 return 0; 1506 } 1507 1508 basereg = win * 8 + 0x2c; 1509 limitreg = win * 8 + 0x30; 1510 1511 DPRINTF(("pccbb_io_open: 0x%x[0x%x] - 0x%x[0x%x]\n", 1512 start, basereg, end, limitreg)); 1513 1514 pci_conf_write(sc->sc_pc, sc->sc_tag, basereg, start); 1515 pci_conf_write(sc->sc_pc, sc->sc_tag, limitreg, end); 1516 return 1; 1517 } 1518 1519 /* 1520 * int pccbb_io_close(cardbus_chipset_tag_t, int) 1521 */ 1522 int 1523 pccbb_io_close(ct, win) 1524 cardbus_chipset_tag_t ct; 1525 int win; 1526 { 1527 struct pccbb_softc *sc = (struct pccbb_softc *)ct; 1528 int basereg; 1529 int limitreg; 1530 1531 if ((win < 0) || (win > 2)) { 1532 #if defined DIAGNOSTIC 1533 printf("cardbus_io_close: window out of range %d\n", win); 1534 #endif 1535 return 0; 1536 } 1537 1538 basereg = win * 8 + 0x2c; 1539 limitreg = win * 8 + 0x30; 1540 1541 pci_conf_write(sc->sc_pc, sc->sc_tag, basereg, 0); 1542 pci_conf_write(sc->sc_pc, sc->sc_tag, limitreg, 0); 1543 return 1; 1544 } 1545 1546 /* 1547 * int pccbb_mem_open(cardbus_chipset_tag_t, int, u_int32_t, u_int32_t) 1548 */ 1549 int 1550 pccbb_mem_open(ct, win, start, end) 1551 cardbus_chipset_tag_t ct; 1552 int win; 1553 u_int32_t start, end; 1554 { 1555 struct pccbb_softc *sc = (struct pccbb_softc *)ct; 1556 int basereg; 1557 int limitreg; 1558 1559 if ((win < 0) || (win > 2)) { 1560 #if defined DIAGNOSTIC 1561 printf("cardbus_mem_open: window out of range %d\n", win); 1562 #endif 1563 return 0; 1564 } 1565 1566 basereg = win * 8 + 0x1c; 1567 limitreg = win * 8 + 0x20; 1568 1569 pci_conf_write(sc->sc_pc, sc->sc_tag, basereg, start); 1570 pci_conf_write(sc->sc_pc, sc->sc_tag, limitreg, end); 1571 return 1; 1572 } 1573 1574 /* 1575 * int pccbb_mem_close(cardbus_chipset_tag_t, int) 1576 */ 1577 int 1578 pccbb_mem_close(ct, win) 1579 cardbus_chipset_tag_t ct; 1580 int win; 1581 { 1582 struct pccbb_softc *sc = (struct pccbb_softc *)ct; 1583 int basereg; 1584 int limitreg; 1585 1586 if ((win < 0) || (win > 2)) { 1587 #if defined DIAGNOSTIC 1588 printf("cardbus_mem_close: window out of range %d\n", win); 1589 #endif 1590 return 0; 1591 } 1592 1593 basereg = win * 8 + 0x1c; 1594 limitreg = win * 8 + 0x20; 1595 1596 pci_conf_write(sc->sc_pc, sc->sc_tag, basereg, 0); 1597 pci_conf_write(sc->sc_pc, sc->sc_tag, limitreg, 0); 1598 return 1; 1599 } 1600 #endif 1601 1602 /* 1603 * void *pccbb_cb_intr_establish(cardbus_chipset_tag_t ct, 1604 * int irq, 1605 * int level, 1606 * int (* func) __P((void *)), 1607 * void *arg) 1608 * 1609 * This function registers an interrupt handler at the bridge, in 1610 * order not to call the interrupt handlers of child devices when 1611 * a card-deletion interrupt occurs. 1612 * 1613 * The arguments irq is not used because pccbb selects intr vector. 1614 */ 1615 void * 1616 pccbb_cb_intr_establish(ct, irq, level, func, arg) 1617 cardbus_chipset_tag_t ct; 1618 int irq, level; 1619 int (*func) __P((void *)); 1620 void *arg; 1621 { 1622 struct pccbb_softc *sc = (struct pccbb_softc *)ct; 1623 1624 return pccbb_intr_establish(sc, irq, level, func, arg); 1625 } 1626 1627 1628 /* 1629 * void *pccbb_cb_intr_disestablish(cardbus_chipset_tag_t ct, 1630 * void *ih) 1631 * 1632 * This function removes an interrupt handler pointed by ih. 1633 */ 1634 void 1635 pccbb_cb_intr_disestablish(ct, ih) 1636 cardbus_chipset_tag_t ct; 1637 void *ih; 1638 { 1639 struct pccbb_softc *sc = (struct pccbb_softc *)ct; 1640 1641 pccbb_intr_disestablish(sc, ih); 1642 } 1643 1644 1645 /* 1646 * void *pccbb_intr_establish(struct pccbb_softc *sc, 1647 * int irq, 1648 * int level, 1649 * int (* func) __P((void *)), 1650 * void *arg) 1651 * 1652 * This function registers an interrupt handler at the bridge, in 1653 * order not to call the interrupt handlers of child devices when 1654 * a card-deletion interrupt occurs. 1655 * 1656 * The arguments irq and level are not used. 1657 */ 1658 void * 1659 pccbb_intr_establish(sc, irq, level, func, arg) 1660 struct pccbb_softc *sc; 1661 int irq, level; 1662 int (*func) __P((void *)); 1663 void *arg; 1664 { 1665 struct pccbb_intrhand_list *pil, *newpil; 1666 pcireg_t reg; 1667 1668 DPRINTF(("pccbb_intr_establish start. %p\n", sc->sc_pil)); 1669 1670 if (sc->sc_pil == NULL) { 1671 /* initialize bridge intr routing */ 1672 reg = pci_conf_read(sc->sc_pc, sc->sc_tag, PCI_BCR_INTR); 1673 reg &= ~CB_BCR_INTR_IREQ_ENABLE; 1674 pci_conf_write(sc->sc_pc, sc->sc_tag, PCI_BCR_INTR, reg); 1675 1676 switch (sc->sc_chipset) { 1677 case CB_TI113X: 1678 reg = pci_conf_read(sc->sc_pc, sc->sc_tag, PCI_CBCTRL); 1679 /* functional intr enabled */ 1680 reg |= PCI113X_CBCTRL_PCI_INTR; 1681 pci_conf_write(sc->sc_pc, sc->sc_tag, PCI_CBCTRL, reg); 1682 break; 1683 default: 1684 break; 1685 } 1686 } 1687 1688 /* 1689 * Allocate a room for interrupt handler structure. 1690 */ 1691 newpil = (struct pccbb_intrhand_list *) 1692 malloc(sizeof(struct pccbb_intrhand_list), M_DEVBUF, M_WAITOK); 1693 1694 newpil->pil_func = func; 1695 newpil->pil_arg = arg; 1696 newpil->pil_level = level; 1697 newpil->pil_next = NULL; 1698 1699 if (sc->sc_pil == NULL) { 1700 sc->sc_pil = newpil; 1701 } else { 1702 for (pil = sc->sc_pil; pil->pil_next != NULL; 1703 pil = pil->pil_next); 1704 pil->pil_next = newpil; 1705 } 1706 1707 DPRINTF(("pccbb_intr_establish add pil. %p\n", sc->sc_pil)); 1708 1709 return newpil; 1710 } 1711 1712 /* 1713 * void *pccbb_intr_disestablish(struct pccbb_softc *sc, 1714 * void *ih) 1715 * 1716 * This function removes an interrupt handler pointed by ih. 1717 */ 1718 void 1719 pccbb_intr_disestablish(sc, ih) 1720 struct pccbb_softc *sc; 1721 void *ih; 1722 { 1723 struct pccbb_intrhand_list *pil, **pil_prev; 1724 pcireg_t reg; 1725 1726 DPRINTF(("pccbb_intr_disestablish start. %p\n", sc->sc_pil)); 1727 1728 pil_prev = &sc->sc_pil; 1729 1730 for (pil = sc->sc_pil; pil != NULL; pil = pil->pil_next) { 1731 if (pil == ih) { 1732 *pil_prev = pil->pil_next; 1733 free(pil, M_DEVBUF); 1734 DPRINTF(("pccbb_intr_disestablish frees one pil\n")); 1735 break; 1736 } 1737 pil_prev = &pil->pil_next; 1738 } 1739 1740 if (sc->sc_pil == NULL) { 1741 /* No interrupt handlers */ 1742 1743 DPRINTF(("pccbb_intr_disestablish: no interrupt handler\n")); 1744 1745 /* stop routing PCI intr */ 1746 reg = pci_conf_read(sc->sc_pc, sc->sc_tag, PCI_BCR_INTR); 1747 reg |= CB_BCR_INTR_IREQ_ENABLE; 1748 pci_conf_write(sc->sc_pc, sc->sc_tag, PCI_BCR_INTR, reg); 1749 1750 switch (sc->sc_chipset) { 1751 case CB_TI113X: 1752 reg = pci_conf_read(sc->sc_pc, sc->sc_tag, PCI_CBCTRL); 1753 /* functional intr disabled */ 1754 reg &= ~PCI113X_CBCTRL_PCI_INTR; 1755 pci_conf_write(sc->sc_pc, sc->sc_tag, PCI_CBCTRL, reg); 1756 break; 1757 default: 1758 break; 1759 } 1760 } 1761 } 1762 1763 #if defined SHOW_REGS 1764 void 1765 cb_show_regs(pc, tag, memt, memh) 1766 pci_chipset_tag_t pc; 1767 pcitag_t tag; 1768 bus_space_tag_t memt; 1769 bus_space_handle_t memh; 1770 { 1771 int i; 1772 printf("PCI config regs:"); 1773 for (i = 0; i < 0x50; i += 4) { 1774 if (i % 16 == 0) { 1775 printf("\n 0x%02x:", i); 1776 } 1777 printf(" %08x", pci_conf_read(pc, tag, i)); 1778 } 1779 for (i = 0x80; i < 0xb0; i += 4) { 1780 if (i % 16 == 0) { 1781 printf("\n 0x%02x:", i); 1782 } 1783 printf(" %08x", pci_conf_read(pc, tag, i)); 1784 } 1785 1786 if (memh == 0) { 1787 printf("\n"); 1788 return; 1789 } 1790 1791 printf("\nsocket regs:"); 1792 for (i = 0; i <= 0x10; i += 0x04) { 1793 printf(" %08x", bus_space_read_4(memt, memh, i)); 1794 } 1795 printf("\nExCA regs:"); 1796 for (i = 0; i < 0x08; ++i) { 1797 printf(" %02x", bus_space_read_1(memt, memh, 0x800 + i)); 1798 } 1799 printf("\n"); 1800 return; 1801 } 1802 #endif 1803 1804 /* 1805 * cardbustag_t pccbb_make_tag(cardbus_chipset_tag_t cc, 1806 * int busno, int devno, int function) 1807 * This is the function to make a tag to access config space of 1808 * a CardBus Card. It works same as pci_conf_read. 1809 */ 1810 cardbustag_t 1811 pccbb_make_tag(cc, busno, devno, function) 1812 cardbus_chipset_tag_t cc; 1813 int busno, devno, function; 1814 { 1815 struct pccbb_softc *sc = (struct pccbb_softc *)cc; 1816 1817 return pci_make_tag(sc->sc_pc, busno, devno, function); 1818 } 1819 1820 void 1821 pccbb_free_tag(cc, tag) 1822 cardbus_chipset_tag_t cc; 1823 cardbustag_t tag; 1824 { 1825 } 1826 1827 /* 1828 * cardbusreg_t pccbb_conf_read(cardbus_chipset_tag_t cc, 1829 * cardbustag_t tag, int offset) 1830 * This is the function to read the config space of a CardBus Card. 1831 * It works same as pci_conf_read. 1832 */ 1833 cardbusreg_t 1834 pccbb_conf_read(cc, tag, offset) 1835 cardbus_chipset_tag_t cc; 1836 cardbustag_t tag; 1837 int offset; /* register offset */ 1838 { 1839 struct pccbb_softc *sc = (struct pccbb_softc *)cc; 1840 1841 return pci_conf_read(sc->sc_pc, tag, offset); 1842 } 1843 1844 /* 1845 * void pccbb_conf_write(cardbus_chipset_tag_t cc, cardbustag_t tag, 1846 * int offs, cardbusreg_t val) 1847 * This is the function to write the config space of a CardBus Card. 1848 * It works same as pci_conf_write. 1849 */ 1850 void 1851 pccbb_conf_write(cc, tag, reg, val) 1852 cardbus_chipset_tag_t cc; 1853 cardbustag_t tag; 1854 int reg; /* register offset */ 1855 cardbusreg_t val; 1856 { 1857 struct pccbb_softc *sc = (struct pccbb_softc *)cc; 1858 1859 pci_conf_write(sc->sc_pc, tag, reg, val); 1860 } 1861 1862 #if 0 1863 int 1864 pccbb_new_pcmcia_io_alloc(pcmcia_chipset_handle_t pch, 1865 bus_addr_t start, bus_size_t size, bus_size_t align, bus_addr_t mask, 1866 int speed, int flags, 1867 bus_space_handle_t * iohp) 1868 #endif 1869 /* 1870 * int pccbb_pcmcia_io_alloc(pcmcia_chipset_handle_t pch, 1871 * bus_addr_t start, bus_size_t size, 1872 * bus_size_t align, 1873 * struct pcmcia_io_handle *pcihp 1874 * 1875 * This function only allocates I/O region for pccard. This function 1876 * never maps the allocated region to pccard I/O area. 1877 * 1878 * XXX: The interface of this function is not very good, I believe. 1879 */ 1880 int 1881 pccbb_pcmcia_io_alloc(pch, start, size, align, pcihp) 1882 pcmcia_chipset_handle_t pch; 1883 bus_addr_t start; /* start address */ 1884 bus_size_t size; 1885 bus_size_t align; 1886 struct pcmcia_io_handle *pcihp; 1887 { 1888 struct pcic_handle *ph = (struct pcic_handle *)pch; 1889 bus_addr_t ioaddr; 1890 int flags = 0; 1891 bus_space_tag_t iot; 1892 bus_space_handle_t ioh; 1893 #if rbus 1894 rbus_tag_t rb; 1895 #endif 1896 if (align == 0) { 1897 align = size; /* XXX: funny??? */ 1898 } 1899 1900 /* 1901 * Allocate some arbitrary I/O space. 1902 */ 1903 1904 iot = ((struct pccbb_softc *)(ph->ph_parent))->sc_iot; 1905 1906 #if rbus 1907 rb = ((struct pccbb_softc *)(ph->ph_parent))->sc_rbus_iot; 1908 /* XXX: I assume all card decode lower 10 bits by its hardware */ 1909 if (rbus_space_alloc(rb, start, size, 0x3ff, align, 0, &ioaddr, &ioh)) { 1910 return 1; 1911 } 1912 #else 1913 if (start) { 1914 ioaddr = start; 1915 if (bus_space_map(iot, start, size, 0, &ioh)) { 1916 return 1; 1917 } 1918 DPRINTF(("pccbb_pcmcia_io_alloc map port %lx+%lx\n", 1919 (u_long) ioaddr, (u_long) size)); 1920 } else { 1921 flags |= PCMCIA_IO_ALLOCATED; 1922 if (bus_space_alloc(iot, 0x700 /* ph->sc->sc_iobase */ , 1923 0x800, /* ph->sc->sc_iobase + ph->sc->sc_iosize */ 1924 size, align, 0, 0, &ioaddr, &ioh)) { 1925 /* No room be able to be get. */ 1926 return 1; 1927 } 1928 DPRINTF(("pccbb_pcmmcia_io_alloc alloc port 0x%lx+0x%lx\n", 1929 (u_long) ioaddr, (u_long) size)); 1930 } 1931 #endif 1932 1933 pcihp->iot = iot; 1934 pcihp->ioh = ioh; 1935 pcihp->addr = ioaddr; 1936 pcihp->size = size; 1937 pcihp->flags = flags; 1938 1939 return 0; 1940 } 1941 1942 /* 1943 * int pccbb_pcmcia_io_free(pcmcia_chipset_handle_t pch, 1944 * struct pcmcia_io_handle *pcihp) 1945 * 1946 * This function only frees I/O region for pccard. 1947 * 1948 * XXX: The interface of this function is not very good, I believe. 1949 */ 1950 void 1951 pccbb_pcmcia_io_free(pch, pcihp) 1952 pcmcia_chipset_handle_t pch; 1953 struct pcmcia_io_handle *pcihp; 1954 { 1955 #if !rbus 1956 bus_space_tag_t iot = pcihp->iot; 1957 #endif 1958 bus_space_handle_t ioh = pcihp->ioh; 1959 bus_size_t size = pcihp->size; 1960 1961 #if rbus 1962 struct pccbb_softc *sc = 1963 (struct pccbb_softc *)((struct pcic_handle *)pch)->ph_parent; 1964 rbus_tag_t rb = sc->sc_rbus_iot; 1965 1966 rbus_space_free(rb, ioh, size, NULL); 1967 #else 1968 if (pcihp->flags & PCMCIA_IO_ALLOCATED) 1969 bus_space_free(iot, ioh, size); 1970 else 1971 bus_space_unmap(iot, ioh, size); 1972 #endif 1973 } 1974 1975 /* 1976 * int pccbb_pcmcia_io_map(pcmcia_chipset_handle_t pch, int width, 1977 * bus_addr_t offset, bus_size_t size, 1978 * struct pcmcia_io_handle *pcihp, 1979 * int *windowp) 1980 * 1981 * This function maps the allocated I/O region to pccard. This function 1982 * never allocates any I/O region for pccard I/O area. I don't 1983 * understand why the original authors of pcmciabus separated alloc and 1984 * map. I believe the two must be unite. 1985 * 1986 * XXX: no wait timing control? 1987 */ 1988 int 1989 pccbb_pcmcia_io_map(pch, width, offset, size, pcihp, windowp) 1990 pcmcia_chipset_handle_t pch; 1991 int width; 1992 bus_addr_t offset; 1993 bus_size_t size; 1994 struct pcmcia_io_handle *pcihp; 1995 int *windowp; 1996 { 1997 struct pcic_handle *ph = (struct pcic_handle *)pch; 1998 bus_addr_t ioaddr = pcihp->addr + offset; 1999 int i, win; 2000 #if defined CBB_DEBUG 2001 static char *width_names[] = { "dynamic", "io8", "io16" }; 2002 #endif 2003 2004 /* Sanity check I/O handle. */ 2005 2006 if (((struct pccbb_softc *)ph->ph_parent)->sc_iot != pcihp->iot) { 2007 panic("pccbb_pcmcia_io_map iot is bogus"); 2008 } 2009 2010 /* XXX Sanity check offset/size. */ 2011 2012 win = -1; 2013 for (i = 0; i < PCIC_IO_WINS; i++) { 2014 if ((ph->ioalloc & (1 << i)) == 0) { 2015 win = i; 2016 ph->ioalloc |= (1 << i); 2017 break; 2018 } 2019 } 2020 2021 if (win == -1) { 2022 return 1; 2023 } 2024 2025 *windowp = win; 2026 2027 /* XXX this is pretty gross */ 2028 2029 DPRINTF(("pccbb_pcmcia_io_map window %d %s port %lx+%lx\n", 2030 win, width_names[width], (u_long) ioaddr, (u_long) size)); 2031 2032 /* XXX wtf is this doing here? */ 2033 2034 #if 0 2035 printf(" port 0x%lx", (u_long) ioaddr); 2036 if (size > 1) { 2037 printf("-0x%lx", (u_long) ioaddr + (u_long) size - 1); 2038 } 2039 #endif 2040 2041 ph->io[win].addr = ioaddr; 2042 ph->io[win].size = size; 2043 ph->io[win].width = width; 2044 2045 /* actual dirty register-value changing in the function below. */ 2046 pccbb_pcmcia_do_io_map(ph, win); 2047 2048 return 0; 2049 } 2050 2051 /* 2052 * void pccbb_pcmcia_do_io_map(struct pcic_handle *h, int win) 2053 * 2054 * This function changes register-value to map I/O region for pccard. 2055 */ 2056 void 2057 pccbb_pcmcia_do_io_map(ph, win) 2058 struct pcic_handle *ph; 2059 int win; 2060 { 2061 static u_int8_t pcic_iowidth[3] = { 2062 PCIC_IOCTL_IO0_IOCS16SRC_CARD, 2063 PCIC_IOCTL_IO0_IOCS16SRC_DATASIZE | 2064 PCIC_IOCTL_IO0_DATASIZE_8BIT, 2065 PCIC_IOCTL_IO0_IOCS16SRC_DATASIZE | 2066 PCIC_IOCTL_IO0_DATASIZE_16BIT, 2067 }; 2068 2069 #define PCIC_SIA_START_LOW 0 2070 #define PCIC_SIA_START_HIGH 1 2071 #define PCIC_SIA_STOP_LOW 2 2072 #define PCIC_SIA_STOP_HIGH 3 2073 2074 int regbase_win = 0x8 + win * 0x04; 2075 u_int8_t ioctl, enable; 2076 2077 DPRINTF( 2078 ("pccbb_pcmcia_do_io_map win %d addr 0x%lx size 0x%lx width %d\n", 2079 win, (long)ph->io[win].addr, (long)ph->io[win].size, 2080 ph->io[win].width * 8)); 2081 2082 Pcic_write(ph, regbase_win + PCIC_SIA_START_LOW, 2083 ph->io[win].addr & 0xff); 2084 Pcic_write(ph, regbase_win + PCIC_SIA_START_HIGH, 2085 (ph->io[win].addr >> 8) & 0xff); 2086 2087 Pcic_write(ph, regbase_win + PCIC_SIA_STOP_LOW, 2088 (ph->io[win].addr + ph->io[win].size - 1) & 0xff); 2089 Pcic_write(ph, regbase_win + PCIC_SIA_STOP_HIGH, 2090 ((ph->io[win].addr + ph->io[win].size - 1) >> 8) & 0xff); 2091 2092 ioctl = Pcic_read(ph, PCIC_IOCTL); 2093 enable = Pcic_read(ph, PCIC_ADDRWIN_ENABLE); 2094 switch (win) { 2095 case 0: 2096 ioctl &= ~(PCIC_IOCTL_IO0_WAITSTATE | PCIC_IOCTL_IO0_ZEROWAIT | 2097 PCIC_IOCTL_IO0_IOCS16SRC_MASK | 2098 PCIC_IOCTL_IO0_DATASIZE_MASK); 2099 ioctl |= pcic_iowidth[ph->io[win].width]; 2100 enable |= PCIC_ADDRWIN_ENABLE_IO0; 2101 break; 2102 case 1: 2103 ioctl &= ~(PCIC_IOCTL_IO1_WAITSTATE | PCIC_IOCTL_IO1_ZEROWAIT | 2104 PCIC_IOCTL_IO1_IOCS16SRC_MASK | 2105 PCIC_IOCTL_IO1_DATASIZE_MASK); 2106 ioctl |= (pcic_iowidth[ph->io[win].width] << 4); 2107 enable |= PCIC_ADDRWIN_ENABLE_IO1; 2108 break; 2109 } 2110 Pcic_write(ph, PCIC_IOCTL, ioctl); 2111 Pcic_write(ph, PCIC_ADDRWIN_ENABLE, enable); 2112 #if defined CBB_DEBUG 2113 { 2114 u_int8_t start_low = 2115 Pcic_read(ph, regbase_win + PCIC_SIA_START_LOW); 2116 u_int8_t start_high = 2117 Pcic_read(ph, regbase_win + PCIC_SIA_START_HIGH); 2118 u_int8_t stop_low = 2119 Pcic_read(ph, regbase_win + PCIC_SIA_STOP_LOW); 2120 u_int8_t stop_high = 2121 Pcic_read(ph, regbase_win + PCIC_SIA_STOP_HIGH); 2122 printf 2123 (" start %02x %02x, stop %02x %02x, ioctl %02x enable %02x\n", 2124 start_low, start_high, stop_low, stop_high, ioctl, enable); 2125 } 2126 #endif 2127 } 2128 2129 /* 2130 * void pccbb_pcmcia_io_unmap(pcmcia_chipset_handle_t *h, int win) 2131 * 2132 * This function unmaps I/O region. No return value. 2133 */ 2134 void 2135 pccbb_pcmcia_io_unmap(pch, win) 2136 pcmcia_chipset_handle_t pch; 2137 int win; 2138 { 2139 struct pcic_handle *ph = (struct pcic_handle *)pch; 2140 int reg; 2141 2142 if (win >= PCIC_IO_WINS || win < 0) { 2143 panic("pccbb_pcmcia_io_unmap: window out of range"); 2144 } 2145 2146 reg = Pcic_read(ph, PCIC_ADDRWIN_ENABLE); 2147 switch (win) { 2148 case 0: 2149 reg &= ~PCIC_ADDRWIN_ENABLE_IO0; 2150 break; 2151 case 1: 2152 reg &= ~PCIC_ADDRWIN_ENABLE_IO1; 2153 break; 2154 } 2155 Pcic_write(ph, PCIC_ADDRWIN_ENABLE, reg); 2156 2157 ph->ioalloc &= ~(1 << win); 2158 } 2159 2160 /* 2161 * void pccbb_pcmcia_wait_ready(struct pcic_handle *ph) 2162 * 2163 * This function enables the card. All information is stored in 2164 * the first argument, pcmcia_chipset_handle_t. 2165 */ 2166 void 2167 pccbb_pcmcia_wait_ready(ph) 2168 struct pcic_handle *ph; 2169 { 2170 int i; 2171 2172 DPRINTF(("pccbb_pcmcia_wait_ready: status 0x%02x\n", 2173 Pcic_read(ph, PCIC_IF_STATUS))); 2174 2175 for (i = 0; i < 10000; i++) { 2176 if (Pcic_read(ph, PCIC_IF_STATUS) & PCIC_IF_STATUS_READY) { 2177 return; 2178 } 2179 delay(500); 2180 #ifdef CBB_DEBUG 2181 if ((i > 5000) && (i % 100 == 99)) 2182 printf("."); 2183 #endif 2184 } 2185 2186 #ifdef DIAGNOSTIC 2187 printf("pcic_wait_ready: ready never happened, status = %02x\n", 2188 Pcic_read(ph, PCIC_IF_STATUS)); 2189 #endif 2190 } 2191 2192 /* 2193 * void pccbb_pcmcia_socket_enable(pcmcia_chipset_handle_t pch) 2194 * 2195 * This function enables the card. All information is stored in 2196 * the first argument, pcmcia_chipset_handle_t. 2197 */ 2198 void 2199 pccbb_pcmcia_socket_enable(pch) 2200 pcmcia_chipset_handle_t pch; 2201 { 2202 struct pcic_handle *ph = (struct pcic_handle *)pch; 2203 struct pccbb_softc *sc = (struct pccbb_softc *)ph->ph_parent; 2204 int cardtype, win; 2205 u_int8_t power, intr; 2206 pcireg_t spsr; 2207 int voltage; 2208 2209 /* this bit is mostly stolen from pcic_attach_card */ 2210 2211 DPRINTF(("pccbb_pcmcia_socket_enable: ")); 2212 2213 /* get card Vcc info */ 2214 2215 spsr = 2216 bus_space_read_4(sc->sc_base_memt, sc->sc_base_memh, 2217 CB_SOCKET_STAT); 2218 if (spsr & CB_SOCKET_STAT_5VCARD) { 2219 DPRINTF(("5V card\n")); 2220 voltage = CARDBUS_VCC_5V | CARDBUS_VPP_VCC; 2221 } else if (spsr & CB_SOCKET_STAT_3VCARD) { 2222 DPRINTF(("3V card\n")); 2223 voltage = CARDBUS_VCC_3V | CARDBUS_VPP_VCC; 2224 } else { 2225 printf("?V card, 0x%x\n", spsr); /* XXX */ 2226 return; 2227 } 2228 2229 /* disable socket i/o: negate output enable bit */ 2230 2231 power = 0; 2232 Pcic_write(ph, PCIC_PWRCTL, power); 2233 2234 /* power down the socket to reset it, clear the card reset pin */ 2235 2236 pccbb_power(sc, CARDBUS_VCC_0V | CARDBUS_VPP_0V); 2237 2238 /* 2239 * wait 200ms until power fails (Tpf). Then, wait 100ms since 2240 * we are changing Vcc (Toff). 2241 */ 2242 /* delay(300*1000); too much */ 2243 2244 /* assert reset bit */ 2245 intr = Pcic_read(ph, PCIC_INTR); 2246 intr &= ~(PCIC_INTR_RESET | PCIC_INTR_CARDTYPE_MASK); 2247 Pcic_write(ph, PCIC_INTR, intr); 2248 2249 /* power up the socket and output enable */ 2250 power = Pcic_read(ph, PCIC_PWRCTL); 2251 power |= PCIC_PWRCTL_OE; 2252 Pcic_write(ph, PCIC_PWRCTL, power); 2253 pccbb_power(sc, voltage); 2254 2255 /* 2256 * hold RESET at least 10us. 2257 */ 2258 delay(10); 2259 delay(2 * 1000); /* XXX: TI1130 requires it. */ 2260 delay(20 * 1000); /* XXX: TI1130 requires it. */ 2261 2262 /* clear the reset flag */ 2263 2264 intr |= PCIC_INTR_RESET; 2265 Pcic_write(ph, PCIC_INTR, intr); 2266 2267 /* wait 20ms as per pc card standard (r2.01) section 4.3.6 */ 2268 2269 delay(20000); 2270 2271 /* wait for the chip to finish initializing */ 2272 2273 pccbb_pcmcia_wait_ready(ph); 2274 2275 /* zero out the address windows */ 2276 2277 Pcic_write(ph, PCIC_ADDRWIN_ENABLE, 0); 2278 2279 /* set the card type */ 2280 2281 cardtype = pcmcia_card_gettype(ph->pcmcia); 2282 2283 intr |= ((cardtype == PCMCIA_IFTYPE_IO) ? 2284 PCIC_INTR_CARDTYPE_IO : PCIC_INTR_CARDTYPE_MEM); 2285 Pcic_write(ph, PCIC_INTR, intr); 2286 2287 DPRINTF(("%s: pccbb_pcmcia_socket_enable %02x cardtype %s %02x\n", 2288 ph->ph_parent->dv_xname, ph->sock, 2289 ((cardtype == PCMCIA_IFTYPE_IO) ? "io" : "mem"), intr)); 2290 2291 /* reinstall all the memory and io mappings */ 2292 2293 for (win = 0; win < PCIC_MEM_WINS; ++win) { 2294 if (ph->memalloc & (1 << win)) { 2295 pccbb_pcmcia_do_mem_map(ph, win); 2296 } 2297 } 2298 2299 for (win = 0; win < PCIC_IO_WINS; ++win) { 2300 if (ph->ioalloc & (1 << win)) { 2301 pccbb_pcmcia_do_io_map(ph, win); 2302 } 2303 } 2304 } 2305 2306 /* 2307 * void pccbb_pcmcia_socket_disable(pcmcia_chipset_handle_t *ph) 2308 * 2309 * This function disables the card. All information is stored in 2310 * the first argument, pcmcia_chipset_handle_t. 2311 */ 2312 void 2313 pccbb_pcmcia_socket_disable(pch) 2314 pcmcia_chipset_handle_t pch; 2315 { 2316 struct pcic_handle *ph = (struct pcic_handle *)pch; 2317 struct pccbb_softc *sc = (struct pccbb_softc *)ph->ph_parent; 2318 u_int8_t power, intr; 2319 2320 DPRINTF(("pccbb_pcmcia_socket_disable\n")); 2321 2322 /* reset signal asserting... */ 2323 2324 intr = Pcic_read(ph, PCIC_INTR); 2325 intr &= ~(PCIC_INTR_CARDTYPE_MASK); 2326 Pcic_write(ph, PCIC_INTR, intr); 2327 delay(2 * 1000); 2328 2329 /* power down the socket */ 2330 power = Pcic_read(ph, PCIC_PWRCTL); 2331 power &= ~PCIC_PWRCTL_OE; 2332 Pcic_write(ph, PCIC_PWRCTL, power); 2333 pccbb_power(sc, CARDBUS_VCC_0V | CARDBUS_VPP_0V); 2334 /* 2335 * wait 300ms until power fails (Tpf). 2336 */ 2337 delay(300 * 1000); 2338 } 2339 2340 /* 2341 * int pccbb_pcmcia_card_detect(pcmcia_chipset_handle_t *ph) 2342 * 2343 * This function detects whether a card is in the slot or not. 2344 * If a card is inserted, return 1. Otherwise, return 0. 2345 */ 2346 int 2347 pccbb_pcmcia_card_detect(pch) 2348 pcmcia_chipset_handle_t pch; 2349 { 2350 struct pcic_handle *ph = (struct pcic_handle *)pch; 2351 struct pccbb_softc *sc = (struct pccbb_softc *)ph->ph_parent; 2352 2353 DPRINTF(("pccbb_pcmcia_card_detect\n")); 2354 return pccbb_detect_card(sc) == 1 ? 1 : 0; 2355 } 2356 2357 #if 0 2358 int 2359 pccbb_new_pcmcia_mem_alloc(pcmcia_chipset_handle_t pch, 2360 bus_addr_t start, bus_size_t size, bus_size_t align, int speed, int flags, 2361 bus_space_tag_t * memtp bus_space_handle_t * memhp) 2362 #endif 2363 /* 2364 * int pccbb_pcmcia_mem_alloc(pcmcia_chipset_handle_t pch, 2365 * bus_size_t size, 2366 * struct pcmcia_mem_handle *pcmhp) 2367 * 2368 * This function only allocates memory region for pccard. This 2369 * function never maps the allocated region to pccard memory area. 2370 * 2371 * XXX: Why the argument of start address is not in? 2372 */ 2373 int 2374 pccbb_pcmcia_mem_alloc(pch, size, pcmhp) 2375 pcmcia_chipset_handle_t pch; 2376 bus_size_t size; 2377 struct pcmcia_mem_handle *pcmhp; 2378 { 2379 struct pcic_handle *ph = (struct pcic_handle *)pch; 2380 bus_space_handle_t memh; 2381 bus_addr_t addr; 2382 bus_size_t sizepg; 2383 struct pccbb_softc *sc = (struct pccbb_softc *)ph->ph_parent; 2384 #if rbus 2385 rbus_tag_t rb; 2386 #endif 2387 2388 /* out of sc->memh, allocate as many pages as necessary */ 2389 2390 /* convert size to PCIC pages */ 2391 /* 2392 * This is not enough; when the requested region is on the page 2393 * boundaries, this may calculate wrong result. 2394 */ 2395 sizepg = (size + (PCIC_MEM_PAGESIZE - 1)) / PCIC_MEM_PAGESIZE; 2396 #if 0 2397 if (sizepg > PCIC_MAX_MEM_PAGES) { 2398 return 1; 2399 } 2400 #endif 2401 2402 if (!(sc->sc_pcmcia_flags & PCCBB_PCMCIA_MEM_32)) { 2403 return 1; 2404 } 2405 2406 addr = 0; /* XXX gcc -Wuninitialized */ 2407 2408 #if rbus 2409 rb = sc->sc_rbus_memt; 2410 if (rbus_space_alloc(rb, 0, sizepg * PCIC_MEM_PAGESIZE, 2411 sizepg * PCIC_MEM_PAGESIZE - 1, PCIC_MEM_PAGESIZE, 0, 2412 &addr, &memh)) { 2413 return 1; 2414 } 2415 #else 2416 if (bus_space_alloc(sc->sc_memt, sc->sc_mem_start, sc->sc_mem_end, 2417 sizepg * PCIC_MEM_PAGESIZE, PCIC_MEM_PAGESIZE, 2418 0, /* boundary */ 2419 0, /* flags */ 2420 &addr, &memh)) { 2421 return 1; 2422 } 2423 #endif 2424 2425 DPRINTF( 2426 ("pccbb_pcmcia_alloc_mem: addr 0x%lx size 0x%lx, realsize 0x%lx\n", 2427 addr, size, sizepg * PCIC_MEM_PAGESIZE)); 2428 2429 pcmhp->memt = sc->sc_memt; 2430 pcmhp->memh = memh; 2431 pcmhp->addr = addr; 2432 pcmhp->size = size; 2433 pcmhp->realsize = sizepg * PCIC_MEM_PAGESIZE; 2434 /* What is mhandle? I feel it is very dirty and it must go trush. */ 2435 pcmhp->mhandle = 0; 2436 /* No offset??? Funny. */ 2437 2438 return 0; 2439 } 2440 2441 /* 2442 * void pccbb_pcmcia_mem_free(pcmcia_chipset_handle_t pch, 2443 * struct pcmcia_mem_handle *pcmhp) 2444 * 2445 * This function release the memory space allocated by the function 2446 * pccbb_pcmcia_mem_alloc(). 2447 */ 2448 void 2449 pccbb_pcmcia_mem_free(pch, pcmhp) 2450 pcmcia_chipset_handle_t pch; 2451 struct pcmcia_mem_handle *pcmhp; 2452 { 2453 #if rbus 2454 struct pcic_handle *ph = (struct pcic_handle *)pch; 2455 struct pccbb_softc *sc = (struct pccbb_softc *)ph->ph_parent; 2456 2457 rbus_space_free(sc->sc_rbus_memt, pcmhp->memh, pcmhp->realsize, NULL); 2458 #else 2459 bus_space_free(pcmhp->memt, pcmhp->memh, pcmhp->realsize); 2460 #endif 2461 } 2462 2463 /* 2464 * void pccbb_pcmcia_do_mem_map(struct pcic_handle *ph, int win) 2465 * 2466 * This function release the memory space allocated by the function 2467 * pccbb_pcmcia_mem_alloc(). 2468 */ 2469 void 2470 pccbb_pcmcia_do_mem_map(ph, win) 2471 struct pcic_handle *ph; 2472 int win; 2473 { 2474 int regbase_win; 2475 bus_addr_t phys_addr; 2476 bus_addr_t phys_end; 2477 2478 #define PCIC_SMM_START_LOW 0 2479 #define PCIC_SMM_START_HIGH 1 2480 #define PCIC_SMM_STOP_LOW 2 2481 #define PCIC_SMM_STOP_HIGH 3 2482 #define PCIC_CMA_LOW 4 2483 #define PCIC_CMA_HIGH 5 2484 2485 u_int8_t start_low, start_high = 0; 2486 u_int8_t stop_low, stop_high; 2487 u_int8_t off_low, off_high; 2488 u_int8_t mem_window; 2489 int reg; 2490 2491 regbase_win = 0x10 + win * 0x08; 2492 2493 phys_addr = ph->mem[win].addr; 2494 phys_end = phys_addr + ph->mem[win].size; 2495 2496 DPRINTF(("pccbb_pcmcia_do_mem_map: start 0x%lx end 0x%lx off 0x%lx\n", 2497 phys_addr, phys_end, ph->mem[win].offset)); 2498 2499 #define PCIC_MEMREG_LSB_SHIFT PCIC_SYSMEM_ADDRX_SHIFT 2500 #define PCIC_MEMREG_MSB_SHIFT (PCIC_SYSMEM_ADDRX_SHIFT + 8) 2501 #define PCIC_MEMREG_WIN_SHIFT (PCIC_SYSMEM_ADDRX_SHIFT + 12) 2502 2503 /* bit 19:12 */ 2504 start_low = (phys_addr >> PCIC_MEMREG_LSB_SHIFT) & 0xff; 2505 /* bit 23:20 and bit 7 on */ 2506 start_high = ((phys_addr >> PCIC_MEMREG_MSB_SHIFT) & 0x0f) 2507 | PCIC_SYSMEM_ADDRX_START_MSB_DATASIZE_16BIT; /* bit 7 on */ 2508 /* bit 31:24, for 32-bit address */ 2509 mem_window = (phys_addr >> PCIC_MEMREG_WIN_SHIFT) & 0xff; 2510 2511 Pcic_write(ph, regbase_win + PCIC_SMM_START_LOW, start_low); 2512 Pcic_write(ph, regbase_win + PCIC_SMM_START_HIGH, start_high); 2513 2514 if (((struct pccbb_softc *)ph-> 2515 ph_parent)->sc_pcmcia_flags & PCCBB_PCMCIA_MEM_32) { 2516 Pcic_write(ph, 0x40 + win, mem_window); 2517 } 2518 2519 stop_low = (phys_end >> PCIC_MEMREG_LSB_SHIFT) & 0xff; 2520 stop_high = ((phys_end >> PCIC_MEMREG_MSB_SHIFT) & 0x0f) 2521 | PCIC_SYSMEM_ADDRX_STOP_MSB_WAIT2; /* wait 2 cycles */ 2522 /* XXX Geee, WAIT2!! Crazy!! I must rewrite this routine. */ 2523 2524 Pcic_write(ph, regbase_win + PCIC_SMM_STOP_LOW, stop_low); 2525 Pcic_write(ph, regbase_win + PCIC_SMM_STOP_HIGH, stop_high); 2526 2527 off_low = (ph->mem[win].offset >> PCIC_CARDMEM_ADDRX_SHIFT) & 0xff; 2528 off_high = ((ph->mem[win].offset >> (PCIC_CARDMEM_ADDRX_SHIFT + 8)) 2529 & PCIC_CARDMEM_ADDRX_MSB_ADDR_MASK) 2530 | ((ph->mem[win].kind == PCMCIA_MEM_ATTR) ? 2531 PCIC_CARDMEM_ADDRX_MSB_REGACTIVE_ATTR : 0); 2532 2533 Pcic_write(ph, regbase_win + PCIC_CMA_LOW, off_low); 2534 Pcic_write(ph, regbase_win + PCIC_CMA_HIGH, off_high); 2535 2536 reg = Pcic_read(ph, PCIC_ADDRWIN_ENABLE); 2537 reg |= ((1 << win) | PCIC_ADDRWIN_ENABLE_MEMCS16); 2538 Pcic_write(ph, PCIC_ADDRWIN_ENABLE, reg); 2539 2540 #if defined CBB_DEBUG 2541 { 2542 int r1, r2, r3, r4, r5, r6, r7 = 0; 2543 2544 r1 = Pcic_read(ph, regbase_win + PCIC_SMM_START_LOW); 2545 r2 = Pcic_read(ph, regbase_win + PCIC_SMM_START_HIGH); 2546 r3 = Pcic_read(ph, regbase_win + PCIC_SMM_STOP_LOW); 2547 r4 = Pcic_read(ph, regbase_win + PCIC_SMM_STOP_HIGH); 2548 r5 = Pcic_read(ph, regbase_win + PCIC_CMA_LOW); 2549 r6 = Pcic_read(ph, regbase_win + PCIC_CMA_HIGH); 2550 if (((struct pccbb_softc *)(ph-> 2551 ph_parent))->sc_pcmcia_flags & PCCBB_PCMCIA_MEM_32) { 2552 r7 = Pcic_read(ph, 0x40 + win); 2553 } 2554 2555 DPRINTF(("pccbb_pcmcia_do_mem_map window %d: %02x%02x %02x%02x " 2556 "%02x%02x", win, r1, r2, r3, r4, r5, r6)); 2557 if (((struct pccbb_softc *)(ph-> 2558 ph_parent))->sc_pcmcia_flags & PCCBB_PCMCIA_MEM_32) { 2559 DPRINTF((" %02x", r7)); 2560 } 2561 DPRINTF(("\n")); 2562 } 2563 #endif 2564 } 2565 2566 /* 2567 * int pccbb_pcmcia_mem_map(pcmcia_chipset_handle_t pch, int kind, 2568 * bus_addr_t card_addr, bus_size_t size, 2569 * struct pcmcia_mem_handle *pcmhp, 2570 * bus_addr_t *offsetp, int *windowp) 2571 * 2572 * This function maps memory space allocated by the function 2573 * pccbb_pcmcia_mem_alloc(). 2574 */ 2575 int 2576 pccbb_pcmcia_mem_map(pch, kind, card_addr, size, pcmhp, offsetp, windowp) 2577 pcmcia_chipset_handle_t pch; 2578 int kind; 2579 bus_addr_t card_addr; 2580 bus_size_t size; 2581 struct pcmcia_mem_handle *pcmhp; 2582 bus_addr_t *offsetp; 2583 int *windowp; 2584 { 2585 struct pcic_handle *ph = (struct pcic_handle *)pch; 2586 bus_addr_t busaddr; 2587 long card_offset; 2588 int win; 2589 2590 for (win = 0; win < PCIC_MEM_WINS; ++win) { 2591 if ((ph->memalloc & (1 << win)) == 0) { 2592 ph->memalloc |= (1 << win); 2593 break; 2594 } 2595 } 2596 2597 if (win == PCIC_MEM_WINS) { 2598 return 1; 2599 } 2600 2601 *windowp = win; 2602 2603 /* XXX this is pretty gross */ 2604 2605 if (((struct pccbb_softc *)ph->ph_parent)->sc_memt != pcmhp->memt) { 2606 panic("pccbb_pcmcia_mem_map memt is bogus"); 2607 } 2608 2609 busaddr = pcmhp->addr; 2610 2611 /* 2612 * compute the address offset to the pcmcia address space for the 2613 * pcic. this is intentionally signed. The masks and shifts below 2614 * will cause TRT to happen in the pcic registers. Deal with making 2615 * sure the address is aligned, and return the alignment offset. 2616 */ 2617 2618 *offsetp = card_addr % PCIC_MEM_PAGESIZE; 2619 card_addr -= *offsetp; 2620 2621 DPRINTF(("pccbb_pcmcia_mem_map window %d bus %lx+%lx+%lx at card addr " 2622 "%lx\n", win, (u_long) busaddr, (u_long) * offsetp, (u_long) size, 2623 (u_long) card_addr)); 2624 2625 /* 2626 * include the offset in the size, and decrement size by one, since 2627 * the hw wants start/stop 2628 */ 2629 size += *offsetp - 1; 2630 2631 card_offset = (((long)card_addr) - ((long)busaddr)); 2632 2633 ph->mem[win].addr = busaddr; 2634 ph->mem[win].size = size; 2635 ph->mem[win].offset = card_offset; 2636 ph->mem[win].kind = kind; 2637 2638 pccbb_pcmcia_do_mem_map(ph, win); 2639 2640 return 0; 2641 } 2642 2643 /* 2644 * int pccbb_pcmcia_mem_unmap(pcmcia_chipset_handle_t pch, 2645 * int window) 2646 * 2647 * This function unmaps memory space which mapped by the function 2648 * pccbb_pcmcia_mem_map(). 2649 */ 2650 void 2651 pccbb_pcmcia_mem_unmap(pch, window) 2652 pcmcia_chipset_handle_t pch; 2653 int window; 2654 { 2655 struct pcic_handle *ph = (struct pcic_handle *)pch; 2656 int reg; 2657 2658 if (window >= PCIC_MEM_WINS) { 2659 panic("pccbb_pcmcia_mem_unmap: window out of range"); 2660 } 2661 2662 reg = Pcic_read(ph, PCIC_ADDRWIN_ENABLE); 2663 reg &= ~(1 << window); 2664 Pcic_write(ph, PCIC_ADDRWIN_ENABLE, reg); 2665 2666 ph->memalloc &= ~(1 << window); 2667 } 2668 2669 #if defined PCCBB_PCMCIA_POLL 2670 struct pccbb_poll_str { 2671 void *arg; 2672 int (*func) __P((void *)); 2673 int level; 2674 struct pcic_handle *ph; 2675 int count; 2676 int num; 2677 }; 2678 2679 static struct pccbb_poll_str pccbb_poll[10]; 2680 static int pccbb_poll_n = 0; 2681 static struct timeout pccbb_poll_timeout; 2682 2683 void pccbb_pcmcia_poll __P((void *arg)); 2684 2685 void 2686 pccbb_pcmcia_poll(arg) 2687 void *arg; 2688 { 2689 struct pccbb_poll_str *poll = arg; 2690 struct pcic_handle *ph = poll->ph; 2691 struct pccbb_softc *sc = ph->sc; 2692 int s; 2693 u_int32_t spsr; /* socket present-state reg */ 2694 2695 timeout_set(&pccbb_poll_timeout, pccbb_pcmcia_poll, arg); 2696 timeout_add(&pccbb_poll_timeout, hz * 2); 2697 switch (poll->level) { 2698 case IPL_NET: 2699 s = splnet(); 2700 break; 2701 case IPL_BIO: 2702 s = splbio(); 2703 break; 2704 case IPL_TTY: /* fallthrough */ 2705 default: 2706 s = spltty(); 2707 break; 2708 } 2709 2710 spsr = 2711 bus_space_read_4(sc->sc_base_memt, sc->sc_base_memh, 2712 CB_SOCKET_STAT); 2713 2714 #if defined PCCBB_PCMCIA_POLL_ONLY && defined LEVEL2 2715 if (!(spsr & 0x40)) /* CINT low */ 2716 #else 2717 if (1) 2718 #endif 2719 { 2720 if ((*poll->func) (poll->arg) > 0) { 2721 ++poll->count; 2722 /* printf("intr: reported from poller, 0x%x\n", spsr); */ 2723 #if defined LEVEL2 2724 } else { 2725 printf("intr: miss! 0x%x\n", spsr); 2726 #endif 2727 } 2728 } 2729 splx(s); 2730 } 2731 #endif /* defined CB_PCMCIA_POLL */ 2732 2733 /* 2734 * void *pccbb_pcmcia_intr_establish(pcmcia_chipset_handle_t pch, 2735 * struct pcmcia_function *pf, 2736 * int ipl, 2737 * int (*func)(void *), 2738 * void *arg); 2739 * 2740 * This function enables PC-Card interrupt. PCCBB uses PCI interrupt line. 2741 */ 2742 void * 2743 pccbb_pcmcia_intr_establish(pch, pf, ipl, func, arg, xname) 2744 pcmcia_chipset_handle_t pch; 2745 struct pcmcia_function *pf; 2746 int ipl; 2747 int (*func) __P((void *)); 2748 void *arg; 2749 char *xname; 2750 { 2751 struct pcic_handle *ph = (struct pcic_handle *)pch; 2752 struct pccbb_softc *sc = (struct pccbb_softc *)ph->ph_parent; 2753 2754 if (!(pf->cfe->flags & PCMCIA_CFE_IRQLEVEL)) { 2755 /* what should I do? */ 2756 if ((pf->cfe->flags & PCMCIA_CFE_IRQLEVEL)) { 2757 DPRINTF( 2758 ("%s does not provide edge nor pulse interrupt\n", 2759 sc->sc_dev.dv_xname)); 2760 return NULL; 2761 } 2762 /* 2763 * XXX Noooooo! The interrupt flag must set properly!! 2764 * dumb pcmcia driver!! 2765 */ 2766 } 2767 2768 return pccbb_intr_establish(sc, IST_LEVEL, ipl, func, arg); 2769 } 2770 2771 /* 2772 * void pccbb_pcmcia_intr_disestablish(pcmcia_chipset_handle_t pch, 2773 * void *ih) 2774 * 2775 * This function disables PC-Card interrupt. 2776 */ 2777 void 2778 pccbb_pcmcia_intr_disestablish(pch, ih) 2779 pcmcia_chipset_handle_t pch; 2780 void *ih; 2781 { 2782 struct pcic_handle *ph = (struct pcic_handle *)pch; 2783 struct pccbb_softc *sc = (struct pccbb_softc *)ph->ph_parent; 2784 2785 pccbb_intr_disestablish(sc, ih); 2786 } 2787 2788 #if rbus 2789 /* 2790 * int 2791 * pccbb_rbus_cb_space_alloc(cardbus_chipset_tag_t ct, rbus_tag_t rb, 2792 * bus_addr_t addr, bus_size_t size, 2793 * bus_addr_t mask, bus_size_t align, 2794 * int flags, bus_addr_t *addrp; 2795 * bus_space_handle_t *bshp) 2796 * 2797 * This function allocates a portion of memory or io space for 2798 * clients. This function is called from CardBus card drivers. 2799 */ 2800 int 2801 pccbb_rbus_cb_space_alloc(ct, rb, addr, size, mask, align, flags, addrp, bshp) 2802 cardbus_chipset_tag_t ct; 2803 rbus_tag_t rb; 2804 bus_addr_t addr; 2805 bus_size_t size; 2806 bus_addr_t mask; 2807 bus_size_t align; 2808 int flags; 2809 bus_addr_t *addrp; 2810 bus_space_handle_t *bshp; 2811 { 2812 struct pccbb_softc *sc = (struct pccbb_softc *)ct; 2813 2814 DPRINTF( 2815 ("pccbb_rbus_cb_space_alloc: adr %lx, size %lx, mask %lx, align %lx\n", 2816 addr, size, mask, align)); 2817 2818 if (align == 0) { 2819 align = size; 2820 } 2821 2822 if (rb->rb_bt == sc->sc_memt) { 2823 if (align < 16) { 2824 return 1; 2825 } 2826 } else if (rb->rb_bt == sc->sc_iot) { 2827 if (align < 4) { 2828 return 1; 2829 } 2830 /* XXX: hack for avoiding ISA image */ 2831 if (mask < 0x0100) { 2832 mask = 0x3ff; 2833 addr = 0x300; 2834 } 2835 2836 } else { 2837 DPRINTF( 2838 ("pccbb_rbus_cb_space_alloc: Bus space tag %x is NOT used.\n", 2839 rb->rb_bt)); 2840 return 1; 2841 /* XXX: panic here? */ 2842 } 2843 2844 if (rbus_space_alloc(rb, addr, size, mask, align, flags, addrp, bshp)) { 2845 printf("%s: <rbus> no bus space\n", sc->sc_dev.dv_xname); 2846 return 1; 2847 } 2848 2849 pccbb_open_win(sc, rb->rb_bt, *addrp, size, *bshp, 0); 2850 2851 return 0; 2852 } 2853 2854 /* 2855 * int 2856 * pccbb_rbus_cb_space_free(cardbus_chipset_tag_t *ct, rbus_tag_t rb, 2857 * bus_space_handle_t *bshp, bus_size_t size); 2858 * 2859 * This function is called from CardBus card drivers. 2860 */ 2861 int 2862 pccbb_rbus_cb_space_free(ct, rb, bsh, size) 2863 cardbus_chipset_tag_t ct; 2864 rbus_tag_t rb; 2865 bus_space_handle_t bsh; 2866 bus_size_t size; 2867 { 2868 struct pccbb_softc *sc = (struct pccbb_softc *)ct; 2869 bus_space_tag_t bt = rb->rb_bt; 2870 2871 pccbb_close_win(sc, bt, bsh, size); 2872 2873 if (bt == sc->sc_memt) { 2874 } else if (bt == sc->sc_iot) { 2875 } else { 2876 return 1; 2877 /* XXX: panic here? */ 2878 } 2879 2880 return rbus_space_free(rb, bsh, size, NULL); 2881 } 2882 #endif /* rbus */ 2883 2884 #if rbus 2885 2886 int 2887 pccbb_open_win(sc, bst, addr, size, bsh, flags) 2888 struct pccbb_softc *sc; 2889 bus_space_tag_t bst; 2890 bus_addr_t addr; 2891 bus_size_t size; 2892 bus_space_handle_t bsh; 2893 int flags; 2894 { 2895 struct pccbb_win_chain_head *head; 2896 bus_addr_t align; 2897 2898 head = &sc->sc_iowindow; 2899 align = 0x04; 2900 if (sc->sc_memt == bst) { 2901 head = &sc->sc_memwindow; 2902 align = 0x1000; 2903 DPRINTF(("using memory window, %x %x %x\n\n", 2904 sc->sc_iot, sc->sc_memt, bst)); 2905 } 2906 2907 if (pccbb_winlist_insert(head, addr, size, bsh, flags)) { 2908 printf("%s: pccbb_open_win: %s winlist insert failed\n", 2909 sc->sc_dev.dv_xname, 2910 (head == &sc->sc_memwindow) ? "mem" : "io"); 2911 } 2912 pccbb_winset(align, sc, bst); 2913 2914 return 0; 2915 } 2916 2917 int 2918 pccbb_close_win(sc, bst, bsh, size) 2919 struct pccbb_softc *sc; 2920 bus_space_tag_t bst; 2921 bus_space_handle_t bsh; 2922 bus_size_t size; 2923 { 2924 struct pccbb_win_chain_head *head; 2925 bus_addr_t align; 2926 2927 head = &sc->sc_iowindow; 2928 align = 0x04; 2929 if (sc->sc_memt == bst) { 2930 head = &sc->sc_memwindow; 2931 align = 0x1000; 2932 } 2933 2934 if (pccbb_winlist_delete(head, bsh, size)) { 2935 printf("%s: pccbb_close_win: %s winlist delete failed\n", 2936 sc->sc_dev.dv_xname, 2937 (head == &sc->sc_memwindow) ? "mem" : "io"); 2938 } 2939 pccbb_winset(align, sc, bst); 2940 2941 return 0; 2942 } 2943 2944 int 2945 pccbb_winlist_insert(head, start, size, bsh, flags) 2946 struct pccbb_win_chain_head *head; 2947 bus_addr_t start; 2948 bus_size_t size; 2949 bus_space_handle_t bsh; 2950 int flags; 2951 { 2952 struct pccbb_win_chain *chainp, *elem; 2953 2954 if ((elem = malloc(sizeof(struct pccbb_win_chain), M_DEVBUF, 2955 M_NOWAIT)) == NULL) 2956 return (1); /* fail */ 2957 2958 elem->wc_start = start; 2959 elem->wc_end = start + (size - 1); 2960 elem->wc_handle = bsh; 2961 elem->wc_flags = flags; 2962 2963 for (chainp = TAILQ_FIRST(head); chainp != NULL; 2964 chainp = TAILQ_NEXT(chainp, wc_list)) { 2965 if (chainp->wc_end < start) 2966 continue; 2967 TAILQ_INSERT_AFTER(head, chainp, elem, wc_list); 2968 return (0); 2969 } 2970 2971 TAILQ_INSERT_TAIL(head, elem, wc_list); 2972 return (0); 2973 } 2974 2975 int 2976 pccbb_winlist_delete(head, bsh, size) 2977 struct pccbb_win_chain_head *head; 2978 bus_space_handle_t bsh; 2979 bus_size_t size; 2980 { 2981 struct pccbb_win_chain *chainp; 2982 2983 for (chainp = TAILQ_FIRST(head); chainp != NULL; 2984 chainp = TAILQ_NEXT(chainp, wc_list)) { 2985 if (chainp->wc_handle != bsh) 2986 continue; 2987 if ((chainp->wc_end - chainp->wc_start) != (size - 1)) { 2988 printf("pccbb_winlist_delete: window 0x%lx size " 2989 "inconsistent: 0x%lx, 0x%lx\n", 2990 chainp->wc_start, 2991 chainp->wc_end - chainp->wc_start, 2992 size - 1); 2993 return 1; 2994 } 2995 2996 TAILQ_REMOVE(head, chainp, wc_list); 2997 free(chainp, M_DEVBUF); 2998 2999 return 0; 3000 } 3001 3002 return 1; /* fail: no candidate to remove */ 3003 } 3004 3005 void 3006 pccbb_winset(align, sc, bst) 3007 bus_addr_t align; 3008 struct pccbb_softc *sc; 3009 bus_space_tag_t bst; 3010 { 3011 pci_chipset_tag_t pc; 3012 pcitag_t tag; 3013 bus_addr_t mask = ~(align - 1); 3014 struct { 3015 cardbusreg_t win_start; 3016 cardbusreg_t win_limit; 3017 int win_flags; 3018 } win[2]; 3019 struct pccbb_win_chain *chainp; 3020 int offs; 3021 3022 win[0].win_start = win[1].win_start = 0xffffffff; 3023 win[0].win_limit = win[1].win_limit = 0; 3024 win[0].win_flags = win[1].win_flags = 0; 3025 3026 chainp = TAILQ_FIRST(&sc->sc_iowindow); 3027 offs = 0x2c; 3028 if (sc->sc_memt == bst) { 3029 chainp = TAILQ_FIRST(&sc->sc_memwindow); 3030 offs = 0x1c; 3031 } 3032 3033 if (chainp != NULL) { 3034 win[0].win_start = chainp->wc_start & mask; 3035 win[0].win_limit = chainp->wc_end & mask; 3036 win[0].win_flags = chainp->wc_flags; 3037 chainp = TAILQ_NEXT(chainp, wc_list); 3038 } 3039 3040 for (; chainp != NULL; chainp = TAILQ_NEXT(chainp, wc_list)) { 3041 if (win[1].win_start == 0xffffffff) { 3042 /* window 1 is not used */ 3043 if ((win[0].win_flags == chainp->wc_flags) && 3044 (win[0].win_limit + align >= 3045 (chainp->wc_start & mask))) { 3046 /* concatenate */ 3047 win[0].win_limit = chainp->wc_end & mask; 3048 } else { 3049 /* make new window */ 3050 win[1].win_start = chainp->wc_start & mask; 3051 win[1].win_limit = chainp->wc_end & mask; 3052 win[1].win_flags = chainp->wc_flags; 3053 } 3054 continue; 3055 } 3056 3057 /* Both windows are engaged. */ 3058 if (win[0].win_flags == win[1].win_flags) { 3059 /* same flags */ 3060 if (win[0].win_flags == chainp->wc_flags) { 3061 if (win[1].win_start - (win[0].win_limit + 3062 align) < 3063 (chainp->wc_start & mask) - 3064 ((chainp->wc_end & mask) + align)) { 3065 /* 3066 * merge window 0 and 1, and set win1 3067 * to chainp 3068 */ 3069 win[0].win_limit = win[1].win_limit; 3070 win[1].win_start = 3071 chainp->wc_start & mask; 3072 win[1].win_limit = 3073 chainp->wc_end & mask; 3074 } else { 3075 win[1].win_limit = 3076 chainp->wc_end & mask; 3077 } 3078 } else { 3079 /* different flags */ 3080 3081 /* concatenate win0 and win1 */ 3082 win[0].win_limit = win[1].win_limit; 3083 /* allocate win[1] to new space */ 3084 win[1].win_start = chainp->wc_start & mask; 3085 win[1].win_limit = chainp->wc_end & mask; 3086 win[1].win_flags = chainp->wc_flags; 3087 } 3088 } else { 3089 /* the flags of win[0] and win[1] is different */ 3090 if (win[0].win_flags == chainp->wc_flags) { 3091 win[0].win_limit = chainp->wc_end & mask; 3092 /* 3093 * XXX this creates overlapping windows, so 3094 * what should the poor bridge do if one is 3095 * cachable, and the other is not? 3096 */ 3097 printf("%s: overlapping windows\n", 3098 sc->sc_dev.dv_xname); 3099 } else { 3100 win[1].win_limit = chainp->wc_end & mask; 3101 } 3102 } 3103 } 3104 3105 pc = sc->sc_pc; 3106 tag = sc->sc_tag; 3107 pci_conf_write(pc, tag, offs, win[0].win_start); 3108 pci_conf_write(pc, tag, offs + 4, win[0].win_limit); 3109 pci_conf_write(pc, tag, offs + 8, win[1].win_start); 3110 pci_conf_write(pc, tag, offs + 12, win[1].win_limit); 3111 DPRINTF(("--pccbb_winset: win0 [%x, %lx), win1 [%x, %lx)\n", 3112 pci_conf_read(pc, tag, offs), 3113 pci_conf_read(pc, tag, offs + 4) + align, 3114 pci_conf_read(pc, tag, offs + 8), 3115 pci_conf_read(pc, tag, offs + 12) + align)); 3116 3117 if (bst == sc->sc_memt) { 3118 pcireg_t bcr = pci_conf_read(pc, tag, PCI_BCR_INTR); 3119 3120 bcr &= ~(CB_BCR_PREFETCH_MEMWIN0 | CB_BCR_PREFETCH_MEMWIN1); 3121 if (win[0].win_flags & PCCBB_MEM_CACHABLE) 3122 bcr |= CB_BCR_PREFETCH_MEMWIN0; 3123 if (win[1].win_flags & PCCBB_MEM_CACHABLE) 3124 bcr |= CB_BCR_PREFETCH_MEMWIN1; 3125 pci_conf_write(pc, tag, PCI_BCR_INTR, bcr); 3126 } 3127 } 3128 3129 #endif /* rbus */ 3130 3131 void 3132 pccbb_powerhook(why, arg) 3133 int why; 3134 void *arg; 3135 { 3136 struct pccbb_softc *sc = arg; 3137 u_int32_t reg; 3138 bus_space_tag_t base_memt = sc->sc_base_memt; /* socket regs memory */ 3139 bus_space_handle_t base_memh = sc->sc_base_memh; 3140 3141 DPRINTF(("%s: power: why %d\n", sc->sc_dev.dv_xname, why)); 3142 3143 if (why == PWR_SUSPEND || why == PWR_STANDBY) { 3144 DPRINTF(("%s: power: why %d stopping intr\n", 3145 sc->sc_dev.dv_xname, why)); 3146 if (sc->sc_pil_intr_enable) { 3147 (void)pccbbintr_function(sc); 3148 } 3149 sc->sc_pil_intr_enable = 0; 3150 3151 /* ToDo: deactivate or suspend child devices */ 3152 3153 } 3154 3155 if (why == PWR_RESUME) { 3156 if (pci_conf_read (sc->sc_pc, sc->sc_tag, PCI_SOCKBASE) == 0) 3157 /* BIOS did not recover this register */ 3158 pci_conf_write (sc->sc_pc, sc->sc_tag, 3159 PCI_SOCKBASE, sc->sc_sockbase); 3160 if (pci_conf_read (sc->sc_pc, sc->sc_tag, PCI_BUSNUM) == 0) 3161 /* BIOS did not recover this register */ 3162 pci_conf_write (sc->sc_pc, sc->sc_tag, 3163 PCI_BUSNUM, sc->sc_busnum); 3164 /* CSC Interrupt: Card detect interrupt on */ 3165 reg = bus_space_read_4(base_memt, base_memh, CB_SOCKET_MASK); 3166 /* Card detect intr is turned on. */ 3167 reg |= CB_SOCKET_MASK_CD; 3168 bus_space_write_4(base_memt, base_memh, CB_SOCKET_MASK, reg); 3169 /* reset interrupt */ 3170 reg = bus_space_read_4(base_memt, base_memh, CB_SOCKET_EVENT); 3171 bus_space_write_4(base_memt, base_memh, CB_SOCKET_EVENT, reg); 3172 3173 /* 3174 * check for card insertion or removal during suspend period. 3175 * XXX: the code can't cope with card swap (remove then 3176 * insert). how can we detect such situation? 3177 */ 3178 (void)pccbbintr(sc); 3179 3180 sc->sc_pil_intr_enable = 1; 3181 DPRINTF(("%s: power: RESUME enabling intr\n", 3182 sc->sc_dev.dv_xname)); 3183 3184 /* ToDo: activate or wakeup child devices */ 3185 } 3186 } 3187