1 /* $OpenBSD: mpii.c,v 1.113 2017/12/12 11:18:32 mpi Exp $ */ 2 /* 3 * Copyright (c) 2010, 2012 Mike Belopuhov 4 * Copyright (c) 2009 James Giannoules 5 * Copyright (c) 2005 - 2010 David Gwynne <dlg@openbsd.org> 6 * Copyright (c) 2005 - 2010 Marco Peereboom <marco@openbsd.org> 7 * 8 * Permission to use, copy, modify, and distribute this software for any 9 * purpose with or without fee is hereby granted, provided that the above 10 * copyright notice and this permission notice appear in all copies. 11 * 12 * THE SOFTWARE IS PROVIDED "AS IS" AND THE AUTHOR DISCLAIMS ALL WARRANTIES 13 * WITH REGARD TO THIS SOFTWARE INCLUDING ALL IMPLIED WARRANTIES OF 14 * MERCHANTABILITY AND FITNESS. IN NO EVENT SHALL THE AUTHOR BE LIABLE FOR 15 * ANY SPECIAL, DIRECT, INDIRECT, OR CONSEQUENTIAL DAMAGES OR ANY DAMAGES 16 * WHATSOEVER RESULTING FROM LOSS OF USE, DATA OR PROFITS, WHETHER IN AN 17 * ACTION OF CONTRACT, NEGLIGENCE OR OTHER TORTIOUS ACTION, ARISING OUT OF 18 * OR IN CONNECTION WITH THE USE OR PERFORMANCE OF THIS SOFTWARE. 19 */ 20 21 #include "bio.h" 22 23 #include <sys/param.h> 24 #include <sys/systm.h> 25 #include <sys/device.h> 26 #include <sys/ioctl.h> 27 #include <sys/malloc.h> 28 #include <sys/kernel.h> 29 #include <sys/rwlock.h> 30 #include <sys/sensors.h> 31 #include <sys/dkio.h> 32 #include <sys/tree.h> 33 #include <sys/task.h> 34 35 #include <machine/bus.h> 36 37 #include <dev/pci/pcireg.h> 38 #include <dev/pci/pcivar.h> 39 #include <dev/pci/pcidevs.h> 40 41 #include <scsi/scsi_all.h> 42 #include <scsi/scsiconf.h> 43 44 #include <dev/biovar.h> 45 46 #include <dev/pci/mpiireg.h> 47 48 /* #define MPII_DEBUG */ 49 #ifdef MPII_DEBUG 50 #define DPRINTF(x...) do { if (mpii_debug) printf(x); } while(0) 51 #define DNPRINTF(n,x...) do { if (mpii_debug & (n)) printf(x); } while(0) 52 #define MPII_D_CMD (0x0001) 53 #define MPII_D_INTR (0x0002) 54 #define MPII_D_MISC (0x0004) 55 #define MPII_D_DMA (0x0008) 56 #define MPII_D_IOCTL (0x0010) 57 #define MPII_D_RW (0x0020) 58 #define MPII_D_MEM (0x0040) 59 #define MPII_D_CCB (0x0080) 60 #define MPII_D_PPR (0x0100) 61 #define MPII_D_RAID (0x0200) 62 #define MPII_D_EVT (0x0400) 63 #define MPII_D_CFG (0x0800) 64 #define MPII_D_MAP (0x1000) 65 66 u_int32_t mpii_debug = 0 67 | MPII_D_CMD 68 | MPII_D_INTR 69 | MPII_D_MISC 70 | MPII_D_DMA 71 | MPII_D_IOCTL 72 | MPII_D_RW 73 | MPII_D_MEM 74 | MPII_D_CCB 75 | MPII_D_PPR 76 | MPII_D_RAID 77 | MPII_D_EVT 78 | MPII_D_CFG 79 | MPII_D_MAP 80 ; 81 #else 82 #define DPRINTF(x...) 83 #define DNPRINTF(n,x...) 84 #endif 85 86 #define MPII_REQUEST_SIZE (512) 87 #define MPII_REQUEST_CREDIT (128) 88 89 struct mpii_dmamem { 90 bus_dmamap_t mdm_map; 91 bus_dma_segment_t mdm_seg; 92 size_t mdm_size; 93 caddr_t mdm_kva; 94 }; 95 #define MPII_DMA_MAP(_mdm) ((_mdm)->mdm_map) 96 #define MPII_DMA_DVA(_mdm) ((u_int64_t)(_mdm)->mdm_map->dm_segs[0].ds_addr) 97 #define MPII_DMA_KVA(_mdm) ((void *)(_mdm)->mdm_kva) 98 99 struct mpii_softc; 100 101 struct mpii_rcb { 102 SIMPLEQ_ENTRY(mpii_rcb) rcb_link; 103 void *rcb_reply; 104 u_int32_t rcb_reply_dva; 105 }; 106 107 SIMPLEQ_HEAD(mpii_rcb_list, mpii_rcb); 108 109 struct mpii_device { 110 int flags; 111 #define MPII_DF_ATTACH (0x0001) 112 #define MPII_DF_DETACH (0x0002) 113 #define MPII_DF_HIDDEN (0x0004) 114 #define MPII_DF_UNUSED (0x0008) 115 #define MPII_DF_VOLUME (0x0010) 116 #define MPII_DF_VOLUME_DISK (0x0020) 117 #define MPII_DF_HOT_SPARE (0x0040) 118 short slot; 119 short percent; 120 u_int16_t dev_handle; 121 u_int16_t enclosure; 122 u_int16_t expander; 123 u_int8_t phy_num; 124 u_int8_t physical_port; 125 }; 126 127 struct mpii_ccb { 128 struct mpii_softc *ccb_sc; 129 130 void * ccb_cookie; 131 bus_dmamap_t ccb_dmamap; 132 133 bus_addr_t ccb_offset; 134 void *ccb_cmd; 135 bus_addr_t ccb_cmd_dva; 136 u_int16_t ccb_dev_handle; 137 u_int16_t ccb_smid; 138 139 volatile enum { 140 MPII_CCB_FREE, 141 MPII_CCB_READY, 142 MPII_CCB_QUEUED, 143 MPII_CCB_TIMEOUT 144 } ccb_state; 145 146 void (*ccb_done)(struct mpii_ccb *); 147 struct mpii_rcb *ccb_rcb; 148 149 SIMPLEQ_ENTRY(mpii_ccb) ccb_link; 150 }; 151 152 SIMPLEQ_HEAD(mpii_ccb_list, mpii_ccb); 153 154 struct mpii_softc { 155 struct device sc_dev; 156 157 pci_chipset_tag_t sc_pc; 158 pcitag_t sc_tag; 159 160 void *sc_ih; 161 162 struct scsi_link sc_link; 163 164 int sc_flags; 165 #define MPII_F_RAID (1<<1) 166 #define MPII_F_SAS3 (1<<2) 167 #define MPII_F_CONFIG_PENDING (1<<3) 168 169 struct scsibus_softc *sc_scsibus; 170 171 struct mpii_device **sc_devs; 172 173 bus_space_tag_t sc_iot; 174 bus_space_handle_t sc_ioh; 175 bus_size_t sc_ios; 176 bus_dma_tag_t sc_dmat; 177 178 struct mutex sc_req_mtx; 179 struct mutex sc_rep_mtx; 180 181 ushort sc_reply_size; 182 ushort sc_request_size; 183 184 ushort sc_max_cmds; 185 ushort sc_num_reply_frames; 186 u_int sc_reply_free_qdepth; 187 u_int sc_reply_post_qdepth; 188 189 ushort sc_chain_sge; 190 ushort sc_max_sgl; 191 192 u_int8_t sc_ioc_event_replay; 193 194 u_int8_t sc_porttype; 195 u_int8_t sc_max_volumes; 196 u_int16_t sc_max_devices; 197 u_int16_t sc_vd_count; 198 u_int16_t sc_vd_id_low; 199 u_int16_t sc_pd_id_start; 200 int sc_ioc_number; 201 u_int8_t sc_vf_id; 202 203 struct mpii_ccb *sc_ccbs; 204 struct mpii_ccb_list sc_ccb_free; 205 struct mutex sc_ccb_free_mtx; 206 207 struct mutex sc_ccb_mtx; 208 /* 209 * this protects the ccb state and list entry 210 * between mpii_scsi_cmd and scsidone. 211 */ 212 213 struct mpii_ccb_list sc_ccb_tmos; 214 struct scsi_iohandler sc_ccb_tmo_handler; 215 216 struct scsi_iopool sc_iopool; 217 218 struct mpii_dmamem *sc_requests; 219 220 struct mpii_dmamem *sc_replies; 221 struct mpii_rcb *sc_rcbs; 222 223 struct mpii_dmamem *sc_reply_postq; 224 struct mpii_reply_descr *sc_reply_postq_kva; 225 u_int sc_reply_post_host_index; 226 227 struct mpii_dmamem *sc_reply_freeq; 228 u_int sc_reply_free_host_index; 229 230 struct mpii_rcb_list sc_evt_sas_queue; 231 struct mutex sc_evt_sas_mtx; 232 struct task sc_evt_sas_task; 233 234 struct mpii_rcb_list sc_evt_ack_queue; 235 struct mutex sc_evt_ack_mtx; 236 struct scsi_iohandler sc_evt_ack_handler; 237 238 /* scsi ioctl from sd device */ 239 int (*sc_ioctl)(struct device *, u_long, caddr_t); 240 241 int sc_nsensors; 242 struct ksensor *sc_sensors; 243 struct ksensordev sc_sensordev; 244 }; 245 246 int mpii_match(struct device *, void *, void *); 247 void mpii_attach(struct device *, struct device *, void *); 248 int mpii_detach(struct device *, int); 249 250 int mpii_intr(void *); 251 252 struct cfattach mpii_ca = { 253 sizeof(struct mpii_softc), 254 mpii_match, 255 mpii_attach, 256 mpii_detach 257 }; 258 259 struct cfdriver mpii_cd = { 260 NULL, 261 "mpii", 262 DV_DULL 263 }; 264 265 void mpii_scsi_cmd(struct scsi_xfer *); 266 void mpii_scsi_cmd_done(struct mpii_ccb *); 267 int mpii_scsi_probe(struct scsi_link *); 268 int mpii_scsi_ioctl(struct scsi_link *, u_long, caddr_t, int); 269 270 struct scsi_adapter mpii_switch = { 271 mpii_scsi_cmd, 272 scsi_minphys, 273 mpii_scsi_probe, 274 NULL, 275 mpii_scsi_ioctl 276 }; 277 278 struct mpii_dmamem * 279 mpii_dmamem_alloc(struct mpii_softc *, size_t); 280 void mpii_dmamem_free(struct mpii_softc *, 281 struct mpii_dmamem *); 282 int mpii_alloc_ccbs(struct mpii_softc *); 283 void * mpii_get_ccb(void *); 284 void mpii_put_ccb(void *, void *); 285 int mpii_alloc_replies(struct mpii_softc *); 286 int mpii_alloc_queues(struct mpii_softc *); 287 void mpii_push_reply(struct mpii_softc *, struct mpii_rcb *); 288 void mpii_push_replies(struct mpii_softc *); 289 290 void mpii_scsi_cmd_tmo(void *); 291 void mpii_scsi_cmd_tmo_handler(void *, void *); 292 void mpii_scsi_cmd_tmo_done(struct mpii_ccb *); 293 294 int mpii_insert_dev(struct mpii_softc *, struct mpii_device *); 295 int mpii_remove_dev(struct mpii_softc *, struct mpii_device *); 296 struct mpii_device * 297 mpii_find_dev(struct mpii_softc *, u_int16_t); 298 299 void mpii_start(struct mpii_softc *, struct mpii_ccb *); 300 int mpii_poll(struct mpii_softc *, struct mpii_ccb *); 301 void mpii_poll_done(struct mpii_ccb *); 302 struct mpii_rcb * 303 mpii_reply(struct mpii_softc *, struct mpii_reply_descr *); 304 305 void mpii_wait(struct mpii_softc *, struct mpii_ccb *); 306 void mpii_wait_done(struct mpii_ccb *); 307 308 void mpii_init_queues(struct mpii_softc *); 309 310 int mpii_load_xs(struct mpii_ccb *); 311 int mpii_load_xs_sas3(struct mpii_ccb *); 312 313 u_int32_t mpii_read(struct mpii_softc *, bus_size_t); 314 void mpii_write(struct mpii_softc *, bus_size_t, u_int32_t); 315 int mpii_wait_eq(struct mpii_softc *, bus_size_t, u_int32_t, 316 u_int32_t); 317 int mpii_wait_ne(struct mpii_softc *, bus_size_t, u_int32_t, 318 u_int32_t); 319 320 int mpii_init(struct mpii_softc *); 321 int mpii_reset_soft(struct mpii_softc *); 322 int mpii_reset_hard(struct mpii_softc *); 323 324 int mpii_handshake_send(struct mpii_softc *, void *, size_t); 325 int mpii_handshake_recv_dword(struct mpii_softc *, 326 u_int32_t *); 327 int mpii_handshake_recv(struct mpii_softc *, void *, size_t); 328 329 void mpii_empty_done(struct mpii_ccb *); 330 331 int mpii_iocinit(struct mpii_softc *); 332 int mpii_iocfacts(struct mpii_softc *); 333 int mpii_portfacts(struct mpii_softc *); 334 int mpii_portenable(struct mpii_softc *); 335 int mpii_cfg_coalescing(struct mpii_softc *); 336 int mpii_board_info(struct mpii_softc *); 337 int mpii_target_map(struct mpii_softc *); 338 339 int mpii_eventnotify(struct mpii_softc *); 340 void mpii_eventnotify_done(struct mpii_ccb *); 341 void mpii_eventack(void *, void *); 342 void mpii_eventack_done(struct mpii_ccb *); 343 void mpii_event_process(struct mpii_softc *, struct mpii_rcb *); 344 void mpii_event_done(struct mpii_softc *, struct mpii_rcb *); 345 void mpii_event_sas(void *); 346 void mpii_event_raid(struct mpii_softc *, 347 struct mpii_msg_event_reply *); 348 void mpii_event_discovery(struct mpii_softc *, 349 struct mpii_msg_event_reply *); 350 351 void mpii_sas_remove_device(struct mpii_softc *, u_int16_t); 352 353 int mpii_req_cfg_header(struct mpii_softc *, u_int8_t, 354 u_int8_t, u_int32_t, int, void *); 355 int mpii_req_cfg_page(struct mpii_softc *, u_int32_t, int, 356 void *, int, void *, size_t); 357 358 int mpii_ioctl_cache(struct scsi_link *, u_long, struct dk_cache *); 359 360 #if NBIO > 0 361 int mpii_ioctl(struct device *, u_long, caddr_t); 362 int mpii_ioctl_inq(struct mpii_softc *, struct bioc_inq *); 363 int mpii_ioctl_vol(struct mpii_softc *, struct bioc_vol *); 364 int mpii_ioctl_disk(struct mpii_softc *, struct bioc_disk *); 365 int mpii_bio_hs(struct mpii_softc *, struct bioc_disk *, int, 366 int, int *); 367 int mpii_bio_disk(struct mpii_softc *, struct bioc_disk *, 368 u_int8_t); 369 struct mpii_device * 370 mpii_find_vol(struct mpii_softc *, int); 371 #ifndef SMALL_KERNEL 372 int mpii_bio_volstate(struct mpii_softc *, struct bioc_vol *); 373 int mpii_create_sensors(struct mpii_softc *); 374 void mpii_refresh_sensors(void *); 375 #endif /* SMALL_KERNEL */ 376 #endif /* NBIO > 0 */ 377 378 #define DEVNAME(s) ((s)->sc_dev.dv_xname) 379 380 #define dwordsof(s) (sizeof(s) / sizeof(u_int32_t)) 381 382 #define mpii_read_db(s) mpii_read((s), MPII_DOORBELL) 383 #define mpii_write_db(s, v) mpii_write((s), MPII_DOORBELL, (v)) 384 #define mpii_read_intr(s) mpii_read((s), MPII_INTR_STATUS) 385 #define mpii_write_intr(s, v) mpii_write((s), MPII_INTR_STATUS, (v)) 386 #define mpii_reply_waiting(s) ((mpii_read_intr((s)) & MPII_INTR_STATUS_REPLY)\ 387 == MPII_INTR_STATUS_REPLY) 388 389 #define mpii_write_reply_free(s, v) \ 390 bus_space_write_4((s)->sc_iot, (s)->sc_ioh, \ 391 MPII_REPLY_FREE_HOST_INDEX, (v)) 392 #define mpii_write_reply_post(s, v) \ 393 bus_space_write_4((s)->sc_iot, (s)->sc_ioh, \ 394 MPII_REPLY_POST_HOST_INDEX, (v)) 395 396 #define mpii_wait_db_int(s) mpii_wait_ne((s), MPII_INTR_STATUS, \ 397 MPII_INTR_STATUS_IOC2SYSDB, 0) 398 #define mpii_wait_db_ack(s) mpii_wait_eq((s), MPII_INTR_STATUS, \ 399 MPII_INTR_STATUS_SYS2IOCDB, 0) 400 401 static inline void 402 mpii_dvatosge(struct mpii_sge *sge, u_int64_t dva) 403 { 404 htolem32(&sge->sg_addr_lo, dva); 405 htolem32(&sge->sg_addr_hi, dva >> 32); 406 } 407 408 #define MPII_PG_EXTENDED (1<<0) 409 #define MPII_PG_POLL (1<<1) 410 #define MPII_PG_FMT "\020" "\002POLL" "\001EXTENDED" 411 412 static const struct pci_matchid mpii_devices[] = { 413 { PCI_VENDOR_SYMBIOS, PCI_PRODUCT_SYMBIOS_SAS2004 }, 414 { PCI_VENDOR_SYMBIOS, PCI_PRODUCT_SYMBIOS_SAS2008 }, 415 { PCI_VENDOR_SYMBIOS, PCI_PRODUCT_SYMBIOS_SAS2108_3 }, 416 { PCI_VENDOR_SYMBIOS, PCI_PRODUCT_SYMBIOS_SAS2108_4 }, 417 { PCI_VENDOR_SYMBIOS, PCI_PRODUCT_SYMBIOS_SAS2108_5 }, 418 { PCI_VENDOR_SYMBIOS, PCI_PRODUCT_SYMBIOS_SAS2116_1 }, 419 { PCI_VENDOR_SYMBIOS, PCI_PRODUCT_SYMBIOS_SAS2116_2 }, 420 { PCI_VENDOR_SYMBIOS, PCI_PRODUCT_SYMBIOS_SAS2208_1 }, 421 { PCI_VENDOR_SYMBIOS, PCI_PRODUCT_SYMBIOS_SAS2208_2 }, 422 { PCI_VENDOR_SYMBIOS, PCI_PRODUCT_SYMBIOS_SAS2208_3 }, 423 { PCI_VENDOR_SYMBIOS, PCI_PRODUCT_SYMBIOS_SAS2208_4 }, 424 { PCI_VENDOR_SYMBIOS, PCI_PRODUCT_SYMBIOS_SAS2208_5 }, 425 { PCI_VENDOR_SYMBIOS, PCI_PRODUCT_SYMBIOS_SAS2208_6 }, 426 { PCI_VENDOR_SYMBIOS, PCI_PRODUCT_SYMBIOS_SAS2308_1 }, 427 { PCI_VENDOR_SYMBIOS, PCI_PRODUCT_SYMBIOS_SAS2308_2 }, 428 { PCI_VENDOR_SYMBIOS, PCI_PRODUCT_SYMBIOS_SAS2308_3 }, 429 { PCI_VENDOR_SYMBIOS, PCI_PRODUCT_SYMBIOS_SAS3004 }, 430 { PCI_VENDOR_SYMBIOS, PCI_PRODUCT_SYMBIOS_SAS3008 }, 431 { PCI_VENDOR_SYMBIOS, PCI_PRODUCT_SYMBIOS_SAS3108_1 }, 432 { PCI_VENDOR_SYMBIOS, PCI_PRODUCT_SYMBIOS_SAS3108_2 }, 433 { PCI_VENDOR_SYMBIOS, PCI_PRODUCT_SYMBIOS_SAS3108_3 }, 434 { PCI_VENDOR_SYMBIOS, PCI_PRODUCT_SYMBIOS_SAS3108_4 } 435 }; 436 437 int 438 mpii_match(struct device *parent, void *match, void *aux) 439 { 440 return (pci_matchbyid(aux, mpii_devices, nitems(mpii_devices))); 441 } 442 443 void 444 mpii_attach(struct device *parent, struct device *self, void *aux) 445 { 446 struct mpii_softc *sc = (struct mpii_softc *)self; 447 struct pci_attach_args *pa = aux; 448 pcireg_t memtype; 449 int r; 450 pci_intr_handle_t ih; 451 struct scsibus_attach_args saa; 452 struct mpii_ccb *ccb; 453 454 sc->sc_pc = pa->pa_pc; 455 sc->sc_tag = pa->pa_tag; 456 sc->sc_dmat = pa->pa_dmat; 457 458 mtx_init(&sc->sc_req_mtx, IPL_BIO); 459 mtx_init(&sc->sc_rep_mtx, IPL_BIO); 460 461 /* find the appropriate memory base */ 462 for (r = PCI_MAPREG_START; r < PCI_MAPREG_END; r += sizeof(memtype)) { 463 memtype = pci_mapreg_type(sc->sc_pc, sc->sc_tag, r); 464 if ((memtype & PCI_MAPREG_TYPE_MASK) == PCI_MAPREG_TYPE_MEM) 465 break; 466 } 467 if (r >= PCI_MAPREG_END) { 468 printf(": unable to locate system interface registers\n"); 469 return; 470 } 471 472 if (pci_mapreg_map(pa, r, memtype, 0, &sc->sc_iot, &sc->sc_ioh, 473 NULL, &sc->sc_ios, 0xFF) != 0) { 474 printf(": unable to map system interface registers\n"); 475 return; 476 } 477 478 /* disable the expansion rom */ 479 pci_conf_write(sc->sc_pc, sc->sc_tag, PCI_ROM_REG, 480 pci_conf_read(sc->sc_pc, sc->sc_tag, PCI_ROM_REG) & 481 ~PCI_ROM_ENABLE); 482 483 /* disable interrupts */ 484 mpii_write(sc, MPII_INTR_MASK, 485 MPII_INTR_MASK_RESET | MPII_INTR_MASK_REPLY | 486 MPII_INTR_MASK_DOORBELL); 487 488 /* hook up the interrupt */ 489 if (pci_intr_map_msi(pa, &ih) != 0 && pci_intr_map(pa, &ih) != 0) { 490 printf(": unable to map interrupt\n"); 491 goto unmap; 492 } 493 printf(": %s\n", pci_intr_string(sc->sc_pc, ih)); 494 495 if (mpii_init(sc) != 0) { 496 printf("%s: unable to initialize ioc\n", DEVNAME(sc)); 497 goto unmap; 498 } 499 500 if (mpii_iocfacts(sc) != 0) { 501 printf("%s: unable to get iocfacts\n", DEVNAME(sc)); 502 goto unmap; 503 } 504 505 if (mpii_alloc_ccbs(sc) != 0) { 506 /* error already printed */ 507 goto unmap; 508 } 509 510 if (mpii_alloc_replies(sc) != 0) { 511 printf("%s: unable to allocated reply space\n", DEVNAME(sc)); 512 goto free_ccbs; 513 } 514 515 if (mpii_alloc_queues(sc) != 0) { 516 printf("%s: unable to allocate reply queues\n", DEVNAME(sc)); 517 goto free_replies; 518 } 519 520 if (mpii_iocinit(sc) != 0) { 521 printf("%s: unable to send iocinit\n", DEVNAME(sc)); 522 goto free_queues; 523 } 524 525 if (mpii_wait_eq(sc, MPII_DOORBELL, MPII_DOORBELL_STATE, 526 MPII_DOORBELL_STATE_OPER) != 0) { 527 printf("%s: state: 0x%08x\n", DEVNAME(sc), 528 mpii_read_db(sc) & MPII_DOORBELL_STATE); 529 printf("%s: operational state timeout\n", DEVNAME(sc)); 530 goto free_queues; 531 } 532 533 mpii_push_replies(sc); 534 mpii_init_queues(sc); 535 536 if (mpii_board_info(sc) != 0) { 537 printf("%s: unable to get manufacturing page 0\n", 538 DEVNAME(sc)); 539 goto free_queues; 540 } 541 542 if (mpii_portfacts(sc) != 0) { 543 printf("%s: unable to get portfacts\n", DEVNAME(sc)); 544 goto free_queues; 545 } 546 547 if (mpii_target_map(sc) != 0) { 548 printf("%s: unable to setup target mappings\n", DEVNAME(sc)); 549 goto free_queues; 550 } 551 552 if (mpii_cfg_coalescing(sc) != 0) { 553 printf("%s: unable to configure coalescing\n", DEVNAME(sc)); 554 goto free_queues; 555 } 556 557 /* XXX bail on unsupported porttype? */ 558 if ((sc->sc_porttype == MPII_PORTFACTS_PORTTYPE_SAS_PHYSICAL) || 559 (sc->sc_porttype == MPII_PORTFACTS_PORTTYPE_SAS_VIRTUAL)) { 560 if (mpii_eventnotify(sc) != 0) { 561 printf("%s: unable to enable events\n", DEVNAME(sc)); 562 goto free_queues; 563 } 564 } 565 566 sc->sc_devs = mallocarray(sc->sc_max_devices, 567 sizeof(struct mpii_device *), M_DEVBUF, M_NOWAIT | M_ZERO); 568 if (sc->sc_devs == NULL) { 569 printf("%s: unable to allocate memory for mpii_device\n", 570 DEVNAME(sc)); 571 goto free_queues; 572 } 573 574 if (mpii_portenable(sc) != 0) { 575 printf("%s: unable to enable port\n", DEVNAME(sc)); 576 goto free_devs; 577 } 578 579 /* we should be good to go now, attach scsibus */ 580 sc->sc_link.adapter = &mpii_switch; 581 sc->sc_link.adapter_softc = sc; 582 sc->sc_link.adapter_target = -1; 583 sc->sc_link.adapter_buswidth = sc->sc_max_devices; 584 sc->sc_link.luns = 1; 585 sc->sc_link.openings = sc->sc_max_cmds - 1; 586 sc->sc_link.pool = &sc->sc_iopool; 587 588 memset(&saa, 0, sizeof(saa)); 589 saa.saa_sc_link = &sc->sc_link; 590 591 sc->sc_ih = pci_intr_establish(sc->sc_pc, ih, IPL_BIO, 592 mpii_intr, sc, sc->sc_dev.dv_xname); 593 if (sc->sc_ih == NULL) 594 goto free_devs; 595 596 /* force autoconf to wait for the first sas discovery to complete */ 597 SET(sc->sc_flags, MPII_F_CONFIG_PENDING); 598 config_pending_incr(); 599 600 /* config_found() returns the scsibus attached to us */ 601 sc->sc_scsibus = (struct scsibus_softc *) config_found(&sc->sc_dev, 602 &saa, scsiprint); 603 604 /* enable interrupts */ 605 mpii_write(sc, MPII_INTR_MASK, MPII_INTR_MASK_DOORBELL 606 | MPII_INTR_MASK_RESET); 607 608 #if NBIO > 0 609 if (ISSET(sc->sc_flags, MPII_F_RAID)) { 610 if (bio_register(&sc->sc_dev, mpii_ioctl) != 0) 611 panic("%s: controller registration failed", 612 DEVNAME(sc)); 613 else 614 sc->sc_ioctl = mpii_ioctl; 615 616 #ifndef SMALL_KERNEL 617 if (mpii_create_sensors(sc) != 0) 618 printf("%s: unable to create sensors\n", DEVNAME(sc)); 619 #endif 620 } 621 #endif 622 623 return; 624 625 free_devs: 626 free(sc->sc_devs, M_DEVBUF, 0); 627 sc->sc_devs = NULL; 628 629 free_queues: 630 bus_dmamap_sync(sc->sc_dmat, MPII_DMA_MAP(sc->sc_reply_freeq), 631 0, sc->sc_reply_free_qdepth * 4, BUS_DMASYNC_POSTREAD); 632 mpii_dmamem_free(sc, sc->sc_reply_freeq); 633 634 bus_dmamap_sync(sc->sc_dmat, MPII_DMA_MAP(sc->sc_reply_postq), 635 0, sc->sc_reply_post_qdepth * 8, BUS_DMASYNC_POSTREAD); 636 mpii_dmamem_free(sc, sc->sc_reply_postq); 637 638 free_replies: 639 bus_dmamap_sync(sc->sc_dmat, MPII_DMA_MAP(sc->sc_replies), 640 0, PAGE_SIZE, BUS_DMASYNC_POSTREAD); 641 mpii_dmamem_free(sc, sc->sc_replies); 642 643 free_ccbs: 644 while ((ccb = mpii_get_ccb(sc)) != NULL) 645 bus_dmamap_destroy(sc->sc_dmat, ccb->ccb_dmamap); 646 mpii_dmamem_free(sc, sc->sc_requests); 647 free(sc->sc_ccbs, M_DEVBUF, 0); 648 649 unmap: 650 bus_space_unmap(sc->sc_iot, sc->sc_ioh, sc->sc_ios); 651 sc->sc_ios = 0; 652 } 653 654 int 655 mpii_detach(struct device *self, int flags) 656 { 657 struct mpii_softc *sc = (struct mpii_softc *)self; 658 659 if (sc->sc_ih != NULL) { 660 pci_intr_disestablish(sc->sc_pc, sc->sc_ih); 661 sc->sc_ih = NULL; 662 } 663 if (sc->sc_ios != 0) { 664 bus_space_unmap(sc->sc_iot, sc->sc_ioh, sc->sc_ios); 665 sc->sc_ios = 0; 666 } 667 668 return (0); 669 } 670 671 int 672 mpii_intr(void *arg) 673 { 674 struct mpii_rcb_list evts = SIMPLEQ_HEAD_INITIALIZER(evts); 675 struct mpii_ccb_list ccbs = SIMPLEQ_HEAD_INITIALIZER(ccbs); 676 struct mpii_softc *sc = arg; 677 struct mpii_reply_descr *postq = sc->sc_reply_postq_kva, *rdp; 678 struct mpii_ccb *ccb; 679 struct mpii_rcb *rcb; 680 int smid; 681 u_int idx; 682 int rv = 0; 683 684 mtx_enter(&sc->sc_rep_mtx); 685 bus_dmamap_sync(sc->sc_dmat, 686 MPII_DMA_MAP(sc->sc_reply_postq), 687 0, sc->sc_reply_post_qdepth * sizeof(*rdp), 688 BUS_DMASYNC_POSTREAD | BUS_DMASYNC_POSTWRITE); 689 690 idx = sc->sc_reply_post_host_index; 691 for (;;) { 692 rdp = &postq[idx]; 693 if ((rdp->reply_flags & MPII_REPLY_DESCR_TYPE_MASK) == 694 MPII_REPLY_DESCR_UNUSED) 695 break; 696 if (rdp->data == 0xffffffff) { 697 /* 698 * ioc is still writing to the reply post queue 699 * race condition - bail! 700 */ 701 break; 702 } 703 704 smid = lemtoh16(&rdp->smid); 705 rcb = mpii_reply(sc, rdp); 706 707 if (smid) { 708 ccb = &sc->sc_ccbs[smid - 1]; 709 ccb->ccb_state = MPII_CCB_READY; 710 ccb->ccb_rcb = rcb; 711 SIMPLEQ_INSERT_TAIL(&ccbs, ccb, ccb_link); 712 } else 713 SIMPLEQ_INSERT_TAIL(&evts, rcb, rcb_link); 714 715 if (++idx >= sc->sc_reply_post_qdepth) 716 idx = 0; 717 718 rv = 1; 719 } 720 721 bus_dmamap_sync(sc->sc_dmat, 722 MPII_DMA_MAP(sc->sc_reply_postq), 723 0, sc->sc_reply_post_qdepth * sizeof(*rdp), 724 BUS_DMASYNC_PREREAD | BUS_DMASYNC_PREWRITE); 725 726 if (rv) 727 mpii_write_reply_post(sc, sc->sc_reply_post_host_index = idx); 728 729 mtx_leave(&sc->sc_rep_mtx); 730 731 if (rv == 0) 732 return (0); 733 734 while ((ccb = SIMPLEQ_FIRST(&ccbs)) != NULL) { 735 SIMPLEQ_REMOVE_HEAD(&ccbs, ccb_link); 736 ccb->ccb_done(ccb); 737 } 738 while ((rcb = SIMPLEQ_FIRST(&evts)) != NULL) { 739 SIMPLEQ_REMOVE_HEAD(&evts, rcb_link); 740 mpii_event_process(sc, rcb); 741 } 742 743 return (1); 744 } 745 746 int 747 mpii_load_xs_sas3(struct mpii_ccb *ccb) 748 { 749 struct mpii_softc *sc = ccb->ccb_sc; 750 struct scsi_xfer *xs = ccb->ccb_cookie; 751 struct mpii_msg_scsi_io *io = ccb->ccb_cmd; 752 struct mpii_ieee_sge *csge, *nsge, *sge; 753 bus_dmamap_t dmap = ccb->ccb_dmamap; 754 int i, error; 755 756 /* Request frame structure is described in the mpii_iocfacts */ 757 nsge = (struct mpii_ieee_sge *)(io + 1); 758 csge = nsge + sc->sc_chain_sge; 759 760 /* zero length transfer still requires an SGE */ 761 if (xs->datalen == 0) { 762 nsge->sg_flags = MPII_IEEE_SGE_END_OF_LIST; 763 return (0); 764 } 765 766 error = bus_dmamap_load(sc->sc_dmat, dmap, xs->data, xs->datalen, NULL, 767 (xs->flags & SCSI_NOSLEEP) ? BUS_DMA_NOWAIT : BUS_DMA_WAITOK); 768 if (error) { 769 printf("%s: error %d loading dmamap\n", DEVNAME(sc), error); 770 return (1); 771 } 772 773 for (i = 0; i < dmap->dm_nsegs; i++, nsge++) { 774 if (nsge == csge) { 775 nsge++; 776 /* offset to the chain sge from the beginning */ 777 io->chain_offset = ((caddr_t)csge - (caddr_t)io) / 4; 778 csge->sg_flags = MPII_IEEE_SGE_CHAIN_ELEMENT | 779 MPII_IEEE_SGE_ADDR_SYSTEM; 780 /* address of the next sge */ 781 csge->sg_addr = htole64(ccb->ccb_cmd_dva + 782 ((caddr_t)nsge - (caddr_t)io)); 783 csge->sg_len = htole32((dmap->dm_nsegs - i) * 784 sizeof(*sge)); 785 } 786 787 sge = nsge; 788 sge->sg_flags = MPII_IEEE_SGE_ADDR_SYSTEM; 789 sge->sg_len = htole32(dmap->dm_segs[i].ds_len); 790 sge->sg_addr = htole64(dmap->dm_segs[i].ds_addr); 791 } 792 793 /* terminate list */ 794 sge->sg_flags |= MPII_IEEE_SGE_END_OF_LIST; 795 796 bus_dmamap_sync(sc->sc_dmat, dmap, 0, dmap->dm_mapsize, 797 (xs->flags & SCSI_DATA_IN) ? BUS_DMASYNC_PREREAD : 798 BUS_DMASYNC_PREWRITE); 799 800 return (0); 801 } 802 803 int 804 mpii_load_xs(struct mpii_ccb *ccb) 805 { 806 struct mpii_softc *sc = ccb->ccb_sc; 807 struct scsi_xfer *xs = ccb->ccb_cookie; 808 struct mpii_msg_scsi_io *io = ccb->ccb_cmd; 809 struct mpii_sge *csge, *nsge, *sge; 810 bus_dmamap_t dmap = ccb->ccb_dmamap; 811 u_int32_t flags; 812 u_int16_t len; 813 int i, error; 814 815 /* Request frame structure is described in the mpii_iocfacts */ 816 nsge = (struct mpii_sge *)(io + 1); 817 csge = nsge + sc->sc_chain_sge; 818 819 /* zero length transfer still requires an SGE */ 820 if (xs->datalen == 0) { 821 nsge->sg_hdr = htole32(MPII_SGE_FL_TYPE_SIMPLE | 822 MPII_SGE_FL_LAST | MPII_SGE_FL_EOB | MPII_SGE_FL_EOL); 823 return (0); 824 } 825 826 error = bus_dmamap_load(sc->sc_dmat, dmap, xs->data, xs->datalen, NULL, 827 (xs->flags & SCSI_NOSLEEP) ? BUS_DMA_NOWAIT : BUS_DMA_WAITOK); 828 if (error) { 829 printf("%s: error %d loading dmamap\n", DEVNAME(sc), error); 830 return (1); 831 } 832 833 /* safe default starting flags */ 834 flags = MPII_SGE_FL_TYPE_SIMPLE | MPII_SGE_FL_SIZE_64; 835 if (xs->flags & SCSI_DATA_OUT) 836 flags |= MPII_SGE_FL_DIR_OUT; 837 838 for (i = 0; i < dmap->dm_nsegs; i++, nsge++) { 839 if (nsge == csge) { 840 nsge++; 841 /* offset to the chain sge from the beginning */ 842 io->chain_offset = ((caddr_t)csge - (caddr_t)io) / 4; 843 /* length of the sgl segment we're pointing to */ 844 len = (dmap->dm_nsegs - i) * sizeof(*sge); 845 csge->sg_hdr = htole32(MPII_SGE_FL_TYPE_CHAIN | 846 MPII_SGE_FL_SIZE_64 | len); 847 /* address of the next sge */ 848 mpii_dvatosge(csge, ccb->ccb_cmd_dva + 849 ((caddr_t)nsge - (caddr_t)io)); 850 } 851 852 sge = nsge; 853 sge->sg_hdr = htole32(flags | dmap->dm_segs[i].ds_len); 854 mpii_dvatosge(sge, dmap->dm_segs[i].ds_addr); 855 } 856 857 /* terminate list */ 858 sge->sg_hdr |= htole32(MPII_SGE_FL_LAST | MPII_SGE_FL_EOB | 859 MPII_SGE_FL_EOL); 860 861 bus_dmamap_sync(sc->sc_dmat, dmap, 0, dmap->dm_mapsize, 862 (xs->flags & SCSI_DATA_IN) ? BUS_DMASYNC_PREREAD : 863 BUS_DMASYNC_PREWRITE); 864 865 return (0); 866 } 867 868 int 869 mpii_scsi_probe(struct scsi_link *link) 870 { 871 struct mpii_softc *sc = link->adapter_softc; 872 struct mpii_cfg_sas_dev_pg0 pg0; 873 struct mpii_ecfg_hdr ehdr; 874 struct mpii_device *dev; 875 uint32_t address; 876 int flags; 877 878 if ((sc->sc_porttype != MPII_PORTFACTS_PORTTYPE_SAS_PHYSICAL) && 879 (sc->sc_porttype != MPII_PORTFACTS_PORTTYPE_SAS_VIRTUAL)) 880 return (ENXIO); 881 882 dev = sc->sc_devs[link->target]; 883 if (dev == NULL) 884 return (1); 885 886 flags = dev->flags; 887 if (ISSET(flags, MPII_DF_HIDDEN) || ISSET(flags, MPII_DF_UNUSED)) 888 return (1); 889 890 if (ISSET(flags, MPII_DF_VOLUME)) 891 return (0); 892 893 memset(&ehdr, 0, sizeof(ehdr)); 894 ehdr.page_type = MPII_CONFIG_REQ_PAGE_TYPE_EXTENDED; 895 ehdr.page_number = 0; 896 ehdr.page_version = 0; 897 ehdr.ext_page_type = MPII_CONFIG_REQ_EXTPAGE_TYPE_SAS_DEVICE; 898 ehdr.ext_page_length = htole16(sizeof(pg0) / 4); /* dwords */ 899 900 address = MPII_PGAD_SAS_DEVICE_FORM_HANDLE | (uint32_t)dev->dev_handle; 901 if (mpii_req_cfg_page(sc, address, MPII_PG_EXTENDED, 902 &ehdr, 1, &pg0, sizeof(pg0)) != 0) { 903 printf("%s: unable to fetch SAS device page 0 for target %u\n", 904 DEVNAME(sc), link->target); 905 906 return (0); /* the handle should still work */ 907 } 908 909 link->port_wwn = letoh64(pg0.sas_addr); 910 link->node_wwn = letoh64(pg0.device_name); 911 912 if (ISSET(lemtoh32(&pg0.device_info), 913 MPII_CFG_SAS_DEV_0_DEVINFO_ATAPI_DEVICE)) { 914 link->flags |= SDEV_ATAPI; 915 link->quirks |= SDEV_ONLYBIG; 916 } 917 918 return (0); 919 } 920 921 u_int32_t 922 mpii_read(struct mpii_softc *sc, bus_size_t r) 923 { 924 u_int32_t rv; 925 926 bus_space_barrier(sc->sc_iot, sc->sc_ioh, r, 4, 927 BUS_SPACE_BARRIER_READ); 928 rv = bus_space_read_4(sc->sc_iot, sc->sc_ioh, r); 929 930 DNPRINTF(MPII_D_RW, "%s: mpii_read %#lx %#x\n", DEVNAME(sc), r, rv); 931 932 return (rv); 933 } 934 935 void 936 mpii_write(struct mpii_softc *sc, bus_size_t r, u_int32_t v) 937 { 938 DNPRINTF(MPII_D_RW, "%s: mpii_write %#lx %#x\n", DEVNAME(sc), r, v); 939 940 bus_space_write_4(sc->sc_iot, sc->sc_ioh, r, v); 941 bus_space_barrier(sc->sc_iot, sc->sc_ioh, r, 4, 942 BUS_SPACE_BARRIER_WRITE); 943 } 944 945 946 int 947 mpii_wait_eq(struct mpii_softc *sc, bus_size_t r, u_int32_t mask, 948 u_int32_t target) 949 { 950 int i; 951 952 DNPRINTF(MPII_D_RW, "%s: mpii_wait_eq %#lx %#x %#x\n", DEVNAME(sc), r, 953 mask, target); 954 955 for (i = 0; i < 15000; i++) { 956 if ((mpii_read(sc, r) & mask) == target) 957 return (0); 958 delay(1000); 959 } 960 961 return (1); 962 } 963 964 int 965 mpii_wait_ne(struct mpii_softc *sc, bus_size_t r, u_int32_t mask, 966 u_int32_t target) 967 { 968 int i; 969 970 DNPRINTF(MPII_D_RW, "%s: mpii_wait_ne %#lx %#x %#x\n", DEVNAME(sc), r, 971 mask, target); 972 973 for (i = 0; i < 15000; i++) { 974 if ((mpii_read(sc, r) & mask) != target) 975 return (0); 976 delay(1000); 977 } 978 979 return (1); 980 } 981 982 int 983 mpii_init(struct mpii_softc *sc) 984 { 985 u_int32_t db; 986 int i; 987 988 /* spin until the ioc leaves the reset state */ 989 if (mpii_wait_ne(sc, MPII_DOORBELL, MPII_DOORBELL_STATE, 990 MPII_DOORBELL_STATE_RESET) != 0) { 991 DNPRINTF(MPII_D_MISC, "%s: mpii_init timeout waiting to leave " 992 "reset state\n", DEVNAME(sc)); 993 return (1); 994 } 995 996 /* check current ownership */ 997 db = mpii_read_db(sc); 998 if ((db & MPII_DOORBELL_WHOINIT) == MPII_DOORBELL_WHOINIT_PCIPEER) { 999 DNPRINTF(MPII_D_MISC, "%s: mpii_init initialised by pci peer\n", 1000 DEVNAME(sc)); 1001 return (0); 1002 } 1003 1004 for (i = 0; i < 5; i++) { 1005 switch (db & MPII_DOORBELL_STATE) { 1006 case MPII_DOORBELL_STATE_READY: 1007 DNPRINTF(MPII_D_MISC, "%s: mpii_init ioc is ready\n", 1008 DEVNAME(sc)); 1009 return (0); 1010 1011 case MPII_DOORBELL_STATE_OPER: 1012 DNPRINTF(MPII_D_MISC, "%s: mpii_init ioc is oper\n", 1013 DEVNAME(sc)); 1014 if (sc->sc_ioc_event_replay) 1015 mpii_reset_soft(sc); 1016 else 1017 mpii_reset_hard(sc); 1018 break; 1019 1020 case MPII_DOORBELL_STATE_FAULT: 1021 DNPRINTF(MPII_D_MISC, "%s: mpii_init ioc is being " 1022 "reset hard\n" , DEVNAME(sc)); 1023 mpii_reset_hard(sc); 1024 break; 1025 1026 case MPII_DOORBELL_STATE_RESET: 1027 DNPRINTF(MPII_D_MISC, "%s: mpii_init waiting to come " 1028 "out of reset\n", DEVNAME(sc)); 1029 if (mpii_wait_ne(sc, MPII_DOORBELL, MPII_DOORBELL_STATE, 1030 MPII_DOORBELL_STATE_RESET) != 0) 1031 return (1); 1032 break; 1033 } 1034 db = mpii_read_db(sc); 1035 } 1036 1037 return (1); 1038 } 1039 1040 int 1041 mpii_reset_soft(struct mpii_softc *sc) 1042 { 1043 DNPRINTF(MPII_D_MISC, "%s: mpii_reset_soft\n", DEVNAME(sc)); 1044 1045 if (mpii_read_db(sc) & MPII_DOORBELL_INUSE) { 1046 return (1); 1047 } 1048 1049 mpii_write_db(sc, 1050 MPII_DOORBELL_FUNCTION(MPII_FUNCTION_IOC_MESSAGE_UNIT_RESET)); 1051 1052 /* XXX LSI waits 15 sec */ 1053 if (mpii_wait_db_ack(sc) != 0) 1054 return (1); 1055 1056 /* XXX LSI waits 15 sec */ 1057 if (mpii_wait_eq(sc, MPII_DOORBELL, MPII_DOORBELL_STATE, 1058 MPII_DOORBELL_STATE_READY) != 0) 1059 return (1); 1060 1061 /* XXX wait for Sys2IOCDB bit to clear in HIS?? */ 1062 1063 return (0); 1064 } 1065 1066 int 1067 mpii_reset_hard(struct mpii_softc *sc) 1068 { 1069 u_int16_t i; 1070 1071 DNPRINTF(MPII_D_MISC, "%s: mpii_reset_hard\n", DEVNAME(sc)); 1072 1073 mpii_write_intr(sc, 0); 1074 1075 /* enable diagnostic register */ 1076 mpii_write(sc, MPII_WRITESEQ, MPII_WRITESEQ_FLUSH); 1077 mpii_write(sc, MPII_WRITESEQ, MPII_WRITESEQ_1); 1078 mpii_write(sc, MPII_WRITESEQ, MPII_WRITESEQ_2); 1079 mpii_write(sc, MPII_WRITESEQ, MPII_WRITESEQ_3); 1080 mpii_write(sc, MPII_WRITESEQ, MPII_WRITESEQ_4); 1081 mpii_write(sc, MPII_WRITESEQ, MPII_WRITESEQ_5); 1082 mpii_write(sc, MPII_WRITESEQ, MPII_WRITESEQ_6); 1083 1084 delay(100); 1085 1086 if ((mpii_read(sc, MPII_HOSTDIAG) & MPII_HOSTDIAG_DWRE) == 0) { 1087 DNPRINTF(MPII_D_MISC, "%s: mpii_reset_hard failure to enable " 1088 "diagnostic read/write\n", DEVNAME(sc)); 1089 return(1); 1090 } 1091 1092 /* reset ioc */ 1093 mpii_write(sc, MPII_HOSTDIAG, MPII_HOSTDIAG_RESET_ADAPTER); 1094 1095 /* 240 milliseconds */ 1096 delay(240000); 1097 1098 1099 /* XXX this whole function should be more robust */ 1100 1101 /* XXX read the host diagnostic reg until reset adapter bit clears ? */ 1102 for (i = 0; i < 30000; i++) { 1103 if ((mpii_read(sc, MPII_HOSTDIAG) & 1104 MPII_HOSTDIAG_RESET_ADAPTER) == 0) 1105 break; 1106 delay(10000); 1107 } 1108 1109 /* disable diagnostic register */ 1110 mpii_write(sc, MPII_WRITESEQ, 0xff); 1111 1112 /* XXX what else? */ 1113 1114 DNPRINTF(MPII_D_MISC, "%s: done with mpii_reset_hard\n", DEVNAME(sc)); 1115 1116 return(0); 1117 } 1118 1119 int 1120 mpii_handshake_send(struct mpii_softc *sc, void *buf, size_t dwords) 1121 { 1122 u_int32_t *query = buf; 1123 int i; 1124 1125 /* make sure the doorbell is not in use. */ 1126 if (mpii_read_db(sc) & MPII_DOORBELL_INUSE) 1127 return (1); 1128 1129 /* clear pending doorbell interrupts */ 1130 if (mpii_read_intr(sc) & MPII_INTR_STATUS_IOC2SYSDB) 1131 mpii_write_intr(sc, 0); 1132 1133 /* 1134 * first write the doorbell with the handshake function and the 1135 * dword count. 1136 */ 1137 mpii_write_db(sc, MPII_DOORBELL_FUNCTION(MPII_FUNCTION_HANDSHAKE) | 1138 MPII_DOORBELL_DWORDS(dwords)); 1139 1140 /* 1141 * the doorbell used bit will be set because a doorbell function has 1142 * started. wait for the interrupt and then ack it. 1143 */ 1144 if (mpii_wait_db_int(sc) != 0) 1145 return (1); 1146 mpii_write_intr(sc, 0); 1147 1148 /* poll for the acknowledgement. */ 1149 if (mpii_wait_db_ack(sc) != 0) 1150 return (1); 1151 1152 /* write the query through the doorbell. */ 1153 for (i = 0; i < dwords; i++) { 1154 mpii_write_db(sc, htole32(query[i])); 1155 if (mpii_wait_db_ack(sc) != 0) 1156 return (1); 1157 } 1158 1159 return (0); 1160 } 1161 1162 int 1163 mpii_handshake_recv_dword(struct mpii_softc *sc, u_int32_t *dword) 1164 { 1165 u_int16_t *words = (u_int16_t *)dword; 1166 int i; 1167 1168 for (i = 0; i < 2; i++) { 1169 if (mpii_wait_db_int(sc) != 0) 1170 return (1); 1171 words[i] = letoh16(mpii_read_db(sc) & MPII_DOORBELL_DATA_MASK); 1172 mpii_write_intr(sc, 0); 1173 } 1174 1175 return (0); 1176 } 1177 1178 int 1179 mpii_handshake_recv(struct mpii_softc *sc, void *buf, size_t dwords) 1180 { 1181 struct mpii_msg_reply *reply = buf; 1182 u_int32_t *dbuf = buf, dummy; 1183 int i; 1184 1185 /* get the first dword so we can read the length out of the header. */ 1186 if (mpii_handshake_recv_dword(sc, &dbuf[0]) != 0) 1187 return (1); 1188 1189 DNPRINTF(MPII_D_CMD, "%s: mpii_handshake_recv dwords: %lu reply: %d\n", 1190 DEVNAME(sc), dwords, reply->msg_length); 1191 1192 /* 1193 * the total length, in dwords, is in the message length field of the 1194 * reply header. 1195 */ 1196 for (i = 1; i < MIN(dwords, reply->msg_length); i++) { 1197 if (mpii_handshake_recv_dword(sc, &dbuf[i]) != 0) 1198 return (1); 1199 } 1200 1201 /* if there's extra stuff to come off the ioc, discard it */ 1202 while (i++ < reply->msg_length) { 1203 if (mpii_handshake_recv_dword(sc, &dummy) != 0) 1204 return (1); 1205 DNPRINTF(MPII_D_CMD, "%s: mpii_handshake_recv dummy read: " 1206 "0x%08x\n", DEVNAME(sc), dummy); 1207 } 1208 1209 /* wait for the doorbell used bit to be reset and clear the intr */ 1210 if (mpii_wait_db_int(sc) != 0) 1211 return (1); 1212 1213 if (mpii_wait_eq(sc, MPII_DOORBELL, MPII_DOORBELL_INUSE, 0) != 0) 1214 return (1); 1215 1216 mpii_write_intr(sc, 0); 1217 1218 return (0); 1219 } 1220 1221 void 1222 mpii_empty_done(struct mpii_ccb *ccb) 1223 { 1224 /* nothing to do */ 1225 } 1226 1227 int 1228 mpii_iocfacts(struct mpii_softc *sc) 1229 { 1230 struct mpii_msg_iocfacts_request ifq; 1231 struct mpii_msg_iocfacts_reply ifp; 1232 int irs; 1233 int sge_size; 1234 u_int qdepth; 1235 1236 DNPRINTF(MPII_D_MISC, "%s: mpii_iocfacts\n", DEVNAME(sc)); 1237 1238 memset(&ifq, 0, sizeof(ifq)); 1239 memset(&ifp, 0, sizeof(ifp)); 1240 1241 ifq.function = MPII_FUNCTION_IOC_FACTS; 1242 1243 if (mpii_handshake_send(sc, &ifq, dwordsof(ifq)) != 0) { 1244 DNPRINTF(MPII_D_MISC, "%s: mpii_iocfacts send failed\n", 1245 DEVNAME(sc)); 1246 return (1); 1247 } 1248 1249 if (mpii_handshake_recv(sc, &ifp, dwordsof(ifp)) != 0) { 1250 DNPRINTF(MPII_D_MISC, "%s: mpii_iocfacts recv failed\n", 1251 DEVNAME(sc)); 1252 return (1); 1253 } 1254 1255 sc->sc_ioc_number = ifp.ioc_number; 1256 sc->sc_vf_id = ifp.vf_id; 1257 1258 sc->sc_max_volumes = ifp.max_volumes; 1259 sc->sc_max_devices = ifp.max_volumes + lemtoh16(&ifp.max_targets); 1260 1261 if (ISSET(lemtoh32(&ifp.ioc_capabilities), 1262 MPII_IOCFACTS_CAPABILITY_INTEGRATED_RAID)) 1263 SET(sc->sc_flags, MPII_F_RAID); 1264 1265 sc->sc_max_cmds = MIN(lemtoh16(&ifp.request_credit), 1266 MPII_REQUEST_CREDIT); 1267 1268 /* SAS3 controllers have different sgl layouts */ 1269 if (ifp.msg_version_maj == 2 && ifp.msg_version_min == 5) 1270 SET(sc->sc_flags, MPII_F_SAS3); 1271 1272 /* 1273 * The host driver must ensure that there is at least one 1274 * unused entry in the Reply Free Queue. One way to ensure 1275 * that this requirement is met is to never allocate a number 1276 * of reply frames that is a multiple of 16. 1277 */ 1278 sc->sc_num_reply_frames = sc->sc_max_cmds + 32; 1279 if (!(sc->sc_num_reply_frames % 16)) 1280 sc->sc_num_reply_frames--; 1281 1282 /* must be multiple of 16 */ 1283 sc->sc_reply_post_qdepth = sc->sc_max_cmds + 1284 sc->sc_num_reply_frames; 1285 sc->sc_reply_post_qdepth += 16 - (sc->sc_reply_post_qdepth % 16); 1286 1287 qdepth = lemtoh16(&ifp.max_reply_descriptor_post_queue_depth); 1288 if (sc->sc_reply_post_qdepth > qdepth) { 1289 sc->sc_reply_post_qdepth = qdepth; 1290 if (sc->sc_reply_post_qdepth < 16) { 1291 printf("%s: RDPQ is too shallow\n", DEVNAME(sc)); 1292 return (1); 1293 } 1294 sc->sc_max_cmds = sc->sc_reply_post_qdepth / 2 - 4; 1295 sc->sc_num_reply_frames = sc->sc_max_cmds + 4; 1296 } 1297 1298 sc->sc_reply_free_qdepth = sc->sc_num_reply_frames + 1299 16 - (sc->sc_num_reply_frames % 16); 1300 1301 /* 1302 * Our request frame for an I/O operation looks like this: 1303 * 1304 * +-------------------+ -. 1305 * | mpii_msg_scsi_io | | 1306 * +-------------------| | 1307 * | mpii_sge | | 1308 * + - - - - - - - - - + | 1309 * | ... | > ioc_request_frame_size 1310 * + - - - - - - - - - + | 1311 * | mpii_sge (tail) | | 1312 * + - - - - - - - - - + | 1313 * | mpii_sge (csge) | | --. 1314 * + - - - - - - - - - + -' | chain sge points to the next sge 1315 * | mpii_sge |<-----' 1316 * + - - - - - - - - - + 1317 * | ... | 1318 * + - - - - - - - - - + 1319 * | mpii_sge (tail) | 1320 * +-------------------+ 1321 * | | 1322 * ~~~~~~~~~~~~~~~~~~~~~ 1323 * | | 1324 * +-------------------+ <- sc_request_size - sizeof(scsi_sense_data) 1325 * | scsi_sense_data | 1326 * +-------------------+ 1327 */ 1328 1329 /* both sizes are in 32-bit words */ 1330 sc->sc_reply_size = ifp.reply_frame_size * 4; 1331 irs = lemtoh16(&ifp.ioc_request_frame_size) * 4; 1332 sc->sc_request_size = MPII_REQUEST_SIZE; 1333 /* make sure we have enough space for scsi sense data */ 1334 if (irs > sc->sc_request_size) { 1335 sc->sc_request_size = irs + sizeof(struct scsi_sense_data); 1336 sc->sc_request_size += 16 - (sc->sc_request_size % 16); 1337 } 1338 1339 if (ISSET(sc->sc_flags, MPII_F_SAS3)) { 1340 sge_size = sizeof(struct mpii_ieee_sge); 1341 } else { 1342 sge_size = sizeof(struct mpii_sge); 1343 } 1344 1345 /* offset to the chain sge */ 1346 sc->sc_chain_sge = (irs - sizeof(struct mpii_msg_scsi_io)) / 1347 sge_size - 1; 1348 1349 /* 1350 * A number of simple scatter-gather elements we can fit into the 1351 * request buffer after the I/O command minus the chain element. 1352 */ 1353 sc->sc_max_sgl = (sc->sc_request_size - 1354 sizeof(struct mpii_msg_scsi_io) - sizeof(struct scsi_sense_data)) / 1355 sge_size - 1; 1356 1357 return (0); 1358 } 1359 1360 int 1361 mpii_iocinit(struct mpii_softc *sc) 1362 { 1363 struct mpii_msg_iocinit_request iiq; 1364 struct mpii_msg_iocinit_reply iip; 1365 1366 DNPRINTF(MPII_D_MISC, "%s: mpii_iocinit\n", DEVNAME(sc)); 1367 1368 memset(&iiq, 0, sizeof(iiq)); 1369 memset(&iip, 0, sizeof(iip)); 1370 1371 iiq.function = MPII_FUNCTION_IOC_INIT; 1372 iiq.whoinit = MPII_WHOINIT_HOST_DRIVER; 1373 1374 /* XXX JPG do something about vf_id */ 1375 iiq.vf_id = 0; 1376 1377 iiq.msg_version_maj = 0x02; 1378 iiq.msg_version_min = 0x00; 1379 1380 /* XXX JPG ensure compliance with some level and hard-code? */ 1381 iiq.hdr_version_unit = 0x00; 1382 iiq.hdr_version_dev = 0x00; 1383 1384 htolem16(&iiq.system_request_frame_size, sc->sc_request_size / 4); 1385 1386 htolem16(&iiq.reply_descriptor_post_queue_depth, 1387 sc->sc_reply_post_qdepth); 1388 1389 htolem16(&iiq.reply_free_queue_depth, sc->sc_reply_free_qdepth); 1390 1391 htolem32(&iiq.sense_buffer_address_high, 1392 MPII_DMA_DVA(sc->sc_requests) >> 32); 1393 1394 htolem32(&iiq.system_reply_address_high, 1395 MPII_DMA_DVA(sc->sc_replies) >> 32); 1396 1397 htolem32(&iiq.system_request_frame_base_address_lo, 1398 MPII_DMA_DVA(sc->sc_requests)); 1399 htolem32(&iiq.system_request_frame_base_address_hi, 1400 MPII_DMA_DVA(sc->sc_requests) >> 32); 1401 1402 htolem32(&iiq.reply_descriptor_post_queue_address_lo, 1403 MPII_DMA_DVA(sc->sc_reply_postq)); 1404 htolem32(&iiq.reply_descriptor_post_queue_address_hi, 1405 MPII_DMA_DVA(sc->sc_reply_postq) >> 32); 1406 1407 htolem32(&iiq.reply_free_queue_address_lo, 1408 MPII_DMA_DVA(sc->sc_reply_freeq)); 1409 htolem32(&iiq.reply_free_queue_address_hi, 1410 MPII_DMA_DVA(sc->sc_reply_freeq) >> 32); 1411 1412 if (mpii_handshake_send(sc, &iiq, dwordsof(iiq)) != 0) { 1413 DNPRINTF(MPII_D_MISC, "%s: mpii_iocinit send failed\n", 1414 DEVNAME(sc)); 1415 return (1); 1416 } 1417 1418 if (mpii_handshake_recv(sc, &iip, dwordsof(iip)) != 0) { 1419 DNPRINTF(MPII_D_MISC, "%s: mpii_iocinit recv failed\n", 1420 DEVNAME(sc)); 1421 return (1); 1422 } 1423 1424 DNPRINTF(MPII_D_MISC, "%s: function: 0x%02x msg_length: %d " 1425 "whoinit: 0x%02x\n", DEVNAME(sc), iip.function, 1426 iip.msg_length, iip.whoinit); 1427 DNPRINTF(MPII_D_MISC, "%s: msg_flags: 0x%02x\n", DEVNAME(sc), 1428 iip.msg_flags); 1429 DNPRINTF(MPII_D_MISC, "%s: vf_id: 0x%02x vp_id: 0x%02x\n", DEVNAME(sc), 1430 iip.vf_id, iip.vp_id); 1431 DNPRINTF(MPII_D_MISC, "%s: ioc_status: 0x%04x\n", DEVNAME(sc), 1432 letoh16(iip.ioc_status)); 1433 DNPRINTF(MPII_D_MISC, "%s: ioc_loginfo: 0x%08x\n", DEVNAME(sc), 1434 letoh32(iip.ioc_loginfo)); 1435 1436 if (lemtoh16(&iip.ioc_status) != MPII_IOCSTATUS_SUCCESS || 1437 lemtoh32(&iip.ioc_loginfo)) 1438 return (1); 1439 1440 return (0); 1441 } 1442 1443 void 1444 mpii_push_reply(struct mpii_softc *sc, struct mpii_rcb *rcb) 1445 { 1446 u_int32_t *rfp; 1447 u_int idx; 1448 1449 if (rcb == NULL) 1450 return; 1451 1452 idx = sc->sc_reply_free_host_index; 1453 1454 rfp = MPII_DMA_KVA(sc->sc_reply_freeq); 1455 htolem32(&rfp[idx], rcb->rcb_reply_dva); 1456 1457 if (++idx >= sc->sc_reply_free_qdepth) 1458 idx = 0; 1459 1460 mpii_write_reply_free(sc, sc->sc_reply_free_host_index = idx); 1461 } 1462 1463 int 1464 mpii_portfacts(struct mpii_softc *sc) 1465 { 1466 struct mpii_msg_portfacts_request *pfq; 1467 struct mpii_msg_portfacts_reply *pfp; 1468 struct mpii_ccb *ccb; 1469 int rv = 1; 1470 1471 DNPRINTF(MPII_D_MISC, "%s: mpii_portfacts\n", DEVNAME(sc)); 1472 1473 ccb = scsi_io_get(&sc->sc_iopool, 0); 1474 if (ccb == NULL) { 1475 DNPRINTF(MPII_D_MISC, "%s: mpii_portfacts mpii_get_ccb fail\n", 1476 DEVNAME(sc)); 1477 return (rv); 1478 } 1479 1480 ccb->ccb_done = mpii_empty_done; 1481 pfq = ccb->ccb_cmd; 1482 1483 memset(pfq, 0, sizeof(*pfq)); 1484 1485 pfq->function = MPII_FUNCTION_PORT_FACTS; 1486 pfq->chain_offset = 0; 1487 pfq->msg_flags = 0; 1488 pfq->port_number = 0; 1489 pfq->vp_id = 0; 1490 pfq->vf_id = 0; 1491 1492 if (mpii_poll(sc, ccb) != 0) { 1493 DNPRINTF(MPII_D_MISC, "%s: mpii_portfacts poll\n", 1494 DEVNAME(sc)); 1495 goto err; 1496 } 1497 1498 if (ccb->ccb_rcb == NULL) { 1499 DNPRINTF(MPII_D_MISC, "%s: empty portfacts reply\n", 1500 DEVNAME(sc)); 1501 goto err; 1502 } 1503 1504 pfp = ccb->ccb_rcb->rcb_reply; 1505 sc->sc_porttype = pfp->port_type; 1506 1507 mpii_push_reply(sc, ccb->ccb_rcb); 1508 rv = 0; 1509 err: 1510 scsi_io_put(&sc->sc_iopool, ccb); 1511 1512 return (rv); 1513 } 1514 1515 void 1516 mpii_eventack(void *cookie, void *io) 1517 { 1518 struct mpii_softc *sc = cookie; 1519 struct mpii_ccb *ccb = io; 1520 struct mpii_rcb *rcb, *next; 1521 struct mpii_msg_event_reply *enp; 1522 struct mpii_msg_eventack_request *eaq; 1523 1524 mtx_enter(&sc->sc_evt_ack_mtx); 1525 rcb = SIMPLEQ_FIRST(&sc->sc_evt_ack_queue); 1526 if (rcb != NULL) { 1527 next = SIMPLEQ_NEXT(rcb, rcb_link); 1528 SIMPLEQ_REMOVE_HEAD(&sc->sc_evt_ack_queue, rcb_link); 1529 } 1530 mtx_leave(&sc->sc_evt_ack_mtx); 1531 1532 if (rcb == NULL) { 1533 scsi_io_put(&sc->sc_iopool, ccb); 1534 return; 1535 } 1536 1537 enp = (struct mpii_msg_event_reply *)rcb->rcb_reply; 1538 1539 ccb->ccb_done = mpii_eventack_done; 1540 eaq = ccb->ccb_cmd; 1541 1542 eaq->function = MPII_FUNCTION_EVENT_ACK; 1543 1544 eaq->event = enp->event; 1545 eaq->event_context = enp->event_context; 1546 1547 mpii_push_reply(sc, rcb); 1548 1549 mpii_start(sc, ccb); 1550 1551 if (next != NULL) 1552 scsi_ioh_add(&sc->sc_evt_ack_handler); 1553 } 1554 1555 void 1556 mpii_eventack_done(struct mpii_ccb *ccb) 1557 { 1558 struct mpii_softc *sc = ccb->ccb_sc; 1559 1560 DNPRINTF(MPII_D_EVT, "%s: event ack done\n", DEVNAME(sc)); 1561 1562 mpii_push_reply(sc, ccb->ccb_rcb); 1563 scsi_io_put(&sc->sc_iopool, ccb); 1564 } 1565 1566 int 1567 mpii_portenable(struct mpii_softc *sc) 1568 { 1569 struct mpii_msg_portenable_request *peq; 1570 struct mpii_ccb *ccb; 1571 1572 DNPRINTF(MPII_D_MISC, "%s: mpii_portenable\n", DEVNAME(sc)); 1573 1574 ccb = scsi_io_get(&sc->sc_iopool, 0); 1575 if (ccb == NULL) { 1576 DNPRINTF(MPII_D_MISC, "%s: mpii_portenable ccb_get\n", 1577 DEVNAME(sc)); 1578 return (1); 1579 } 1580 1581 ccb->ccb_done = mpii_empty_done; 1582 peq = ccb->ccb_cmd; 1583 1584 peq->function = MPII_FUNCTION_PORT_ENABLE; 1585 peq->vf_id = sc->sc_vf_id; 1586 1587 if (mpii_poll(sc, ccb) != 0) { 1588 DNPRINTF(MPII_D_MISC, "%s: mpii_portenable poll\n", 1589 DEVNAME(sc)); 1590 return (1); 1591 } 1592 1593 if (ccb->ccb_rcb == NULL) { 1594 DNPRINTF(MPII_D_MISC, "%s: empty portenable reply\n", 1595 DEVNAME(sc)); 1596 return (1); 1597 } 1598 1599 mpii_push_reply(sc, ccb->ccb_rcb); 1600 scsi_io_put(&sc->sc_iopool, ccb); 1601 1602 return (0); 1603 } 1604 1605 int 1606 mpii_cfg_coalescing(struct mpii_softc *sc) 1607 { 1608 struct mpii_cfg_hdr hdr; 1609 struct mpii_cfg_ioc_pg1 ipg; 1610 1611 hdr.page_version = 0; 1612 hdr.page_length = sizeof(ipg) / 4; 1613 hdr.page_number = 1; 1614 hdr.page_type = MPII_CONFIG_REQ_PAGE_TYPE_IOC; 1615 memset(&ipg, 0, sizeof(ipg)); 1616 if (mpii_req_cfg_page(sc, 0, MPII_PG_POLL, &hdr, 1, &ipg, 1617 sizeof(ipg)) != 0) { 1618 DNPRINTF(MPII_D_MISC, "%s: unable to fetch IOC page 1\n" 1619 "page 1\n", DEVNAME(sc)); 1620 return (1); 1621 } 1622 1623 if (!ISSET(lemtoh32(&ipg.flags), MPII_CFG_IOC_1_REPLY_COALESCING)) 1624 return (0); 1625 1626 /* Disable coalescing */ 1627 CLR(ipg.flags, htole32(MPII_CFG_IOC_1_REPLY_COALESCING)); 1628 if (mpii_req_cfg_page(sc, 0, MPII_PG_POLL, &hdr, 0, &ipg, 1629 sizeof(ipg)) != 0) { 1630 DNPRINTF(MPII_D_MISC, "%s: unable to clear coalescing\n", 1631 DEVNAME(sc)); 1632 return (1); 1633 } 1634 1635 return (0); 1636 } 1637 1638 #define MPII_EVENT_MASKALL(enq) do { \ 1639 enq->event_masks[0] = 0xffffffff; \ 1640 enq->event_masks[1] = 0xffffffff; \ 1641 enq->event_masks[2] = 0xffffffff; \ 1642 enq->event_masks[3] = 0xffffffff; \ 1643 } while (0) 1644 1645 #define MPII_EVENT_UNMASK(enq, evt) do { \ 1646 enq->event_masks[evt / 32] &= \ 1647 htole32(~(1 << (evt % 32))); \ 1648 } while (0) 1649 1650 int 1651 mpii_eventnotify(struct mpii_softc *sc) 1652 { 1653 struct mpii_msg_event_request *enq; 1654 struct mpii_ccb *ccb; 1655 1656 ccb = scsi_io_get(&sc->sc_iopool, 0); 1657 if (ccb == NULL) { 1658 DNPRINTF(MPII_D_MISC, "%s: mpii_eventnotify ccb_get\n", 1659 DEVNAME(sc)); 1660 return (1); 1661 } 1662 1663 SIMPLEQ_INIT(&sc->sc_evt_sas_queue); 1664 mtx_init(&sc->sc_evt_sas_mtx, IPL_BIO); 1665 task_set(&sc->sc_evt_sas_task, mpii_event_sas, sc); 1666 1667 SIMPLEQ_INIT(&sc->sc_evt_ack_queue); 1668 mtx_init(&sc->sc_evt_ack_mtx, IPL_BIO); 1669 scsi_ioh_set(&sc->sc_evt_ack_handler, &sc->sc_iopool, 1670 mpii_eventack, sc); 1671 1672 ccb->ccb_done = mpii_eventnotify_done; 1673 enq = ccb->ccb_cmd; 1674 1675 enq->function = MPII_FUNCTION_EVENT_NOTIFICATION; 1676 1677 /* 1678 * Enable reporting of the following events: 1679 * 1680 * MPII_EVENT_SAS_DISCOVERY 1681 * MPII_EVENT_SAS_TOPOLOGY_CHANGE_LIST 1682 * MPII_EVENT_SAS_DEVICE_STATUS_CHANGE 1683 * MPII_EVENT_SAS_ENCL_DEVICE_STATUS_CHANGE 1684 * MPII_EVENT_IR_CONFIGURATION_CHANGE_LIST 1685 * MPII_EVENT_IR_VOLUME 1686 * MPII_EVENT_IR_PHYSICAL_DISK 1687 * MPII_EVENT_IR_OPERATION_STATUS 1688 */ 1689 1690 MPII_EVENT_MASKALL(enq); 1691 MPII_EVENT_UNMASK(enq, MPII_EVENT_SAS_DISCOVERY); 1692 MPII_EVENT_UNMASK(enq, MPII_EVENT_SAS_TOPOLOGY_CHANGE_LIST); 1693 MPII_EVENT_UNMASK(enq, MPII_EVENT_SAS_DEVICE_STATUS_CHANGE); 1694 MPII_EVENT_UNMASK(enq, MPII_EVENT_SAS_ENCL_DEVICE_STATUS_CHANGE); 1695 MPII_EVENT_UNMASK(enq, MPII_EVENT_IR_CONFIGURATION_CHANGE_LIST); 1696 MPII_EVENT_UNMASK(enq, MPII_EVENT_IR_VOLUME); 1697 MPII_EVENT_UNMASK(enq, MPII_EVENT_IR_PHYSICAL_DISK); 1698 MPII_EVENT_UNMASK(enq, MPII_EVENT_IR_OPERATION_STATUS); 1699 1700 mpii_start(sc, ccb); 1701 1702 return (0); 1703 } 1704 1705 void 1706 mpii_eventnotify_done(struct mpii_ccb *ccb) 1707 { 1708 struct mpii_softc *sc = ccb->ccb_sc; 1709 struct mpii_rcb *rcb = ccb->ccb_rcb; 1710 1711 DNPRINTF(MPII_D_EVT, "%s: mpii_eventnotify_done\n", DEVNAME(sc)); 1712 1713 scsi_io_put(&sc->sc_iopool, ccb); 1714 mpii_event_process(sc, rcb); 1715 } 1716 1717 void 1718 mpii_event_raid(struct mpii_softc *sc, struct mpii_msg_event_reply *enp) 1719 { 1720 struct mpii_evt_ir_cfg_change_list *ccl; 1721 struct mpii_evt_ir_cfg_element *ce; 1722 struct mpii_device *dev; 1723 u_int16_t type; 1724 int i; 1725 1726 ccl = (struct mpii_evt_ir_cfg_change_list *)(enp + 1); 1727 if (ccl->num_elements == 0) 1728 return; 1729 1730 if (ISSET(lemtoh32(&ccl->flags), MPII_EVT_IR_CFG_CHANGE_LIST_FOREIGN)) { 1731 /* bail on foreign configurations */ 1732 return; 1733 } 1734 1735 ce = (struct mpii_evt_ir_cfg_element *)(ccl + 1); 1736 1737 for (i = 0; i < ccl->num_elements; i++, ce++) { 1738 type = (lemtoh16(&ce->element_flags) & 1739 MPII_EVT_IR_CFG_ELEMENT_TYPE_MASK); 1740 1741 switch (type) { 1742 case MPII_EVT_IR_CFG_ELEMENT_TYPE_VOLUME: 1743 switch (ce->reason_code) { 1744 case MPII_EVT_IR_CFG_ELEMENT_RC_ADDED: 1745 case MPII_EVT_IR_CFG_ELEMENT_RC_VOLUME_CREATED: 1746 if (mpii_find_dev(sc, 1747 lemtoh16(&ce->vol_dev_handle))) { 1748 printf("%s: device %#x is already " 1749 "configured\n", DEVNAME(sc), 1750 lemtoh16(&ce->vol_dev_handle)); 1751 break; 1752 } 1753 dev = malloc(sizeof(*dev), M_DEVBUF, 1754 M_NOWAIT | M_ZERO); 1755 if (!dev) { 1756 printf("%s: failed to allocate a " 1757 "device structure\n", DEVNAME(sc)); 1758 break; 1759 } 1760 SET(dev->flags, MPII_DF_VOLUME); 1761 dev->slot = sc->sc_vd_id_low; 1762 dev->dev_handle = lemtoh16(&ce->vol_dev_handle); 1763 if (mpii_insert_dev(sc, dev)) { 1764 free(dev, M_DEVBUF, sizeof *dev); 1765 break; 1766 } 1767 sc->sc_vd_count++; 1768 break; 1769 case MPII_EVT_IR_CFG_ELEMENT_RC_REMOVED: 1770 case MPII_EVT_IR_CFG_ELEMENT_RC_VOLUME_DELETED: 1771 if (!(dev = mpii_find_dev(sc, 1772 lemtoh16(&ce->vol_dev_handle)))) 1773 break; 1774 mpii_remove_dev(sc, dev); 1775 sc->sc_vd_count--; 1776 break; 1777 } 1778 break; 1779 case MPII_EVT_IR_CFG_ELEMENT_TYPE_VOLUME_DISK: 1780 if (ce->reason_code == 1781 MPII_EVT_IR_CFG_ELEMENT_RC_PD_CREATED || 1782 ce->reason_code == 1783 MPII_EVT_IR_CFG_ELEMENT_RC_HIDE) { 1784 /* there should be an underlying sas drive */ 1785 if (!(dev = mpii_find_dev(sc, 1786 lemtoh16(&ce->phys_disk_dev_handle)))) 1787 break; 1788 /* promoted from a hot spare? */ 1789 CLR(dev->flags, MPII_DF_HOT_SPARE); 1790 SET(dev->flags, MPII_DF_VOLUME_DISK | 1791 MPII_DF_HIDDEN); 1792 } 1793 break; 1794 case MPII_EVT_IR_CFG_ELEMENT_TYPE_HOT_SPARE: 1795 if (ce->reason_code == 1796 MPII_EVT_IR_CFG_ELEMENT_RC_HIDE) { 1797 /* there should be an underlying sas drive */ 1798 if (!(dev = mpii_find_dev(sc, 1799 lemtoh16(&ce->phys_disk_dev_handle)))) 1800 break; 1801 SET(dev->flags, MPII_DF_HOT_SPARE | 1802 MPII_DF_HIDDEN); 1803 } 1804 break; 1805 } 1806 } 1807 } 1808 1809 void 1810 mpii_event_sas(void *xsc) 1811 { 1812 struct mpii_softc *sc = xsc; 1813 struct mpii_rcb *rcb, *next; 1814 struct mpii_msg_event_reply *enp; 1815 struct mpii_evt_sas_tcl *tcl; 1816 struct mpii_evt_phy_entry *pe; 1817 struct mpii_device *dev; 1818 int i; 1819 u_int16_t handle; 1820 1821 mtx_enter(&sc->sc_evt_sas_mtx); 1822 rcb = SIMPLEQ_FIRST(&sc->sc_evt_sas_queue); 1823 if (rcb != NULL) { 1824 next = SIMPLEQ_NEXT(rcb, rcb_link); 1825 SIMPLEQ_REMOVE_HEAD(&sc->sc_evt_sas_queue, rcb_link); 1826 } 1827 mtx_leave(&sc->sc_evt_sas_mtx); 1828 1829 if (rcb == NULL) 1830 return; 1831 if (next != NULL) 1832 task_add(systq, &sc->sc_evt_sas_task); 1833 1834 enp = (struct mpii_msg_event_reply *)rcb->rcb_reply; 1835 switch (lemtoh16(&enp->event)) { 1836 case MPII_EVENT_SAS_DISCOVERY: 1837 mpii_event_discovery(sc, enp); 1838 goto done; 1839 case MPII_EVENT_SAS_TOPOLOGY_CHANGE_LIST: 1840 /* handle below */ 1841 break; 1842 default: 1843 panic("%s: unexpected event %#x in sas event queue", 1844 DEVNAME(sc), lemtoh16(&enp->event)); 1845 /* NOTREACHED */ 1846 } 1847 1848 tcl = (struct mpii_evt_sas_tcl *)(enp + 1); 1849 pe = (struct mpii_evt_phy_entry *)(tcl + 1); 1850 1851 for (i = 0; i < tcl->num_entries; i++, pe++) { 1852 switch (pe->phy_status & MPII_EVENT_SAS_TOPO_PS_RC_MASK) { 1853 case MPII_EVENT_SAS_TOPO_PS_RC_ADDED: 1854 handle = lemtoh16(&pe->dev_handle); 1855 if (mpii_find_dev(sc, handle)) { 1856 printf("%s: device %#x is already " 1857 "configured\n", DEVNAME(sc), handle); 1858 break; 1859 } 1860 1861 dev = malloc(sizeof(*dev), M_DEVBUF, M_WAITOK | M_ZERO); 1862 dev->slot = sc->sc_pd_id_start + tcl->start_phy_num + i; 1863 dev->dev_handle = handle; 1864 dev->phy_num = tcl->start_phy_num + i; 1865 if (tcl->enclosure_handle) 1866 dev->physical_port = tcl->physical_port; 1867 dev->enclosure = lemtoh16(&tcl->enclosure_handle); 1868 dev->expander = lemtoh16(&tcl->expander_handle); 1869 1870 if (mpii_insert_dev(sc, dev)) { 1871 free(dev, M_DEVBUF, sizeof *dev); 1872 break; 1873 } 1874 1875 if (sc->sc_scsibus != NULL) 1876 scsi_probe_target(sc->sc_scsibus, dev->slot); 1877 break; 1878 1879 case MPII_EVENT_SAS_TOPO_PS_RC_MISSING: 1880 dev = mpii_find_dev(sc, lemtoh16(&pe->dev_handle)); 1881 if (dev == NULL) 1882 break; 1883 1884 mpii_remove_dev(sc, dev); 1885 mpii_sas_remove_device(sc, dev->dev_handle); 1886 if (sc->sc_scsibus != NULL && 1887 !ISSET(dev->flags, MPII_DF_HIDDEN)) { 1888 scsi_activate(sc->sc_scsibus, dev->slot, -1, 1889 DVACT_DEACTIVATE); 1890 scsi_detach_target(sc->sc_scsibus, dev->slot, 1891 DETACH_FORCE); 1892 } 1893 1894 free(dev, M_DEVBUF, sizeof *dev); 1895 break; 1896 } 1897 } 1898 1899 done: 1900 mpii_event_done(sc, rcb); 1901 } 1902 1903 void 1904 mpii_event_discovery(struct mpii_softc *sc, struct mpii_msg_event_reply *enp) 1905 { 1906 struct mpii_evt_sas_discovery *esd = 1907 (struct mpii_evt_sas_discovery *)(enp + 1); 1908 1909 if (esd->reason_code == MPII_EVENT_SAS_DISC_REASON_CODE_COMPLETED) { 1910 if (esd->discovery_status != 0) { 1911 printf("%s: sas discovery completed with status %#x\n", 1912 DEVNAME(sc), esd->discovery_status); 1913 } 1914 1915 if (ISSET(sc->sc_flags, MPII_F_CONFIG_PENDING)) { 1916 CLR(sc->sc_flags, MPII_F_CONFIG_PENDING); 1917 config_pending_decr(); 1918 } 1919 } 1920 } 1921 1922 void 1923 mpii_event_process(struct mpii_softc *sc, struct mpii_rcb *rcb) 1924 { 1925 struct mpii_msg_event_reply *enp; 1926 1927 enp = (struct mpii_msg_event_reply *)rcb->rcb_reply; 1928 1929 DNPRINTF(MPII_D_EVT, "%s: mpii_event_process: %#x\n", DEVNAME(sc), 1930 letoh16(enp->event)); 1931 1932 switch (lemtoh16(&enp->event)) { 1933 case MPII_EVENT_EVENT_CHANGE: 1934 /* should be properly ignored */ 1935 break; 1936 case MPII_EVENT_SAS_DISCOVERY: 1937 case MPII_EVENT_SAS_TOPOLOGY_CHANGE_LIST: 1938 mtx_enter(&sc->sc_evt_sas_mtx); 1939 SIMPLEQ_INSERT_TAIL(&sc->sc_evt_sas_queue, rcb, rcb_link); 1940 mtx_leave(&sc->sc_evt_sas_mtx); 1941 task_add(systq, &sc->sc_evt_sas_task); 1942 return; 1943 case MPII_EVENT_SAS_DEVICE_STATUS_CHANGE: 1944 break; 1945 case MPII_EVENT_SAS_ENCL_DEVICE_STATUS_CHANGE: 1946 break; 1947 case MPII_EVENT_IR_VOLUME: { 1948 struct mpii_evt_ir_volume *evd = 1949 (struct mpii_evt_ir_volume *)(enp + 1); 1950 struct mpii_device *dev; 1951 #if NBIO > 0 1952 const char *vol_states[] = { 1953 BIOC_SVINVALID_S, 1954 BIOC_SVOFFLINE_S, 1955 BIOC_SVBUILDING_S, 1956 BIOC_SVONLINE_S, 1957 BIOC_SVDEGRADED_S, 1958 BIOC_SVONLINE_S, 1959 }; 1960 #endif 1961 1962 if (cold) 1963 break; 1964 KERNEL_LOCK(); 1965 dev = mpii_find_dev(sc, lemtoh16(&evd->vol_dev_handle)); 1966 KERNEL_UNLOCK(); 1967 if (dev == NULL) 1968 break; 1969 #if NBIO > 0 1970 if (evd->reason_code == MPII_EVENT_IR_VOL_RC_STATE_CHANGED) 1971 printf("%s: volume %d state changed from %s to %s\n", 1972 DEVNAME(sc), dev->slot - sc->sc_vd_id_low, 1973 vol_states[evd->prev_value], 1974 vol_states[evd->new_value]); 1975 #endif 1976 if (evd->reason_code == MPII_EVENT_IR_VOL_RC_STATUS_CHANGED && 1977 ISSET(evd->new_value, MPII_CFG_RAID_VOL_0_STATUS_RESYNC) && 1978 !ISSET(evd->prev_value, MPII_CFG_RAID_VOL_0_STATUS_RESYNC)) 1979 printf("%s: started resync on a volume %d\n", 1980 DEVNAME(sc), dev->slot - sc->sc_vd_id_low); 1981 } 1982 break; 1983 case MPII_EVENT_IR_PHYSICAL_DISK: 1984 break; 1985 case MPII_EVENT_IR_CONFIGURATION_CHANGE_LIST: 1986 mpii_event_raid(sc, enp); 1987 break; 1988 case MPII_EVENT_IR_OPERATION_STATUS: { 1989 struct mpii_evt_ir_status *evs = 1990 (struct mpii_evt_ir_status *)(enp + 1); 1991 struct mpii_device *dev; 1992 1993 KERNEL_LOCK(); 1994 dev = mpii_find_dev(sc, lemtoh16(&evs->vol_dev_handle)); 1995 KERNEL_UNLOCK(); 1996 if (dev != NULL && 1997 evs->operation == MPII_EVENT_IR_RAIDOP_RESYNC) 1998 dev->percent = evs->percent; 1999 break; 2000 } 2001 default: 2002 DNPRINTF(MPII_D_EVT, "%s: unhandled event 0x%02x\n", 2003 DEVNAME(sc), lemtoh16(&enp->event)); 2004 } 2005 2006 mpii_event_done(sc, rcb); 2007 } 2008 2009 void 2010 mpii_event_done(struct mpii_softc *sc, struct mpii_rcb *rcb) 2011 { 2012 struct mpii_msg_event_reply *enp = rcb->rcb_reply; 2013 2014 if (enp->ack_required) { 2015 mtx_enter(&sc->sc_evt_ack_mtx); 2016 SIMPLEQ_INSERT_TAIL(&sc->sc_evt_ack_queue, rcb, rcb_link); 2017 mtx_leave(&sc->sc_evt_ack_mtx); 2018 scsi_ioh_add(&sc->sc_evt_ack_handler); 2019 } else 2020 mpii_push_reply(sc, rcb); 2021 } 2022 2023 void 2024 mpii_sas_remove_device(struct mpii_softc *sc, u_int16_t handle) 2025 { 2026 struct mpii_msg_scsi_task_request *stq; 2027 struct mpii_msg_sas_oper_request *soq; 2028 struct mpii_ccb *ccb; 2029 2030 ccb = scsi_io_get(&sc->sc_iopool, 0); 2031 if (ccb == NULL) 2032 return; 2033 2034 stq = ccb->ccb_cmd; 2035 stq->function = MPII_FUNCTION_SCSI_TASK_MGMT; 2036 stq->task_type = MPII_SCSI_TASK_TARGET_RESET; 2037 htolem16(&stq->dev_handle, handle); 2038 2039 ccb->ccb_done = mpii_empty_done; 2040 mpii_wait(sc, ccb); 2041 2042 if (ccb->ccb_rcb != NULL) 2043 mpii_push_reply(sc, ccb->ccb_rcb); 2044 2045 /* reuse a ccb */ 2046 ccb->ccb_state = MPII_CCB_READY; 2047 ccb->ccb_rcb = NULL; 2048 2049 soq = ccb->ccb_cmd; 2050 memset(soq, 0, sizeof(*soq)); 2051 soq->function = MPII_FUNCTION_SAS_IO_UNIT_CONTROL; 2052 soq->operation = MPII_SAS_OP_REMOVE_DEVICE; 2053 htolem16(&soq->dev_handle, handle); 2054 2055 ccb->ccb_done = mpii_empty_done; 2056 mpii_wait(sc, ccb); 2057 if (ccb->ccb_rcb != NULL) 2058 mpii_push_reply(sc, ccb->ccb_rcb); 2059 2060 scsi_io_put(&sc->sc_iopool, ccb); 2061 } 2062 2063 int 2064 mpii_board_info(struct mpii_softc *sc) 2065 { 2066 struct mpii_msg_iocfacts_request ifq; 2067 struct mpii_msg_iocfacts_reply ifp; 2068 struct mpii_cfg_manufacturing_pg0 mpg; 2069 struct mpii_cfg_hdr hdr; 2070 2071 memset(&ifq, 0, sizeof(ifq)); 2072 memset(&ifp, 0, sizeof(ifp)); 2073 2074 ifq.function = MPII_FUNCTION_IOC_FACTS; 2075 2076 if (mpii_handshake_send(sc, &ifq, dwordsof(ifq)) != 0) { 2077 DNPRINTF(MPII_D_MISC, "%s: failed to request ioc facts\n", 2078 DEVNAME(sc)); 2079 return (1); 2080 } 2081 2082 if (mpii_handshake_recv(sc, &ifp, dwordsof(ifp)) != 0) { 2083 DNPRINTF(MPII_D_MISC, "%s: failed to receive ioc facts\n", 2084 DEVNAME(sc)); 2085 return (1); 2086 } 2087 2088 hdr.page_version = 0; 2089 hdr.page_length = sizeof(mpg) / 4; 2090 hdr.page_number = 0; 2091 hdr.page_type = MPII_CONFIG_REQ_PAGE_TYPE_MANUFACTURING; 2092 memset(&mpg, 0, sizeof(mpg)); 2093 if (mpii_req_cfg_page(sc, 0, MPII_PG_POLL, &hdr, 1, &mpg, 2094 sizeof(mpg)) != 0) { 2095 printf("%s: unable to fetch manufacturing page 0\n", 2096 DEVNAME(sc)); 2097 return (EINVAL); 2098 } 2099 2100 printf("%s: %s, firmware %u.%u.%u.%u%s, MPI %u.%u\n", DEVNAME(sc), 2101 mpg.board_name, ifp.fw_version_maj, ifp.fw_version_min, 2102 ifp.fw_version_unit, ifp.fw_version_dev, 2103 ISSET(sc->sc_flags, MPII_F_RAID) ? " IR" : "", 2104 ifp.msg_version_maj, ifp.msg_version_min); 2105 2106 return (0); 2107 } 2108 2109 int 2110 mpii_target_map(struct mpii_softc *sc) 2111 { 2112 struct mpii_cfg_hdr hdr; 2113 struct mpii_cfg_ioc_pg8 ipg; 2114 int flags, pad = 0; 2115 2116 hdr.page_version = 0; 2117 hdr.page_length = sizeof(ipg) / 4; 2118 hdr.page_number = 8; 2119 hdr.page_type = MPII_CONFIG_REQ_PAGE_TYPE_IOC; 2120 memset(&ipg, 0, sizeof(ipg)); 2121 if (mpii_req_cfg_page(sc, 0, MPII_PG_POLL, &hdr, 1, &ipg, 2122 sizeof(ipg)) != 0) { 2123 printf("%s: unable to fetch ioc page 8\n", 2124 DEVNAME(sc)); 2125 return (EINVAL); 2126 } 2127 2128 if (lemtoh16(&ipg.flags) & MPII_IOC_PG8_FLAGS_RESERVED_TARGETID_0) 2129 pad = 1; 2130 2131 flags = lemtoh16(&ipg.ir_volume_mapping_flags) & 2132 MPII_IOC_PG8_IRFLAGS_VOLUME_MAPPING_MODE_MASK; 2133 if (ISSET(sc->sc_flags, MPII_F_RAID)) { 2134 if (flags == MPII_IOC_PG8_IRFLAGS_LOW_VOLUME_MAPPING) { 2135 sc->sc_vd_id_low += pad; 2136 pad = sc->sc_max_volumes; /* for sc_pd_id_start */ 2137 } else 2138 sc->sc_vd_id_low = sc->sc_max_devices - 2139 sc->sc_max_volumes; 2140 } 2141 2142 sc->sc_pd_id_start += pad; 2143 2144 return (0); 2145 } 2146 2147 int 2148 mpii_req_cfg_header(struct mpii_softc *sc, u_int8_t type, u_int8_t number, 2149 u_int32_t address, int flags, void *p) 2150 { 2151 struct mpii_msg_config_request *cq; 2152 struct mpii_msg_config_reply *cp; 2153 struct mpii_ccb *ccb; 2154 struct mpii_cfg_hdr *hdr = p; 2155 struct mpii_ecfg_hdr *ehdr = p; 2156 int etype = 0; 2157 int rv = 0; 2158 2159 DNPRINTF(MPII_D_MISC, "%s: mpii_req_cfg_header type: %#x number: %x " 2160 "address: 0x%08x flags: 0x%b\n", DEVNAME(sc), type, number, 2161 address, flags, MPII_PG_FMT); 2162 2163 ccb = scsi_io_get(&sc->sc_iopool, 2164 ISSET(flags, MPII_PG_POLL) ? SCSI_NOSLEEP : 0); 2165 if (ccb == NULL) { 2166 DNPRINTF(MPII_D_MISC, "%s: mpii_cfg_header ccb_get\n", 2167 DEVNAME(sc)); 2168 return (1); 2169 } 2170 2171 if (ISSET(flags, MPII_PG_EXTENDED)) { 2172 etype = type; 2173 type = MPII_CONFIG_REQ_PAGE_TYPE_EXTENDED; 2174 } 2175 2176 cq = ccb->ccb_cmd; 2177 2178 cq->function = MPII_FUNCTION_CONFIG; 2179 2180 cq->action = MPII_CONFIG_REQ_ACTION_PAGE_HEADER; 2181 2182 cq->config_header.page_number = number; 2183 cq->config_header.page_type = type; 2184 cq->ext_page_type = etype; 2185 htolem32(&cq->page_address, address); 2186 htolem32(&cq->page_buffer.sg_hdr, MPII_SGE_FL_TYPE_SIMPLE | 2187 MPII_SGE_FL_LAST | MPII_SGE_FL_EOB | MPII_SGE_FL_EOL); 2188 2189 ccb->ccb_done = mpii_empty_done; 2190 if (ISSET(flags, MPII_PG_POLL)) { 2191 if (mpii_poll(sc, ccb) != 0) { 2192 DNPRINTF(MPII_D_MISC, "%s: mpii_cfg_header poll\n", 2193 DEVNAME(sc)); 2194 return (1); 2195 } 2196 } else 2197 mpii_wait(sc, ccb); 2198 2199 if (ccb->ccb_rcb == NULL) { 2200 scsi_io_put(&sc->sc_iopool, ccb); 2201 return (1); 2202 } 2203 cp = ccb->ccb_rcb->rcb_reply; 2204 2205 DNPRINTF(MPII_D_MISC, "%s: action: 0x%02x sgl_flags: 0x%02x " 2206 "msg_length: %d function: 0x%02x\n", DEVNAME(sc), cp->action, 2207 cp->sgl_flags, cp->msg_length, cp->function); 2208 DNPRINTF(MPII_D_MISC, "%s: ext_page_length: %d ext_page_type: 0x%02x " 2209 "msg_flags: 0x%02x\n", DEVNAME(sc), 2210 letoh16(cp->ext_page_length), cp->ext_page_type, 2211 cp->msg_flags); 2212 DNPRINTF(MPII_D_MISC, "%s: vp_id: 0x%02x vf_id: 0x%02x\n", DEVNAME(sc), 2213 cp->vp_id, cp->vf_id); 2214 DNPRINTF(MPII_D_MISC, "%s: ioc_status: 0x%04x\n", DEVNAME(sc), 2215 letoh16(cp->ioc_status)); 2216 DNPRINTF(MPII_D_MISC, "%s: ioc_loginfo: 0x%08x\n", DEVNAME(sc), 2217 letoh32(cp->ioc_loginfo)); 2218 DNPRINTF(MPII_D_MISC, "%s: page_version: 0x%02x page_length: %d " 2219 "page_number: 0x%02x page_type: 0x%02x\n", DEVNAME(sc), 2220 cp->config_header.page_version, 2221 cp->config_header.page_length, 2222 cp->config_header.page_number, 2223 cp->config_header.page_type); 2224 2225 if (lemtoh16(&cp->ioc_status) != MPII_IOCSTATUS_SUCCESS) 2226 rv = 1; 2227 else if (ISSET(flags, MPII_PG_EXTENDED)) { 2228 memset(ehdr, 0, sizeof(*ehdr)); 2229 ehdr->page_version = cp->config_header.page_version; 2230 ehdr->page_number = cp->config_header.page_number; 2231 ehdr->page_type = cp->config_header.page_type; 2232 ehdr->ext_page_length = cp->ext_page_length; 2233 ehdr->ext_page_type = cp->ext_page_type; 2234 } else 2235 *hdr = cp->config_header; 2236 2237 mpii_push_reply(sc, ccb->ccb_rcb); 2238 scsi_io_put(&sc->sc_iopool, ccb); 2239 2240 return (rv); 2241 } 2242 2243 int 2244 mpii_req_cfg_page(struct mpii_softc *sc, u_int32_t address, int flags, 2245 void *p, int read, void *page, size_t len) 2246 { 2247 struct mpii_msg_config_request *cq; 2248 struct mpii_msg_config_reply *cp; 2249 struct mpii_ccb *ccb; 2250 struct mpii_cfg_hdr *hdr = p; 2251 struct mpii_ecfg_hdr *ehdr = p; 2252 caddr_t kva; 2253 int page_length; 2254 int rv = 0; 2255 2256 DNPRINTF(MPII_D_MISC, "%s: mpii_cfg_page address: %d read: %d " 2257 "type: %x\n", DEVNAME(sc), address, read, hdr->page_type); 2258 2259 page_length = ISSET(flags, MPII_PG_EXTENDED) ? 2260 lemtoh16(&ehdr->ext_page_length) : hdr->page_length; 2261 2262 if (len > sc->sc_request_size - sizeof(*cq) || len < page_length * 4) 2263 return (1); 2264 2265 ccb = scsi_io_get(&sc->sc_iopool, 2266 ISSET(flags, MPII_PG_POLL) ? SCSI_NOSLEEP : 0); 2267 if (ccb == NULL) { 2268 DNPRINTF(MPII_D_MISC, "%s: mpii_cfg_page ccb_get\n", 2269 DEVNAME(sc)); 2270 return (1); 2271 } 2272 2273 cq = ccb->ccb_cmd; 2274 2275 cq->function = MPII_FUNCTION_CONFIG; 2276 2277 cq->action = (read ? MPII_CONFIG_REQ_ACTION_PAGE_READ_CURRENT : 2278 MPII_CONFIG_REQ_ACTION_PAGE_WRITE_CURRENT); 2279 2280 if (ISSET(flags, MPII_PG_EXTENDED)) { 2281 cq->config_header.page_version = ehdr->page_version; 2282 cq->config_header.page_number = ehdr->page_number; 2283 cq->config_header.page_type = ehdr->page_type; 2284 cq->ext_page_len = ehdr->ext_page_length; 2285 cq->ext_page_type = ehdr->ext_page_type; 2286 } else 2287 cq->config_header = *hdr; 2288 cq->config_header.page_type &= MPII_CONFIG_REQ_PAGE_TYPE_MASK; 2289 htolem32(&cq->page_address, address); 2290 htolem32(&cq->page_buffer.sg_hdr, MPII_SGE_FL_TYPE_SIMPLE | 2291 MPII_SGE_FL_LAST | MPII_SGE_FL_EOB | MPII_SGE_FL_EOL | 2292 MPII_SGE_FL_SIZE_64 | (page_length * 4) | 2293 (read ? MPII_SGE_FL_DIR_IN : MPII_SGE_FL_DIR_OUT)); 2294 2295 /* bounce the page via the request space to avoid more bus_dma games */ 2296 mpii_dvatosge(&cq->page_buffer, ccb->ccb_cmd_dva + 2297 sizeof(struct mpii_msg_config_request)); 2298 2299 kva = ccb->ccb_cmd; 2300 kva += sizeof(struct mpii_msg_config_request); 2301 2302 if (!read) 2303 memcpy(kva, page, len); 2304 2305 ccb->ccb_done = mpii_empty_done; 2306 if (ISSET(flags, MPII_PG_POLL)) { 2307 if (mpii_poll(sc, ccb) != 0) { 2308 DNPRINTF(MPII_D_MISC, "%s: mpii_cfg_header poll\n", 2309 DEVNAME(sc)); 2310 return (1); 2311 } 2312 } else 2313 mpii_wait(sc, ccb); 2314 2315 if (ccb->ccb_rcb == NULL) { 2316 scsi_io_put(&sc->sc_iopool, ccb); 2317 return (1); 2318 } 2319 cp = ccb->ccb_rcb->rcb_reply; 2320 2321 DNPRINTF(MPII_D_MISC, "%s: action: 0x%02x msg_length: %d " 2322 "function: 0x%02x\n", DEVNAME(sc), cp->action, cp->msg_length, 2323 cp->function); 2324 DNPRINTF(MPII_D_MISC, "%s: ext_page_length: %d ext_page_type: 0x%02x " 2325 "msg_flags: 0x%02x\n", DEVNAME(sc), 2326 letoh16(cp->ext_page_length), cp->ext_page_type, 2327 cp->msg_flags); 2328 DNPRINTF(MPII_D_MISC, "%s: vp_id: 0x%02x vf_id: 0x%02x\n", DEVNAME(sc), 2329 cp->vp_id, cp->vf_id); 2330 DNPRINTF(MPII_D_MISC, "%s: ioc_status: 0x%04x\n", DEVNAME(sc), 2331 letoh16(cp->ioc_status)); 2332 DNPRINTF(MPII_D_MISC, "%s: ioc_loginfo: 0x%08x\n", DEVNAME(sc), 2333 letoh32(cp->ioc_loginfo)); 2334 DNPRINTF(MPII_D_MISC, "%s: page_version: 0x%02x page_length: %d " 2335 "page_number: 0x%02x page_type: 0x%02x\n", DEVNAME(sc), 2336 cp->config_header.page_version, 2337 cp->config_header.page_length, 2338 cp->config_header.page_number, 2339 cp->config_header.page_type); 2340 2341 if (lemtoh16(&cp->ioc_status) != MPII_IOCSTATUS_SUCCESS) 2342 rv = 1; 2343 else if (read) 2344 memcpy(page, kva, len); 2345 2346 mpii_push_reply(sc, ccb->ccb_rcb); 2347 scsi_io_put(&sc->sc_iopool, ccb); 2348 2349 return (rv); 2350 } 2351 2352 struct mpii_rcb * 2353 mpii_reply(struct mpii_softc *sc, struct mpii_reply_descr *rdp) 2354 { 2355 struct mpii_rcb *rcb = NULL; 2356 u_int32_t rfid; 2357 2358 DNPRINTF(MPII_D_INTR, "%s: mpii_reply\n", DEVNAME(sc)); 2359 2360 if ((rdp->reply_flags & MPII_REPLY_DESCR_TYPE_MASK) == 2361 MPII_REPLY_DESCR_ADDRESS_REPLY) { 2362 rfid = (lemtoh32(&rdp->frame_addr) - 2363 (u_int32_t)MPII_DMA_DVA(sc->sc_replies)) / 2364 sc->sc_reply_size; 2365 2366 bus_dmamap_sync(sc->sc_dmat, 2367 MPII_DMA_MAP(sc->sc_replies), sc->sc_reply_size * rfid, 2368 sc->sc_reply_size, BUS_DMASYNC_POSTREAD); 2369 2370 rcb = &sc->sc_rcbs[rfid]; 2371 } 2372 2373 memset(rdp, 0xff, sizeof(*rdp)); 2374 2375 bus_dmamap_sync(sc->sc_dmat, MPII_DMA_MAP(sc->sc_reply_postq), 2376 8 * sc->sc_reply_post_host_index, 8, 2377 BUS_DMASYNC_POSTREAD | BUS_DMASYNC_POSTWRITE); 2378 2379 return (rcb); 2380 } 2381 2382 struct mpii_dmamem * 2383 mpii_dmamem_alloc(struct mpii_softc *sc, size_t size) 2384 { 2385 struct mpii_dmamem *mdm; 2386 int nsegs; 2387 2388 mdm = malloc(sizeof(*mdm), M_DEVBUF, M_NOWAIT | M_ZERO); 2389 if (mdm == NULL) 2390 return (NULL); 2391 2392 mdm->mdm_size = size; 2393 2394 if (bus_dmamap_create(sc->sc_dmat, size, 1, size, 0, 2395 BUS_DMA_NOWAIT | BUS_DMA_ALLOCNOW, &mdm->mdm_map) != 0) 2396 goto mdmfree; 2397 2398 if (bus_dmamem_alloc(sc->sc_dmat, size, PAGE_SIZE, 0, &mdm->mdm_seg, 2399 1, &nsegs, BUS_DMA_NOWAIT | BUS_DMA_ZERO) != 0) 2400 goto destroy; 2401 2402 if (bus_dmamem_map(sc->sc_dmat, &mdm->mdm_seg, nsegs, size, 2403 &mdm->mdm_kva, BUS_DMA_NOWAIT) != 0) 2404 goto free; 2405 2406 if (bus_dmamap_load(sc->sc_dmat, mdm->mdm_map, mdm->mdm_kva, size, 2407 NULL, BUS_DMA_NOWAIT) != 0) 2408 goto unmap; 2409 2410 return (mdm); 2411 2412 unmap: 2413 bus_dmamem_unmap(sc->sc_dmat, mdm->mdm_kva, size); 2414 free: 2415 bus_dmamem_free(sc->sc_dmat, &mdm->mdm_seg, 1); 2416 destroy: 2417 bus_dmamap_destroy(sc->sc_dmat, mdm->mdm_map); 2418 mdmfree: 2419 free(mdm, M_DEVBUF, sizeof *mdm); 2420 2421 return (NULL); 2422 } 2423 2424 void 2425 mpii_dmamem_free(struct mpii_softc *sc, struct mpii_dmamem *mdm) 2426 { 2427 DNPRINTF(MPII_D_MEM, "%s: mpii_dmamem_free %p\n", DEVNAME(sc), mdm); 2428 2429 bus_dmamap_unload(sc->sc_dmat, mdm->mdm_map); 2430 bus_dmamem_unmap(sc->sc_dmat, mdm->mdm_kva, mdm->mdm_size); 2431 bus_dmamem_free(sc->sc_dmat, &mdm->mdm_seg, 1); 2432 bus_dmamap_destroy(sc->sc_dmat, mdm->mdm_map); 2433 free(mdm, M_DEVBUF, sizeof *mdm); 2434 } 2435 2436 int 2437 mpii_insert_dev(struct mpii_softc *sc, struct mpii_device *dev) 2438 { 2439 int slot; /* initial hint */ 2440 2441 if (dev == NULL || dev->slot < 0) 2442 return (1); 2443 slot = dev->slot; 2444 2445 while (slot < sc->sc_max_devices && sc->sc_devs[slot] != NULL) 2446 slot++; 2447 2448 if (slot >= sc->sc_max_devices) 2449 return (1); 2450 2451 dev->slot = slot; 2452 sc->sc_devs[slot] = dev; 2453 2454 return (0); 2455 } 2456 2457 int 2458 mpii_remove_dev(struct mpii_softc *sc, struct mpii_device *dev) 2459 { 2460 int i; 2461 2462 if (dev == NULL) 2463 return (1); 2464 2465 for (i = 0; i < sc->sc_max_devices; i++) { 2466 if (sc->sc_devs[i] == NULL) 2467 continue; 2468 2469 if (sc->sc_devs[i]->dev_handle == dev->dev_handle) { 2470 sc->sc_devs[i] = NULL; 2471 return (0); 2472 } 2473 } 2474 2475 return (1); 2476 } 2477 2478 struct mpii_device * 2479 mpii_find_dev(struct mpii_softc *sc, u_int16_t handle) 2480 { 2481 int i; 2482 2483 for (i = 0; i < sc->sc_max_devices; i++) { 2484 if (sc->sc_devs[i] == NULL) 2485 continue; 2486 2487 if (sc->sc_devs[i]->dev_handle == handle) 2488 return (sc->sc_devs[i]); 2489 } 2490 2491 return (NULL); 2492 } 2493 2494 int 2495 mpii_alloc_ccbs(struct mpii_softc *sc) 2496 { 2497 struct mpii_ccb *ccb; 2498 u_int8_t *cmd; 2499 int i; 2500 2501 SIMPLEQ_INIT(&sc->sc_ccb_free); 2502 SIMPLEQ_INIT(&sc->sc_ccb_tmos); 2503 mtx_init(&sc->sc_ccb_free_mtx, IPL_BIO); 2504 mtx_init(&sc->sc_ccb_mtx, IPL_BIO); 2505 scsi_ioh_set(&sc->sc_ccb_tmo_handler, &sc->sc_iopool, 2506 mpii_scsi_cmd_tmo_handler, sc); 2507 2508 sc->sc_ccbs = mallocarray((sc->sc_max_cmds-1), sizeof(*ccb), 2509 M_DEVBUF, M_NOWAIT | M_ZERO); 2510 if (sc->sc_ccbs == NULL) { 2511 printf("%s: unable to allocate ccbs\n", DEVNAME(sc)); 2512 return (1); 2513 } 2514 2515 sc->sc_requests = mpii_dmamem_alloc(sc, 2516 sc->sc_request_size * sc->sc_max_cmds); 2517 if (sc->sc_requests == NULL) { 2518 printf("%s: unable to allocate ccb dmamem\n", DEVNAME(sc)); 2519 goto free_ccbs; 2520 } 2521 cmd = MPII_DMA_KVA(sc->sc_requests); 2522 2523 /* 2524 * we have sc->sc_max_cmds system request message 2525 * frames, but smid zero cannot be used. so we then 2526 * have (sc->sc_max_cmds - 1) number of ccbs 2527 */ 2528 for (i = 1; i < sc->sc_max_cmds; i++) { 2529 ccb = &sc->sc_ccbs[i - 1]; 2530 2531 if (bus_dmamap_create(sc->sc_dmat, MAXPHYS, sc->sc_max_sgl, 2532 MAXPHYS, 0, BUS_DMA_NOWAIT | BUS_DMA_ALLOCNOW, 2533 &ccb->ccb_dmamap) != 0) { 2534 printf("%s: unable to create dma map\n", DEVNAME(sc)); 2535 goto free_maps; 2536 } 2537 2538 ccb->ccb_sc = sc; 2539 htolem16(&ccb->ccb_smid, i); 2540 ccb->ccb_offset = sc->sc_request_size * i; 2541 2542 ccb->ccb_cmd = &cmd[ccb->ccb_offset]; 2543 ccb->ccb_cmd_dva = (u_int32_t)MPII_DMA_DVA(sc->sc_requests) + 2544 ccb->ccb_offset; 2545 2546 DNPRINTF(MPII_D_CCB, "%s: mpii_alloc_ccbs(%d) ccb: %p map: %p " 2547 "sc: %p smid: %#x offs: %#lx cmd: %p dva: %#lx\n", 2548 DEVNAME(sc), i, ccb, ccb->ccb_dmamap, ccb->ccb_sc, 2549 ccb->ccb_smid, ccb->ccb_offset, ccb->ccb_cmd, 2550 ccb->ccb_cmd_dva); 2551 2552 mpii_put_ccb(sc, ccb); 2553 } 2554 2555 scsi_iopool_init(&sc->sc_iopool, sc, mpii_get_ccb, mpii_put_ccb); 2556 2557 return (0); 2558 2559 free_maps: 2560 while ((ccb = mpii_get_ccb(sc)) != NULL) 2561 bus_dmamap_destroy(sc->sc_dmat, ccb->ccb_dmamap); 2562 2563 mpii_dmamem_free(sc, sc->sc_requests); 2564 free_ccbs: 2565 free(sc->sc_ccbs, M_DEVBUF, (sc->sc_max_cmds-1) * sizeof(*ccb)); 2566 2567 return (1); 2568 } 2569 2570 void 2571 mpii_put_ccb(void *cookie, void *io) 2572 { 2573 struct mpii_softc *sc = cookie; 2574 struct mpii_ccb *ccb = io; 2575 2576 DNPRINTF(MPII_D_CCB, "%s: mpii_put_ccb %p\n", DEVNAME(sc), ccb); 2577 2578 ccb->ccb_state = MPII_CCB_FREE; 2579 ccb->ccb_cookie = NULL; 2580 ccb->ccb_done = NULL; 2581 ccb->ccb_rcb = NULL; 2582 memset(ccb->ccb_cmd, 0, sc->sc_request_size); 2583 2584 KERNEL_UNLOCK(); 2585 mtx_enter(&sc->sc_ccb_free_mtx); 2586 SIMPLEQ_INSERT_HEAD(&sc->sc_ccb_free, ccb, ccb_link); 2587 mtx_leave(&sc->sc_ccb_free_mtx); 2588 KERNEL_LOCK(); 2589 } 2590 2591 void * 2592 mpii_get_ccb(void *cookie) 2593 { 2594 struct mpii_softc *sc = cookie; 2595 struct mpii_ccb *ccb; 2596 2597 KERNEL_UNLOCK(); 2598 2599 mtx_enter(&sc->sc_ccb_free_mtx); 2600 ccb = SIMPLEQ_FIRST(&sc->sc_ccb_free); 2601 if (ccb != NULL) { 2602 SIMPLEQ_REMOVE_HEAD(&sc->sc_ccb_free, ccb_link); 2603 ccb->ccb_state = MPII_CCB_READY; 2604 } 2605 mtx_leave(&sc->sc_ccb_free_mtx); 2606 2607 KERNEL_LOCK(); 2608 2609 DNPRINTF(MPII_D_CCB, "%s: mpii_get_ccb %p\n", DEVNAME(sc), ccb); 2610 2611 return (ccb); 2612 } 2613 2614 int 2615 mpii_alloc_replies(struct mpii_softc *sc) 2616 { 2617 DNPRINTF(MPII_D_MISC, "%s: mpii_alloc_replies\n", DEVNAME(sc)); 2618 2619 sc->sc_rcbs = mallocarray(sc->sc_num_reply_frames, 2620 sizeof(struct mpii_rcb), M_DEVBUF, M_NOWAIT); 2621 if (sc->sc_rcbs == NULL) 2622 return (1); 2623 2624 sc->sc_replies = mpii_dmamem_alloc(sc, sc->sc_reply_size * 2625 sc->sc_num_reply_frames); 2626 if (sc->sc_replies == NULL) { 2627 free(sc->sc_rcbs, M_DEVBUF, 2628 sc->sc_num_reply_frames * sizeof(struct mpii_rcb)); 2629 return (1); 2630 } 2631 2632 return (0); 2633 } 2634 2635 void 2636 mpii_push_replies(struct mpii_softc *sc) 2637 { 2638 struct mpii_rcb *rcb; 2639 caddr_t kva = MPII_DMA_KVA(sc->sc_replies); 2640 int i; 2641 2642 bus_dmamap_sync(sc->sc_dmat, MPII_DMA_MAP(sc->sc_replies), 2643 0, sc->sc_reply_size * sc->sc_num_reply_frames, 2644 BUS_DMASYNC_PREREAD); 2645 2646 for (i = 0; i < sc->sc_num_reply_frames; i++) { 2647 rcb = &sc->sc_rcbs[i]; 2648 2649 rcb->rcb_reply = kva + sc->sc_reply_size * i; 2650 rcb->rcb_reply_dva = (u_int32_t)MPII_DMA_DVA(sc->sc_replies) + 2651 sc->sc_reply_size * i; 2652 mpii_push_reply(sc, rcb); 2653 } 2654 } 2655 2656 void 2657 mpii_start(struct mpii_softc *sc, struct mpii_ccb *ccb) 2658 { 2659 struct mpii_request_header *rhp; 2660 struct mpii_request_descr descr; 2661 u_long *rdp = (u_long *)&descr; 2662 2663 DNPRINTF(MPII_D_RW, "%s: mpii_start %#lx\n", DEVNAME(sc), 2664 ccb->ccb_cmd_dva); 2665 2666 bus_dmamap_sync(sc->sc_dmat, MPII_DMA_MAP(sc->sc_requests), 2667 ccb->ccb_offset, sc->sc_request_size, 2668 BUS_DMASYNC_PREREAD | BUS_DMASYNC_PREWRITE); 2669 2670 ccb->ccb_state = MPII_CCB_QUEUED; 2671 2672 rhp = ccb->ccb_cmd; 2673 2674 memset(&descr, 0, sizeof(descr)); 2675 2676 switch (rhp->function) { 2677 case MPII_FUNCTION_SCSI_IO_REQUEST: 2678 descr.request_flags = MPII_REQ_DESCR_SCSI_IO; 2679 descr.dev_handle = htole16(ccb->ccb_dev_handle); 2680 break; 2681 case MPII_FUNCTION_SCSI_TASK_MGMT: 2682 descr.request_flags = MPII_REQ_DESCR_HIGH_PRIORITY; 2683 break; 2684 default: 2685 descr.request_flags = MPII_REQ_DESCR_DEFAULT; 2686 } 2687 2688 descr.vf_id = sc->sc_vf_id; 2689 descr.smid = ccb->ccb_smid; 2690 2691 DNPRINTF(MPII_D_RW, "%s: MPII_REQ_DESCR_POST_LOW (0x%08x) write " 2692 "0x%08lx\n", DEVNAME(sc), MPII_REQ_DESCR_POST_LOW, *rdp); 2693 2694 DNPRINTF(MPII_D_RW, "%s: MPII_REQ_DESCR_POST_HIGH (0x%08x) write " 2695 "0x%08lx\n", DEVNAME(sc), MPII_REQ_DESCR_POST_HIGH, *(rdp+1)); 2696 2697 #if defined(__LP64__) 2698 bus_space_write_raw_8(sc->sc_iot, sc->sc_ioh, 2699 MPII_REQ_DESCR_POST_LOW, *rdp); 2700 #else 2701 mtx_enter(&sc->sc_req_mtx); 2702 bus_space_write_raw_4(sc->sc_iot, sc->sc_ioh, 2703 MPII_REQ_DESCR_POST_LOW, rdp[0]); 2704 bus_space_barrier(sc->sc_iot, sc->sc_ioh, 2705 MPII_REQ_DESCR_POST_LOW, 8, BUS_SPACE_BARRIER_WRITE); 2706 2707 bus_space_write_raw_4(sc->sc_iot, sc->sc_ioh, 2708 MPII_REQ_DESCR_POST_HIGH, rdp[1]); 2709 bus_space_barrier(sc->sc_iot, sc->sc_ioh, 2710 MPII_REQ_DESCR_POST_LOW, 8, BUS_SPACE_BARRIER_WRITE); 2711 mtx_leave(&sc->sc_req_mtx); 2712 #endif 2713 } 2714 2715 int 2716 mpii_poll(struct mpii_softc *sc, struct mpii_ccb *ccb) 2717 { 2718 void (*done)(struct mpii_ccb *); 2719 void *cookie; 2720 int rv = 1; 2721 2722 DNPRINTF(MPII_D_INTR, "%s: mpii_poll\n", DEVNAME(sc)); 2723 2724 done = ccb->ccb_done; 2725 cookie = ccb->ccb_cookie; 2726 2727 ccb->ccb_done = mpii_poll_done; 2728 ccb->ccb_cookie = &rv; 2729 2730 mpii_start(sc, ccb); 2731 2732 while (rv == 1) { 2733 /* avoid excessive polling */ 2734 if (mpii_reply_waiting(sc)) 2735 mpii_intr(sc); 2736 else 2737 delay(10); 2738 } 2739 2740 ccb->ccb_cookie = cookie; 2741 done(ccb); 2742 2743 return (0); 2744 } 2745 2746 void 2747 mpii_poll_done(struct mpii_ccb *ccb) 2748 { 2749 int *rv = ccb->ccb_cookie; 2750 2751 *rv = 0; 2752 } 2753 2754 int 2755 mpii_alloc_queues(struct mpii_softc *sc) 2756 { 2757 u_int32_t *rfp; 2758 int i; 2759 2760 DNPRINTF(MPII_D_MISC, "%s: mpii_alloc_queues\n", DEVNAME(sc)); 2761 2762 sc->sc_reply_freeq = mpii_dmamem_alloc(sc, 2763 sc->sc_reply_free_qdepth * sizeof(*rfp)); 2764 if (sc->sc_reply_freeq == NULL) 2765 return (1); 2766 rfp = MPII_DMA_KVA(sc->sc_reply_freeq); 2767 for (i = 0; i < sc->sc_num_reply_frames; i++) { 2768 rfp[i] = (u_int32_t)MPII_DMA_DVA(sc->sc_replies) + 2769 sc->sc_reply_size * i; 2770 } 2771 2772 sc->sc_reply_postq = mpii_dmamem_alloc(sc, 2773 sc->sc_reply_post_qdepth * sizeof(struct mpii_reply_descr)); 2774 if (sc->sc_reply_postq == NULL) 2775 goto free_reply_freeq; 2776 sc->sc_reply_postq_kva = MPII_DMA_KVA(sc->sc_reply_postq); 2777 memset(sc->sc_reply_postq_kva, 0xff, sc->sc_reply_post_qdepth * 2778 sizeof(struct mpii_reply_descr)); 2779 2780 return (0); 2781 2782 free_reply_freeq: 2783 mpii_dmamem_free(sc, sc->sc_reply_freeq); 2784 return (1); 2785 } 2786 2787 void 2788 mpii_init_queues(struct mpii_softc *sc) 2789 { 2790 DNPRINTF(MPII_D_MISC, "%s: mpii_init_queues\n", DEVNAME(sc)); 2791 2792 sc->sc_reply_free_host_index = sc->sc_reply_free_qdepth - 1; 2793 sc->sc_reply_post_host_index = 0; 2794 mpii_write_reply_free(sc, sc->sc_reply_free_host_index); 2795 mpii_write_reply_post(sc, sc->sc_reply_post_host_index); 2796 } 2797 2798 void 2799 mpii_wait(struct mpii_softc *sc, struct mpii_ccb *ccb) 2800 { 2801 struct mutex mtx = MUTEX_INITIALIZER(IPL_BIO); 2802 void (*done)(struct mpii_ccb *); 2803 void *cookie; 2804 2805 done = ccb->ccb_done; 2806 cookie = ccb->ccb_cookie; 2807 2808 ccb->ccb_done = mpii_wait_done; 2809 ccb->ccb_cookie = &mtx; 2810 2811 /* XXX this will wait forever for the ccb to complete */ 2812 2813 mpii_start(sc, ccb); 2814 2815 mtx_enter(&mtx); 2816 while (ccb->ccb_cookie != NULL) 2817 msleep(ccb, &mtx, PRIBIO, "mpiiwait", 0); 2818 mtx_leave(&mtx); 2819 2820 ccb->ccb_cookie = cookie; 2821 done(ccb); 2822 } 2823 2824 void 2825 mpii_wait_done(struct mpii_ccb *ccb) 2826 { 2827 struct mutex *mtx = ccb->ccb_cookie; 2828 2829 mtx_enter(mtx); 2830 ccb->ccb_cookie = NULL; 2831 mtx_leave(mtx); 2832 2833 wakeup_one(ccb); 2834 } 2835 2836 void 2837 mpii_scsi_cmd(struct scsi_xfer *xs) 2838 { 2839 struct scsi_link *link = xs->sc_link; 2840 struct mpii_softc *sc = link->adapter_softc; 2841 struct mpii_ccb *ccb = xs->io; 2842 struct mpii_msg_scsi_io *io; 2843 struct mpii_device *dev; 2844 int ret; 2845 2846 DNPRINTF(MPII_D_CMD, "%s: mpii_scsi_cmd\n", DEVNAME(sc)); 2847 2848 if (xs->cmdlen > MPII_CDB_LEN) { 2849 DNPRINTF(MPII_D_CMD, "%s: CDB too big %d\n", 2850 DEVNAME(sc), xs->cmdlen); 2851 memset(&xs->sense, 0, sizeof(xs->sense)); 2852 xs->sense.error_code = SSD_ERRCODE_VALID | 0x70; 2853 xs->sense.flags = SKEY_ILLEGAL_REQUEST; 2854 xs->sense.add_sense_code = 0x20; 2855 xs->error = XS_SENSE; 2856 scsi_done(xs); 2857 return; 2858 } 2859 2860 if ((dev = sc->sc_devs[link->target]) == NULL) { 2861 /* device no longer exists */ 2862 xs->error = XS_SELTIMEOUT; 2863 scsi_done(xs); 2864 return; 2865 } 2866 2867 KERNEL_UNLOCK(); 2868 2869 DNPRINTF(MPII_D_CMD, "%s: ccb_smid: %d xs->flags: 0x%x\n", 2870 DEVNAME(sc), ccb->ccb_smid, xs->flags); 2871 2872 ccb->ccb_cookie = xs; 2873 ccb->ccb_done = mpii_scsi_cmd_done; 2874 ccb->ccb_dev_handle = dev->dev_handle; 2875 2876 io = ccb->ccb_cmd; 2877 memset(io, 0, sizeof(*io)); 2878 io->function = MPII_FUNCTION_SCSI_IO_REQUEST; 2879 io->sense_buffer_length = sizeof(xs->sense); 2880 io->sgl_offset0 = sizeof(struct mpii_msg_scsi_io) / 4; 2881 htolem16(&io->io_flags, xs->cmdlen); 2882 htolem16(&io->dev_handle, ccb->ccb_dev_handle); 2883 htobem16(&io->lun[0], link->lun); 2884 2885 switch (xs->flags & (SCSI_DATA_IN | SCSI_DATA_OUT)) { 2886 case SCSI_DATA_IN: 2887 io->direction = MPII_SCSIIO_DIR_READ; 2888 break; 2889 case SCSI_DATA_OUT: 2890 io->direction = MPII_SCSIIO_DIR_WRITE; 2891 break; 2892 default: 2893 io->direction = MPII_SCSIIO_DIR_NONE; 2894 break; 2895 } 2896 2897 io->tagging = MPII_SCSIIO_ATTR_SIMPLE_Q; 2898 2899 memcpy(io->cdb, xs->cmd, xs->cmdlen); 2900 2901 htolem32(&io->data_length, xs->datalen); 2902 2903 /* sense data is at the end of a request */ 2904 htolem32(&io->sense_buffer_low_address, ccb->ccb_cmd_dva + 2905 sc->sc_request_size - sizeof(struct scsi_sense_data)); 2906 2907 if (ISSET(sc->sc_flags, MPII_F_SAS3)) 2908 ret = mpii_load_xs_sas3(ccb); 2909 else 2910 ret = mpii_load_xs(ccb); 2911 2912 if (ret != 0) { 2913 xs->error = XS_DRIVER_STUFFUP; 2914 goto done; 2915 } 2916 2917 timeout_set(&xs->stimeout, mpii_scsi_cmd_tmo, ccb); 2918 if (xs->flags & SCSI_POLL) { 2919 if (mpii_poll(sc, ccb) != 0) { 2920 xs->error = XS_DRIVER_STUFFUP; 2921 goto done; 2922 } 2923 } else { 2924 timeout_add_msec(&xs->stimeout, xs->timeout); 2925 mpii_start(sc, ccb); 2926 } 2927 2928 KERNEL_LOCK(); 2929 return; 2930 2931 done: 2932 KERNEL_LOCK(); 2933 scsi_done(xs); 2934 } 2935 2936 void 2937 mpii_scsi_cmd_tmo(void *xccb) 2938 { 2939 struct mpii_ccb *ccb = xccb; 2940 struct mpii_softc *sc = ccb->ccb_sc; 2941 2942 printf("%s: mpii_scsi_cmd_tmo\n", DEVNAME(sc)); 2943 2944 mtx_enter(&sc->sc_ccb_mtx); 2945 if (ccb->ccb_state == MPII_CCB_QUEUED) { 2946 ccb->ccb_state = MPII_CCB_TIMEOUT; 2947 SIMPLEQ_INSERT_HEAD(&sc->sc_ccb_tmos, ccb, ccb_link); 2948 } 2949 mtx_leave(&sc->sc_ccb_mtx); 2950 2951 scsi_ioh_add(&sc->sc_ccb_tmo_handler); 2952 } 2953 2954 void 2955 mpii_scsi_cmd_tmo_handler(void *cookie, void *io) 2956 { 2957 struct mpii_softc *sc = cookie; 2958 struct mpii_ccb *tccb = io; 2959 struct mpii_ccb *ccb; 2960 struct mpii_msg_scsi_task_request *stq; 2961 2962 mtx_enter(&sc->sc_ccb_mtx); 2963 ccb = SIMPLEQ_FIRST(&sc->sc_ccb_tmos); 2964 if (ccb != NULL) { 2965 SIMPLEQ_REMOVE_HEAD(&sc->sc_ccb_tmos, ccb_link); 2966 ccb->ccb_state = MPII_CCB_QUEUED; 2967 } 2968 /* should remove any other ccbs for the same dev handle */ 2969 mtx_leave(&sc->sc_ccb_mtx); 2970 2971 if (ccb == NULL) { 2972 scsi_io_put(&sc->sc_iopool, tccb); 2973 return; 2974 } 2975 2976 stq = tccb->ccb_cmd; 2977 stq->function = MPII_FUNCTION_SCSI_TASK_MGMT; 2978 stq->task_type = MPII_SCSI_TASK_TARGET_RESET; 2979 htolem16(&stq->dev_handle, ccb->ccb_dev_handle); 2980 2981 tccb->ccb_done = mpii_scsi_cmd_tmo_done; 2982 mpii_start(sc, tccb); 2983 } 2984 2985 void 2986 mpii_scsi_cmd_tmo_done(struct mpii_ccb *tccb) 2987 { 2988 mpii_scsi_cmd_tmo_handler(tccb->ccb_sc, tccb); 2989 } 2990 2991 void 2992 mpii_scsi_cmd_done(struct mpii_ccb *ccb) 2993 { 2994 struct mpii_ccb *tccb; 2995 struct mpii_msg_scsi_io_error *sie; 2996 struct mpii_softc *sc = ccb->ccb_sc; 2997 struct scsi_xfer *xs = ccb->ccb_cookie; 2998 struct scsi_sense_data *sense; 2999 bus_dmamap_t dmap = ccb->ccb_dmamap; 3000 3001 timeout_del(&xs->stimeout); 3002 mtx_enter(&sc->sc_ccb_mtx); 3003 if (ccb->ccb_state == MPII_CCB_TIMEOUT) { 3004 /* ENOSIMPLEQ_REMOVE :( */ 3005 if (ccb == SIMPLEQ_FIRST(&sc->sc_ccb_tmos)) 3006 SIMPLEQ_REMOVE_HEAD(&sc->sc_ccb_tmos, ccb_link); 3007 else { 3008 SIMPLEQ_FOREACH(tccb, &sc->sc_ccb_tmos, ccb_link) { 3009 if (SIMPLEQ_NEXT(tccb, ccb_link) == ccb) { 3010 SIMPLEQ_REMOVE_AFTER(&sc->sc_ccb_tmos, 3011 tccb, ccb_link); 3012 break; 3013 } 3014 } 3015 } 3016 } 3017 3018 ccb->ccb_state = MPII_CCB_READY; 3019 mtx_leave(&sc->sc_ccb_mtx); 3020 3021 if (xs->datalen != 0) { 3022 bus_dmamap_sync(sc->sc_dmat, dmap, 0, dmap->dm_mapsize, 3023 (xs->flags & SCSI_DATA_IN) ? BUS_DMASYNC_POSTREAD : 3024 BUS_DMASYNC_POSTWRITE); 3025 3026 bus_dmamap_unload(sc->sc_dmat, dmap); 3027 } 3028 3029 xs->error = XS_NOERROR; 3030 xs->resid = 0; 3031 3032 if (ccb->ccb_rcb == NULL) { 3033 /* no scsi error, we're ok so drop out early */ 3034 xs->status = SCSI_OK; 3035 goto done; 3036 } 3037 3038 sie = ccb->ccb_rcb->rcb_reply; 3039 3040 DNPRINTF(MPII_D_CMD, "%s: mpii_scsi_cmd_done xs cmd: 0x%02x len: %d " 3041 "flags 0x%x\n", DEVNAME(sc), xs->cmd->opcode, xs->datalen, 3042 xs->flags); 3043 DNPRINTF(MPII_D_CMD, "%s: dev_handle: %d msg_length: %d " 3044 "function: 0x%02x\n", DEVNAME(sc), letoh16(sie->dev_handle), 3045 sie->msg_length, sie->function); 3046 DNPRINTF(MPII_D_CMD, "%s: vp_id: 0x%02x vf_id: 0x%02x\n", DEVNAME(sc), 3047 sie->vp_id, sie->vf_id); 3048 DNPRINTF(MPII_D_CMD, "%s: scsi_status: 0x%02x scsi_state: 0x%02x " 3049 "ioc_status: 0x%04x\n", DEVNAME(sc), sie->scsi_status, 3050 sie->scsi_state, letoh16(sie->ioc_status)); 3051 DNPRINTF(MPII_D_CMD, "%s: ioc_loginfo: 0x%08x\n", DEVNAME(sc), 3052 letoh32(sie->ioc_loginfo)); 3053 DNPRINTF(MPII_D_CMD, "%s: transfer_count: %d\n", DEVNAME(sc), 3054 letoh32(sie->transfer_count)); 3055 DNPRINTF(MPII_D_CMD, "%s: sense_count: %d\n", DEVNAME(sc), 3056 letoh32(sie->sense_count)); 3057 DNPRINTF(MPII_D_CMD, "%s: response_info: 0x%08x\n", DEVNAME(sc), 3058 letoh32(sie->response_info)); 3059 DNPRINTF(MPII_D_CMD, "%s: task_tag: 0x%04x\n", DEVNAME(sc), 3060 letoh16(sie->task_tag)); 3061 DNPRINTF(MPII_D_CMD, "%s: bidirectional_transfer_count: 0x%08x\n", 3062 DEVNAME(sc), letoh32(sie->bidirectional_transfer_count)); 3063 3064 if (sie->scsi_state & MPII_SCSIIO_STATE_NO_SCSI_STATUS) 3065 xs->status = SCSI_TERMINATED; 3066 else 3067 xs->status = sie->scsi_status; 3068 xs->resid = 0; 3069 3070 switch (lemtoh16(&sie->ioc_status) & MPII_IOCSTATUS_MASK) { 3071 case MPII_IOCSTATUS_SCSI_DATA_UNDERRUN: 3072 xs->resid = xs->datalen - lemtoh32(&sie->transfer_count); 3073 /* FALLTHROUGH */ 3074 3075 case MPII_IOCSTATUS_SUCCESS: 3076 case MPII_IOCSTATUS_SCSI_RECOVERED_ERROR: 3077 switch (xs->status) { 3078 case SCSI_OK: 3079 xs->error = XS_NOERROR; 3080 break; 3081 3082 case SCSI_CHECK: 3083 xs->error = XS_SENSE; 3084 break; 3085 3086 case SCSI_BUSY: 3087 case SCSI_QUEUE_FULL: 3088 xs->error = XS_BUSY; 3089 break; 3090 3091 default: 3092 xs->error = XS_DRIVER_STUFFUP; 3093 } 3094 break; 3095 3096 case MPII_IOCSTATUS_BUSY: 3097 case MPII_IOCSTATUS_INSUFFICIENT_RESOURCES: 3098 xs->error = XS_BUSY; 3099 break; 3100 3101 case MPII_IOCSTATUS_SCSI_IOC_TERMINATED: 3102 case MPII_IOCSTATUS_SCSI_TASK_TERMINATED: 3103 xs->error = XS_RESET; 3104 break; 3105 3106 case MPII_IOCSTATUS_SCSI_INVALID_DEVHANDLE: 3107 case MPII_IOCSTATUS_SCSI_DEVICE_NOT_THERE: 3108 xs->error = XS_SELTIMEOUT; 3109 break; 3110 3111 default: 3112 xs->error = XS_DRIVER_STUFFUP; 3113 break; 3114 } 3115 3116 sense = (struct scsi_sense_data *)((caddr_t)ccb->ccb_cmd + 3117 sc->sc_request_size - sizeof(*sense)); 3118 if (sie->scsi_state & MPII_SCSIIO_STATE_AUTOSENSE_VALID) 3119 memcpy(&xs->sense, sense, sizeof(xs->sense)); 3120 3121 DNPRINTF(MPII_D_CMD, "%s: xs err: %d status: %#x\n", DEVNAME(sc), 3122 xs->error, xs->status); 3123 3124 mpii_push_reply(sc, ccb->ccb_rcb); 3125 done: 3126 KERNEL_LOCK(); 3127 scsi_done(xs); 3128 KERNEL_UNLOCK(); 3129 } 3130 3131 int 3132 mpii_scsi_ioctl(struct scsi_link *link, u_long cmd, caddr_t addr, int flag) 3133 { 3134 struct mpii_softc *sc = (struct mpii_softc *)link->adapter_softc; 3135 struct mpii_device *dev = sc->sc_devs[link->target]; 3136 3137 DNPRINTF(MPII_D_IOCTL, "%s: mpii_scsi_ioctl\n", DEVNAME(sc)); 3138 3139 switch (cmd) { 3140 case DIOCGCACHE: 3141 case DIOCSCACHE: 3142 if (dev != NULL && ISSET(dev->flags, MPII_DF_VOLUME)) { 3143 return (mpii_ioctl_cache(link, cmd, 3144 (struct dk_cache *)addr)); 3145 } 3146 break; 3147 3148 default: 3149 if (sc->sc_ioctl) 3150 return (sc->sc_ioctl(link->adapter_softc, cmd, addr)); 3151 3152 break; 3153 } 3154 3155 return (ENOTTY); 3156 } 3157 3158 int 3159 mpii_ioctl_cache(struct scsi_link *link, u_long cmd, struct dk_cache *dc) 3160 { 3161 struct mpii_softc *sc = (struct mpii_softc *)link->adapter_softc; 3162 struct mpii_device *dev = sc->sc_devs[link->target]; 3163 struct mpii_cfg_raid_vol_pg0 *vpg; 3164 struct mpii_msg_raid_action_request *req; 3165 struct mpii_msg_raid_action_reply *rep; 3166 struct mpii_cfg_hdr hdr; 3167 struct mpii_ccb *ccb; 3168 u_int32_t addr = MPII_CFG_RAID_VOL_ADDR_HANDLE | dev->dev_handle; 3169 size_t pagelen; 3170 int rv = 0; 3171 int enabled; 3172 3173 if (mpii_req_cfg_header(sc, MPII_CONFIG_REQ_PAGE_TYPE_RAID_VOL, 0, 3174 addr, MPII_PG_POLL, &hdr) != 0) 3175 return (EINVAL); 3176 3177 pagelen = hdr.page_length * 4; 3178 vpg = malloc(pagelen, M_TEMP, M_WAITOK | M_CANFAIL | M_ZERO); 3179 if (vpg == NULL) 3180 return (ENOMEM); 3181 3182 if (mpii_req_cfg_page(sc, addr, MPII_PG_POLL, &hdr, 1, 3183 vpg, pagelen) != 0) { 3184 rv = EINVAL; 3185 goto done; 3186 } 3187 3188 enabled = ((lemtoh16(&vpg->volume_settings) & 3189 MPII_CFG_RAID_VOL_0_SETTINGS_CACHE_MASK) == 3190 MPII_CFG_RAID_VOL_0_SETTINGS_CACHE_ENABLED) ? 1 : 0; 3191 3192 if (cmd == DIOCGCACHE) { 3193 dc->wrcache = enabled; 3194 dc->rdcache = 0; 3195 goto done; 3196 } /* else DIOCSCACHE */ 3197 3198 if (dc->rdcache) { 3199 rv = EOPNOTSUPP; 3200 goto done; 3201 } 3202 3203 if (((dc->wrcache) ? 1 : 0) == enabled) 3204 goto done; 3205 3206 ccb = scsi_io_get(&sc->sc_iopool, SCSI_POLL); 3207 if (ccb == NULL) { 3208 rv = ENOMEM; 3209 goto done; 3210 } 3211 3212 ccb->ccb_done = mpii_empty_done; 3213 3214 req = ccb->ccb_cmd; 3215 memset(req, 0, sizeof(*req)); 3216 req->function = MPII_FUNCTION_RAID_ACTION; 3217 req->action = MPII_RAID_ACTION_CHANGE_VOL_WRITE_CACHE; 3218 htolem16(&req->vol_dev_handle, dev->dev_handle); 3219 htolem32(&req->action_data, dc->wrcache ? 3220 MPII_RAID_VOL_WRITE_CACHE_ENABLE : 3221 MPII_RAID_VOL_WRITE_CACHE_DISABLE); 3222 3223 if (mpii_poll(sc, ccb) != 0) { 3224 rv = EIO; 3225 goto done; 3226 } 3227 3228 if (ccb->ccb_rcb != NULL) { 3229 rep = ccb->ccb_rcb->rcb_reply; 3230 if ((rep->ioc_status != MPII_IOCSTATUS_SUCCESS) || 3231 ((rep->action_data[0] & 3232 MPII_RAID_VOL_WRITE_CACHE_MASK) != 3233 (dc->wrcache ? MPII_RAID_VOL_WRITE_CACHE_ENABLE : 3234 MPII_RAID_VOL_WRITE_CACHE_DISABLE))) 3235 rv = EINVAL; 3236 mpii_push_reply(sc, ccb->ccb_rcb); 3237 } 3238 3239 scsi_io_put(&sc->sc_iopool, ccb); 3240 3241 done: 3242 free(vpg, M_TEMP, pagelen); 3243 return (rv); 3244 } 3245 3246 #if NBIO > 0 3247 int 3248 mpii_ioctl(struct device *dev, u_long cmd, caddr_t addr) 3249 { 3250 struct mpii_softc *sc = (struct mpii_softc *)dev; 3251 int error = 0; 3252 3253 DNPRINTF(MPII_D_IOCTL, "%s: mpii_ioctl ", DEVNAME(sc)); 3254 3255 switch (cmd) { 3256 case BIOCINQ: 3257 DNPRINTF(MPII_D_IOCTL, "inq\n"); 3258 error = mpii_ioctl_inq(sc, (struct bioc_inq *)addr); 3259 break; 3260 case BIOCVOL: 3261 DNPRINTF(MPII_D_IOCTL, "vol\n"); 3262 error = mpii_ioctl_vol(sc, (struct bioc_vol *)addr); 3263 break; 3264 case BIOCDISK: 3265 DNPRINTF(MPII_D_IOCTL, "disk\n"); 3266 error = mpii_ioctl_disk(sc, (struct bioc_disk *)addr); 3267 break; 3268 default: 3269 DNPRINTF(MPII_D_IOCTL, " invalid ioctl\n"); 3270 error = EINVAL; 3271 } 3272 3273 return (error); 3274 } 3275 3276 int 3277 mpii_ioctl_inq(struct mpii_softc *sc, struct bioc_inq *bi) 3278 { 3279 int i; 3280 3281 DNPRINTF(MPII_D_IOCTL, "%s: mpii_ioctl_inq\n", DEVNAME(sc)); 3282 3283 strlcpy(bi->bi_dev, DEVNAME(sc), sizeof(bi->bi_dev)); 3284 for (i = 0; i < sc->sc_max_devices; i++) 3285 if (sc->sc_devs[i] && 3286 ISSET(sc->sc_devs[i]->flags, MPII_DF_VOLUME)) 3287 bi->bi_novol++; 3288 return (0); 3289 } 3290 3291 int 3292 mpii_ioctl_vol(struct mpii_softc *sc, struct bioc_vol *bv) 3293 { 3294 struct mpii_cfg_raid_vol_pg0 *vpg; 3295 struct mpii_cfg_hdr hdr; 3296 struct mpii_device *dev; 3297 struct scsi_link *lnk; 3298 struct device *scdev; 3299 size_t pagelen; 3300 u_int16_t volh; 3301 int rv, hcnt = 0; 3302 3303 DNPRINTF(MPII_D_IOCTL, "%s: mpii_ioctl_vol %d\n", 3304 DEVNAME(sc), bv->bv_volid); 3305 3306 if ((dev = mpii_find_vol(sc, bv->bv_volid)) == NULL) 3307 return (ENODEV); 3308 volh = dev->dev_handle; 3309 3310 if (mpii_req_cfg_header(sc, MPII_CONFIG_REQ_PAGE_TYPE_RAID_VOL, 0, 3311 MPII_CFG_RAID_VOL_ADDR_HANDLE | volh, 0, &hdr) != 0) { 3312 printf("%s: unable to fetch header for raid volume page 0\n", 3313 DEVNAME(sc)); 3314 return (EINVAL); 3315 } 3316 3317 pagelen = hdr.page_length * 4; 3318 vpg = malloc(pagelen, M_TEMP, M_WAITOK | M_CANFAIL | M_ZERO); 3319 if (vpg == NULL) { 3320 printf("%s: unable to allocate space for raid " 3321 "volume page 0\n", DEVNAME(sc)); 3322 return (ENOMEM); 3323 } 3324 3325 if (mpii_req_cfg_page(sc, MPII_CFG_RAID_VOL_ADDR_HANDLE | volh, 0, 3326 &hdr, 1, vpg, pagelen) != 0) { 3327 printf("%s: unable to fetch raid volume page 0\n", 3328 DEVNAME(sc)); 3329 free(vpg, M_TEMP, pagelen); 3330 return (EINVAL); 3331 } 3332 3333 switch (vpg->volume_state) { 3334 case MPII_CFG_RAID_VOL_0_STATE_ONLINE: 3335 case MPII_CFG_RAID_VOL_0_STATE_OPTIMAL: 3336 bv->bv_status = BIOC_SVONLINE; 3337 break; 3338 case MPII_CFG_RAID_VOL_0_STATE_DEGRADED: 3339 if (ISSET(lemtoh32(&vpg->volume_status), 3340 MPII_CFG_RAID_VOL_0_STATUS_RESYNC)) { 3341 bv->bv_status = BIOC_SVREBUILD; 3342 bv->bv_percent = dev->percent; 3343 } else 3344 bv->bv_status = BIOC_SVDEGRADED; 3345 break; 3346 case MPII_CFG_RAID_VOL_0_STATE_FAILED: 3347 bv->bv_status = BIOC_SVOFFLINE; 3348 break; 3349 case MPII_CFG_RAID_VOL_0_STATE_INITIALIZING: 3350 bv->bv_status = BIOC_SVBUILDING; 3351 break; 3352 case MPII_CFG_RAID_VOL_0_STATE_MISSING: 3353 default: 3354 bv->bv_status = BIOC_SVINVALID; 3355 break; 3356 } 3357 3358 switch (vpg->volume_type) { 3359 case MPII_CFG_RAID_VOL_0_TYPE_RAID0: 3360 bv->bv_level = 0; 3361 break; 3362 case MPII_CFG_RAID_VOL_0_TYPE_RAID1: 3363 bv->bv_level = 1; 3364 break; 3365 case MPII_CFG_RAID_VOL_0_TYPE_RAID1E: 3366 case MPII_CFG_RAID_VOL_0_TYPE_RAID10: 3367 bv->bv_level = 10; 3368 break; 3369 default: 3370 bv->bv_level = -1; 3371 } 3372 3373 if ((rv = mpii_bio_hs(sc, NULL, 0, vpg->hot_spare_pool, &hcnt)) != 0) { 3374 free(vpg, M_TEMP, pagelen); 3375 return (rv); 3376 } 3377 3378 bv->bv_nodisk = vpg->num_phys_disks + hcnt; 3379 3380 bv->bv_size = letoh64(vpg->max_lba) * lemtoh16(&vpg->block_size); 3381 3382 lnk = scsi_get_link(sc->sc_scsibus, dev->slot, 0); 3383 if (lnk != NULL) { 3384 scdev = lnk->device_softc; 3385 strlcpy(bv->bv_dev, scdev->dv_xname, sizeof(bv->bv_dev)); 3386 } 3387 3388 free(vpg, M_TEMP, pagelen); 3389 return (0); 3390 } 3391 3392 int 3393 mpii_ioctl_disk(struct mpii_softc *sc, struct bioc_disk *bd) 3394 { 3395 struct mpii_cfg_raid_vol_pg0 *vpg; 3396 struct mpii_cfg_raid_vol_pg0_physdisk *pd; 3397 struct mpii_cfg_hdr hdr; 3398 struct mpii_device *dev; 3399 size_t pagelen; 3400 u_int16_t volh; 3401 u_int8_t dn; 3402 3403 DNPRINTF(MPII_D_IOCTL, "%s: mpii_ioctl_disk %d/%d\n", 3404 DEVNAME(sc), bd->bd_volid, bd->bd_diskid); 3405 3406 if ((dev = mpii_find_vol(sc, bd->bd_volid)) == NULL) 3407 return (ENODEV); 3408 volh = dev->dev_handle; 3409 3410 if (mpii_req_cfg_header(sc, MPII_CONFIG_REQ_PAGE_TYPE_RAID_VOL, 0, 3411 MPII_CFG_RAID_VOL_ADDR_HANDLE | volh, 0, &hdr) != 0) { 3412 printf("%s: unable to fetch header for raid volume page 0\n", 3413 DEVNAME(sc)); 3414 return (EINVAL); 3415 } 3416 3417 pagelen = hdr.page_length * 4; 3418 vpg = malloc(pagelen, M_TEMP, M_WAITOK | M_CANFAIL | M_ZERO); 3419 if (vpg == NULL) { 3420 printf("%s: unable to allocate space for raid " 3421 "volume page 0\n", DEVNAME(sc)); 3422 return (ENOMEM); 3423 } 3424 3425 if (mpii_req_cfg_page(sc, MPII_CFG_RAID_VOL_ADDR_HANDLE | volh, 0, 3426 &hdr, 1, vpg, pagelen) != 0) { 3427 printf("%s: unable to fetch raid volume page 0\n", 3428 DEVNAME(sc)); 3429 free(vpg, M_TEMP, pagelen); 3430 return (EINVAL); 3431 } 3432 3433 if (bd->bd_diskid >= vpg->num_phys_disks) { 3434 int nvdsk = vpg->num_phys_disks; 3435 int hsmap = vpg->hot_spare_pool; 3436 3437 free(vpg, M_TEMP, pagelen); 3438 return (mpii_bio_hs(sc, bd, nvdsk, hsmap, NULL)); 3439 } 3440 3441 pd = (struct mpii_cfg_raid_vol_pg0_physdisk *)(vpg + 1) + 3442 bd->bd_diskid; 3443 dn = pd->phys_disk_num; 3444 3445 free(vpg, M_TEMP, pagelen); 3446 return (mpii_bio_disk(sc, bd, dn)); 3447 } 3448 3449 int 3450 mpii_bio_hs(struct mpii_softc *sc, struct bioc_disk *bd, int nvdsk, 3451 int hsmap, int *hscnt) 3452 { 3453 struct mpii_cfg_raid_config_pg0 *cpg; 3454 struct mpii_raid_config_element *el; 3455 struct mpii_ecfg_hdr ehdr; 3456 size_t pagelen; 3457 int i, nhs = 0; 3458 3459 if (bd) 3460 DNPRINTF(MPII_D_IOCTL, "%s: mpii_bio_hs %d\n", DEVNAME(sc), 3461 bd->bd_diskid - nvdsk); 3462 else 3463 DNPRINTF(MPII_D_IOCTL, "%s: mpii_bio_hs\n", DEVNAME(sc)); 3464 3465 if (mpii_req_cfg_header(sc, MPII_CONFIG_REQ_PAGE_TYPE_RAID_CONFIG, 3466 0, MPII_CFG_RAID_CONFIG_ACTIVE_CONFIG, MPII_PG_EXTENDED, 3467 &ehdr) != 0) { 3468 printf("%s: unable to fetch header for raid config page 0\n", 3469 DEVNAME(sc)); 3470 return (EINVAL); 3471 } 3472 3473 pagelen = lemtoh16(&ehdr.ext_page_length) * 4; 3474 cpg = malloc(pagelen, M_TEMP, M_WAITOK | M_CANFAIL | M_ZERO); 3475 if (cpg == NULL) { 3476 printf("%s: unable to allocate space for raid config page 0\n", 3477 DEVNAME(sc)); 3478 return (ENOMEM); 3479 } 3480 3481 if (mpii_req_cfg_page(sc, MPII_CFG_RAID_CONFIG_ACTIVE_CONFIG, 3482 MPII_PG_EXTENDED, &ehdr, 1, cpg, pagelen) != 0) { 3483 printf("%s: unable to fetch raid config page 0\n", 3484 DEVNAME(sc)); 3485 free(cpg, M_TEMP, pagelen); 3486 return (EINVAL); 3487 } 3488 3489 el = (struct mpii_raid_config_element *)(cpg + 1); 3490 for (i = 0; i < cpg->num_elements; i++, el++) { 3491 if (ISSET(lemtoh16(&el->element_flags), 3492 MPII_RAID_CONFIG_ELEMENT_FLAG_HSP_PHYS_DISK) && 3493 el->hot_spare_pool == hsmap) { 3494 /* 3495 * diskid comparison is based on the idea that all 3496 * disks are counted by the bio(4) in sequence, thus 3497 * substracting the number of disks in the volume 3498 * from the diskid yields us a "relative" hotspare 3499 * number, which is good enough for us. 3500 */ 3501 if (bd != NULL && bd->bd_diskid == nhs + nvdsk) { 3502 u_int8_t dn = el->phys_disk_num; 3503 3504 free(cpg, M_TEMP, pagelen); 3505 return (mpii_bio_disk(sc, bd, dn)); 3506 } 3507 nhs++; 3508 } 3509 } 3510 3511 if (hscnt) 3512 *hscnt = nhs; 3513 3514 free(cpg, M_TEMP, pagelen); 3515 return (0); 3516 } 3517 3518 int 3519 mpii_bio_disk(struct mpii_softc *sc, struct bioc_disk *bd, u_int8_t dn) 3520 { 3521 struct mpii_cfg_raid_physdisk_pg0 *ppg; 3522 struct mpii_cfg_hdr hdr; 3523 struct mpii_device *dev; 3524 int len; 3525 3526 DNPRINTF(MPII_D_IOCTL, "%s: mpii_bio_disk %d\n", DEVNAME(sc), 3527 bd->bd_diskid); 3528 3529 ppg = malloc(sizeof(*ppg), M_TEMP, M_WAITOK | M_CANFAIL | M_ZERO); 3530 if (ppg == NULL) { 3531 printf("%s: unable to allocate space for raid physical disk " 3532 "page 0\n", DEVNAME(sc)); 3533 return (ENOMEM); 3534 } 3535 3536 hdr.page_version = 0; 3537 hdr.page_length = sizeof(*ppg) / 4; 3538 hdr.page_number = 0; 3539 hdr.page_type = MPII_CONFIG_REQ_PAGE_TYPE_RAID_PD; 3540 3541 if (mpii_req_cfg_page(sc, MPII_CFG_RAID_PHYS_DISK_ADDR_NUMBER | dn, 0, 3542 &hdr, 1, ppg, sizeof(*ppg)) != 0) { 3543 printf("%s: unable to fetch raid drive page 0\n", 3544 DEVNAME(sc)); 3545 free(ppg, M_TEMP, sizeof(*ppg)); 3546 return (EINVAL); 3547 } 3548 3549 bd->bd_target = ppg->phys_disk_num; 3550 3551 if ((dev = mpii_find_dev(sc, lemtoh16(&ppg->dev_handle))) == NULL) { 3552 bd->bd_status = BIOC_SDINVALID; 3553 free(ppg, M_TEMP, sizeof(*ppg)); 3554 return (0); 3555 } 3556 3557 switch (ppg->phys_disk_state) { 3558 case MPII_CFG_RAID_PHYDISK_0_STATE_ONLINE: 3559 case MPII_CFG_RAID_PHYDISK_0_STATE_OPTIMAL: 3560 bd->bd_status = BIOC_SDONLINE; 3561 break; 3562 case MPII_CFG_RAID_PHYDISK_0_STATE_OFFLINE: 3563 if (ppg->offline_reason == 3564 MPII_CFG_RAID_PHYDISK_0_OFFLINE_FAILED || 3565 ppg->offline_reason == 3566 MPII_CFG_RAID_PHYDISK_0_OFFLINE_FAILEDREQ) 3567 bd->bd_status = BIOC_SDFAILED; 3568 else 3569 bd->bd_status = BIOC_SDOFFLINE; 3570 break; 3571 case MPII_CFG_RAID_PHYDISK_0_STATE_DEGRADED: 3572 bd->bd_status = BIOC_SDFAILED; 3573 break; 3574 case MPII_CFG_RAID_PHYDISK_0_STATE_REBUILDING: 3575 bd->bd_status = BIOC_SDREBUILD; 3576 break; 3577 case MPII_CFG_RAID_PHYDISK_0_STATE_HOTSPARE: 3578 bd->bd_status = BIOC_SDHOTSPARE; 3579 break; 3580 case MPII_CFG_RAID_PHYDISK_0_STATE_NOTCONFIGURED: 3581 bd->bd_status = BIOC_SDUNUSED; 3582 break; 3583 case MPII_CFG_RAID_PHYDISK_0_STATE_NOTCOMPATIBLE: 3584 default: 3585 bd->bd_status = BIOC_SDINVALID; 3586 break; 3587 } 3588 3589 bd->bd_size = letoh64(ppg->dev_max_lba) * lemtoh16(&ppg->block_size); 3590 3591 scsi_strvis(bd->bd_vendor, ppg->vendor_id, sizeof(ppg->vendor_id)); 3592 len = strlen(bd->bd_vendor); 3593 bd->bd_vendor[len] = ' '; 3594 scsi_strvis(&bd->bd_vendor[len + 1], ppg->product_id, 3595 sizeof(ppg->product_id)); 3596 scsi_strvis(bd->bd_serial, ppg->serial, sizeof(ppg->serial)); 3597 3598 free(ppg, M_TEMP, sizeof(*ppg)); 3599 return (0); 3600 } 3601 3602 struct mpii_device * 3603 mpii_find_vol(struct mpii_softc *sc, int volid) 3604 { 3605 struct mpii_device *dev = NULL; 3606 3607 if (sc->sc_vd_id_low + volid >= sc->sc_max_devices) 3608 return (NULL); 3609 dev = sc->sc_devs[sc->sc_vd_id_low + volid]; 3610 if (dev && ISSET(dev->flags, MPII_DF_VOLUME)) 3611 return (dev); 3612 return (NULL); 3613 } 3614 3615 #ifndef SMALL_KERNEL 3616 /* 3617 * Non-sleeping lightweight version of the mpii_ioctl_vol 3618 */ 3619 int 3620 mpii_bio_volstate(struct mpii_softc *sc, struct bioc_vol *bv) 3621 { 3622 struct mpii_cfg_raid_vol_pg0 *vpg; 3623 struct mpii_cfg_hdr hdr; 3624 struct mpii_device *dev = NULL; 3625 size_t pagelen; 3626 u_int16_t volh; 3627 3628 if ((dev = mpii_find_vol(sc, bv->bv_volid)) == NULL) 3629 return (ENODEV); 3630 volh = dev->dev_handle; 3631 3632 if (mpii_req_cfg_header(sc, MPII_CONFIG_REQ_PAGE_TYPE_RAID_VOL, 0, 3633 MPII_CFG_RAID_VOL_ADDR_HANDLE | volh, MPII_PG_POLL, &hdr) != 0) { 3634 DNPRINTF(MPII_D_MISC, "%s: unable to fetch header for raid " 3635 "volume page 0\n", DEVNAME(sc)); 3636 return (EINVAL); 3637 } 3638 3639 pagelen = hdr.page_length * 4; 3640 vpg = malloc(pagelen, M_TEMP, M_NOWAIT | M_ZERO); 3641 if (vpg == NULL) { 3642 DNPRINTF(MPII_D_MISC, "%s: unable to allocate space for raid " 3643 "volume page 0\n", DEVNAME(sc)); 3644 return (ENOMEM); 3645 } 3646 3647 if (mpii_req_cfg_page(sc, MPII_CFG_RAID_VOL_ADDR_HANDLE | volh, 3648 MPII_PG_POLL, &hdr, 1, vpg, pagelen) != 0) { 3649 DNPRINTF(MPII_D_MISC, "%s: unable to fetch raid volume " 3650 "page 0\n", DEVNAME(sc)); 3651 free(vpg, M_TEMP, pagelen); 3652 return (EINVAL); 3653 } 3654 3655 switch (vpg->volume_state) { 3656 case MPII_CFG_RAID_VOL_0_STATE_ONLINE: 3657 case MPII_CFG_RAID_VOL_0_STATE_OPTIMAL: 3658 bv->bv_status = BIOC_SVONLINE; 3659 break; 3660 case MPII_CFG_RAID_VOL_0_STATE_DEGRADED: 3661 if (ISSET(lemtoh32(&vpg->volume_status), 3662 MPII_CFG_RAID_VOL_0_STATUS_RESYNC)) 3663 bv->bv_status = BIOC_SVREBUILD; 3664 else 3665 bv->bv_status = BIOC_SVDEGRADED; 3666 break; 3667 case MPII_CFG_RAID_VOL_0_STATE_FAILED: 3668 bv->bv_status = BIOC_SVOFFLINE; 3669 break; 3670 case MPII_CFG_RAID_VOL_0_STATE_INITIALIZING: 3671 bv->bv_status = BIOC_SVBUILDING; 3672 break; 3673 case MPII_CFG_RAID_VOL_0_STATE_MISSING: 3674 default: 3675 bv->bv_status = BIOC_SVINVALID; 3676 break; 3677 } 3678 3679 free(vpg, M_TEMP, pagelen); 3680 return (0); 3681 } 3682 3683 int 3684 mpii_create_sensors(struct mpii_softc *sc) 3685 { 3686 struct scsibus_softc *ssc = sc->sc_scsibus; 3687 struct device *dev; 3688 struct scsi_link *link; 3689 int i; 3690 3691 sc->sc_sensors = mallocarray(sc->sc_vd_count, sizeof(struct ksensor), 3692 M_DEVBUF, M_NOWAIT | M_ZERO); 3693 if (sc->sc_sensors == NULL) 3694 return (1); 3695 sc->sc_nsensors = sc->sc_vd_count; 3696 3697 strlcpy(sc->sc_sensordev.xname, DEVNAME(sc), 3698 sizeof(sc->sc_sensordev.xname)); 3699 3700 for (i = 0; i < sc->sc_vd_count; i++) { 3701 link = scsi_get_link(ssc, i + sc->sc_vd_id_low, 0); 3702 if (link == NULL) 3703 goto bad; 3704 3705 dev = link->device_softc; 3706 3707 sc->sc_sensors[i].type = SENSOR_DRIVE; 3708 sc->sc_sensors[i].status = SENSOR_S_UNKNOWN; 3709 3710 strlcpy(sc->sc_sensors[i].desc, dev->dv_xname, 3711 sizeof(sc->sc_sensors[i].desc)); 3712 3713 sensor_attach(&sc->sc_sensordev, &sc->sc_sensors[i]); 3714 } 3715 3716 if (sensor_task_register(sc, mpii_refresh_sensors, 10) == NULL) 3717 goto bad; 3718 3719 sensordev_install(&sc->sc_sensordev); 3720 3721 return (0); 3722 3723 bad: 3724 free(sc->sc_sensors, M_DEVBUF, 0); 3725 3726 return (1); 3727 } 3728 3729 void 3730 mpii_refresh_sensors(void *arg) 3731 { 3732 struct mpii_softc *sc = arg; 3733 struct bioc_vol bv; 3734 int i; 3735 3736 for (i = 0; i < sc->sc_nsensors; i++) { 3737 memset(&bv, 0, sizeof(bv)); 3738 bv.bv_volid = i; 3739 if (mpii_bio_volstate(sc, &bv)) 3740 return; 3741 switch(bv.bv_status) { 3742 case BIOC_SVOFFLINE: 3743 sc->sc_sensors[i].value = SENSOR_DRIVE_FAIL; 3744 sc->sc_sensors[i].status = SENSOR_S_CRIT; 3745 break; 3746 case BIOC_SVDEGRADED: 3747 sc->sc_sensors[i].value = SENSOR_DRIVE_PFAIL; 3748 sc->sc_sensors[i].status = SENSOR_S_WARN; 3749 break; 3750 case BIOC_SVREBUILD: 3751 sc->sc_sensors[i].value = SENSOR_DRIVE_REBUILD; 3752 sc->sc_sensors[i].status = SENSOR_S_WARN; 3753 break; 3754 case BIOC_SVONLINE: 3755 sc->sc_sensors[i].value = SENSOR_DRIVE_ONLINE; 3756 sc->sc_sensors[i].status = SENSOR_S_OK; 3757 break; 3758 case BIOC_SVINVALID: 3759 /* FALLTHROUGH */ 3760 default: 3761 sc->sc_sensors[i].value = 0; /* unknown */ 3762 sc->sc_sensors[i].status = SENSOR_S_UNKNOWN; 3763 } 3764 } 3765 } 3766 #endif /* SMALL_KERNEL */ 3767 #endif /* NBIO > 0 */ 3768