1 /* $OpenBSD: maestro.c,v 1.50 2022/10/28 15:09:46 kn Exp $ */ 2 /* $FreeBSD: /c/ncvs/src/sys/dev/sound/pci/maestro.c,v 1.3 2000/11/21 12:22:11 julian Exp $ */ 3 /* 4 * FreeBSD's ESS Agogo/Maestro driver 5 * Converted from FreeBSD's pcm to OpenBSD's audio. 6 * Copyright (c) 2000, 2001 David Leonard & Marc Espie 7 * All rights reserved. 8 * 9 * Redistribution and use in source and binary forms, with or without 10 * modification, are permitted provided that the following conditions 11 * are met: 12 * 1. Redistributions of source code must retain the above copyright 13 * notice, this list of conditions and the following disclaimer. 14 * 2. Redistributions in binary form must reproduce the above copyright 15 * notice, this list of conditions and the following disclaimer in the 16 * documentation and/or other materials provided with the distribution. 17 * 18 * THIS SOFTWARE IS PROVIDED BY THE AUTHOR AND CONTRIBUTORS ``AS IS'' AND 19 * ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE 20 * IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE 21 * ARE DISCLAIMED. IN NO EVENT SHALL THE AUTHOR OR CONTRIBUTORS BE LIABLE 22 * FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL 23 * DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS 24 * OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) 25 * HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT 26 * LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY 27 * OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF 28 * SUCH DAMAGE. 29 */ 30 /*- 31 * (FreeBSD) Credits: 32 * Copyright (c) 2000 Taku YAMAMOTO <taku@cent.saitama-u.ac.jp> 33 * 34 * Part of this code (especially in many magic numbers) was heavily inspired 35 * by the Linux driver originally written by 36 * Alan Cox <alan.cox@linux.org>, modified heavily by 37 * Zach Brown <zab@zabbo.net>. 38 * 39 * busdma()-ize and buffer size reduction were suggested by 40 * Cameron Grant <gandalf@vilnya.demon.co.uk>. 41 * Also he showed me the way to use busdma() suite. 42 * 43 * Internal speaker problems on NEC VersaPro's and Dell Inspiron 7500 44 * were looked at by 45 * Munehiro Matsuda <haro@tk.kubota.co.jp>, 46 * who brought patches based on the Linux driver with some simplification. 47 */ 48 49 #include <sys/param.h> 50 #include <sys/systm.h> 51 #include <sys/kernel.h> 52 #include <sys/malloc.h> 53 #include <sys/device.h> 54 #include <sys/queue.h> 55 #include <sys/fcntl.h> 56 57 #include <dev/pci/pcidevs.h> 58 #include <dev/pci/pcivar.h> 59 60 #include <sys/audioio.h> 61 #include <dev/audio_if.h> 62 63 #include <dev/ic/ac97.h> 64 65 /* ----------------------------- 66 * PCI config registers 67 */ 68 69 /* Legacy emulation */ 70 #define CONF_LEGACY 0x40 71 72 #define LEGACY_DISABLED 0x8000 73 74 /* Chip configurations */ 75 #define CONF_MAESTRO 0x50 76 #define MAESTRO_CHIBUS 0x00100000 77 #define MAESTRO_POSTEDWRITE 0x00000080 78 #define MAESTRO_DMA_PCITIMING 0x00000040 79 #define MAESTRO_SWAP_LR 0x00000010 80 81 /* ACPI configurations */ 82 #define CONF_ACPI_STOPCLOCK 0x54 83 #define ACPI_PART_2ndC_CLOCK 15 84 #define ACPI_PART_CODEC_CLOCK 14 85 #define ACPI_PART_978 13 /* Docking station or something */ 86 #define ACPI_PART_SPDIF 12 87 #define ACPI_PART_GLUE 11 /* What? */ 88 #define ACPI_PART_DAA 10 89 #define ACPI_PART_PCI_IF 9 90 #define ACPI_PART_HW_VOL 8 91 #define ACPI_PART_GPIO 7 92 #define ACPI_PART_ASSP 6 93 #define ACPI_PART_SB 5 94 #define ACPI_PART_FM 4 95 #define ACPI_PART_RINGBUS 3 96 #define ACPI_PART_MIDI 2 97 #define ACPI_PART_GAME_PORT 1 98 #define ACPI_PART_WP 0 99 100 101 /* ----------------------------- 102 * I/O ports 103 */ 104 105 /* Direct Sound Processor (aka Wave Processor) */ 106 #define PORT_DSP_DATA 0x00 /* WORD RW */ 107 #define PORT_DSP_INDEX 0x02 /* WORD RW */ 108 #define PORT_INT_STAT 0x04 /* WORD RW */ 109 #define PORT_SAMPLE_CNT 0x06 /* WORD RO */ 110 111 /* WaveCache */ 112 #define PORT_WAVCACHE_INDEX 0x10 /* WORD RW */ 113 #define PORT_WAVCACHE_DATA 0x12 /* WORD RW */ 114 #define WAVCACHE_PCMBAR 0x1fc 115 #define WAVCACHE_WTBAR 0x1f0 116 #define WAVCACHE_BASEADDR_SHIFT 12 117 118 #define WAVCACHE_CHCTL_ADDRTAG_MASK 0xfff8 119 #define WAVCACHE_CHCTL_U8 0x0004 120 #define WAVCACHE_CHCTL_STEREO 0x0002 121 #define WAVCACHE_CHCTL_DECREMENTAL 0x0001 122 123 #define PORT_WAVCACHE_CTRL 0x14 /* WORD RW */ 124 #define WAVCACHE_EXTRA_CH_ENABLED 0x0200 125 #define WAVCACHE_ENABLED 0x0100 126 #define WAVCACHE_CH_60_ENABLED 0x0080 127 #define WAVCACHE_WTSIZE_MASK 0x0060 128 #define WAVCACHE_WTSIZE_1MB 0x0000 129 #define WAVCACHE_WTSIZE_2MB 0x0020 130 #define WAVCACHE_WTSIZE_4MB 0x0040 131 #define WAVCACHE_WTSIZE_8MB 0x0060 132 #define WAVCACHE_SGC_MASK 0x000c 133 #define WAVCACHE_SGC_DISABLED 0x0000 134 #define WAVCACHE_SGC_40_47 0x0004 135 #define WAVCACHE_SGC_32_47 0x0008 136 #define WAVCACHE_TESTMODE 0x0001 137 138 /* Host Interruption */ 139 #define PORT_HOSTINT_CTRL 0x18 /* WORD RW */ 140 #define HOSTINT_CTRL_SOFT_RESET 0x8000 141 #define HOSTINT_CTRL_DSOUND_RESET 0x4000 142 #define HOSTINT_CTRL_HW_VOL_TO_PME 0x0400 143 #define HOSTINT_CTRL_CLKRUN_ENABLED 0x0100 144 #define HOSTINT_CTRL_HWVOL_ENABLED 0x0040 145 #define HOSTINT_CTRL_ASSP_INT_ENABLED 0x0010 146 #define HOSTINT_CTRL_ISDN_INT_ENABLED 0x0008 147 #define HOSTINT_CTRL_DSOUND_INT_ENABLED 0x0004 148 #define HOSTINT_CTRL_MPU401_INT_ENABLED 0x0002 149 #define HOSTINT_CTRL_SB_INT_ENABLED 0x0001 150 151 #define PORT_HOSTINT_STAT 0x1a /* BYTE RW */ 152 #define HOSTINT_STAT_HWVOL 0x40 153 #define HOSTINT_STAT_ASSP 0x10 154 #define HOSTINT_STAT_ISDN 0x08 155 #define HOSTINT_STAT_DSOUND 0x04 156 #define HOSTINT_STAT_MPU401 0x02 157 #define HOSTINT_STAT_SB 0x01 158 159 /* Hardware volume */ 160 #define PORT_HWVOL_VOICE_SHADOW 0x1c /* BYTE RW */ 161 #define PORT_HWVOL_VOICE 0x1d /* BYTE RW */ 162 #define PORT_HWVOL_MASTER_SHADOW 0x1e /* BYTE RW */ 163 #define PORT_HWVOL_MASTER 0x1f /* BYTE RW */ 164 165 /* CODEC */ 166 #define PORT_CODEC_CMD 0x30 /* BYTE W */ 167 #define CODEC_CMD_READ 0x80 168 #define CODEC_CMD_WRITE 0x00 169 #define CODEC_CMD_ADDR_MASK 0x7f 170 171 #define PORT_CODEC_STAT 0x30 /* BYTE R */ 172 #define CODEC_STAT_MASK 0x01 173 #define CODEC_STAT_RW_DONE 0x00 174 #define CODEC_STAT_PROGLESS 0x01 175 176 #define PORT_CODEC_REG 0x32 /* WORD RW */ 177 178 /* Ring bus control */ 179 #define PORT_RINGBUS_CTRL 0x34 /* DWORD RW */ 180 #define RINGBUS_CTRL_I2S_ENABLED 0x80000000 181 #define RINGBUS_CTRL_RINGBUS_ENABLED 0x20000000 182 #define RINGBUS_CTRL_ACLINK_ENABLED 0x10000000 183 #define RINGBUS_CTRL_AC97_SWRESET 0x08000000 184 #define RINGBUS_CTRL_IODMA_PLAYBACK_ENABLED 0x04000000 185 #define RINGBUS_CTRL_IODMA_RECORD_ENABLED 0x02000000 186 187 #define RINGBUS_SRC_MIC 20 188 #define RINGBUS_SRC_I2S 16 189 #define RINGBUS_SRC_ADC 12 190 #define RINGBUS_SRC_MODEM 8 191 #define RINGBUS_SRC_DSOUND 4 192 #define RINGBUS_SRC_ASSP 0 193 194 #define RINGBUS_DEST_MONORAL 000 195 #define RINGBUS_DEST_STEREO 010 196 #define RINGBUS_DEST_NONE 0 197 #define RINGBUS_DEST_DAC 1 198 #define RINGBUS_DEST_MODEM_IN 2 199 #define RINGBUS_DEST_RESERVED3 3 200 #define RINGBUS_DEST_DSOUND_IN 4 201 #define RINGBUS_DEST_ASSP_IN 5 202 203 /* General Purpose I/O */ 204 #define PORT_GPIO_DATA 0x60 /* WORD RW */ 205 #define PORT_GPIO_MASK 0x64 /* WORD RW */ 206 #define PORT_GPIO_DIR 0x68 /* WORD RW */ 207 208 /* Application Specific Signal Processor */ 209 #define PORT_ASSP_MEM_INDEX 0x80 /* DWORD RW */ 210 #define PORT_ASSP_MEM_DATA 0x84 /* WORD RW */ 211 #define PORT_ASSP_CTRL_A 0xa2 /* BYTE RW */ 212 #define PORT_ASSP_CTRL_B 0xa4 /* BYTE RW */ 213 #define PORT_ASSP_CTRL_C 0xa6 /* BYTE RW */ 214 #define PORT_ASSP_HOST_WR_INDEX 0xa8 /* BYTE W */ 215 #define PORT_ASSP_HOST_WR_DATA 0xaa /* BYTE RW */ 216 #define PORT_ASSP_INT_STAT 0xac /* BYTE RW */ 217 218 219 /* ----------------------------- 220 * Wave Processor Indexed Data Registers. 221 */ 222 223 #define WPREG_DATA_PORT 0 224 #define WPREG_CRAM_PTR 1 225 #define WPREG_CRAM_DATA 2 226 #define WPREG_WAVE_DATA 3 227 #define WPREG_WAVE_PTR_LOW 4 228 #define WPREG_WAVE_PTR_HIGH 5 229 230 #define WPREG_TIMER_FREQ 6 231 #define WP_TIMER_FREQ_PRESCALE_MASK 0x00e0 /* actual - 9 */ 232 #define WP_TIMER_FREQ_PRESCALE_SHIFT 5 233 #define WP_TIMER_FREQ_DIVIDE_MASK 0x001f 234 #define WP_TIMER_FREQ_DIVIDE_SHIFT 0 235 236 #define WPREG_WAVE_ROMRAM 7 237 #define WP_WAVE_VIRTUAL_ENABLED 0x0400 238 #define WP_WAVE_8BITRAM_ENABLED 0x0200 239 #define WP_WAVE_DRAM_ENABLED 0x0100 240 #define WP_WAVE_RAMSPLIT_MASK 0x00ff 241 #define WP_WAVE_RAMSPLIT_SHIFT 0 242 243 #define WPREG_BASE 12 244 #define WP_PARAOUT_BASE_MASK 0xf000 245 #define WP_PARAOUT_BASE_SHIFT 12 246 #define WP_PARAIN_BASE_MASK 0x0f00 247 #define WP_PARAIN_BASE_SHIFT 8 248 #define WP_SERIAL0_BASE_MASK 0x00f0 249 #define WP_SERIAL0_BASE_SHIFT 4 250 #define WP_SERIAL1_BASE_MASK 0x000f 251 #define WP_SERIAL1_BASE_SHIFT 0 252 253 #define WPREG_TIMER_ENABLE 17 254 #define WPREG_TIMER_START 23 255 256 257 /* ----------------------------- 258 * Audio Processing Unit. 259 */ 260 #define APUREG_APUTYPE 0 261 #define APU_DMA_ENABLED 0x4000 262 #define APU_INT_ON_LOOP 0x2000 263 #define APU_ENDCURVE 0x1000 264 #define APU_APUTYPE_MASK 0x00f0 265 #define APU_FILTERTYPE_MASK 0x000c 266 #define APU_FILTERQ_MASK 0x0003 267 268 /* APU types */ 269 #define APU_APUTYPE_SHIFT 4 270 271 #define APUTYPE_INACTIVE 0 272 #define APUTYPE_16BITLINEAR 1 273 #define APUTYPE_16BITSTEREO 2 274 #define APUTYPE_8BITLINEAR 3 275 #define APUTYPE_8BITSTEREO 4 276 #define APUTYPE_8BITDIFF 5 277 #define APUTYPE_DIGITALDELAY 6 278 #define APUTYPE_DUALTAP_READER 7 279 #define APUTYPE_CORRELATOR 8 280 #define APUTYPE_INPUTMIXER 9 281 #define APUTYPE_WAVETABLE 10 282 #define APUTYPE_RATECONV 11 283 #define APUTYPE_16BITPINGPONG 12 284 /* APU type 13 through 15 are reserved. */ 285 286 /* Filter types */ 287 #define APU_FILTERTYPE_SHIFT 2 288 289 #define FILTERTYPE_2POLE_LOPASS 0 290 #define FILTERTYPE_2POLE_BANDPASS 1 291 #define FILTERTYPE_2POLE_HIPASS 2 292 #define FILTERTYPE_1POLE_LOPASS 3 293 #define FILTERTYPE_1POLE_HIPASS 4 294 #define FILTERTYPE_PASSTHROUGH 5 295 296 /* Filter Q */ 297 #define APU_FILTERQ_SHIFT 0 298 299 #define FILTERQ_LESSQ 0 300 #define FILTERQ_MOREQ 3 301 302 /* APU register 2 */ 303 #define APUREG_FREQ_LOBYTE 2 304 #define APU_FREQ_LOBYTE_MASK 0xff00 305 #define APU_plus6dB 0x0010 306 307 /* APU register 3 */ 308 #define APUREG_FREQ_HIWORD 3 309 #define APU_FREQ_HIWORD_MASK 0x0fff 310 311 /* Frequency */ 312 #define APU_FREQ_LOBYTE_SHIFT 8 313 #define APU_FREQ_HIWORD_SHIFT 0 314 #define FREQ_Hz2DIV(freq) (((u_int64_t)(freq) << 16) / 48000) 315 316 /* APU register 4 */ 317 #define APUREG_WAVESPACE 4 318 #define APU_STEREO 0x8000 319 #define APU_USE_SYSMEM 0x4000 320 #define APU_PCMBAR_MASK 0x6000 321 #define APU_64KPAGE_MASK 0xff00 322 323 /* PCM Base Address Register selection */ 324 #define APU_PCMBAR_SHIFT 13 325 326 /* 64KW (==128KB) Page */ 327 #define APU_64KPAGE_SHIFT 8 328 329 /* APU register 5 - 7 */ 330 #define APUREG_CURPTR 5 331 #define APUREG_ENDPTR 6 332 #define APUREG_LOOPLEN 7 333 334 /* APU register 9 */ 335 #define APUREG_AMPLITUDE 9 336 #define APU_AMPLITUDE_NOW_MASK 0xff00 337 #define APU_AMPLITUDE_DEST_MASK 0x00ff 338 339 /* Amplitude now? */ 340 #define APU_AMPLITUDE_NOW_SHIFT 8 341 342 /* APU register 10 */ 343 #define APUREG_POSITION 10 344 #define APU_RADIUS_MASK 0x00c0 345 #define APU_PAN_MASK 0x003f 346 347 /* Radius control. */ 348 #define APU_RADIUS_SHIFT 6 349 #define RADIUS_CENTERCIRCLE 0 350 #define RADIUS_MIDDLE 1 351 #define RADIUS_OUTSIDE 2 352 353 /* Polar pan. */ 354 #define APU_PAN_SHIFT 0 355 #define PAN_RIGHT 0x00 356 #define PAN_FRONT 0x08 357 #define PAN_LEFT 0x10 358 359 360 /* ----------------------------- 361 * Limits. 362 */ 363 #define WPWA_MAX ((1 << 22) - 1) 364 #define WPWA_MAXADDR ((1 << 23) - 1) 365 #define MAESTRO_MAXADDR ((1 << 28) - 1) 366 367 368 369 #ifdef AUDIO_DEBUG 370 #define DPRINTF(x) if (maestrodebug) printf x 371 #define DLPRINTF(i, x) if (maestrodebug & i) printf x 372 int maestrodebug = 0; 373 u_long maestrointr_called; 374 u_long maestrodma_effective; 375 376 #define MAESTRODEBUG_INTR 1 377 #define MAESTRODEBUG_TIMER 2 378 #else 379 #define DPRINTF(x) 380 #define DLPRINTF(i, x) 381 #endif 382 383 #define MAESTRO_BUFSIZ 0x4000 384 #define lengthof(array) (sizeof (array) / sizeof (array)[0]) 385 386 #define STEP_VOLUME 0x22 387 #define MIDDLE_VOLUME (STEP_VOLUME * 4) 388 389 typedef struct salloc_pool { 390 struct salloc_zone { 391 SLIST_ENTRY(salloc_zone) link; 392 caddr_t addr; 393 size_t size; 394 } *zones; 395 SLIST_HEAD(salloc_head, salloc_zone) free, used, spare; 396 } *salloc_t; 397 398 struct maestro_softc; 399 400 #define MAESTRO_PLAY 1 401 #define MAESTRO_STEREO 2 402 #define MAESTRO_8BIT 4 403 #define MAESTRO_UNSIGNED 8 404 #define MAESTRO_RUNNING 16 405 406 struct maestro_channel { 407 struct maestro_softc *sc; 408 int num; 409 u_int32_t blocksize; 410 u_int16_t mode; 411 u_int32_t speed; 412 u_int32_t dv; 413 u_int16_t start; 414 u_int16_t threshold; 415 u_int16_t end; 416 u_int16_t current; 417 u_int wpwa; 418 void (*intr)(void *); 419 void *intr_arg; 420 }; 421 422 struct maestro_softc { 423 struct device dev; 424 425 void *ih; 426 pci_chipset_tag_t pc; 427 pcitag_t pt; 428 429 #define MAESTRO_FLAG_SETUPGPIO 0x0001 430 int flags; 431 bus_space_tag_t iot; 432 bus_space_handle_t ioh; 433 bus_dma_tag_t dmat; 434 435 caddr_t dmabase; 436 bus_addr_t physaddr; 437 size_t dmasize; 438 bus_dmamap_t dmamap; 439 bus_dma_segment_t dmaseg; 440 salloc_t dmapool; 441 442 struct ac97_codec_if *codec_if; 443 struct ac97_host_if host_if; 444 445 int suspend; 446 447 struct maestro_channel play; 448 struct maestro_channel record; 449 }; 450 451 452 typedef u_int16_t wpreg_t; 453 typedef u_int16_t wcreg_t; 454 455 salloc_t salloc_new(caddr_t, size_t, int); 456 void salloc_destroy(salloc_t); 457 caddr_t salloc_alloc(salloc_t, size_t); 458 void salloc_free(salloc_t, caddr_t); 459 void salloc_insert(salloc_t, struct salloc_head *, 460 struct salloc_zone *, int); 461 462 int maestro_match(struct device *, void *, void *); 463 void maestro_attach(struct device *, struct device *, void *); 464 int maestro_activate(struct device *, int); 465 int maestro_intr(void *); 466 467 int maestro_open(void *, int); 468 void maestro_close(void *); 469 int maestro_set_params(void *, int, int, struct audio_params *, 470 struct audio_params *); 471 int maestro_round_blocksize(void *, int); 472 int maestro_halt_output(void *); 473 int maestro_halt_input(void *); 474 int maestro_set_port(void *, mixer_ctrl_t *); 475 int maestro_get_port(void *, mixer_ctrl_t *); 476 int maestro_query_devinfo(void *, mixer_devinfo_t *); 477 void *maestro_malloc(void *, int, size_t, int, int); 478 void maestro_free(void *, void *, int); 479 int maestro_trigger_output(void *, void *, void *, int, void (*)(void *), 480 void *, struct audio_params *); 481 int maestro_trigger_input(void *, void *, void *, int, void (*)(void *), 482 void *, struct audio_params *); 483 484 int maestro_attach_codec(void *, struct ac97_codec_if *); 485 enum ac97_host_flags maestro_codec_flags(void *); 486 int maestro_read_codec(void *, u_int8_t, u_int16_t *); 487 int maestro_write_codec(void *, u_int8_t, u_int16_t); 488 void maestro_reset_codec(void *); 489 490 void maestro_initcodec(void *); 491 492 void maestro_set_speed(struct maestro_channel *, u_long *); 493 void maestro_init(struct maestro_softc *); 494 495 void maestro_channel_start(struct maestro_channel *); 496 void maestro_channel_stop(struct maestro_channel *); 497 void maestro_channel_advance_dma(struct maestro_channel *); 498 void maestro_channel_suppress_jitter(struct maestro_channel *); 499 500 int maestro_get_flags(struct pci_attach_args *); 501 502 void ringbus_setdest(struct maestro_softc *, int, int); 503 504 wpreg_t wp_reg_read(struct maestro_softc *, int); 505 void wp_reg_write(struct maestro_softc *, int, wpreg_t); 506 wpreg_t wp_apu_read(struct maestro_softc *, int, int); 507 void wp_apu_write(struct maestro_softc *, int, int, wpreg_t); 508 void wp_settimer(struct maestro_softc *, u_int); 509 void wp_starttimer(struct maestro_softc *); 510 void wp_stoptimer(struct maestro_softc *); 511 512 wcreg_t wc_reg_read(struct maestro_softc *, int); 513 void wc_reg_write(struct maestro_softc *, int, wcreg_t); 514 wcreg_t wc_ctrl_read(struct maestro_softc *, int); 515 void wc_ctrl_write(struct maestro_softc *, int, wcreg_t); 516 517 u_int maestro_calc_timer_freq(struct maestro_channel *); 518 void maestro_update_timer(struct maestro_softc *); 519 520 struct cfdriver maestro_cd = { 521 NULL, "maestro", DV_DULL 522 }; 523 524 const struct cfattach maestro_ca = { 525 sizeof (struct maestro_softc), maestro_match, maestro_attach, 526 NULL, maestro_activate 527 }; 528 529 const struct audio_hw_if maestro_hw_if = { 530 .open = maestro_open, 531 .close = maestro_close, 532 .set_params = maestro_set_params, 533 .round_blocksize = maestro_round_blocksize, 534 .halt_output = maestro_halt_output, 535 .halt_input = maestro_halt_input, 536 .set_port = maestro_set_port, 537 .get_port = maestro_get_port, 538 .query_devinfo = maestro_query_devinfo, 539 .allocm = maestro_malloc, 540 .freem = maestro_free, 541 .trigger_output = maestro_trigger_output, 542 .trigger_input = maestro_trigger_input, 543 }; 544 545 const struct { 546 u_short vendor, product; 547 int flags; 548 } maestro_pcitab[] = { 549 { PCI_VENDOR_ESSTECH, PCI_PRODUCT_ESSTECH_MAESTROII, 0 }, 550 { PCI_VENDOR_ESSTECH, PCI_PRODUCT_ESSTECH_MAESTRO2E, 0 }, 551 { PCI_VENDOR_PLATFORM, PCI_PRODUCT_PLATFORM_ES1849, 0 }, 552 { PCI_VENDOR_NEC, PCI_PRODUCT_NEC_VERSAMAESTRO, MAESTRO_FLAG_SETUPGPIO }, 553 { PCI_VENDOR_NEC, PCI_PRODUCT_NEC_VERSAPRONXVA26D, MAESTRO_FLAG_SETUPGPIO } 554 }; 555 #define NMAESTRO_PCITAB lengthof(maestro_pcitab) 556 557 int 558 maestro_get_flags(struct pci_attach_args *pa) 559 { 560 int i; 561 562 /* Distinguish audio devices from modems with the same manfid */ 563 if (PCI_CLASS(pa->pa_class) != PCI_CLASS_MULTIMEDIA) 564 return (-1); 565 if (PCI_SUBCLASS(pa->pa_class) != PCI_SUBCLASS_MULTIMEDIA_AUDIO) 566 return (-1); 567 for (i = 0; i < NMAESTRO_PCITAB; i++) 568 if (PCI_VENDOR(pa->pa_id) == maestro_pcitab[i].vendor && 569 PCI_PRODUCT(pa->pa_id) == maestro_pcitab[i].product) 570 return (maestro_pcitab[i].flags); 571 return (-1); 572 } 573 574 /* ----------------------------- 575 * Driver interface. 576 */ 577 578 int 579 maestro_match(struct device *parent, void *match, void *aux) 580 { 581 struct pci_attach_args *pa = (struct pci_attach_args *)aux; 582 583 if (maestro_get_flags(pa) == -1) 584 return (0); 585 else 586 return (1); 587 } 588 589 void 590 maestro_attach(struct device *parent, struct device *self, void *aux) 591 { 592 struct maestro_softc *sc = (struct maestro_softc *)self; 593 struct pci_attach_args *pa = (struct pci_attach_args *)aux; 594 pci_chipset_tag_t pc = pa->pa_pc; 595 char const *intrstr; 596 pci_intr_handle_t ih; 597 int error; 598 u_int16_t cdata; 599 int dmastage = 0; 600 int rseg; 601 602 sc->flags = maestro_get_flags(pa); 603 604 sc->pc = pa->pa_pc; 605 sc->pt = pa->pa_tag; 606 sc->dmat = pa->pa_dmat; 607 608 /* Map interrupt */ 609 if (pci_intr_map(pa, &ih)) { 610 printf(": can't map interrupt\n"); 611 return; 612 } 613 intrstr = pci_intr_string(pc, ih); 614 sc->ih = pci_intr_establish(pc, ih, IPL_AUDIO | IPL_MPSAFE, 615 maestro_intr, sc, sc->dev.dv_xname); 616 if (sc->ih == NULL) { 617 printf(": can't establish interrupt"); 618 if (intrstr != NULL) 619 printf(" at %s\n", intrstr); 620 return; 621 } 622 printf(": %s", intrstr); 623 624 pci_set_powerstate(pc, sc->pt, PCI_PMCSR_STATE_D0); 625 626 /* Map i/o */ 627 if ((error = pci_mapreg_map(pa, PCI_MAPS, PCI_MAPREG_TYPE_IO, 628 0, &sc->iot, &sc->ioh, NULL, NULL, 0)) != 0) { 629 printf(", can't map i/o space\n"); 630 goto bad; 631 }; 632 633 /* Allocate fixed DMA segment :-( */ 634 sc->dmasize = MAESTRO_BUFSIZ * 16; 635 if ((error = bus_dmamem_alloc(sc->dmat, sc->dmasize, NBPG, 0, 636 &sc->dmaseg, 1, &rseg, BUS_DMA_NOWAIT)) != 0) { 637 printf(", unable to alloc dma, error %d\n", error); 638 goto bad; 639 } 640 dmastage = 1; 641 if ((error = bus_dmamem_map(sc->dmat, &sc->dmaseg, 1, 642 sc->dmasize, &sc->dmabase, BUS_DMA_NOWAIT | 643 BUS_DMA_COHERENT)) != 0) { 644 printf(", unable to map dma, error %d\n", error); 645 goto bad; 646 } 647 dmastage = 2; 648 if ((error = bus_dmamap_create(sc->dmat, sc->dmasize, 1, 649 sc->dmasize, 0, BUS_DMA_NOWAIT, &sc->dmamap)) != 0) { 650 printf(", unable to create dma map, error %d\n", error); 651 goto bad; 652 } 653 dmastage = 3; 654 if ((error = bus_dmamap_load(sc->dmat, sc->dmamap, 655 sc->dmabase, sc->dmasize, NULL, BUS_DMA_NOWAIT)) != 0) { 656 printf(", unable to load dma map, error %d\n", error); 657 goto bad; 658 } 659 660 /* XXX 661 * The first byte of the allocated memory is not usable, 662 * the WP sometimes uses it to store status. 663 */ 664 /* Make DMA memory pool */ 665 if ((sc->dmapool = salloc_new(sc->dmabase+16, sc->dmasize-16, 666 128/*overkill?*/)) == NULL) { 667 printf(", unable to make dma pool\n"); 668 goto bad; 669 } 670 671 sc->physaddr = sc->dmamap->dm_segs[0].ds_addr; 672 673 printf("\n"); 674 675 /* Kick device */ 676 maestro_init(sc); 677 maestro_read_codec(sc, 0, &cdata); 678 if (cdata == 0x80) { 679 printf("%s: PT101 codec unsupported, no mixer\n", 680 sc->dev.dv_xname); 681 /* Init values from Linux, no idea what this does. */ 682 maestro_write_codec(sc, 0x2a, 0x0001); 683 maestro_write_codec(sc, 0x2C, 0x0000); 684 maestro_write_codec(sc, 0x2C, 0xFFFF); 685 maestro_write_codec(sc, 0x10, 0x9F1F); 686 maestro_write_codec(sc, 0x12, 0x0808); 687 maestro_write_codec(sc, 0x14, 0x9F1F); 688 maestro_write_codec(sc, 0x16, 0x9F1F); 689 maestro_write_codec(sc, 0x18, 0x0404); 690 maestro_write_codec(sc, 0x1A, 0x0000); 691 maestro_write_codec(sc, 0x1C, 0x0000); 692 maestro_write_codec(sc, 0x02, 0x0404); 693 maestro_write_codec(sc, 0x04, 0x0808); 694 maestro_write_codec(sc, 0x0C, 0x801F); 695 maestro_write_codec(sc, 0x0E, 0x801F); 696 /* no control over the mixer, sorry */ 697 sc->codec_if = NULL; 698 } else { 699 /* Attach the AC'97 */ 700 sc->host_if.arg = sc; 701 sc->host_if.attach = maestro_attach_codec; 702 sc->host_if.flags = maestro_codec_flags; 703 sc->host_if.read = maestro_read_codec; 704 sc->host_if.write = maestro_write_codec; 705 sc->host_if.reset = maestro_reset_codec; 706 if (ac97_attach(&sc->host_if) != 0) { 707 printf("%s: can't attach codec\n", sc->dev.dv_xname); 708 goto bad; 709 } 710 } 711 712 sc->play.mode = MAESTRO_PLAY; 713 sc->play.sc = sc; 714 sc->play.num = 0; 715 sc->record.sc = sc; 716 sc->record.num = 2; 717 sc->record.mode = 0; 718 719 /* Attach audio */ 720 audio_attach_mi(&maestro_hw_if, sc, NULL, &sc->dev); 721 return; 722 723 bad: 724 if (sc->ih) 725 pci_intr_disestablish(pc, sc->ih); 726 printf("%s: disabled\n", sc->dev.dv_xname); 727 if (sc->dmapool) 728 salloc_destroy(sc->dmapool); 729 if (dmastage >= 3) 730 bus_dmamap_destroy(sc->dmat, sc->dmamap); 731 if (dmastage >= 2) 732 bus_dmamem_unmap(sc->dmat, sc->dmabase, sc->dmasize); 733 if (dmastage >= 1) 734 bus_dmamem_free(sc->dmat, &sc->dmaseg, 1); 735 } 736 737 void 738 maestro_init(struct maestro_softc *sc) 739 { 740 int reg; 741 pcireg_t data; 742 743 /* Disable all legacy emulations. */ 744 data = pci_conf_read(sc->pc, sc->pt, CONF_LEGACY); 745 data |= LEGACY_DISABLED; 746 pci_conf_write(sc->pc, sc->pt, CONF_LEGACY, data); 747 748 /* Disconnect from CHI. (Makes Dell inspiron 7500 work?) 749 * Enable posted write. 750 * Prefer PCI timing rather than that of ISA. 751 * Don't swap L/R. */ 752 data = pci_conf_read(sc->pc, sc->pt, CONF_MAESTRO); 753 data |= MAESTRO_CHIBUS | MAESTRO_POSTEDWRITE | MAESTRO_DMA_PCITIMING; 754 data &= ~MAESTRO_SWAP_LR; 755 pci_conf_write(sc->pc, sc->pt, CONF_MAESTRO, data); 756 /* Reset direct sound. */ 757 bus_space_write_2(sc->iot, sc->ioh, PORT_HOSTINT_CTRL, 758 HOSTINT_CTRL_DSOUND_RESET); 759 DELAY(10000); /* XXX - too long? */ 760 bus_space_write_2(sc->iot, sc->ioh, PORT_HOSTINT_CTRL, 0); 761 DELAY(10000); 762 763 /* Enable direct sound and hardware volume control interruptions. */ 764 bus_space_write_2(sc->iot, sc->ioh, PORT_HOSTINT_CTRL, 765 HOSTINT_CTRL_DSOUND_INT_ENABLED | HOSTINT_CTRL_HWVOL_ENABLED); 766 767 /* Setup Wave Processor. */ 768 769 /* Enable WaveCache, set DMA base address. */ 770 wp_reg_write(sc, WPREG_WAVE_ROMRAM, 771 WP_WAVE_VIRTUAL_ENABLED | WP_WAVE_DRAM_ENABLED); 772 bus_space_write_2(sc->iot, sc->ioh, PORT_WAVCACHE_CTRL, 773 WAVCACHE_ENABLED | WAVCACHE_WTSIZE_4MB); 774 775 for (reg = WAVCACHE_PCMBAR; reg < WAVCACHE_PCMBAR + 4; reg++) 776 wc_reg_write(sc, reg, 777 sc->physaddr >> WAVCACHE_BASEADDR_SHIFT); 778 779 /* Setup Codec/Ringbus. */ 780 maestro_initcodec(sc); 781 bus_space_write_4(sc->iot, sc->ioh, PORT_RINGBUS_CTRL, 782 RINGBUS_CTRL_RINGBUS_ENABLED | RINGBUS_CTRL_ACLINK_ENABLED); 783 784 wp_reg_write(sc, WPREG_BASE, 0x8500); /* Parallel I/O */ 785 ringbus_setdest(sc, RINGBUS_SRC_ADC, 786 RINGBUS_DEST_STEREO | RINGBUS_DEST_DSOUND_IN); 787 ringbus_setdest(sc, RINGBUS_SRC_DSOUND, 788 RINGBUS_DEST_STEREO | RINGBUS_DEST_DAC); 789 790 /* Setup ASSP. Needed for Dell Inspiron 7500? */ 791 bus_space_write_1(sc->iot, sc->ioh, PORT_ASSP_CTRL_B, 0x00); 792 bus_space_write_1(sc->iot, sc->ioh, PORT_ASSP_CTRL_A, 0x03); 793 bus_space_write_1(sc->iot, sc->ioh, PORT_ASSP_CTRL_C, 0x00); 794 795 /* 796 * Reset hw volume to a known value so that we may handle diffs 797 * off to AC'97. 798 */ 799 800 bus_space_write_1(sc->iot, sc->ioh, PORT_HWVOL_MASTER, MIDDLE_VOLUME); 801 /* Setup GPIO if needed (NEC systems) */ 802 if (sc->flags & MAESTRO_FLAG_SETUPGPIO) { 803 /* Matthew Braithwaite <matt@braithwaite.net> reported that 804 * NEC Versa LX doesn't need GPIO operation. */ 805 bus_space_write_2(sc->iot, sc->ioh, 806 PORT_GPIO_MASK, 0x9ff); 807 bus_space_write_2(sc->iot, sc->ioh, PORT_GPIO_DIR, 808 bus_space_read_2(sc->iot, sc->ioh, PORT_GPIO_DIR) | 0x600); 809 bus_space_write_2(sc->iot, sc->ioh, 810 PORT_GPIO_DATA, 0x200); 811 } 812 } 813 814 /* ----------------------------- 815 * Audio interface 816 */ 817 818 int 819 maestro_round_blocksize(void *self, int blk) 820 { 821 return ((blk + 0xf) & ~0xf); 822 } 823 824 void * 825 maestro_malloc(void *arg, int dir, size_t size, int pool, int flags) 826 { 827 struct maestro_softc *sc = (struct maestro_softc *)arg; 828 829 return (salloc_alloc(sc->dmapool, size)); 830 } 831 832 void 833 maestro_free(void *self, void *ptr, int pool) 834 { 835 struct maestro_softc *sc = (struct maestro_softc *)self; 836 837 salloc_free(sc->dmapool, ptr); 838 } 839 840 int 841 maestro_set_port(void *self, mixer_ctrl_t *cp) 842 { 843 struct ac97_codec_if *c = ((struct maestro_softc *)self)->codec_if; 844 int rc; 845 846 if (c) { 847 /* interrupts use the mixer */ 848 mtx_enter(&audio_lock); 849 rc = c->vtbl->mixer_set_port(c, cp); 850 mtx_leave(&audio_lock); 851 return rc; 852 } else 853 return (ENXIO); 854 } 855 856 int 857 maestro_get_port(void *self, mixer_ctrl_t *cp) 858 { 859 struct ac97_codec_if *c = ((struct maestro_softc *)self)->codec_if; 860 int rc; 861 862 if (c) { 863 /* interrupts use the mixer */ 864 mtx_enter(&audio_lock); 865 rc = c->vtbl->mixer_get_port(c, cp); 866 mtx_leave(&audio_lock); 867 return rc; 868 } else 869 return (ENXIO); 870 } 871 872 int 873 maestro_query_devinfo(void *self, mixer_devinfo_t *cp) 874 { 875 struct ac97_codec_if *c = ((struct maestro_softc *)self)->codec_if; 876 int rc; 877 878 if (c) { 879 /* interrupts use the mixer */ 880 mtx_enter(&audio_lock); 881 rc = c->vtbl->query_devinfo(c, cp); 882 mtx_leave(&audio_lock); 883 return rc; 884 } else 885 return (ENXIO); 886 } 887 888 #define UNUSED __attribute__((unused)) 889 890 void 891 maestro_set_speed(struct maestro_channel *ch, u_long *prate) 892 { 893 ch->speed = *prate; 894 if ((ch->mode & (MAESTRO_8BIT | MAESTRO_STEREO)) == MAESTRO_8BIT) 895 ch->speed /= 2; 896 897 /* special common case */ 898 if (ch->speed == 48000) { 899 ch->dv = 0x10000; 900 } else { 901 /* compute 16 bits fixed point value of speed/48000, 902 * being careful not to overflow */ 903 ch->dv = (((ch->speed % 48000) << 16U) + 24000) / 48000 904 + ((ch->speed / 48000) << 16U); 905 /* And this is the real rate obtained */ 906 ch->speed = (ch->dv >> 16U) * 48000 + 907 (((ch->dv & 0xffff)*48000)>>16U); 908 } 909 *prate = ch->speed; 910 if ((ch->mode & (MAESTRO_8BIT | MAESTRO_STEREO)) == MAESTRO_8BIT) 911 *prate *= 2; 912 } 913 914 u_int 915 maestro_calc_timer_freq(struct maestro_channel *ch) 916 { 917 u_int ss = 2; 918 919 if (ch->mode & MAESTRO_8BIT) 920 ss = 1; 921 return (ch->speed * ss) / ch->blocksize; 922 } 923 924 void 925 maestro_update_timer(struct maestro_softc *sc) 926 { 927 u_int freq = 0; 928 u_int n; 929 930 if (sc->play.mode & MAESTRO_RUNNING) 931 freq = maestro_calc_timer_freq(&sc->play); 932 if (sc->record.mode & MAESTRO_RUNNING) { 933 n = maestro_calc_timer_freq(&sc->record); 934 if (freq < n) 935 freq = n; 936 } 937 if (freq) { 938 wp_settimer(sc, freq); 939 wp_starttimer(sc); 940 } else 941 wp_stoptimer(sc); 942 } 943 944 945 int 946 maestro_set_params(void *hdl, int setmode, int usemode, 947 struct audio_params *play, struct audio_params *rec) 948 { 949 struct maestro_softc *sc = (struct maestro_softc *)hdl; 950 951 if ((setmode & AUMODE_PLAY) == 0) 952 return (0); 953 954 /* Disallow parameter change on a running audio for now */ 955 if (sc->play.mode & MAESTRO_RUNNING) 956 return (EINVAL); 957 958 if (play->sample_rate < 4000) 959 play->sample_rate = 4000; 960 else if (play->sample_rate > 48000) 961 play->sample_rate = 48000; 962 963 if (play->channels > 2) 964 play->channels = 2; 965 966 sc->play.mode = MAESTRO_PLAY; 967 if (play->channels == 2) 968 sc->play.mode |= MAESTRO_STEREO; 969 970 if (play->precision == 8) { 971 sc->play.mode |= MAESTRO_8BIT; 972 if (play->encoding == AUDIO_ENCODING_ULINEAR_LE || 973 play->encoding == AUDIO_ENCODING_ULINEAR_BE) 974 sc->play.mode |= MAESTRO_UNSIGNED; 975 } 976 else if (play->encoding != AUDIO_ENCODING_SLINEAR_LE) 977 return (EINVAL); 978 979 play->bps = AUDIO_BPS(play->precision); 980 play->msb = 1; 981 982 maestro_set_speed(&sc->play, &play->sample_rate); 983 return (0); 984 } 985 986 int 987 maestro_open(void *hdl, int flags) 988 { 989 struct maestro_softc *sc = (struct maestro_softc *)hdl; 990 DPRINTF(("%s: open(%d)\n", sc->dev.dv_xname, flags)); 991 992 if ((flags & (FWRITE | FREAD)) == (FWRITE | FREAD)) 993 return ENXIO; /* XXX */ 994 995 /* XXX work around VM brokeness */ 996 #if 0 997 if ((OFLAGS(flags) & O_ACCMODE) != O_WRONLY) 998 return (EINVAL); 999 #endif 1000 sc->play.mode = MAESTRO_PLAY; 1001 sc->record.mode = 0; 1002 #ifdef AUDIO_DEBUG 1003 maestrointr_called = 0; 1004 maestrodma_effective = 0; 1005 #endif 1006 return (0); 1007 } 1008 1009 void 1010 maestro_close(void *hdl) 1011 { 1012 struct maestro_softc *sc UNUSED = (struct maestro_softc *)hdl; 1013 /* nothing to do */ 1014 } 1015 1016 1017 void 1018 maestro_channel_stop(struct maestro_channel *ch) 1019 { 1020 wp_apu_write(ch->sc, ch->num, APUREG_APUTYPE, 1021 APUTYPE_INACTIVE << APU_APUTYPE_SHIFT); 1022 if (ch->mode & MAESTRO_STEREO) 1023 wp_apu_write(ch->sc, ch->num+1, APUREG_APUTYPE, 1024 APUTYPE_INACTIVE << APU_APUTYPE_SHIFT); 1025 /* four channels for record... */ 1026 if (ch->mode & MAESTRO_PLAY) 1027 return; 1028 wp_apu_write(ch->sc, ch->num+2, APUREG_APUTYPE, 1029 APUTYPE_INACTIVE << APU_APUTYPE_SHIFT); 1030 if (ch->mode & MAESTRO_STEREO) 1031 wp_apu_write(ch->sc, ch->num+3, APUREG_APUTYPE, 1032 APUTYPE_INACTIVE << APU_APUTYPE_SHIFT); 1033 1034 } 1035 1036 int 1037 maestro_halt_input(void *hdl) 1038 { 1039 struct maestro_softc *sc = (struct maestro_softc *)hdl; 1040 1041 mtx_enter(&audio_lock); 1042 maestro_channel_stop(&sc->record); 1043 sc->record.mode &= ~MAESTRO_RUNNING; 1044 maestro_update_timer(sc); 1045 mtx_leave(&audio_lock); 1046 return 0; 1047 } 1048 1049 int 1050 maestro_halt_output(void *hdl) 1051 { 1052 struct maestro_softc *sc = (struct maestro_softc *)hdl; 1053 1054 mtx_enter(&audio_lock); 1055 maestro_channel_stop(&sc->play); 1056 sc->play.mode &= ~MAESTRO_RUNNING; 1057 maestro_update_timer(sc); 1058 mtx_leave(&audio_lock); 1059 return 0; 1060 } 1061 1062 int 1063 maestro_trigger_input(void *hdl, void *start, void *end, int blksize, 1064 void (*intr)(void *), void *arg, struct audio_params *param) 1065 { 1066 struct maestro_softc *sc = (struct maestro_softc *)hdl; 1067 1068 mtx_enter(&audio_lock); 1069 sc->record.mode |= MAESTRO_RUNNING; 1070 sc->record.blocksize = blksize; 1071 1072 maestro_channel_start(&sc->record); 1073 1074 sc->record.threshold = sc->record.start; 1075 maestro_update_timer(sc); 1076 mtx_leave(&audio_lock); 1077 return 0; 1078 } 1079 1080 void 1081 maestro_channel_start(struct maestro_channel *ch) 1082 { 1083 struct maestro_softc *sc = ch->sc; 1084 int n = ch->num; 1085 int aputype; 1086 wcreg_t wcreg = (sc->physaddr - 16) & WAVCACHE_CHCTL_ADDRTAG_MASK; 1087 1088 switch(ch->mode & (MAESTRO_STEREO | MAESTRO_8BIT)) { 1089 case 0: 1090 aputype = APUTYPE_16BITLINEAR; 1091 break; 1092 case MAESTRO_STEREO: 1093 aputype = APUTYPE_16BITSTEREO; 1094 break; 1095 case MAESTRO_8BIT: 1096 aputype = APUTYPE_8BITLINEAR; 1097 break; 1098 case MAESTRO_8BIT|MAESTRO_STEREO: 1099 aputype = APUTYPE_8BITSTEREO; 1100 break; 1101 } 1102 if (ch->mode & MAESTRO_UNSIGNED) 1103 wcreg |= WAVCACHE_CHCTL_U8; 1104 if ((ch->mode & MAESTRO_STEREO) == 0) { 1105 DPRINTF(("Setting mono parameters\n")); 1106 wp_apu_write(sc, n, APUREG_WAVESPACE, ch->wpwa & 0xff00); 1107 wp_apu_write(sc, n, APUREG_CURPTR, ch->current); 1108 wp_apu_write(sc, n, APUREG_ENDPTR, ch->end); 1109 wp_apu_write(sc, n, APUREG_LOOPLEN, ch->end - ch->start); 1110 wp_apu_write(sc, n, APUREG_AMPLITUDE, 0xe800); 1111 wp_apu_write(sc, n, APUREG_POSITION, 0x8f00 1112 | (RADIUS_CENTERCIRCLE << APU_RADIUS_SHIFT) 1113 | (PAN_FRONT << APU_PAN_SHIFT)); 1114 wp_apu_write(sc, n, APUREG_FREQ_LOBYTE, APU_plus6dB 1115 | ((ch->dv & 0xff) << APU_FREQ_LOBYTE_SHIFT)); 1116 wp_apu_write(sc, n, APUREG_FREQ_HIWORD, ch->dv >> 8); 1117 wc_ctrl_write(sc, n, wcreg); 1118 wp_apu_write(sc, n, APUREG_APUTYPE, 1119 (aputype << APU_APUTYPE_SHIFT) | APU_DMA_ENABLED | 0xf); 1120 } else { 1121 wcreg |= WAVCACHE_CHCTL_STEREO; 1122 DPRINTF(("Setting stereo parameters\n")); 1123 wp_apu_write(sc, n+1, APUREG_WAVESPACE, ch->wpwa & 0xff00); 1124 wp_apu_write(sc, n+1, APUREG_CURPTR, ch->current); 1125 wp_apu_write(sc, n+1, APUREG_ENDPTR, ch->end); 1126 wp_apu_write(sc, n+1, APUREG_LOOPLEN, ch->end - ch->start); 1127 wp_apu_write(sc, n+1, APUREG_AMPLITUDE, 0xe800); 1128 wp_apu_write(sc, n+1, APUREG_POSITION, 0x8f00 1129 | (RADIUS_CENTERCIRCLE << APU_RADIUS_SHIFT) 1130 | (PAN_LEFT << APU_PAN_SHIFT)); 1131 wp_apu_write(sc, n+1, APUREG_FREQ_LOBYTE, APU_plus6dB 1132 | ((ch->dv & 0xff) << APU_FREQ_LOBYTE_SHIFT)); 1133 wp_apu_write(sc, n+1, APUREG_FREQ_HIWORD, ch->dv >> 8); 1134 if (ch->mode & MAESTRO_8BIT) 1135 wp_apu_write(sc, n, APUREG_WAVESPACE, 1136 ch->wpwa & 0xff00); 1137 else 1138 wp_apu_write(sc, n, APUREG_WAVESPACE, 1139 (ch->wpwa|(APU_STEREO >> 1)) & 0xff00); 1140 wp_apu_write(sc, n, APUREG_CURPTR, ch->current); 1141 wp_apu_write(sc, n, APUREG_ENDPTR, ch->end); 1142 wp_apu_write(sc, n, APUREG_LOOPLEN, ch->end - ch->start); 1143 wp_apu_write(sc, n, APUREG_AMPLITUDE, 0xe800); 1144 wp_apu_write(sc, n, APUREG_POSITION, 0x8f00 1145 | (RADIUS_CENTERCIRCLE << APU_RADIUS_SHIFT) 1146 | (PAN_RIGHT << APU_PAN_SHIFT)); 1147 wp_apu_write(sc, n, APUREG_FREQ_LOBYTE, APU_plus6dB 1148 | ((ch->dv & 0xff) << APU_FREQ_LOBYTE_SHIFT)); 1149 wp_apu_write(sc, n, APUREG_FREQ_HIWORD, ch->dv >> 8); 1150 wc_ctrl_write(sc, n, wcreg); 1151 wc_ctrl_write(sc, n+1, wcreg); 1152 wp_apu_write(sc, n, APUREG_APUTYPE, 1153 (aputype << APU_APUTYPE_SHIFT) | APU_DMA_ENABLED | 0xf); 1154 wp_apu_write(sc, n+1, APUREG_APUTYPE, 1155 (aputype << APU_APUTYPE_SHIFT) | APU_DMA_ENABLED | 0xf); 1156 } 1157 } 1158 1159 int 1160 maestro_trigger_output(void *hdl, void *start, void *end, int blksize, 1161 void (*intr)(void *), void *arg, struct audio_params *param) 1162 { 1163 struct maestro_softc *sc = (struct maestro_softc *)hdl; 1164 u_int offset = ((caddr_t)start - sc->dmabase) >> 1; 1165 u_int size = ((char *)end - (char *)start) >> 1; 1166 1167 mtx_enter(&audio_lock); 1168 sc->play.mode |= MAESTRO_RUNNING; 1169 sc->play.wpwa = APU_USE_SYSMEM | (offset >> 8); 1170 DPRINTF(("maestro_trigger_output: start=%p, end=%p, blksize=%x ", 1171 start, end, blksize)); 1172 DPRINTF(("offset = %x, size=%x\n", offset, size)); 1173 1174 sc->play.intr = intr; 1175 sc->play.intr_arg = arg; 1176 sc->play.blocksize = blksize; 1177 sc->play.end = offset+size; 1178 sc->play.start = offset; 1179 sc->play.current = sc->play.start; 1180 if ((sc->play.mode & (MAESTRO_STEREO | MAESTRO_8BIT)) == MAESTRO_STEREO) { 1181 sc->play.wpwa >>= 1; 1182 sc->play.start >>= 1; 1183 sc->play.end >>= 1; 1184 sc->play.blocksize >>= 1; 1185 } 1186 maestro_channel_start(&sc->play); 1187 1188 sc->play.threshold = sc->play.start; 1189 maestro_update_timer(sc); 1190 mtx_leave(&audio_lock); 1191 return 0; 1192 } 1193 1194 /* ----------------------------- 1195 * Codec interface 1196 */ 1197 1198 enum ac97_host_flags 1199 maestro_codec_flags(void *self) 1200 { 1201 return AC97_HOST_DONT_READ; 1202 } 1203 1204 int 1205 maestro_read_codec(void *self, u_int8_t regno, u_int16_t *datap) 1206 { 1207 struct maestro_softc *sc = (struct maestro_softc *)self; 1208 int t; 1209 1210 /* We have to wait for a SAFE time to write addr/data */ 1211 for (t = 0; t < 20; t++) { 1212 if ((bus_space_read_1(sc->iot, sc->ioh, PORT_CODEC_STAT) 1213 & CODEC_STAT_MASK) != CODEC_STAT_PROGLESS) 1214 break; 1215 DELAY(2); /* 20.8us / 13 */ 1216 } 1217 if (t == 20) 1218 printf("%s: maestro_read_codec() PROGLESS timed out.\n", 1219 sc->dev.dv_xname); 1220 /* XXX return 1 */ 1221 1222 bus_space_write_1(sc->iot, sc->ioh, PORT_CODEC_CMD, 1223 CODEC_CMD_READ | regno); 1224 DELAY(21); /* AC97 cycle = 20.8usec */ 1225 1226 /* Wait for data retrieve */ 1227 for (t = 0; t < 20; t++) { 1228 if ((bus_space_read_1(sc->iot, sc->ioh, PORT_CODEC_STAT) 1229 & CODEC_STAT_MASK) == CODEC_STAT_RW_DONE) 1230 break; 1231 DELAY(2); /* 20.8us / 13 */ 1232 } 1233 if (t == 20) 1234 /* Timed out, but perform dummy read. */ 1235 printf("%s: maestro_read_codec() RW_DONE timed out.\n", 1236 sc->dev.dv_xname); 1237 1238 *datap = bus_space_read_2(sc->iot, sc->ioh, PORT_CODEC_REG); 1239 return 0; 1240 } 1241 1242 int 1243 maestro_write_codec(void *self, u_int8_t regno, u_int16_t data) 1244 { 1245 struct maestro_softc *sc = (struct maestro_softc *)self; 1246 int t; 1247 1248 /* We have to wait for a SAFE time to write addr/data */ 1249 for (t = 0; t < 20; t++) { 1250 if ((bus_space_read_1(sc->iot, sc->ioh, PORT_CODEC_STAT) 1251 & CODEC_STAT_MASK) != CODEC_STAT_PROGLESS) 1252 break; 1253 DELAY(2); /* 20.8us / 13 */ 1254 } 1255 if (t == 20) { 1256 /* Timed out. Abort writing. */ 1257 printf("%s: maestro_write_codec() PROGLESS timed out.\n", 1258 sc->dev.dv_xname); 1259 return 1; 1260 } 1261 1262 bus_space_write_2(sc->iot, sc->ioh, PORT_CODEC_REG, data); 1263 bus_space_write_1(sc->iot, sc->ioh, PORT_CODEC_CMD, 1264 CODEC_CMD_WRITE | regno); 1265 1266 return 0; 1267 } 1268 1269 int 1270 maestro_attach_codec(void *self, struct ac97_codec_if *cif) 1271 { 1272 struct maestro_softc *sc = (struct maestro_softc *)self; 1273 1274 sc->codec_if = cif; 1275 return 0; 1276 } 1277 1278 void 1279 maestro_reset_codec(void *self UNUSED) 1280 { 1281 } 1282 1283 void 1284 maestro_initcodec(void *self) 1285 { 1286 struct maestro_softc *sc = (struct maestro_softc *)self; 1287 u_int16_t data; 1288 1289 if (bus_space_read_4(sc->iot, sc->ioh, PORT_RINGBUS_CTRL) 1290 & RINGBUS_CTRL_ACLINK_ENABLED) { 1291 bus_space_write_4(sc->iot, sc->ioh, PORT_RINGBUS_CTRL, 0); 1292 DELAY(104); /* 20.8us * (4 + 1) */ 1293 } 1294 /* XXX - 2nd codec should be looked at. */ 1295 bus_space_write_4(sc->iot, sc->ioh, 1296 PORT_RINGBUS_CTRL, RINGBUS_CTRL_AC97_SWRESET); 1297 DELAY(2); 1298 bus_space_write_4(sc->iot, sc->ioh, 1299 PORT_RINGBUS_CTRL, RINGBUS_CTRL_ACLINK_ENABLED); 1300 DELAY(21); 1301 1302 maestro_read_codec(sc, 0, &data); 1303 if ((bus_space_read_1(sc->iot, sc->ioh, PORT_CODEC_STAT) 1304 & CODEC_STAT_MASK) != 0) { 1305 bus_space_write_4(sc->iot, sc->ioh, 1306 PORT_RINGBUS_CTRL, 0); 1307 DELAY(21); 1308 1309 /* Try cold reset. */ 1310 printf("%s: resetting codec\n", sc->dev.dv_xname); 1311 1312 data = bus_space_read_2(sc->iot, sc->ioh, PORT_GPIO_DIR); 1313 if (pci_conf_read(sc->pc, sc->pt, 0x58) & 1) 1314 data |= 0x10; 1315 data |= 0x009 & 1316 ~bus_space_read_2(sc->iot, sc->ioh, PORT_GPIO_DATA); 1317 bus_space_write_2(sc->iot, sc->ioh, 1318 PORT_GPIO_MASK, 0xff6); 1319 bus_space_write_2(sc->iot, sc->ioh, 1320 PORT_GPIO_DIR, data | 0x009); 1321 bus_space_write_2(sc->iot, sc->ioh, 1322 PORT_GPIO_DATA, 0x000); 1323 DELAY(2); 1324 bus_space_write_2(sc->iot, sc->ioh, 1325 PORT_GPIO_DATA, 0x001); 1326 DELAY(1); 1327 bus_space_write_2(sc->iot, sc->ioh, 1328 PORT_GPIO_DATA, 0x009); 1329 DELAY(500000); 1330 bus_space_write_2(sc->iot, sc->ioh, 1331 PORT_GPIO_DIR, data); 1332 DELAY(84); /* 20.8us * 4 */ 1333 bus_space_write_4(sc->iot, sc->ioh, 1334 PORT_RINGBUS_CTRL, RINGBUS_CTRL_ACLINK_ENABLED); 1335 DELAY(21); 1336 } 1337 1338 /* Check the codec to see is still busy */ 1339 if ((bus_space_read_1(sc->iot, sc->ioh, PORT_CODEC_STAT) & 1340 CODEC_STAT_MASK) != 0) { 1341 printf("%s: codec failure\n", sc->dev.dv_xname); 1342 } 1343 } 1344 1345 /* ----------------------------- 1346 * Power management interface 1347 */ 1348 1349 int 1350 maestro_activate(struct device *self, int act) 1351 { 1352 struct maestro_softc *sc = (struct maestro_softc *)self; 1353 1354 switch (act) { 1355 case DVACT_SUSPEND: 1356 /* Power down device on shutdown. */ 1357 DPRINTF(("maestro: power down\n")); 1358 if (sc->record.mode & MAESTRO_RUNNING) { 1359 sc->record.current = wp_apu_read(sc, sc->record.num, APUREG_CURPTR); 1360 maestro_channel_stop(&sc->record); 1361 } 1362 if (sc->play.mode & MAESTRO_RUNNING) { 1363 sc->play.current = wp_apu_read(sc, sc->play.num, APUREG_CURPTR); 1364 maestro_channel_stop(&sc->play); 1365 } 1366 1367 wp_stoptimer(sc); 1368 1369 /* Power down everything except clock. */ 1370 bus_space_write_2(sc->iot, sc->ioh, PORT_HOSTINT_CTRL, 0); 1371 maestro_write_codec(sc, AC97_REG_POWER, 0xdf00); 1372 DELAY(20); 1373 bus_space_write_4(sc->iot, sc->ioh, PORT_RINGBUS_CTRL, 0); 1374 DELAY(1); 1375 break; 1376 case DVACT_RESUME: 1377 /* Power up device on resume. */ 1378 DPRINTF(("maestro: power resume\n")); 1379 maestro_init(sc); 1380 /* Restore codec settings */ 1381 if (sc->play.mode & MAESTRO_RUNNING) 1382 maestro_channel_start(&sc->play); 1383 if (sc->record.mode & MAESTRO_RUNNING) 1384 maestro_channel_start(&sc->record); 1385 maestro_update_timer(sc); 1386 break; 1387 } 1388 return 0; 1389 } 1390 1391 void 1392 maestro_channel_advance_dma(struct maestro_channel *ch) 1393 { 1394 wpreg_t pos; 1395 #ifdef AUDIO_DEBUG 1396 maestrointr_called++; 1397 #endif 1398 for (;;) { 1399 pos = wp_apu_read(ch->sc, ch->num, APUREG_CURPTR); 1400 /* Are we still processing the current dma block ? */ 1401 if (pos >= ch->threshold && 1402 pos < ch->threshold + ch->blocksize/2) 1403 break; 1404 ch->threshold += ch->blocksize/2; 1405 if (ch->threshold >= ch->end) 1406 ch->threshold = ch->start; 1407 (*ch->intr)(ch->intr_arg); 1408 #ifdef AUDIO_DEBUG 1409 maestrodma_effective++; 1410 #endif 1411 } 1412 1413 #ifdef AUDIO_DEBUG 1414 if (maestrodebug && maestrointr_called % 64 == 0) 1415 printf("maestro: dma advanced %lu for %lu calls\n", 1416 maestrodma_effective, maestrointr_called); 1417 #endif 1418 } 1419 1420 /* Some maestro makes sometimes get desynchronized in stereo mode. */ 1421 void 1422 maestro_channel_suppress_jitter(struct maestro_channel *ch) 1423 { 1424 int cp, diff; 1425 1426 /* Verify that both channels are not too far off. */ 1427 cp = wp_apu_read(ch->sc, ch->num, APUREG_CURPTR); 1428 diff = wp_apu_read(ch->sc, ch->num+1, APUREG_CURPTR) - cp; 1429 if (diff > 4 || diff < -4) 1430 /* Otherwise, directly resynch the 2nd channel. */ 1431 bus_space_write_2(ch->sc->iot, ch->sc->ioh, 1432 PORT_DSP_DATA, cp); 1433 } 1434 1435 /* ----------------------------- 1436 * Interrupt handler interface 1437 */ 1438 int 1439 maestro_intr(void *arg) 1440 { 1441 struct maestro_softc *sc = (struct maestro_softc *)arg; 1442 u_int16_t status; 1443 1444 status = bus_space_read_1(sc->iot, sc->ioh, PORT_HOSTINT_STAT); 1445 if (status == 0) 1446 return 0; /* Not for us? */ 1447 1448 mtx_enter(&audio_lock); 1449 1450 /* Acknowledge all. */ 1451 bus_space_write_2(sc->iot, sc->ioh, PORT_INT_STAT, 1); 1452 bus_space_write_1(sc->iot, sc->ioh, PORT_HOSTINT_STAT, status); 1453 1454 /* Hardware volume support */ 1455 if (status & HOSTINT_STAT_HWVOL && sc->codec_if != NULL) { 1456 int n, i, delta, v; 1457 mixer_ctrl_t hwvol; 1458 1459 n = bus_space_read_1(sc->iot, sc->ioh, PORT_HWVOL_MASTER); 1460 /* Special case: Mute key */ 1461 if (n & 0x11) { 1462 hwvol.type = AUDIO_MIXER_ENUM; 1463 hwvol.dev = 1464 sc->codec_if->vtbl->get_portnum_by_name(sc->codec_if, 1465 AudioCoutputs, AudioNmaster, AudioNmute); 1466 sc->codec_if->vtbl->mixer_get_port(sc->codec_if, &hwvol); 1467 hwvol.un.ord = !hwvol.un.ord; 1468 } else { 1469 hwvol.type = AUDIO_MIXER_VALUE; 1470 hwvol.un.value.num_channels = 2; 1471 hwvol.dev = 1472 sc->codec_if->vtbl->get_portnum_by_name( 1473 sc->codec_if, AudioCoutputs, AudioNmaster, 1474 NULL); 1475 sc->codec_if->vtbl->mixer_get_port(sc->codec_if, &hwvol); 1476 /* XXX AC'97 yields five bits for master volume. */ 1477 delta = (n - MIDDLE_VOLUME)/STEP_VOLUME * 8; 1478 for (i = 0; i < hwvol.un.value.num_channels; i++) { 1479 v = ((int)hwvol.un.value.level[i]) + delta; 1480 if (v < 0) 1481 v = 0; 1482 else if (v > 255) 1483 v = 255; 1484 hwvol.un.value.level[i] = v; 1485 } 1486 } 1487 sc->codec_if->vtbl->mixer_set_port(sc->codec_if, &hwvol); 1488 /* Reset to compute next diffs */ 1489 bus_space_write_1(sc->iot, sc->ioh, PORT_HWVOL_MASTER, 1490 MIDDLE_VOLUME); 1491 } 1492 1493 if (sc->play.mode & MAESTRO_RUNNING) { 1494 maestro_channel_advance_dma(&sc->play); 1495 if (sc->play.mode & MAESTRO_STEREO) 1496 maestro_channel_suppress_jitter(&sc->play); 1497 } 1498 1499 if (sc->record.mode & MAESTRO_RUNNING) 1500 maestro_channel_advance_dma(&sc->record); 1501 1502 mtx_leave(&audio_lock); 1503 return 1; 1504 } 1505 1506 /* ----------------------------- 1507 * Hardware interface 1508 */ 1509 1510 /* Codec/Ringbus */ 1511 1512 void 1513 ringbus_setdest(struct maestro_softc *sc, int src, int dest) 1514 { 1515 u_int32_t data; 1516 1517 data = bus_space_read_4(sc->iot, sc->ioh, PORT_RINGBUS_CTRL); 1518 data &= ~(0xfU << src); 1519 data |= (0xfU & dest) << src; 1520 bus_space_write_4(sc->iot, sc->ioh, PORT_RINGBUS_CTRL, data); 1521 } 1522 1523 /* Wave Processor */ 1524 1525 wpreg_t 1526 wp_reg_read(struct maestro_softc *sc, int reg) 1527 { 1528 bus_space_write_2(sc->iot, sc->ioh, PORT_DSP_INDEX, reg); 1529 return bus_space_read_2(sc->iot, sc->ioh, PORT_DSP_DATA); 1530 } 1531 1532 void 1533 wp_reg_write(struct maestro_softc *sc, int reg, wpreg_t data) 1534 { 1535 bus_space_write_2(sc->iot, sc->ioh, PORT_DSP_INDEX, reg); 1536 bus_space_write_2(sc->iot, sc->ioh, PORT_DSP_DATA, data); 1537 } 1538 1539 static void 1540 apu_setindex(struct maestro_softc *sc, int reg) 1541 { 1542 int t; 1543 1544 wp_reg_write(sc, WPREG_CRAM_PTR, reg); 1545 /* Sometimes WP fails to set apu register index. */ 1546 for (t = 0; t < 1000; t++) { 1547 if (bus_space_read_2(sc->iot, sc->ioh, 1548 PORT_DSP_DATA) == reg) 1549 break; 1550 bus_space_write_2(sc->iot, sc->ioh, PORT_DSP_DATA, reg); 1551 } 1552 if (t == 1000) 1553 printf("%s: apu_setindex() timeout\n", sc->dev.dv_xname); 1554 } 1555 1556 wpreg_t 1557 wp_apu_read(struct maestro_softc *sc, int ch, int reg) 1558 { 1559 wpreg_t ret; 1560 1561 apu_setindex(sc, ((unsigned)ch << 4) + reg); 1562 ret = wp_reg_read(sc, WPREG_DATA_PORT); 1563 return ret; 1564 } 1565 1566 void 1567 wp_apu_write(struct maestro_softc *sc, int ch, int reg, wpreg_t data) 1568 { 1569 int t; 1570 1571 apu_setindex(sc, ((unsigned)ch << 4) + reg); 1572 wp_reg_write(sc, WPREG_DATA_PORT, data); 1573 for (t = 0; t < 1000; t++) { 1574 if (bus_space_read_2(sc->iot, sc->ioh, PORT_DSP_DATA) == data) 1575 break; 1576 bus_space_write_2(sc->iot, sc->ioh, PORT_DSP_DATA, data); 1577 } 1578 if (t == 1000) 1579 printf("%s: wp_apu_write() timeout\n", sc->dev.dv_xname); 1580 } 1581 1582 void 1583 wp_settimer(struct maestro_softc *sc, u_int freq) 1584 { 1585 u_int clock = 48000 << 2; 1586 u_int prescale = 0, divide = (freq != 0) ? (clock / freq) : ~0; 1587 1588 if (divide < 4) 1589 divide = 4; 1590 else if (divide > 32 << 8) 1591 divide = 32 << 8; 1592 1593 for (; divide > 32 << 1; divide >>= 1) 1594 prescale++; 1595 divide = (divide + 1) >> 1; 1596 1597 for (; prescale < 7 && divide > 2 && !(divide & 1); divide >>= 1) 1598 prescale++; 1599 1600 wp_reg_write(sc, WPREG_TIMER_ENABLE, 0); 1601 wp_reg_write(sc, WPREG_TIMER_FREQ, 1602 (prescale << WP_TIMER_FREQ_PRESCALE_SHIFT) | (divide - 1)); 1603 wp_reg_write(sc, WPREG_TIMER_ENABLE, 1); 1604 } 1605 1606 void 1607 wp_starttimer(struct maestro_softc *sc) 1608 { 1609 wp_reg_write(sc, WPREG_TIMER_START, 1); 1610 } 1611 1612 void 1613 wp_stoptimer(struct maestro_softc *sc) 1614 { 1615 wp_reg_write(sc, WPREG_TIMER_START, 0); 1616 bus_space_write_2(sc->iot, sc->ioh, PORT_INT_STAT, 1); 1617 } 1618 1619 /* WaveCache */ 1620 1621 wcreg_t 1622 wc_reg_read(struct maestro_softc *sc, int reg) 1623 { 1624 bus_space_write_2(sc->iot, sc->ioh, PORT_WAVCACHE_INDEX, reg); 1625 return bus_space_read_2(sc->iot, sc->ioh, PORT_WAVCACHE_DATA); 1626 } 1627 1628 void 1629 wc_reg_write(struct maestro_softc *sc, int reg, wcreg_t data) 1630 { 1631 bus_space_write_2(sc->iot, sc->ioh, PORT_WAVCACHE_INDEX, reg); 1632 bus_space_write_2(sc->iot, sc->ioh, PORT_WAVCACHE_DATA, data); 1633 } 1634 1635 u_int16_t 1636 wc_ctrl_read(struct maestro_softc *sc, int ch) 1637 { 1638 return wc_reg_read(sc, ch << 3); 1639 } 1640 1641 void 1642 wc_ctrl_write(struct maestro_softc *sc, int ch, wcreg_t data) 1643 { 1644 wc_reg_write(sc, ch << 3, data); 1645 } 1646 1647 /* ----------------------------- 1648 * Simple zone allocator. 1649 * (All memory allocated in advance) 1650 */ 1651 1652 salloc_t 1653 salloc_new(caddr_t addr, size_t size, int nzones) 1654 { 1655 struct salloc_pool *pool; 1656 struct salloc_zone *space; 1657 int i; 1658 1659 pool = malloc(sizeof *pool + nzones * sizeof pool->zones[0], 1660 M_TEMP, M_NOWAIT); 1661 if (pool == NULL) 1662 return NULL; 1663 SLIST_INIT(&pool->free); 1664 SLIST_INIT(&pool->used); 1665 SLIST_INIT(&pool->spare); 1666 /* Espie says the following line is obvious */ 1667 pool->zones = (struct salloc_zone *)(pool + 1); 1668 for (i = 1; i < nzones; i++) 1669 SLIST_INSERT_HEAD(&pool->spare, &pool->zones[i], link); 1670 space = &pool->zones[0]; 1671 space->addr = addr; 1672 space->size = size; 1673 SLIST_INSERT_HEAD(&pool->free, space, link); 1674 return pool; 1675 } 1676 1677 void 1678 salloc_destroy(salloc_t pool) 1679 { 1680 free(pool, M_TEMP, 0); 1681 } 1682 1683 void 1684 salloc_insert(salloc_t pool, struct salloc_head *head, struct salloc_zone *zone, 1685 int merge) 1686 { 1687 struct salloc_zone *prev, *next; 1688 1689 /* 1690 * Insert a zone into an ordered list of zones, possibly 1691 * merging adjacent zones. 1692 */ 1693 prev = NULL; 1694 SLIST_FOREACH(next, head, link) { 1695 if (next->addr > zone->addr) 1696 break; 1697 prev = next; 1698 } 1699 1700 if (merge && prev && prev->addr + prev->size == zone->addr) { 1701 prev->size += zone->size; 1702 SLIST_INSERT_HEAD(&pool->spare, zone, link); 1703 zone = prev; 1704 } else if (prev) 1705 SLIST_INSERT_AFTER(prev, zone, link); 1706 else 1707 SLIST_INSERT_HEAD(head, zone, link); 1708 if (merge && next && zone->addr + zone->size == next->addr) { 1709 zone->size += next->size; 1710 SLIST_REMOVE(head, next, salloc_zone, link); 1711 SLIST_INSERT_HEAD(&pool->spare, next, link); 1712 } 1713 } 1714 1715 caddr_t 1716 salloc_alloc(salloc_t pool, size_t size) 1717 { 1718 struct salloc_zone *zone, *uzone; 1719 1720 SLIST_FOREACH(zone, &pool->free, link) 1721 if (zone->size >= size) 1722 break; 1723 if (zone == NULL) 1724 return NULL; 1725 if (zone->size == size) { 1726 SLIST_REMOVE(&pool->free, zone, salloc_zone, link); 1727 uzone = zone; 1728 } else { 1729 uzone = SLIST_FIRST(&pool->spare); 1730 if (uzone == NULL) 1731 return NULL; /* XXX */ 1732 SLIST_REMOVE_HEAD(&pool->spare, link); 1733 uzone->size = size; 1734 uzone->addr = zone->addr; 1735 zone->size -= size; 1736 zone->addr += size; 1737 } 1738 salloc_insert(pool, &pool->used, uzone, 0); 1739 return uzone->addr; 1740 } 1741 1742 void 1743 salloc_free(salloc_t pool, caddr_t addr) 1744 { 1745 struct salloc_zone *zone; 1746 1747 SLIST_FOREACH(zone, &pool->used, link) 1748 if (zone->addr == addr) 1749 break; 1750 #ifdef DIAGNOSTIC 1751 if (zone == NULL) 1752 panic("salloc_free: freeing unallocated memory"); 1753 #endif 1754 SLIST_REMOVE(&pool->used, zone, salloc_zone, link); 1755 salloc_insert(pool, &pool->free, zone, 1); 1756 } 1757