1 /* $OpenBSD: jmb.c,v 1.7 2008/03/27 09:21:59 dlg Exp $ */ 2 3 /* 4 * Copyright (c) 2007 David Gwynne <dlg@openbsd.org> 5 * 6 * Permission to use, copy, modify, and distribute this software for any 7 * purpose with or without fee is hereby granted, provided that the above 8 * copyright notice and this permission notice appear in all copies. 9 * 10 * THE SOFTWARE IS PROVIDED "AS IS" AND THE AUTHOR DISCLAIMS ALL WARRANTIES 11 * WITH REGARD TO THIS SOFTWARE INCLUDING ALL IMPLIED WARRANTIES OF 12 * MERCHANTABILITY AND FITNESS. IN NO EVENT SHALL THE AUTHOR BE LIABLE FOR 13 * ANY SPECIAL, DIRECT, INDIRECT, OR CONSEQUENTIAL DAMAGES OR ANY DAMAGES 14 * WHATSOEVER RESULTING FROM LOSS OF USE, DATA OR PROFITS, WHETHER IN AN 15 * ACTION OF CONTRACT, NEGLIGENCE OR OTHER TORTIOUS ACTION, ARISING OUT OF 16 * OR IN CONNECTION WITH THE USE OR PERFORMANCE OF THIS SOFTWARE. 17 */ 18 19 #include <sys/param.h> 20 #include <sys/systm.h> 21 #include <sys/buf.h> 22 #include <sys/kernel.h> 23 #include <sys/malloc.h> 24 #include <sys/device.h> 25 #include <sys/proc.h> 26 #include <sys/queue.h> 27 28 #include <machine/bus.h> 29 30 #include <dev/pci/pcireg.h> 31 #include <dev/pci/pcivar.h> 32 #include <dev/pci/pcidevs.h> 33 34 /* JMicron registers */ 35 #define JM_PCI_CTL0 0x40 /* control register 0 */ 36 #define JM_PCI_CTL0_ROM_EN (1<<31) /* External Option ROM */ 37 #define JM_PCI_CTL0_IDWR_EN (1<<30) /* Device ID Write */ 38 #define JM_PCI_CTL0_MSI64_EN (1<<25) /* 64bit MSI Addr Mode */ 39 #define JM_PCI_CTL0_MSI_EN (1<<24) /* MSI Addr Mode */ 40 #define JM_PCI_CTL0_IDEDMA_CFG (1<<23) /* PCIIDE DMA Chan Cfg */ 41 #define JM_PCI_CTL0_PCIIDE_CS (1<<22) /* PCIIDE channels Swap */ 42 #define JM_PCI_CTL0_SATA_PS (1<<21) /* SATA channel M/S swap */ 43 #define JM_PCI_CTL0_AHCI_PS (1<<20) /* SATA AHCI ports swap */ 44 #define JM_PCI_CTL0_F1_SUBCLASS_M 0xc0000 /* subclass for func 1 */ 45 #define JM_PCI_CTL0_F0_SUBCLASS_M 0x30000 /* subclass for func 0 */ 46 #define JM_PCI_CTL0_SUBCLASS_IDE 0x0 /* IDE Controller */ 47 #define JM_PCI_CTL0_SUBCLASS_RAID 0x1 /* RAID Controller */ 48 #define JM_PCI_CTL0_SUBCLASS_AHCI 0x2 /* AHCI Controller */ 49 #define JM_PCI_CTL0_SUBCLASS_OTHER 0x3 /* Other Mass Storage */ 50 #define JM_PCI_CTL0_F1_SUBCLASS(_m) ((_m)<<18) /* subclass for func 1 */ 51 #define JM_PCI_CTL0_F0_SUBCLASS(_m) ((_m)<<16) /* subclass for func 0 */ 52 #define JM_PCI_CTL0_SATA1_AHCI (1<<15) /* SATA port 1 AHCI enable */ 53 #define JM_PCI_CTL0_SATA1_IDE (1<<14) /* SATA port 1 IDE enable */ 54 #define JM_PCI_CTL0_SATA0_AHCI (1<<13) /* SATA port 0 AHCI enable */ 55 #define JM_PCI_CTL0_SATA0_IDE (1<<12) /* SATA port 0 PCIIDE enable */ 56 #define JM_PCI_CTL0_AHCI_F1 (1<<9) /* AHCI on function 1 */ 57 #define JM_PCI_CTL0_AHCI_EN (1<<8) /* ACHI enable */ 58 #define JM_PCI_CTL0_PATA0_RST (1<<6) /* PATA port 0 reset */ 59 #define JM_PCI_CTL0_PATA0_EN (1<<5) /* PATA port 0 enable */ 60 #define JM_PCI_CTL0_PATA0_SEC (1<<4) /* PATA 0 enable on 2nd chan */ 61 #define JM_PCI_CTL0_PATA0_40P (1<<3) /* PATA 0 40pin cable */ 62 #define JM_PCI_CTL0_PCIIDE_F1 (1<<1) /* PCIIDE on function 1 */ 63 #define JM_PCI_CTL0_PATA0_PRI (1<<0) /* PATA 0 enable on 1st chan */ 64 65 #define JM_PCI_CTL5 0x80 /* control register 8 */ 66 #define JM_PCI_CTL5_PATA1_PRI (1<<24) /* force PATA 1 on chan0 */ 67 68 int jmb_match(struct device *, void *, void *); 69 void jmb_attach(struct device *, struct device *, void *); 70 int jmb_print(void *, const char *); 71 72 struct jmb_softc { 73 struct device sc_dev; 74 }; 75 76 struct cfattach jmb_ca = { 77 sizeof(struct jmb_softc), 78 jmb_match, 79 jmb_attach, 80 config_detach_children 81 }; 82 83 struct cfdriver jmb_cd = { 84 NULL, "jmb", DV_DULL 85 }; 86 87 static const struct pci_matchid jmb_devices[] = { 88 { PCI_VENDOR_JMICRON, PCI_PRODUCT_JMICRON_JMB360 }, 89 { PCI_VENDOR_JMICRON, PCI_PRODUCT_JMICRON_JMB361 }, 90 { PCI_VENDOR_JMICRON, PCI_PRODUCT_JMICRON_JMB362 }, 91 { PCI_VENDOR_JMICRON, PCI_PRODUCT_JMICRON_JMB363 }, 92 { PCI_VENDOR_JMICRON, PCI_PRODUCT_JMICRON_JMB365 }, 93 { PCI_VENDOR_JMICRON, PCI_PRODUCT_JMICRON_JMB366 }, 94 { PCI_VENDOR_JMICRON, PCI_PRODUCT_JMICRON_JMB368 } 95 }; 96 97 int 98 jmb_match(struct device *parent, void *match, void *aux) 99 { 100 struct pci_attach_args *pa = aux; 101 102 return (pci_matchbyid(pa, jmb_devices, 103 sizeof(jmb_devices) / sizeof(jmb_devices[0])) * 3); 104 } 105 106 void 107 jmb_attach(struct device *parent, struct device *self, void *aux) 108 { 109 struct pci_attach_args *pa = aux, jpa; 110 u_int32_t ctl0, ctl5; 111 int sata = 0, pata = 0; 112 113 ctl0 = pci_conf_read(pa->pa_pc, pa->pa_tag, JM_PCI_CTL0); 114 ctl5 = pci_conf_read(pa->pa_pc, pa->pa_tag, JM_PCI_CTL5); 115 116 /* configure sata bits if it is on this function */ 117 if (pa->pa_function == (ISSET(ctl0, JM_PCI_CTL0_AHCI_F1) ? 1 : 0)) { 118 ctl0 &= ~(JM_PCI_CTL0_AHCI_EN | JM_PCI_CTL0_SATA0_IDE | 119 JM_PCI_CTL0_SATA0_AHCI | JM_PCI_CTL0_SATA1_IDE | 120 JM_PCI_CTL0_SATA1_AHCI); 121 122 switch (PCI_PRODUCT(pa->pa_id)) { 123 case PCI_PRODUCT_JMICRON_JMB360: 124 case PCI_PRODUCT_JMICRON_JMB361: 125 case PCI_PRODUCT_JMICRON_JMB362: 126 case PCI_PRODUCT_JMICRON_JMB363: 127 case PCI_PRODUCT_JMICRON_JMB365: 128 case PCI_PRODUCT_JMICRON_JMB366: 129 /* enable AHCI */ 130 ctl0 |= JM_PCI_CTL0_AHCI_EN | JM_PCI_CTL0_SATA0_AHCI | 131 JM_PCI_CTL0_SATA1_AHCI; 132 sata = 1; 133 break; 134 } 135 } 136 137 /* configure pata bits if it is on this function */ 138 if (pa->pa_function == (ISSET(ctl0, JM_PCI_CTL0_PCIIDE_F1) ? 1 : 0)) { 139 ctl0 &= ~(JM_PCI_CTL0_PCIIDE_CS | JM_PCI_CTL0_IDEDMA_CFG); 140 ctl5 &= ~JM_PCI_CTL5_PATA1_PRI; 141 142 switch (PCI_PRODUCT(pa->pa_id)) { 143 case PCI_PRODUCT_JMICRON_JMB366: 144 case PCI_PRODUCT_JMICRON_JMB365: 145 /* wire the second PATA port in the right place */ 146 ctl5 |= JM_PCI_CTL5_PATA1_PRI; 147 /* FALLTHROUGH */ 148 case PCI_PRODUCT_JMICRON_JMB363: 149 case PCI_PRODUCT_JMICRON_JMB361: 150 case PCI_PRODUCT_JMICRON_JMB368: 151 ctl0 |= JM_PCI_CTL0_PCIIDE_CS | JM_PCI_CTL0_IDEDMA_CFG; 152 pata = 1; 153 break; 154 } 155 } 156 157 pci_conf_write(pa->pa_pc, pa->pa_tag, JM_PCI_CTL0, ctl0); 158 pci_conf_write(pa->pa_pc, pa->pa_tag, JM_PCI_CTL5, ctl5); 159 160 printf("\n"); 161 162 jpa = *pa; 163 164 if (sata) { 165 /* tweak the class to look like ahci, then try to attach it */ 166 jpa.pa_class = (PCI_CLASS_MASS_STORAGE << PCI_CLASS_SHIFT) | 167 (PCI_SUBCLASS_MASS_STORAGE_SATA << PCI_SUBCLASS_SHIFT) | 168 (0x01 << PCI_INTERFACE_SHIFT); /* AHCI_PCI_INTERFACE */ 169 config_found(self, &jpa, jmb_print); 170 } 171 172 if (pata) { 173 /* set things up for pciide */ 174 jpa.pa_class = (PCI_CLASS_MASS_STORAGE << PCI_CLASS_SHIFT) | 175 (PCI_SUBCLASS_MASS_STORAGE_IDE << PCI_SUBCLASS_SHIFT) | 176 (0x85 << PCI_INTERFACE_SHIFT); 177 config_found(self, &jpa, jmb_print); 178 } 179 } 180 181 int 182 jmb_print(void *aux, const char *pnp) 183 { 184 struct pci_attach_args *pa = aux; 185 char devinfo[256]; 186 187 if (pnp != NULL) { 188 pci_devinfo(pa->pa_id, pa->pa_class, 1, devinfo, 189 sizeof(devinfo)); 190 printf("%s at %s", devinfo, pnp); 191 } 192 193 return (UNCONF); 194 } 195