1 /* $OpenBSD: ixgbe_x540.c,v 1.4 2015/05/20 14:34:27 mikeb Exp $ */ 2 3 /****************************************************************************** 4 5 Copyright (c) 2001-2013, Intel Corporation 6 All rights reserved. 7 8 Redistribution and use in source and binary forms, with or without 9 modification, are permitted provided that the following conditions are met: 10 11 1. Redistributions of source code must retain the above copyright notice, 12 this list of conditions and the following disclaimer. 13 14 2. Redistributions in binary form must reproduce the above copyright 15 notice, this list of conditions and the following disclaimer in the 16 documentation and/or other materials provided with the distribution. 17 18 3. Neither the name of the Intel Corporation nor the names of its 19 contributors may be used to endorse or promote products derived from 20 this software without specific prior written permission. 21 22 THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS" 23 AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE 24 IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE 25 ARE DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT OWNER OR CONTRIBUTORS BE 26 LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR 27 CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF 28 SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS 29 INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN 30 CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) 31 ARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE 32 POSSIBILITY OF SUCH DAMAGE. 33 34 ******************************************************************************/ 35 /* FreeBSD: src/sys/dev/ixgbe/ixgbe_x540.c 251964 Jun 18 21:28:19 2013 UTC */ 36 37 #include <dev/pci/ixgbe.h> 38 #include <dev/pci/ixgbe_type.h> 39 40 int32_t ixgbe_update_flash_X540(struct ixgbe_hw *hw); 41 int32_t ixgbe_poll_flash_update_done_X540(struct ixgbe_hw *hw); 42 int32_t ixgbe_get_swfw_sync_semaphore(struct ixgbe_hw *hw); 43 void ixgbe_release_swfw_sync_semaphore(struct ixgbe_hw *hw); 44 45 enum ixgbe_media_type ixgbe_get_media_type_X540(struct ixgbe_hw *hw); 46 int32_t ixgbe_setup_mac_link_X540(struct ixgbe_hw *hw, ixgbe_link_speed speed, 47 bool link_up_wait_to_complete); 48 int32_t ixgbe_reset_hw_X540(struct ixgbe_hw *hw); 49 int32_t ixgbe_start_hw_X540(struct ixgbe_hw *hw); 50 uint32_t ixgbe_get_supported_physical_layer_X540(struct ixgbe_hw *hw); 51 52 int32_t ixgbe_init_eeprom_params_X540(struct ixgbe_hw *hw); 53 int32_t ixgbe_read_eerd_X540(struct ixgbe_hw *hw, uint16_t offset, uint16_t *data); 54 int32_t ixgbe_write_eewr_X540(struct ixgbe_hw *hw, uint16_t offset, uint16_t data); 55 int32_t ixgbe_update_eeprom_checksum_X540(struct ixgbe_hw *hw); 56 int32_t ixgbe_validate_eeprom_checksum_X540(struct ixgbe_hw *hw, uint16_t *checksum_val); 57 uint16_t ixgbe_calc_eeprom_checksum_X540(struct ixgbe_hw *hw); 58 59 int32_t ixgbe_acquire_swfw_sync_X540(struct ixgbe_hw *hw, uint16_t mask); 60 void ixgbe_release_swfw_sync_X540(struct ixgbe_hw *hw, uint16_t mask); 61 62 int32_t ixgbe_blink_led_start_X540(struct ixgbe_hw *hw, uint32_t index); 63 int32_t ixgbe_blink_led_stop_X540(struct ixgbe_hw *hw, uint32_t index); 64 65 /** 66 * ixgbe_init_ops_X540 - Inits func ptrs and MAC type 67 * @hw: pointer to hardware structure 68 * 69 * Initialize the function pointers and assign the MAC type for X540. 70 * Does not touch the hardware. 71 **/ 72 int32_t ixgbe_init_ops_X540(struct ixgbe_hw *hw) 73 { 74 struct ixgbe_mac_info *mac = &hw->mac; 75 struct ixgbe_phy_info *phy = &hw->phy; 76 struct ixgbe_eeprom_info *eeprom = &hw->eeprom; 77 int32_t ret_val; 78 79 DEBUGFUNC("ixgbe_init_ops_X540"); 80 81 ret_val = ixgbe_init_phy_ops_generic(hw); 82 ret_val = ixgbe_init_ops_generic(hw); 83 84 /* EEPROM */ 85 eeprom->ops.init_params = &ixgbe_init_eeprom_params_X540; 86 eeprom->ops.read = &ixgbe_read_eerd_X540; 87 eeprom->ops.write = &ixgbe_write_eewr_X540; 88 eeprom->ops.update_checksum = &ixgbe_update_eeprom_checksum_X540; 89 eeprom->ops.validate_checksum = &ixgbe_validate_eeprom_checksum_X540; 90 eeprom->ops.calc_checksum = &ixgbe_calc_eeprom_checksum_X540; 91 92 /* PHY */ 93 phy->ops.init = &ixgbe_init_phy_ops_generic; 94 phy->ops.reset = NULL; 95 96 /* MAC */ 97 mac->ops.reset_hw = &ixgbe_reset_hw_X540; 98 mac->ops.enable_relaxed_ordering = &ixgbe_enable_relaxed_ordering_gen2; 99 mac->ops.get_media_type = &ixgbe_get_media_type_X540; 100 mac->ops.get_supported_physical_layer = 101 &ixgbe_get_supported_physical_layer_X540; 102 mac->ops.read_analog_reg8 = NULL; 103 mac->ops.write_analog_reg8 = NULL; 104 mac->ops.start_hw = &ixgbe_start_hw_X540; 105 mac->ops.acquire_swfw_sync = &ixgbe_acquire_swfw_sync_X540; 106 mac->ops.release_swfw_sync = &ixgbe_release_swfw_sync_X540; 107 mac->ops.disable_sec_rx_path = &ixgbe_disable_sec_rx_path_generic; 108 mac->ops.enable_sec_rx_path = &ixgbe_enable_sec_rx_path_generic; 109 110 /* RAR, Multicast, VLAN */ 111 mac->ops.set_vmdq = &ixgbe_set_vmdq_generic; 112 mac->ops.clear_vmdq = &ixgbe_clear_vmdq_generic; 113 mac->ops.insert_mac_addr = &ixgbe_insert_mac_addr_generic; 114 mac->rar_highwater = 1; 115 mac->ops.set_vfta = &ixgbe_set_vfta_generic; 116 mac->ops.clear_vfta = &ixgbe_clear_vfta_generic; 117 mac->ops.init_uta_tables = &ixgbe_init_uta_tables_generic; 118 119 /* Link */ 120 mac->ops.get_link_capabilities = 121 &ixgbe_get_copper_link_capabilities_generic; 122 mac->ops.setup_link = &ixgbe_setup_mac_link_X540; 123 mac->ops.check_link = &ixgbe_check_mac_link_generic; 124 125 mac->mcft_size = 128; 126 mac->vft_size = 128; 127 mac->num_rar_entries = 128; 128 mac->rx_pb_size = 384; 129 mac->max_tx_queues = 128; 130 mac->max_rx_queues = 128; 131 mac->max_msix_vectors = 0 /*ixgbe_get_pcie_msix_count_generic(hw)*/; 132 133 hw->mbx.ops.init_params = ixgbe_init_mbx_params_pf; 134 135 /* LEDs */ 136 mac->ops.blink_led_start = ixgbe_blink_led_start_X540; 137 mac->ops.blink_led_stop = ixgbe_blink_led_stop_X540; 138 139 return ret_val; 140 } 141 142 /** 143 * ixgbe_get_media_type_X540 - Get media type 144 * @hw: pointer to hardware structure 145 * 146 * Returns the media type (fiber, copper, backplane) 147 **/ 148 enum ixgbe_media_type ixgbe_get_media_type_X540(struct ixgbe_hw *hw) 149 { 150 return ixgbe_media_type_copper; 151 } 152 153 /** 154 * ixgbe_setup_mac_link_X540 - Sets the auto advertised capabilities 155 * @hw: pointer to hardware structure 156 * @speed: new link speed 157 * @autoneg_wait_to_complete: TRUE when waiting for completion is needed 158 **/ 159 int32_t ixgbe_setup_mac_link_X540(struct ixgbe_hw *hw, 160 ixgbe_link_speed speed, 161 bool autoneg_wait_to_complete) 162 { 163 DEBUGFUNC("ixgbe_setup_mac_link_X540"); 164 return hw->phy.ops.setup_link_speed(hw, speed, 165 autoneg_wait_to_complete); 166 } 167 168 /** 169 * ixgbe_reset_hw_X540 - Perform hardware reset 170 * @hw: pointer to hardware structure 171 * 172 * Resets the hardware by resetting the transmit and receive units, masks 173 * and clears all interrupts, and perform a reset. 174 **/ 175 int32_t ixgbe_reset_hw_X540(struct ixgbe_hw *hw) 176 { 177 int32_t status; 178 uint32_t ctrl, i; 179 180 DEBUGFUNC("ixgbe_reset_hw_X540"); 181 182 /* Call adapter stop to disable tx/rx and clear interrupts */ 183 status = hw->mac.ops.stop_adapter(hw); 184 if (status != IXGBE_SUCCESS) 185 goto reset_hw_out; 186 187 /* flush pending Tx transactions */ 188 ixgbe_clear_tx_pending(hw); 189 190 mac_reset_top: 191 ctrl = IXGBE_CTRL_RST; 192 ctrl |= IXGBE_READ_REG(hw, IXGBE_CTRL); 193 IXGBE_WRITE_REG(hw, IXGBE_CTRL, ctrl); 194 IXGBE_WRITE_FLUSH(hw); 195 196 /* Poll for reset bit to self-clear indicating reset is complete */ 197 for (i = 0; i < 10; i++) { 198 usec_delay(1); 199 ctrl = IXGBE_READ_REG(hw, IXGBE_CTRL); 200 if (!(ctrl & IXGBE_CTRL_RST_MASK)) 201 break; 202 } 203 204 if (ctrl & IXGBE_CTRL_RST_MASK) { 205 status = IXGBE_ERR_RESET_FAILED; 206 DEBUGOUT("Reset polling failed to complete.\n"); 207 } 208 msec_delay(100); 209 210 /* 211 * Double resets are required for recovery from certain error 212 * conditions. Between resets, it is necessary to stall to allow time 213 * for any pending HW events to complete. 214 */ 215 if (hw->mac.flags & IXGBE_FLAGS_DOUBLE_RESET_REQUIRED) { 216 hw->mac.flags &= ~IXGBE_FLAGS_DOUBLE_RESET_REQUIRED; 217 goto mac_reset_top; 218 } 219 220 /* Set the Rx packet buffer size. */ 221 IXGBE_WRITE_REG(hw, IXGBE_RXPBSIZE(0), 384 << IXGBE_RXPBSIZE_SHIFT); 222 223 /* Store the permanent mac address */ 224 hw->mac.ops.get_mac_addr(hw, hw->mac.perm_addr); 225 226 /* 227 * Store MAC address from RAR0, clear receive address registers, and 228 * clear the multicast table. Also reset num_rar_entries to 128, 229 * since we modify this value when programming the SAN MAC address. 230 */ 231 hw->mac.num_rar_entries = 128; 232 hw->mac.ops.init_rx_addrs(hw); 233 234 reset_hw_out: 235 return status; 236 } 237 238 /** 239 * ixgbe_start_hw_X540 - Prepare hardware for Tx/Rx 240 * @hw: pointer to hardware structure 241 * 242 * Starts the hardware using the generic start_hw function 243 * and the generation start_hw function. 244 * Then performs revision-specific operations, if any. 245 **/ 246 int32_t ixgbe_start_hw_X540(struct ixgbe_hw *hw) 247 { 248 int32_t ret_val = IXGBE_SUCCESS; 249 250 DEBUGFUNC("ixgbe_start_hw_X540"); 251 252 ret_val = ixgbe_start_hw_generic(hw); 253 if (ret_val != IXGBE_SUCCESS) 254 goto out; 255 256 ret_val = ixgbe_start_hw_gen2(hw); 257 258 out: 259 return ret_val; 260 } 261 262 /** 263 * ixgbe_get_supported_physical_layer_X540 - Returns physical layer type 264 * @hw: pointer to hardware structure 265 * 266 * Determines physical layer capabilities of the current configuration. 267 **/ 268 uint32_t ixgbe_get_supported_physical_layer_X540(struct ixgbe_hw *hw) 269 { 270 uint32_t physical_layer = IXGBE_PHYSICAL_LAYER_UNKNOWN; 271 uint16_t ext_ability = 0; 272 273 DEBUGFUNC("ixgbe_get_supported_physical_layer_X540"); 274 275 hw->phy.ops.read_reg(hw, IXGBE_MDIO_PHY_EXT_ABILITY, 276 IXGBE_MDIO_PMA_PMD_DEV_TYPE, &ext_ability); 277 if (ext_ability & IXGBE_MDIO_PHY_10GBASET_ABILITY) 278 physical_layer |= IXGBE_PHYSICAL_LAYER_10GBASE_T; 279 if (ext_ability & IXGBE_MDIO_PHY_1000BASET_ABILITY) 280 physical_layer |= IXGBE_PHYSICAL_LAYER_1000BASE_T; 281 if (ext_ability & IXGBE_MDIO_PHY_100BASETX_ABILITY) 282 physical_layer |= IXGBE_PHYSICAL_LAYER_100BASE_TX; 283 284 return physical_layer; 285 } 286 287 /** 288 * ixgbe_init_eeprom_params_X540 - Initialize EEPROM params 289 * @hw: pointer to hardware structure 290 * 291 * Initializes the EEPROM parameters ixgbe_eeprom_info within the 292 * ixgbe_hw struct in order to set up EEPROM access. 293 **/ 294 int32_t ixgbe_init_eeprom_params_X540(struct ixgbe_hw *hw) 295 { 296 struct ixgbe_eeprom_info *eeprom = &hw->eeprom; 297 uint32_t eec; 298 uint16_t eeprom_size; 299 300 DEBUGFUNC("ixgbe_init_eeprom_params_X540"); 301 302 if (eeprom->type == ixgbe_eeprom_uninitialized) { 303 eeprom->semaphore_delay = 10; 304 eeprom->type = ixgbe_flash; 305 306 eec = IXGBE_READ_REG(hw, IXGBE_EEC); 307 eeprom_size = (uint16_t)((eec & IXGBE_EEC_SIZE) >> 308 IXGBE_EEC_SIZE_SHIFT); 309 eeprom->word_size = 1 << (eeprom_size + 310 IXGBE_EEPROM_WORD_SIZE_SHIFT); 311 312 DEBUGOUT2("Eeprom params: type = %d, size = %d\n", 313 eeprom->type, eeprom->word_size); 314 } 315 316 return IXGBE_SUCCESS; 317 } 318 319 /** 320 * ixgbe_read_eerd_X540- Read EEPROM word using EERD 321 * @hw: pointer to hardware structure 322 * @offset: offset of word in the EEPROM to read 323 * @data: word read from the EEPROM 324 * 325 * Reads a 16 bit word from the EEPROM using the EERD register. 326 **/ 327 int32_t ixgbe_read_eerd_X540(struct ixgbe_hw *hw, uint16_t offset, uint16_t *data) 328 { 329 int32_t status = IXGBE_SUCCESS; 330 331 DEBUGFUNC("ixgbe_read_eerd_X540"); 332 if (hw->mac.ops.acquire_swfw_sync(hw, IXGBE_GSSR_EEP_SM) == 333 IXGBE_SUCCESS) { 334 status = ixgbe_read_eerd_generic(hw, offset, data); 335 hw->mac.ops.release_swfw_sync(hw, IXGBE_GSSR_EEP_SM); 336 } else { 337 status = IXGBE_ERR_SWFW_SYNC; 338 } 339 340 return status; 341 } 342 343 /** 344 * ixgbe_write_eewr_X540 - Write EEPROM word using EEWR 345 * @hw: pointer to hardware structure 346 * @offset: offset of word in the EEPROM to write 347 * @data: word write to the EEPROM 348 * 349 * Write a 16 bit word to the EEPROM using the EEWR register. 350 **/ 351 int32_t ixgbe_write_eewr_X540(struct ixgbe_hw *hw, uint16_t offset, uint16_t data) 352 { 353 int32_t status = IXGBE_SUCCESS; 354 355 DEBUGFUNC("ixgbe_write_eewr_X540"); 356 if (hw->mac.ops.acquire_swfw_sync(hw, IXGBE_GSSR_EEP_SM) == 357 IXGBE_SUCCESS) { 358 status = ixgbe_write_eewr_generic(hw, offset, data); 359 hw->mac.ops.release_swfw_sync(hw, IXGBE_GSSR_EEP_SM); 360 } else { 361 status = IXGBE_ERR_SWFW_SYNC; 362 } 363 364 return status; 365 } 366 367 /** 368 * ixgbe_calc_eeprom_checksum_X540 - Calculates and returns the checksum 369 * 370 * This function does not use synchronization for EERD and EEWR. It can 371 * be used internally by function which utilize ixgbe_acquire_swfw_sync_X540. 372 * 373 * @hw: pointer to hardware structure 374 **/ 375 uint16_t ixgbe_calc_eeprom_checksum_X540(struct ixgbe_hw *hw) 376 { 377 uint16_t i; 378 uint16_t j; 379 uint16_t checksum = 0; 380 uint16_t length = 0; 381 uint16_t pointer = 0; 382 uint16_t word = 0; 383 384 /* 385 * Do not use hw->eeprom.ops.read because we do not want to take 386 * the synchronization semaphores here. Instead use 387 * ixgbe_read_eerd_generic 388 */ 389 390 DEBUGFUNC("ixgbe_calc_eeprom_checksum_X540"); 391 392 /* Include 0x0-0x3F in the checksum */ 393 for (i = 0; i < IXGBE_EEPROM_CHECKSUM; i++) { 394 if (ixgbe_read_eerd_generic(hw, i, &word) != IXGBE_SUCCESS) { 395 DEBUGOUT("EEPROM read failed\n"); 396 break; 397 } 398 checksum += word; 399 } 400 401 /* 402 * Include all data from pointers 0x3, 0x6-0xE. This excludes the 403 * FW, PHY module, and PCIe Expansion/Option ROM pointers. 404 */ 405 for (i = IXGBE_PCIE_ANALOG_PTR; i < IXGBE_FW_PTR; i++) { 406 if (i == IXGBE_PHY_PTR || i == IXGBE_OPTION_ROM_PTR) 407 continue; 408 409 if (ixgbe_read_eerd_generic(hw, i, &pointer) != IXGBE_SUCCESS) { 410 DEBUGOUT("EEPROM read failed\n"); 411 break; 412 } 413 414 /* Skip pointer section if the pointer is invalid. */ 415 if (pointer == 0xFFFF || pointer == 0 || 416 pointer >= hw->eeprom.word_size) 417 continue; 418 419 if (ixgbe_read_eerd_generic(hw, pointer, &length) != 420 IXGBE_SUCCESS) { 421 DEBUGOUT("EEPROM read failed\n"); 422 break; 423 } 424 425 /* Skip pointer section if length is invalid. */ 426 if (length == 0xFFFF || length == 0 || 427 (pointer + length) >= hw->eeprom.word_size) 428 continue; 429 430 for (j = pointer+1; j <= pointer+length; j++) { 431 if (ixgbe_read_eerd_generic(hw, j, &word) != 432 IXGBE_SUCCESS) { 433 DEBUGOUT("EEPROM read failed\n"); 434 break; 435 } 436 checksum += word; 437 } 438 } 439 440 checksum = (uint16_t)IXGBE_EEPROM_SUM - checksum; 441 442 return checksum; 443 } 444 445 /** 446 * ixgbe_validate_eeprom_checksum_X540 - Validate EEPROM checksum 447 * @hw: pointer to hardware structure 448 * @checksum_val: calculated checksum 449 * 450 * Performs checksum calculation and validates the EEPROM checksum. If the 451 * caller does not need checksum_val, the value can be NULL. 452 **/ 453 int32_t ixgbe_validate_eeprom_checksum_X540(struct ixgbe_hw *hw, 454 uint16_t *checksum_val) 455 { 456 int32_t status; 457 uint16_t checksum; 458 uint16_t read_checksum = 0; 459 460 DEBUGFUNC("ixgbe_validate_eeprom_checksum_X540"); 461 462 /* 463 * Read the first word from the EEPROM. If this times out or fails, do 464 * not continue or we could be in for a very long wait while every 465 * EEPROM read fails 466 */ 467 status = hw->eeprom.ops.read(hw, 0, &checksum); 468 469 if (status != IXGBE_SUCCESS) { 470 DEBUGOUT("EEPROM read failed\n"); 471 goto out; 472 } 473 474 if (hw->mac.ops.acquire_swfw_sync(hw, IXGBE_GSSR_EEP_SM) == 475 IXGBE_SUCCESS) { 476 checksum = hw->eeprom.ops.calc_checksum(hw); 477 478 /* 479 * Do not use hw->eeprom.ops.read because we do not want to take 480 * the synchronization semaphores twice here. 481 */ 482 ixgbe_read_eerd_generic(hw, IXGBE_EEPROM_CHECKSUM, 483 &read_checksum); 484 485 /* 486 * Verify read checksum from EEPROM is the same as 487 * calculated checksum 488 */ 489 if (read_checksum != checksum) 490 status = IXGBE_ERR_EEPROM_CHECKSUM; 491 492 /* If the user cares, return the calculated checksum */ 493 if (checksum_val) 494 *checksum_val = checksum; 495 hw->mac.ops.release_swfw_sync(hw, IXGBE_GSSR_EEP_SM); 496 } else { 497 status = IXGBE_ERR_SWFW_SYNC; 498 } 499 500 out: 501 return status; 502 } 503 504 /** 505 * ixgbe_update_eeprom_checksum_X540 - Updates the EEPROM checksum and flash 506 * @hw: pointer to hardware structure 507 * 508 * After writing EEPROM to shadow RAM using EEWR register, software calculates 509 * checksum and updates the EEPROM and instructs the hardware to update 510 * the flash. 511 **/ 512 int32_t ixgbe_update_eeprom_checksum_X540(struct ixgbe_hw *hw) 513 { 514 int32_t status; 515 uint16_t checksum; 516 517 DEBUGFUNC("ixgbe_update_eeprom_checksum_X540"); 518 519 /* 520 * Read the first word from the EEPROM. If this times out or fails, do 521 * not continue or we could be in for a very long wait while every 522 * EEPROM read fails 523 */ 524 status = hw->eeprom.ops.read(hw, 0, &checksum); 525 526 if (status != IXGBE_SUCCESS) 527 DEBUGOUT("EEPROM read failed\n"); 528 529 if (hw->mac.ops.acquire_swfw_sync(hw, IXGBE_GSSR_EEP_SM) == 530 IXGBE_SUCCESS) { 531 checksum = hw->eeprom.ops.calc_checksum(hw); 532 533 /* 534 * Do not use hw->eeprom.ops.write because we do not want to 535 * take the synchronization semaphores twice here. 536 */ 537 status = ixgbe_write_eewr_generic(hw, IXGBE_EEPROM_CHECKSUM, 538 checksum); 539 540 if (status == IXGBE_SUCCESS) 541 status = ixgbe_update_flash_X540(hw); 542 hw->mac.ops.release_swfw_sync(hw, IXGBE_GSSR_EEP_SM); 543 } else { 544 status = IXGBE_ERR_SWFW_SYNC; 545 } 546 547 return status; 548 } 549 550 /** 551 * ixgbe_update_flash_X540 - Instruct HW to copy EEPROM to Flash device 552 * @hw: pointer to hardware structure 553 * 554 * Set FLUP (bit 23) of the EEC register to instruct Hardware to copy 555 * EEPROM from shadow RAM to the flash device. 556 **/ 557 int32_t ixgbe_update_flash_X540(struct ixgbe_hw *hw) 558 { 559 uint32_t flup; 560 int32_t status = IXGBE_ERR_EEPROM; 561 562 DEBUGFUNC("ixgbe_update_flash_X540"); 563 564 status = ixgbe_poll_flash_update_done_X540(hw); 565 if (status == IXGBE_ERR_EEPROM) { 566 DEBUGOUT("Flash update time out\n"); 567 goto out; 568 } 569 570 flup = IXGBE_READ_REG(hw, IXGBE_EEC) | IXGBE_EEC_FLUP; 571 IXGBE_WRITE_REG(hw, IXGBE_EEC, flup); 572 573 status = ixgbe_poll_flash_update_done_X540(hw); 574 if (status == IXGBE_SUCCESS) 575 DEBUGOUT("Flash update complete\n"); 576 else 577 DEBUGOUT("Flash update time out\n"); 578 579 if (hw->mac.type == ixgbe_mac_X540 && hw->revision_id == 0) { 580 flup = IXGBE_READ_REG(hw, IXGBE_EEC); 581 582 if (flup & IXGBE_EEC_SEC1VAL) { 583 flup |= IXGBE_EEC_FLUP; 584 IXGBE_WRITE_REG(hw, IXGBE_EEC, flup); 585 } 586 587 status = ixgbe_poll_flash_update_done_X540(hw); 588 if (status == IXGBE_SUCCESS) 589 DEBUGOUT("Flash update complete\n"); 590 else 591 DEBUGOUT("Flash update time out\n"); 592 } 593 out: 594 return status; 595 } 596 597 /** 598 * ixgbe_poll_flash_update_done_X540 - Poll flash update status 599 * @hw: pointer to hardware structure 600 * 601 * Polls the FLUDONE (bit 26) of the EEC Register to determine when the 602 * flash update is done. 603 **/ 604 int32_t ixgbe_poll_flash_update_done_X540(struct ixgbe_hw *hw) 605 { 606 uint32_t i; 607 uint32_t reg; 608 int32_t status = IXGBE_ERR_EEPROM; 609 610 DEBUGFUNC("ixgbe_poll_flash_update_done_X540"); 611 612 for (i = 0; i < IXGBE_FLUDONE_ATTEMPTS; i++) { 613 reg = IXGBE_READ_REG(hw, IXGBE_EEC); 614 if (reg & IXGBE_EEC_FLUDONE) { 615 status = IXGBE_SUCCESS; 616 break; 617 } 618 usec_delay(5); 619 } 620 return status; 621 } 622 623 /** 624 * ixgbe_acquire_swfw_sync_X540 - Acquire SWFW semaphore 625 * @hw: pointer to hardware structure 626 * @mask: Mask to specify which semaphore to acquire 627 * 628 * Acquires the SWFW semaphore thought the SW_FW_SYNC register for 629 * the specified function (CSR, PHY0, PHY1, NVM, Flash) 630 **/ 631 int32_t ixgbe_acquire_swfw_sync_X540(struct ixgbe_hw *hw, uint16_t mask) 632 { 633 uint32_t swfw_sync; 634 uint32_t swmask = mask; 635 uint32_t fwmask = mask << 5; 636 uint32_t hwmask = 0; 637 uint32_t timeout = 200; 638 uint32_t i; 639 int32_t ret_val = IXGBE_SUCCESS; 640 641 DEBUGFUNC("ixgbe_acquire_swfw_sync_X540"); 642 643 if (swmask == IXGBE_GSSR_EEP_SM) 644 hwmask = IXGBE_GSSR_FLASH_SM; 645 646 /* SW only mask doesn't have FW bit pair */ 647 if (swmask == IXGBE_GSSR_SW_MNG_SM) 648 fwmask = 0; 649 650 for (i = 0; i < timeout; i++) { 651 /* 652 * SW NVM semaphore bit is used for access to all 653 * SW_FW_SYNC bits (not just NVM) 654 */ 655 if (ixgbe_get_swfw_sync_semaphore(hw)) { 656 ret_val = IXGBE_ERR_SWFW_SYNC; 657 goto out; 658 } 659 660 swfw_sync = IXGBE_READ_REG(hw, IXGBE_SWFW_SYNC); 661 if (!(swfw_sync & (fwmask | swmask | hwmask))) { 662 swfw_sync |= swmask; 663 IXGBE_WRITE_REG(hw, IXGBE_SWFW_SYNC, swfw_sync); 664 ixgbe_release_swfw_sync_semaphore(hw); 665 goto out; 666 } else { 667 /* 668 * Firmware currently using resource (fwmask), hardware 669 * currently using resource (hwmask), or other software 670 * thread currently using resource (swmask) 671 */ 672 ixgbe_release_swfw_sync_semaphore(hw); 673 msec_delay(5); 674 } 675 } 676 677 /* Failed to get SW only semaphore */ 678 if (swmask == IXGBE_GSSR_SW_MNG_SM) { 679 ret_val = IXGBE_ERR_SWFW_SYNC; 680 goto out; 681 } 682 683 /* If the resource is not released by the FW/HW the SW can assume that 684 * the FW/HW malfunctions. In that case the SW should set the SW bit(s) 685 * of the requested resource(s) while ignoring the corresponding FW/HW 686 * bits in the SW_FW_SYNC register. 687 */ 688 swfw_sync = IXGBE_READ_REG(hw, IXGBE_SWFW_SYNC); 689 if (swfw_sync & (fwmask | hwmask)) { 690 if (ixgbe_get_swfw_sync_semaphore(hw)) { 691 ret_val = IXGBE_ERR_SWFW_SYNC; 692 goto out; 693 } 694 695 swfw_sync |= swmask; 696 IXGBE_WRITE_REG(hw, IXGBE_SWFW_SYNC, swfw_sync); 697 ixgbe_release_swfw_sync_semaphore(hw); 698 msec_delay(5); 699 } 700 /* If the resource is not released by other SW the SW can assume that 701 * the other SW malfunctions. In that case the SW should clear all SW 702 * flags that it does not own and then repeat the whole process once 703 * again. 704 */ 705 else if (swfw_sync & swmask) { 706 ixgbe_release_swfw_sync_X540(hw, IXGBE_GSSR_EEP_SM | 707 IXGBE_GSSR_PHY0_SM | IXGBE_GSSR_PHY1_SM | 708 IXGBE_GSSR_MAC_CSR_SM); 709 ret_val = IXGBE_ERR_SWFW_SYNC; 710 } 711 712 out: 713 return ret_val; 714 } 715 716 /** 717 * ixgbe_release_swfw_sync_X540 - Release SWFW semaphore 718 * @hw: pointer to hardware structure 719 * @mask: Mask to specify which semaphore to release 720 * 721 * Releases the SWFW semaphore through the SW_FW_SYNC register 722 * for the specified function (CSR, PHY0, PHY1, EVM, Flash) 723 **/ 724 void ixgbe_release_swfw_sync_X540(struct ixgbe_hw *hw, uint16_t mask) 725 { 726 uint32_t swfw_sync; 727 uint32_t swmask = mask; 728 729 DEBUGFUNC("ixgbe_release_swfw_sync_X540"); 730 731 ixgbe_get_swfw_sync_semaphore(hw); 732 733 swfw_sync = IXGBE_READ_REG(hw, IXGBE_SWFW_SYNC); 734 swfw_sync &= ~swmask; 735 IXGBE_WRITE_REG(hw, IXGBE_SWFW_SYNC, swfw_sync); 736 737 ixgbe_release_swfw_sync_semaphore(hw); 738 } 739 740 /** 741 * ixgbe_get_nvm_semaphore - Get hardware semaphore 742 * @hw: pointer to hardware structure 743 * 744 * Sets the hardware semaphores so SW/FW can gain control of shared resources 745 **/ 746 int32_t ixgbe_get_swfw_sync_semaphore(struct ixgbe_hw *hw) 747 { 748 int32_t status = IXGBE_ERR_EEPROM; 749 uint32_t timeout = 2000; 750 uint32_t i; 751 uint32_t swsm; 752 753 DEBUGFUNC("ixgbe_get_swfw_sync_semaphore"); 754 755 /* Get SMBI software semaphore between device drivers first */ 756 for (i = 0; i < timeout; i++) { 757 /* 758 * If the SMBI bit is 0 when we read it, then the bit will be 759 * set and we have the semaphore 760 */ 761 swsm = IXGBE_READ_REG(hw, IXGBE_SWSM); 762 if (!(swsm & IXGBE_SWSM_SMBI)) { 763 status = IXGBE_SUCCESS; 764 break; 765 } 766 usec_delay(50); 767 } 768 769 /* Now get the semaphore between SW/FW through the REGSMP bit */ 770 if (status == IXGBE_SUCCESS) { 771 for (i = 0; i < timeout; i++) { 772 swsm = IXGBE_READ_REG(hw, IXGBE_SWFW_SYNC); 773 if (!(swsm & IXGBE_SWFW_REGSMP)) 774 break; 775 776 usec_delay(50); 777 } 778 779 /* 780 * Release semaphores and return error if SW NVM semaphore 781 * was not granted because we don't have access to the EEPROM 782 */ 783 if (i >= timeout) { 784 DEBUGOUT("REGSMP Software NVM semaphore not " 785 "granted.\n"); 786 ixgbe_release_swfw_sync_semaphore(hw); 787 status = IXGBE_ERR_EEPROM; 788 } 789 } else { 790 DEBUGOUT("Software semaphore SMBI between device drivers " 791 "not granted.\n"); 792 } 793 794 return status; 795 } 796 797 /** 798 * ixgbe_release_nvm_semaphore - Release hardware semaphore 799 * @hw: pointer to hardware structure 800 * 801 * This function clears hardware semaphore bits. 802 **/ 803 void ixgbe_release_swfw_sync_semaphore(struct ixgbe_hw *hw) 804 { 805 uint32_t swsm; 806 807 DEBUGFUNC("ixgbe_release_swfw_sync_semaphore"); 808 809 /* Release both semaphores by writing 0 to the bits REGSMP and SMBI */ 810 811 swsm = IXGBE_READ_REG(hw, IXGBE_SWSM); 812 swsm &= ~IXGBE_SWSM_SMBI; 813 IXGBE_WRITE_REG(hw, IXGBE_SWSM, swsm); 814 815 swsm = IXGBE_READ_REG(hw, IXGBE_SWFW_SYNC); 816 swsm &= ~IXGBE_SWFW_REGSMP; 817 IXGBE_WRITE_REG(hw, IXGBE_SWFW_SYNC, swsm); 818 819 IXGBE_WRITE_FLUSH(hw); 820 } 821 822 /** 823 * ixgbe_blink_led_start_X540 - Blink LED based on index. 824 * @hw: pointer to hardware structure 825 * @index: led number to blink 826 * 827 * Devices that implement the version 2 interface: 828 * X540 829 **/ 830 int32_t ixgbe_blink_led_start_X540(struct ixgbe_hw *hw, uint32_t index) 831 { 832 uint32_t macc_reg; 833 uint32_t ledctl_reg; 834 ixgbe_link_speed speed; 835 bool link_up; 836 837 DEBUGFUNC("ixgbe_blink_led_start_X540"); 838 839 /* 840 * Link should be up in order for the blink bit in the LED control 841 * register to work. Force link and speed in the MAC if link is down. 842 * This will be reversed when we stop the blinking. 843 */ 844 hw->mac.ops.check_link(hw, &speed, &link_up, FALSE); 845 if (link_up == FALSE) { 846 macc_reg = IXGBE_READ_REG(hw, IXGBE_MACC); 847 macc_reg |= IXGBE_MACC_FLU | IXGBE_MACC_FSV_10G | IXGBE_MACC_FS; 848 IXGBE_WRITE_REG(hw, IXGBE_MACC, macc_reg); 849 } 850 /* Set the LED to LINK_UP + BLINK. */ 851 ledctl_reg = IXGBE_READ_REG(hw, IXGBE_LEDCTL); 852 ledctl_reg &= ~IXGBE_LED_MODE_MASK(index); 853 ledctl_reg |= IXGBE_LED_BLINK(index); 854 IXGBE_WRITE_REG(hw, IXGBE_LEDCTL, ledctl_reg); 855 IXGBE_WRITE_FLUSH(hw); 856 857 return IXGBE_SUCCESS; 858 } 859 860 /** 861 * ixgbe_blink_led_stop_X540 - Stop blinking LED based on index. 862 * @hw: pointer to hardware structure 863 * @index: led number to stop blinking 864 * 865 * Devices that implement the version 2 interface: 866 * X540 867 **/ 868 int32_t ixgbe_blink_led_stop_X540(struct ixgbe_hw *hw, uint32_t index) 869 { 870 uint32_t macc_reg; 871 uint32_t ledctl_reg; 872 873 DEBUGFUNC("ixgbe_blink_led_stop_X540"); 874 875 /* Restore the LED to its default value. */ 876 ledctl_reg = IXGBE_READ_REG(hw, IXGBE_LEDCTL); 877 ledctl_reg &= ~IXGBE_LED_MODE_MASK(index); 878 ledctl_reg |= IXGBE_LED_LINK_ACTIVE << IXGBE_LED_MODE_SHIFT(index); 879 ledctl_reg &= ~IXGBE_LED_BLINK(index); 880 IXGBE_WRITE_REG(hw, IXGBE_LEDCTL, ledctl_reg); 881 882 /* Unforce link and speed in the MAC. */ 883 macc_reg = IXGBE_READ_REG(hw, IXGBE_MACC); 884 macc_reg &= ~(IXGBE_MACC_FLU | IXGBE_MACC_FSV_10G | IXGBE_MACC_FS); 885 IXGBE_WRITE_REG(hw, IXGBE_MACC, macc_reg); 886 IXGBE_WRITE_FLUSH(hw); 887 888 return IXGBE_SUCCESS; 889 } 890