1 /* $OpenBSD: ixgbe_x540.c,v 1.2 2013/08/05 19:58:06 mikeb Exp $ */ 2 3 /****************************************************************************** 4 5 Copyright (c) 2001-2013, Intel Corporation 6 All rights reserved. 7 8 Redistribution and use in source and binary forms, with or without 9 modification, are permitted provided that the following conditions are met: 10 11 1. Redistributions of source code must retain the above copyright notice, 12 this list of conditions and the following disclaimer. 13 14 2. Redistributions in binary form must reproduce the above copyright 15 notice, this list of conditions and the following disclaimer in the 16 documentation and/or other materials provided with the distribution. 17 18 3. Neither the name of the Intel Corporation nor the names of its 19 contributors may be used to endorse or promote products derived from 20 this software without specific prior written permission. 21 22 THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS" 23 AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE 24 IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE 25 ARE DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT OWNER OR CONTRIBUTORS BE 26 LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR 27 CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF 28 SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS 29 INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN 30 CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) 31 ARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE 32 POSSIBILITY OF SUCH DAMAGE. 33 34 ******************************************************************************/ 35 /* FreeBSD: src/sys/dev/ixgbe/ixgbe_x540.c 251964 Jun 18 21:28:19 2013 UTC */ 36 37 #include <dev/pci/ixgbe.h> 38 #include <dev/pci/ixgbe_type.h> 39 40 int32_t ixgbe_update_flash_X540(struct ixgbe_hw *hw); 41 int32_t ixgbe_poll_flash_update_done_X540(struct ixgbe_hw *hw); 42 int32_t ixgbe_get_swfw_sync_semaphore(struct ixgbe_hw *hw); 43 void ixgbe_release_swfw_sync_semaphore(struct ixgbe_hw *hw); 44 45 int32_t ixgbe_get_link_capabilities_X540(struct ixgbe_hw *hw, 46 ixgbe_link_speed *speed, 47 bool *autoneg); 48 enum ixgbe_media_type ixgbe_get_media_type_X540(struct ixgbe_hw *hw); 49 int32_t ixgbe_setup_mac_link_X540(struct ixgbe_hw *hw, ixgbe_link_speed speed, 50 bool link_up_wait_to_complete); 51 int32_t ixgbe_reset_hw_X540(struct ixgbe_hw *hw); 52 int32_t ixgbe_start_hw_X540(struct ixgbe_hw *hw); 53 uint32_t ixgbe_get_supported_physical_layer_X540(struct ixgbe_hw *hw); 54 55 int32_t ixgbe_init_eeprom_params_X540(struct ixgbe_hw *hw); 56 int32_t ixgbe_read_eerd_X540(struct ixgbe_hw *hw, uint16_t offset, uint16_t *data); 57 int32_t ixgbe_write_eewr_X540(struct ixgbe_hw *hw, uint16_t offset, uint16_t data); 58 int32_t ixgbe_update_eeprom_checksum_X540(struct ixgbe_hw *hw); 59 int32_t ixgbe_validate_eeprom_checksum_X540(struct ixgbe_hw *hw, uint16_t *checksum_val); 60 uint16_t ixgbe_calc_eeprom_checksum_X540(struct ixgbe_hw *hw); 61 62 int32_t ixgbe_acquire_swfw_sync_X540(struct ixgbe_hw *hw, uint16_t mask); 63 void ixgbe_release_swfw_sync_X540(struct ixgbe_hw *hw, uint16_t mask); 64 65 int32_t ixgbe_blink_led_start_X540(struct ixgbe_hw *hw, uint32_t index); 66 int32_t ixgbe_blink_led_stop_X540(struct ixgbe_hw *hw, uint32_t index); 67 68 /** 69 * ixgbe_init_ops_X540 - Inits func ptrs and MAC type 70 * @hw: pointer to hardware structure 71 * 72 * Initialize the function pointers and assign the MAC type for X540. 73 * Does not touch the hardware. 74 **/ 75 int32_t ixgbe_init_ops_X540(struct ixgbe_hw *hw) 76 { 77 struct ixgbe_mac_info *mac = &hw->mac; 78 struct ixgbe_phy_info *phy = &hw->phy; 79 struct ixgbe_eeprom_info *eeprom = &hw->eeprom; 80 int32_t ret_val; 81 82 DEBUGFUNC("ixgbe_init_ops_X540"); 83 84 ret_val = ixgbe_init_phy_ops_generic(hw); 85 ret_val = ixgbe_init_ops_generic(hw); 86 87 /* EEPROM */ 88 eeprom->ops.init_params = &ixgbe_init_eeprom_params_X540; 89 eeprom->ops.read = &ixgbe_read_eerd_X540; 90 eeprom->ops.write = &ixgbe_write_eewr_X540; 91 eeprom->ops.update_checksum = &ixgbe_update_eeprom_checksum_X540; 92 eeprom->ops.validate_checksum = &ixgbe_validate_eeprom_checksum_X540; 93 eeprom->ops.calc_checksum = &ixgbe_calc_eeprom_checksum_X540; 94 95 /* PHY */ 96 phy->ops.init = &ixgbe_init_phy_ops_generic; 97 phy->ops.reset = NULL; 98 99 /* MAC */ 100 mac->ops.reset_hw = &ixgbe_reset_hw_X540; 101 mac->ops.enable_relaxed_ordering = &ixgbe_enable_relaxed_ordering_gen2; 102 mac->ops.get_media_type = &ixgbe_get_media_type_X540; 103 mac->ops.get_supported_physical_layer = 104 &ixgbe_get_supported_physical_layer_X540; 105 mac->ops.read_analog_reg8 = NULL; 106 mac->ops.write_analog_reg8 = NULL; 107 mac->ops.start_hw = &ixgbe_start_hw_X540; 108 mac->ops.get_device_caps = &ixgbe_get_device_caps_generic; 109 mac->ops.acquire_swfw_sync = &ixgbe_acquire_swfw_sync_X540; 110 mac->ops.release_swfw_sync = &ixgbe_release_swfw_sync_X540; 111 mac->ops.disable_sec_rx_path = &ixgbe_disable_sec_rx_path_generic; 112 mac->ops.enable_sec_rx_path = &ixgbe_enable_sec_rx_path_generic; 113 114 /* RAR, Multicast, VLAN */ 115 mac->ops.set_vmdq = &ixgbe_set_vmdq_generic; 116 mac->ops.clear_vmdq = &ixgbe_clear_vmdq_generic; 117 mac->ops.insert_mac_addr = &ixgbe_insert_mac_addr_generic; 118 mac->rar_highwater = 1; 119 mac->ops.set_vfta = &ixgbe_set_vfta_generic; 120 mac->ops.clear_vfta = &ixgbe_clear_vfta_generic; 121 mac->ops.init_uta_tables = &ixgbe_init_uta_tables_generic; 122 123 /* Link */ 124 mac->ops.get_link_capabilities = 125 &ixgbe_get_copper_link_capabilities_generic; 126 mac->ops.setup_link = &ixgbe_setup_mac_link_X540; 127 mac->ops.check_link = &ixgbe_check_mac_link_generic; 128 129 mac->mcft_size = 128; 130 mac->vft_size = 128; 131 mac->num_rar_entries = 128; 132 mac->rx_pb_size = 384; 133 mac->max_tx_queues = 128; 134 mac->max_rx_queues = 128; 135 mac->max_msix_vectors = 0 /*ixgbe_get_pcie_msix_count_generic(hw)*/; 136 137 hw->mbx.ops.init_params = ixgbe_init_mbx_params_pf; 138 139 /* LEDs */ 140 mac->ops.blink_led_start = ixgbe_blink_led_start_X540; 141 mac->ops.blink_led_stop = ixgbe_blink_led_stop_X540; 142 143 return ret_val; 144 } 145 146 /** 147 * ixgbe_get_link_capabilities_X540 - Determines link capabilities 148 * @hw: pointer to hardware structure 149 * @speed: pointer to link speed 150 * @autoneg: TRUE when autoneg or autotry is enabled 151 * 152 * Determines the link capabilities by reading the AUTOC register. 153 **/ 154 int32_t ixgbe_get_link_capabilities_X540(struct ixgbe_hw *hw, 155 ixgbe_link_speed *speed, 156 bool *autoneg) 157 { 158 ixgbe_get_copper_link_capabilities_generic(hw, speed, autoneg); 159 160 return IXGBE_SUCCESS; 161 } 162 163 /** 164 * ixgbe_get_media_type_X540 - Get media type 165 * @hw: pointer to hardware structure 166 * 167 * Returns the media type (fiber, copper, backplane) 168 **/ 169 enum ixgbe_media_type ixgbe_get_media_type_X540(struct ixgbe_hw *hw) 170 { 171 return ixgbe_media_type_copper; 172 } 173 174 /** 175 * ixgbe_setup_mac_link_X540 - Sets the auto advertised capabilities 176 * @hw: pointer to hardware structure 177 * @speed: new link speed 178 * @autoneg_wait_to_complete: TRUE when waiting for completion is needed 179 **/ 180 int32_t ixgbe_setup_mac_link_X540(struct ixgbe_hw *hw, 181 ixgbe_link_speed speed, 182 bool autoneg_wait_to_complete) 183 { 184 DEBUGFUNC("ixgbe_setup_mac_link_X540"); 185 return hw->phy.ops.setup_link_speed(hw, speed, 186 autoneg_wait_to_complete); 187 } 188 189 /** 190 * ixgbe_reset_hw_X540 - Perform hardware reset 191 * @hw: pointer to hardware structure 192 * 193 * Resets the hardware by resetting the transmit and receive units, masks 194 * and clears all interrupts, and perform a reset. 195 **/ 196 int32_t ixgbe_reset_hw_X540(struct ixgbe_hw *hw) 197 { 198 int32_t status; 199 uint32_t ctrl, i; 200 201 DEBUGFUNC("ixgbe_reset_hw_X540"); 202 203 /* Call adapter stop to disable tx/rx and clear interrupts */ 204 status = hw->mac.ops.stop_adapter(hw); 205 if (status != IXGBE_SUCCESS) 206 goto reset_hw_out; 207 208 /* flush pending Tx transactions */ 209 ixgbe_clear_tx_pending(hw); 210 211 mac_reset_top: 212 ctrl = IXGBE_CTRL_RST; 213 ctrl |= IXGBE_READ_REG(hw, IXGBE_CTRL); 214 IXGBE_WRITE_REG(hw, IXGBE_CTRL, ctrl); 215 IXGBE_WRITE_FLUSH(hw); 216 217 /* Poll for reset bit to self-clear indicating reset is complete */ 218 for (i = 0; i < 10; i++) { 219 usec_delay(1); 220 ctrl = IXGBE_READ_REG(hw, IXGBE_CTRL); 221 if (!(ctrl & IXGBE_CTRL_RST_MASK)) 222 break; 223 } 224 225 if (ctrl & IXGBE_CTRL_RST_MASK) { 226 status = IXGBE_ERR_RESET_FAILED; 227 DEBUGOUT("Reset polling failed to complete.\n"); 228 } 229 msec_delay(100); 230 231 /* 232 * Double resets are required for recovery from certain error 233 * conditions. Between resets, it is necessary to stall to allow time 234 * for any pending HW events to complete. 235 */ 236 if (hw->mac.flags & IXGBE_FLAGS_DOUBLE_RESET_REQUIRED) { 237 hw->mac.flags &= ~IXGBE_FLAGS_DOUBLE_RESET_REQUIRED; 238 goto mac_reset_top; 239 } 240 241 /* Set the Rx packet buffer size. */ 242 IXGBE_WRITE_REG(hw, IXGBE_RXPBSIZE(0), 384 << IXGBE_RXPBSIZE_SHIFT); 243 244 /* Store the permanent mac address */ 245 hw->mac.ops.get_mac_addr(hw, hw->mac.perm_addr); 246 247 /* 248 * Store MAC address from RAR0, clear receive address registers, and 249 * clear the multicast table. Also reset num_rar_entries to 128, 250 * since we modify this value when programming the SAN MAC address. 251 */ 252 hw->mac.num_rar_entries = 128; 253 hw->mac.ops.init_rx_addrs(hw); 254 255 reset_hw_out: 256 return status; 257 } 258 259 /** 260 * ixgbe_start_hw_X540 - Prepare hardware for Tx/Rx 261 * @hw: pointer to hardware structure 262 * 263 * Starts the hardware using the generic start_hw function 264 * and the generation start_hw function. 265 * Then performs revision-specific operations, if any. 266 **/ 267 int32_t ixgbe_start_hw_X540(struct ixgbe_hw *hw) 268 { 269 int32_t ret_val = IXGBE_SUCCESS; 270 271 DEBUGFUNC("ixgbe_start_hw_X540"); 272 273 ret_val = ixgbe_start_hw_generic(hw); 274 if (ret_val != IXGBE_SUCCESS) 275 goto out; 276 277 ret_val = ixgbe_start_hw_gen2(hw); 278 279 out: 280 return ret_val; 281 } 282 283 /** 284 * ixgbe_get_supported_physical_layer_X540 - Returns physical layer type 285 * @hw: pointer to hardware structure 286 * 287 * Determines physical layer capabilities of the current configuration. 288 **/ 289 uint32_t ixgbe_get_supported_physical_layer_X540(struct ixgbe_hw *hw) 290 { 291 uint32_t physical_layer = IXGBE_PHYSICAL_LAYER_UNKNOWN; 292 uint16_t ext_ability = 0; 293 294 DEBUGFUNC("ixgbe_get_supported_physical_layer_X540"); 295 296 hw->phy.ops.read_reg(hw, IXGBE_MDIO_PHY_EXT_ABILITY, 297 IXGBE_MDIO_PMA_PMD_DEV_TYPE, &ext_ability); 298 if (ext_ability & IXGBE_MDIO_PHY_10GBASET_ABILITY) 299 physical_layer |= IXGBE_PHYSICAL_LAYER_10GBASE_T; 300 if (ext_ability & IXGBE_MDIO_PHY_1000BASET_ABILITY) 301 physical_layer |= IXGBE_PHYSICAL_LAYER_1000BASE_T; 302 if (ext_ability & IXGBE_MDIO_PHY_100BASETX_ABILITY) 303 physical_layer |= IXGBE_PHYSICAL_LAYER_100BASE_TX; 304 305 return physical_layer; 306 } 307 308 /** 309 * ixgbe_init_eeprom_params_X540 - Initialize EEPROM params 310 * @hw: pointer to hardware structure 311 * 312 * Initializes the EEPROM parameters ixgbe_eeprom_info within the 313 * ixgbe_hw struct in order to set up EEPROM access. 314 **/ 315 int32_t ixgbe_init_eeprom_params_X540(struct ixgbe_hw *hw) 316 { 317 struct ixgbe_eeprom_info *eeprom = &hw->eeprom; 318 uint32_t eec; 319 uint16_t eeprom_size; 320 321 DEBUGFUNC("ixgbe_init_eeprom_params_X540"); 322 323 if (eeprom->type == ixgbe_eeprom_uninitialized) { 324 eeprom->semaphore_delay = 10; 325 eeprom->type = ixgbe_flash; 326 327 eec = IXGBE_READ_REG(hw, IXGBE_EEC); 328 eeprom_size = (uint16_t)((eec & IXGBE_EEC_SIZE) >> 329 IXGBE_EEC_SIZE_SHIFT); 330 eeprom->word_size = 1 << (eeprom_size + 331 IXGBE_EEPROM_WORD_SIZE_SHIFT); 332 333 DEBUGOUT2("Eeprom params: type = %d, size = %d\n", 334 eeprom->type, eeprom->word_size); 335 } 336 337 return IXGBE_SUCCESS; 338 } 339 340 /** 341 * ixgbe_read_eerd_X540- Read EEPROM word using EERD 342 * @hw: pointer to hardware structure 343 * @offset: offset of word in the EEPROM to read 344 * @data: word read from the EEPROM 345 * 346 * Reads a 16 bit word from the EEPROM using the EERD register. 347 **/ 348 int32_t ixgbe_read_eerd_X540(struct ixgbe_hw *hw, uint16_t offset, uint16_t *data) 349 { 350 int32_t status = IXGBE_SUCCESS; 351 352 DEBUGFUNC("ixgbe_read_eerd_X540"); 353 if (hw->mac.ops.acquire_swfw_sync(hw, IXGBE_GSSR_EEP_SM) == 354 IXGBE_SUCCESS) { 355 status = ixgbe_read_eerd_generic(hw, offset, data); 356 hw->mac.ops.release_swfw_sync(hw, IXGBE_GSSR_EEP_SM); 357 } else { 358 status = IXGBE_ERR_SWFW_SYNC; 359 } 360 361 return status; 362 } 363 364 /** 365 * ixgbe_write_eewr_X540 - Write EEPROM word using EEWR 366 * @hw: pointer to hardware structure 367 * @offset: offset of word in the EEPROM to write 368 * @data: word write to the EEPROM 369 * 370 * Write a 16 bit word to the EEPROM using the EEWR register. 371 **/ 372 int32_t ixgbe_write_eewr_X540(struct ixgbe_hw *hw, uint16_t offset, uint16_t data) 373 { 374 int32_t status = IXGBE_SUCCESS; 375 376 DEBUGFUNC("ixgbe_write_eewr_X540"); 377 if (hw->mac.ops.acquire_swfw_sync(hw, IXGBE_GSSR_EEP_SM) == 378 IXGBE_SUCCESS) { 379 status = ixgbe_write_eewr_generic(hw, offset, data); 380 hw->mac.ops.release_swfw_sync(hw, IXGBE_GSSR_EEP_SM); 381 } else { 382 status = IXGBE_ERR_SWFW_SYNC; 383 } 384 385 return status; 386 } 387 388 /** 389 * ixgbe_calc_eeprom_checksum_X540 - Calculates and returns the checksum 390 * 391 * This function does not use synchronization for EERD and EEWR. It can 392 * be used internally by function which utilize ixgbe_acquire_swfw_sync_X540. 393 * 394 * @hw: pointer to hardware structure 395 **/ 396 uint16_t ixgbe_calc_eeprom_checksum_X540(struct ixgbe_hw *hw) 397 { 398 uint16_t i; 399 uint16_t j; 400 uint16_t checksum = 0; 401 uint16_t length = 0; 402 uint16_t pointer = 0; 403 uint16_t word = 0; 404 405 /* 406 * Do not use hw->eeprom.ops.read because we do not want to take 407 * the synchronization semaphores here. Instead use 408 * ixgbe_read_eerd_generic 409 */ 410 411 DEBUGFUNC("ixgbe_calc_eeprom_checksum_X540"); 412 413 /* Include 0x0-0x3F in the checksum */ 414 for (i = 0; i < IXGBE_EEPROM_CHECKSUM; i++) { 415 if (ixgbe_read_eerd_generic(hw, i, &word) != IXGBE_SUCCESS) { 416 DEBUGOUT("EEPROM read failed\n"); 417 break; 418 } 419 checksum += word; 420 } 421 422 /* 423 * Include all data from pointers 0x3, 0x6-0xE. This excludes the 424 * FW, PHY module, and PCIe Expansion/Option ROM pointers. 425 */ 426 for (i = IXGBE_PCIE_ANALOG_PTR; i < IXGBE_FW_PTR; i++) { 427 if (i == IXGBE_PHY_PTR || i == IXGBE_OPTION_ROM_PTR) 428 continue; 429 430 if (ixgbe_read_eerd_generic(hw, i, &pointer) != IXGBE_SUCCESS) { 431 DEBUGOUT("EEPROM read failed\n"); 432 break; 433 } 434 435 /* Skip pointer section if the pointer is invalid. */ 436 if (pointer == 0xFFFF || pointer == 0 || 437 pointer >= hw->eeprom.word_size) 438 continue; 439 440 if (ixgbe_read_eerd_generic(hw, pointer, &length) != 441 IXGBE_SUCCESS) { 442 DEBUGOUT("EEPROM read failed\n"); 443 break; 444 } 445 446 /* Skip pointer section if length is invalid. */ 447 if (length == 0xFFFF || length == 0 || 448 (pointer + length) >= hw->eeprom.word_size) 449 continue; 450 451 for (j = pointer+1; j <= pointer+length; j++) { 452 if (ixgbe_read_eerd_generic(hw, j, &word) != 453 IXGBE_SUCCESS) { 454 DEBUGOUT("EEPROM read failed\n"); 455 break; 456 } 457 checksum += word; 458 } 459 } 460 461 checksum = (uint16_t)IXGBE_EEPROM_SUM - checksum; 462 463 return checksum; 464 } 465 466 /** 467 * ixgbe_validate_eeprom_checksum_X540 - Validate EEPROM checksum 468 * @hw: pointer to hardware structure 469 * @checksum_val: calculated checksum 470 * 471 * Performs checksum calculation and validates the EEPROM checksum. If the 472 * caller does not need checksum_val, the value can be NULL. 473 **/ 474 int32_t ixgbe_validate_eeprom_checksum_X540(struct ixgbe_hw *hw, 475 uint16_t *checksum_val) 476 { 477 int32_t status; 478 uint16_t checksum; 479 uint16_t read_checksum = 0; 480 481 DEBUGFUNC("ixgbe_validate_eeprom_checksum_X540"); 482 483 /* 484 * Read the first word from the EEPROM. If this times out or fails, do 485 * not continue or we could be in for a very long wait while every 486 * EEPROM read fails 487 */ 488 status = hw->eeprom.ops.read(hw, 0, &checksum); 489 490 if (status != IXGBE_SUCCESS) { 491 DEBUGOUT("EEPROM read failed\n"); 492 goto out; 493 } 494 495 if (hw->mac.ops.acquire_swfw_sync(hw, IXGBE_GSSR_EEP_SM) == 496 IXGBE_SUCCESS) { 497 checksum = hw->eeprom.ops.calc_checksum(hw); 498 499 /* 500 * Do not use hw->eeprom.ops.read because we do not want to take 501 * the synchronization semaphores twice here. 502 */ 503 ixgbe_read_eerd_generic(hw, IXGBE_EEPROM_CHECKSUM, 504 &read_checksum); 505 506 /* 507 * Verify read checksum from EEPROM is the same as 508 * calculated checksum 509 */ 510 if (read_checksum != checksum) 511 status = IXGBE_ERR_EEPROM_CHECKSUM; 512 513 /* If the user cares, return the calculated checksum */ 514 if (checksum_val) 515 *checksum_val = checksum; 516 hw->mac.ops.release_swfw_sync(hw, IXGBE_GSSR_EEP_SM); 517 } else { 518 status = IXGBE_ERR_SWFW_SYNC; 519 } 520 521 out: 522 return status; 523 } 524 525 /** 526 * ixgbe_update_eeprom_checksum_X540 - Updates the EEPROM checksum and flash 527 * @hw: pointer to hardware structure 528 * 529 * After writing EEPROM to shadow RAM using EEWR register, software calculates 530 * checksum and updates the EEPROM and instructs the hardware to update 531 * the flash. 532 **/ 533 int32_t ixgbe_update_eeprom_checksum_X540(struct ixgbe_hw *hw) 534 { 535 int32_t status; 536 uint16_t checksum; 537 538 DEBUGFUNC("ixgbe_update_eeprom_checksum_X540"); 539 540 /* 541 * Read the first word from the EEPROM. If this times out or fails, do 542 * not continue or we could be in for a very long wait while every 543 * EEPROM read fails 544 */ 545 status = hw->eeprom.ops.read(hw, 0, &checksum); 546 547 if (status != IXGBE_SUCCESS) 548 DEBUGOUT("EEPROM read failed\n"); 549 550 if (hw->mac.ops.acquire_swfw_sync(hw, IXGBE_GSSR_EEP_SM) == 551 IXGBE_SUCCESS) { 552 checksum = hw->eeprom.ops.calc_checksum(hw); 553 554 /* 555 * Do not use hw->eeprom.ops.write because we do not want to 556 * take the synchronization semaphores twice here. 557 */ 558 status = ixgbe_write_eewr_generic(hw, IXGBE_EEPROM_CHECKSUM, 559 checksum); 560 561 if (status == IXGBE_SUCCESS) 562 status = ixgbe_update_flash_X540(hw); 563 hw->mac.ops.release_swfw_sync(hw, IXGBE_GSSR_EEP_SM); 564 } else { 565 status = IXGBE_ERR_SWFW_SYNC; 566 } 567 568 return status; 569 } 570 571 /** 572 * ixgbe_update_flash_X540 - Instruct HW to copy EEPROM to Flash device 573 * @hw: pointer to hardware structure 574 * 575 * Set FLUP (bit 23) of the EEC register to instruct Hardware to copy 576 * EEPROM from shadow RAM to the flash device. 577 **/ 578 int32_t ixgbe_update_flash_X540(struct ixgbe_hw *hw) 579 { 580 uint32_t flup; 581 int32_t status = IXGBE_ERR_EEPROM; 582 583 DEBUGFUNC("ixgbe_update_flash_X540"); 584 585 status = ixgbe_poll_flash_update_done_X540(hw); 586 if (status == IXGBE_ERR_EEPROM) { 587 DEBUGOUT("Flash update time out\n"); 588 goto out; 589 } 590 591 flup = IXGBE_READ_REG(hw, IXGBE_EEC) | IXGBE_EEC_FLUP; 592 IXGBE_WRITE_REG(hw, IXGBE_EEC, flup); 593 594 status = ixgbe_poll_flash_update_done_X540(hw); 595 if (status == IXGBE_SUCCESS) 596 DEBUGOUT("Flash update complete\n"); 597 else 598 DEBUGOUT("Flash update time out\n"); 599 600 if (hw->mac.type == ixgbe_mac_X540 && hw->revision_id == 0) { 601 flup = IXGBE_READ_REG(hw, IXGBE_EEC); 602 603 if (flup & IXGBE_EEC_SEC1VAL) { 604 flup |= IXGBE_EEC_FLUP; 605 IXGBE_WRITE_REG(hw, IXGBE_EEC, flup); 606 } 607 608 status = ixgbe_poll_flash_update_done_X540(hw); 609 if (status == IXGBE_SUCCESS) 610 DEBUGOUT("Flash update complete\n"); 611 else 612 DEBUGOUT("Flash update time out\n"); 613 } 614 out: 615 return status; 616 } 617 618 /** 619 * ixgbe_poll_flash_update_done_X540 - Poll flash update status 620 * @hw: pointer to hardware structure 621 * 622 * Polls the FLUDONE (bit 26) of the EEC Register to determine when the 623 * flash update is done. 624 **/ 625 int32_t ixgbe_poll_flash_update_done_X540(struct ixgbe_hw *hw) 626 { 627 uint32_t i; 628 uint32_t reg; 629 int32_t status = IXGBE_ERR_EEPROM; 630 631 DEBUGFUNC("ixgbe_poll_flash_update_done_X540"); 632 633 for (i = 0; i < IXGBE_FLUDONE_ATTEMPTS; i++) { 634 reg = IXGBE_READ_REG(hw, IXGBE_EEC); 635 if (reg & IXGBE_EEC_FLUDONE) { 636 status = IXGBE_SUCCESS; 637 break; 638 } 639 usec_delay(5); 640 } 641 return status; 642 } 643 644 /** 645 * ixgbe_acquire_swfw_sync_X540 - Acquire SWFW semaphore 646 * @hw: pointer to hardware structure 647 * @mask: Mask to specify which semaphore to acquire 648 * 649 * Acquires the SWFW semaphore thought the SW_FW_SYNC register for 650 * the specified function (CSR, PHY0, PHY1, NVM, Flash) 651 **/ 652 int32_t ixgbe_acquire_swfw_sync_X540(struct ixgbe_hw *hw, uint16_t mask) 653 { 654 uint32_t swfw_sync; 655 uint32_t swmask = mask; 656 uint32_t fwmask = mask << 5; 657 uint32_t hwmask = 0; 658 uint32_t timeout = 200; 659 uint32_t i; 660 int32_t ret_val = IXGBE_SUCCESS; 661 662 DEBUGFUNC("ixgbe_acquire_swfw_sync_X540"); 663 664 if (swmask == IXGBE_GSSR_EEP_SM) 665 hwmask = IXGBE_GSSR_FLASH_SM; 666 667 /* SW only mask doesn't have FW bit pair */ 668 if (swmask == IXGBE_GSSR_SW_MNG_SM) 669 fwmask = 0; 670 671 for (i = 0; i < timeout; i++) { 672 /* 673 * SW NVM semaphore bit is used for access to all 674 * SW_FW_SYNC bits (not just NVM) 675 */ 676 if (ixgbe_get_swfw_sync_semaphore(hw)) { 677 ret_val = IXGBE_ERR_SWFW_SYNC; 678 goto out; 679 } 680 681 swfw_sync = IXGBE_READ_REG(hw, IXGBE_SWFW_SYNC); 682 if (!(swfw_sync & (fwmask | swmask | hwmask))) { 683 swfw_sync |= swmask; 684 IXGBE_WRITE_REG(hw, IXGBE_SWFW_SYNC, swfw_sync); 685 ixgbe_release_swfw_sync_semaphore(hw); 686 goto out; 687 } else { 688 /* 689 * Firmware currently using resource (fwmask), hardware 690 * currently using resource (hwmask), or other software 691 * thread currently using resource (swmask) 692 */ 693 ixgbe_release_swfw_sync_semaphore(hw); 694 msec_delay(5); 695 } 696 } 697 698 /* Failed to get SW only semaphore */ 699 if (swmask == IXGBE_GSSR_SW_MNG_SM) { 700 ret_val = IXGBE_ERR_SWFW_SYNC; 701 goto out; 702 } 703 704 /* If the resource is not released by the FW/HW the SW can assume that 705 * the FW/HW malfunctions. In that case the SW should set the SW bit(s) 706 * of the requested resource(s) while ignoring the corresponding FW/HW 707 * bits in the SW_FW_SYNC register. 708 */ 709 swfw_sync = IXGBE_READ_REG(hw, IXGBE_SWFW_SYNC); 710 if (swfw_sync & (fwmask | hwmask)) { 711 if (ixgbe_get_swfw_sync_semaphore(hw)) { 712 ret_val = IXGBE_ERR_SWFW_SYNC; 713 goto out; 714 } 715 716 swfw_sync |= swmask; 717 IXGBE_WRITE_REG(hw, IXGBE_SWFW_SYNC, swfw_sync); 718 ixgbe_release_swfw_sync_semaphore(hw); 719 msec_delay(5); 720 } 721 /* If the resource is not released by other SW the SW can assume that 722 * the other SW malfunctions. In that case the SW should clear all SW 723 * flags that it does not own and then repeat the whole process once 724 * again. 725 */ 726 else if (swfw_sync & swmask) { 727 ixgbe_release_swfw_sync_X540(hw, IXGBE_GSSR_EEP_SM | 728 IXGBE_GSSR_PHY0_SM | IXGBE_GSSR_PHY1_SM | 729 IXGBE_GSSR_MAC_CSR_SM); 730 ret_val = IXGBE_ERR_SWFW_SYNC; 731 } 732 733 out: 734 return ret_val; 735 } 736 737 /** 738 * ixgbe_release_swfw_sync_X540 - Release SWFW semaphore 739 * @hw: pointer to hardware structure 740 * @mask: Mask to specify which semaphore to release 741 * 742 * Releases the SWFW semaphore through the SW_FW_SYNC register 743 * for the specified function (CSR, PHY0, PHY1, EVM, Flash) 744 **/ 745 void ixgbe_release_swfw_sync_X540(struct ixgbe_hw *hw, uint16_t mask) 746 { 747 uint32_t swfw_sync; 748 uint32_t swmask = mask; 749 750 DEBUGFUNC("ixgbe_release_swfw_sync_X540"); 751 752 ixgbe_get_swfw_sync_semaphore(hw); 753 754 swfw_sync = IXGBE_READ_REG(hw, IXGBE_SWFW_SYNC); 755 swfw_sync &= ~swmask; 756 IXGBE_WRITE_REG(hw, IXGBE_SWFW_SYNC, swfw_sync); 757 758 ixgbe_release_swfw_sync_semaphore(hw); 759 } 760 761 /** 762 * ixgbe_get_nvm_semaphore - Get hardware semaphore 763 * @hw: pointer to hardware structure 764 * 765 * Sets the hardware semaphores so SW/FW can gain control of shared resources 766 **/ 767 int32_t ixgbe_get_swfw_sync_semaphore(struct ixgbe_hw *hw) 768 { 769 int32_t status = IXGBE_ERR_EEPROM; 770 uint32_t timeout = 2000; 771 uint32_t i; 772 uint32_t swsm; 773 774 DEBUGFUNC("ixgbe_get_swfw_sync_semaphore"); 775 776 /* Get SMBI software semaphore between device drivers first */ 777 for (i = 0; i < timeout; i++) { 778 /* 779 * If the SMBI bit is 0 when we read it, then the bit will be 780 * set and we have the semaphore 781 */ 782 swsm = IXGBE_READ_REG(hw, IXGBE_SWSM); 783 if (!(swsm & IXGBE_SWSM_SMBI)) { 784 status = IXGBE_SUCCESS; 785 break; 786 } 787 usec_delay(50); 788 } 789 790 /* Now get the semaphore between SW/FW through the REGSMP bit */ 791 if (status == IXGBE_SUCCESS) { 792 for (i = 0; i < timeout; i++) { 793 swsm = IXGBE_READ_REG(hw, IXGBE_SWFW_SYNC); 794 if (!(swsm & IXGBE_SWFW_REGSMP)) 795 break; 796 797 usec_delay(50); 798 } 799 800 /* 801 * Release semaphores and return error if SW NVM semaphore 802 * was not granted because we don't have access to the EEPROM 803 */ 804 if (i >= timeout) { 805 DEBUGOUT("REGSMP Software NVM semaphore not " 806 "granted.\n"); 807 ixgbe_release_swfw_sync_semaphore(hw); 808 status = IXGBE_ERR_EEPROM; 809 } 810 } else { 811 DEBUGOUT("Software semaphore SMBI between device drivers " 812 "not granted.\n"); 813 } 814 815 return status; 816 } 817 818 /** 819 * ixgbe_release_nvm_semaphore - Release hardware semaphore 820 * @hw: pointer to hardware structure 821 * 822 * This function clears hardware semaphore bits. 823 **/ 824 void ixgbe_release_swfw_sync_semaphore(struct ixgbe_hw *hw) 825 { 826 uint32_t swsm; 827 828 DEBUGFUNC("ixgbe_release_swfw_sync_semaphore"); 829 830 /* Release both semaphores by writing 0 to the bits REGSMP and SMBI */ 831 832 swsm = IXGBE_READ_REG(hw, IXGBE_SWSM); 833 swsm &= ~IXGBE_SWSM_SMBI; 834 IXGBE_WRITE_REG(hw, IXGBE_SWSM, swsm); 835 836 swsm = IXGBE_READ_REG(hw, IXGBE_SWFW_SYNC); 837 swsm &= ~IXGBE_SWFW_REGSMP; 838 IXGBE_WRITE_REG(hw, IXGBE_SWFW_SYNC, swsm); 839 840 IXGBE_WRITE_FLUSH(hw); 841 } 842 843 /** 844 * ixgbe_blink_led_start_X540 - Blink LED based on index. 845 * @hw: pointer to hardware structure 846 * @index: led number to blink 847 * 848 * Devices that implement the version 2 interface: 849 * X540 850 **/ 851 int32_t ixgbe_blink_led_start_X540(struct ixgbe_hw *hw, uint32_t index) 852 { 853 uint32_t macc_reg; 854 uint32_t ledctl_reg; 855 ixgbe_link_speed speed; 856 bool link_up; 857 858 DEBUGFUNC("ixgbe_blink_led_start_X540"); 859 860 /* 861 * Link should be up in order for the blink bit in the LED control 862 * register to work. Force link and speed in the MAC if link is down. 863 * This will be reversed when we stop the blinking. 864 */ 865 hw->mac.ops.check_link(hw, &speed, &link_up, FALSE); 866 if (link_up == FALSE) { 867 macc_reg = IXGBE_READ_REG(hw, IXGBE_MACC); 868 macc_reg |= IXGBE_MACC_FLU | IXGBE_MACC_FSV_10G | IXGBE_MACC_FS; 869 IXGBE_WRITE_REG(hw, IXGBE_MACC, macc_reg); 870 } 871 /* Set the LED to LINK_UP + BLINK. */ 872 ledctl_reg = IXGBE_READ_REG(hw, IXGBE_LEDCTL); 873 ledctl_reg &= ~IXGBE_LED_MODE_MASK(index); 874 ledctl_reg |= IXGBE_LED_BLINK(index); 875 IXGBE_WRITE_REG(hw, IXGBE_LEDCTL, ledctl_reg); 876 IXGBE_WRITE_FLUSH(hw); 877 878 return IXGBE_SUCCESS; 879 } 880 881 /** 882 * ixgbe_blink_led_stop_X540 - Stop blinking LED based on index. 883 * @hw: pointer to hardware structure 884 * @index: led number to stop blinking 885 * 886 * Devices that implement the version 2 interface: 887 * X540 888 **/ 889 int32_t ixgbe_blink_led_stop_X540(struct ixgbe_hw *hw, uint32_t index) 890 { 891 uint32_t macc_reg; 892 uint32_t ledctl_reg; 893 894 DEBUGFUNC("ixgbe_blink_led_stop_X540"); 895 896 /* Restore the LED to its default value. */ 897 ledctl_reg = IXGBE_READ_REG(hw, IXGBE_LEDCTL); 898 ledctl_reg &= ~IXGBE_LED_MODE_MASK(index); 899 ledctl_reg |= IXGBE_LED_LINK_ACTIVE << IXGBE_LED_MODE_SHIFT(index); 900 ledctl_reg &= ~IXGBE_LED_BLINK(index); 901 IXGBE_WRITE_REG(hw, IXGBE_LEDCTL, ledctl_reg); 902 903 /* Unforce link and speed in the MAC. */ 904 macc_reg = IXGBE_READ_REG(hw, IXGBE_MACC); 905 macc_reg &= ~(IXGBE_MACC_FLU | IXGBE_MACC_FSV_10G | IXGBE_MACC_FS); 906 IXGBE_WRITE_REG(hw, IXGBE_MACC, macc_reg); 907 IXGBE_WRITE_FLUSH(hw); 908 909 return IXGBE_SUCCESS; 910 } 911