1 /* $OpenBSD: ixgbe_phy.c,v 1.6 2011/06/10 12:46:35 claudio Exp $ */ 2 3 /****************************************************************************** 4 5 Copyright (c) 2001-2009, Intel Corporation 6 All rights reserved. 7 8 Redistribution and use in source and binary forms, with or without 9 modification, are permitted provided that the following conditions are met: 10 11 1. Redistributions of source code must retain the above copyright notice, 12 this list of conditions and the following disclaimer. 13 14 2. Redistributions in binary form must reproduce the above copyright 15 notice, this list of conditions and the following disclaimer in the 16 documentation and/or other materials provided with the distribution. 17 18 3. Neither the name of the Intel Corporation nor the names of its 19 contributors may be used to endorse or promote products derived from 20 this software without specific prior written permission. 21 22 THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS" 23 AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE 24 IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE 25 ARE DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT OWNER OR CONTRIBUTORS BE 26 LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR 27 CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF 28 SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS 29 INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN 30 CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) 31 ARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE 32 POSSIBILITY OF SUCH DAMAGE. 33 34 ******************************************************************************/ 35 /*$FreeBSD: src/sys/dev/ixgbe/ixgbe_phy.c,v 1.9 2009/12/07 21:30:54 jfv Exp $*/ 36 37 #include <dev/pci/ixgbe.h> 38 39 void ixgbe_i2c_start(struct ixgbe_hw *hw); 40 void ixgbe_i2c_stop(struct ixgbe_hw *hw); 41 int32_t ixgbe_clock_in_i2c_byte(struct ixgbe_hw *hw, uint8_t *data); 42 int32_t ixgbe_clock_out_i2c_byte(struct ixgbe_hw *hw, uint8_t data); 43 int32_t ixgbe_get_i2c_ack(struct ixgbe_hw *hw); 44 int32_t ixgbe_clock_in_i2c_bit(struct ixgbe_hw *hw, int *data); 45 int32_t ixgbe_clock_out_i2c_bit(struct ixgbe_hw *hw, int data); 46 int32_t ixgbe_raise_i2c_clk(struct ixgbe_hw *hw, uint32_t *i2cctl); 47 void ixgbe_lower_i2c_clk(struct ixgbe_hw *hw, uint32_t *i2cctl); 48 int32_t ixgbe_set_i2c_data(struct ixgbe_hw *hw, uint32_t *i2cctl, int data); 49 int ixgbe_get_i2c_data(uint32_t *i2cctl); 50 void ixgbe_i2c_bus_clear(struct ixgbe_hw *hw); 51 52 /** 53 * ixgbe_init_phy_ops_generic - Inits PHY function ptrs 54 * @hw: pointer to the hardware structure 55 * 56 * Initialize the function pointers. 57 **/ 58 int32_t ixgbe_init_phy_ops_generic(struct ixgbe_hw *hw) 59 { 60 struct ixgbe_phy_info *phy = &hw->phy; 61 62 /* PHY */ 63 phy->ops.identify = &ixgbe_identify_phy_generic; 64 phy->ops.reset = &ixgbe_reset_phy_generic; 65 phy->ops.read_reg = &ixgbe_read_phy_reg_generic; 66 phy->ops.write_reg = &ixgbe_write_phy_reg_generic; 67 phy->ops.setup_link = &ixgbe_setup_phy_link_generic; 68 phy->ops.setup_link_speed = &ixgbe_setup_phy_link_speed_generic; 69 phy->ops.check_link = NULL; 70 phy->ops.get_firmware_version = ixgbe_get_phy_firmware_version_generic; 71 phy->ops.read_i2c_byte = &ixgbe_read_i2c_byte_generic; 72 phy->ops.write_i2c_byte = &ixgbe_write_i2c_byte_generic; 73 phy->ops.read_i2c_eeprom = &ixgbe_read_i2c_eeprom_generic; 74 phy->ops.write_i2c_eeprom = &ixgbe_write_i2c_eeprom_generic; 75 phy->ops.i2c_bus_clear = &ixgbe_i2c_bus_clear; 76 phy->ops.identify_sfp = &ixgbe_identify_sfp_module_generic; 77 phy->sfp_type = ixgbe_sfp_type_unknown; 78 phy->ops.check_overtemp = &ixgbe_tn_check_overtemp; 79 return IXGBE_SUCCESS; 80 } 81 82 /** 83 * ixgbe_identify_phy_generic - Get physical layer module 84 * @hw: pointer to hardware structure 85 * 86 * Determines the physical layer module found on the current adapter. 87 **/ 88 int32_t ixgbe_identify_phy_generic(struct ixgbe_hw *hw) 89 { 90 int32_t status = IXGBE_ERR_PHY_ADDR_INVALID; 91 uint32_t phy_addr; 92 uint16_t ext_ability = 0; 93 94 if (hw->phy.type == ixgbe_phy_unknown) { 95 for (phy_addr = 0; phy_addr < IXGBE_MAX_PHY_ADDR; phy_addr++) { 96 if (ixgbe_validate_phy_addr(hw, phy_addr)) { 97 hw->phy.addr = phy_addr; 98 ixgbe_get_phy_id(hw); 99 hw->phy.type = 100 ixgbe_get_phy_type_from_id(hw->phy.id); 101 102 if (hw->phy.type == ixgbe_phy_unknown) { 103 hw->phy.ops.read_reg(hw, 104 IXGBE_MDIO_PHY_EXT_ABILITY, 105 IXGBE_MDIO_PMA_PMD_DEV_TYPE, 106 &ext_ability); 107 if (ext_ability & 108 (IXGBE_MDIO_PHY_10GBASET_ABILITY | 109 IXGBE_MDIO_PHY_1000BASET_ABILITY)) 110 hw->phy.type = 111 ixgbe_phy_cu_unknown; 112 else 113 hw->phy.type = 114 ixgbe_phy_generic; 115 } 116 117 status = IXGBE_SUCCESS; 118 break; 119 } 120 } 121 /* clear value if nothing found */ 122 if (status != IXGBE_SUCCESS) 123 hw->phy.addr = 0; 124 } else { 125 status = IXGBE_SUCCESS; 126 } 127 128 return status; 129 } 130 131 /** 132 * ixgbe_validate_phy_addr - Determines phy address is valid 133 * @hw: pointer to hardware structure 134 * 135 **/ 136 int ixgbe_validate_phy_addr(struct ixgbe_hw *hw, uint32_t phy_addr) 137 { 138 uint16_t phy_id = 0; 139 int valid = FALSE; 140 141 hw->phy.addr = phy_addr; 142 hw->phy.ops.read_reg(hw, IXGBE_MDIO_PHY_ID_HIGH, 143 IXGBE_MDIO_PMA_PMD_DEV_TYPE, &phy_id); 144 145 if (phy_id != 0xFFFF && phy_id != 0x0) 146 valid = TRUE; 147 148 return valid; 149 } 150 151 /** 152 * ixgbe_get_phy_id - Get the phy type 153 * @hw: pointer to hardware structure 154 * 155 **/ 156 int32_t ixgbe_get_phy_id(struct ixgbe_hw *hw) 157 { 158 uint32_t status; 159 uint16_t phy_id_high = 0; 160 uint16_t phy_id_low = 0; 161 162 status = hw->phy.ops.read_reg(hw, IXGBE_MDIO_PHY_ID_HIGH, 163 IXGBE_MDIO_PMA_PMD_DEV_TYPE, 164 &phy_id_high); 165 166 if (status == IXGBE_SUCCESS) { 167 hw->phy.id = (uint32_t)(phy_id_high << 16); 168 status = hw->phy.ops.read_reg(hw, IXGBE_MDIO_PHY_ID_LOW, 169 IXGBE_MDIO_PMA_PMD_DEV_TYPE, 170 &phy_id_low); 171 hw->phy.id |= (uint32_t)(phy_id_low & IXGBE_PHY_REVISION_MASK); 172 hw->phy.revision = (uint32_t)(phy_id_low & ~IXGBE_PHY_REVISION_MASK); 173 } 174 return status; 175 } 176 177 /** 178 * ixgbe_get_phy_type_from_id - Get the phy type 179 * @hw: pointer to hardware structure 180 * 181 **/ 182 enum ixgbe_phy_type ixgbe_get_phy_type_from_id(uint32_t phy_id) 183 { 184 enum ixgbe_phy_type phy_type; 185 186 switch (phy_id) { 187 case TN1010_PHY_ID: 188 phy_type = ixgbe_phy_tn; 189 break; 190 case AQ1002_PHY_ID: 191 phy_type = ixgbe_phy_aq; 192 break; 193 case QT2022_PHY_ID: 194 phy_type = ixgbe_phy_qt; 195 break; 196 case ATH_PHY_ID: 197 phy_type = ixgbe_phy_nl; 198 break; 199 default: 200 phy_type = ixgbe_phy_unknown; 201 break; 202 } 203 204 DEBUGOUT1("phy type found is %d\n", phy_type); 205 return phy_type; 206 } 207 208 /** 209 * ixgbe_reset_phy_generic - Performs a PHY reset 210 * @hw: pointer to hardware structure 211 **/ 212 int32_t ixgbe_reset_phy_generic(struct ixgbe_hw *hw) 213 { 214 int32_t i; 215 uint16_t ctrl = 0; 216 int32_t status = IXGBE_SUCCESS; 217 218 if (hw->phy.type == ixgbe_phy_unknown) 219 status = ixgbe_identify_phy_generic(hw); 220 221 if (status != IXGBE_SUCCESS || hw->phy.type == ixgbe_phy_none) 222 goto out; 223 224 /* Don't reset PHY if it's shut down due to overtemp. */ 225 if (!hw->phy.reset_if_overtemp && 226 (IXGBE_ERR_OVERTEMP == hw->phy.ops.check_overtemp(hw))) 227 goto out; 228 229 /* 230 * Perform soft PHY reset to the PHY_XS. 231 * This will cause a soft reset to the PHY 232 */ 233 hw->phy.ops.write_reg(hw, IXGBE_MDIO_PHY_XS_CONTROL, 234 IXGBE_MDIO_PHY_XS_DEV_TYPE, 235 IXGBE_MDIO_PHY_XS_RESET); 236 237 /* 238 * Poll for reset bit to self-clear indicating reset is complete. 239 * Some PHYs could take up to 3 seconds to complete and need about 240 * 1.7 usec delay after the reset is complete. 241 */ 242 for (i = 0; i < 30; i++) { 243 msec_delay(100); 244 hw->phy.ops.read_reg(hw, IXGBE_MDIO_PHY_XS_CONTROL, 245 IXGBE_MDIO_PHY_XS_DEV_TYPE, &ctrl); 246 if (!(ctrl & IXGBE_MDIO_PHY_XS_RESET)) { 247 usec_delay(2); 248 break; 249 } 250 } 251 252 if (ctrl & IXGBE_MDIO_PHY_XS_RESET) { 253 status = IXGBE_ERR_RESET_FAILED; 254 DEBUGOUT("PHY reset polling failed to complete.\n"); 255 } 256 257 out: 258 return status; 259 } 260 261 /** 262 * ixgbe_read_phy_reg_generic - Reads a value from a specified PHY register 263 * @hw: pointer to hardware structure 264 * @reg_addr: 32 bit address of PHY register to read 265 * @phy_data: Pointer to read data from PHY register 266 **/ 267 int32_t ixgbe_read_phy_reg_generic(struct ixgbe_hw *hw, uint32_t reg_addr, 268 uint32_t device_type, uint16_t *phy_data) 269 { 270 uint32_t command; 271 uint32_t i; 272 uint32_t data; 273 int32_t status = IXGBE_SUCCESS; 274 uint16_t gssr; 275 276 if (IXGBE_READ_REG(hw, IXGBE_STATUS) & IXGBE_STATUS_LAN_ID_1) 277 gssr = IXGBE_GSSR_PHY1_SM; 278 else 279 gssr = IXGBE_GSSR_PHY0_SM; 280 281 if (ixgbe_acquire_swfw_sync(hw, gssr) != IXGBE_SUCCESS) 282 status = IXGBE_ERR_SWFW_SYNC; 283 284 if (status == IXGBE_SUCCESS) { 285 /* Setup and write the address cycle command */ 286 command = ((reg_addr << IXGBE_MSCA_NP_ADDR_SHIFT) | 287 (device_type << IXGBE_MSCA_DEV_TYPE_SHIFT) | 288 (hw->phy.addr << IXGBE_MSCA_PHY_ADDR_SHIFT) | 289 (IXGBE_MSCA_ADDR_CYCLE | IXGBE_MSCA_MDI_COMMAND)); 290 291 IXGBE_WRITE_REG(hw, IXGBE_MSCA, command); 292 293 /* 294 * Check every 10 usec to see if the address cycle completed. 295 * The MDI Command bit will clear when the operation is 296 * complete 297 */ 298 for (i = 0; i < IXGBE_MDIO_COMMAND_TIMEOUT; i++) { 299 usec_delay(10); 300 301 command = IXGBE_READ_REG(hw, IXGBE_MSCA); 302 303 if ((command & IXGBE_MSCA_MDI_COMMAND) == 0) 304 break; 305 } 306 307 if ((command & IXGBE_MSCA_MDI_COMMAND) != 0) { 308 DEBUGOUT("PHY address command did not complete.\n"); 309 status = IXGBE_ERR_PHY; 310 } 311 312 if (status == IXGBE_SUCCESS) { 313 /* 314 * Address cycle complete, setup and write the read 315 * command 316 */ 317 command = ((reg_addr << IXGBE_MSCA_NP_ADDR_SHIFT) | 318 (device_type << IXGBE_MSCA_DEV_TYPE_SHIFT) | 319 (hw->phy.addr << IXGBE_MSCA_PHY_ADDR_SHIFT) | 320 (IXGBE_MSCA_READ | IXGBE_MSCA_MDI_COMMAND)); 321 322 IXGBE_WRITE_REG(hw, IXGBE_MSCA, command); 323 324 /* 325 * Check every 10 usec to see if the address cycle 326 * completed. The MDI Command bit will clear when the 327 * operation is complete 328 */ 329 for (i = 0; i < IXGBE_MDIO_COMMAND_TIMEOUT; i++) { 330 usec_delay(10); 331 332 command = IXGBE_READ_REG(hw, IXGBE_MSCA); 333 334 if ((command & IXGBE_MSCA_MDI_COMMAND) == 0) 335 break; 336 } 337 338 if ((command & IXGBE_MSCA_MDI_COMMAND) != 0) { 339 DEBUGOUT("PHY read command didn't complete\n"); 340 status = IXGBE_ERR_PHY; 341 } else { 342 /* 343 * Read operation is complete. Get the data 344 * from MSRWD 345 */ 346 data = IXGBE_READ_REG(hw, IXGBE_MSRWD); 347 data >>= IXGBE_MSRWD_READ_DATA_SHIFT; 348 *phy_data = (uint16_t)(data); 349 } 350 } 351 352 ixgbe_release_swfw_sync(hw, gssr); 353 } 354 355 return status; 356 } 357 358 /** 359 * ixgbe_write_phy_reg_generic - Writes a value to specified PHY register 360 * @hw: pointer to hardware structure 361 * @reg_addr: 32 bit PHY register to write 362 * @device_type: 5 bit device type 363 * @phy_data: Data to write to the PHY register 364 **/ 365 int32_t ixgbe_write_phy_reg_generic(struct ixgbe_hw *hw, uint32_t reg_addr, 366 uint32_t device_type, uint16_t phy_data) 367 { 368 uint32_t command; 369 uint32_t i; 370 int32_t status = IXGBE_SUCCESS; 371 uint16_t gssr; 372 373 if (IXGBE_READ_REG(hw, IXGBE_STATUS) & IXGBE_STATUS_LAN_ID_1) 374 gssr = IXGBE_GSSR_PHY1_SM; 375 else 376 gssr = IXGBE_GSSR_PHY0_SM; 377 378 if (ixgbe_acquire_swfw_sync(hw, gssr) != IXGBE_SUCCESS) 379 status = IXGBE_ERR_SWFW_SYNC; 380 381 if (status == IXGBE_SUCCESS) { 382 /* Put the data in the MDI single read and write data register*/ 383 IXGBE_WRITE_REG(hw, IXGBE_MSRWD, (uint32_t)phy_data); 384 385 /* Setup and write the address cycle command */ 386 command = ((reg_addr << IXGBE_MSCA_NP_ADDR_SHIFT) | 387 (device_type << IXGBE_MSCA_DEV_TYPE_SHIFT) | 388 (hw->phy.addr << IXGBE_MSCA_PHY_ADDR_SHIFT) | 389 (IXGBE_MSCA_ADDR_CYCLE | IXGBE_MSCA_MDI_COMMAND)); 390 391 IXGBE_WRITE_REG(hw, IXGBE_MSCA, command); 392 393 /* 394 * Check every 10 usec to see if the address cycle completed. 395 * The MDI Command bit will clear when the operation is 396 * complete 397 */ 398 for (i = 0; i < IXGBE_MDIO_COMMAND_TIMEOUT; i++) { 399 usec_delay(10); 400 401 command = IXGBE_READ_REG(hw, IXGBE_MSCA); 402 403 if ((command & IXGBE_MSCA_MDI_COMMAND) == 0) 404 break; 405 } 406 407 if ((command & IXGBE_MSCA_MDI_COMMAND) != 0) { 408 DEBUGOUT("PHY address cmd didn't complete\n"); 409 status = IXGBE_ERR_PHY; 410 } 411 412 if (status == IXGBE_SUCCESS) { 413 /* 414 * Address cycle complete, setup and write the write 415 * command 416 */ 417 command = ((reg_addr << IXGBE_MSCA_NP_ADDR_SHIFT) | 418 (device_type << IXGBE_MSCA_DEV_TYPE_SHIFT) | 419 (hw->phy.addr << IXGBE_MSCA_PHY_ADDR_SHIFT) | 420 (IXGBE_MSCA_WRITE | IXGBE_MSCA_MDI_COMMAND)); 421 422 IXGBE_WRITE_REG(hw, IXGBE_MSCA, command); 423 424 /* 425 * Check every 10 usec to see if the address cycle 426 * completed. The MDI Command bit will clear when the 427 * operation is complete 428 */ 429 for (i = 0; i < IXGBE_MDIO_COMMAND_TIMEOUT; i++) { 430 usec_delay(10); 431 432 command = IXGBE_READ_REG(hw, IXGBE_MSCA); 433 434 if ((command & IXGBE_MSCA_MDI_COMMAND) == 0) 435 break; 436 } 437 438 if ((command & IXGBE_MSCA_MDI_COMMAND) != 0) { 439 DEBUGOUT("PHY address cmd didn't complete\n"); 440 status = IXGBE_ERR_PHY; 441 } 442 } 443 444 ixgbe_release_swfw_sync(hw, gssr); 445 } 446 447 return status; 448 } 449 450 /** 451 * ixgbe_setup_phy_link_generic - Set and restart autoneg 452 * @hw: pointer to hardware structure 453 * 454 * Restart autonegotiation and PHY and waits for completion. 455 **/ 456 int32_t ixgbe_setup_phy_link_generic(struct ixgbe_hw *hw) 457 { 458 int32_t status = IXGBE_SUCCESS; 459 uint32_t time_out; 460 uint32_t max_time_out = 10; 461 uint16_t autoneg_reg = IXGBE_MII_AUTONEG_REG; 462 int autoneg = 0; 463 ixgbe_link_speed speed; 464 465 466 ixgbe_get_copper_link_capabilities_generic(hw, &speed, &autoneg); 467 468 if (speed & IXGBE_LINK_SPEED_10GB_FULL) { 469 /* Set or unset auto-negotiation 10G advertisement */ 470 hw->phy.ops.read_reg(hw, IXGBE_MII_10GBASE_T_AUTONEG_CTRL_REG, 471 IXGBE_MDIO_AUTO_NEG_DEV_TYPE, 472 &autoneg_reg); 473 474 autoneg_reg &= ~IXGBE_MII_10GBASE_T_ADVERTISE; 475 if (hw->phy.autoneg_advertised & IXGBE_LINK_SPEED_10GB_FULL) 476 autoneg_reg |= IXGBE_MII_10GBASE_T_ADVERTISE; 477 478 hw->phy.ops.write_reg(hw, IXGBE_MII_10GBASE_T_AUTONEG_CTRL_REG, 479 IXGBE_MDIO_AUTO_NEG_DEV_TYPE, 480 autoneg_reg); 481 } 482 483 if (speed & IXGBE_LINK_SPEED_1GB_FULL) { 484 /* Set or unset auto-negotiation 1G advertisement */ 485 hw->phy.ops.read_reg(hw, 486 IXGBE_MII_AUTONEG_VENDOR_PROVISION_1_REG, 487 IXGBE_MDIO_AUTO_NEG_DEV_TYPE, 488 &autoneg_reg); 489 490 autoneg_reg &= ~IXGBE_MII_1GBASE_T_ADVERTISE; 491 if (hw->phy.autoneg_advertised & IXGBE_LINK_SPEED_1GB_FULL) 492 autoneg_reg |= IXGBE_MII_1GBASE_T_ADVERTISE; 493 494 hw->phy.ops.write_reg(hw, 495 IXGBE_MII_AUTONEG_VENDOR_PROVISION_1_REG, 496 IXGBE_MDIO_AUTO_NEG_DEV_TYPE, 497 autoneg_reg); 498 } 499 500 if (speed & IXGBE_LINK_SPEED_100_FULL) { 501 /* Set or unset auto-negotiation 100M advertisement */ 502 hw->phy.ops.read_reg(hw, IXGBE_MII_AUTONEG_ADVERTISE_REG, 503 IXGBE_MDIO_AUTO_NEG_DEV_TYPE, 504 &autoneg_reg); 505 506 autoneg_reg &= ~IXGBE_MII_100BASE_T_ADVERTISE; 507 if (hw->phy.autoneg_advertised & IXGBE_LINK_SPEED_100_FULL) 508 autoneg_reg |= IXGBE_MII_100BASE_T_ADVERTISE; 509 510 hw->phy.ops.write_reg(hw, IXGBE_MII_AUTONEG_ADVERTISE_REG, 511 IXGBE_MDIO_AUTO_NEG_DEV_TYPE, 512 autoneg_reg); 513 } 514 515 /* Restart PHY autonegotiation and wait for completion */ 516 hw->phy.ops.read_reg(hw, IXGBE_MDIO_AUTO_NEG_CONTROL, 517 IXGBE_MDIO_AUTO_NEG_DEV_TYPE, &autoneg_reg); 518 519 autoneg_reg |= IXGBE_MII_RESTART; 520 521 hw->phy.ops.write_reg(hw, IXGBE_MDIO_AUTO_NEG_CONTROL, 522 IXGBE_MDIO_AUTO_NEG_DEV_TYPE, autoneg_reg); 523 524 /* Wait for autonegotiation to finish */ 525 for (time_out = 0; time_out < max_time_out; time_out++) { 526 usec_delay(10); 527 /* Restart PHY autonegotiation and wait for completion */ 528 status = hw->phy.ops.read_reg(hw, IXGBE_MDIO_AUTO_NEG_STATUS, 529 IXGBE_MDIO_AUTO_NEG_DEV_TYPE, 530 &autoneg_reg); 531 532 autoneg_reg &= IXGBE_MII_AUTONEG_COMPLETE; 533 if (autoneg_reg == IXGBE_MII_AUTONEG_COMPLETE) { 534 break; 535 } 536 } 537 538 if (time_out == max_time_out) { 539 status = IXGBE_ERR_LINK_SETUP; 540 DEBUGOUT("ixgbe_setup_phy_link_generic: time out"); 541 } 542 543 return status; 544 } 545 546 /** 547 * ixgbe_setup_phy_link_speed_generic - Sets the auto advertised capabilities 548 * @hw: pointer to hardware structure 549 * @speed: new link speed 550 * @autoneg: TRUE if autonegotiation enabled 551 **/ 552 int32_t ixgbe_setup_phy_link_speed_generic(struct ixgbe_hw *hw, 553 ixgbe_link_speed speed, 554 int autoneg, 555 int autoneg_wait_to_complete) 556 { 557 UNREFERENCED_PARAMETER(autoneg); 558 UNREFERENCED_PARAMETER(autoneg_wait_to_complete); 559 560 /* 561 * Clear autoneg_advertised and set new values based on input link 562 * speed. 563 */ 564 hw->phy.autoneg_advertised = 0; 565 566 if (speed & IXGBE_LINK_SPEED_10GB_FULL) 567 hw->phy.autoneg_advertised |= IXGBE_LINK_SPEED_10GB_FULL; 568 569 if (speed & IXGBE_LINK_SPEED_1GB_FULL) 570 hw->phy.autoneg_advertised |= IXGBE_LINK_SPEED_1GB_FULL; 571 572 if (speed & IXGBE_LINK_SPEED_100_FULL) 573 hw->phy.autoneg_advertised |= IXGBE_LINK_SPEED_100_FULL; 574 575 /* Setup link based on the new speed settings */ 576 hw->phy.ops.setup_link(hw); 577 578 return IXGBE_SUCCESS; 579 } 580 581 /** 582 * ixgbe_get_copper_link_capabilities_generic - Determines link capabilities 583 * @hw: pointer to hardware structure 584 * @speed: pointer to link speed 585 * @autoneg: boolean auto-negotiation value 586 * 587 * Determines the link capabilities by reading the AUTOC register. 588 **/ 589 int32_t ixgbe_get_copper_link_capabilities_generic(struct ixgbe_hw *hw, 590 ixgbe_link_speed *speed, 591 int *autoneg) 592 { 593 int32_t status = IXGBE_ERR_LINK_SETUP; 594 uint16_t speed_ability; 595 596 *speed = 0; 597 *autoneg = TRUE; 598 599 status = hw->phy.ops.read_reg(hw, IXGBE_MDIO_PHY_SPEED_ABILITY, 600 IXGBE_MDIO_PMA_PMD_DEV_TYPE, 601 &speed_ability); 602 603 if (status == IXGBE_SUCCESS) { 604 if (speed_ability & IXGBE_MDIO_PHY_SPEED_10G) 605 *speed |= IXGBE_LINK_SPEED_10GB_FULL; 606 if (speed_ability & IXGBE_MDIO_PHY_SPEED_1G) 607 *speed |= IXGBE_LINK_SPEED_1GB_FULL; 608 if (speed_ability & IXGBE_MDIO_PHY_SPEED_100M) 609 *speed |= IXGBE_LINK_SPEED_100_FULL; 610 } 611 612 return status; 613 } 614 615 /** 616 * ixgbe_check_phy_link_tnx - Determine link and speed status 617 * @hw: pointer to hardware structure 618 * 619 * Reads the VS1 register to determine if link is up and the current speed for 620 * the PHY. 621 **/ 622 int32_t ixgbe_check_phy_link_tnx(struct ixgbe_hw *hw, ixgbe_link_speed *speed, 623 int *link_up) 624 { 625 int32_t status = IXGBE_SUCCESS; 626 uint32_t time_out; 627 uint32_t max_time_out = 10; 628 uint16_t phy_link = 0; 629 uint16_t phy_speed = 0; 630 uint16_t phy_data = 0; 631 632 /* Initialize speed and link to default case */ 633 *link_up = FALSE; 634 *speed = IXGBE_LINK_SPEED_10GB_FULL; 635 636 /* 637 * Check current speed and link status of the PHY register. 638 * This is a vendor specific register and may have to 639 * be changed for other copper PHYs. 640 */ 641 for (time_out = 0; time_out < max_time_out; time_out++) { 642 usec_delay(10); 643 status = hw->phy.ops.read_reg(hw, 644 IXGBE_MDIO_VENDOR_SPECIFIC_1_STATUS, 645 IXGBE_MDIO_VENDOR_SPECIFIC_1_DEV_TYPE, 646 &phy_data); 647 phy_link = phy_data & 648 IXGBE_MDIO_VENDOR_SPECIFIC_1_LINK_STATUS; 649 phy_speed = phy_data & 650 IXGBE_MDIO_VENDOR_SPECIFIC_1_SPEED_STATUS; 651 if (phy_link == IXGBE_MDIO_VENDOR_SPECIFIC_1_LINK_STATUS) { 652 *link_up = TRUE; 653 if (phy_speed == 654 IXGBE_MDIO_VENDOR_SPECIFIC_1_SPEED_STATUS) 655 *speed = IXGBE_LINK_SPEED_1GB_FULL; 656 break; 657 } 658 } 659 660 return status; 661 } 662 663 /** 664 * ixgbe_setup_phy_link_tnx - Set and restart autoneg 665 * @hw: pointer to hardware structure 666 * 667 * Restart autonegotiation and PHY and waits for completion. 668 **/ 669 int32_t ixgbe_setup_phy_link_tnx(struct ixgbe_hw *hw) 670 { 671 int32_t status = IXGBE_SUCCESS; 672 uint32_t time_out; 673 uint32_t max_time_out = 10; 674 uint16_t autoneg_reg = IXGBE_MII_AUTONEG_REG; 675 int autoneg = FALSE; 676 ixgbe_link_speed speed; 677 678 ixgbe_get_copper_link_capabilities_generic(hw, &speed, &autoneg); 679 680 if (speed & IXGBE_LINK_SPEED_10GB_FULL) { 681 /* Set or unset auto-negotiation 10G advertisement */ 682 hw->phy.ops.read_reg(hw, IXGBE_MII_10GBASE_T_AUTONEG_CTRL_REG, 683 IXGBE_MDIO_AUTO_NEG_DEV_TYPE, 684 &autoneg_reg); 685 686 autoneg_reg &= ~IXGBE_MII_10GBASE_T_ADVERTISE; 687 if (hw->phy.autoneg_advertised & IXGBE_LINK_SPEED_10GB_FULL) 688 autoneg_reg |= IXGBE_MII_10GBASE_T_ADVERTISE; 689 690 hw->phy.ops.write_reg(hw, IXGBE_MII_10GBASE_T_AUTONEG_CTRL_REG, 691 IXGBE_MDIO_AUTO_NEG_DEV_TYPE, 692 autoneg_reg); 693 } 694 695 if (speed & IXGBE_LINK_SPEED_1GB_FULL) { 696 /* Set or unset auto-negotiation 1G advertisement */ 697 hw->phy.ops.read_reg(hw, IXGBE_MII_AUTONEG_XNP_TX_REG, 698 IXGBE_MDIO_AUTO_NEG_DEV_TYPE, 699 &autoneg_reg); 700 701 autoneg_reg &= ~IXGBE_MII_1GBASE_T_ADVERTISE_XNP_TX; 702 if (hw->phy.autoneg_advertised & IXGBE_LINK_SPEED_1GB_FULL) 703 autoneg_reg |= IXGBE_MII_1GBASE_T_ADVERTISE_XNP_TX; 704 705 hw->phy.ops.write_reg(hw, IXGBE_MII_AUTONEG_XNP_TX_REG, 706 IXGBE_MDIO_AUTO_NEG_DEV_TYPE, 707 autoneg_reg); 708 } 709 710 if (speed & IXGBE_LINK_SPEED_100_FULL) { 711 /* Set or unset auto-negotiation 100M advertisement */ 712 hw->phy.ops.read_reg(hw, IXGBE_MII_AUTONEG_ADVERTISE_REG, 713 IXGBE_MDIO_AUTO_NEG_DEV_TYPE, 714 &autoneg_reg); 715 716 autoneg_reg &= ~IXGBE_MII_100BASE_T_ADVERTISE; 717 if (hw->phy.autoneg_advertised & IXGBE_LINK_SPEED_100_FULL) 718 autoneg_reg |= IXGBE_MII_100BASE_T_ADVERTISE; 719 720 hw->phy.ops.write_reg(hw, IXGBE_MII_AUTONEG_ADVERTISE_REG, 721 IXGBE_MDIO_AUTO_NEG_DEV_TYPE, 722 autoneg_reg); 723 } 724 725 /* Restart PHY autonegotiation and wait for completion */ 726 hw->phy.ops.read_reg(hw, IXGBE_MDIO_AUTO_NEG_CONTROL, 727 IXGBE_MDIO_AUTO_NEG_DEV_TYPE, &autoneg_reg); 728 729 autoneg_reg |= IXGBE_MII_RESTART; 730 731 hw->phy.ops.write_reg(hw, IXGBE_MDIO_AUTO_NEG_CONTROL, 732 IXGBE_MDIO_AUTO_NEG_DEV_TYPE, autoneg_reg); 733 734 /* Wait for autonegotiation to finish */ 735 for (time_out = 0; time_out < max_time_out; time_out++) { 736 usec_delay(10); 737 /* Restart PHY autonegotiation and wait for completion */ 738 status = hw->phy.ops.read_reg(hw, IXGBE_MDIO_AUTO_NEG_STATUS, 739 IXGBE_MDIO_AUTO_NEG_DEV_TYPE, 740 &autoneg_reg); 741 742 autoneg_reg &= IXGBE_MII_AUTONEG_COMPLETE; 743 if (autoneg_reg == IXGBE_MII_AUTONEG_COMPLETE) { 744 break; 745 } 746 } 747 748 if (time_out == max_time_out) { 749 status = IXGBE_ERR_LINK_SETUP; 750 DEBUGOUT("ixgbe_setup_phy_link_tnx: time out"); 751 } 752 753 return status; 754 } 755 756 /** 757 * ixgbe_get_phy_firmware_version_tnx - Gets the PHY Firmware Version 758 * @hw: pointer to hardware structure 759 * @firmware_version: pointer to the PHY Firmware Version 760 **/ 761 int32_t ixgbe_get_phy_firmware_version_tnx(struct ixgbe_hw *hw, 762 uint16_t *firmware_version) 763 { 764 int32_t status = IXGBE_SUCCESS; 765 766 status = hw->phy.ops.read_reg(hw, TNX_FW_REV, 767 IXGBE_MDIO_VENDOR_SPECIFIC_1_DEV_TYPE, 768 firmware_version); 769 770 return status; 771 } 772 773 /** 774 * ixgbe_get_phy_firmware_version_generic - Gets the PHY Firmware Version 775 * @hw: pointer to hardware structure 776 * @firmware_version: pointer to the PHY Firmware Version 777 **/ 778 int32_t ixgbe_get_phy_firmware_version_generic(struct ixgbe_hw *hw, 779 uint16_t *firmware_version) 780 { 781 int32_t status = IXGBE_SUCCESS; 782 783 status = hw->phy.ops.read_reg(hw, AQ_FW_REV, 784 IXGBE_MDIO_VENDOR_SPECIFIC_1_DEV_TYPE, 785 firmware_version); 786 787 return status; 788 } 789 790 /** 791 * ixgbe_reset_phy_nl - Performs a PHY reset 792 * @hw: pointer to hardware structure 793 **/ 794 int32_t ixgbe_reset_phy_nl(struct ixgbe_hw *hw) 795 { 796 uint16_t phy_offset, control, eword, edata, block_crc; 797 int end_data = FALSE; 798 uint16_t list_offset, data_offset; 799 uint16_t phy_data = 0; 800 int32_t ret_val = IXGBE_SUCCESS; 801 uint32_t i; 802 803 hw->phy.ops.read_reg(hw, IXGBE_MDIO_PHY_XS_CONTROL, 804 IXGBE_MDIO_PHY_XS_DEV_TYPE, &phy_data); 805 806 /* reset the PHY and poll for completion */ 807 hw->phy.ops.write_reg(hw, IXGBE_MDIO_PHY_XS_CONTROL, 808 IXGBE_MDIO_PHY_XS_DEV_TYPE, 809 (phy_data | IXGBE_MDIO_PHY_XS_RESET)); 810 811 for (i = 0; i < 100; i++) { 812 hw->phy.ops.read_reg(hw, IXGBE_MDIO_PHY_XS_CONTROL, 813 IXGBE_MDIO_PHY_XS_DEV_TYPE, &phy_data); 814 if ((phy_data & IXGBE_MDIO_PHY_XS_RESET) == 0) 815 break; 816 msec_delay(10); 817 } 818 819 if ((phy_data & IXGBE_MDIO_PHY_XS_RESET) != 0) { 820 DEBUGOUT("PHY reset did not complete.\n"); 821 ret_val = IXGBE_ERR_PHY; 822 goto out; 823 } 824 825 /* Get init offsets */ 826 ret_val = ixgbe_get_sfp_init_sequence_offsets(hw, &list_offset, 827 &data_offset); 828 if (ret_val != IXGBE_SUCCESS) 829 goto out; 830 831 ret_val = hw->eeprom.ops.read(hw, data_offset, &block_crc); 832 data_offset++; 833 while (!end_data) { 834 /* 835 * Read control word from PHY init contents offset 836 */ 837 ret_val = hw->eeprom.ops.read(hw, data_offset, &eword); 838 control = (eword & IXGBE_CONTROL_MASK_NL) >> 839 IXGBE_CONTROL_SHIFT_NL; 840 edata = eword & IXGBE_DATA_MASK_NL; 841 switch (control) { 842 case IXGBE_DELAY_NL: 843 data_offset++; 844 DEBUGOUT1("DELAY: %d MS\n", edata); 845 msec_delay(edata); 846 break; 847 case IXGBE_DATA_NL: 848 DEBUGOUT("DATA: \n"); 849 data_offset++; 850 hw->eeprom.ops.read(hw, data_offset++, 851 &phy_offset); 852 for (i = 0; i < edata; i++) { 853 hw->eeprom.ops.read(hw, data_offset, &eword); 854 hw->phy.ops.write_reg(hw, phy_offset, 855 IXGBE_TWINAX_DEV, eword); 856 DEBUGOUT2("Wrote %4.4x to %4.4x\n", eword, 857 phy_offset); 858 data_offset++; 859 phy_offset++; 860 } 861 break; 862 case IXGBE_CONTROL_NL: 863 data_offset++; 864 DEBUGOUT("CONTROL: \n"); 865 if (edata == IXGBE_CONTROL_EOL_NL) { 866 DEBUGOUT("EOL\n"); 867 end_data = TRUE; 868 } else if (edata == IXGBE_CONTROL_SOL_NL) { 869 DEBUGOUT("SOL\n"); 870 } else { 871 DEBUGOUT("Bad control value\n"); 872 ret_val = IXGBE_ERR_PHY; 873 goto out; 874 } 875 break; 876 default: 877 DEBUGOUT("Bad control type\n"); 878 ret_val = IXGBE_ERR_PHY; 879 goto out; 880 } 881 } 882 883 out: 884 return ret_val; 885 } 886 887 /** 888 * ixgbe_identify_sfp_module_generic - Identifies SFP modules 889 * @hw: pointer to hardware structure 890 * 891 * Searches for and identifies the SFP module and assigns appropriate PHY type. 892 **/ 893 int32_t ixgbe_identify_sfp_module_generic(struct ixgbe_hw *hw) 894 { 895 int32_t status = IXGBE_ERR_PHY_ADDR_INVALID; 896 uint32_t vendor_oui = 0; 897 enum ixgbe_sfp_type stored_sfp_type = hw->phy.sfp_type; 898 uint8_t identifier = 0; 899 uint8_t comp_codes_1g = 0; 900 uint8_t comp_codes_10g = 0; 901 uint8_t oui_bytes[3] = {0, 0, 0}; 902 uint8_t cable_tech = 0; 903 uint8_t cable_spec = 0; 904 uint16_t enforce_sfp = 0; 905 906 if (hw->mac.ops.get_media_type(hw) != ixgbe_media_type_fiber) { 907 hw->phy.sfp_type = ixgbe_sfp_type_not_present; 908 status = IXGBE_ERR_SFP_NOT_PRESENT; 909 DEBUGOUT("SFP+ not present"); 910 goto out; 911 } 912 913 status = hw->phy.ops.read_i2c_eeprom(hw, IXGBE_SFF_IDENTIFIER, 914 &identifier); 915 916 if (status == IXGBE_ERR_SWFW_SYNC || 917 status == IXGBE_ERR_I2C || 918 status == IXGBE_ERR_SFP_NOT_PRESENT) 919 goto err_read_i2c_eeprom; 920 921 /* LAN ID is needed for sfp_type determination */ 922 hw->mac.ops.set_lan_id(hw); 923 924 if (identifier != IXGBE_SFF_IDENTIFIER_SFP) { 925 hw->phy.type = ixgbe_phy_sfp_unsupported; 926 status = IXGBE_ERR_SFP_NOT_SUPPORTED; 927 } else { 928 status = hw->phy.ops.read_i2c_eeprom(hw, 929 IXGBE_SFF_1GBE_COMP_CODES, 930 &comp_codes_1g); 931 932 if (status == IXGBE_ERR_SWFW_SYNC || 933 status == IXGBE_ERR_I2C || 934 status == IXGBE_ERR_SFP_NOT_PRESENT) 935 goto err_read_i2c_eeprom; 936 937 status = hw->phy.ops.read_i2c_eeprom(hw, 938 IXGBE_SFF_10GBE_COMP_CODES, 939 &comp_codes_10g); 940 941 if (status == IXGBE_ERR_SWFW_SYNC || 942 status == IXGBE_ERR_I2C || 943 status == IXGBE_ERR_SFP_NOT_PRESENT) 944 goto err_read_i2c_eeprom; 945 status = hw->phy.ops.read_i2c_eeprom(hw, 946 IXGBE_SFF_CABLE_TECHNOLOGY, 947 &cable_tech); 948 949 if (status == IXGBE_ERR_SWFW_SYNC || 950 status == IXGBE_ERR_I2C || 951 status == IXGBE_ERR_SFP_NOT_PRESENT) 952 goto err_read_i2c_eeprom; 953 954 /* ID Module 955 * ========= 956 * 0 SFP_DA_CU 957 * 1 SFP_SR 958 * 2 SFP_LR 959 * 3 SFP_DA_CORE0 - 82599-specific 960 * 4 SFP_DA_CORE1 - 82599-specific 961 * 5 SFP_SR/LR_CORE0 - 82599-specific 962 * 6 SFP_SR/LR_CORE1 - 82599-specific 963 * 7 SFP_act_lmt_DA_CORE0 - 82599-specific 964 * 8 SFP_act_lmt_DA_CORE1 - 82599-specific 965 * 9 SFP_1g_cu_CORE0 - 82599-specific 966 * 10 SFP_1g_cu_CORE1 - 82599-specific 967 */ 968 if (hw->mac.type == ixgbe_mac_82598EB) { 969 if (cable_tech & IXGBE_SFF_DA_PASSIVE_CABLE) 970 hw->phy.sfp_type = ixgbe_sfp_type_da_cu; 971 else if (comp_codes_10g & IXGBE_SFF_10GBASESR_CAPABLE) 972 hw->phy.sfp_type = ixgbe_sfp_type_sr; 973 else if (comp_codes_10g & IXGBE_SFF_10GBASELR_CAPABLE) 974 hw->phy.sfp_type = ixgbe_sfp_type_lr; 975 else if (comp_codes_10g & IXGBE_SFF_DA_BAD_HP_CABLE) 976 hw->phy.sfp_type = ixgbe_sfp_type_da_cu; 977 else 978 hw->phy.sfp_type = ixgbe_sfp_type_unknown; 979 } else if (hw->mac.type == ixgbe_mac_82599EB) { 980 if (cable_tech & IXGBE_SFF_DA_PASSIVE_CABLE) { 981 if (hw->bus.lan_id == 0) 982 hw->phy.sfp_type = 983 ixgbe_sfp_type_da_cu_core0; 984 else 985 hw->phy.sfp_type = 986 ixgbe_sfp_type_da_cu_core1; 987 } else if (cable_tech & IXGBE_SFF_DA_ACTIVE_CABLE) { 988 hw->phy.ops.read_i2c_eeprom( 989 hw, IXGBE_SFF_CABLE_SPEC_COMP, 990 &cable_spec); 991 if (cable_spec & 992 IXGBE_SFF_DA_SPEC_ACTIVE_LIMITING) { 993 if (hw->bus.lan_id == 0) 994 hw->phy.sfp_type = 995 ixgbe_sfp_type_da_act_lmt_core0; 996 else 997 hw->phy.sfp_type = 998 ixgbe_sfp_type_da_act_lmt_core1; 999 } else { 1000 hw->phy.sfp_type = 1001 ixgbe_sfp_type_unknown; 1002 } 1003 } else if (comp_codes_10g & 1004 (IXGBE_SFF_10GBASESR_CAPABLE | 1005 IXGBE_SFF_10GBASELR_CAPABLE)) { 1006 if (hw->bus.lan_id == 0) 1007 hw->phy.sfp_type = 1008 ixgbe_sfp_type_srlr_core0; 1009 else 1010 hw->phy.sfp_type = 1011 ixgbe_sfp_type_srlr_core1; 1012 } else if (comp_codes_1g & IXGBE_SFF_1GBASET_CAPABLE) { 1013 if (hw->bus.lan_id == 0) 1014 hw->phy.sfp_type = 1015 ixgbe_sfp_type_1g_cu_core0; 1016 else 1017 hw->phy.sfp_type = 1018 ixgbe_sfp_type_1g_cu_core1; 1019 } else { 1020 hw->phy.sfp_type = ixgbe_sfp_type_unknown; 1021 } 1022 } 1023 1024 if (hw->phy.sfp_type != stored_sfp_type) 1025 hw->phy.sfp_setup_needed = TRUE; 1026 1027 /* Determine if the SFP+ PHY is dual speed or not. */ 1028 hw->phy.multispeed_fiber = FALSE; 1029 if (((comp_codes_1g & IXGBE_SFF_1GBASESX_CAPABLE) && 1030 (comp_codes_10g & IXGBE_SFF_10GBASESR_CAPABLE)) || 1031 ((comp_codes_1g & IXGBE_SFF_1GBASELX_CAPABLE) && 1032 (comp_codes_10g & IXGBE_SFF_10GBASELR_CAPABLE))) 1033 hw->phy.multispeed_fiber = TRUE; 1034 1035 /* Determine PHY vendor */ 1036 if (hw->phy.type != ixgbe_phy_nl) { 1037 hw->phy.id = identifier; 1038 status = hw->phy.ops.read_i2c_eeprom(hw, 1039 IXGBE_SFF_VENDOR_OUI_BYTE0, 1040 &oui_bytes[0]); 1041 1042 if (status == IXGBE_ERR_SWFW_SYNC || 1043 status == IXGBE_ERR_I2C || 1044 status == IXGBE_ERR_SFP_NOT_PRESENT) 1045 goto err_read_i2c_eeprom; 1046 1047 status = hw->phy.ops.read_i2c_eeprom(hw, 1048 IXGBE_SFF_VENDOR_OUI_BYTE1, 1049 &oui_bytes[1]); 1050 1051 if (status == IXGBE_ERR_SWFW_SYNC || 1052 status == IXGBE_ERR_I2C || 1053 status == IXGBE_ERR_SFP_NOT_PRESENT) 1054 goto err_read_i2c_eeprom; 1055 1056 status = hw->phy.ops.read_i2c_eeprom(hw, 1057 IXGBE_SFF_VENDOR_OUI_BYTE2, 1058 &oui_bytes[2]); 1059 1060 if (status == IXGBE_ERR_SWFW_SYNC || 1061 status == IXGBE_ERR_I2C || 1062 status == IXGBE_ERR_SFP_NOT_PRESENT) 1063 goto err_read_i2c_eeprom; 1064 1065 vendor_oui = 1066 ((oui_bytes[0] << IXGBE_SFF_VENDOR_OUI_BYTE0_SHIFT) | 1067 (oui_bytes[1] << IXGBE_SFF_VENDOR_OUI_BYTE1_SHIFT) | 1068 (oui_bytes[2] << IXGBE_SFF_VENDOR_OUI_BYTE2_SHIFT)); 1069 1070 switch (vendor_oui) { 1071 case IXGBE_SFF_VENDOR_OUI_TYCO: 1072 if (cable_tech & IXGBE_SFF_DA_PASSIVE_CABLE) 1073 hw->phy.type = 1074 ixgbe_phy_sfp_passive_tyco; 1075 break; 1076 case IXGBE_SFF_VENDOR_OUI_FTL: 1077 if (cable_tech & IXGBE_SFF_DA_ACTIVE_CABLE) 1078 hw->phy.type = ixgbe_phy_sfp_ftl_active; 1079 else 1080 hw->phy.type = ixgbe_phy_sfp_ftl; 1081 break; 1082 case IXGBE_SFF_VENDOR_OUI_AVAGO: 1083 hw->phy.type = ixgbe_phy_sfp_avago; 1084 break; 1085 case IXGBE_SFF_VENDOR_OUI_INTEL: 1086 hw->phy.type = ixgbe_phy_sfp_intel; 1087 break; 1088 default: 1089 if (cable_tech & IXGBE_SFF_DA_PASSIVE_CABLE) 1090 hw->phy.type = 1091 ixgbe_phy_sfp_passive_unknown; 1092 else if (cable_tech & IXGBE_SFF_DA_ACTIVE_CABLE) 1093 hw->phy.type = 1094 ixgbe_phy_sfp_active_unknown; 1095 else 1096 hw->phy.type = ixgbe_phy_sfp_unknown; 1097 break; 1098 } 1099 } 1100 1101 /* Allow any DA cable vendor */ 1102 if (cable_tech & (IXGBE_SFF_DA_PASSIVE_CABLE | 1103 IXGBE_SFF_DA_ACTIVE_CABLE)) { 1104 status = IXGBE_SUCCESS; 1105 goto out; 1106 } 1107 1108 /* Verify supported 1G SFP modules */ 1109 if (comp_codes_10g == 0 && 1110 !(hw->phy.sfp_type == ixgbe_sfp_type_1g_cu_core1 || 1111 hw->phy.sfp_type == ixgbe_sfp_type_1g_cu_core0)) { 1112 hw->phy.type = ixgbe_phy_sfp_unsupported; 1113 status = IXGBE_ERR_SFP_NOT_SUPPORTED; 1114 goto out; 1115 } 1116 1117 /* Anything else 82598-based is supported */ 1118 if (hw->mac.type == ixgbe_mac_82598EB) { 1119 status = IXGBE_SUCCESS; 1120 goto out; 1121 } 1122 1123 /* unimplemented even in the intel driver */ 1124 /* ixgbe_get_device_caps(hw, &enforce_sfp); */ 1125 enforce_sfp = IXGBE_DEVICE_CAPS_ALLOW_ANY_SFP; 1126 if (!(enforce_sfp & IXGBE_DEVICE_CAPS_ALLOW_ANY_SFP) && 1127 !((hw->phy.sfp_type == ixgbe_sfp_type_1g_cu_core0) || 1128 (hw->phy.sfp_type == ixgbe_sfp_type_1g_cu_core1))) { 1129 /* Make sure we're a supported PHY type */ 1130 if (hw->phy.type == ixgbe_phy_sfp_intel) { 1131 status = IXGBE_SUCCESS; 1132 } else { 1133 DEBUGOUT("SFP+ module not supported\n"); 1134 hw->phy.type = ixgbe_phy_sfp_unsupported; 1135 status = IXGBE_ERR_SFP_NOT_SUPPORTED; 1136 } 1137 } else { 1138 DEBUGOUT("SFP+ module type ignored\n"); 1139 status = IXGBE_SUCCESS; 1140 } 1141 } 1142 1143 out: 1144 return status; 1145 1146 err_read_i2c_eeprom: 1147 hw->phy.sfp_type = ixgbe_sfp_type_not_present; 1148 if (hw->phy.type != ixgbe_phy_nl) { 1149 hw->phy.id = 0; 1150 hw->phy.type = ixgbe_phy_unknown; 1151 } 1152 return IXGBE_ERR_SFP_NOT_PRESENT; 1153 } 1154 1155 /** 1156 * ixgbe_get_sfp_init_sequence_offsets - Provides offset of PHY init sequence 1157 * @hw: pointer to hardware structure 1158 * @list_offset: offset to the SFP ID list 1159 * @data_offset: offset to the SFP data block 1160 * 1161 * Checks the MAC's EEPROM to see if it supports a given SFP+ module type, if 1162 * so it returns the offsets to the phy init sequence block. 1163 **/ 1164 int32_t ixgbe_get_sfp_init_sequence_offsets(struct ixgbe_hw *hw, 1165 uint16_t *list_offset, 1166 uint16_t *data_offset) 1167 { 1168 uint16_t sfp_id; 1169 uint16_t sfp_type = hw->phy.sfp_type; 1170 1171 if (hw->phy.sfp_type == ixgbe_sfp_type_unknown) 1172 return IXGBE_ERR_SFP_NOT_SUPPORTED; 1173 1174 if (hw->phy.sfp_type == ixgbe_sfp_type_not_present) 1175 return IXGBE_ERR_SFP_NOT_PRESENT; 1176 1177 if ((hw->device_id == IXGBE_DEV_ID_82598_SR_DUAL_PORT_EM) && 1178 (hw->phy.sfp_type == ixgbe_sfp_type_da_cu)) 1179 return IXGBE_ERR_SFP_NOT_SUPPORTED; 1180 1181 /* 1182 * Limiting active cables and 1G Phys must be initialized as 1183 * SR modules 1184 */ 1185 if (sfp_type == ixgbe_sfp_type_da_act_lmt_core0 || 1186 sfp_type == ixgbe_sfp_type_1g_cu_core0) 1187 sfp_type = ixgbe_sfp_type_srlr_core0; 1188 else if (sfp_type == ixgbe_sfp_type_da_act_lmt_core1 || 1189 sfp_type == ixgbe_sfp_type_1g_cu_core1) 1190 sfp_type = ixgbe_sfp_type_srlr_core1; 1191 1192 /* Read offset to PHY init contents */ 1193 hw->eeprom.ops.read(hw, IXGBE_PHY_INIT_OFFSET_NL, list_offset); 1194 1195 if ((!*list_offset) || (*list_offset == 0xFFFF)) 1196 return IXGBE_ERR_SFP_NO_INIT_SEQ_PRESENT; 1197 1198 /* Shift offset to first ID word */ 1199 (*list_offset)++; 1200 1201 /* 1202 * Find the matching SFP ID in the EEPROM 1203 * and program the init sequence 1204 */ 1205 hw->eeprom.ops.read(hw, *list_offset, &sfp_id); 1206 1207 while (sfp_id != IXGBE_PHY_INIT_END_NL) { 1208 if (sfp_id == sfp_type) { 1209 (*list_offset)++; 1210 hw->eeprom.ops.read(hw, *list_offset, data_offset); 1211 if ((!*data_offset) || (*data_offset == 0xFFFF)) { 1212 DEBUGOUT("SFP+ module not supported\n"); 1213 return IXGBE_ERR_SFP_NOT_SUPPORTED; 1214 } else { 1215 break; 1216 } 1217 } else { 1218 (*list_offset) += 2; 1219 if (hw->eeprom.ops.read(hw, *list_offset, &sfp_id)) 1220 return IXGBE_ERR_PHY; 1221 } 1222 } 1223 1224 /* 1225 * the 82598EB SFP+ card offically supports only direct attached cables 1226 * but works fine with optical SFP+ modules as well. Even though the 1227 * EEPROM has no matching ID for them. So just accept the module. 1228 */ 1229 if (sfp_id == IXGBE_PHY_INIT_END_NL && 1230 hw->mac.type == ixgbe_mac_82598EB) { 1231 /* refetch offset for the first phy entry */ 1232 hw->eeprom.ops.read(hw, IXGBE_PHY_INIT_OFFSET_NL, list_offset); 1233 (*list_offset) += 2; 1234 hw->eeprom.ops.read(hw, *list_offset, data_offset); 1235 } else if (sfp_id == IXGBE_PHY_INIT_END_NL) { 1236 DEBUGOUT("No matching SFP+ module found\n"); 1237 return IXGBE_ERR_SFP_NOT_SUPPORTED; 1238 } 1239 return IXGBE_SUCCESS; 1240 } 1241 1242 /** 1243 * ixgbe_read_i2c_eeprom_generic - Reads 8 bit EEPROM word over I2C interface 1244 * @hw: pointer to hardware structure 1245 * @byte_offset: EEPROM byte offset to read 1246 * @eeprom_data: value read 1247 * 1248 * Performs byte read operation to SFP module's EEPROM over I2C interface. 1249 **/ 1250 int32_t ixgbe_read_i2c_eeprom_generic(struct ixgbe_hw *hw, uint8_t byte_offset, 1251 uint8_t *eeprom_data) 1252 { 1253 return hw->phy.ops.read_i2c_byte(hw, byte_offset, 1254 IXGBE_I2C_EEPROM_DEV_ADDR, 1255 eeprom_data); 1256 } 1257 1258 /** 1259 * ixgbe_write_i2c_eeprom_generic - Writes 8 bit EEPROM word over I2C interface 1260 * @hw: pointer to hardware structure 1261 * @byte_offset: EEPROM byte offset to write 1262 * @eeprom_data: value to write 1263 * 1264 * Performs byte write operation to SFP module's EEPROM over I2C interface. 1265 **/ 1266 int32_t ixgbe_write_i2c_eeprom_generic(struct ixgbe_hw *hw, uint8_t byte_offset, 1267 uint8_t eeprom_data) 1268 { 1269 return hw->phy.ops.write_i2c_byte(hw, byte_offset, 1270 IXGBE_I2C_EEPROM_DEV_ADDR, 1271 eeprom_data); 1272 } 1273 1274 /** 1275 * ixgbe_read_i2c_byte_generic - Reads 8 bit word over I2C 1276 * @hw: pointer to hardware structure 1277 * @byte_offset: byte offset to read 1278 * @data: value read 1279 * 1280 * Performs byte read operation to SFP module's EEPROM over I2C interface at 1281 * a specified deivce address. 1282 **/ 1283 int32_t ixgbe_read_i2c_byte_generic(struct ixgbe_hw *hw, uint8_t byte_offset, 1284 uint8_t dev_addr, uint8_t *data) 1285 { 1286 int32_t status = IXGBE_SUCCESS; 1287 uint32_t max_retry = 10; 1288 uint32_t retry = 0; 1289 uint16_t swfw_mask = 0; 1290 int nack = 1; 1291 1292 if (IXGBE_READ_REG(hw, IXGBE_STATUS) & IXGBE_STATUS_LAN_ID_1) 1293 swfw_mask = IXGBE_GSSR_PHY1_SM; 1294 else 1295 swfw_mask = IXGBE_GSSR_PHY0_SM; 1296 1297 do { 1298 if (ixgbe_acquire_swfw_sync(hw, swfw_mask) != IXGBE_SUCCESS) { 1299 status = IXGBE_ERR_SWFW_SYNC; 1300 goto read_byte_out; 1301 } 1302 1303 ixgbe_i2c_start(hw); 1304 1305 /* Device Address and write indication */ 1306 status = ixgbe_clock_out_i2c_byte(hw, dev_addr); 1307 if (status != IXGBE_SUCCESS) 1308 goto fail; 1309 1310 status = ixgbe_get_i2c_ack(hw); 1311 if (status != IXGBE_SUCCESS) 1312 goto fail; 1313 1314 status = ixgbe_clock_out_i2c_byte(hw, byte_offset); 1315 if (status != IXGBE_SUCCESS) 1316 goto fail; 1317 1318 status = ixgbe_get_i2c_ack(hw); 1319 if (status != IXGBE_SUCCESS) 1320 goto fail; 1321 1322 ixgbe_i2c_start(hw); 1323 1324 /* Device Address and read indication */ 1325 status = ixgbe_clock_out_i2c_byte(hw, (dev_addr | 0x1)); 1326 if (status != IXGBE_SUCCESS) 1327 goto fail; 1328 1329 status = ixgbe_get_i2c_ack(hw); 1330 if (status != IXGBE_SUCCESS) 1331 goto fail; 1332 1333 status = ixgbe_clock_in_i2c_byte(hw, data); 1334 if (status != IXGBE_SUCCESS) 1335 goto fail; 1336 1337 status = ixgbe_clock_out_i2c_bit(hw, nack); 1338 if (status != IXGBE_SUCCESS) 1339 goto fail; 1340 1341 ixgbe_i2c_stop(hw); 1342 break; 1343 1344 fail: 1345 ixgbe_release_swfw_sync(hw, swfw_mask); 1346 msec_delay(100); 1347 ixgbe_i2c_bus_clear(hw); 1348 retry++; 1349 if (retry < max_retry) 1350 DEBUGOUT("I2C byte read error - Retrying.\n"); 1351 else 1352 DEBUGOUT("I2C byte read error.\n"); 1353 1354 } while (retry < max_retry); 1355 1356 ixgbe_release_swfw_sync(hw, swfw_mask); 1357 1358 read_byte_out: 1359 return status; 1360 } 1361 1362 /** 1363 * ixgbe_write_i2c_byte_generic - Writes 8 bit word over I2C 1364 * @hw: pointer to hardware structure 1365 * @byte_offset: byte offset to write 1366 * @data: value to write 1367 * 1368 * Performs byte write operation to SFP module's EEPROM over I2C interface at 1369 * a specified device address. 1370 **/ 1371 int32_t ixgbe_write_i2c_byte_generic(struct ixgbe_hw *hw, uint8_t byte_offset, 1372 uint8_t dev_addr, uint8_t data) 1373 { 1374 int32_t status = IXGBE_SUCCESS; 1375 uint32_t max_retry = 1; 1376 uint32_t retry = 0; 1377 uint16_t swfw_mask = 0; 1378 1379 if (IXGBE_READ_REG(hw, IXGBE_STATUS) & IXGBE_STATUS_LAN_ID_1) 1380 swfw_mask = IXGBE_GSSR_PHY1_SM; 1381 else 1382 swfw_mask = IXGBE_GSSR_PHY0_SM; 1383 1384 if (ixgbe_acquire_swfw_sync(hw, swfw_mask) != IXGBE_SUCCESS) { 1385 status = IXGBE_ERR_SWFW_SYNC; 1386 goto write_byte_out; 1387 } 1388 1389 do { 1390 ixgbe_i2c_start(hw); 1391 1392 status = ixgbe_clock_out_i2c_byte(hw, dev_addr); 1393 if (status != IXGBE_SUCCESS) 1394 goto fail; 1395 1396 status = ixgbe_get_i2c_ack(hw); 1397 if (status != IXGBE_SUCCESS) 1398 goto fail; 1399 1400 status = ixgbe_clock_out_i2c_byte(hw, byte_offset); 1401 if (status != IXGBE_SUCCESS) 1402 goto fail; 1403 1404 status = ixgbe_get_i2c_ack(hw); 1405 if (status != IXGBE_SUCCESS) 1406 goto fail; 1407 1408 status = ixgbe_clock_out_i2c_byte(hw, data); 1409 if (status != IXGBE_SUCCESS) 1410 goto fail; 1411 1412 status = ixgbe_get_i2c_ack(hw); 1413 if (status != IXGBE_SUCCESS) 1414 goto fail; 1415 1416 ixgbe_i2c_stop(hw); 1417 break; 1418 1419 fail: 1420 ixgbe_i2c_bus_clear(hw); 1421 retry++; 1422 if (retry < max_retry) 1423 DEBUGOUT("I2C byte write error - Retrying.\n"); 1424 else 1425 DEBUGOUT("I2C byte write error.\n"); 1426 } while (retry < max_retry); 1427 1428 ixgbe_release_swfw_sync(hw, swfw_mask); 1429 1430 write_byte_out: 1431 return status; 1432 } 1433 1434 /** 1435 * ixgbe_i2c_start - Sets I2C start condition 1436 * @hw: pointer to hardware structure 1437 * 1438 * Sets I2C start condition (High -> Low on SDA while SCL is High) 1439 **/ 1440 void ixgbe_i2c_start(struct ixgbe_hw *hw) 1441 { 1442 uint32_t i2cctl = IXGBE_READ_REG(hw, IXGBE_I2CCTL); 1443 1444 /* Start condition must begin with data and clock high */ 1445 ixgbe_set_i2c_data(hw, &i2cctl, 1); 1446 ixgbe_raise_i2c_clk(hw, &i2cctl); 1447 1448 /* Setup time for start condition (4.7us) */ 1449 usec_delay(IXGBE_I2C_T_SU_STA); 1450 1451 ixgbe_set_i2c_data(hw, &i2cctl, 0); 1452 1453 /* Hold time for start condition (4us) */ 1454 usec_delay(IXGBE_I2C_T_HD_STA); 1455 1456 ixgbe_lower_i2c_clk(hw, &i2cctl); 1457 1458 /* Minimum low period of clock is 4.7 us */ 1459 usec_delay(IXGBE_I2C_T_LOW); 1460 1461 } 1462 1463 /** 1464 * ixgbe_i2c_stop - Sets I2C stop condition 1465 * @hw: pointer to hardware structure 1466 * 1467 * Sets I2C stop condition (Low -> High on SDA while SCL is High) 1468 **/ 1469 void ixgbe_i2c_stop(struct ixgbe_hw *hw) 1470 { 1471 uint32_t i2cctl = IXGBE_READ_REG(hw, IXGBE_I2CCTL); 1472 1473 /* Stop condition must begin with data low and clock high */ 1474 ixgbe_set_i2c_data(hw, &i2cctl, 0); 1475 ixgbe_raise_i2c_clk(hw, &i2cctl); 1476 1477 /* Setup time for stop condition (4us) */ 1478 usec_delay(IXGBE_I2C_T_SU_STO); 1479 1480 ixgbe_set_i2c_data(hw, &i2cctl, 1); 1481 1482 /* bus free time between stop and start (4.7us)*/ 1483 usec_delay(IXGBE_I2C_T_BUF); 1484 } 1485 1486 /** 1487 * ixgbe_clock_in_i2c_byte - Clocks in one byte via I2C 1488 * @hw: pointer to hardware structure 1489 * @data: data byte to clock in 1490 * 1491 * Clocks in one byte data via I2C data/clock 1492 **/ 1493 int32_t ixgbe_clock_in_i2c_byte(struct ixgbe_hw *hw, uint8_t *data) 1494 { 1495 int32_t status = IXGBE_SUCCESS; 1496 int32_t i; 1497 int bit = 0; 1498 1499 for (i = 7; i >= 0; i--) { 1500 status = ixgbe_clock_in_i2c_bit(hw, &bit); 1501 *data |= bit << i; 1502 1503 if (status != IXGBE_SUCCESS) 1504 break; 1505 } 1506 1507 return status; 1508 } 1509 1510 /** 1511 * ixgbe_clock_out_i2c_byte - Clocks out one byte via I2C 1512 * @hw: pointer to hardware structure 1513 * @data: data byte clocked out 1514 * 1515 * Clocks out one byte data via I2C data/clock 1516 **/ 1517 int32_t ixgbe_clock_out_i2c_byte(struct ixgbe_hw *hw, uint8_t data) 1518 { 1519 int32_t status = IXGBE_SUCCESS; 1520 int32_t i; 1521 uint32_t i2cctl; 1522 int bit = 0; 1523 1524 for (i = 7; i >= 0; i--) { 1525 bit = (data >> i) & 0x1; 1526 status = ixgbe_clock_out_i2c_bit(hw, bit); 1527 1528 if (status != IXGBE_SUCCESS) 1529 break; 1530 } 1531 1532 /* Release SDA line (set high) */ 1533 i2cctl = IXGBE_READ_REG(hw, IXGBE_I2CCTL); 1534 i2cctl |= IXGBE_I2C_DATA_OUT; 1535 IXGBE_WRITE_REG(hw, IXGBE_I2CCTL, i2cctl); 1536 1537 return status; 1538 } 1539 1540 /** 1541 * ixgbe_get_i2c_ack - Polls for I2C ACK 1542 * @hw: pointer to hardware structure 1543 * 1544 * Clocks in/out one bit via I2C data/clock 1545 **/ 1546 int32_t ixgbe_get_i2c_ack(struct ixgbe_hw *hw) 1547 { 1548 int32_t status; 1549 uint32_t i = 0; 1550 uint32_t i2cctl = IXGBE_READ_REG(hw, IXGBE_I2CCTL); 1551 uint32_t timeout = 10; 1552 int ack = 1; 1553 1554 status = ixgbe_raise_i2c_clk(hw, &i2cctl); 1555 1556 if (status != IXGBE_SUCCESS) 1557 goto out; 1558 1559 /* Minimum high period of clock is 4us */ 1560 usec_delay(IXGBE_I2C_T_HIGH); 1561 1562 /* Poll for ACK. Note that ACK in I2C spec is 1563 * transition from 1 to 0 */ 1564 for (i = 0; i < timeout; i++) { 1565 i2cctl = IXGBE_READ_REG(hw, IXGBE_I2CCTL); 1566 ack = ixgbe_get_i2c_data(&i2cctl); 1567 1568 usec_delay(1); 1569 if (ack == 0) 1570 break; 1571 } 1572 1573 if (ack == 1) { 1574 DEBUGOUT("I2C ack was not received.\n"); 1575 status = IXGBE_ERR_I2C; 1576 } 1577 1578 ixgbe_lower_i2c_clk(hw, &i2cctl); 1579 1580 /* Minimum low period of clock is 4.7 us */ 1581 usec_delay(IXGBE_I2C_T_LOW); 1582 1583 out: 1584 return status; 1585 } 1586 1587 /** 1588 * ixgbe_clock_in_i2c_bit - Clocks in one bit via I2C data/clock 1589 * @hw: pointer to hardware structure 1590 * @data: read data value 1591 * 1592 * Clocks in one bit via I2C data/clock 1593 **/ 1594 int32_t ixgbe_clock_in_i2c_bit(struct ixgbe_hw *hw, int *data) 1595 { 1596 int32_t status; 1597 uint32_t i2cctl = IXGBE_READ_REG(hw, IXGBE_I2CCTL); 1598 1599 status = ixgbe_raise_i2c_clk(hw, &i2cctl); 1600 1601 /* Minimum high period of clock is 4us */ 1602 usec_delay(IXGBE_I2C_T_HIGH); 1603 1604 i2cctl = IXGBE_READ_REG(hw, IXGBE_I2CCTL); 1605 *data = ixgbe_get_i2c_data(&i2cctl); 1606 1607 ixgbe_lower_i2c_clk(hw, &i2cctl); 1608 1609 /* Minimum low period of clock is 4.7 us */ 1610 usec_delay(IXGBE_I2C_T_LOW); 1611 1612 return status; 1613 } 1614 1615 /** 1616 * ixgbe_clock_out_i2c_bit - Clocks in/out one bit via I2C data/clock 1617 * @hw: pointer to hardware structure 1618 * @data: data value to write 1619 * 1620 * Clocks out one bit via I2C data/clock 1621 **/ 1622 int32_t ixgbe_clock_out_i2c_bit(struct ixgbe_hw *hw, int data) 1623 { 1624 int32_t status; 1625 uint32_t i2cctl = IXGBE_READ_REG(hw, IXGBE_I2CCTL); 1626 1627 status = ixgbe_set_i2c_data(hw, &i2cctl, data); 1628 if (status == IXGBE_SUCCESS) { 1629 status = ixgbe_raise_i2c_clk(hw, &i2cctl); 1630 1631 /* Minimum high period of clock is 4us */ 1632 usec_delay(IXGBE_I2C_T_HIGH); 1633 1634 ixgbe_lower_i2c_clk(hw, &i2cctl); 1635 1636 /* Minimum low period of clock is 4.7 us. 1637 * This also takes care of the data hold time. 1638 */ 1639 usec_delay(IXGBE_I2C_T_LOW); 1640 } else { 1641 status = IXGBE_ERR_I2C; 1642 DEBUGOUT1("I2C data was not set to %X\n", data); 1643 } 1644 1645 return status; 1646 } 1647 /** 1648 * ixgbe_raise_i2c_clk - Raises the I2C SCL clock 1649 * @hw: pointer to hardware structure 1650 * @i2cctl: Current value of I2CCTL register 1651 * 1652 * Raises the I2C clock line '0'->'1' 1653 **/ 1654 int32_t ixgbe_raise_i2c_clk(struct ixgbe_hw *hw, uint32_t *i2cctl) 1655 { 1656 int32_t status = IXGBE_SUCCESS; 1657 1658 *i2cctl |= IXGBE_I2C_CLK_OUT; 1659 1660 IXGBE_WRITE_REG(hw, IXGBE_I2CCTL, *i2cctl); 1661 1662 /* SCL rise time (1000ns) */ 1663 usec_delay(IXGBE_I2C_T_RISE); 1664 1665 return status; 1666 } 1667 1668 /** 1669 * ixgbe_lower_i2c_clk - Lowers the I2C SCL clock 1670 * @hw: pointer to hardware structure 1671 * @i2cctl: Current value of I2CCTL register 1672 * 1673 * Lowers the I2C clock line '1'->'0' 1674 **/ 1675 void ixgbe_lower_i2c_clk(struct ixgbe_hw *hw, uint32_t *i2cctl) 1676 { 1677 1678 *i2cctl &= ~IXGBE_I2C_CLK_OUT; 1679 1680 IXGBE_WRITE_REG(hw, IXGBE_I2CCTL, *i2cctl); 1681 1682 /* SCL fall time (300ns) */ 1683 usec_delay(IXGBE_I2C_T_FALL); 1684 } 1685 1686 /** 1687 * ixgbe_set_i2c_data - Sets the I2C data bit 1688 * @hw: pointer to hardware structure 1689 * @i2cctl: Current value of I2CCTL register 1690 * @data: I2C data value (0 or 1) to set 1691 * 1692 * Sets the I2C data bit 1693 **/ 1694 int32_t ixgbe_set_i2c_data(struct ixgbe_hw *hw, uint32_t *i2cctl, int data) 1695 { 1696 int32_t status = IXGBE_SUCCESS; 1697 1698 if (data) 1699 *i2cctl |= IXGBE_I2C_DATA_OUT; 1700 else 1701 *i2cctl &= ~IXGBE_I2C_DATA_OUT; 1702 1703 IXGBE_WRITE_REG(hw, IXGBE_I2CCTL, *i2cctl); 1704 1705 /* Data rise/fall (1000ns/300ns) and set-up time (250ns) */ 1706 usec_delay(IXGBE_I2C_T_RISE + IXGBE_I2C_T_FALL + IXGBE_I2C_T_SU_DATA); 1707 1708 /* Verify data was set correctly */ 1709 *i2cctl = IXGBE_READ_REG(hw, IXGBE_I2CCTL); 1710 if (data != ixgbe_get_i2c_data(i2cctl)) { 1711 status = IXGBE_ERR_I2C; 1712 DEBUGOUT1("Error - I2C data was not set to %X.\n", data); 1713 } 1714 1715 return status; 1716 } 1717 1718 /** 1719 * ixgbe_get_i2c_data - Reads the I2C SDA data bit 1720 * @hw: pointer to hardware structure 1721 * @i2cctl: Current value of I2CCTL register 1722 * 1723 * Returns the I2C data bit value 1724 **/ 1725 int ixgbe_get_i2c_data(uint32_t *i2cctl) 1726 { 1727 int data; 1728 1729 if (*i2cctl & IXGBE_I2C_DATA_IN) 1730 data = 1; 1731 else 1732 data = 0; 1733 1734 return data; 1735 } 1736 1737 /** 1738 * ixgbe_i2c_bus_clear - Clears the I2C bus 1739 * @hw: pointer to hardware structure 1740 * 1741 * Clears the I2C bus by sending nine clock pulses. 1742 * Used when data line is stuck low. 1743 **/ 1744 void ixgbe_i2c_bus_clear(struct ixgbe_hw *hw) 1745 { 1746 uint32_t i2cctl = IXGBE_READ_REG(hw, IXGBE_I2CCTL); 1747 uint32_t i; 1748 1749 ixgbe_i2c_start(hw); 1750 1751 ixgbe_set_i2c_data(hw, &i2cctl, 1); 1752 1753 for (i = 0; i < 9; i++) { 1754 ixgbe_raise_i2c_clk(hw, &i2cctl); 1755 1756 /* Min high period of clock is 4us */ 1757 usec_delay(IXGBE_I2C_T_HIGH); 1758 1759 ixgbe_lower_i2c_clk(hw, &i2cctl); 1760 1761 /* Min low period of clock is 4.7us*/ 1762 usec_delay(IXGBE_I2C_T_LOW); 1763 } 1764 1765 ixgbe_i2c_start(hw); 1766 1767 /* Put the i2c bus back to default state */ 1768 ixgbe_i2c_stop(hw); 1769 } 1770 1771 /** 1772 * ixgbe_tn_check_overtemp - Checks if an overtemp occured. 1773 * @hw: pointer to hardware structure 1774 * 1775 * Checks if the LASI temp alarm status was triggered due to overtemp 1776 **/ 1777 int32_t ixgbe_tn_check_overtemp(struct ixgbe_hw *hw) 1778 { 1779 int32_t status = IXGBE_SUCCESS; 1780 uint16_t phy_data = 0; 1781 1782 if (hw->device_id != IXGBE_DEV_ID_82599_T3_LOM) 1783 goto out; 1784 1785 /* Check that the LASI temp alarm status was triggered */ 1786 hw->phy.ops.read_reg(hw, IXGBE_TN_LASI_STATUS_REG, 1787 IXGBE_MDIO_PMA_PMD_DEV_TYPE, &phy_data); 1788 1789 if (!(phy_data & IXGBE_TN_LASI_STATUS_TEMP_ALARM)) 1790 goto out; 1791 1792 status = IXGBE_ERR_OVERTEMP; 1793 out: 1794 return status; 1795 } 1796