1 /* $OpenBSD: ixgbe_phy.c,v 1.11 2013/08/05 19:58:06 mikeb Exp $ */ 2 3 /****************************************************************************** 4 5 Copyright (c) 2001-2013, Intel Corporation 6 All rights reserved. 7 8 Redistribution and use in source and binary forms, with or without 9 modification, are permitted provided that the following conditions are met: 10 11 1. Redistributions of source code must retain the above copyright notice, 12 this list of conditions and the following disclaimer. 13 14 2. Redistributions in binary form must reproduce the above copyright 15 notice, this list of conditions and the following disclaimer in the 16 documentation and/or other materials provided with the distribution. 17 18 3. Neither the name of the Intel Corporation nor the names of its 19 contributors may be used to endorse or promote products derived from 20 this software without specific prior written permission. 21 22 THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS" 23 AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE 24 IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE 25 ARE DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT OWNER OR CONTRIBUTORS BE 26 LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR 27 CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF 28 SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS 29 INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN 30 CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) 31 ARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE 32 POSSIBILITY OF SUCH DAMAGE. 33 34 ******************************************************************************/ 35 /* FreeBSD: src/sys/dev/ixgbe/ixgbe_phy.c 251964 Jun 18 21:28:19 2013 UTC */ 36 37 #include <dev/pci/ixgbe.h> 38 39 void ixgbe_i2c_start(struct ixgbe_hw *hw); 40 void ixgbe_i2c_stop(struct ixgbe_hw *hw); 41 int32_t ixgbe_clock_in_i2c_byte(struct ixgbe_hw *hw, uint8_t *data); 42 int32_t ixgbe_clock_out_i2c_byte(struct ixgbe_hw *hw, uint8_t data); 43 int32_t ixgbe_get_i2c_ack(struct ixgbe_hw *hw); 44 int32_t ixgbe_clock_in_i2c_bit(struct ixgbe_hw *hw, int *data); 45 int32_t ixgbe_clock_out_i2c_bit(struct ixgbe_hw *hw, int data); 46 void ixgbe_raise_i2c_clk(struct ixgbe_hw *hw, uint32_t *i2cctl); 47 void ixgbe_lower_i2c_clk(struct ixgbe_hw *hw, uint32_t *i2cctl); 48 int32_t ixgbe_set_i2c_data(struct ixgbe_hw *hw, uint32_t *i2cctl, int data); 49 int ixgbe_get_i2c_data(uint32_t *i2cctl); 50 void ixgbe_i2c_bus_clear(struct ixgbe_hw *hw); 51 52 /** 53 * ixgbe_init_phy_ops_generic - Inits PHY function ptrs 54 * @hw: pointer to the hardware structure 55 * 56 * Initialize the function pointers. 57 **/ 58 int32_t ixgbe_init_phy_ops_generic(struct ixgbe_hw *hw) 59 { 60 struct ixgbe_phy_info *phy = &hw->phy; 61 62 DEBUGFUNC("ixgbe_init_phy_ops_generic"); 63 64 /* PHY */ 65 phy->ops.identify = &ixgbe_identify_phy_generic; 66 phy->ops.reset = &ixgbe_reset_phy_generic; 67 phy->ops.read_reg = &ixgbe_read_phy_reg_generic; 68 phy->ops.write_reg = &ixgbe_write_phy_reg_generic; 69 phy->ops.read_reg_mdi = &ixgbe_read_phy_reg_mdi; 70 phy->ops.write_reg_mdi = &ixgbe_write_phy_reg_mdi; 71 phy->ops.setup_link = &ixgbe_setup_phy_link_generic; 72 phy->ops.setup_link_speed = &ixgbe_setup_phy_link_speed_generic; 73 phy->ops.check_link = NULL; 74 phy->ops.get_firmware_version = ixgbe_get_phy_firmware_version_generic; 75 phy->ops.read_i2c_byte = &ixgbe_read_i2c_byte_generic; 76 phy->ops.write_i2c_byte = &ixgbe_write_i2c_byte_generic; 77 phy->ops.read_i2c_eeprom = &ixgbe_read_i2c_eeprom_generic; 78 phy->ops.write_i2c_eeprom = &ixgbe_write_i2c_eeprom_generic; 79 phy->ops.i2c_bus_clear = &ixgbe_i2c_bus_clear; 80 phy->ops.identify_sfp = &ixgbe_identify_module_generic; 81 phy->sfp_type = ixgbe_sfp_type_unknown; 82 phy->ops.check_overtemp = &ixgbe_tn_check_overtemp; 83 return IXGBE_SUCCESS; 84 } 85 86 /** 87 * ixgbe_identify_phy_generic - Get physical layer module 88 * @hw: pointer to hardware structure 89 * 90 * Determines the physical layer module found on the current adapter. 91 **/ 92 int32_t ixgbe_identify_phy_generic(struct ixgbe_hw *hw) 93 { 94 int32_t status = IXGBE_ERR_PHY_ADDR_INVALID; 95 uint32_t phy_addr; 96 uint16_t ext_ability = 0; 97 98 DEBUGFUNC("ixgbe_identify_phy_generic"); 99 100 if (hw->phy.type == ixgbe_phy_unknown) { 101 for (phy_addr = 0; phy_addr < IXGBE_MAX_PHY_ADDR; phy_addr++) { 102 if (ixgbe_validate_phy_addr(hw, phy_addr)) { 103 hw->phy.addr = phy_addr; 104 ixgbe_get_phy_id(hw); 105 hw->phy.type = 106 ixgbe_get_phy_type_from_id(hw->phy.id); 107 108 if (hw->phy.type == ixgbe_phy_unknown) { 109 hw->phy.ops.read_reg(hw, 110 IXGBE_MDIO_PHY_EXT_ABILITY, 111 IXGBE_MDIO_PMA_PMD_DEV_TYPE, 112 &ext_ability); 113 if (ext_ability & 114 (IXGBE_MDIO_PHY_10GBASET_ABILITY | 115 IXGBE_MDIO_PHY_1000BASET_ABILITY)) 116 hw->phy.type = 117 ixgbe_phy_cu_unknown; 118 else 119 hw->phy.type = 120 ixgbe_phy_generic; 121 } 122 123 status = IXGBE_SUCCESS; 124 break; 125 } 126 } 127 /* clear value if nothing found */ 128 if (status != IXGBE_SUCCESS) { 129 hw->phy.addr = 0; 130 ERROR_REPORT1(IXGBE_ERROR_SOFTWARE, 131 "Could not identify valid PHY address"); 132 } 133 } else { 134 status = IXGBE_SUCCESS; 135 } 136 137 return status; 138 } 139 140 /** 141 * ixgbe_validate_phy_addr - Determines phy address is valid 142 * @hw: pointer to hardware structure 143 * 144 **/ 145 bool ixgbe_validate_phy_addr(struct ixgbe_hw *hw, uint32_t phy_addr) 146 { 147 uint16_t phy_id = 0; 148 bool valid = FALSE; 149 150 DEBUGFUNC("ixgbe_validate_phy_addr"); 151 152 hw->phy.addr = phy_addr; 153 hw->phy.ops.read_reg(hw, IXGBE_MDIO_PHY_ID_HIGH, 154 IXGBE_MDIO_PMA_PMD_DEV_TYPE, &phy_id); 155 156 if (phy_id != 0xFFFF && phy_id != 0x0) 157 valid = TRUE; 158 159 return valid; 160 } 161 162 /** 163 * ixgbe_get_phy_id - Get the phy type 164 * @hw: pointer to hardware structure 165 * 166 **/ 167 int32_t ixgbe_get_phy_id(struct ixgbe_hw *hw) 168 { 169 uint32_t status; 170 uint16_t phy_id_high = 0; 171 uint16_t phy_id_low = 0; 172 173 DEBUGFUNC("ixgbe_get_phy_id"); 174 175 status = hw->phy.ops.read_reg(hw, IXGBE_MDIO_PHY_ID_HIGH, 176 IXGBE_MDIO_PMA_PMD_DEV_TYPE, 177 &phy_id_high); 178 179 if (status == IXGBE_SUCCESS) { 180 hw->phy.id = (uint32_t)(phy_id_high << 16); 181 status = hw->phy.ops.read_reg(hw, IXGBE_MDIO_PHY_ID_LOW, 182 IXGBE_MDIO_PMA_PMD_DEV_TYPE, 183 &phy_id_low); 184 hw->phy.id |= (uint32_t)(phy_id_low & IXGBE_PHY_REVISION_MASK); 185 hw->phy.revision = (uint32_t)(phy_id_low & ~IXGBE_PHY_REVISION_MASK); 186 } 187 return status; 188 } 189 190 /** 191 * ixgbe_get_phy_type_from_id - Get the phy type 192 * @hw: pointer to hardware structure 193 * 194 **/ 195 enum ixgbe_phy_type ixgbe_get_phy_type_from_id(uint32_t phy_id) 196 { 197 enum ixgbe_phy_type phy_type; 198 199 DEBUGFUNC("ixgbe_get_phy_type_from_id"); 200 201 switch (phy_id) { 202 case TN1010_PHY_ID: 203 phy_type = ixgbe_phy_tn; 204 break; 205 case X540_PHY_ID: 206 phy_type = ixgbe_phy_aq; 207 break; 208 case QT2022_PHY_ID: 209 phy_type = ixgbe_phy_qt; 210 break; 211 case ATH_PHY_ID: 212 phy_type = ixgbe_phy_nl; 213 break; 214 default: 215 phy_type = ixgbe_phy_unknown; 216 break; 217 } 218 219 DEBUGOUT1("phy type found is %d\n", phy_type); 220 return phy_type; 221 } 222 223 /** 224 * ixgbe_reset_phy_generic - Performs a PHY reset 225 * @hw: pointer to hardware structure 226 **/ 227 int32_t ixgbe_reset_phy_generic(struct ixgbe_hw *hw) 228 { 229 uint32_t i; 230 uint16_t ctrl = 0; 231 int32_t status = IXGBE_SUCCESS; 232 233 DEBUGFUNC("ixgbe_reset_phy_generic"); 234 235 if (hw->phy.type == ixgbe_phy_unknown) 236 status = ixgbe_identify_phy_generic(hw); 237 238 if (status != IXGBE_SUCCESS || hw->phy.type == ixgbe_phy_none) 239 goto out; 240 241 /* Don't reset PHY if it's shut down due to overtemp. */ 242 if (!hw->phy.reset_if_overtemp && 243 (IXGBE_ERR_OVERTEMP == hw->phy.ops.check_overtemp(hw))) 244 goto out; 245 246 /* 247 * Perform soft PHY reset to the PHY_XS. 248 * This will cause a soft reset to the PHY 249 */ 250 hw->phy.ops.write_reg(hw, IXGBE_MDIO_PHY_XS_CONTROL, 251 IXGBE_MDIO_PHY_XS_DEV_TYPE, 252 IXGBE_MDIO_PHY_XS_RESET); 253 254 /* 255 * Poll for reset bit to self-clear indicating reset is complete. 256 * Some PHYs could take up to 3 seconds to complete and need about 257 * 1.7 usec delay after the reset is complete. 258 */ 259 for (i = 0; i < 30; i++) { 260 msec_delay(100); 261 hw->phy.ops.read_reg(hw, IXGBE_MDIO_PHY_XS_CONTROL, 262 IXGBE_MDIO_PHY_XS_DEV_TYPE, &ctrl); 263 if (!(ctrl & IXGBE_MDIO_PHY_XS_RESET)) { 264 usec_delay(2); 265 break; 266 } 267 } 268 269 if (ctrl & IXGBE_MDIO_PHY_XS_RESET) { 270 status = IXGBE_ERR_RESET_FAILED; 271 ERROR_REPORT1(IXGBE_ERROR_POLLING, 272 "PHY reset polling failed to complete.\n"); 273 } 274 275 out: 276 return status; 277 } 278 279 /** 280 * ixgbe_read_phy_mdi - Reads a value from a specified PHY register without 281 * the SWFW lock 282 * @hw: pointer to hardware structure 283 * @reg_addr: 32 bit address of PHY register to read 284 * @phy_data: Pointer to read data from PHY register 285 **/ 286 int32_t ixgbe_read_phy_reg_mdi(struct ixgbe_hw *hw, uint32_t reg_addr, 287 uint32_t device_type, uint16_t *phy_data) 288 { 289 uint32_t i, data, command; 290 291 /* Setup and write the address cycle command */ 292 command = ((reg_addr << IXGBE_MSCA_NP_ADDR_SHIFT) | 293 (device_type << IXGBE_MSCA_DEV_TYPE_SHIFT) | 294 (hw->phy.addr << IXGBE_MSCA_PHY_ADDR_SHIFT) | 295 (IXGBE_MSCA_ADDR_CYCLE | IXGBE_MSCA_MDI_COMMAND)); 296 297 IXGBE_WRITE_REG(hw, IXGBE_MSCA, command); 298 299 /* 300 * Check every 10 usec to see if the address cycle completed. 301 * The MDI Command bit will clear when the operation is 302 * complete 303 */ 304 for (i = 0; i < IXGBE_MDIO_COMMAND_TIMEOUT; i++) { 305 usec_delay(10); 306 307 command = IXGBE_READ_REG(hw, IXGBE_MSCA); 308 if ((command & IXGBE_MSCA_MDI_COMMAND) == 0) 309 break; 310 } 311 312 313 if ((command & IXGBE_MSCA_MDI_COMMAND) != 0) { 314 ERROR_REPORT1(IXGBE_ERROR_POLLING, "PHY address command did not complete.\n"); 315 return IXGBE_ERR_PHY; 316 } 317 318 /* 319 * Address cycle complete, setup and write the read 320 * command 321 */ 322 command = ((reg_addr << IXGBE_MSCA_NP_ADDR_SHIFT) | 323 (device_type << IXGBE_MSCA_DEV_TYPE_SHIFT) | 324 (hw->phy.addr << IXGBE_MSCA_PHY_ADDR_SHIFT) | 325 (IXGBE_MSCA_READ | IXGBE_MSCA_MDI_COMMAND)); 326 327 IXGBE_WRITE_REG(hw, IXGBE_MSCA, command); 328 329 /* 330 * Check every 10 usec to see if the address cycle 331 * completed. The MDI Command bit will clear when the 332 * operation is complete 333 */ 334 for (i = 0; i < IXGBE_MDIO_COMMAND_TIMEOUT; i++) { 335 usec_delay(10); 336 337 command = IXGBE_READ_REG(hw, IXGBE_MSCA); 338 if ((command & IXGBE_MSCA_MDI_COMMAND) == 0) 339 break; 340 } 341 342 if ((command & IXGBE_MSCA_MDI_COMMAND) != 0) { 343 ERROR_REPORT1(IXGBE_ERROR_POLLING, "PHY read command didn't complete\n"); 344 return IXGBE_ERR_PHY; 345 } 346 347 /* 348 * Read operation is complete. Get the data 349 * from MSRWD 350 */ 351 data = IXGBE_READ_REG(hw, IXGBE_MSRWD); 352 data >>= IXGBE_MSRWD_READ_DATA_SHIFT; 353 *phy_data = (uint16_t)(data); 354 355 return IXGBE_SUCCESS; 356 } 357 358 /** 359 * ixgbe_read_phy_reg_generic - Reads a value from a specified PHY register 360 * using the SWFW lock - this function is needed in most cases 361 * @hw: pointer to hardware structure 362 * @reg_addr: 32 bit address of PHY register to read 363 * @phy_data: Pointer to read data from PHY register 364 **/ 365 int32_t ixgbe_read_phy_reg_generic(struct ixgbe_hw *hw, uint32_t reg_addr, 366 uint32_t device_type, uint16_t *phy_data) 367 { 368 int32_t status; 369 uint16_t gssr; 370 371 DEBUGFUNC("ixgbe_read_phy_reg_generic"); 372 373 if (IXGBE_READ_REG(hw, IXGBE_STATUS) & IXGBE_STATUS_LAN_ID_1) 374 gssr = IXGBE_GSSR_PHY1_SM; 375 else 376 gssr = IXGBE_GSSR_PHY0_SM; 377 378 if (hw->mac.ops.acquire_swfw_sync(hw, gssr) == IXGBE_SUCCESS) { 379 status = ixgbe_read_phy_reg_mdi(hw, reg_addr, device_type, 380 phy_data); 381 hw->mac.ops.release_swfw_sync(hw, gssr); 382 } else { 383 status = IXGBE_ERR_SWFW_SYNC; 384 } 385 386 return status; 387 } 388 389 /** 390 * ixgbe_write_phy_reg_mdi - Writes a value to specified PHY register 391 * without SWFW lock 392 * @hw: pointer to hardware structure 393 * @reg_addr: 32 bit PHY register to write 394 * @device_type: 5 bit device type 395 * @phy_data: Data to write to the PHY register 396 **/ 397 int32_t ixgbe_write_phy_reg_mdi(struct ixgbe_hw *hw, uint32_t reg_addr, 398 uint32_t device_type, uint16_t phy_data) 399 { 400 uint32_t i, command; 401 402 /* Put the data in the MDI single read and write data register*/ 403 IXGBE_WRITE_REG(hw, IXGBE_MSRWD, (uint32_t)phy_data); 404 405 /* Setup and write the address cycle command */ 406 command = ((reg_addr << IXGBE_MSCA_NP_ADDR_SHIFT) | 407 (device_type << IXGBE_MSCA_DEV_TYPE_SHIFT) | 408 (hw->phy.addr << IXGBE_MSCA_PHY_ADDR_SHIFT) | 409 (IXGBE_MSCA_ADDR_CYCLE | IXGBE_MSCA_MDI_COMMAND)); 410 411 IXGBE_WRITE_REG(hw, IXGBE_MSCA, command); 412 413 /* 414 * Check every 10 usec to see if the address cycle completed. 415 * The MDI Command bit will clear when the operation is 416 * complete 417 */ 418 for (i = 0; i < IXGBE_MDIO_COMMAND_TIMEOUT; i++) { 419 usec_delay(10); 420 421 command = IXGBE_READ_REG(hw, IXGBE_MSCA); 422 if ((command & IXGBE_MSCA_MDI_COMMAND) == 0) 423 break; 424 } 425 426 if ((command & IXGBE_MSCA_MDI_COMMAND) != 0) { 427 ERROR_REPORT1(IXGBE_ERROR_POLLING, "PHY address cmd didn't complete\n"); 428 return IXGBE_ERR_PHY; 429 } 430 431 /* 432 * Address cycle complete, setup and write the write 433 * command 434 */ 435 command = ((reg_addr << IXGBE_MSCA_NP_ADDR_SHIFT) | 436 (device_type << IXGBE_MSCA_DEV_TYPE_SHIFT) | 437 (hw->phy.addr << IXGBE_MSCA_PHY_ADDR_SHIFT) | 438 (IXGBE_MSCA_WRITE | IXGBE_MSCA_MDI_COMMAND)); 439 440 IXGBE_WRITE_REG(hw, IXGBE_MSCA, command); 441 442 /* 443 * Check every 10 usec to see if the address cycle 444 * completed. The MDI Command bit will clear when the 445 * operation is complete 446 */ 447 for (i = 0; i < IXGBE_MDIO_COMMAND_TIMEOUT; i++) { 448 usec_delay(10); 449 450 command = IXGBE_READ_REG(hw, IXGBE_MSCA); 451 if ((command & IXGBE_MSCA_MDI_COMMAND) == 0) 452 break; 453 } 454 455 if ((command & IXGBE_MSCA_MDI_COMMAND) != 0) { 456 ERROR_REPORT1(IXGBE_ERROR_POLLING, "PHY write cmd didn't complete\n"); 457 return IXGBE_ERR_PHY; 458 } 459 460 return IXGBE_SUCCESS; 461 } 462 463 /** 464 * ixgbe_write_phy_reg_generic - Writes a value to specified PHY register 465 * using SWFW lock- this function is needed in most cases 466 * @hw: pointer to hardware structure 467 * @reg_addr: 32 bit PHY register to write 468 * @device_type: 5 bit device type 469 * @phy_data: Data to write to the PHY register 470 **/ 471 int32_t ixgbe_write_phy_reg_generic(struct ixgbe_hw *hw, uint32_t reg_addr, 472 uint32_t device_type, uint16_t phy_data) 473 { 474 int32_t status; 475 uint16_t gssr; 476 477 DEBUGFUNC("ixgbe_write_phy_reg_generic"); 478 479 if (IXGBE_READ_REG(hw, IXGBE_STATUS) & IXGBE_STATUS_LAN_ID_1) 480 gssr = IXGBE_GSSR_PHY1_SM; 481 else 482 gssr = IXGBE_GSSR_PHY0_SM; 483 484 if (hw->mac.ops.acquire_swfw_sync(hw, gssr) == IXGBE_SUCCESS) { 485 status = ixgbe_write_phy_reg_mdi(hw, reg_addr, device_type, 486 phy_data); 487 hw->mac.ops.release_swfw_sync(hw, gssr); 488 } else { 489 status = IXGBE_ERR_SWFW_SYNC; 490 } 491 492 return status; 493 } 494 495 /** 496 * ixgbe_setup_phy_link_generic - Set and restart autoneg 497 * @hw: pointer to hardware structure 498 * 499 * Restart autonegotiation and PHY and waits for completion. 500 **/ 501 int32_t ixgbe_setup_phy_link_generic(struct ixgbe_hw *hw) 502 { 503 int32_t status = IXGBE_SUCCESS; 504 uint32_t time_out; 505 uint32_t max_time_out = 10; 506 uint16_t autoneg_reg = IXGBE_MII_AUTONEG_REG; 507 bool autoneg = FALSE; 508 ixgbe_link_speed speed; 509 510 DEBUGFUNC("ixgbe_setup_phy_link_generic"); 511 512 ixgbe_get_copper_link_capabilities_generic(hw, &speed, &autoneg); 513 514 if (speed & IXGBE_LINK_SPEED_10GB_FULL) { 515 /* Set or unset auto-negotiation 10G advertisement */ 516 hw->phy.ops.read_reg(hw, IXGBE_MII_10GBASE_T_AUTONEG_CTRL_REG, 517 IXGBE_MDIO_AUTO_NEG_DEV_TYPE, 518 &autoneg_reg); 519 520 autoneg_reg &= ~IXGBE_MII_10GBASE_T_ADVERTISE; 521 if (hw->phy.autoneg_advertised & IXGBE_LINK_SPEED_10GB_FULL) 522 autoneg_reg |= IXGBE_MII_10GBASE_T_ADVERTISE; 523 524 hw->phy.ops.write_reg(hw, IXGBE_MII_10GBASE_T_AUTONEG_CTRL_REG, 525 IXGBE_MDIO_AUTO_NEG_DEV_TYPE, 526 autoneg_reg); 527 } 528 529 if (speed & IXGBE_LINK_SPEED_1GB_FULL) { 530 /* Set or unset auto-negotiation 1G advertisement */ 531 hw->phy.ops.read_reg(hw, 532 IXGBE_MII_AUTONEG_VENDOR_PROVISION_1_REG, 533 IXGBE_MDIO_AUTO_NEG_DEV_TYPE, 534 &autoneg_reg); 535 536 autoneg_reg &= ~IXGBE_MII_1GBASE_T_ADVERTISE; 537 if (hw->phy.autoneg_advertised & IXGBE_LINK_SPEED_1GB_FULL) 538 autoneg_reg |= IXGBE_MII_1GBASE_T_ADVERTISE; 539 540 hw->phy.ops.write_reg(hw, 541 IXGBE_MII_AUTONEG_VENDOR_PROVISION_1_REG, 542 IXGBE_MDIO_AUTO_NEG_DEV_TYPE, 543 autoneg_reg); 544 } 545 546 if (speed & IXGBE_LINK_SPEED_100_FULL) { 547 /* Set or unset auto-negotiation 100M advertisement */ 548 hw->phy.ops.read_reg(hw, IXGBE_MII_AUTONEG_ADVERTISE_REG, 549 IXGBE_MDIO_AUTO_NEG_DEV_TYPE, 550 &autoneg_reg); 551 552 autoneg_reg &= ~(IXGBE_MII_100BASE_T_ADVERTISE | 553 IXGBE_MII_100BASE_T_ADVERTISE_HALF); 554 if (hw->phy.autoneg_advertised & IXGBE_LINK_SPEED_100_FULL) 555 autoneg_reg |= IXGBE_MII_100BASE_T_ADVERTISE; 556 557 hw->phy.ops.write_reg(hw, IXGBE_MII_AUTONEG_ADVERTISE_REG, 558 IXGBE_MDIO_AUTO_NEG_DEV_TYPE, 559 autoneg_reg); 560 } 561 562 /* Restart PHY autonegotiation and wait for completion */ 563 hw->phy.ops.read_reg(hw, IXGBE_MDIO_AUTO_NEG_CONTROL, 564 IXGBE_MDIO_AUTO_NEG_DEV_TYPE, &autoneg_reg); 565 566 autoneg_reg |= IXGBE_MII_RESTART; 567 568 hw->phy.ops.write_reg(hw, IXGBE_MDIO_AUTO_NEG_CONTROL, 569 IXGBE_MDIO_AUTO_NEG_DEV_TYPE, autoneg_reg); 570 571 /* Wait for autonegotiation to finish */ 572 for (time_out = 0; time_out < max_time_out; time_out++) { 573 usec_delay(10); 574 /* Restart PHY autonegotiation and wait for completion */ 575 status = hw->phy.ops.read_reg(hw, IXGBE_MDIO_AUTO_NEG_STATUS, 576 IXGBE_MDIO_AUTO_NEG_DEV_TYPE, 577 &autoneg_reg); 578 579 autoneg_reg &= IXGBE_MII_AUTONEG_COMPLETE; 580 if (autoneg_reg == IXGBE_MII_AUTONEG_COMPLETE) 581 break; 582 } 583 584 if (time_out == max_time_out) { 585 status = IXGBE_ERR_LINK_SETUP; 586 ERROR_REPORT1(IXGBE_ERROR_POLLING, 587 "PHY autonegotiation time out"); 588 } 589 590 return status; 591 } 592 593 /** 594 * ixgbe_setup_phy_link_speed_generic - Sets the auto advertised capabilities 595 * @hw: pointer to hardware structure 596 * @speed: new link speed 597 **/ 598 int32_t ixgbe_setup_phy_link_speed_generic(struct ixgbe_hw *hw, 599 ixgbe_link_speed speed, 600 bool autoneg_wait_to_complete) 601 { 602 DEBUGFUNC("ixgbe_setup_phy_link_speed_generic"); 603 604 /* 605 * Clear autoneg_advertised and set new values based on input link 606 * speed. 607 */ 608 hw->phy.autoneg_advertised = 0; 609 610 if (speed & IXGBE_LINK_SPEED_10GB_FULL) 611 hw->phy.autoneg_advertised |= IXGBE_LINK_SPEED_10GB_FULL; 612 613 if (speed & IXGBE_LINK_SPEED_1GB_FULL) 614 hw->phy.autoneg_advertised |= IXGBE_LINK_SPEED_1GB_FULL; 615 616 if (speed & IXGBE_LINK_SPEED_100_FULL) 617 hw->phy.autoneg_advertised |= IXGBE_LINK_SPEED_100_FULL; 618 619 /* Setup link based on the new speed settings */ 620 hw->phy.ops.setup_link(hw); 621 622 return IXGBE_SUCCESS; 623 } 624 625 /** 626 * ixgbe_get_copper_link_capabilities_generic - Determines link capabilities 627 * @hw: pointer to hardware structure 628 * @speed: pointer to link speed 629 * @autoneg: boolean auto-negotiation value 630 * 631 * Determines the link capabilities by reading the AUTOC register. 632 **/ 633 int32_t ixgbe_get_copper_link_capabilities_generic(struct ixgbe_hw *hw, 634 ixgbe_link_speed *speed, 635 bool *autoneg) 636 { 637 int32_t status = IXGBE_ERR_LINK_SETUP; 638 uint16_t speed_ability; 639 640 DEBUGFUNC("ixgbe_get_copper_link_capabilities_generic"); 641 642 *speed = 0; 643 *autoneg = TRUE; 644 645 status = hw->phy.ops.read_reg(hw, IXGBE_MDIO_PHY_SPEED_ABILITY, 646 IXGBE_MDIO_PMA_PMD_DEV_TYPE, 647 &speed_ability); 648 649 if (status == IXGBE_SUCCESS) { 650 if (speed_ability & IXGBE_MDIO_PHY_SPEED_10G) 651 *speed |= IXGBE_LINK_SPEED_10GB_FULL; 652 if (speed_ability & IXGBE_MDIO_PHY_SPEED_1G) 653 *speed |= IXGBE_LINK_SPEED_1GB_FULL; 654 if (speed_ability & IXGBE_MDIO_PHY_SPEED_100M) 655 *speed |= IXGBE_LINK_SPEED_100_FULL; 656 } 657 658 return status; 659 } 660 661 /** 662 * ixgbe_check_phy_link_tnx - Determine link and speed status 663 * @hw: pointer to hardware structure 664 * 665 * Reads the VS1 register to determine if link is up and the current speed for 666 * the PHY. 667 **/ 668 int32_t ixgbe_check_phy_link_tnx(struct ixgbe_hw *hw, ixgbe_link_speed *speed, 669 bool *link_up) 670 { 671 int32_t status = IXGBE_SUCCESS; 672 uint32_t time_out; 673 uint32_t max_time_out = 10; 674 uint16_t phy_link = 0; 675 uint16_t phy_speed = 0; 676 uint16_t phy_data = 0; 677 678 DEBUGFUNC("ixgbe_check_phy_link_tnx"); 679 680 /* Initialize speed and link to default case */ 681 *link_up = FALSE; 682 *speed = IXGBE_LINK_SPEED_10GB_FULL; 683 684 /* 685 * Check current speed and link status of the PHY register. 686 * This is a vendor specific register and may have to 687 * be changed for other copper PHYs. 688 */ 689 for (time_out = 0; time_out < max_time_out; time_out++) { 690 usec_delay(10); 691 status = hw->phy.ops.read_reg(hw, 692 IXGBE_MDIO_VENDOR_SPECIFIC_1_STATUS, 693 IXGBE_MDIO_VENDOR_SPECIFIC_1_DEV_TYPE, 694 &phy_data); 695 phy_link = phy_data & IXGBE_MDIO_VENDOR_SPECIFIC_1_LINK_STATUS; 696 phy_speed = phy_data & 697 IXGBE_MDIO_VENDOR_SPECIFIC_1_SPEED_STATUS; 698 if (phy_link == IXGBE_MDIO_VENDOR_SPECIFIC_1_LINK_STATUS) { 699 *link_up = TRUE; 700 if (phy_speed == 701 IXGBE_MDIO_VENDOR_SPECIFIC_1_SPEED_STATUS) 702 *speed = IXGBE_LINK_SPEED_1GB_FULL; 703 break; 704 } 705 } 706 707 return status; 708 } 709 710 /** 711 * ixgbe_setup_phy_link_tnx - Set and restart autoneg 712 * @hw: pointer to hardware structure 713 * 714 * Restart autonegotiation and PHY and waits for completion. 715 **/ 716 int32_t ixgbe_setup_phy_link_tnx(struct ixgbe_hw *hw) 717 { 718 int32_t status = IXGBE_SUCCESS; 719 uint32_t time_out; 720 uint32_t max_time_out = 10; 721 uint16_t autoneg_reg = IXGBE_MII_AUTONEG_REG; 722 bool autoneg = FALSE; 723 ixgbe_link_speed speed; 724 725 DEBUGFUNC("ixgbe_setup_phy_link_tnx"); 726 727 ixgbe_get_copper_link_capabilities_generic(hw, &speed, &autoneg); 728 729 if (speed & IXGBE_LINK_SPEED_10GB_FULL) { 730 /* Set or unset auto-negotiation 10G advertisement */ 731 hw->phy.ops.read_reg(hw, IXGBE_MII_10GBASE_T_AUTONEG_CTRL_REG, 732 IXGBE_MDIO_AUTO_NEG_DEV_TYPE, 733 &autoneg_reg); 734 735 autoneg_reg &= ~IXGBE_MII_10GBASE_T_ADVERTISE; 736 if (hw->phy.autoneg_advertised & IXGBE_LINK_SPEED_10GB_FULL) 737 autoneg_reg |= IXGBE_MII_10GBASE_T_ADVERTISE; 738 739 hw->phy.ops.write_reg(hw, IXGBE_MII_10GBASE_T_AUTONEG_CTRL_REG, 740 IXGBE_MDIO_AUTO_NEG_DEV_TYPE, 741 autoneg_reg); 742 } 743 744 if (speed & IXGBE_LINK_SPEED_1GB_FULL) { 745 /* Set or unset auto-negotiation 1G advertisement */ 746 hw->phy.ops.read_reg(hw, IXGBE_MII_AUTONEG_XNP_TX_REG, 747 IXGBE_MDIO_AUTO_NEG_DEV_TYPE, 748 &autoneg_reg); 749 750 autoneg_reg &= ~IXGBE_MII_1GBASE_T_ADVERTISE_XNP_TX; 751 if (hw->phy.autoneg_advertised & IXGBE_LINK_SPEED_1GB_FULL) 752 autoneg_reg |= IXGBE_MII_1GBASE_T_ADVERTISE_XNP_TX; 753 754 hw->phy.ops.write_reg(hw, IXGBE_MII_AUTONEG_XNP_TX_REG, 755 IXGBE_MDIO_AUTO_NEG_DEV_TYPE, 756 autoneg_reg); 757 } 758 759 if (speed & IXGBE_LINK_SPEED_100_FULL) { 760 /* Set or unset auto-negotiation 100M advertisement */ 761 hw->phy.ops.read_reg(hw, IXGBE_MII_AUTONEG_ADVERTISE_REG, 762 IXGBE_MDIO_AUTO_NEG_DEV_TYPE, 763 &autoneg_reg); 764 765 autoneg_reg &= ~IXGBE_MII_100BASE_T_ADVERTISE; 766 if (hw->phy.autoneg_advertised & IXGBE_LINK_SPEED_100_FULL) 767 autoneg_reg |= IXGBE_MII_100BASE_T_ADVERTISE; 768 769 hw->phy.ops.write_reg(hw, IXGBE_MII_AUTONEG_ADVERTISE_REG, 770 IXGBE_MDIO_AUTO_NEG_DEV_TYPE, 771 autoneg_reg); 772 } 773 774 /* Restart PHY autonegotiation and wait for completion */ 775 hw->phy.ops.read_reg(hw, IXGBE_MDIO_AUTO_NEG_CONTROL, 776 IXGBE_MDIO_AUTO_NEG_DEV_TYPE, &autoneg_reg); 777 778 autoneg_reg |= IXGBE_MII_RESTART; 779 780 hw->phy.ops.write_reg(hw, IXGBE_MDIO_AUTO_NEG_CONTROL, 781 IXGBE_MDIO_AUTO_NEG_DEV_TYPE, autoneg_reg); 782 783 /* Wait for autonegotiation to finish */ 784 for (time_out = 0; time_out < max_time_out; time_out++) { 785 usec_delay(10); 786 /* Restart PHY autonegotiation and wait for completion */ 787 status = hw->phy.ops.read_reg(hw, IXGBE_MDIO_AUTO_NEG_STATUS, 788 IXGBE_MDIO_AUTO_NEG_DEV_TYPE, 789 &autoneg_reg); 790 791 autoneg_reg &= IXGBE_MII_AUTONEG_COMPLETE; 792 if (autoneg_reg == IXGBE_MII_AUTONEG_COMPLETE) 793 break; 794 } 795 796 if (time_out == max_time_out) { 797 status = IXGBE_ERR_LINK_SETUP; 798 DEBUGOUT("ixgbe_setup_phy_link_tnx: time out"); 799 } 800 801 return status; 802 } 803 804 /** 805 * ixgbe_get_phy_firmware_version_tnx - Gets the PHY Firmware Version 806 * @hw: pointer to hardware structure 807 * @firmware_version: pointer to the PHY Firmware Version 808 **/ 809 int32_t ixgbe_get_phy_firmware_version_tnx(struct ixgbe_hw *hw, 810 uint16_t *firmware_version) 811 { 812 int32_t status = IXGBE_SUCCESS; 813 814 DEBUGFUNC("ixgbe_get_phy_firmware_version_tnx"); 815 816 status = hw->phy.ops.read_reg(hw, TNX_FW_REV, 817 IXGBE_MDIO_VENDOR_SPECIFIC_1_DEV_TYPE, 818 firmware_version); 819 820 return status; 821 } 822 823 /** 824 * ixgbe_get_phy_firmware_version_generic - Gets the PHY Firmware Version 825 * @hw: pointer to hardware structure 826 * @firmware_version: pointer to the PHY Firmware Version 827 **/ 828 int32_t ixgbe_get_phy_firmware_version_generic(struct ixgbe_hw *hw, 829 uint16_t *firmware_version) 830 { 831 int32_t status = IXGBE_SUCCESS; 832 833 DEBUGFUNC("ixgbe_get_phy_firmware_version_generic"); 834 835 status = hw->phy.ops.read_reg(hw, AQ_FW_REV, 836 IXGBE_MDIO_VENDOR_SPECIFIC_1_DEV_TYPE, 837 firmware_version); 838 839 return status; 840 } 841 842 /** 843 * ixgbe_reset_phy_nl - Performs a PHY reset 844 * @hw: pointer to hardware structure 845 **/ 846 int32_t ixgbe_reset_phy_nl(struct ixgbe_hw *hw) 847 { 848 uint16_t phy_offset, control, eword, edata, block_crc; 849 bool end_data = FALSE; 850 uint16_t list_offset, data_offset; 851 uint16_t phy_data = 0; 852 int32_t ret_val = IXGBE_SUCCESS; 853 uint32_t i; 854 855 DEBUGFUNC("ixgbe_reset_phy_nl"); 856 857 hw->phy.ops.read_reg(hw, IXGBE_MDIO_PHY_XS_CONTROL, 858 IXGBE_MDIO_PHY_XS_DEV_TYPE, &phy_data); 859 860 /* reset the PHY and poll for completion */ 861 hw->phy.ops.write_reg(hw, IXGBE_MDIO_PHY_XS_CONTROL, 862 IXGBE_MDIO_PHY_XS_DEV_TYPE, 863 (phy_data | IXGBE_MDIO_PHY_XS_RESET)); 864 865 for (i = 0; i < 100; i++) { 866 hw->phy.ops.read_reg(hw, IXGBE_MDIO_PHY_XS_CONTROL, 867 IXGBE_MDIO_PHY_XS_DEV_TYPE, &phy_data); 868 if ((phy_data & IXGBE_MDIO_PHY_XS_RESET) == 0) 869 break; 870 msec_delay(10); 871 } 872 873 if ((phy_data & IXGBE_MDIO_PHY_XS_RESET) != 0) { 874 DEBUGOUT("PHY reset did not complete.\n"); 875 ret_val = IXGBE_ERR_PHY; 876 goto out; 877 } 878 879 /* Get init offsets */ 880 ret_val = ixgbe_get_sfp_init_sequence_offsets(hw, &list_offset, 881 &data_offset); 882 if (ret_val != IXGBE_SUCCESS) 883 goto out; 884 885 ret_val = hw->eeprom.ops.read(hw, data_offset, &block_crc); 886 data_offset++; 887 while (!end_data) { 888 /* 889 * Read control word from PHY init contents offset 890 */ 891 ret_val = hw->eeprom.ops.read(hw, data_offset, &eword); 892 if (ret_val) 893 goto err_eeprom; 894 control = (eword & IXGBE_CONTROL_MASK_NL) >> 895 IXGBE_CONTROL_SHIFT_NL; 896 edata = eword & IXGBE_DATA_MASK_NL; 897 switch (control) { 898 case IXGBE_DELAY_NL: 899 data_offset++; 900 DEBUGOUT1("DELAY: %d MS\n", edata); 901 msec_delay(edata); 902 break; 903 case IXGBE_DATA_NL: 904 DEBUGOUT("DATA:\n"); 905 data_offset++; 906 ret_val = hw->eeprom.ops.read(hw, data_offset, 907 &phy_offset); 908 if (ret_val) 909 goto err_eeprom; 910 data_offset++; 911 for (i = 0; i < edata; i++) { 912 ret_val = hw->eeprom.ops.read(hw, data_offset, 913 &eword); 914 if (ret_val) 915 goto err_eeprom; 916 hw->phy.ops.write_reg(hw, phy_offset, 917 IXGBE_TWINAX_DEV, eword); 918 DEBUGOUT2("Wrote %4.4x to %4.4x\n", eword, 919 phy_offset); 920 data_offset++; 921 phy_offset++; 922 } 923 break; 924 case IXGBE_CONTROL_NL: 925 data_offset++; 926 DEBUGOUT("CONTROL:\n"); 927 if (edata == IXGBE_CONTROL_EOL_NL) { 928 DEBUGOUT("EOL\n"); 929 end_data = TRUE; 930 } else if (edata == IXGBE_CONTROL_SOL_NL) { 931 DEBUGOUT("SOL\n"); 932 } else { 933 DEBUGOUT("Bad control value\n"); 934 ret_val = IXGBE_ERR_PHY; 935 goto out; 936 } 937 break; 938 default: 939 DEBUGOUT("Bad control type\n"); 940 ret_val = IXGBE_ERR_PHY; 941 goto out; 942 } 943 } 944 945 out: 946 return ret_val; 947 948 err_eeprom: 949 ERROR_REPORT2(IXGBE_ERROR_INVALID_STATE, 950 "eeprom read at offset %d failed", data_offset); 951 return IXGBE_ERR_PHY; 952 } 953 954 /** 955 * ixgbe_identify_module_generic - Identifies module type 956 * @hw: pointer to hardware structure 957 * 958 * Determines HW type and calls appropriate function. 959 **/ 960 int32_t ixgbe_identify_module_generic(struct ixgbe_hw *hw) 961 { 962 int32_t status = IXGBE_ERR_SFP_NOT_PRESENT; 963 964 DEBUGFUNC("ixgbe_identify_module_generic"); 965 966 switch (hw->mac.ops.get_media_type(hw)) { 967 case ixgbe_media_type_fiber: 968 status = ixgbe_identify_sfp_module_generic(hw); 969 break; 970 971 972 default: 973 hw->phy.sfp_type = ixgbe_sfp_type_not_present; 974 status = IXGBE_ERR_SFP_NOT_PRESENT; 975 break; 976 } 977 978 return status; 979 } 980 981 /** 982 * ixgbe_identify_sfp_module_generic - Identifies SFP modules 983 * @hw: pointer to hardware structure 984 * 985 * Searches for and identifies the SFP module and assigns appropriate PHY type. 986 **/ 987 int32_t ixgbe_identify_sfp_module_generic(struct ixgbe_hw *hw) 988 { 989 int32_t status = IXGBE_ERR_PHY_ADDR_INVALID; 990 uint32_t vendor_oui = 0; 991 enum ixgbe_sfp_type stored_sfp_type = hw->phy.sfp_type; 992 uint8_t identifier = 0; 993 uint8_t comp_codes_1g = 0; 994 uint8_t comp_codes_10g = 0; 995 uint8_t oui_bytes[3] = {0, 0, 0}; 996 uint8_t cable_tech = 0; 997 uint8_t cable_spec = 0; 998 uint16_t enforce_sfp = 0; 999 1000 DEBUGFUNC("ixgbe_identify_sfp_module_generic"); 1001 1002 if (hw->mac.ops.get_media_type(hw) != ixgbe_media_type_fiber) { 1003 hw->phy.sfp_type = ixgbe_sfp_type_not_present; 1004 status = IXGBE_ERR_SFP_NOT_PRESENT; 1005 goto out; 1006 } 1007 1008 status = hw->phy.ops.read_i2c_eeprom(hw, 1009 IXGBE_SFF_IDENTIFIER, 1010 &identifier); 1011 1012 if (status != IXGBE_SUCCESS) 1013 goto err_read_i2c_eeprom; 1014 1015 /* LAN ID is needed for sfp_type determination */ 1016 hw->mac.ops.set_lan_id(hw); 1017 1018 if (identifier != IXGBE_SFF_IDENTIFIER_SFP) { 1019 hw->phy.type = ixgbe_phy_sfp_unsupported; 1020 status = IXGBE_ERR_SFP_NOT_SUPPORTED; 1021 } else { 1022 status = hw->phy.ops.read_i2c_eeprom(hw, 1023 IXGBE_SFF_1GBE_COMP_CODES, 1024 &comp_codes_1g); 1025 1026 if (status != IXGBE_SUCCESS) 1027 goto err_read_i2c_eeprom; 1028 1029 status = hw->phy.ops.read_i2c_eeprom(hw, 1030 IXGBE_SFF_10GBE_COMP_CODES, 1031 &comp_codes_10g); 1032 1033 if (status != IXGBE_SUCCESS) 1034 goto err_read_i2c_eeprom; 1035 status = hw->phy.ops.read_i2c_eeprom(hw, 1036 IXGBE_SFF_CABLE_TECHNOLOGY, 1037 &cable_tech); 1038 1039 if (status != IXGBE_SUCCESS) 1040 goto err_read_i2c_eeprom; 1041 1042 /* ID Module 1043 * ========= 1044 * 0 SFP_DA_CU 1045 * 1 SFP_SR 1046 * 2 SFP_LR 1047 * 3 SFP_DA_CORE0 - 82599-specific 1048 * 4 SFP_DA_CORE1 - 82599-specific 1049 * 5 SFP_SR/LR_CORE0 - 82599-specific 1050 * 6 SFP_SR/LR_CORE1 - 82599-specific 1051 * 7 SFP_act_lmt_DA_CORE0 - 82599-specific 1052 * 8 SFP_act_lmt_DA_CORE1 - 82599-specific 1053 * 9 SFP_1g_cu_CORE0 - 82599-specific 1054 * 10 SFP_1g_cu_CORE1 - 82599-specific 1055 * 11 SFP_1g_sx_CORE0 - 82599-specific 1056 * 12 SFP_1g_sx_CORE1 - 82599-specific 1057 */ 1058 if (hw->mac.type == ixgbe_mac_82598EB) { 1059 if (cable_tech & IXGBE_SFF_DA_PASSIVE_CABLE) 1060 hw->phy.sfp_type = ixgbe_sfp_type_da_cu; 1061 else if (comp_codes_10g & IXGBE_SFF_10GBASESR_CAPABLE) 1062 hw->phy.sfp_type = ixgbe_sfp_type_sr; 1063 else if (comp_codes_10g & IXGBE_SFF_10GBASELR_CAPABLE) 1064 hw->phy.sfp_type = ixgbe_sfp_type_lr; 1065 else if (comp_codes_10g & IXGBE_SFF_DA_BAD_HP_CABLE) 1066 hw->phy.sfp_type = ixgbe_sfp_type_da_cu; 1067 else 1068 hw->phy.sfp_type = ixgbe_sfp_type_unknown; 1069 } else if (hw->mac.type == ixgbe_mac_82599EB) { 1070 if (cable_tech & IXGBE_SFF_DA_PASSIVE_CABLE) { 1071 if (hw->bus.lan_id == 0) 1072 hw->phy.sfp_type = 1073 ixgbe_sfp_type_da_cu_core0; 1074 else 1075 hw->phy.sfp_type = 1076 ixgbe_sfp_type_da_cu_core1; 1077 } else if (cable_tech & IXGBE_SFF_DA_ACTIVE_CABLE) { 1078 hw->phy.ops.read_i2c_eeprom( 1079 hw, IXGBE_SFF_CABLE_SPEC_COMP, 1080 &cable_spec); 1081 if (cable_spec & 1082 IXGBE_SFF_DA_SPEC_ACTIVE_LIMITING) { 1083 if (hw->bus.lan_id == 0) 1084 hw->phy.sfp_type = 1085 ixgbe_sfp_type_da_act_lmt_core0; 1086 else 1087 hw->phy.sfp_type = 1088 ixgbe_sfp_type_da_act_lmt_core1; 1089 } else { 1090 hw->phy.sfp_type = 1091 ixgbe_sfp_type_unknown; 1092 } 1093 } else if (comp_codes_10g & 1094 (IXGBE_SFF_10GBASESR_CAPABLE | 1095 IXGBE_SFF_10GBASELR_CAPABLE)) { 1096 if (hw->bus.lan_id == 0) 1097 hw->phy.sfp_type = 1098 ixgbe_sfp_type_srlr_core0; 1099 else 1100 hw->phy.sfp_type = 1101 ixgbe_sfp_type_srlr_core1; 1102 } else if (comp_codes_1g & IXGBE_SFF_1GBASET_CAPABLE) { 1103 if (hw->bus.lan_id == 0) 1104 hw->phy.sfp_type = 1105 ixgbe_sfp_type_1g_cu_core0; 1106 else 1107 hw->phy.sfp_type = 1108 ixgbe_sfp_type_1g_cu_core1; 1109 } else if (comp_codes_1g & IXGBE_SFF_1GBASESX_CAPABLE) { 1110 if (hw->bus.lan_id == 0) 1111 hw->phy.sfp_type = 1112 ixgbe_sfp_type_1g_sx_core0; 1113 else 1114 hw->phy.sfp_type = 1115 ixgbe_sfp_type_1g_sx_core1; 1116 } else { 1117 hw->phy.sfp_type = ixgbe_sfp_type_unknown; 1118 } 1119 } 1120 1121 if (hw->phy.sfp_type != stored_sfp_type) 1122 hw->phy.sfp_setup_needed = TRUE; 1123 1124 /* Determine if the SFP+ PHY is dual speed or not. */ 1125 hw->phy.multispeed_fiber = FALSE; 1126 if (((comp_codes_1g & IXGBE_SFF_1GBASESX_CAPABLE) && 1127 (comp_codes_10g & IXGBE_SFF_10GBASESR_CAPABLE)) || 1128 ((comp_codes_1g & IXGBE_SFF_1GBASELX_CAPABLE) && 1129 (comp_codes_10g & IXGBE_SFF_10GBASELR_CAPABLE))) 1130 hw->phy.multispeed_fiber = TRUE; 1131 1132 /* Determine PHY vendor */ 1133 if (hw->phy.type != ixgbe_phy_nl) { 1134 hw->phy.id = identifier; 1135 status = hw->phy.ops.read_i2c_eeprom(hw, 1136 IXGBE_SFF_VENDOR_OUI_BYTE0, 1137 &oui_bytes[0]); 1138 1139 if (status != IXGBE_SUCCESS) 1140 goto err_read_i2c_eeprom; 1141 1142 status = hw->phy.ops.read_i2c_eeprom(hw, 1143 IXGBE_SFF_VENDOR_OUI_BYTE1, 1144 &oui_bytes[1]); 1145 1146 if (status != IXGBE_SUCCESS) 1147 goto err_read_i2c_eeprom; 1148 1149 status = hw->phy.ops.read_i2c_eeprom(hw, 1150 IXGBE_SFF_VENDOR_OUI_BYTE2, 1151 &oui_bytes[2]); 1152 1153 if (status != IXGBE_SUCCESS) 1154 goto err_read_i2c_eeprom; 1155 1156 vendor_oui = 1157 ((oui_bytes[0] << IXGBE_SFF_VENDOR_OUI_BYTE0_SHIFT) | 1158 (oui_bytes[1] << IXGBE_SFF_VENDOR_OUI_BYTE1_SHIFT) | 1159 (oui_bytes[2] << IXGBE_SFF_VENDOR_OUI_BYTE2_SHIFT)); 1160 1161 switch (vendor_oui) { 1162 case IXGBE_SFF_VENDOR_OUI_TYCO: 1163 if (cable_tech & IXGBE_SFF_DA_PASSIVE_CABLE) 1164 hw->phy.type = 1165 ixgbe_phy_sfp_passive_tyco; 1166 break; 1167 case IXGBE_SFF_VENDOR_OUI_FTL: 1168 if (cable_tech & IXGBE_SFF_DA_ACTIVE_CABLE) 1169 hw->phy.type = ixgbe_phy_sfp_ftl_active; 1170 else 1171 hw->phy.type = ixgbe_phy_sfp_ftl; 1172 break; 1173 case IXGBE_SFF_VENDOR_OUI_AVAGO: 1174 hw->phy.type = ixgbe_phy_sfp_avago; 1175 break; 1176 case IXGBE_SFF_VENDOR_OUI_INTEL: 1177 hw->phy.type = ixgbe_phy_sfp_intel; 1178 break; 1179 default: 1180 if (cable_tech & IXGBE_SFF_DA_PASSIVE_CABLE) 1181 hw->phy.type = 1182 ixgbe_phy_sfp_passive_unknown; 1183 else if (cable_tech & IXGBE_SFF_DA_ACTIVE_CABLE) 1184 hw->phy.type = 1185 ixgbe_phy_sfp_active_unknown; 1186 else 1187 hw->phy.type = ixgbe_phy_sfp_unknown; 1188 break; 1189 } 1190 } 1191 1192 /* Allow any DA cable vendor */ 1193 if (cable_tech & (IXGBE_SFF_DA_PASSIVE_CABLE | 1194 IXGBE_SFF_DA_ACTIVE_CABLE)) { 1195 status = IXGBE_SUCCESS; 1196 goto out; 1197 } 1198 1199 /* Verify supported 1G SFP modules */ 1200 if (comp_codes_10g == 0 && 1201 !(hw->phy.sfp_type == ixgbe_sfp_type_1g_cu_core1 || 1202 hw->phy.sfp_type == ixgbe_sfp_type_1g_cu_core0 || 1203 hw->phy.sfp_type == ixgbe_sfp_type_1g_sx_core0 || 1204 hw->phy.sfp_type == ixgbe_sfp_type_1g_sx_core1)) { 1205 hw->phy.type = ixgbe_phy_sfp_unsupported; 1206 status = IXGBE_ERR_SFP_NOT_SUPPORTED; 1207 goto out; 1208 } 1209 1210 /* Anything else 82598-based is supported */ 1211 if (hw->mac.type == ixgbe_mac_82598EB) { 1212 status = IXGBE_SUCCESS; 1213 goto out; 1214 } 1215 1216 if (hw->mac.type != ixgbe_mac_82598EB) 1217 ixgbe_get_device_caps_generic(hw, &enforce_sfp); 1218 if (!(enforce_sfp & IXGBE_DEVICE_CAPS_ALLOW_ANY_SFP) && 1219 !(hw->phy.sfp_type == ixgbe_sfp_type_1g_cu_core0 || 1220 hw->phy.sfp_type == ixgbe_sfp_type_1g_cu_core1 || 1221 hw->phy.sfp_type == ixgbe_sfp_type_1g_sx_core0 || 1222 hw->phy.sfp_type == ixgbe_sfp_type_1g_sx_core1)) { 1223 /* Make sure we're a supported PHY type */ 1224 if (hw->phy.type == ixgbe_phy_sfp_intel) { 1225 status = IXGBE_SUCCESS; 1226 } else { 1227 DEBUGOUT("SFP+ module not supported\n"); 1228 hw->phy.type = ixgbe_phy_sfp_unsupported; 1229 status = IXGBE_ERR_SFP_NOT_SUPPORTED; 1230 } 1231 } else { 1232 status = IXGBE_SUCCESS; 1233 } 1234 } 1235 1236 out: 1237 return status; 1238 1239 err_read_i2c_eeprom: 1240 hw->phy.sfp_type = ixgbe_sfp_type_not_present; 1241 if (hw->phy.type != ixgbe_phy_nl) { 1242 hw->phy.id = 0; 1243 hw->phy.type = ixgbe_phy_unknown; 1244 } 1245 return IXGBE_ERR_SFP_NOT_PRESENT; 1246 } 1247 1248 /** 1249 * ixgbe_get_sfp_init_sequence_offsets - Provides offset of PHY init sequence 1250 * @hw: pointer to hardware structure 1251 * @list_offset: offset to the SFP ID list 1252 * @data_offset: offset to the SFP data block 1253 * 1254 * Checks the MAC's EEPROM to see if it supports a given SFP+ module type, if 1255 * so it returns the offsets to the phy init sequence block. 1256 **/ 1257 int32_t ixgbe_get_sfp_init_sequence_offsets(struct ixgbe_hw *hw, 1258 uint16_t *list_offset, 1259 uint16_t *data_offset) 1260 { 1261 uint16_t sfp_id; 1262 uint16_t sfp_type = hw->phy.sfp_type; 1263 1264 DEBUGFUNC("ixgbe_get_sfp_init_sequence_offsets"); 1265 1266 if (hw->phy.sfp_type == ixgbe_sfp_type_unknown) 1267 return IXGBE_ERR_SFP_NOT_SUPPORTED; 1268 1269 if (hw->phy.sfp_type == ixgbe_sfp_type_not_present) 1270 return IXGBE_ERR_SFP_NOT_PRESENT; 1271 1272 if ((hw->device_id == IXGBE_DEV_ID_82598_SR_DUAL_PORT_EM) && 1273 (hw->phy.sfp_type == ixgbe_sfp_type_da_cu)) 1274 return IXGBE_ERR_SFP_NOT_SUPPORTED; 1275 1276 /* 1277 * Limiting active cables and 1G Phys must be initialized as 1278 * SR modules 1279 */ 1280 if (sfp_type == ixgbe_sfp_type_da_act_lmt_core0 || 1281 sfp_type == ixgbe_sfp_type_1g_cu_core0 || 1282 sfp_type == ixgbe_sfp_type_1g_sx_core0) 1283 sfp_type = ixgbe_sfp_type_srlr_core0; 1284 else if (sfp_type == ixgbe_sfp_type_da_act_lmt_core1 || 1285 sfp_type == ixgbe_sfp_type_1g_cu_core1 || 1286 sfp_type == ixgbe_sfp_type_1g_sx_core1) 1287 sfp_type = ixgbe_sfp_type_srlr_core1; 1288 1289 /* Read offset to PHY init contents */ 1290 if (hw->eeprom.ops.read(hw, IXGBE_PHY_INIT_OFFSET_NL, list_offset)) { 1291 ERROR_REPORT2(IXGBE_ERROR_INVALID_STATE, 1292 "eeprom read at offset %d failed", 1293 IXGBE_PHY_INIT_OFFSET_NL); 1294 return IXGBE_ERR_SFP_NO_INIT_SEQ_PRESENT; 1295 } 1296 1297 if ((!*list_offset) || (*list_offset == 0xFFFF)) 1298 return IXGBE_ERR_SFP_NO_INIT_SEQ_PRESENT; 1299 1300 /* Shift offset to first ID word */ 1301 (*list_offset)++; 1302 1303 /* 1304 * Find the matching SFP ID in the EEPROM 1305 * and program the init sequence 1306 */ 1307 if (hw->eeprom.ops.read(hw, *list_offset, &sfp_id)) 1308 goto err_phy; 1309 1310 while (sfp_id != IXGBE_PHY_INIT_END_NL) { 1311 if (sfp_id == sfp_type) { 1312 (*list_offset)++; 1313 if (hw->eeprom.ops.read(hw, *list_offset, data_offset)) 1314 goto err_phy; 1315 if ((!*data_offset) || (*data_offset == 0xFFFF)) { 1316 DEBUGOUT("SFP+ module not supported\n"); 1317 return IXGBE_ERR_SFP_NOT_SUPPORTED; 1318 } else { 1319 break; 1320 } 1321 } else { 1322 (*list_offset) += 2; 1323 if (hw->eeprom.ops.read(hw, *list_offset, &sfp_id)) 1324 goto err_phy; 1325 } 1326 } 1327 1328 /* 1329 * the 82598EB SFP+ card offically supports only direct attached cables 1330 * but works fine with optical SFP+ modules as well. Even though the 1331 * EEPROM has no matching ID for them. So just accept the module. 1332 */ 1333 if (sfp_id == IXGBE_PHY_INIT_END_NL && 1334 hw->mac.type == ixgbe_mac_82598EB) { 1335 /* refetch offset for the first phy entry */ 1336 hw->eeprom.ops.read(hw, IXGBE_PHY_INIT_OFFSET_NL, list_offset); 1337 (*list_offset) += 2; 1338 hw->eeprom.ops.read(hw, *list_offset, data_offset); 1339 } else if (sfp_id == IXGBE_PHY_INIT_END_NL) { 1340 DEBUGOUT("No matching SFP+ module found\n"); 1341 return IXGBE_ERR_SFP_NOT_SUPPORTED; 1342 } 1343 1344 return IXGBE_SUCCESS; 1345 1346 err_phy: 1347 ERROR_REPORT2(IXGBE_ERROR_INVALID_STATE, 1348 "eeprom read at offset %d failed", *list_offset); 1349 return IXGBE_ERR_PHY; 1350 } 1351 1352 /** 1353 * ixgbe_read_i2c_eeprom_generic - Reads 8 bit EEPROM word over I2C interface 1354 * @hw: pointer to hardware structure 1355 * @byte_offset: EEPROM byte offset to read 1356 * @eeprom_data: value read 1357 * 1358 * Performs byte read operation to SFP module's EEPROM over I2C interface. 1359 **/ 1360 int32_t ixgbe_read_i2c_eeprom_generic(struct ixgbe_hw *hw, uint8_t byte_offset, 1361 uint8_t *eeprom_data) 1362 { 1363 DEBUGFUNC("ixgbe_read_i2c_eeprom_generic"); 1364 1365 return hw->phy.ops.read_i2c_byte(hw, byte_offset, 1366 IXGBE_I2C_EEPROM_DEV_ADDR, 1367 eeprom_data); 1368 } 1369 1370 /** 1371 * ixgbe_write_i2c_eeprom_generic - Writes 8 bit EEPROM word over I2C interface 1372 * @hw: pointer to hardware structure 1373 * @byte_offset: EEPROM byte offset to write 1374 * @eeprom_data: value to write 1375 * 1376 * Performs byte write operation to SFP module's EEPROM over I2C interface. 1377 **/ 1378 int32_t ixgbe_write_i2c_eeprom_generic(struct ixgbe_hw *hw, uint8_t byte_offset, 1379 uint8_t eeprom_data) 1380 { 1381 DEBUGFUNC("ixgbe_write_i2c_eeprom_generic"); 1382 1383 return hw->phy.ops.write_i2c_byte(hw, byte_offset, 1384 IXGBE_I2C_EEPROM_DEV_ADDR, 1385 eeprom_data); 1386 } 1387 1388 /** 1389 * ixgbe_read_i2c_byte_generic - Reads 8 bit word over I2C 1390 * @hw: pointer to hardware structure 1391 * @byte_offset: byte offset to read 1392 * @data: value read 1393 * 1394 * Performs byte read operation to SFP module's EEPROM over I2C interface at 1395 * a specified device address. 1396 **/ 1397 int32_t ixgbe_read_i2c_byte_generic(struct ixgbe_hw *hw, uint8_t byte_offset, 1398 uint8_t dev_addr, uint8_t *data) 1399 { 1400 int32_t status = IXGBE_SUCCESS; 1401 uint32_t max_retry = 10; 1402 uint32_t retry = 0; 1403 uint16_t swfw_mask = 0; 1404 int nack = 1; 1405 *data = 0; 1406 1407 DEBUGFUNC("ixgbe_read_i2c_byte_generic"); 1408 1409 if (IXGBE_READ_REG(hw, IXGBE_STATUS) & IXGBE_STATUS_LAN_ID_1) 1410 swfw_mask = IXGBE_GSSR_PHY1_SM; 1411 else 1412 swfw_mask = IXGBE_GSSR_PHY0_SM; 1413 1414 do { 1415 if (hw->mac.ops.acquire_swfw_sync(hw, swfw_mask) 1416 != IXGBE_SUCCESS) { 1417 status = IXGBE_ERR_SWFW_SYNC; 1418 goto read_byte_out; 1419 } 1420 1421 ixgbe_i2c_start(hw); 1422 1423 /* Device Address and write indication */ 1424 status = ixgbe_clock_out_i2c_byte(hw, dev_addr); 1425 if (status != IXGBE_SUCCESS) 1426 goto fail; 1427 1428 status = ixgbe_get_i2c_ack(hw); 1429 if (status != IXGBE_SUCCESS) 1430 goto fail; 1431 1432 status = ixgbe_clock_out_i2c_byte(hw, byte_offset); 1433 if (status != IXGBE_SUCCESS) 1434 goto fail; 1435 1436 status = ixgbe_get_i2c_ack(hw); 1437 if (status != IXGBE_SUCCESS) 1438 goto fail; 1439 1440 ixgbe_i2c_start(hw); 1441 1442 /* Device Address and read indication */ 1443 status = ixgbe_clock_out_i2c_byte(hw, (dev_addr | 0x1)); 1444 if (status != IXGBE_SUCCESS) 1445 goto fail; 1446 1447 status = ixgbe_get_i2c_ack(hw); 1448 if (status != IXGBE_SUCCESS) 1449 goto fail; 1450 1451 status = ixgbe_clock_in_i2c_byte(hw, data); 1452 if (status != IXGBE_SUCCESS) 1453 goto fail; 1454 1455 status = ixgbe_clock_out_i2c_bit(hw, nack); 1456 if (status != IXGBE_SUCCESS) 1457 goto fail; 1458 1459 ixgbe_i2c_stop(hw); 1460 break; 1461 1462 fail: 1463 ixgbe_i2c_bus_clear(hw); 1464 hw->mac.ops.release_swfw_sync(hw, swfw_mask); 1465 msec_delay(100); 1466 retry++; 1467 if (retry < max_retry) 1468 DEBUGOUT("I2C byte read error - Retrying.\n"); 1469 else 1470 DEBUGOUT("I2C byte read error.\n"); 1471 1472 } while (retry < max_retry); 1473 1474 hw->mac.ops.release_swfw_sync(hw, swfw_mask); 1475 1476 read_byte_out: 1477 return status; 1478 } 1479 1480 /** 1481 * ixgbe_write_i2c_byte_generic - Writes 8 bit word over I2C 1482 * @hw: pointer to hardware structure 1483 * @byte_offset: byte offset to write 1484 * @data: value to write 1485 * 1486 * Performs byte write operation to SFP module's EEPROM over I2C interface at 1487 * a specified device address. 1488 **/ 1489 int32_t ixgbe_write_i2c_byte_generic(struct ixgbe_hw *hw, uint8_t byte_offset, 1490 uint8_t dev_addr, uint8_t data) 1491 { 1492 int32_t status = IXGBE_SUCCESS; 1493 uint32_t max_retry = 1; 1494 uint32_t retry = 0; 1495 uint16_t swfw_mask = 0; 1496 1497 DEBUGFUNC("ixgbe_write_i2c_byte_generic"); 1498 1499 if (IXGBE_READ_REG(hw, IXGBE_STATUS) & IXGBE_STATUS_LAN_ID_1) 1500 swfw_mask = IXGBE_GSSR_PHY1_SM; 1501 else 1502 swfw_mask = IXGBE_GSSR_PHY0_SM; 1503 1504 if (hw->mac.ops.acquire_swfw_sync(hw, swfw_mask) != IXGBE_SUCCESS) { 1505 status = IXGBE_ERR_SWFW_SYNC; 1506 goto write_byte_out; 1507 } 1508 1509 do { 1510 ixgbe_i2c_start(hw); 1511 1512 status = ixgbe_clock_out_i2c_byte(hw, dev_addr); 1513 if (status != IXGBE_SUCCESS) 1514 goto fail; 1515 1516 status = ixgbe_get_i2c_ack(hw); 1517 if (status != IXGBE_SUCCESS) 1518 goto fail; 1519 1520 status = ixgbe_clock_out_i2c_byte(hw, byte_offset); 1521 if (status != IXGBE_SUCCESS) 1522 goto fail; 1523 1524 status = ixgbe_get_i2c_ack(hw); 1525 if (status != IXGBE_SUCCESS) 1526 goto fail; 1527 1528 status = ixgbe_clock_out_i2c_byte(hw, data); 1529 if (status != IXGBE_SUCCESS) 1530 goto fail; 1531 1532 status = ixgbe_get_i2c_ack(hw); 1533 if (status != IXGBE_SUCCESS) 1534 goto fail; 1535 1536 ixgbe_i2c_stop(hw); 1537 break; 1538 1539 fail: 1540 ixgbe_i2c_bus_clear(hw); 1541 retry++; 1542 if (retry < max_retry) 1543 DEBUGOUT("I2C byte write error - Retrying.\n"); 1544 else 1545 DEBUGOUT("I2C byte write error.\n"); 1546 } while (retry < max_retry); 1547 1548 hw->mac.ops.release_swfw_sync(hw, swfw_mask); 1549 1550 write_byte_out: 1551 return status; 1552 } 1553 1554 /** 1555 * ixgbe_i2c_start - Sets I2C start condition 1556 * @hw: pointer to hardware structure 1557 * 1558 * Sets I2C start condition (High -> Low on SDA while SCL is High) 1559 **/ 1560 void ixgbe_i2c_start(struct ixgbe_hw *hw) 1561 { 1562 uint32_t i2cctl = IXGBE_READ_REG(hw, IXGBE_I2CCTL); 1563 1564 DEBUGFUNC("ixgbe_i2c_start"); 1565 1566 /* Start condition must begin with data and clock high */ 1567 ixgbe_set_i2c_data(hw, &i2cctl, 1); 1568 ixgbe_raise_i2c_clk(hw, &i2cctl); 1569 1570 /* Setup time for start condition (4.7us) */ 1571 usec_delay(IXGBE_I2C_T_SU_STA); 1572 1573 ixgbe_set_i2c_data(hw, &i2cctl, 0); 1574 1575 /* Hold time for start condition (4us) */ 1576 usec_delay(IXGBE_I2C_T_HD_STA); 1577 1578 ixgbe_lower_i2c_clk(hw, &i2cctl); 1579 1580 /* Minimum low period of clock is 4.7 us */ 1581 usec_delay(IXGBE_I2C_T_LOW); 1582 1583 } 1584 1585 /** 1586 * ixgbe_i2c_stop - Sets I2C stop condition 1587 * @hw: pointer to hardware structure 1588 * 1589 * Sets I2C stop condition (Low -> High on SDA while SCL is High) 1590 **/ 1591 void ixgbe_i2c_stop(struct ixgbe_hw *hw) 1592 { 1593 uint32_t i2cctl = IXGBE_READ_REG(hw, IXGBE_I2CCTL); 1594 1595 DEBUGFUNC("ixgbe_i2c_stop"); 1596 1597 /* Stop condition must begin with data low and clock high */ 1598 ixgbe_set_i2c_data(hw, &i2cctl, 0); 1599 ixgbe_raise_i2c_clk(hw, &i2cctl); 1600 1601 /* Setup time for stop condition (4us) */ 1602 usec_delay(IXGBE_I2C_T_SU_STO); 1603 1604 ixgbe_set_i2c_data(hw, &i2cctl, 1); 1605 1606 /* bus free time between stop and start (4.7us)*/ 1607 usec_delay(IXGBE_I2C_T_BUF); 1608 } 1609 1610 /** 1611 * ixgbe_clock_in_i2c_byte - Clocks in one byte via I2C 1612 * @hw: pointer to hardware structure 1613 * @data: data byte to clock in 1614 * 1615 * Clocks in one byte data via I2C data/clock 1616 **/ 1617 int32_t ixgbe_clock_in_i2c_byte(struct ixgbe_hw *hw, uint8_t *data) 1618 { 1619 int32_t i; 1620 int bit = 0; 1621 1622 DEBUGFUNC("ixgbe_clock_in_i2c_byte"); 1623 1624 for (i = 7; i >= 0; i--) { 1625 ixgbe_clock_in_i2c_bit(hw, &bit); 1626 *data |= bit << i; 1627 } 1628 1629 return IXGBE_SUCCESS; 1630 } 1631 1632 /** 1633 * ixgbe_clock_out_i2c_byte - Clocks out one byte via I2C 1634 * @hw: pointer to hardware structure 1635 * @data: data byte clocked out 1636 * 1637 * Clocks out one byte data via I2C data/clock 1638 **/ 1639 int32_t ixgbe_clock_out_i2c_byte(struct ixgbe_hw *hw, uint8_t data) 1640 { 1641 int32_t status = IXGBE_SUCCESS; 1642 int32_t i; 1643 uint32_t i2cctl; 1644 int bit = 0; 1645 1646 DEBUGFUNC("ixgbe_clock_out_i2c_byte"); 1647 1648 for (i = 7; i >= 0; i--) { 1649 bit = (data >> i) & 0x1; 1650 status = ixgbe_clock_out_i2c_bit(hw, bit); 1651 1652 if (status != IXGBE_SUCCESS) 1653 break; 1654 } 1655 1656 /* Release SDA line (set high) */ 1657 i2cctl = IXGBE_READ_REG(hw, IXGBE_I2CCTL); 1658 i2cctl |= IXGBE_I2C_DATA_OUT; 1659 IXGBE_WRITE_REG(hw, IXGBE_I2CCTL, i2cctl); 1660 IXGBE_WRITE_FLUSH(hw); 1661 1662 return status; 1663 } 1664 1665 /** 1666 * ixgbe_get_i2c_ack - Polls for I2C ACK 1667 * @hw: pointer to hardware structure 1668 * 1669 * Clocks in/out one bit via I2C data/clock 1670 **/ 1671 int32_t ixgbe_get_i2c_ack(struct ixgbe_hw *hw) 1672 { 1673 int32_t status = IXGBE_SUCCESS; 1674 uint32_t i = 0; 1675 uint32_t i2cctl = IXGBE_READ_REG(hw, IXGBE_I2CCTL); 1676 uint32_t timeout = 10; 1677 int ack = 1; 1678 1679 DEBUGFUNC("ixgbe_get_i2c_ack"); 1680 1681 ixgbe_raise_i2c_clk(hw, &i2cctl); 1682 1683 /* Minimum high period of clock is 4us */ 1684 usec_delay(IXGBE_I2C_T_HIGH); 1685 1686 /* Poll for ACK. Note that ACK in I2C spec is 1687 * transition from 1 to 0 */ 1688 for (i = 0; i < timeout; i++) { 1689 i2cctl = IXGBE_READ_REG(hw, IXGBE_I2CCTL); 1690 ack = ixgbe_get_i2c_data(&i2cctl); 1691 1692 usec_delay(1); 1693 if (ack == 0) 1694 break; 1695 } 1696 1697 if (ack == 1) { 1698 ERROR_REPORT1(IXGBE_ERROR_POLLING, 1699 "I2C ack was not received.\n"); 1700 status = IXGBE_ERR_I2C; 1701 } 1702 1703 ixgbe_lower_i2c_clk(hw, &i2cctl); 1704 1705 /* Minimum low period of clock is 4.7 us */ 1706 usec_delay(IXGBE_I2C_T_LOW); 1707 1708 return status; 1709 } 1710 1711 /** 1712 * ixgbe_clock_in_i2c_bit - Clocks in one bit via I2C data/clock 1713 * @hw: pointer to hardware structure 1714 * @data: read data value 1715 * 1716 * Clocks in one bit via I2C data/clock 1717 **/ 1718 int32_t ixgbe_clock_in_i2c_bit(struct ixgbe_hw *hw, int *data) 1719 { 1720 uint32_t i2cctl = IXGBE_READ_REG(hw, IXGBE_I2CCTL); 1721 1722 DEBUGFUNC("ixgbe_clock_in_i2c_bit"); 1723 1724 ixgbe_raise_i2c_clk(hw, &i2cctl); 1725 1726 /* Minimum high period of clock is 4us */ 1727 usec_delay(IXGBE_I2C_T_HIGH); 1728 1729 i2cctl = IXGBE_READ_REG(hw, IXGBE_I2CCTL); 1730 *data = ixgbe_get_i2c_data(&i2cctl); 1731 1732 ixgbe_lower_i2c_clk(hw, &i2cctl); 1733 1734 /* Minimum low period of clock is 4.7 us */ 1735 usec_delay(IXGBE_I2C_T_LOW); 1736 1737 return IXGBE_SUCCESS; 1738 } 1739 1740 /** 1741 * ixgbe_clock_out_i2c_bit - Clocks in/out one bit via I2C data/clock 1742 * @hw: pointer to hardware structure 1743 * @data: data value to write 1744 * 1745 * Clocks out one bit via I2C data/clock 1746 **/ 1747 int32_t ixgbe_clock_out_i2c_bit(struct ixgbe_hw *hw, int data) 1748 { 1749 int32_t status; 1750 uint32_t i2cctl = IXGBE_READ_REG(hw, IXGBE_I2CCTL); 1751 1752 DEBUGFUNC("ixgbe_clock_out_i2c_bit"); 1753 1754 status = ixgbe_set_i2c_data(hw, &i2cctl, data); 1755 if (status == IXGBE_SUCCESS) { 1756 ixgbe_raise_i2c_clk(hw, &i2cctl); 1757 1758 /* Minimum high period of clock is 4us */ 1759 usec_delay(IXGBE_I2C_T_HIGH); 1760 1761 ixgbe_lower_i2c_clk(hw, &i2cctl); 1762 1763 /* Minimum low period of clock is 4.7 us. 1764 * This also takes care of the data hold time. 1765 */ 1766 usec_delay(IXGBE_I2C_T_LOW); 1767 } else { 1768 status = IXGBE_ERR_I2C; 1769 ERROR_REPORT2(IXGBE_ERROR_INVALID_STATE, 1770 "I2C data was not set to %X\n", data); 1771 } 1772 1773 return status; 1774 } 1775 /** 1776 * ixgbe_raise_i2c_clk - Raises the I2C SCL clock 1777 * @hw: pointer to hardware structure 1778 * @i2cctl: Current value of I2CCTL register 1779 * 1780 * Raises the I2C clock line '0'->'1' 1781 **/ 1782 void ixgbe_raise_i2c_clk(struct ixgbe_hw *hw, uint32_t *i2cctl) 1783 { 1784 int i; 1785 1786 *i2cctl |= IXGBE_I2C_CLK_OUT; 1787 1788 for (i = 0; i < IXGBE_I2C_CLOCK_STRETCHING_TIMEOUT; i++) { 1789 IXGBE_WRITE_REG(hw, IXGBE_I2CCTL, *i2cctl); 1790 IXGBE_WRITE_FLUSH(hw); 1791 /* SCL rise time (1000ns) */ 1792 usec_delay(IXGBE_I2C_T_RISE); 1793 1794 if (IXGBE_READ_REG(hw, IXGBE_I2CCTL) & IXGBE_I2C_CLK_IN) 1795 break; 1796 } 1797 } 1798 1799 /** 1800 * ixgbe_lower_i2c_clk - Lowers the I2C SCL clock 1801 * @hw: pointer to hardware structure 1802 * @i2cctl: Current value of I2CCTL register 1803 * 1804 * Lowers the I2C clock line '1'->'0' 1805 **/ 1806 void ixgbe_lower_i2c_clk(struct ixgbe_hw *hw, uint32_t *i2cctl) 1807 { 1808 1809 DEBUGFUNC("ixgbe_lower_i2c_clk"); 1810 1811 *i2cctl &= ~IXGBE_I2C_CLK_OUT; 1812 1813 IXGBE_WRITE_REG(hw, IXGBE_I2CCTL, *i2cctl); 1814 IXGBE_WRITE_FLUSH(hw); 1815 1816 /* SCL fall time (300ns) */ 1817 usec_delay(IXGBE_I2C_T_FALL); 1818 } 1819 1820 /** 1821 * ixgbe_set_i2c_data - Sets the I2C data bit 1822 * @hw: pointer to hardware structure 1823 * @i2cctl: Current value of I2CCTL register 1824 * @data: I2C data value (0 or 1) to set 1825 * 1826 * Sets the I2C data bit 1827 **/ 1828 int32_t ixgbe_set_i2c_data(struct ixgbe_hw *hw, uint32_t *i2cctl, int data) 1829 { 1830 int32_t status = IXGBE_SUCCESS; 1831 1832 DEBUGFUNC("ixgbe_set_i2c_data"); 1833 1834 if (data) 1835 *i2cctl |= IXGBE_I2C_DATA_OUT; 1836 else 1837 *i2cctl &= ~IXGBE_I2C_DATA_OUT; 1838 1839 IXGBE_WRITE_REG(hw, IXGBE_I2CCTL, *i2cctl); 1840 IXGBE_WRITE_FLUSH(hw); 1841 1842 /* Data rise/fall (1000ns/300ns) and set-up time (250ns) */ 1843 usec_delay(IXGBE_I2C_T_RISE + IXGBE_I2C_T_FALL + IXGBE_I2C_T_SU_DATA); 1844 1845 /* Verify data was set correctly */ 1846 *i2cctl = IXGBE_READ_REG(hw, IXGBE_I2CCTL); 1847 if (data != ixgbe_get_i2c_data(i2cctl)) { 1848 status = IXGBE_ERR_I2C; 1849 ERROR_REPORT2(IXGBE_ERROR_INVALID_STATE, 1850 "Error - I2C data was not set to %X.\n", 1851 data); 1852 } 1853 1854 return status; 1855 } 1856 1857 /** 1858 * ixgbe_get_i2c_data - Reads the I2C SDA data bit 1859 * @hw: pointer to hardware structure 1860 * @i2cctl: Current value of I2CCTL register 1861 * 1862 * Returns the I2C data bit value 1863 **/ 1864 int ixgbe_get_i2c_data(uint32_t *i2cctl) 1865 { 1866 int data; 1867 1868 DEBUGFUNC("ixgbe_get_i2c_data"); 1869 1870 if (*i2cctl & IXGBE_I2C_DATA_IN) 1871 data = 1; 1872 else 1873 data = 0; 1874 1875 return data; 1876 } 1877 1878 /** 1879 * ixgbe_i2c_bus_clear - Clears the I2C bus 1880 * @hw: pointer to hardware structure 1881 * 1882 * Clears the I2C bus by sending nine clock pulses. 1883 * Used when data line is stuck low. 1884 **/ 1885 void ixgbe_i2c_bus_clear(struct ixgbe_hw *hw) 1886 { 1887 uint32_t i2cctl = IXGBE_READ_REG(hw, IXGBE_I2CCTL); 1888 uint32_t i; 1889 1890 DEBUGFUNC("ixgbe_i2c_bus_clear"); 1891 1892 ixgbe_i2c_start(hw); 1893 1894 ixgbe_set_i2c_data(hw, &i2cctl, 1); 1895 1896 for (i = 0; i < 9; i++) { 1897 ixgbe_raise_i2c_clk(hw, &i2cctl); 1898 1899 /* Min high period of clock is 4us */ 1900 usec_delay(IXGBE_I2C_T_HIGH); 1901 1902 ixgbe_lower_i2c_clk(hw, &i2cctl); 1903 1904 /* Min low period of clock is 4.7us*/ 1905 usec_delay(IXGBE_I2C_T_LOW); 1906 } 1907 1908 ixgbe_i2c_start(hw); 1909 1910 /* Put the i2c bus back to default state */ 1911 ixgbe_i2c_stop(hw); 1912 } 1913 1914 /** 1915 * ixgbe_tn_check_overtemp - Checks if an overtemp occurred. 1916 * @hw: pointer to hardware structure 1917 * 1918 * Checks if the LASI temp alarm status was triggered due to overtemp 1919 **/ 1920 int32_t ixgbe_tn_check_overtemp(struct ixgbe_hw *hw) 1921 { 1922 int32_t status = IXGBE_SUCCESS; 1923 uint16_t phy_data = 0; 1924 1925 DEBUGFUNC("ixgbe_tn_check_overtemp"); 1926 1927 if (hw->device_id != IXGBE_DEV_ID_82599_T3_LOM) 1928 goto out; 1929 1930 /* Check that the LASI temp alarm status was triggered */ 1931 hw->phy.ops.read_reg(hw, IXGBE_TN_LASI_STATUS_REG, 1932 IXGBE_MDIO_PMA_PMD_DEV_TYPE, &phy_data); 1933 1934 if (!(phy_data & IXGBE_TN_LASI_STATUS_TEMP_ALARM)) 1935 goto out; 1936 1937 status = IXGBE_ERR_OVERTEMP; 1938 ERROR_REPORT1(IXGBE_ERROR_CAUTION, "Device over temperature"); 1939 out: 1940 return status; 1941 } 1942