1 /* $OpenBSD: ixgbe_82599.c,v 1.12 2015/04/30 14:17:26 jsg Exp $ */ 2 3 /****************************************************************************** 4 5 Copyright (c) 2001-2013, Intel Corporation 6 All rights reserved. 7 8 Redistribution and use in source and binary forms, with or without 9 modification, are permitted provided that the following conditions are met: 10 11 1. Redistributions of source code must retain the above copyright notice, 12 this list of conditions and the following disclaimer. 13 14 2. Redistributions in binary form must reproduce the above copyright 15 notice, this list of conditions and the following disclaimer in the 16 documentation and/or other materials provided with the distribution. 17 18 3. Neither the name of the Intel Corporation nor the names of its 19 contributors may be used to endorse or promote products derived from 20 this software without specific prior written permission. 21 22 THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS" 23 AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE 24 IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE 25 ARE DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT OWNER OR CONTRIBUTORS BE 26 LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR 27 CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF 28 SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS 29 INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN 30 CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) 31 ARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE 32 POSSIBILITY OF SUCH DAMAGE. 33 34 ******************************************************************************/ 35 /* FreeBSD: src/sys/dev/ixgbe/ixgbe_82599.c 251964 Jun 18 21:28:19 2013 UTC */ 36 37 #include <dev/pci/ixgbe.h> 38 #include <dev/pci/ixgbe_type.h> 39 40 int32_t ixgbe_get_link_capabilities_82599(struct ixgbe_hw *hw, 41 ixgbe_link_speed *speed, 42 bool *autoneg); 43 enum ixgbe_media_type ixgbe_get_media_type_82599(struct ixgbe_hw *hw); 44 void ixgbe_disable_tx_laser_multispeed_fiber(struct ixgbe_hw *hw); 45 void ixgbe_enable_tx_laser_multispeed_fiber(struct ixgbe_hw *hw); 46 void ixgbe_flap_tx_laser_multispeed_fiber(struct ixgbe_hw *hw); 47 void ixgbe_set_fiber_fixed_speed(struct ixgbe_hw *hw, 48 ixgbe_link_speed speed); 49 int32_t ixgbe_setup_mac_link_multispeed_fiber(struct ixgbe_hw *hw, 50 ixgbe_link_speed speed, 51 bool autoneg_wait_to_complete); 52 int32_t ixgbe_setup_mac_link_smartspeed(struct ixgbe_hw *hw, 53 ixgbe_link_speed speed, 54 bool autoneg_wait_to_complete); 55 int32_t ixgbe_start_mac_link_82599(struct ixgbe_hw *hw, 56 bool autoneg_wait_to_complete); 57 void ixgbe_stop_mac_link_on_d3_82599(struct ixgbe_hw *hw); 58 int32_t ixgbe_setup_mac_link_82599(struct ixgbe_hw *hw, 59 ixgbe_link_speed speed, 60 bool autoneg_wait_to_complete); 61 int32_t ixgbe_setup_copper_link_82599(struct ixgbe_hw *hw, 62 ixgbe_link_speed speed, 63 bool autoneg_wait_to_complete); 64 int32_t ixgbe_setup_sfp_modules_82599(struct ixgbe_hw *hw); 65 void ixgbe_init_mac_link_ops_82599(struct ixgbe_hw *hw); 66 int32_t ixgbe_reset_hw_82599(struct ixgbe_hw *hw); 67 int32_t ixgbe_read_analog_reg8_82599(struct ixgbe_hw *hw, uint32_t reg, 68 uint8_t *val); 69 int32_t ixgbe_write_analog_reg8_82599(struct ixgbe_hw *hw, uint32_t reg, 70 uint8_t val); 71 int32_t ixgbe_start_hw_82599(struct ixgbe_hw *hw); 72 int32_t ixgbe_identify_phy_82599(struct ixgbe_hw *hw); 73 int32_t ixgbe_init_phy_ops_82599(struct ixgbe_hw *hw); 74 uint32_t ixgbe_get_supported_physical_layer_82599(struct ixgbe_hw *hw); 75 int32_t ixgbe_enable_rx_dma_82599(struct ixgbe_hw *hw, uint32_t regval); 76 int32_t ixgbe_verify_fw_version_82599(struct ixgbe_hw *hw); 77 bool ixgbe_verify_lesm_fw_enabled_82599(struct ixgbe_hw *hw); 78 int32_t ixgbe_read_eeprom_82599(struct ixgbe_hw *hw, 79 uint16_t offset, uint16_t *data); 80 int32_t ixgbe_reset_pipeline_82599(struct ixgbe_hw *hw); 81 int32_t ixgbe_blink_led_start_82599(struct ixgbe_hw *hw, uint32_t index); 82 int32_t ixgbe_blink_led_stop_82599(struct ixgbe_hw *hw, uint32_t index); 83 84 static bool ixgbe_mng_enabled(struct ixgbe_hw *hw) 85 { 86 uint32_t fwsm, manc, factps; 87 88 fwsm = IXGBE_READ_REG(hw, IXGBE_FWSM); 89 if ((fwsm & IXGBE_FWSM_MODE_MASK) != IXGBE_FWSM_FW_MODE_PT) 90 return FALSE; 91 92 manc = IXGBE_READ_REG(hw, IXGBE_MANC); 93 if (!(manc & IXGBE_MANC_RCV_TCO_EN)) 94 return FALSE; 95 96 factps = IXGBE_READ_REG(hw, IXGBE_FACTPS); 97 if (factps & IXGBE_FACTPS_MNGCG) 98 return FALSE; 99 100 return TRUE; 101 } 102 103 void ixgbe_init_mac_link_ops_82599(struct ixgbe_hw *hw) 104 { 105 struct ixgbe_mac_info *mac = &hw->mac; 106 107 DEBUGFUNC("ixgbe_init_mac_link_ops_82599"); 108 109 /* 110 * enable the laser control functions for SFP+ fiber 111 * and MNG not enabled 112 */ 113 if ((mac->ops.get_media_type(hw) == ixgbe_media_type_fiber) && 114 !hw->mng_fw_enabled) { 115 mac->ops.disable_tx_laser = 116 &ixgbe_disable_tx_laser_multispeed_fiber; 117 mac->ops.enable_tx_laser = 118 &ixgbe_enable_tx_laser_multispeed_fiber; 119 mac->ops.flap_tx_laser = &ixgbe_flap_tx_laser_multispeed_fiber; 120 121 } else { 122 mac->ops.disable_tx_laser = NULL; 123 mac->ops.enable_tx_laser = NULL; 124 mac->ops.flap_tx_laser = NULL; 125 } 126 127 if (hw->phy.multispeed_fiber) { 128 /* Set up dual speed SFP+ support */ 129 mac->ops.setup_link = &ixgbe_setup_mac_link_multispeed_fiber; 130 } else { 131 if ((ixgbe_get_media_type(hw) == ixgbe_media_type_backplane) && 132 (hw->phy.smart_speed == ixgbe_smart_speed_auto || 133 hw->phy.smart_speed == ixgbe_smart_speed_on) && 134 !ixgbe_verify_lesm_fw_enabled_82599(hw)) { 135 mac->ops.setup_link = &ixgbe_setup_mac_link_smartspeed; 136 } else { 137 mac->ops.setup_link = &ixgbe_setup_mac_link_82599; 138 } 139 } 140 } 141 142 /** 143 * ixgbe_init_phy_ops_82599 - PHY/SFP specific init 144 * @hw: pointer to hardware structure 145 * 146 * Initialize any function pointers that were not able to be 147 * set during init_shared_code because the PHY/SFP type was 148 * not known. Perform the SFP init if necessary. 149 * 150 **/ 151 int32_t ixgbe_init_phy_ops_82599(struct ixgbe_hw *hw) 152 { 153 struct ixgbe_mac_info *mac = &hw->mac; 154 struct ixgbe_phy_info *phy = &hw->phy; 155 int32_t ret_val = IXGBE_SUCCESS; 156 157 DEBUGFUNC("ixgbe_init_phy_ops_82599"); 158 159 /* Identify the PHY or SFP module */ 160 ret_val = phy->ops.identify(hw); 161 if (ret_val == IXGBE_ERR_SFP_NOT_SUPPORTED) 162 goto init_phy_ops_out; 163 164 /* Setup function pointers based on detected SFP module and speeds */ 165 ixgbe_init_mac_link_ops_82599(hw); 166 if (hw->phy.sfp_type != ixgbe_sfp_type_unknown) 167 hw->phy.ops.reset = NULL; 168 169 /* If copper media, overwrite with copper function pointers */ 170 if (mac->ops.get_media_type(hw) == ixgbe_media_type_copper) { 171 mac->ops.setup_link = &ixgbe_setup_copper_link_82599; 172 mac->ops.get_link_capabilities = 173 &ixgbe_get_copper_link_capabilities_generic; 174 } 175 176 /* Set necessary function pointers based on phy type */ 177 switch (hw->phy.type) { 178 case ixgbe_phy_tn: 179 phy->ops.setup_link = &ixgbe_setup_phy_link_tnx; 180 phy->ops.check_link = &ixgbe_check_phy_link_tnx; 181 phy->ops.get_firmware_version = 182 &ixgbe_get_phy_firmware_version_tnx; 183 break; 184 default: 185 break; 186 } 187 init_phy_ops_out: 188 return ret_val; 189 } 190 191 int32_t ixgbe_setup_sfp_modules_82599(struct ixgbe_hw *hw) 192 { 193 int32_t ret_val = IXGBE_SUCCESS; 194 uint16_t list_offset, data_offset, data_value; 195 bool got_lock = FALSE; 196 197 DEBUGFUNC("ixgbe_setup_sfp_modules_82599"); 198 199 if (hw->phy.sfp_type != ixgbe_sfp_type_unknown) { 200 ixgbe_init_mac_link_ops_82599(hw); 201 202 hw->phy.ops.reset = NULL; 203 204 ret_val = ixgbe_get_sfp_init_sequence_offsets(hw, &list_offset, 205 &data_offset); 206 if (ret_val != IXGBE_SUCCESS) 207 goto setup_sfp_out; 208 209 /* PHY config will finish before releasing the semaphore */ 210 ret_val = hw->mac.ops.acquire_swfw_sync(hw, 211 IXGBE_GSSR_MAC_CSR_SM); 212 if (ret_val != IXGBE_SUCCESS) { 213 ret_val = IXGBE_ERR_SWFW_SYNC; 214 goto setup_sfp_out; 215 } 216 217 if (hw->eeprom.ops.read(hw, ++data_offset, &data_value)) 218 goto setup_sfp_err; 219 while (data_value != 0xffff) { 220 IXGBE_WRITE_REG(hw, IXGBE_CORECTL, data_value); 221 IXGBE_WRITE_FLUSH(hw); 222 if (hw->eeprom.ops.read(hw, ++data_offset, &data_value)) 223 goto setup_sfp_err; 224 } 225 226 /* Release the semaphore */ 227 hw->mac.ops.release_swfw_sync(hw, IXGBE_GSSR_MAC_CSR_SM); 228 /* Delay obtaining semaphore again to allow FW access */ 229 msec_delay(hw->eeprom.semaphore_delay); 230 231 /* Need SW/FW semaphore around AUTOC writes if LESM on, 232 * likewise reset_pipeline requires lock as it also writes 233 * AUTOC. 234 */ 235 if (ixgbe_verify_lesm_fw_enabled_82599(hw)) { 236 ret_val = hw->mac.ops.acquire_swfw_sync(hw, 237 IXGBE_GSSR_MAC_CSR_SM); 238 if (ret_val != IXGBE_SUCCESS) { 239 ret_val = IXGBE_ERR_SWFW_SYNC; 240 goto setup_sfp_out; 241 } 242 243 got_lock = TRUE; 244 } 245 246 /* Restart DSP and set SFI mode */ 247 IXGBE_WRITE_REG(hw, IXGBE_AUTOC, ((hw->mac.orig_autoc) | 248 IXGBE_AUTOC_LMS_10G_SERIAL)); 249 hw->mac.cached_autoc = IXGBE_READ_REG(hw, IXGBE_AUTOC); 250 ret_val = ixgbe_reset_pipeline_82599(hw); 251 252 if (got_lock) { 253 hw->mac.ops.release_swfw_sync(hw, 254 IXGBE_GSSR_MAC_CSR_SM); 255 got_lock = FALSE; 256 } 257 258 if (ret_val) { 259 DEBUGOUT("sfp module setup not complete\n"); 260 ret_val = IXGBE_ERR_SFP_SETUP_NOT_COMPLETE; 261 goto setup_sfp_out; 262 } 263 264 } 265 266 setup_sfp_out: 267 return ret_val; 268 269 setup_sfp_err: 270 /* Release the semaphore */ 271 hw->mac.ops.release_swfw_sync(hw, IXGBE_GSSR_MAC_CSR_SM); 272 /* Delay obtaining semaphore again to allow FW access */ 273 msec_delay(hw->eeprom.semaphore_delay); 274 ERROR_REPORT2(IXGBE_ERROR_INVALID_STATE, 275 "eeprom read at offset %d failed", data_offset); 276 return IXGBE_ERR_PHY; 277 } 278 279 /** 280 * ixgbe_init_ops_82599 - Inits func ptrs and MAC type 281 * @hw: pointer to hardware structure 282 * 283 * Initialize the function pointers and assign the MAC type for 82599. 284 * Does not touch the hardware. 285 **/ 286 287 int32_t ixgbe_init_ops_82599(struct ixgbe_hw *hw) 288 { 289 struct ixgbe_mac_info *mac = &hw->mac; 290 struct ixgbe_phy_info *phy = &hw->phy; 291 struct ixgbe_eeprom_info *eeprom = &hw->eeprom; 292 int32_t ret_val; 293 294 DEBUGFUNC("ixgbe_init_ops_82599"); 295 296 ixgbe_init_phy_ops_generic(hw); 297 ret_val = ixgbe_init_ops_generic(hw); 298 299 /* PHY */ 300 phy->ops.identify = &ixgbe_identify_phy_82599; 301 phy->ops.init = &ixgbe_init_phy_ops_82599; 302 303 /* MAC */ 304 mac->ops.reset_hw = &ixgbe_reset_hw_82599; 305 mac->ops.enable_relaxed_ordering = &ixgbe_enable_relaxed_ordering_gen2; 306 mac->ops.get_media_type = &ixgbe_get_media_type_82599; 307 mac->ops.get_supported_physical_layer = 308 &ixgbe_get_supported_physical_layer_82599; 309 mac->ops.disable_sec_rx_path = &ixgbe_disable_sec_rx_path_generic; 310 mac->ops.enable_sec_rx_path = &ixgbe_enable_sec_rx_path_generic; 311 mac->ops.enable_rx_dma = &ixgbe_enable_rx_dma_82599; 312 mac->ops.read_analog_reg8 = &ixgbe_read_analog_reg8_82599; 313 mac->ops.write_analog_reg8 = &ixgbe_write_analog_reg8_82599; 314 mac->ops.start_hw = &ixgbe_start_hw_82599; 315 316 /* RAR, Multicast, VLAN */ 317 mac->ops.set_vmdq = &ixgbe_set_vmdq_generic; 318 mac->ops.clear_vmdq = &ixgbe_clear_vmdq_generic; 319 mac->ops.insert_mac_addr = &ixgbe_insert_mac_addr_generic; 320 mac->rar_highwater = 1; 321 mac->ops.set_vfta = &ixgbe_set_vfta_generic; 322 mac->ops.set_vlvf = &ixgbe_set_vlvf_generic; 323 mac->ops.clear_vfta = &ixgbe_clear_vfta_generic; 324 mac->ops.init_uta_tables = &ixgbe_init_uta_tables_generic; 325 mac->ops.setup_sfp = &ixgbe_setup_sfp_modules_82599; 326 327 mac->ops.verify_lesm_fw_enabled = &ixgbe_verify_lesm_fw_enabled_82599; 328 mac->ops.reset_pipeline = &ixgbe_reset_pipeline_82599; 329 mac->ops.stop_mac_link_on_d3 = &ixgbe_stop_mac_link_on_d3_82599; 330 331 /* Link */ 332 mac->ops.get_link_capabilities = &ixgbe_get_link_capabilities_82599; 333 mac->ops.check_link = &ixgbe_check_mac_link_generic; 334 ixgbe_init_mac_link_ops_82599(hw); 335 336 mac->mcft_size = 128; 337 mac->vft_size = 128; 338 mac->num_rar_entries = 128; 339 mac->rx_pb_size = 512; 340 mac->max_tx_queues = 128; 341 mac->max_rx_queues = 128; 342 mac->max_msix_vectors = 0 /*ixgbe_get_pcie_msix_count_generic(hw)*/; 343 344 hw->mbx.ops.init_params = ixgbe_init_mbx_params_pf; 345 346 /* EEPROM */ 347 eeprom->ops.read = &ixgbe_read_eeprom_82599; 348 349 /* Cache if MNG FW is up */ 350 hw->mng_fw_enabled = ixgbe_mng_enabled(hw); 351 352 return ret_val; 353 } 354 355 /** 356 * ixgbe_get_link_capabilities_82599 - Determines link capabilities 357 * @hw: pointer to hardware structure 358 * @speed: pointer to link speed 359 * @autoneg: TRUE when autoneg or autotry is enabled 360 * 361 * Determines the link capabilities by reading the AUTOC register. 362 **/ 363 int32_t ixgbe_get_link_capabilities_82599(struct ixgbe_hw *hw, 364 ixgbe_link_speed *speed, 365 bool *autoneg) 366 { 367 int32_t status = IXGBE_SUCCESS; 368 uint32_t autoc = 0; 369 370 DEBUGFUNC("ixgbe_get_link_capabilities_82599"); 371 372 /* Check if 1G SFP module. */ 373 if (hw->phy.sfp_type == ixgbe_sfp_type_1g_cu_core0 || 374 hw->phy.sfp_type == ixgbe_sfp_type_1g_cu_core1 || 375 hw->phy.sfp_type == ixgbe_sfp_type_1g_lx_core0 || 376 hw->phy.sfp_type == ixgbe_sfp_type_1g_lx_core1 || 377 hw->phy.sfp_type == ixgbe_sfp_type_1g_sx_core0 || 378 hw->phy.sfp_type == ixgbe_sfp_type_1g_sx_core1) { 379 *speed = IXGBE_LINK_SPEED_1GB_FULL; 380 *autoneg = TRUE; 381 goto out; 382 } 383 384 /* 385 * Determine link capabilities based on the stored value of AUTOC, 386 * which represents EEPROM defaults. If AUTOC value has not 387 * been stored, use the current register values. 388 */ 389 if (hw->mac.orig_link_settings_stored) 390 autoc = hw->mac.orig_autoc; 391 else 392 autoc = IXGBE_READ_REG(hw, IXGBE_AUTOC); 393 394 switch (autoc & IXGBE_AUTOC_LMS_MASK) { 395 case IXGBE_AUTOC_LMS_1G_LINK_NO_AN: 396 *speed = IXGBE_LINK_SPEED_1GB_FULL; 397 *autoneg = FALSE; 398 break; 399 400 case IXGBE_AUTOC_LMS_10G_LINK_NO_AN: 401 *speed = IXGBE_LINK_SPEED_10GB_FULL; 402 *autoneg = FALSE; 403 break; 404 405 case IXGBE_AUTOC_LMS_1G_AN: 406 *speed = IXGBE_LINK_SPEED_1GB_FULL; 407 *autoneg = TRUE; 408 break; 409 410 case IXGBE_AUTOC_LMS_10G_SERIAL: 411 *speed = IXGBE_LINK_SPEED_10GB_FULL; 412 *autoneg = FALSE; 413 break; 414 415 case IXGBE_AUTOC_LMS_KX4_KX_KR: 416 case IXGBE_AUTOC_LMS_KX4_KX_KR_1G_AN: 417 *speed = IXGBE_LINK_SPEED_UNKNOWN; 418 if (autoc & IXGBE_AUTOC_KR_SUPP) 419 *speed |= IXGBE_LINK_SPEED_10GB_FULL; 420 if (autoc & IXGBE_AUTOC_KX4_SUPP) 421 *speed |= IXGBE_LINK_SPEED_10GB_FULL; 422 if (autoc & IXGBE_AUTOC_KX_SUPP) 423 *speed |= IXGBE_LINK_SPEED_1GB_FULL; 424 *autoneg = TRUE; 425 break; 426 427 case IXGBE_AUTOC_LMS_KX4_KX_KR_SGMII: 428 *speed = IXGBE_LINK_SPEED_100_FULL; 429 if (autoc & IXGBE_AUTOC_KR_SUPP) 430 *speed |= IXGBE_LINK_SPEED_10GB_FULL; 431 if (autoc & IXGBE_AUTOC_KX4_SUPP) 432 *speed |= IXGBE_LINK_SPEED_10GB_FULL; 433 if (autoc & IXGBE_AUTOC_KX_SUPP) 434 *speed |= IXGBE_LINK_SPEED_1GB_FULL; 435 *autoneg = TRUE; 436 break; 437 438 case IXGBE_AUTOC_LMS_SGMII_1G_100M: 439 *speed = IXGBE_LINK_SPEED_1GB_FULL | IXGBE_LINK_SPEED_100_FULL; 440 *autoneg = FALSE; 441 break; 442 443 default: 444 status = IXGBE_ERR_LINK_SETUP; 445 goto out; 446 break; 447 } 448 449 if (hw->phy.multispeed_fiber) { 450 *speed |= IXGBE_LINK_SPEED_10GB_FULL | 451 IXGBE_LINK_SPEED_1GB_FULL; 452 *autoneg = TRUE; 453 } 454 455 out: 456 return status; 457 } 458 459 /** 460 * ixgbe_get_media_type_82599 - Get media type 461 * @hw: pointer to hardware structure 462 * 463 * Returns the media type (fiber, copper, backplane) 464 **/ 465 enum ixgbe_media_type ixgbe_get_media_type_82599(struct ixgbe_hw *hw) 466 { 467 enum ixgbe_media_type media_type; 468 469 DEBUGFUNC("ixgbe_get_media_type_82599"); 470 471 /* Detect if there is a copper PHY attached. */ 472 switch (hw->phy.type) { 473 case ixgbe_phy_cu_unknown: 474 case ixgbe_phy_tn: 475 media_type = ixgbe_media_type_copper; 476 goto out; 477 default: 478 break; 479 } 480 481 switch (hw->device_id) { 482 case IXGBE_DEV_ID_82599_KX4: 483 case IXGBE_DEV_ID_82599_KX4_MEZZ: 484 case IXGBE_DEV_ID_82599_COMBO_BACKPLANE: 485 case IXGBE_DEV_ID_82599_KR: 486 case IXGBE_DEV_ID_82599_BACKPLANE_FCOE: 487 case IXGBE_DEV_ID_82599_XAUI_LOM: 488 /* Default device ID is mezzanine card KX/KX4 */ 489 media_type = ixgbe_media_type_backplane; 490 break; 491 case IXGBE_DEV_ID_82599_SFP: 492 case IXGBE_DEV_ID_82599_SFP_FCOE: 493 case IXGBE_DEV_ID_82599_SFP_EM: 494 case IXGBE_DEV_ID_82599_SFP_SF2: 495 case IXGBE_DEV_ID_82599_SFP_SF_QP: 496 case IXGBE_DEV_ID_82599EN_SFP: 497 media_type = ixgbe_media_type_fiber; 498 break; 499 case IXGBE_DEV_ID_82599_CX4: 500 media_type = ixgbe_media_type_cx4; 501 break; 502 case IXGBE_DEV_ID_82599_T3_LOM: 503 media_type = ixgbe_media_type_copper; 504 break; 505 case IXGBE_DEV_ID_82599_BYPASS: 506 media_type = ixgbe_media_type_fiber_fixed; 507 hw->phy.multispeed_fiber = TRUE; 508 break; 509 default: 510 media_type = ixgbe_media_type_unknown; 511 break; 512 } 513 out: 514 return media_type; 515 } 516 517 /** 518 * ixgbe_stop_mac_link_on_d3_82599 - Disables link on D3 519 * @hw: pointer to hardware structure 520 * 521 * Disables link during D3 power down sequence. 522 * 523 **/ 524 void ixgbe_stop_mac_link_on_d3_82599(struct ixgbe_hw *hw) 525 { 526 uint32_t autoc2_reg; 527 uint16_t ee_ctrl_2 = 0; 528 529 DEBUGFUNC("ixgbe_stop_mac_link_on_d3_82599"); 530 ixgbe_read_eeprom_82599(hw, IXGBE_EEPROM_CTRL_2, &ee_ctrl_2); 531 532 if (!hw->mng_fw_enabled && ee_ctrl_2 & IXGBE_EEPROM_CCD_BIT) { 533 autoc2_reg = IXGBE_READ_REG(hw, IXGBE_AUTOC2); 534 autoc2_reg |= IXGBE_AUTOC2_LINK_DISABLE_ON_D3_MASK; 535 IXGBE_WRITE_REG(hw, IXGBE_AUTOC2, autoc2_reg); 536 } 537 } 538 539 /** 540 * ixgbe_start_mac_link_82599 - Setup MAC link settings 541 * @hw: pointer to hardware structure 542 * @autoneg_wait_to_complete: TRUE when waiting for completion is needed 543 * 544 * Configures link settings based on values in the ixgbe_hw struct. 545 * Restarts the link. Performs autonegotiation if needed. 546 **/ 547 int32_t ixgbe_start_mac_link_82599(struct ixgbe_hw *hw, 548 bool autoneg_wait_to_complete) 549 { 550 uint32_t autoc_reg; 551 uint32_t links_reg; 552 uint32_t i; 553 int32_t status = IXGBE_SUCCESS; 554 bool got_lock = FALSE; 555 556 DEBUGFUNC("ixgbe_start_mac_link_82599"); 557 558 559 /* reset_pipeline requires us to hold this lock as it writes to 560 * AUTOC. 561 */ 562 if (ixgbe_verify_lesm_fw_enabled_82599(hw)) { 563 status = hw->mac.ops.acquire_swfw_sync(hw, 564 IXGBE_GSSR_MAC_CSR_SM); 565 if (status != IXGBE_SUCCESS) 566 goto out; 567 568 got_lock = TRUE; 569 } 570 571 /* Restart link */ 572 ixgbe_reset_pipeline_82599(hw); 573 574 if (got_lock) 575 hw->mac.ops.release_swfw_sync(hw, IXGBE_GSSR_MAC_CSR_SM); 576 577 /* Only poll for autoneg to complete if specified to do so */ 578 if (autoneg_wait_to_complete) { 579 autoc_reg = IXGBE_READ_REG(hw, IXGBE_AUTOC); 580 if ((autoc_reg & IXGBE_AUTOC_LMS_MASK) == 581 IXGBE_AUTOC_LMS_KX4_KX_KR || 582 (autoc_reg & IXGBE_AUTOC_LMS_MASK) == 583 IXGBE_AUTOC_LMS_KX4_KX_KR_1G_AN || 584 (autoc_reg & IXGBE_AUTOC_LMS_MASK) == 585 IXGBE_AUTOC_LMS_KX4_KX_KR_SGMII) { 586 links_reg = 0; /* Just in case Autoneg time = 0 */ 587 for (i = 0; i < IXGBE_AUTO_NEG_TIME; i++) { 588 links_reg = IXGBE_READ_REG(hw, IXGBE_LINKS); 589 if (links_reg & IXGBE_LINKS_KX_AN_COMP) 590 break; 591 msec_delay(100); 592 } 593 if (!(links_reg & IXGBE_LINKS_KX_AN_COMP)) { 594 status = IXGBE_ERR_AUTONEG_NOT_COMPLETE; 595 DEBUGOUT("Autoneg did not complete.\n"); 596 } 597 } 598 } 599 600 /* Add delay to filter out noises during initial link setup */ 601 msec_delay(50); 602 603 out: 604 return status; 605 } 606 607 /** 608 * ixgbe_disable_tx_laser_multispeed_fiber - Disable Tx laser 609 * @hw: pointer to hardware structure 610 * 611 * The base drivers may require better control over SFP+ module 612 * PHY states. This includes selectively shutting down the Tx 613 * laser on the PHY, effectively halting physical link. 614 **/ 615 void ixgbe_disable_tx_laser_multispeed_fiber(struct ixgbe_hw *hw) 616 { 617 uint32_t esdp_reg = IXGBE_READ_REG(hw, IXGBE_ESDP); 618 619 /* Disable tx laser; allow 100us to go dark per spec */ 620 esdp_reg |= IXGBE_ESDP_SDP3; 621 IXGBE_WRITE_REG(hw, IXGBE_ESDP, esdp_reg); 622 IXGBE_WRITE_FLUSH(hw); 623 usec_delay(100); 624 } 625 626 /** 627 * ixgbe_enable_tx_laser_multispeed_fiber - Enable Tx laser 628 * @hw: pointer to hardware structure 629 * 630 * The base drivers may require better control over SFP+ module 631 * PHY states. This includes selectively turning on the Tx 632 * laser on the PHY, effectively starting physical link. 633 **/ 634 void ixgbe_enable_tx_laser_multispeed_fiber(struct ixgbe_hw *hw) 635 { 636 uint32_t esdp_reg = IXGBE_READ_REG(hw, IXGBE_ESDP); 637 638 /* Enable tx laser; allow 100ms to light up */ 639 esdp_reg &= ~IXGBE_ESDP_SDP3; 640 IXGBE_WRITE_REG(hw, IXGBE_ESDP, esdp_reg); 641 IXGBE_WRITE_FLUSH(hw); 642 msec_delay(100); 643 } 644 645 /** 646 * ixgbe_flap_tx_laser_multispeed_fiber - Flap Tx laser 647 * @hw: pointer to hardware structure 648 * 649 * When the driver changes the link speeds that it can support, 650 * it sets autotry_restart to TRUE to indicate that we need to 651 * initiate a new autotry session with the link partner. To do 652 * so, we set the speed then disable and re-enable the tx laser, to 653 * alert the link partner that it also needs to restart autotry on its 654 * end. This is consistent with TRUE clause 37 autoneg, which also 655 * involves a loss of signal. 656 **/ 657 void ixgbe_flap_tx_laser_multispeed_fiber(struct ixgbe_hw *hw) 658 { 659 DEBUGFUNC("ixgbe_flap_tx_laser_multispeed_fiber"); 660 661 if (hw->mac.autotry_restart) { 662 ixgbe_disable_tx_laser_multispeed_fiber(hw); 663 ixgbe_enable_tx_laser_multispeed_fiber(hw); 664 hw->mac.autotry_restart = FALSE; 665 } 666 } 667 668 /** 669 * ixgbe_set_fiber_fixed_speed - Set module link speed for fixed fiber 670 * @hw: pointer to hardware structure 671 * @speed: link speed to set 672 * 673 * We set the module speed differently for fixed fiber. For other 674 * multi-speed devices we don't have an error value so here if we 675 * detect an error we just log it and exit. 676 */ 677 void ixgbe_set_fiber_fixed_speed(struct ixgbe_hw *hw, 678 ixgbe_link_speed speed) 679 { 680 int32_t status; 681 uint8_t rs, eeprom_data; 682 683 switch (speed) { 684 case IXGBE_LINK_SPEED_10GB_FULL: 685 /* one bit mask same as setting on */ 686 rs = IXGBE_SFF_SOFT_RS_SELECT_10G; 687 break; 688 case IXGBE_LINK_SPEED_1GB_FULL: 689 rs = IXGBE_SFF_SOFT_RS_SELECT_1G; 690 break; 691 default: 692 DEBUGOUT("Invalid fixed module speed\n"); 693 return; 694 } 695 696 /* Set RS0 */ 697 status = hw->phy.ops.read_i2c_byte(hw, IXGBE_SFF_SFF_8472_OSCB, 698 IXGBE_I2C_EEPROM_DEV_ADDR2, 699 &eeprom_data); 700 if (status) { 701 DEBUGOUT("Failed to read Rx Rate Select RS0\n"); 702 goto out; 703 } 704 705 eeprom_data = (eeprom_data & ~IXGBE_SFF_SOFT_RS_SELECT_MASK) & rs; 706 707 status = hw->phy.ops.write_i2c_byte(hw, IXGBE_SFF_SFF_8472_OSCB, 708 IXGBE_I2C_EEPROM_DEV_ADDR2, 709 eeprom_data); 710 if (status) { 711 DEBUGOUT("Failed to write Rx Rate Select RS0\n"); 712 goto out; 713 } 714 715 /* Set RS1 */ 716 status = hw->phy.ops.read_i2c_byte(hw, IXGBE_SFF_SFF_8472_ESCB, 717 IXGBE_I2C_EEPROM_DEV_ADDR2, 718 &eeprom_data); 719 if (status) { 720 DEBUGOUT("Failed to read Rx Rate Select RS1\n"); 721 goto out; 722 } 723 724 eeprom_data = (eeprom_data & ~IXGBE_SFF_SOFT_RS_SELECT_MASK) & rs; 725 726 status = hw->phy.ops.write_i2c_byte(hw, IXGBE_SFF_SFF_8472_ESCB, 727 IXGBE_I2C_EEPROM_DEV_ADDR2, 728 eeprom_data); 729 if (status) { 730 DEBUGOUT("Failed to write Rx Rate Select RS1\n"); 731 goto out; 732 } 733 out: 734 return; 735 } 736 737 /** 738 * ixgbe_setup_mac_link_multispeed_fiber - Set MAC link speed 739 * @hw: pointer to hardware structure 740 * @speed: new link speed 741 * @autoneg_wait_to_complete: TRUE when waiting for completion is needed 742 * 743 * Set the link speed in the AUTOC register and restarts link. 744 **/ 745 int32_t ixgbe_setup_mac_link_multispeed_fiber(struct ixgbe_hw *hw, 746 ixgbe_link_speed speed, 747 bool autoneg_wait_to_complete) 748 { 749 int32_t status = IXGBE_SUCCESS; 750 ixgbe_link_speed link_speed = IXGBE_LINK_SPEED_UNKNOWN; 751 ixgbe_link_speed highest_link_speed = IXGBE_LINK_SPEED_UNKNOWN; 752 uint32_t speedcnt = 0; 753 uint32_t esdp_reg = IXGBE_READ_REG(hw, IXGBE_ESDP); 754 uint32_t i = 0; 755 bool autoneg, link_up = FALSE; 756 757 DEBUGFUNC("ixgbe_setup_mac_link_multispeed_fiber"); 758 759 /* Mask off requested but non-supported speeds */ 760 status = ixgbe_get_link_capabilities_82599(hw, &link_speed, &autoneg); 761 if (status != IXGBE_SUCCESS) 762 return status; 763 764 speed &= link_speed; 765 766 /* 767 * Try each speed one by one, highest priority first. We do this in 768 * software because 10gb fiber doesn't support speed autonegotiation. 769 */ 770 if (speed & IXGBE_LINK_SPEED_10GB_FULL) { 771 speedcnt++; 772 highest_link_speed = IXGBE_LINK_SPEED_10GB_FULL; 773 774 /* If we already have link at this speed, just jump out */ 775 status = ixgbe_check_link(hw, &link_speed, &link_up, FALSE); 776 if (status != IXGBE_SUCCESS) 777 return status; 778 779 if ((link_speed == IXGBE_LINK_SPEED_10GB_FULL) && link_up) 780 goto out; 781 782 /* Set the module link speed */ 783 if (hw->phy.media_type == ixgbe_media_type_fiber_fixed) { 784 ixgbe_set_fiber_fixed_speed(hw, 785 IXGBE_LINK_SPEED_10GB_FULL); 786 } else { 787 esdp_reg |= (IXGBE_ESDP_SDP5_DIR | IXGBE_ESDP_SDP5); 788 IXGBE_WRITE_REG(hw, IXGBE_ESDP, esdp_reg); 789 IXGBE_WRITE_FLUSH(hw); 790 } 791 792 /* Allow module to change analog characteristics (1G->10G) */ 793 msec_delay(40); 794 795 status = ixgbe_setup_mac_link_82599(hw, 796 IXGBE_LINK_SPEED_10GB_FULL, 797 autoneg_wait_to_complete); 798 if (status != IXGBE_SUCCESS) 799 return status; 800 801 /* Flap the tx laser if it has not already been done */ 802 ixgbe_flap_tx_laser(hw); 803 804 /* 805 * Wait for the controller to acquire link. Per IEEE 802.3ap, 806 * Section 73.10.2, we may have to wait up to 500ms if KR is 807 * attempted. 82599 uses the same timing for 10g SFI. 808 */ 809 for (i = 0; i < 5; i++) { 810 /* Wait for the link partner to also set speed */ 811 msec_delay(100); 812 813 /* If we have link, just jump out */ 814 status = ixgbe_check_link(hw, &link_speed, 815 &link_up, FALSE); 816 if (status != IXGBE_SUCCESS) 817 return status; 818 819 if (link_up) 820 goto out; 821 } 822 } 823 824 if (speed & IXGBE_LINK_SPEED_1GB_FULL) { 825 speedcnt++; 826 if (highest_link_speed == IXGBE_LINK_SPEED_UNKNOWN) 827 highest_link_speed = IXGBE_LINK_SPEED_1GB_FULL; 828 829 /* If we already have link at this speed, just jump out */ 830 status = ixgbe_check_link(hw, &link_speed, &link_up, FALSE); 831 if (status != IXGBE_SUCCESS) 832 return status; 833 834 if ((link_speed == IXGBE_LINK_SPEED_1GB_FULL) && link_up) 835 goto out; 836 837 /* Set the module link speed */ 838 if (hw->phy.media_type == ixgbe_media_type_fiber_fixed) { 839 ixgbe_set_fiber_fixed_speed(hw, 840 IXGBE_LINK_SPEED_1GB_FULL); 841 } else { 842 esdp_reg &= ~IXGBE_ESDP_SDP5; 843 esdp_reg |= IXGBE_ESDP_SDP5_DIR; 844 IXGBE_WRITE_REG(hw, IXGBE_ESDP, esdp_reg); 845 IXGBE_WRITE_FLUSH(hw); 846 } 847 848 /* Allow module to change analog characteristics (10G->1G) */ 849 msec_delay(40); 850 851 status = ixgbe_setup_mac_link_82599(hw, 852 IXGBE_LINK_SPEED_1GB_FULL, 853 autoneg_wait_to_complete); 854 if (status != IXGBE_SUCCESS) 855 return status; 856 857 /* Flap the tx laser if it has not already been done */ 858 ixgbe_flap_tx_laser(hw); 859 860 /* Wait for the link partner to also set speed */ 861 msec_delay(100); 862 863 /* If we have link, just jump out */ 864 status = ixgbe_check_link(hw, &link_speed, &link_up, FALSE); 865 if (status != IXGBE_SUCCESS) 866 return status; 867 868 if (link_up) 869 goto out; 870 } 871 872 /* 873 * We didn't get link. Configure back to the highest speed we tried, 874 * (if there was more than one). We call ourselves back with just the 875 * single highest speed that the user requested. 876 */ 877 if (speedcnt > 1) 878 status = ixgbe_setup_mac_link_multispeed_fiber(hw, 879 highest_link_speed, autoneg_wait_to_complete); 880 881 out: 882 /* Set autoneg_advertised value based on input link speed */ 883 hw->phy.autoneg_advertised = 0; 884 885 if (speed & IXGBE_LINK_SPEED_10GB_FULL) 886 hw->phy.autoneg_advertised |= IXGBE_LINK_SPEED_10GB_FULL; 887 888 if (speed & IXGBE_LINK_SPEED_1GB_FULL) 889 hw->phy.autoneg_advertised |= IXGBE_LINK_SPEED_1GB_FULL; 890 891 return status; 892 } 893 894 /** 895 * ixgbe_setup_mac_link_smartspeed - Set MAC link speed using SmartSpeed 896 * @hw: pointer to hardware structure 897 * @speed: new link speed 898 * @autoneg_wait_to_complete: TRUE when waiting for completion is needed 899 * 900 * Implements the Intel SmartSpeed algorithm. 901 **/ 902 int32_t ixgbe_setup_mac_link_smartspeed(struct ixgbe_hw *hw, 903 ixgbe_link_speed speed, 904 bool autoneg_wait_to_complete) 905 { 906 int32_t status = IXGBE_SUCCESS; 907 ixgbe_link_speed link_speed = IXGBE_LINK_SPEED_UNKNOWN; 908 int32_t i, j; 909 bool link_up = FALSE; 910 uint32_t autoc_reg = IXGBE_READ_REG(hw, IXGBE_AUTOC); 911 912 DEBUGFUNC("ixgbe_setup_mac_link_smartspeed"); 913 914 /* Set autoneg_advertised value based on input link speed */ 915 hw->phy.autoneg_advertised = 0; 916 917 if (speed & IXGBE_LINK_SPEED_10GB_FULL) 918 hw->phy.autoneg_advertised |= IXGBE_LINK_SPEED_10GB_FULL; 919 920 if (speed & IXGBE_LINK_SPEED_1GB_FULL) 921 hw->phy.autoneg_advertised |= IXGBE_LINK_SPEED_1GB_FULL; 922 923 if (speed & IXGBE_LINK_SPEED_100_FULL) 924 hw->phy.autoneg_advertised |= IXGBE_LINK_SPEED_100_FULL; 925 926 /* 927 * Implement Intel SmartSpeed algorithm. SmartSpeed will reduce the 928 * autoneg advertisement if link is unable to be established at the 929 * highest negotiated rate. This can sometimes happen due to integrity 930 * issues with the physical media connection. 931 */ 932 933 /* First, try to get link with full advertisement */ 934 hw->phy.smart_speed_active = FALSE; 935 for (j = 0; j < IXGBE_SMARTSPEED_MAX_RETRIES; j++) { 936 status = ixgbe_setup_mac_link_82599(hw, speed, 937 autoneg_wait_to_complete); 938 if (status != IXGBE_SUCCESS) 939 goto out; 940 941 /* 942 * Wait for the controller to acquire link. Per IEEE 802.3ap, 943 * Section 73.10.2, we may have to wait up to 500ms if KR is 944 * attempted, or 200ms if KX/KX4/BX/BX4 is attempted, per 945 * Table 9 in the AN MAS. 946 */ 947 for (i = 0; i < 5; i++) { 948 msec_delay(100); 949 950 /* If we have link, just jump out */ 951 status = ixgbe_check_link(hw, &link_speed, &link_up, 952 FALSE); 953 if (status != IXGBE_SUCCESS) 954 goto out; 955 956 if (link_up) 957 goto out; 958 } 959 } 960 961 /* 962 * We didn't get link. If we advertised KR plus one of KX4/KX 963 * (or BX4/BX), then disable KR and try again. 964 */ 965 if (((autoc_reg & IXGBE_AUTOC_KR_SUPP) == 0) || 966 ((autoc_reg & IXGBE_AUTOC_KX4_KX_SUPP_MASK) == 0)) 967 goto out; 968 969 /* Turn SmartSpeed on to disable KR support */ 970 hw->phy.smart_speed_active = TRUE; 971 status = ixgbe_setup_mac_link_82599(hw, speed, 972 autoneg_wait_to_complete); 973 if (status != IXGBE_SUCCESS) 974 goto out; 975 976 /* 977 * Wait for the controller to acquire link. 600ms will allow for 978 * the AN link_fail_inhibit_timer as well for multiple cycles of 979 * parallel detect, both 10g and 1g. This allows for the maximum 980 * connect attempts as defined in the AN MAS table 73-7. 981 */ 982 for (i = 0; i < 6; i++) { 983 msec_delay(100); 984 985 /* If we have link, just jump out */ 986 status = ixgbe_check_link(hw, &link_speed, &link_up, FALSE); 987 if (status != IXGBE_SUCCESS) 988 goto out; 989 990 if (link_up) 991 goto out; 992 } 993 994 /* We didn't get link. Turn SmartSpeed back off. */ 995 hw->phy.smart_speed_active = FALSE; 996 status = ixgbe_setup_mac_link_82599(hw, speed, 997 autoneg_wait_to_complete); 998 999 out: 1000 if (link_up && (link_speed == IXGBE_LINK_SPEED_1GB_FULL)) 1001 DEBUGOUT("Smartspeed has downgraded the link speed " 1002 "from the maximum advertised\n"); 1003 return status; 1004 } 1005 1006 /** 1007 * ixgbe_setup_mac_link_82599 - Set MAC link speed 1008 * @hw: pointer to hardware structure 1009 * @speed: new link speed 1010 * @autoneg_wait_to_complete: TRUE when waiting for completion is needed 1011 * 1012 * Set the link speed in the AUTOC register and restarts link. 1013 **/ 1014 int32_t ixgbe_setup_mac_link_82599(struct ixgbe_hw *hw, 1015 ixgbe_link_speed speed, 1016 bool autoneg_wait_to_complete) 1017 { 1018 bool autoneg = FALSE; 1019 int32_t status = IXGBE_SUCCESS; 1020 uint32_t autoc, pma_pmd_1g, link_mode, start_autoc; 1021 uint32_t autoc2 = IXGBE_READ_REG(hw, IXGBE_AUTOC2); 1022 uint32_t orig_autoc = 0; 1023 uint32_t pma_pmd_10g_serial = autoc2 & IXGBE_AUTOC2_10G_SERIAL_PMA_PMD_MASK; 1024 uint32_t links_reg; 1025 uint32_t i; 1026 ixgbe_link_speed link_capabilities = IXGBE_LINK_SPEED_UNKNOWN; 1027 bool got_lock = FALSE; 1028 1029 DEBUGFUNC("ixgbe_setup_mac_link_82599"); 1030 1031 /* Check to see if speed passed in is supported. */ 1032 status = ixgbe_get_link_capabilities_82599(hw, &link_capabilities, &autoneg); 1033 if (status) 1034 goto out; 1035 1036 speed &= link_capabilities; 1037 1038 if (speed == IXGBE_LINK_SPEED_UNKNOWN) { 1039 status = IXGBE_ERR_LINK_SETUP; 1040 goto out; 1041 } 1042 1043 /* Use stored value (EEPROM defaults) of AUTOC to find KR/KX4 support*/ 1044 if (hw->mac.orig_link_settings_stored) 1045 autoc = hw->mac.orig_autoc; 1046 else 1047 autoc = IXGBE_READ_REG(hw, IXGBE_AUTOC); 1048 1049 orig_autoc = autoc; 1050 start_autoc = hw->mac.cached_autoc; 1051 link_mode = autoc & IXGBE_AUTOC_LMS_MASK; 1052 pma_pmd_1g = autoc & IXGBE_AUTOC_1G_PMA_PMD_MASK; 1053 1054 if (link_mode == IXGBE_AUTOC_LMS_KX4_KX_KR || 1055 link_mode == IXGBE_AUTOC_LMS_KX4_KX_KR_1G_AN || 1056 link_mode == IXGBE_AUTOC_LMS_KX4_KX_KR_SGMII) { 1057 /* Set KX4/KX/KR support according to speed requested */ 1058 autoc &= ~(IXGBE_AUTOC_KX4_KX_SUPP_MASK | IXGBE_AUTOC_KR_SUPP); 1059 if (speed & IXGBE_LINK_SPEED_10GB_FULL) { 1060 if (orig_autoc & IXGBE_AUTOC_KX4_SUPP) 1061 autoc |= IXGBE_AUTOC_KX4_SUPP; 1062 if ((orig_autoc & IXGBE_AUTOC_KR_SUPP) && 1063 (hw->phy.smart_speed_active == FALSE)) 1064 autoc |= IXGBE_AUTOC_KR_SUPP; 1065 } 1066 if (speed & IXGBE_LINK_SPEED_1GB_FULL) 1067 autoc |= IXGBE_AUTOC_KX_SUPP; 1068 } else if ((pma_pmd_1g == IXGBE_AUTOC_1G_SFI) && 1069 (link_mode == IXGBE_AUTOC_LMS_1G_LINK_NO_AN || 1070 link_mode == IXGBE_AUTOC_LMS_1G_AN)) { 1071 /* Switch from 1G SFI to 10G SFI if requested */ 1072 if ((speed == IXGBE_LINK_SPEED_10GB_FULL) && 1073 (pma_pmd_10g_serial == IXGBE_AUTOC2_10G_SFI)) { 1074 autoc &= ~IXGBE_AUTOC_LMS_MASK; 1075 autoc |= IXGBE_AUTOC_LMS_10G_SERIAL; 1076 } 1077 } else if ((pma_pmd_10g_serial == IXGBE_AUTOC2_10G_SFI) && 1078 (link_mode == IXGBE_AUTOC_LMS_10G_SERIAL)) { 1079 /* Switch from 10G SFI to 1G SFI if requested */ 1080 if ((speed == IXGBE_LINK_SPEED_1GB_FULL) && 1081 (pma_pmd_1g == IXGBE_AUTOC_1G_SFI)) { 1082 autoc &= ~IXGBE_AUTOC_LMS_MASK; 1083 if (autoneg) 1084 autoc |= IXGBE_AUTOC_LMS_1G_AN; 1085 else 1086 autoc |= IXGBE_AUTOC_LMS_1G_LINK_NO_AN; 1087 } 1088 } 1089 1090 if (autoc != start_autoc) { 1091 /* Need SW/FW semaphore around AUTOC writes if LESM is on, 1092 * likewise reset_pipeline requires us to hold this lock as 1093 * it also writes to AUTOC. 1094 */ 1095 if (ixgbe_verify_lesm_fw_enabled_82599(hw)) { 1096 status = hw->mac.ops.acquire_swfw_sync(hw, 1097 IXGBE_GSSR_MAC_CSR_SM); 1098 if (status != IXGBE_SUCCESS) { 1099 status = IXGBE_ERR_SWFW_SYNC; 1100 goto out; 1101 } 1102 1103 got_lock = TRUE; 1104 } 1105 1106 /* Restart link */ 1107 IXGBE_WRITE_REG(hw, IXGBE_AUTOC, autoc); 1108 hw->mac.cached_autoc = autoc; 1109 ixgbe_reset_pipeline_82599(hw); 1110 1111 if (got_lock) { 1112 hw->mac.ops.release_swfw_sync(hw, 1113 IXGBE_GSSR_MAC_CSR_SM); 1114 got_lock = FALSE; 1115 } 1116 1117 /* Only poll for autoneg to complete if specified to do so */ 1118 if (autoneg_wait_to_complete) { 1119 if (link_mode == IXGBE_AUTOC_LMS_KX4_KX_KR || 1120 link_mode == IXGBE_AUTOC_LMS_KX4_KX_KR_1G_AN || 1121 link_mode == IXGBE_AUTOC_LMS_KX4_KX_KR_SGMII) { 1122 links_reg = 0; /*Just in case Autoneg time=0*/ 1123 for (i = 0; i < IXGBE_AUTO_NEG_TIME; i++) { 1124 links_reg = 1125 IXGBE_READ_REG(hw, IXGBE_LINKS); 1126 if (links_reg & IXGBE_LINKS_KX_AN_COMP) 1127 break; 1128 msec_delay(100); 1129 } 1130 if (!(links_reg & IXGBE_LINKS_KX_AN_COMP)) { 1131 status = 1132 IXGBE_ERR_AUTONEG_NOT_COMPLETE; 1133 DEBUGOUT("Autoneg did not complete.\n"); 1134 } 1135 } 1136 } 1137 1138 /* Add delay to filter out noises during initial link setup */ 1139 msec_delay(50); 1140 } 1141 1142 out: 1143 return status; 1144 } 1145 1146 /** 1147 * ixgbe_setup_copper_link_82599 - Set the PHY autoneg advertised field 1148 * @hw: pointer to hardware structure 1149 * @speed: new link speed 1150 * @autoneg_wait_to_complete: TRUE if waiting is needed to complete 1151 * 1152 * Restarts link on PHY and MAC based on settings passed in. 1153 **/ 1154 int32_t ixgbe_setup_copper_link_82599(struct ixgbe_hw *hw, 1155 ixgbe_link_speed speed, 1156 bool autoneg_wait_to_complete) 1157 { 1158 int32_t status; 1159 1160 DEBUGFUNC("ixgbe_setup_copper_link_82599"); 1161 1162 /* Setup the PHY according to input speed */ 1163 status = hw->phy.ops.setup_link_speed(hw, speed, 1164 autoneg_wait_to_complete); 1165 /* Set up MAC */ 1166 ixgbe_start_mac_link_82599(hw, autoneg_wait_to_complete); 1167 1168 return status; 1169 } 1170 1171 /** 1172 * ixgbe_reset_hw_82599 - Perform hardware reset 1173 * @hw: pointer to hardware structure 1174 * 1175 * Resets the hardware by resetting the transmit and receive units, masks 1176 * and clears all interrupts, perform a PHY reset, and perform a link (MAC) 1177 * reset. 1178 **/ 1179 int32_t ixgbe_reset_hw_82599(struct ixgbe_hw *hw) 1180 { 1181 ixgbe_link_speed link_speed; 1182 int32_t status; 1183 uint32_t ctrl, i, autoc2; 1184 uint32_t curr_lms; 1185 bool link_up = FALSE; 1186 1187 DEBUGFUNC("ixgbe_reset_hw_82599"); 1188 1189 /* Call adapter stop to disable tx/rx and clear interrupts */ 1190 status = hw->mac.ops.stop_adapter(hw); 1191 if (status != IXGBE_SUCCESS) 1192 goto reset_hw_out; 1193 1194 /* flush pending Tx transactions */ 1195 ixgbe_clear_tx_pending(hw); 1196 1197 /* PHY ops must be identified and initialized prior to reset */ 1198 1199 /* Identify PHY and related function pointers */ 1200 status = hw->phy.ops.init(hw); 1201 1202 if (status == IXGBE_ERR_SFP_NOT_SUPPORTED) 1203 goto reset_hw_out; 1204 1205 /* Setup SFP module if there is one present. */ 1206 if (hw->phy.sfp_setup_needed) { 1207 status = hw->mac.ops.setup_sfp(hw); 1208 hw->phy.sfp_setup_needed = FALSE; 1209 } 1210 1211 if (status == IXGBE_ERR_SFP_NOT_SUPPORTED) 1212 goto reset_hw_out; 1213 1214 /* Reset PHY */ 1215 if (hw->phy.reset_disable == FALSE && hw->phy.ops.reset != NULL) 1216 hw->phy.ops.reset(hw); 1217 1218 /* remember AUTOC from before we reset */ 1219 if (hw->mac.cached_autoc) 1220 curr_lms = hw->mac.cached_autoc & IXGBE_AUTOC_LMS_MASK; 1221 else 1222 curr_lms = IXGBE_READ_REG(hw, IXGBE_AUTOC) & 1223 IXGBE_AUTOC_LMS_MASK; 1224 1225 mac_reset_top: 1226 /* 1227 * Issue global reset to the MAC. Needs to be SW reset if link is up. 1228 * If link reset is used when link is up, it might reset the PHY when 1229 * mng is using it. If link is down or the flag to force full link 1230 * reset is set, then perform link reset. 1231 */ 1232 ctrl = IXGBE_CTRL_LNK_RST; 1233 if (!hw->force_full_reset) { 1234 hw->mac.ops.check_link(hw, &link_speed, &link_up, FALSE); 1235 if (link_up) 1236 ctrl = IXGBE_CTRL_RST; 1237 } 1238 1239 ctrl |= IXGBE_READ_REG(hw, IXGBE_CTRL); 1240 IXGBE_WRITE_REG(hw, IXGBE_CTRL, ctrl); 1241 IXGBE_WRITE_FLUSH(hw); 1242 1243 /* Poll for reset bit to self-clear indicating reset is complete */ 1244 for (i = 0; i < 10; i++) { 1245 usec_delay(1); 1246 ctrl = IXGBE_READ_REG(hw, IXGBE_CTRL); 1247 if (!(ctrl & IXGBE_CTRL_RST_MASK)) 1248 break; 1249 } 1250 1251 if (ctrl & IXGBE_CTRL_RST_MASK) { 1252 status = IXGBE_ERR_RESET_FAILED; 1253 DEBUGOUT("Reset polling failed to complete.\n"); 1254 } 1255 1256 msec_delay(50); 1257 1258 /* 1259 * Double resets are required for recovery from certain error 1260 * conditions. Between resets, it is necessary to stall to allow time 1261 * for any pending HW events to complete. 1262 */ 1263 if (hw->mac.flags & IXGBE_FLAGS_DOUBLE_RESET_REQUIRED) { 1264 hw->mac.flags &= ~IXGBE_FLAGS_DOUBLE_RESET_REQUIRED; 1265 goto mac_reset_top; 1266 } 1267 1268 /* 1269 * Store the original AUTOC/AUTOC2 values if they have not been 1270 * stored off yet. Otherwise restore the stored original 1271 * values since the reset operation sets back to defaults. 1272 */ 1273 hw->mac.cached_autoc = IXGBE_READ_REG(hw, IXGBE_AUTOC); 1274 autoc2 = IXGBE_READ_REG(hw, IXGBE_AUTOC2); 1275 1276 /* Enable link if disabled in NVM */ 1277 if (autoc2 & IXGBE_AUTOC2_LINK_DISABLE_MASK) { 1278 autoc2 &= ~IXGBE_AUTOC2_LINK_DISABLE_MASK; 1279 IXGBE_WRITE_REG(hw, IXGBE_AUTOC2, autoc2); 1280 IXGBE_WRITE_FLUSH(hw); 1281 } 1282 1283 if (hw->mac.orig_link_settings_stored == FALSE) { 1284 hw->mac.orig_autoc = hw->mac.cached_autoc; 1285 hw->mac.orig_autoc2 = autoc2; 1286 hw->mac.orig_link_settings_stored = TRUE; 1287 } else { 1288 1289 /* If MNG FW is running on a multi-speed device that 1290 * doesn't autoneg with out driver support we need to 1291 * leave LMS in the state it was before we MAC reset. 1292 * Likewise if we support WoL we don't want change the 1293 * LMS state. 1294 */ 1295 if (hw->phy.multispeed_fiber && hw->mng_fw_enabled) 1296 hw->mac.orig_autoc = 1297 (hw->mac.orig_autoc & ~IXGBE_AUTOC_LMS_MASK) | 1298 curr_lms; 1299 1300 if (hw->mac.cached_autoc != hw->mac.orig_autoc) { 1301 /* Need SW/FW semaphore around AUTOC writes if LESM is 1302 * on, likewise reset_pipeline requires us to hold 1303 * this lock as it also writes to AUTOC. 1304 */ 1305 bool got_lock = FALSE; 1306 if (ixgbe_verify_lesm_fw_enabled_82599(hw)) { 1307 status = hw->mac.ops.acquire_swfw_sync(hw, 1308 IXGBE_GSSR_MAC_CSR_SM); 1309 if (status != IXGBE_SUCCESS) { 1310 status = IXGBE_ERR_SWFW_SYNC; 1311 goto reset_hw_out; 1312 } 1313 1314 got_lock = TRUE; 1315 } 1316 1317 IXGBE_WRITE_REG(hw, IXGBE_AUTOC, hw->mac.orig_autoc); 1318 hw->mac.cached_autoc = hw->mac.orig_autoc; 1319 ixgbe_reset_pipeline_82599(hw); 1320 1321 if (got_lock) 1322 hw->mac.ops.release_swfw_sync(hw, 1323 IXGBE_GSSR_MAC_CSR_SM); 1324 } 1325 1326 if ((autoc2 & IXGBE_AUTOC2_UPPER_MASK) != 1327 (hw->mac.orig_autoc2 & IXGBE_AUTOC2_UPPER_MASK)) { 1328 autoc2 &= ~IXGBE_AUTOC2_UPPER_MASK; 1329 autoc2 |= (hw->mac.orig_autoc2 & 1330 IXGBE_AUTOC2_UPPER_MASK); 1331 IXGBE_WRITE_REG(hw, IXGBE_AUTOC2, autoc2); 1332 } 1333 } 1334 1335 /* Store the permanent mac address */ 1336 hw->mac.ops.get_mac_addr(hw, hw->mac.perm_addr); 1337 1338 /* 1339 * Store MAC address from RAR0, clear receive address registers, and 1340 * clear the multicast table. Also reset num_rar_entries to 128, 1341 * since we modify this value when programming the SAN MAC address. 1342 */ 1343 hw->mac.num_rar_entries = 128; 1344 hw->mac.ops.init_rx_addrs(hw); 1345 1346 reset_hw_out: 1347 return status; 1348 } 1349 1350 /** 1351 * ixgbe_read_analog_reg8_82599 - Reads 8 bit Omer analog register 1352 * @hw: pointer to hardware structure 1353 * @reg: analog register to read 1354 * @val: read value 1355 * 1356 * Performs read operation to Omer analog register specified. 1357 **/ 1358 int32_t ixgbe_read_analog_reg8_82599(struct ixgbe_hw *hw, uint32_t reg, 1359 uint8_t *val) 1360 { 1361 uint32_t core_ctl; 1362 1363 DEBUGFUNC("ixgbe_read_analog_reg8_82599"); 1364 1365 IXGBE_WRITE_REG(hw, IXGBE_CORECTL, IXGBE_CORECTL_WRITE_CMD | 1366 (reg << 8)); 1367 IXGBE_WRITE_FLUSH(hw); 1368 usec_delay(10); 1369 core_ctl = IXGBE_READ_REG(hw, IXGBE_CORECTL); 1370 *val = (uint8_t)core_ctl; 1371 1372 return IXGBE_SUCCESS; 1373 } 1374 1375 /** 1376 * ixgbe_write_analog_reg8_82599 - Writes 8 bit Omer analog register 1377 * @hw: pointer to hardware structure 1378 * @reg: atlas register to write 1379 * @val: value to write 1380 * 1381 * Performs write operation to Omer analog register specified. 1382 **/ 1383 int32_t ixgbe_write_analog_reg8_82599(struct ixgbe_hw *hw, uint32_t reg, 1384 uint8_t val) 1385 { 1386 uint32_t core_ctl; 1387 1388 DEBUGFUNC("ixgbe_write_analog_reg8_82599"); 1389 1390 core_ctl = (reg << 8) | val; 1391 IXGBE_WRITE_REG(hw, IXGBE_CORECTL, core_ctl); 1392 IXGBE_WRITE_FLUSH(hw); 1393 usec_delay(10); 1394 1395 return IXGBE_SUCCESS; 1396 } 1397 1398 /** 1399 * ixgbe_start_hw_82599 - Prepare hardware for Tx/Rx 1400 * @hw: pointer to hardware structure 1401 * 1402 * Starts the hardware using the generic start_hw function 1403 * and the generation start_hw function. 1404 * Then performs revision-specific operations, if any. 1405 **/ 1406 int32_t ixgbe_start_hw_82599(struct ixgbe_hw *hw) 1407 { 1408 int32_t ret_val = IXGBE_SUCCESS; 1409 1410 DEBUGFUNC("ixgbe_start_hw_82599"); 1411 1412 ret_val = ixgbe_start_hw_generic(hw); 1413 if (ret_val != IXGBE_SUCCESS) 1414 goto out; 1415 1416 ret_val = ixgbe_start_hw_gen2(hw); 1417 if (ret_val != IXGBE_SUCCESS) 1418 goto out; 1419 1420 /* We need to run link autotry after the driver loads */ 1421 hw->mac.autotry_restart = TRUE; 1422 1423 if (ret_val == IXGBE_SUCCESS) 1424 ret_val = ixgbe_verify_fw_version_82599(hw); 1425 out: 1426 return ret_val; 1427 } 1428 1429 /** 1430 * ixgbe_identify_phy_82599 - Get physical layer module 1431 * @hw: pointer to hardware structure 1432 * 1433 * Determines the physical layer module found on the current adapter. 1434 * If PHY already detected, maintains current PHY type in hw struct, 1435 * otherwise executes the PHY detection routine. 1436 **/ 1437 int32_t ixgbe_identify_phy_82599(struct ixgbe_hw *hw) 1438 { 1439 int32_t status = IXGBE_ERR_PHY_ADDR_INVALID; 1440 1441 DEBUGFUNC("ixgbe_identify_phy_82599"); 1442 1443 /* Detect PHY if not unknown - returns success if already detected. */ 1444 status = ixgbe_identify_phy_generic(hw); 1445 if (status != IXGBE_SUCCESS) { 1446 /* 82599 10GBASE-T requires an external PHY */ 1447 if (hw->mac.ops.get_media_type(hw) == ixgbe_media_type_copper) 1448 goto out; 1449 else 1450 status = ixgbe_identify_module_generic(hw); 1451 } 1452 1453 /* Set PHY type none if no PHY detected */ 1454 if (hw->phy.type == ixgbe_phy_unknown) { 1455 hw->phy.type = ixgbe_phy_none; 1456 status = IXGBE_SUCCESS; 1457 } 1458 1459 /* Return error if SFP module has been detected but is not supported */ 1460 if (hw->phy.type == ixgbe_phy_sfp_unsupported) 1461 status = IXGBE_ERR_SFP_NOT_SUPPORTED; 1462 1463 out: 1464 return status; 1465 } 1466 1467 /** 1468 * ixgbe_get_supported_physical_layer_82599 - Returns physical layer type 1469 * @hw: pointer to hardware structure 1470 * 1471 * Determines physical layer capabilities of the current configuration. 1472 **/ 1473 uint32_t ixgbe_get_supported_physical_layer_82599(struct ixgbe_hw *hw) 1474 { 1475 uint32_t physical_layer = IXGBE_PHYSICAL_LAYER_UNKNOWN; 1476 uint32_t autoc = IXGBE_READ_REG(hw, IXGBE_AUTOC); 1477 uint32_t autoc2 = IXGBE_READ_REG(hw, IXGBE_AUTOC2); 1478 uint32_t pma_pmd_10g_serial = autoc2 & IXGBE_AUTOC2_10G_SERIAL_PMA_PMD_MASK; 1479 uint32_t pma_pmd_10g_parallel = autoc & IXGBE_AUTOC_10G_PMA_PMD_MASK; 1480 uint32_t pma_pmd_1g = autoc & IXGBE_AUTOC_1G_PMA_PMD_MASK; 1481 uint16_t ext_ability = 0; 1482 uint8_t comp_codes_10g = 0; 1483 uint8_t comp_codes_1g = 0; 1484 1485 DEBUGFUNC("ixgbe_get_support_physical_layer_82599"); 1486 1487 hw->phy.ops.identify(hw); 1488 1489 switch (hw->phy.type) { 1490 case ixgbe_phy_tn: 1491 case ixgbe_phy_cu_unknown: 1492 hw->phy.ops.read_reg(hw, IXGBE_MDIO_PHY_EXT_ABILITY, 1493 IXGBE_MDIO_PMA_PMD_DEV_TYPE, &ext_ability); 1494 if (ext_ability & IXGBE_MDIO_PHY_10GBASET_ABILITY) 1495 physical_layer |= IXGBE_PHYSICAL_LAYER_10GBASE_T; 1496 if (ext_ability & IXGBE_MDIO_PHY_1000BASET_ABILITY) 1497 physical_layer |= IXGBE_PHYSICAL_LAYER_1000BASE_T; 1498 if (ext_ability & IXGBE_MDIO_PHY_100BASETX_ABILITY) 1499 physical_layer |= IXGBE_PHYSICAL_LAYER_100BASE_TX; 1500 goto out; 1501 default: 1502 break; 1503 } 1504 1505 switch (autoc & IXGBE_AUTOC_LMS_MASK) { 1506 case IXGBE_AUTOC_LMS_1G_AN: 1507 case IXGBE_AUTOC_LMS_1G_LINK_NO_AN: 1508 if (pma_pmd_1g == IXGBE_AUTOC_1G_KX_BX) { 1509 physical_layer = IXGBE_PHYSICAL_LAYER_1000BASE_KX | 1510 IXGBE_PHYSICAL_LAYER_1000BASE_BX; 1511 goto out; 1512 } else 1513 /* SFI mode so read SFP module */ 1514 goto sfp_check; 1515 break; 1516 case IXGBE_AUTOC_LMS_10G_LINK_NO_AN: 1517 if (pma_pmd_10g_parallel == IXGBE_AUTOC_10G_CX4) 1518 physical_layer = IXGBE_PHYSICAL_LAYER_10GBASE_CX4; 1519 else if (pma_pmd_10g_parallel == IXGBE_AUTOC_10G_KX4) 1520 physical_layer = IXGBE_PHYSICAL_LAYER_10GBASE_KX4; 1521 else if (pma_pmd_10g_parallel == IXGBE_AUTOC_10G_XAUI) 1522 physical_layer = IXGBE_PHYSICAL_LAYER_10GBASE_XAUI; 1523 goto out; 1524 break; 1525 case IXGBE_AUTOC_LMS_10G_SERIAL: 1526 if (pma_pmd_10g_serial == IXGBE_AUTOC2_10G_KR) { 1527 physical_layer = IXGBE_PHYSICAL_LAYER_10GBASE_KR; 1528 goto out; 1529 } else if (pma_pmd_10g_serial == IXGBE_AUTOC2_10G_SFI) 1530 goto sfp_check; 1531 break; 1532 case IXGBE_AUTOC_LMS_KX4_KX_KR: 1533 case IXGBE_AUTOC_LMS_KX4_KX_KR_1G_AN: 1534 if (autoc & IXGBE_AUTOC_KX_SUPP) 1535 physical_layer |= IXGBE_PHYSICAL_LAYER_1000BASE_KX; 1536 if (autoc & IXGBE_AUTOC_KX4_SUPP) 1537 physical_layer |= IXGBE_PHYSICAL_LAYER_10GBASE_KX4; 1538 if (autoc & IXGBE_AUTOC_KR_SUPP) 1539 physical_layer |= IXGBE_PHYSICAL_LAYER_10GBASE_KR; 1540 goto out; 1541 break; 1542 default: 1543 goto out; 1544 break; 1545 } 1546 1547 sfp_check: 1548 /* SFP check must be done last since DA modules are sometimes used to 1549 * test KR mode - we need to id KR mode correctly before SFP module. 1550 * Call identify_sfp because the pluggable module may have changed */ 1551 hw->phy.ops.identify_sfp(hw); 1552 if (hw->phy.sfp_type == ixgbe_sfp_type_not_present) 1553 goto out; 1554 1555 switch (hw->phy.type) { 1556 case ixgbe_phy_sfp_passive_tyco: 1557 case ixgbe_phy_sfp_passive_unknown: 1558 physical_layer = IXGBE_PHYSICAL_LAYER_SFP_PLUS_CU; 1559 break; 1560 case ixgbe_phy_sfp_ftl_active: 1561 case ixgbe_phy_sfp_active_unknown: 1562 physical_layer = IXGBE_PHYSICAL_LAYER_SFP_ACTIVE_DA; 1563 break; 1564 case ixgbe_phy_sfp_avago: 1565 case ixgbe_phy_sfp_ftl: 1566 case ixgbe_phy_sfp_intel: 1567 case ixgbe_phy_sfp_unknown: 1568 hw->phy.ops.read_i2c_eeprom(hw, 1569 IXGBE_SFF_1GBE_COMP_CODES, &comp_codes_1g); 1570 hw->phy.ops.read_i2c_eeprom(hw, 1571 IXGBE_SFF_10GBE_COMP_CODES, &comp_codes_10g); 1572 if (comp_codes_10g & IXGBE_SFF_10GBASESR_CAPABLE) 1573 physical_layer = IXGBE_PHYSICAL_LAYER_10GBASE_SR; 1574 else if (comp_codes_10g & IXGBE_SFF_10GBASELR_CAPABLE) 1575 physical_layer = IXGBE_PHYSICAL_LAYER_10GBASE_LR; 1576 else if (comp_codes_10g & 1577 (IXGBE_SFF_DA_PASSIVE_CABLE | IXGBE_SFF_DA_BAD_HP_CABLE)) 1578 physical_layer = IXGBE_PHYSICAL_LAYER_SFP_PLUS_CU; 1579 else if (comp_codes_10g & IXGBE_SFF_DA_ACTIVE_CABLE) 1580 physical_layer = IXGBE_PHYSICAL_LAYER_SFP_ACTIVE_DA; 1581 else if (comp_codes_1g & IXGBE_SFF_1GBASET_CAPABLE) 1582 physical_layer = IXGBE_PHYSICAL_LAYER_1000BASE_T; 1583 else if (comp_codes_1g & IXGBE_SFF_1GBASESX_CAPABLE) 1584 physical_layer = IXGBE_PHYSICAL_LAYER_1000BASE_SX; 1585 else if (comp_codes_1g & IXGBE_SFF_1GBASELX_CAPABLE) 1586 physical_layer = IXGBE_PHYSICAL_LAYER_1000BASE_LX; 1587 break; 1588 default: 1589 break; 1590 } 1591 1592 out: 1593 return physical_layer; 1594 } 1595 1596 /** 1597 * ixgbe_enable_rx_dma_82599 - Enable the Rx DMA unit on 82599 1598 * @hw: pointer to hardware structure 1599 * @regval: register value to write to RXCTRL 1600 * 1601 * Enables the Rx DMA unit for 82599 1602 **/ 1603 int32_t ixgbe_enable_rx_dma_82599(struct ixgbe_hw *hw, uint32_t regval) 1604 { 1605 1606 DEBUGFUNC("ixgbe_enable_rx_dma_82599"); 1607 1608 /* 1609 * Workaround for 82599 silicon errata when enabling the Rx datapath. 1610 * If traffic is incoming before we enable the Rx unit, it could hang 1611 * the Rx DMA unit. Therefore, make sure the security engine is 1612 * completely disabled prior to enabling the Rx unit. 1613 */ 1614 1615 hw->mac.ops.disable_sec_rx_path(hw); 1616 1617 IXGBE_WRITE_REG(hw, IXGBE_RXCTRL, regval); 1618 1619 hw->mac.ops.enable_sec_rx_path(hw); 1620 1621 return IXGBE_SUCCESS; 1622 } 1623 1624 /** 1625 * ixgbe_verify_fw_version_82599 - verify fw version for 82599 1626 * @hw: pointer to hardware structure 1627 * 1628 * Verifies that installed the firmware version is 0.6 or higher 1629 * for SFI devices. All 82599 SFI devices should have version 0.6 or higher. 1630 * 1631 * Returns IXGBE_ERR_EEPROM_VERSION if the FW is not present or 1632 * if the FW version is not supported. 1633 **/ 1634 int32_t ixgbe_verify_fw_version_82599(struct ixgbe_hw *hw) 1635 { 1636 int32_t status = IXGBE_ERR_EEPROM_VERSION; 1637 uint16_t fw_offset, fw_ptp_cfg_offset; 1638 uint16_t fw_version; 1639 1640 DEBUGFUNC("ixgbe_verify_fw_version_82599"); 1641 1642 /* firmware check is only necessary for SFI devices */ 1643 if (hw->phy.media_type != ixgbe_media_type_fiber) { 1644 status = IXGBE_SUCCESS; 1645 goto fw_version_out; 1646 } 1647 1648 /* get the offset to the Firmware Module block */ 1649 if (hw->eeprom.ops.read(hw, IXGBE_FW_PTR, &fw_offset)) { 1650 ERROR_REPORT2(IXGBE_ERROR_INVALID_STATE, 1651 "eeprom read at offset %d failed", IXGBE_FW_PTR); 1652 return IXGBE_ERR_EEPROM_VERSION; 1653 } 1654 1655 if ((fw_offset == 0) || (fw_offset == 0xFFFF)) 1656 goto fw_version_out; 1657 1658 /* get the offset to the Pass Through Patch Configuration block */ 1659 if (hw->eeprom.ops.read(hw, (fw_offset + 1660 IXGBE_FW_PASSTHROUGH_PATCH_CONFIG_PTR), 1661 &fw_ptp_cfg_offset)) { 1662 ERROR_REPORT2(IXGBE_ERROR_INVALID_STATE, 1663 "eeprom read at offset %d failed", 1664 fw_offset + 1665 IXGBE_FW_PASSTHROUGH_PATCH_CONFIG_PTR); 1666 return IXGBE_ERR_EEPROM_VERSION; 1667 } 1668 1669 if ((fw_ptp_cfg_offset == 0) || (fw_ptp_cfg_offset == 0xFFFF)) 1670 goto fw_version_out; 1671 1672 /* get the firmware version */ 1673 if (hw->eeprom.ops.read(hw, (fw_ptp_cfg_offset + 1674 IXGBE_FW_PATCH_VERSION_4), &fw_version)) { 1675 ERROR_REPORT2(IXGBE_ERROR_INVALID_STATE, 1676 "eeprom read at offset %d failed", 1677 fw_ptp_cfg_offset + IXGBE_FW_PATCH_VERSION_4); 1678 return IXGBE_ERR_EEPROM_VERSION; 1679 } 1680 1681 if (fw_version > 0x5) 1682 status = IXGBE_SUCCESS; 1683 1684 fw_version_out: 1685 return status; 1686 } 1687 1688 /** 1689 * ixgbe_verify_lesm_fw_enabled_82599 - Checks LESM FW module state. 1690 * @hw: pointer to hardware structure 1691 * 1692 * Returns TRUE if the LESM FW module is present and enabled. Otherwise 1693 * returns FALSE. Smart Speed must be disabled if LESM FW module is enabled. 1694 **/ 1695 bool ixgbe_verify_lesm_fw_enabled_82599(struct ixgbe_hw *hw) 1696 { 1697 bool lesm_enabled = FALSE; 1698 uint16_t fw_offset, fw_lesm_param_offset, fw_lesm_state; 1699 int32_t status; 1700 1701 DEBUGFUNC("ixgbe_verify_lesm_fw_enabled_82599"); 1702 1703 /* get the offset to the Firmware Module block */ 1704 status = hw->eeprom.ops.read(hw, IXGBE_FW_PTR, &fw_offset); 1705 1706 if ((status != IXGBE_SUCCESS) || 1707 (fw_offset == 0) || (fw_offset == 0xFFFF)) 1708 goto out; 1709 1710 /* get the offset to the LESM Parameters block */ 1711 status = hw->eeprom.ops.read(hw, (fw_offset + 1712 IXGBE_FW_LESM_PARAMETERS_PTR), 1713 &fw_lesm_param_offset); 1714 1715 if ((status != IXGBE_SUCCESS) || 1716 (fw_lesm_param_offset == 0) || (fw_lesm_param_offset == 0xFFFF)) 1717 goto out; 1718 1719 /* get the lesm state word */ 1720 status = hw->eeprom.ops.read(hw, (fw_lesm_param_offset + 1721 IXGBE_FW_LESM_STATE_1), 1722 &fw_lesm_state); 1723 1724 if ((status == IXGBE_SUCCESS) && 1725 (fw_lesm_state & IXGBE_FW_LESM_STATE_ENABLED)) 1726 lesm_enabled = TRUE; 1727 1728 out: 1729 return lesm_enabled; 1730 } 1731 1732 /** 1733 * ixgbe_read_eeprom_82599 - Read EEPROM word using 1734 * fastest available method 1735 * 1736 * @hw: pointer to hardware structure 1737 * @offset: offset of word in the EEPROM to read 1738 * @data: word read from the EEPROM 1739 * 1740 * Reads a 16 bit word from the EEPROM 1741 **/ 1742 int32_t ixgbe_read_eeprom_82599(struct ixgbe_hw *hw, 1743 uint16_t offset, uint16_t *data) 1744 { 1745 struct ixgbe_eeprom_info *eeprom = &hw->eeprom; 1746 int32_t ret_val = IXGBE_ERR_CONFIG; 1747 1748 DEBUGFUNC("ixgbe_read_eeprom_82599"); 1749 1750 /* 1751 * If EEPROM is detected and can be addressed using 14 bits, 1752 * use EERD otherwise use bit bang 1753 */ 1754 if ((eeprom->type == ixgbe_eeprom_spi) && 1755 (offset <= IXGBE_EERD_MAX_ADDR)) 1756 ret_val = ixgbe_read_eerd_generic(hw, offset, data); 1757 else 1758 ret_val = ixgbe_read_eeprom_bit_bang_generic(hw, offset, data); 1759 1760 return ret_val; 1761 } 1762 1763 /** 1764 * ixgbe_reset_pipeline_82599 - perform pipeline reset 1765 * 1766 * @hw: pointer to hardware structure 1767 * 1768 * Reset pipeline by asserting Restart_AN together with LMS change to ensure 1769 * full pipeline reset 1770 **/ 1771 int32_t ixgbe_reset_pipeline_82599(struct ixgbe_hw *hw) 1772 { 1773 int32_t ret_val; 1774 uint32_t anlp1_reg = 0; 1775 uint32_t i, autoc_reg, autoc2_reg; 1776 1777 /* Enable link if disabled in NVM */ 1778 autoc2_reg = IXGBE_READ_REG(hw, IXGBE_AUTOC2); 1779 if (autoc2_reg & IXGBE_AUTOC2_LINK_DISABLE_MASK) { 1780 autoc2_reg &= ~IXGBE_AUTOC2_LINK_DISABLE_MASK; 1781 IXGBE_WRITE_REG(hw, IXGBE_AUTOC2, autoc2_reg); 1782 IXGBE_WRITE_FLUSH(hw); 1783 } 1784 1785 autoc_reg = hw->mac.cached_autoc; 1786 autoc_reg |= IXGBE_AUTOC_AN_RESTART; 1787 /* Write AUTOC register with toggled LMS[2] bit and Restart_AN */ 1788 IXGBE_WRITE_REG(hw, IXGBE_AUTOC, autoc_reg ^ IXGBE_AUTOC_LMS_1G_AN); 1789 /* Wait for AN to leave state 0 */ 1790 for (i = 0; i < 10; i++) { 1791 msec_delay(4); 1792 anlp1_reg = IXGBE_READ_REG(hw, IXGBE_ANLP1); 1793 if (anlp1_reg & IXGBE_ANLP1_AN_STATE_MASK) 1794 break; 1795 } 1796 1797 if (!(anlp1_reg & IXGBE_ANLP1_AN_STATE_MASK)) { 1798 DEBUGOUT("auto negotiation not completed\n"); 1799 ret_val = IXGBE_ERR_RESET_FAILED; 1800 goto reset_pipeline_out; 1801 } 1802 1803 ret_val = IXGBE_SUCCESS; 1804 1805 reset_pipeline_out: 1806 /* Write AUTOC register with original LMS field and Restart_AN */ 1807 IXGBE_WRITE_REG(hw, IXGBE_AUTOC, autoc_reg); 1808 IXGBE_WRITE_FLUSH(hw); 1809 1810 return ret_val; 1811 } 1812