1 /* $OpenBSD: ixgbe_82598.c,v 1.15 2016/11/17 19:26:57 mikeb Exp $ */ 2 3 /****************************************************************************** 4 5 Copyright (c) 2001-2015, Intel Corporation 6 All rights reserved. 7 8 Redistribution and use in source and binary forms, with or without 9 modification, are permitted provided that the following conditions are met: 10 11 1. Redistributions of source code must retain the above copyright notice, 12 this list of conditions and the following disclaimer. 13 14 2. Redistributions in binary form must reproduce the above copyright 15 notice, this list of conditions and the following disclaimer in the 16 documentation and/or other materials provided with the distribution. 17 18 3. Neither the name of the Intel Corporation nor the names of its 19 contributors may be used to endorse or promote products derived from 20 this software without specific prior written permission. 21 22 THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS" 23 AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE 24 IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE 25 ARE DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT OWNER OR CONTRIBUTORS BE 26 LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR 27 CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF 28 SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS 29 INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN 30 CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) 31 ARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE 32 POSSIBILITY OF SUCH DAMAGE. 33 34 ******************************************************************************/ 35 /*$FreeBSD: head/sys/dev/ixgbe/ixgbe_82598.c 292674 2015-12-23 22:45:17Z sbruno $*/ 36 37 #include <dev/pci/ixgbe.h> 38 #include <dev/pci/ixgbe_type.h> 39 40 #define IXGBE_82598_MAX_TX_QUEUES 32 41 #define IXGBE_82598_MAX_RX_QUEUES 64 42 #define IXGBE_82598_RAR_ENTRIES 16 43 #define IXGBE_82598_MC_TBL_SIZE 128 44 #define IXGBE_82598_VFT_TBL_SIZE 128 45 #define IXGBE_82598_RX_PB_SIZE 512 46 47 uint32_t ixgbe_get_pcie_msix_count_82598(struct ixgbe_hw *hw); 48 int32_t ixgbe_get_link_capabilities_82598(struct ixgbe_hw *hw, 49 ixgbe_link_speed *speed, 50 bool *autoneg); 51 enum ixgbe_media_type ixgbe_get_media_type_82598(struct ixgbe_hw *hw); 52 int32_t ixgbe_fc_enable_82598(struct ixgbe_hw *hw); 53 int32_t ixgbe_start_mac_link_82598(struct ixgbe_hw *hw, 54 bool autoneg_wait_to_complete); 55 int32_t ixgbe_validate_link_ready(struct ixgbe_hw *hw); 56 int32_t ixgbe_check_mac_link_82598(struct ixgbe_hw *hw, 57 ixgbe_link_speed *speed, bool *link_up, 58 bool link_up_wait_to_complete); 59 int32_t ixgbe_setup_mac_link_82598(struct ixgbe_hw *hw, 60 ixgbe_link_speed speed, 61 bool autoneg_wait_to_complete); 62 int32_t ixgbe_setup_copper_link_82598(struct ixgbe_hw *hw, 63 ixgbe_link_speed speed, 64 bool autoneg_wait_to_complete); 65 int32_t ixgbe_reset_hw_82598(struct ixgbe_hw *hw); 66 int32_t ixgbe_start_hw_82598(struct ixgbe_hw *hw); 67 void ixgbe_enable_relaxed_ordering_82598(struct ixgbe_hw *hw); 68 int32_t ixgbe_set_vmdq_82598(struct ixgbe_hw *hw, uint32_t rar, uint32_t vmdq); 69 int32_t ixgbe_clear_vmdq_82598(struct ixgbe_hw *hw, uint32_t rar, uint32_t vmdq); 70 int32_t ixgbe_set_vfta_82598(struct ixgbe_hw *hw, uint32_t vlan, 71 uint32_t vind, bool vlan_on); 72 int32_t ixgbe_clear_vfta_82598(struct ixgbe_hw *hw); 73 int32_t ixgbe_read_analog_reg8_82598(struct ixgbe_hw *hw, uint32_t reg, uint8_t *val); 74 int32_t ixgbe_write_analog_reg8_82598(struct ixgbe_hw *hw, uint32_t reg, uint8_t val); 75 int32_t ixgbe_read_i2c_phy_82598(struct ixgbe_hw *hw, uint8_t dev_addr, 76 uint8_t byte_offset, uint8_t *eeprom_data); 77 int32_t ixgbe_read_i2c_eeprom_82598(struct ixgbe_hw *hw, uint8_t byte_offset, 78 uint8_t *eeprom_data); 79 uint32_t ixgbe_get_supported_physical_layer_82598(struct ixgbe_hw *hw); 80 int32_t ixgbe_init_phy_ops_82598(struct ixgbe_hw *hw); 81 void ixgbe_set_lan_id_multi_port_pcie_82598(struct ixgbe_hw *hw); 82 void ixgbe_set_pcie_completion_timeout(struct ixgbe_hw *hw); 83 int32_t ixgbe_enable_rx_dma_82598(struct ixgbe_hw *hw, uint32_t regval); 84 85 /** 86 * ixgbe_set_pcie_completion_timeout - set pci-e completion timeout 87 * @hw: pointer to the HW structure 88 * 89 * The defaults for 82598 should be in the range of 50us to 50ms, 90 * however the hardware default for these parts is 500us to 1ms which is less 91 * than the 10ms recommended by the pci-e spec. To address this we need to 92 * increase the value to either 10ms to 250ms for capability version 1 config, 93 * or 16ms to 55ms for version 2. 94 **/ 95 void ixgbe_set_pcie_completion_timeout(struct ixgbe_hw *hw) 96 { 97 uint32_t gcr = IXGBE_READ_REG(hw, IXGBE_GCR); 98 uint16_t pcie_devctl2; 99 100 /* only take action if timeout value is defaulted to 0 */ 101 if (gcr & IXGBE_GCR_CMPL_TMOUT_MASK) 102 goto out; 103 104 /* 105 * if capababilities version is type 1 we can write the 106 * timeout of 10ms to 250ms through the GCR register 107 */ 108 if (!(gcr & IXGBE_GCR_CAP_VER2)) { 109 gcr |= IXGBE_GCR_CMPL_TMOUT_10ms; 110 goto out; 111 } 112 113 /* 114 * for version 2 capabilities we need to write the config space 115 * directly in order to set the completion timeout value for 116 * 16ms to 55ms 117 */ 118 pcie_devctl2 = IXGBE_READ_PCIE_WORD(hw, IXGBE_PCI_DEVICE_CONTROL2); 119 pcie_devctl2 |= IXGBE_PCI_DEVICE_CONTROL2_16ms; 120 IXGBE_WRITE_PCIE_WORD(hw, IXGBE_PCI_DEVICE_CONTROL2, pcie_devctl2); 121 out: 122 /* disable completion timeout resend */ 123 gcr &= ~IXGBE_GCR_CMPL_TMOUT_RESEND; 124 IXGBE_WRITE_REG(hw, IXGBE_GCR, gcr); 125 } 126 127 /** 128 * ixgbe_init_ops_82598 - Inits func ptrs and MAC type 129 * @hw: pointer to hardware structure 130 * 131 * Initialize the function pointers and assign the MAC type for 82598. 132 * Does not touch the hardware. 133 **/ 134 int32_t ixgbe_init_ops_82598(struct ixgbe_hw *hw) 135 { 136 struct ixgbe_mac_info *mac = &hw->mac; 137 struct ixgbe_phy_info *phy = &hw->phy; 138 int32_t ret_val; 139 140 DEBUGFUNC("ixgbe_init_ops_82598"); 141 142 ret_val = ixgbe_init_phy_ops_generic(hw); 143 ret_val = ixgbe_init_ops_generic(hw); 144 145 /* PHY */ 146 phy->ops.init = ixgbe_init_phy_ops_82598; 147 148 /* MAC */ 149 mac->ops.start_hw = ixgbe_start_hw_82598; 150 mac->ops.reset_hw = ixgbe_reset_hw_82598; 151 mac->ops.get_media_type = ixgbe_get_media_type_82598; 152 mac->ops.get_supported_physical_layer = 153 ixgbe_get_supported_physical_layer_82598; 154 mac->ops.read_analog_reg8 = ixgbe_read_analog_reg8_82598; 155 mac->ops.write_analog_reg8 = ixgbe_write_analog_reg8_82598; 156 mac->ops.set_lan_id = ixgbe_set_lan_id_multi_port_pcie_82598; 157 mac->ops.enable_rx_dma = ixgbe_enable_rx_dma_82598; 158 159 /* RAR, Multicast, VLAN */ 160 mac->ops.set_vmdq = ixgbe_set_vmdq_82598; 161 mac->ops.clear_vmdq = ixgbe_clear_vmdq_82598; 162 mac->ops.set_vfta = ixgbe_set_vfta_82598; 163 mac->ops.clear_vfta = ixgbe_clear_vfta_82598; 164 165 /* Flow Control */ 166 mac->ops.fc_enable = ixgbe_fc_enable_82598; 167 168 mac->mcft_size = IXGBE_82598_MC_TBL_SIZE; 169 mac->vft_size = IXGBE_82598_VFT_TBL_SIZE; 170 mac->num_rar_entries = IXGBE_82598_RAR_ENTRIES; 171 mac->rx_pb_size = IXGBE_82598_RX_PB_SIZE; 172 mac->max_rx_queues = IXGBE_82598_MAX_RX_QUEUES; 173 mac->max_tx_queues = IXGBE_82598_MAX_TX_QUEUES; 174 mac->max_msix_vectors = ixgbe_get_pcie_msix_count_generic(hw); 175 176 /* SFP+ Module */ 177 phy->ops.read_i2c_eeprom = ixgbe_read_i2c_eeprom_82598; 178 179 /* Link */ 180 mac->ops.check_link = ixgbe_check_mac_link_82598; 181 mac->ops.setup_link = ixgbe_setup_mac_link_82598; 182 mac->ops.flap_tx_laser = NULL; 183 mac->ops.get_link_capabilities = ixgbe_get_link_capabilities_82598; 184 185 return ret_val; 186 } 187 188 /** 189 * ixgbe_init_phy_ops_82598 - PHY/SFP specific init 190 * @hw: pointer to hardware structure 191 * 192 * Initialize any function pointers that were not able to be 193 * set during init_shared_code because the PHY/SFP type was 194 * not known. Perform the SFP init if necessary. 195 * 196 **/ 197 int32_t ixgbe_init_phy_ops_82598(struct ixgbe_hw *hw) 198 { 199 struct ixgbe_mac_info *mac = &hw->mac; 200 struct ixgbe_phy_info *phy = &hw->phy; 201 int32_t ret_val = IXGBE_SUCCESS; 202 uint16_t list_offset, data_offset; 203 204 DEBUGFUNC("ixgbe_init_phy_ops_82598"); 205 206 /* Identify the PHY */ 207 phy->ops.identify(hw); 208 209 /* Overwrite the link function pointers if copper PHY */ 210 if (mac->ops.get_media_type(hw) == ixgbe_media_type_copper) { 211 mac->ops.setup_link = ixgbe_setup_copper_link_82598; 212 mac->ops.get_link_capabilities = 213 ixgbe_get_copper_link_capabilities_generic; 214 } 215 216 switch (hw->phy.type) { 217 case ixgbe_phy_tn: 218 phy->ops.setup_link = ixgbe_setup_phy_link_tnx; 219 phy->ops.check_link = ixgbe_check_phy_link_tnx; 220 phy->ops.get_firmware_version = 221 ixgbe_get_phy_firmware_version_tnx; 222 break; 223 case ixgbe_phy_nl: 224 phy->ops.reset = ixgbe_reset_phy_nl; 225 226 /* Call SFP+ identify routine to get the SFP+ module type */ 227 ret_val = phy->ops.identify_sfp(hw); 228 if (ret_val != IXGBE_SUCCESS) 229 goto out; 230 else if (hw->phy.sfp_type == ixgbe_sfp_type_unknown) { 231 ret_val = IXGBE_ERR_SFP_NOT_SUPPORTED; 232 goto out; 233 } 234 235 /* Check to see if SFP+ module is supported */ 236 ret_val = ixgbe_get_sfp_init_sequence_offsets(hw, 237 &list_offset, 238 &data_offset); 239 if (ret_val != IXGBE_SUCCESS) { 240 ret_val = IXGBE_ERR_SFP_NOT_SUPPORTED; 241 goto out; 242 } 243 break; 244 default: 245 break; 246 } 247 248 out: 249 return ret_val; 250 } 251 252 /** 253 * ixgbe_start_hw_82598 - Prepare hardware for Tx/Rx 254 * @hw: pointer to hardware structure 255 * 256 * Starts the hardware using the generic start_hw function. 257 * Disables relaxed ordering, then set pcie completion timeout 258 * 259 **/ 260 int32_t ixgbe_start_hw_82598(struct ixgbe_hw *hw) 261 { 262 uint32_t regval; 263 uint32_t i; 264 int32_t ret_val = IXGBE_SUCCESS; 265 266 DEBUGFUNC("ixgbe_start_hw_82598"); 267 268 ret_val = ixgbe_start_hw_generic(hw); 269 if (ret_val) 270 return ret_val; 271 272 /* Disable relaxed ordering */ 273 for (i = 0; ((i < hw->mac.max_tx_queues) && 274 (i < IXGBE_DCA_MAX_QUEUES_82598)); i++) { 275 regval = IXGBE_READ_REG(hw, IXGBE_DCA_TXCTRL(i)); 276 regval &= ~IXGBE_DCA_TXCTRL_DESC_WRO_EN; 277 IXGBE_WRITE_REG(hw, IXGBE_DCA_TXCTRL(i), regval); 278 } 279 280 for (i = 0; ((i < hw->mac.max_rx_queues) && 281 (i < IXGBE_DCA_MAX_QUEUES_82598)); i++) { 282 regval = IXGBE_READ_REG(hw, IXGBE_DCA_RXCTRL(i)); 283 regval &= ~(IXGBE_DCA_RXCTRL_DATA_WRO_EN | 284 IXGBE_DCA_RXCTRL_HEAD_WRO_EN); 285 IXGBE_WRITE_REG(hw, IXGBE_DCA_RXCTRL(i), regval); 286 } 287 288 /* set the completion timeout for interface */ 289 ixgbe_set_pcie_completion_timeout(hw); 290 291 return ret_val; 292 } 293 294 /** 295 * ixgbe_get_link_capabilities_82598 - Determines link capabilities 296 * @hw: pointer to hardware structure 297 * @speed: pointer to link speed 298 * @autoneg: boolean auto-negotiation value 299 * 300 * Determines the link capabilities by reading the AUTOC register. 301 **/ 302 int32_t ixgbe_get_link_capabilities_82598(struct ixgbe_hw *hw, 303 ixgbe_link_speed *speed, 304 bool *autoneg) 305 { 306 int32_t status = IXGBE_SUCCESS; 307 uint32_t autoc = 0; 308 309 DEBUGFUNC("ixgbe_get_link_capabilities_82598"); 310 311 /* 312 * Determine link capabilities based on the stored value of AUTOC, 313 * which represents EEPROM defaults. If AUTOC value has not been 314 * stored, use the current register value. 315 */ 316 if (hw->mac.orig_link_settings_stored) 317 autoc = hw->mac.orig_autoc; 318 else 319 autoc = IXGBE_READ_REG(hw, IXGBE_AUTOC); 320 321 switch (autoc & IXGBE_AUTOC_LMS_MASK) { 322 case IXGBE_AUTOC_LMS_1G_LINK_NO_AN: 323 *speed = IXGBE_LINK_SPEED_1GB_FULL; 324 *autoneg = FALSE; 325 break; 326 327 case IXGBE_AUTOC_LMS_10G_LINK_NO_AN: 328 *speed = IXGBE_LINK_SPEED_10GB_FULL; 329 *autoneg = FALSE; 330 break; 331 332 case IXGBE_AUTOC_LMS_1G_AN: 333 *speed = IXGBE_LINK_SPEED_1GB_FULL; 334 *autoneg = TRUE; 335 break; 336 337 case IXGBE_AUTOC_LMS_KX4_AN: 338 case IXGBE_AUTOC_LMS_KX4_AN_1G_AN: 339 *speed = IXGBE_LINK_SPEED_UNKNOWN; 340 if (autoc & IXGBE_AUTOC_KX4_SUPP) 341 *speed |= IXGBE_LINK_SPEED_10GB_FULL; 342 if (autoc & IXGBE_AUTOC_KX_SUPP) 343 *speed |= IXGBE_LINK_SPEED_1GB_FULL; 344 *autoneg = TRUE; 345 break; 346 347 default: 348 status = IXGBE_ERR_LINK_SETUP; 349 break; 350 } 351 352 return status; 353 } 354 355 /** 356 * ixgbe_get_media_type_82598 - Determines media type 357 * @hw: pointer to hardware structure 358 * 359 * Returns the media type (fiber, copper, backplane) 360 **/ 361 enum ixgbe_media_type ixgbe_get_media_type_82598(struct ixgbe_hw *hw) 362 { 363 enum ixgbe_media_type media_type; 364 365 DEBUGFUNC("ixgbe_get_media_type_82598"); 366 367 /* Detect if there is a copper PHY attached. */ 368 switch (hw->phy.type) { 369 case ixgbe_phy_cu_unknown: 370 case ixgbe_phy_tn: 371 media_type = ixgbe_media_type_copper; 372 goto out; 373 default: 374 break; 375 } 376 377 /* Media type for I82598 is based on device ID */ 378 switch (hw->device_id) { 379 case IXGBE_DEV_ID_82598: 380 case IXGBE_DEV_ID_82598_BX: 381 /* Default device ID is mezzanine card KX/KX4 */ 382 media_type = ixgbe_media_type_backplane; 383 break; 384 case IXGBE_DEV_ID_82598AF_DUAL_PORT: 385 case IXGBE_DEV_ID_82598AF_SINGLE_PORT: 386 case IXGBE_DEV_ID_82598_DA_DUAL_PORT: 387 case IXGBE_DEV_ID_82598_SR_DUAL_PORT_EM: 388 case IXGBE_DEV_ID_82598EB_XF_LR: 389 case IXGBE_DEV_ID_82598EB_SFP_LOM: 390 media_type = ixgbe_media_type_fiber; 391 break; 392 case IXGBE_DEV_ID_82598EB_CX4: 393 case IXGBE_DEV_ID_82598_CX4_DUAL_PORT: 394 media_type = ixgbe_media_type_cx4; 395 break; 396 case IXGBE_DEV_ID_82598AT: 397 case IXGBE_DEV_ID_82598AT2: 398 media_type = ixgbe_media_type_copper; 399 break; 400 default: 401 media_type = ixgbe_media_type_unknown; 402 break; 403 } 404 out: 405 return media_type; 406 } 407 408 /** 409 * ixgbe_fc_enable_82598 - Enable flow control 410 * @hw: pointer to hardware structure 411 * 412 * Enable flow control according to the current settings. 413 **/ 414 int32_t ixgbe_fc_enable_82598(struct ixgbe_hw *hw) 415 { 416 int32_t ret_val = IXGBE_SUCCESS; 417 uint32_t fctrl_reg; 418 uint32_t rmcs_reg; 419 uint32_t reg; 420 uint32_t fcrtl, fcrth; 421 uint32_t link_speed = 0; 422 int i; 423 bool link_up; 424 425 DEBUGFUNC("ixgbe_fc_enable_82598"); 426 427 /* Validate the water mark configuration */ 428 if (!hw->fc.pause_time) { 429 ret_val = IXGBE_ERR_INVALID_LINK_SETTINGS; 430 goto out; 431 } 432 433 /* Low water mark of zero causes XOFF floods */ 434 for (i = 0; i < IXGBE_DCB_MAX_TRAFFIC_CLASS; i++) { 435 if ((hw->fc.current_mode & ixgbe_fc_tx_pause) && 436 hw->fc.high_water[i]) { 437 if (!hw->fc.low_water[i] || 438 hw->fc.low_water[i] >= hw->fc.high_water[i]) { 439 DEBUGOUT("Invalid water mark configuration\n"); 440 ret_val = IXGBE_ERR_INVALID_LINK_SETTINGS; 441 goto out; 442 } 443 } 444 } 445 446 /* 447 * On 82598 having Rx FC on causes resets while doing 1G 448 * so if it's on turn it off once we know link_speed. For 449 * more details see 82598 Specification update. 450 */ 451 hw->mac.ops.check_link(hw, &link_speed, &link_up, FALSE); 452 if (link_up && link_speed == IXGBE_LINK_SPEED_1GB_FULL) { 453 switch (hw->fc.requested_mode) { 454 case ixgbe_fc_full: 455 hw->fc.requested_mode = ixgbe_fc_tx_pause; 456 break; 457 case ixgbe_fc_rx_pause: 458 hw->fc.requested_mode = ixgbe_fc_none; 459 break; 460 default: 461 /* no change */ 462 break; 463 } 464 } 465 466 /* Negotiate the fc mode to use */ 467 ixgbe_fc_autoneg(hw); 468 469 /* Disable any previous flow control settings */ 470 fctrl_reg = IXGBE_READ_REG(hw, IXGBE_FCTRL); 471 fctrl_reg &= ~(IXGBE_FCTRL_RFCE | IXGBE_FCTRL_RPFCE); 472 473 rmcs_reg = IXGBE_READ_REG(hw, IXGBE_RMCS); 474 rmcs_reg &= ~(IXGBE_RMCS_TFCE_PRIORITY | IXGBE_RMCS_TFCE_802_3X); 475 476 /* 477 * The possible values of fc.current_mode are: 478 * 0: Flow control is completely disabled 479 * 1: Rx flow control is enabled (we can receive pause frames, 480 * but not send pause frames). 481 * 2: Tx flow control is enabled (we can send pause frames but 482 * we do not support receiving pause frames). 483 * 3: Both Rx and Tx flow control (symmetric) are enabled. 484 * other: Invalid. 485 */ 486 switch (hw->fc.current_mode) { 487 case ixgbe_fc_none: 488 /* 489 * Flow control is disabled by software override or autoneg. 490 * The code below will actually disable it in the HW. 491 */ 492 break; 493 case ixgbe_fc_rx_pause: 494 /* 495 * Rx Flow control is enabled and Tx Flow control is 496 * disabled by software override. Since there really 497 * isn't a way to advertise that we are capable of RX 498 * Pause ONLY, we will advertise that we support both 499 * symmetric and asymmetric Rx PAUSE. Later, we will 500 * disable the adapter's ability to send PAUSE frames. 501 */ 502 fctrl_reg |= IXGBE_FCTRL_RFCE; 503 break; 504 case ixgbe_fc_tx_pause: 505 /* 506 * Tx Flow control is enabled, and Rx Flow control is 507 * disabled by software override. 508 */ 509 rmcs_reg |= IXGBE_RMCS_TFCE_802_3X; 510 break; 511 case ixgbe_fc_full: 512 /* Flow control (both Rx and Tx) is enabled by SW override. */ 513 fctrl_reg |= IXGBE_FCTRL_RFCE; 514 rmcs_reg |= IXGBE_RMCS_TFCE_802_3X; 515 break; 516 default: 517 DEBUGOUT("Flow control param set incorrectly\n"); 518 ret_val = IXGBE_ERR_CONFIG; 519 goto out; 520 break; 521 } 522 523 /* Set 802.3x based flow control settings. */ 524 fctrl_reg |= IXGBE_FCTRL_DPF; 525 IXGBE_WRITE_REG(hw, IXGBE_FCTRL, fctrl_reg); 526 IXGBE_WRITE_REG(hw, IXGBE_RMCS, rmcs_reg); 527 528 /* Set up and enable Rx high/low water mark thresholds, enable XON. */ 529 for (i = 0; i < IXGBE_DCB_MAX_TRAFFIC_CLASS; i++) { 530 if ((hw->fc.current_mode & ixgbe_fc_tx_pause) && 531 hw->fc.high_water[i]) { 532 fcrtl = (hw->fc.low_water[i] << 10) | IXGBE_FCRTL_XONE; 533 fcrth = (hw->fc.high_water[i] << 10) | IXGBE_FCRTH_FCEN; 534 IXGBE_WRITE_REG(hw, IXGBE_FCRTL(i), fcrtl); 535 IXGBE_WRITE_REG(hw, IXGBE_FCRTH(i), fcrth); 536 } else { 537 IXGBE_WRITE_REG(hw, IXGBE_FCRTL(i), 0); 538 IXGBE_WRITE_REG(hw, IXGBE_FCRTH(i), 0); 539 } 540 541 } 542 543 /* Configure pause time (2 TCs per register) */ 544 reg = hw->fc.pause_time * 0x00010001; 545 for (i = 0; i < (IXGBE_DCB_MAX_TRAFFIC_CLASS / 2); i++) 546 IXGBE_WRITE_REG(hw, IXGBE_FCTTV(i), reg); 547 548 /* Configure flow control refresh threshold value */ 549 IXGBE_WRITE_REG(hw, IXGBE_FCRTV, hw->fc.pause_time / 2); 550 551 out: 552 return ret_val; 553 } 554 555 /** 556 * ixgbe_start_mac_link_82598 - Configures MAC link settings 557 * @hw: pointer to hardware structure 558 * 559 * Configures link settings based on values in the ixgbe_hw struct. 560 * Restarts the link. Performs autonegotiation if needed. 561 **/ 562 int32_t ixgbe_start_mac_link_82598(struct ixgbe_hw *hw, 563 bool autoneg_wait_to_complete) 564 { 565 uint32_t autoc_reg; 566 uint32_t links_reg; 567 uint32_t i; 568 int32_t status = IXGBE_SUCCESS; 569 570 DEBUGFUNC("ixgbe_start_mac_link_82598"); 571 572 /* Restart link */ 573 autoc_reg = IXGBE_READ_REG(hw, IXGBE_AUTOC); 574 autoc_reg |= IXGBE_AUTOC_AN_RESTART; 575 IXGBE_WRITE_REG(hw, IXGBE_AUTOC, autoc_reg); 576 577 /* Only poll for autoneg to complete if specified to do so */ 578 if (autoneg_wait_to_complete) { 579 if ((autoc_reg & IXGBE_AUTOC_LMS_MASK) == 580 IXGBE_AUTOC_LMS_KX4_AN || 581 (autoc_reg & IXGBE_AUTOC_LMS_MASK) == 582 IXGBE_AUTOC_LMS_KX4_AN_1G_AN) { 583 links_reg = 0; /* Just in case Autoneg time = 0 */ 584 for (i = 0; i < IXGBE_AUTO_NEG_TIME; i++) { 585 links_reg = IXGBE_READ_REG(hw, IXGBE_LINKS); 586 if (links_reg & IXGBE_LINKS_KX_AN_COMP) 587 break; 588 msec_delay(100); 589 } 590 if (!(links_reg & IXGBE_LINKS_KX_AN_COMP)) { 591 status = IXGBE_ERR_AUTONEG_NOT_COMPLETE; 592 DEBUGOUT("Autonegotiation did not complete.\n"); 593 } 594 } 595 } 596 597 /* Add delay to filter out noises during initial link setup */ 598 msec_delay(50); 599 600 return status; 601 } 602 603 /** 604 * ixgbe_validate_link_ready - Function looks for phy link 605 * @hw: pointer to hardware structure 606 * 607 * Function indicates success when phy link is available. If phy is not ready 608 * within 5 seconds of MAC indicating link, the function returns error. 609 **/ 610 int32_t ixgbe_validate_link_ready(struct ixgbe_hw *hw) 611 { 612 uint32_t timeout; 613 uint16_t an_reg; 614 615 if (hw->device_id != IXGBE_DEV_ID_82598AT2) 616 return IXGBE_SUCCESS; 617 618 for (timeout = 0; 619 timeout < IXGBE_VALIDATE_LINK_READY_TIMEOUT; timeout++) { 620 hw->phy.ops.read_reg(hw, IXGBE_MDIO_AUTO_NEG_STATUS, 621 IXGBE_MDIO_AUTO_NEG_DEV_TYPE, &an_reg); 622 623 if ((an_reg & IXGBE_MII_AUTONEG_COMPLETE) && 624 (an_reg & IXGBE_MII_AUTONEG_LINK_UP)) 625 break; 626 627 msec_delay(100); 628 } 629 630 if (timeout == IXGBE_VALIDATE_LINK_READY_TIMEOUT) { 631 DEBUGOUT("Link was indicated but link is down\n"); 632 return IXGBE_ERR_LINK_SETUP; 633 } 634 635 return IXGBE_SUCCESS; 636 } 637 638 /** 639 * ixgbe_check_mac_link_82598 - Get link/speed status 640 * @hw: pointer to hardware structure 641 * @speed: pointer to link speed 642 * @link_up: TRUE is link is up, FALSE otherwise 643 * @link_up_wait_to_complete: bool used to wait for link up or not 644 * 645 * Reads the links register to determine if link is up and the current speed 646 **/ 647 int32_t ixgbe_check_mac_link_82598(struct ixgbe_hw *hw, 648 ixgbe_link_speed *speed, bool *link_up, 649 bool link_up_wait_to_complete) 650 { 651 uint32_t links_reg; 652 uint32_t i; 653 uint16_t link_reg, adapt_comp_reg; 654 655 DEBUGFUNC("ixgbe_check_mac_link_82598"); 656 657 /* 658 * SERDES PHY requires us to read link status from undocumented 659 * register 0xC79F. Bit 0 set indicates link is up/ready; clear 660 * indicates link down. OxC00C is read to check that the XAUI lanes 661 * are active. Bit 0 clear indicates active; set indicates inactive. 662 */ 663 if (hw->phy.type == ixgbe_phy_nl) { 664 hw->phy.ops.read_reg(hw, 0xC79F, IXGBE_TWINAX_DEV, &link_reg); 665 hw->phy.ops.read_reg(hw, 0xC79F, IXGBE_TWINAX_DEV, &link_reg); 666 hw->phy.ops.read_reg(hw, 0xC00C, IXGBE_TWINAX_DEV, 667 &adapt_comp_reg); 668 if (link_up_wait_to_complete) { 669 for (i = 0; i < hw->mac.max_link_up_time; i++) { 670 if ((link_reg & 1) && 671 ((adapt_comp_reg & 1) == 0)) { 672 *link_up = TRUE; 673 break; 674 } else { 675 *link_up = FALSE; 676 } 677 msec_delay(100); 678 hw->phy.ops.read_reg(hw, 0xC79F, 679 IXGBE_TWINAX_DEV, 680 &link_reg); 681 hw->phy.ops.read_reg(hw, 0xC00C, 682 IXGBE_TWINAX_DEV, 683 &adapt_comp_reg); 684 } 685 } else { 686 if ((link_reg & 1) && ((adapt_comp_reg & 1) == 0)) 687 *link_up = TRUE; 688 else 689 *link_up = FALSE; 690 } 691 692 if (*link_up == FALSE) 693 goto out; 694 } 695 696 links_reg = IXGBE_READ_REG(hw, IXGBE_LINKS); 697 if (link_up_wait_to_complete) { 698 for (i = 0; i < hw->mac.max_link_up_time; i++) { 699 if (links_reg & IXGBE_LINKS_UP) { 700 *link_up = TRUE; 701 break; 702 } else { 703 *link_up = FALSE; 704 } 705 msec_delay(100); 706 links_reg = IXGBE_READ_REG(hw, IXGBE_LINKS); 707 } 708 } else { 709 if (links_reg & IXGBE_LINKS_UP) 710 *link_up = TRUE; 711 else 712 *link_up = FALSE; 713 } 714 715 if (links_reg & IXGBE_LINKS_SPEED) 716 *speed = IXGBE_LINK_SPEED_10GB_FULL; 717 else 718 *speed = IXGBE_LINK_SPEED_1GB_FULL; 719 720 if ((hw->device_id == IXGBE_DEV_ID_82598AT2) && (*link_up == TRUE) && 721 (ixgbe_validate_link_ready(hw) != IXGBE_SUCCESS)) 722 *link_up = FALSE; 723 724 out: 725 return IXGBE_SUCCESS; 726 } 727 728 /** 729 * ixgbe_setup_mac_link_82598 - Set MAC link speed 730 * @hw: pointer to hardware structure 731 * @speed: new link speed 732 * @autoneg_wait_to_complete: TRUE when waiting for completion is needed 733 * 734 * Set the link speed in the AUTOC register and restarts link. 735 **/ 736 int32_t ixgbe_setup_mac_link_82598(struct ixgbe_hw *hw, 737 ixgbe_link_speed speed, 738 bool autoneg_wait_to_complete) 739 { 740 bool autoneg = FALSE; 741 int32_t status = IXGBE_SUCCESS; 742 ixgbe_link_speed link_capabilities = IXGBE_LINK_SPEED_UNKNOWN; 743 uint32_t curr_autoc = IXGBE_READ_REG(hw, IXGBE_AUTOC); 744 uint32_t autoc = curr_autoc; 745 uint32_t link_mode = autoc & IXGBE_AUTOC_LMS_MASK; 746 747 DEBUGFUNC("ixgbe_setup_mac_link_82598"); 748 749 /* Check to see if speed passed in is supported. */ 750 ixgbe_get_link_capabilities_82598(hw, &link_capabilities, &autoneg); 751 speed &= link_capabilities; 752 753 if (speed == IXGBE_LINK_SPEED_UNKNOWN) 754 status = IXGBE_ERR_LINK_SETUP; 755 756 /* Set KX4/KX support according to speed requested */ 757 else if (link_mode == IXGBE_AUTOC_LMS_KX4_AN || 758 link_mode == IXGBE_AUTOC_LMS_KX4_AN_1G_AN) { 759 autoc &= ~IXGBE_AUTOC_KX4_KX_SUPP_MASK; 760 if (speed & IXGBE_LINK_SPEED_10GB_FULL) 761 autoc |= IXGBE_AUTOC_KX4_SUPP; 762 if (speed & IXGBE_LINK_SPEED_1GB_FULL) 763 autoc |= IXGBE_AUTOC_KX_SUPP; 764 if (autoc != curr_autoc) 765 IXGBE_WRITE_REG(hw, IXGBE_AUTOC, autoc); 766 } 767 768 if (status == IXGBE_SUCCESS) { 769 /* 770 * Setup and restart the link based on the new values in 771 * ixgbe_hw This will write the AUTOC register based on the new 772 * stored values 773 */ 774 status = ixgbe_start_mac_link_82598(hw, 775 autoneg_wait_to_complete); 776 } 777 778 return status; 779 } 780 781 782 /** 783 * ixgbe_setup_copper_link_82598 - Set the PHY autoneg advertised field 784 * @hw: pointer to hardware structure 785 * @speed: new link speed 786 * @autoneg_wait_to_complete: TRUE if waiting is needed to complete 787 * 788 * Sets the link speed in the AUTOC register in the MAC and restarts link. 789 **/ 790 int32_t ixgbe_setup_copper_link_82598(struct ixgbe_hw *hw, 791 ixgbe_link_speed speed, 792 bool autoneg_wait_to_complete) 793 { 794 int32_t status; 795 796 DEBUGFUNC("ixgbe_setup_copper_link_82598"); 797 798 /* Setup the PHY according to input speed */ 799 status = hw->phy.ops.setup_link_speed(hw, speed, 800 autoneg_wait_to_complete); 801 /* Set up MAC */ 802 ixgbe_start_mac_link_82598(hw, autoneg_wait_to_complete); 803 804 return status; 805 } 806 807 /** 808 * ixgbe_reset_hw_82598 - Performs hardware reset 809 * @hw: pointer to hardware structure 810 * 811 * Resets the hardware by resetting the transmit and receive units, masks and 812 * clears all interrupts, performing a PHY reset, and performing a link (MAC) 813 * reset. 814 **/ 815 int32_t ixgbe_reset_hw_82598(struct ixgbe_hw *hw) 816 { 817 int32_t status = IXGBE_SUCCESS; 818 int32_t phy_status = IXGBE_SUCCESS; 819 uint32_t ctrl; 820 uint32_t gheccr; 821 uint32_t i; 822 uint32_t autoc; 823 uint8_t analog_val; 824 825 DEBUGFUNC("ixgbe_reset_hw_82598"); 826 827 /* Call adapter stop to disable tx/rx and clear interrupts */ 828 status = hw->mac.ops.stop_adapter(hw); 829 if (status != IXGBE_SUCCESS) 830 goto reset_hw_out; 831 832 /* 833 * Power up the Atlas Tx lanes if they are currently powered down. 834 * Atlas Tx lanes are powered down for MAC loopback tests, but 835 * they are not automatically restored on reset. 836 */ 837 hw->mac.ops.read_analog_reg8(hw, IXGBE_ATLAS_PDN_LPBK, &analog_val); 838 if (analog_val & IXGBE_ATLAS_PDN_TX_REG_EN) { 839 /* Enable Tx Atlas so packets can be transmitted again */ 840 hw->mac.ops.read_analog_reg8(hw, IXGBE_ATLAS_PDN_LPBK, 841 &analog_val); 842 analog_val &= ~IXGBE_ATLAS_PDN_TX_REG_EN; 843 hw->mac.ops.write_analog_reg8(hw, IXGBE_ATLAS_PDN_LPBK, 844 analog_val); 845 846 hw->mac.ops.read_analog_reg8(hw, IXGBE_ATLAS_PDN_10G, 847 &analog_val); 848 analog_val &= ~IXGBE_ATLAS_PDN_TX_10G_QL_ALL; 849 hw->mac.ops.write_analog_reg8(hw, IXGBE_ATLAS_PDN_10G, 850 analog_val); 851 852 hw->mac.ops.read_analog_reg8(hw, IXGBE_ATLAS_PDN_1G, 853 &analog_val); 854 analog_val &= ~IXGBE_ATLAS_PDN_TX_1G_QL_ALL; 855 hw->mac.ops.write_analog_reg8(hw, IXGBE_ATLAS_PDN_1G, 856 analog_val); 857 858 hw->mac.ops.read_analog_reg8(hw, IXGBE_ATLAS_PDN_AN, 859 &analog_val); 860 analog_val &= ~IXGBE_ATLAS_PDN_TX_AN_QL_ALL; 861 hw->mac.ops.write_analog_reg8(hw, IXGBE_ATLAS_PDN_AN, 862 analog_val); 863 } 864 865 /* Reset PHY */ 866 if (hw->phy.reset_disable == FALSE) { 867 /* PHY ops must be identified and initialized prior to reset */ 868 869 /* Init PHY and function pointers, perform SFP setup */ 870 phy_status = hw->phy.ops.init(hw); 871 if (phy_status == IXGBE_ERR_SFP_NOT_SUPPORTED) 872 goto reset_hw_out; 873 if (phy_status == IXGBE_ERR_SFP_NOT_PRESENT) 874 goto mac_reset_top; 875 876 hw->phy.ops.reset(hw); 877 } 878 879 mac_reset_top: 880 /* 881 * Issue global reset to the MAC. This needs to be a SW reset. 882 * If link reset is used, it might reset the MAC when mng is using it 883 */ 884 ctrl = IXGBE_READ_REG(hw, IXGBE_CTRL) | IXGBE_CTRL_RST; 885 IXGBE_WRITE_REG(hw, IXGBE_CTRL, ctrl); 886 IXGBE_WRITE_FLUSH(hw); 887 888 /* Poll for reset bit to self-clear indicating reset is complete */ 889 for (i = 0; i < 10; i++) { 890 usec_delay(1); 891 ctrl = IXGBE_READ_REG(hw, IXGBE_CTRL); 892 if (!(ctrl & IXGBE_CTRL_RST)) 893 break; 894 } 895 if (ctrl & IXGBE_CTRL_RST) { 896 status = IXGBE_ERR_RESET_FAILED; 897 DEBUGOUT("Reset polling failed to complete.\n"); 898 } 899 900 msec_delay(50); 901 902 /* 903 * Double resets are required for recovery from certain error 904 * conditions. Between resets, it is necessary to stall to allow time 905 * for any pending HW events to complete. 906 */ 907 if (hw->mac.flags & IXGBE_FLAGS_DOUBLE_RESET_REQUIRED) { 908 hw->mac.flags &= ~IXGBE_FLAGS_DOUBLE_RESET_REQUIRED; 909 goto mac_reset_top; 910 } 911 912 gheccr = IXGBE_READ_REG(hw, IXGBE_GHECCR); 913 gheccr &= ~((1 << 21) | (1 << 18) | (1 << 9) | (1 << 6)); 914 IXGBE_WRITE_REG(hw, IXGBE_GHECCR, gheccr); 915 916 /* 917 * Store the original AUTOC value if it has not been 918 * stored off yet. Otherwise restore the stored original 919 * AUTOC value since the reset operation sets back to deaults. 920 */ 921 autoc = IXGBE_READ_REG(hw, IXGBE_AUTOC); 922 if (hw->mac.orig_link_settings_stored == FALSE) { 923 hw->mac.orig_autoc = autoc; 924 hw->mac.orig_link_settings_stored = TRUE; 925 } else if (autoc != hw->mac.orig_autoc) { 926 IXGBE_WRITE_REG(hw, IXGBE_AUTOC, hw->mac.orig_autoc); 927 } 928 929 /* Store the permanent mac address */ 930 hw->mac.ops.get_mac_addr(hw, hw->mac.perm_addr); 931 932 /* 933 * Store MAC address from RAR0, clear receive address registers, and 934 * clear the multicast table 935 */ 936 hw->mac.ops.init_rx_addrs(hw); 937 938 reset_hw_out: 939 if (phy_status != IXGBE_SUCCESS) 940 status = phy_status; 941 942 return status; 943 } 944 945 /** 946 * ixgbe_set_vmdq_82598 - Associate a VMDq set index with a rx address 947 * @hw: pointer to hardware struct 948 * @rar: receive address register index to associate with a VMDq index 949 * @vmdq: VMDq set index 950 **/ 951 int32_t ixgbe_set_vmdq_82598(struct ixgbe_hw *hw, uint32_t rar, uint32_t vmdq) 952 { 953 uint32_t rar_high; 954 uint32_t rar_entries = hw->mac.num_rar_entries; 955 956 DEBUGFUNC("ixgbe_set_vmdq_82598"); 957 958 /* Make sure we are using a valid rar index range */ 959 if (rar >= rar_entries) { 960 DEBUGOUT1("RAR index %d is out of range.\n", rar); 961 return IXGBE_ERR_INVALID_ARGUMENT; 962 } 963 964 rar_high = IXGBE_READ_REG(hw, IXGBE_RAH(rar)); 965 rar_high &= ~IXGBE_RAH_VIND_MASK; 966 rar_high |= ((vmdq << IXGBE_RAH_VIND_SHIFT) & IXGBE_RAH_VIND_MASK); 967 IXGBE_WRITE_REG(hw, IXGBE_RAH(rar), rar_high); 968 return IXGBE_SUCCESS; 969 } 970 971 /** 972 * ixgbe_clear_vmdq_82598 - Disassociate a VMDq set index from an rx address 973 * @hw: pointer to hardware struct 974 * @rar: receive address register index to associate with a VMDq index 975 * @vmdq: VMDq clear index (not used in 82598, but elsewhere) 976 **/ 977 int32_t ixgbe_clear_vmdq_82598(struct ixgbe_hw *hw, uint32_t rar, uint32_t vmdq) 978 { 979 uint32_t rar_high; 980 uint32_t rar_entries = hw->mac.num_rar_entries; 981 982 /* Make sure we are using a valid rar index range */ 983 if (rar >= rar_entries) { 984 DEBUGOUT1("RAR index %d is out of range.\n", rar); 985 return IXGBE_ERR_INVALID_ARGUMENT; 986 } 987 988 rar_high = IXGBE_READ_REG(hw, IXGBE_RAH(rar)); 989 if (rar_high & IXGBE_RAH_VIND_MASK) { 990 rar_high &= ~IXGBE_RAH_VIND_MASK; 991 IXGBE_WRITE_REG(hw, IXGBE_RAH(rar), rar_high); 992 } 993 994 return IXGBE_SUCCESS; 995 } 996 997 /** 998 * ixgbe_set_vfta_82598 - Set VLAN filter table 999 * @hw: pointer to hardware structure 1000 * @vlan: VLAN id to write to VLAN filter 1001 * @vind: VMDq output index that maps queue to VLAN id in VFTA 1002 * @vlan_on: boolean flag to turn on/off VLAN in VFTA 1003 * 1004 * Turn on/off specified VLAN in the VLAN filter table. 1005 **/ 1006 int32_t ixgbe_set_vfta_82598(struct ixgbe_hw *hw, uint32_t vlan, uint32_t vind, 1007 bool vlan_on) 1008 { 1009 uint32_t regindex; 1010 uint32_t bitindex; 1011 uint32_t bits; 1012 uint32_t vftabyte; 1013 1014 DEBUGFUNC("ixgbe_set_vfta_82598"); 1015 1016 if (vlan > 4095) 1017 return IXGBE_ERR_PARAM; 1018 1019 /* Determine 32-bit word position in array */ 1020 regindex = (vlan >> 5) & 0x7F; /* upper seven bits */ 1021 1022 /* Determine the location of the (VMD) queue index */ 1023 vftabyte = ((vlan >> 3) & 0x03); /* bits (4:3) indicating byte array */ 1024 bitindex = (vlan & 0x7) << 2; /* lower 3 bits indicate nibble */ 1025 1026 /* Set the nibble for VMD queue index */ 1027 bits = IXGBE_READ_REG(hw, IXGBE_VFTAVIND(vftabyte, regindex)); 1028 bits &= (~(0x0F << bitindex)); 1029 bits |= (vind << bitindex); 1030 IXGBE_WRITE_REG(hw, IXGBE_VFTAVIND(vftabyte, regindex), bits); 1031 1032 /* Determine the location of the bit for this VLAN id */ 1033 bitindex = vlan & 0x1F; /* lower five bits */ 1034 1035 bits = IXGBE_READ_REG(hw, IXGBE_VFTA(regindex)); 1036 if (vlan_on) 1037 /* Turn on this VLAN id */ 1038 bits |= (1 << bitindex); 1039 else 1040 /* Turn off this VLAN id */ 1041 bits &= ~(1 << bitindex); 1042 IXGBE_WRITE_REG(hw, IXGBE_VFTA(regindex), bits); 1043 1044 return IXGBE_SUCCESS; 1045 } 1046 1047 /** 1048 * ixgbe_clear_vfta_82598 - Clear VLAN filter table 1049 * @hw: pointer to hardware structure 1050 * 1051 * Clears the VLAN filer table, and the VMDq index associated with the filter 1052 **/ 1053 int32_t ixgbe_clear_vfta_82598(struct ixgbe_hw *hw) 1054 { 1055 uint32_t offset; 1056 uint32_t vlanbyte; 1057 1058 DEBUGFUNC("ixgbe_clear_vfta_82598"); 1059 1060 for (offset = 0; offset < hw->mac.vft_size; offset++) 1061 IXGBE_WRITE_REG(hw, IXGBE_VFTA(offset), 0); 1062 1063 for (vlanbyte = 0; vlanbyte < 4; vlanbyte++) 1064 for (offset = 0; offset < hw->mac.vft_size; offset++) 1065 IXGBE_WRITE_REG(hw, IXGBE_VFTAVIND(vlanbyte, offset), 1066 0); 1067 1068 return IXGBE_SUCCESS; 1069 } 1070 1071 /** 1072 * ixgbe_read_analog_reg8_82598 - Reads 8 bit Atlas analog register 1073 * @hw: pointer to hardware structure 1074 * @reg: analog register to read 1075 * @val: read value 1076 * 1077 * Performs read operation to Atlas analog register specified. 1078 **/ 1079 int32_t ixgbe_read_analog_reg8_82598(struct ixgbe_hw *hw, uint32_t reg, uint8_t *val) 1080 { 1081 uint32_t atlas_ctl; 1082 1083 DEBUGFUNC("ixgbe_read_analog_reg8_82598"); 1084 1085 IXGBE_WRITE_REG(hw, IXGBE_ATLASCTL, 1086 IXGBE_ATLASCTL_WRITE_CMD | (reg << 8)); 1087 IXGBE_WRITE_FLUSH(hw); 1088 usec_delay(10); 1089 atlas_ctl = IXGBE_READ_REG(hw, IXGBE_ATLASCTL); 1090 *val = (uint8_t)atlas_ctl; 1091 1092 return IXGBE_SUCCESS; 1093 } 1094 1095 /** 1096 * ixgbe_write_analog_reg8_82598 - Writes 8 bit Atlas analog register 1097 * @hw: pointer to hardware structure 1098 * @reg: atlas register to write 1099 * @val: value to write 1100 * 1101 * Performs write operation to Atlas analog register specified. 1102 **/ 1103 int32_t ixgbe_write_analog_reg8_82598(struct ixgbe_hw *hw, uint32_t reg, uint8_t val) 1104 { 1105 uint32_t atlas_ctl; 1106 1107 DEBUGFUNC("ixgbe_write_analog_reg8_82598"); 1108 1109 atlas_ctl = (reg << 8) | val; 1110 IXGBE_WRITE_REG(hw, IXGBE_ATLASCTL, atlas_ctl); 1111 IXGBE_WRITE_FLUSH(hw); 1112 usec_delay(10); 1113 1114 return IXGBE_SUCCESS; 1115 } 1116 1117 /** 1118 * ixgbe_read_i2c_phy_82598 - Reads 8 bit word over I2C interface. 1119 * @hw: pointer to hardware structure 1120 * @dev_addr: address to read from 1121 * @byte_offset: byte offset to read from dev_addr 1122 * @eeprom_data: value read 1123 * 1124 * Performs 8 byte read operation to SFP module's EEPROM over I2C interface. 1125 **/ 1126 int32_t ixgbe_read_i2c_phy_82598(struct ixgbe_hw *hw, uint8_t dev_addr, 1127 uint8_t byte_offset, uint8_t *eeprom_data) 1128 { 1129 int32_t status = IXGBE_SUCCESS; 1130 uint16_t sfp_addr = 0; 1131 uint16_t sfp_data = 0; 1132 uint16_t sfp_stat = 0; 1133 uint16_t gssr; 1134 uint32_t i; 1135 1136 DEBUGFUNC("ixgbe_read_i2c_phy_82598"); 1137 1138 if (IXGBE_READ_REG(hw, IXGBE_STATUS) & IXGBE_STATUS_LAN_ID_1) 1139 gssr = IXGBE_GSSR_PHY1_SM; 1140 else 1141 gssr = IXGBE_GSSR_PHY0_SM; 1142 1143 if (hw->mac.ops.acquire_swfw_sync(hw, gssr) != IXGBE_SUCCESS) 1144 return IXGBE_ERR_SWFW_SYNC; 1145 1146 if (hw->phy.type == ixgbe_phy_nl) { 1147 /* 1148 * NetLogic phy SDA/SCL registers are at addresses 0xC30A to 1149 * 0xC30D. These registers are used to talk to the SFP+ 1150 * module's EEPROM through the SDA/SCL (I2C) interface. 1151 */ 1152 sfp_addr = (dev_addr << 8) + byte_offset; 1153 sfp_addr = (sfp_addr | IXGBE_I2C_EEPROM_READ_MASK); 1154 hw->phy.ops.write_reg_mdi(hw, 1155 IXGBE_MDIO_PMA_PMD_SDA_SCL_ADDR, 1156 IXGBE_MDIO_PMA_PMD_DEV_TYPE, 1157 sfp_addr); 1158 1159 /* Poll status */ 1160 for (i = 0; i < 100; i++) { 1161 hw->phy.ops.read_reg_mdi(hw, 1162 IXGBE_MDIO_PMA_PMD_SDA_SCL_STAT, 1163 IXGBE_MDIO_PMA_PMD_DEV_TYPE, 1164 &sfp_stat); 1165 sfp_stat = sfp_stat & IXGBE_I2C_EEPROM_STATUS_MASK; 1166 if (sfp_stat != IXGBE_I2C_EEPROM_STATUS_IN_PROGRESS) 1167 break; 1168 msec_delay(10); 1169 } 1170 1171 if (sfp_stat != IXGBE_I2C_EEPROM_STATUS_PASS) { 1172 DEBUGOUT("EEPROM read did not pass.\n"); 1173 status = IXGBE_ERR_SFP_NOT_PRESENT; 1174 goto out; 1175 } 1176 1177 /* Read data */ 1178 hw->phy.ops.read_reg_mdi(hw, IXGBE_MDIO_PMA_PMD_SDA_SCL_DATA, 1179 IXGBE_MDIO_PMA_PMD_DEV_TYPE, &sfp_data); 1180 1181 *eeprom_data = (uint8_t)(sfp_data >> 8); 1182 } else { 1183 status = IXGBE_ERR_PHY; 1184 } 1185 1186 out: 1187 hw->mac.ops.release_swfw_sync(hw, gssr); 1188 return status; 1189 } 1190 1191 /** 1192 * ixgbe_read_i2c_eeprom_82598 - Reads 8 bit word over I2C interface. 1193 * @hw: pointer to hardware structure 1194 * @byte_offset: EEPROM byte offset to read 1195 * @eeprom_data: value read 1196 * 1197 * Performs 8 byte read operation to SFP module's EEPROM over I2C interface. 1198 **/ 1199 int32_t ixgbe_read_i2c_eeprom_82598(struct ixgbe_hw *hw, uint8_t byte_offset, 1200 uint8_t *eeprom_data) 1201 { 1202 return ixgbe_read_i2c_phy_82598(hw, IXGBE_I2C_EEPROM_DEV_ADDR, 1203 byte_offset, eeprom_data); 1204 } 1205 1206 /** 1207 * ixgbe_get_supported_physical_layer_82598 - Returns physical layer type 1208 * @hw: pointer to hardware structure 1209 * 1210 * Determines physical layer capabilities of the current configuration. 1211 **/ 1212 uint32_t ixgbe_get_supported_physical_layer_82598(struct ixgbe_hw *hw) 1213 { 1214 uint32_t physical_layer = IXGBE_PHYSICAL_LAYER_UNKNOWN; 1215 uint32_t autoc = IXGBE_READ_REG(hw, IXGBE_AUTOC); 1216 uint32_t pma_pmd_10g = autoc & IXGBE_AUTOC_10G_PMA_PMD_MASK; 1217 uint32_t pma_pmd_1g = autoc & IXGBE_AUTOC_1G_PMA_PMD_MASK; 1218 uint16_t ext_ability = 0; 1219 1220 DEBUGFUNC("ixgbe_get_supported_physical_layer_82598"); 1221 1222 hw->phy.ops.identify(hw); 1223 1224 /* Copper PHY must be checked before AUTOC LMS to determine correct 1225 * physical layer because 10GBase-T PHYs use LMS = KX4/KX */ 1226 switch (hw->phy.type) { 1227 case ixgbe_phy_tn: 1228 case ixgbe_phy_cu_unknown: 1229 hw->phy.ops.read_reg(hw, IXGBE_MDIO_PHY_EXT_ABILITY, 1230 IXGBE_MDIO_PMA_PMD_DEV_TYPE, &ext_ability); 1231 if (ext_ability & IXGBE_MDIO_PHY_10GBASET_ABILITY) 1232 physical_layer |= IXGBE_PHYSICAL_LAYER_10GBASE_T; 1233 if (ext_ability & IXGBE_MDIO_PHY_1000BASET_ABILITY) 1234 physical_layer |= IXGBE_PHYSICAL_LAYER_1000BASE_T; 1235 if (ext_ability & IXGBE_MDIO_PHY_100BASETX_ABILITY) 1236 physical_layer |= IXGBE_PHYSICAL_LAYER_100BASE_TX; 1237 goto out; 1238 default: 1239 break; 1240 } 1241 1242 switch (autoc & IXGBE_AUTOC_LMS_MASK) { 1243 case IXGBE_AUTOC_LMS_1G_AN: 1244 case IXGBE_AUTOC_LMS_1G_LINK_NO_AN: 1245 if (pma_pmd_1g == IXGBE_AUTOC_1G_KX) 1246 physical_layer = IXGBE_PHYSICAL_LAYER_1000BASE_KX; 1247 else 1248 physical_layer = IXGBE_PHYSICAL_LAYER_1000BASE_BX; 1249 break; 1250 case IXGBE_AUTOC_LMS_10G_LINK_NO_AN: 1251 if (pma_pmd_10g == IXGBE_AUTOC_10G_CX4) 1252 physical_layer = IXGBE_PHYSICAL_LAYER_10GBASE_CX4; 1253 else if (pma_pmd_10g == IXGBE_AUTOC_10G_KX4) 1254 physical_layer = IXGBE_PHYSICAL_LAYER_10GBASE_KX4; 1255 else { /* XAUI */ 1256 if (autoc & IXGBE_AUTOC_KX_SUPP) 1257 physical_layer |= 1258 IXGBE_PHYSICAL_LAYER_1000BASE_KX; 1259 if (autoc & IXGBE_AUTOC_KX4_SUPP) 1260 physical_layer |= 1261 IXGBE_PHYSICAL_LAYER_10GBASE_KX4; 1262 } 1263 break; 1264 case IXGBE_AUTOC_LMS_KX4_AN: 1265 case IXGBE_AUTOC_LMS_KX4_AN_1G_AN: 1266 if (autoc & IXGBE_AUTOC_KX_SUPP) 1267 physical_layer |= IXGBE_PHYSICAL_LAYER_1000BASE_KX; 1268 if (autoc & IXGBE_AUTOC_KX4_SUPP) 1269 physical_layer |= IXGBE_PHYSICAL_LAYER_10GBASE_KX4; 1270 break; 1271 default: 1272 break; 1273 } 1274 1275 if (hw->phy.type == ixgbe_phy_nl) { 1276 hw->phy.ops.identify_sfp(hw); 1277 1278 switch (hw->phy.sfp_type) { 1279 case ixgbe_sfp_type_da_cu: 1280 physical_layer = IXGBE_PHYSICAL_LAYER_SFP_PLUS_CU; 1281 break; 1282 case ixgbe_sfp_type_sr: 1283 physical_layer = IXGBE_PHYSICAL_LAYER_10GBASE_SR; 1284 break; 1285 case ixgbe_sfp_type_lr: 1286 physical_layer = IXGBE_PHYSICAL_LAYER_10GBASE_LR; 1287 break; 1288 default: 1289 physical_layer = IXGBE_PHYSICAL_LAYER_UNKNOWN; 1290 break; 1291 } 1292 } 1293 1294 switch (hw->device_id) { 1295 case IXGBE_DEV_ID_82598_DA_DUAL_PORT: 1296 physical_layer = IXGBE_PHYSICAL_LAYER_SFP_PLUS_CU; 1297 break; 1298 case IXGBE_DEV_ID_82598AF_DUAL_PORT: 1299 case IXGBE_DEV_ID_82598AF_SINGLE_PORT: 1300 case IXGBE_DEV_ID_82598_SR_DUAL_PORT_EM: 1301 physical_layer = IXGBE_PHYSICAL_LAYER_10GBASE_SR; 1302 break; 1303 case IXGBE_DEV_ID_82598EB_XF_LR: 1304 physical_layer = IXGBE_PHYSICAL_LAYER_10GBASE_LR; 1305 break; 1306 default: 1307 break; 1308 } 1309 1310 out: 1311 return physical_layer; 1312 } 1313 1314 /** 1315 * ixgbe_set_lan_id_multi_port_pcie_82598 - Set LAN id for PCIe multiple 1316 * port devices. 1317 * @hw: pointer to the HW structure 1318 * 1319 * Calls common function and corrects issue with some single port devices 1320 * that enable LAN1 but not LAN0. 1321 **/ 1322 void ixgbe_set_lan_id_multi_port_pcie_82598(struct ixgbe_hw *hw) 1323 { 1324 struct ixgbe_bus_info *bus = &hw->bus; 1325 uint16_t pci_gen = 0; 1326 uint16_t pci_ctrl2 = 0; 1327 1328 DEBUGFUNC("ixgbe_set_lan_id_multi_port_pcie_82598"); 1329 1330 ixgbe_set_lan_id_multi_port_pcie(hw); 1331 1332 /* check if LAN0 is disabled */ 1333 hw->eeprom.ops.read(hw, IXGBE_PCIE_GENERAL_PTR, &pci_gen); 1334 if ((pci_gen != 0) && (pci_gen != 0xFFFF)) { 1335 1336 hw->eeprom.ops.read(hw, pci_gen + IXGBE_PCIE_CTRL2, &pci_ctrl2); 1337 1338 /* if LAN0 is completely disabled force function to 0 */ 1339 if ((pci_ctrl2 & IXGBE_PCIE_CTRL2_LAN_DISABLE) && 1340 !(pci_ctrl2 & IXGBE_PCIE_CTRL2_DISABLE_SELECT) && 1341 !(pci_ctrl2 & IXGBE_PCIE_CTRL2_DUMMY_ENABLE)) { 1342 1343 bus->func = 0; 1344 } 1345 } 1346 } 1347 1348 /** 1349 * ixgbe_enable_rx_dma_82598 - Enable the Rx DMA unit 1350 * @hw: pointer to hardware structure 1351 * @regval: register value to write to RXCTRL 1352 * 1353 * Enables the Rx DMA unit 1354 **/ 1355 int32_t ixgbe_enable_rx_dma_82598(struct ixgbe_hw *hw, uint32_t regval) 1356 { 1357 DEBUGFUNC("ixgbe_enable_rx_dma_82598"); 1358 1359 IXGBE_WRITE_REG(hw, IXGBE_RXCTRL, regval); 1360 1361 return IXGBE_SUCCESS; 1362 } 1363