1 /* $OpenBSD: ixgbe_82598.c,v 1.3 2008/06/08 21:15:34 reyk Exp $ */ 2 3 /****************************************************************************** 4 5 Copyright (c) 2001-2008, Intel Corporation 6 All rights reserved. 7 8 Redistribution and use in source and binary forms, with or without 9 modification, are permitted provided that the following conditions are met: 10 11 1. Redistributions of source code must retain the above copyright notice, 12 this list of conditions and the following disclaimer. 13 14 2. Redistributions in binary form must reproduce the above copyright 15 notice, this list of conditions and the following disclaimer in the 16 documentation and/or other materials provided with the distribution. 17 18 3. Neither the name of the Intel Corporation nor the names of its 19 contributors may be used to endorse or promote products derived from 20 this software without specific prior written permission. 21 22 THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS" 23 AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE 24 IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE 25 ARE DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT OWNER OR CONTRIBUTORS BE 26 LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR 27 CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF 28 SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS 29 INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN 30 CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) 31 ARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE 32 POSSIBILITY OF SUCH DAMAGE. 33 34 ******************************************************************************/ 35 /*$FreeBSD: src/sys/dev/ixgbe/ixgbe_82598.c,v 1.4 2008/05/16 18:46:30 jfv Exp $*/ 36 37 #include <dev/pci/ixgbe.h> 38 #include <dev/pci/ixgbe_type.h> 39 40 int32_t ixgbe_init_ops_82598(struct ixgbe_hw *hw); 41 int32_t ixgbe_get_link_capabilities_82598(struct ixgbe_hw *hw, 42 ixgbe_link_speed *speed, 43 int *autoneg); 44 int32_t ixgbe_get_copper_link_capabilities_82598(struct ixgbe_hw *hw, 45 ixgbe_link_speed *speed, 46 int *autoneg); 47 enum ixgbe_media_type ixgbe_get_media_type_82598(struct ixgbe_hw *hw); 48 int32_t ixgbe_setup_fc_82598(struct ixgbe_hw *hw, int32_t packetbuf_num); 49 int32_t ixgbe_setup_mac_link_82598(struct ixgbe_hw *hw); 50 int32_t ixgbe_check_mac_link_82598(struct ixgbe_hw *hw, 51 ixgbe_link_speed *speed, 52 int *link_up, int link_up_wait_to_complete); 53 int32_t ixgbe_setup_mac_link_speed_82598(struct ixgbe_hw *hw, 54 ixgbe_link_speed speed, 55 int autoneg, 56 int autoneg_wait_to_complete); 57 int32_t ixgbe_setup_copper_link_82598(struct ixgbe_hw *hw); 58 int32_t ixgbe_setup_copper_link_speed_82598(struct ixgbe_hw *hw, 59 ixgbe_link_speed speed, 60 int autoneg, 61 int autoneg_wait_to_complete); 62 #ifndef NO_82598_A0_SUPPORT 63 int32_t ixgbe_reset_hw_rev_0_82598(struct ixgbe_hw *hw); 64 #endif 65 int32_t ixgbe_reset_hw_82598(struct ixgbe_hw *hw); 66 int32_t ixgbe_configure_fiber_serdes_fc_82598(struct ixgbe_hw *hw); 67 int32_t ixgbe_setup_fiber_serdes_link_82598(struct ixgbe_hw *hw); 68 int32_t ixgbe_set_vmdq_82598(struct ixgbe_hw *hw, uint32_t rar, uint32_t vmdq); 69 int32_t ixgbe_blink_led_stop_82598(struct ixgbe_hw *hw, uint32_t index); 70 int32_t ixgbe_blink_led_start_82598(struct ixgbe_hw *hw, uint32_t index); 71 72 /** 73 * ixgbe_init_ops_82598 - Inits func ptrs and MAC type 74 * @hw: pointer to hardware structure 75 * 76 * Initialize the function pointers and assign the MAC type for 82598. 77 * Does not touch the hardware. 78 **/ 79 int32_t ixgbe_init_ops_82598(struct ixgbe_hw *hw) 80 { 81 struct ixgbe_mac_info *mac = &hw->mac; 82 struct ixgbe_phy_info *phy = &hw->phy; 83 int32_t ret_val; 84 85 ret_val = ixgbe_init_phy_ops_generic(hw); 86 ret_val = ixgbe_init_ops_generic(hw); 87 88 /* MAC */ 89 #ifndef NO_82598_A0_SUPPORT 90 if (hw->revision_id == 0) 91 mac->ops.reset_hw = &ixgbe_reset_hw_rev_0_82598; 92 else 93 mac->ops.reset_hw = &ixgbe_reset_hw_82598; 94 #else 95 mac->ops.reset_hw = &ixgbe_reset_hw_82598; 96 #endif 97 mac->ops.get_media_type = &ixgbe_get_media_type_82598; 98 99 /* LEDs */ 100 mac->ops.blink_led_start = &ixgbe_blink_led_start_82598; 101 mac->ops.blink_led_stop = &ixgbe_blink_led_stop_82598; 102 103 /* RAR, Multicast, VLAN */ 104 mac->ops.set_vmdq = &ixgbe_set_vmdq_82598; 105 106 /* Flow Control */ 107 mac->ops.setup_fc = &ixgbe_setup_fc_82598; 108 109 /* Call PHY identify routine to get the phy type */ 110 phy->ops.identify(hw); 111 112 /* PHY Init */ 113 switch (hw->phy.type) { 114 case ixgbe_phy_tn: 115 phy->ops.check_link = &ixgbe_check_phy_link_tnx; 116 phy->ops.get_firmware_version = 117 &ixgbe_get_phy_firmware_version_tnx; 118 break; 119 case ixgbe_phy_nl: 120 phy->ops.reset = &ixgbe_reset_phy_nl; 121 break; 122 default: 123 break; 124 } 125 126 /* Link */ 127 mac->ops.check_link = &ixgbe_check_mac_link_82598; 128 if (mac->ops.get_media_type(hw) == ixgbe_media_type_copper) { 129 mac->ops.setup_link = &ixgbe_setup_copper_link_82598; 130 mac->ops.setup_link_speed = 131 &ixgbe_setup_copper_link_speed_82598; 132 mac->ops.get_link_capabilities = 133 &ixgbe_get_copper_link_capabilities_82598; 134 } else { 135 mac->ops.setup_link = &ixgbe_setup_mac_link_82598; 136 mac->ops.setup_link_speed = &ixgbe_setup_mac_link_speed_82598; 137 mac->ops.get_link_capabilities = 138 &ixgbe_get_link_capabilities_82598; 139 } 140 141 mac->mcft_size = 128; 142 mac->vft_size = 128; 143 mac->num_rar_entries = 16; 144 mac->max_tx_queues = 32; 145 mac->max_rx_queues = 64; 146 147 return IXGBE_SUCCESS; 148 } 149 150 /** 151 * ixgbe_get_link_capabilities_82598 - Determines link capabilities 152 * @hw: pointer to hardware structure 153 * @speed: pointer to link speed 154 * @autoneg: intean auto-negotiation value 155 * 156 * Determines the link capabilities by reading the AUTOC register. 157 **/ 158 int32_t ixgbe_get_link_capabilities_82598(struct ixgbe_hw *hw, 159 ixgbe_link_speed *speed, 160 int *autoneg) 161 { 162 int32_t status = IXGBE_SUCCESS; 163 int32_t autoc_reg; 164 165 autoc_reg = IXGBE_READ_REG(hw, IXGBE_AUTOC); 166 167 if (hw->mac.link_settings_loaded) { 168 autoc_reg &= ~IXGBE_AUTOC_LMS_ATTACH_TYPE; 169 autoc_reg &= ~IXGBE_AUTOC_LMS_MASK; 170 autoc_reg |= hw->mac.link_attach_type; 171 autoc_reg |= hw->mac.link_mode_select; 172 } 173 174 switch (autoc_reg & IXGBE_AUTOC_LMS_MASK) { 175 case IXGBE_AUTOC_LMS_1G_LINK_NO_AN: 176 *speed = IXGBE_LINK_SPEED_1GB_FULL; 177 *autoneg = FALSE; 178 break; 179 180 case IXGBE_AUTOC_LMS_10G_LINK_NO_AN: 181 *speed = IXGBE_LINK_SPEED_10GB_FULL; 182 *autoneg = FALSE; 183 break; 184 185 case IXGBE_AUTOC_LMS_1G_AN: 186 *speed = IXGBE_LINK_SPEED_1GB_FULL; 187 *autoneg = TRUE; 188 break; 189 190 case IXGBE_AUTOC_LMS_KX4_AN: 191 case IXGBE_AUTOC_LMS_KX4_AN_1G_AN: 192 *speed = IXGBE_LINK_SPEED_UNKNOWN; 193 if (autoc_reg & IXGBE_AUTOC_KX4_SUPP) 194 *speed |= IXGBE_LINK_SPEED_10GB_FULL; 195 if (autoc_reg & IXGBE_AUTOC_KX_SUPP) 196 *speed |= IXGBE_LINK_SPEED_1GB_FULL; 197 *autoneg = TRUE; 198 break; 199 200 default: 201 status = IXGBE_ERR_LINK_SETUP; 202 break; 203 } 204 205 return status; 206 } 207 208 /** 209 * ixgbe_get_copper_link_capabilities_82598 - Determines link capabilities 210 * @hw: pointer to hardware structure 211 * @speed: pointer to link speed 212 * @autoneg: intean auto-negotiation value 213 * 214 * Determines the link capabilities by reading the AUTOC register. 215 **/ 216 int32_t ixgbe_get_copper_link_capabilities_82598(struct ixgbe_hw *hw, 217 ixgbe_link_speed *speed, 218 int *autoneg) 219 { 220 int32_t status = IXGBE_ERR_LINK_SETUP; 221 uint16_t speed_ability; 222 223 *speed = 0; 224 *autoneg = TRUE; 225 226 status = hw->phy.ops.read_reg(hw, IXGBE_MDIO_PHY_SPEED_ABILITY, 227 IXGBE_MDIO_PMA_PMD_DEV_TYPE, 228 &speed_ability); 229 230 if (status == IXGBE_SUCCESS) { 231 if (speed_ability & IXGBE_MDIO_PHY_SPEED_10G) 232 *speed |= IXGBE_LINK_SPEED_10GB_FULL; 233 if (speed_ability & IXGBE_MDIO_PHY_SPEED_1G) 234 *speed |= IXGBE_LINK_SPEED_1GB_FULL; 235 } 236 237 return status; 238 } 239 240 /** 241 * ixgbe_get_media_type_82598 - Determines media type 242 * @hw: pointer to hardware structure 243 * 244 * Returns the media type (fiber, copper, backplane) 245 **/ 246 enum ixgbe_media_type ixgbe_get_media_type_82598(struct ixgbe_hw *hw) 247 { 248 enum ixgbe_media_type media_type; 249 250 /* Media type for I82598 is based on device ID */ 251 switch (hw->device_id) { 252 case IXGBE_DEV_ID_82598AF_DUAL_PORT: 253 case IXGBE_DEV_ID_82598AF_SINGLE_PORT: 254 case IXGBE_DEV_ID_82598EB_CX4: 255 case IXGBE_DEV_ID_82598_CX4_DUAL_PORT: 256 case IXGBE_DEV_ID_82598_DA_DUAL_PORT: 257 case IXGBE_DEV_ID_82598_SR_DUAL_PORT_EM: 258 case IXGBE_DEV_ID_82598EB_XF_LR: 259 media_type = ixgbe_media_type_fiber; 260 break; 261 case IXGBE_DEV_ID_82598AT: 262 media_type = ixgbe_media_type_copper; 263 break; 264 case IXGBE_DEV_ID_82598AT_DUAL_PORT: 265 media_type = ixgbe_media_type_copper; 266 break; 267 default: 268 media_type = ixgbe_media_type_unknown; 269 break; 270 } 271 272 return media_type; 273 } 274 275 /** 276 * ixgbe_setup_fc_82598 - Configure flow control settings 277 * @hw: pointer to hardware structure 278 * @packetbuf_num: packet buffer number (0-7) 279 * 280 * Configures the flow control settings based on SW configuration. This 281 * function is used for 802.3x flow control configuration only. 282 **/ 283 int32_t ixgbe_setup_fc_82598(struct ixgbe_hw *hw, int32_t packetbuf_num) 284 { 285 uint32_t frctl_reg; 286 uint32_t rmcs_reg; 287 288 if (packetbuf_num < 0 || packetbuf_num > 7) { 289 DEBUGOUT1("Invalid packet buffer number [%d], expected range is" 290 " 0-7\n", packetbuf_num); 291 panic("ixgbe"); 292 } 293 294 frctl_reg = IXGBE_READ_REG(hw, IXGBE_FCTRL); 295 frctl_reg &= ~(IXGBE_FCTRL_RFCE | IXGBE_FCTRL_RPFCE); 296 297 rmcs_reg = IXGBE_READ_REG(hw, IXGBE_RMCS); 298 rmcs_reg &= ~(IXGBE_RMCS_TFCE_PRIORITY | IXGBE_RMCS_TFCE_802_3X); 299 300 /* 301 * 10 gig parts do not have a word in the EEPROM to determine the 302 * default flow control setting, so we explicitly set it to full. 303 */ 304 if (hw->fc.type == ixgbe_fc_default) 305 hw->fc.type = ixgbe_fc_full; 306 307 /* 308 * We want to save off the original Flow Control configuration just in 309 * case we get disconnected and then reconnected into a different hub 310 * or switch with different Flow Control capabilities. 311 */ 312 hw->fc.original_type = hw->fc.type; 313 314 /* 315 * The possible values of the "flow_control" parameter are: 316 * 0: Flow control is completely disabled 317 * 1: Rx flow control is enabled (we can receive pause frames but not 318 * send pause frames). 319 * 2: Tx flow control is enabled (we can send pause frames but we do not 320 * support receiving pause frames) 321 * 3: Both Rx and Tx flow control (symmetric) are enabled. 322 * other: Invalid. 323 */ 324 switch (hw->fc.type) { 325 case ixgbe_fc_none: 326 break; 327 case ixgbe_fc_rx_pause: 328 /* 329 * Rx Flow control is enabled, 330 * and Tx Flow control is disabled. 331 */ 332 frctl_reg |= IXGBE_FCTRL_RFCE; 333 break; 334 case ixgbe_fc_tx_pause: 335 /* 336 * Tx Flow control is enabled, and Rx Flow control is disabled, 337 * by a software over-ride. 338 */ 339 rmcs_reg |= IXGBE_RMCS_TFCE_802_3X; 340 break; 341 case ixgbe_fc_full: 342 /* 343 * Flow control (both Rx and Tx) is enabled by a software 344 * over-ride. 345 */ 346 frctl_reg |= IXGBE_FCTRL_RFCE; 347 rmcs_reg |= IXGBE_RMCS_TFCE_802_3X; 348 break; 349 default: 350 /* We should never get here. The value should be 0-3. */ 351 DEBUGOUT("Flow control param set incorrectly\n"); 352 panic("ixgbe"); 353 break; 354 } 355 356 /* Enable 802.3x based flow control settings. */ 357 IXGBE_WRITE_REG(hw, IXGBE_FCTRL, frctl_reg); 358 IXGBE_WRITE_REG(hw, IXGBE_RMCS, rmcs_reg); 359 360 /* 361 * Check for invalid software configuration, zeros are completely 362 * invalid for all parameters used past this point, and if we enable 363 * flow control with zero water marks, we blast flow control packets. 364 */ 365 if (!hw->fc.low_water || !hw->fc.high_water || !hw->fc.pause_time) { 366 DEBUGOUT("Flow control structure initialized incorrectly\n"); 367 return IXGBE_ERR_INVALID_LINK_SETTINGS; 368 } 369 370 /* 371 * We need to set up the Receive Threshold high and low water 372 * marks as well as (optionally) enabling the transmission of 373 * XON frames. 374 */ 375 if (hw->fc.type & ixgbe_fc_tx_pause) { 376 if (hw->fc.send_xon) { 377 IXGBE_WRITE_REG(hw, IXGBE_FCRTL(packetbuf_num), 378 (hw->fc.low_water | IXGBE_FCRTL_XONE)); 379 } else { 380 IXGBE_WRITE_REG(hw, IXGBE_FCRTL(packetbuf_num), 381 hw->fc.low_water); 382 } 383 IXGBE_WRITE_REG(hw, IXGBE_FCRTH(packetbuf_num), 384 (hw->fc.high_water)|IXGBE_FCRTH_FCEN); 385 } 386 387 IXGBE_WRITE_REG(hw, IXGBE_FCTTV(0), hw->fc.pause_time); 388 IXGBE_WRITE_REG(hw, IXGBE_FCRTV, (hw->fc.pause_time >> 1)); 389 390 return IXGBE_SUCCESS; 391 } 392 393 /** 394 * ixgbe_setup_mac_link_82598 - Configures MAC link settings 395 * @hw: pointer to hardware structure 396 * 397 * Configures link settings based on values in the ixgbe_hw struct. 398 * Restarts the link. Performs autonegotiation if needed. 399 **/ 400 int32_t ixgbe_setup_mac_link_82598(struct ixgbe_hw *hw) 401 { 402 ixgbe_link_speed speed; 403 int link_up; 404 uint32_t autoc_reg; 405 uint32_t links_reg; 406 uint32_t i; 407 int32_t status = IXGBE_SUCCESS; 408 409 autoc_reg = IXGBE_READ_REG(hw, IXGBE_AUTOC); 410 411 if (hw->mac.link_settings_loaded) { 412 autoc_reg &= ~IXGBE_AUTOC_LMS_ATTACH_TYPE; 413 autoc_reg &= ~IXGBE_AUTOC_LMS_MASK; 414 autoc_reg |= hw->mac.link_attach_type; 415 autoc_reg |= hw->mac.link_mode_select; 416 417 IXGBE_WRITE_REG(hw, IXGBE_AUTOC, autoc_reg); 418 IXGBE_WRITE_FLUSH(hw); 419 msec_delay(50); 420 } 421 422 /* Restart link */ 423 autoc_reg |= IXGBE_AUTOC_AN_RESTART; 424 IXGBE_WRITE_REG(hw, IXGBE_AUTOC, autoc_reg); 425 426 /* Only poll for autoneg to complete if specified to do so */ 427 if (hw->phy.autoneg_wait_to_complete) { 428 if (hw->mac.link_mode_select == IXGBE_AUTOC_LMS_KX4_AN || 429 hw->mac.link_mode_select == IXGBE_AUTOC_LMS_KX4_AN_1G_AN) { 430 links_reg = 0; /* Just in case Autoneg time = 0 */ 431 for (i = 0; i < IXGBE_AUTO_NEG_TIME; i++) { 432 links_reg = IXGBE_READ_REG(hw, IXGBE_LINKS); 433 if (links_reg & IXGBE_LINKS_KX_AN_COMP) 434 break; 435 msec_delay(100); 436 } 437 if (!(links_reg & IXGBE_LINKS_KX_AN_COMP)) { 438 status = IXGBE_ERR_AUTONEG_NOT_COMPLETE; 439 DEBUGOUT("Autonegotiation did not complete.\n"); 440 } 441 } 442 } 443 444 /* 445 * We want to save off the original Flow Control configuration just in 446 * case we get disconnected and then reconnected into a different hub 447 * or switch with different Flow Control capabilities. 448 */ 449 hw->fc.original_type = hw->fc.type; 450 /* 451 * Set up the SerDes link if in 1Gb mode, otherwise just set up 452 * 10Gb flow control. 453 */ 454 hw->mac.ops.check_link(hw, &speed, &link_up, FALSE); 455 if (speed == IXGBE_LINK_SPEED_1GB_FULL) 456 status = ixgbe_setup_fiber_serdes_link_82598(hw); 457 else 458 ixgbe_setup_fc_82598(hw, 0); 459 460 /* Add delay to filter out noises during initial link setup */ 461 msec_delay(50); 462 463 return status; 464 } 465 466 /** 467 * ixgbe_check_mac_link_82598 - Get link/speed status 468 * @hw: pointer to hardware structure 469 * @speed: pointer to link speed 470 * @link_up: TRUE is link is up, FALSE otherwise 471 * @link_up_wait_to_complete: int used to wait for link up or not 472 * 473 * Reads the links register to determine if link is up and the current speed 474 **/ 475 int32_t ixgbe_check_mac_link_82598(struct ixgbe_hw *hw, ixgbe_link_speed *speed, 476 int *link_up, int link_up_wait_to_complete) 477 { 478 uint32_t links_reg; 479 uint32_t i; 480 uint16_t link_reg, adapt_comp_reg; 481 482 if (hw->phy.type == ixgbe_phy_nl) { 483 hw->phy.ops.read_reg(hw, 1, IXGBE_TWINAX_DEV, &link_reg); 484 hw->phy.ops.read_reg(hw, 1, IXGBE_TWINAX_DEV, &link_reg); 485 hw->phy.ops.read_reg(hw, 0xC00C, IXGBE_TWINAX_DEV, 486 &adapt_comp_reg); 487 if (link_up_wait_to_complete) { 488 for (i = 0; i < IXGBE_LINK_UP_TIME; i++) { 489 if ((link_reg & (1 << 2)) && 490 ((adapt_comp_reg & 1) == 0)) { 491 *link_up = TRUE; 492 break; 493 } else { 494 *link_up = FALSE; 495 } 496 msec_delay(100); 497 hw->phy.ops.read_reg(hw, 1, IXGBE_TWINAX_DEV, 498 &link_reg); 499 hw->phy.ops.read_reg(hw, 0xC00C, 500 IXGBE_TWINAX_DEV, 501 &adapt_comp_reg); 502 } 503 } else { 504 if ((link_reg & (1 << 2)) && 505 ((adapt_comp_reg & 1) == 0)) 506 *link_up = TRUE; 507 else 508 *link_up = FALSE; 509 } 510 511 if (*link_up == FALSE) 512 goto out; 513 } 514 515 links_reg = IXGBE_READ_REG(hw, IXGBE_LINKS); 516 if (link_up_wait_to_complete) { 517 for (i = 0; i < IXGBE_LINK_UP_TIME; i++) { 518 if (links_reg & IXGBE_LINKS_UP) { 519 *link_up = TRUE; 520 break; 521 } else { 522 *link_up = FALSE; 523 } 524 msec_delay(100); 525 links_reg = IXGBE_READ_REG(hw, IXGBE_LINKS); 526 } 527 } else { 528 if (links_reg & IXGBE_LINKS_UP) 529 *link_up = TRUE; 530 else 531 *link_up = FALSE; 532 } 533 534 if (links_reg & IXGBE_LINKS_SPEED) 535 *speed = IXGBE_LINK_SPEED_10GB_FULL; 536 else 537 *speed = IXGBE_LINK_SPEED_1GB_FULL; 538 539 out: 540 return IXGBE_SUCCESS; 541 } 542 543 /** 544 * ixgbe_configure_fiber_serdes_fc_82598 - Configure fiber flow control 545 * @hw: pointer to hardware structure 546 * 547 * Reads PCS registers and sets flow control settings, based on 548 * link-partner's abilities. 549 **/ 550 int32_t ixgbe_configure_fiber_serdes_fc_82598(struct ixgbe_hw *hw) 551 { 552 int32_t ret_val = IXGBE_SUCCESS; 553 uint32_t pcs_anadv_reg, pcs_lpab_reg, pcs_lstat_reg, i; 554 DEBUGFUNC("ixgbe_configure_fiber_serdes_fc_82598"); 555 556 /* Check that autonegotiation has completed */ 557 for (i = 0; i < FIBER_LINK_UP_LIMIT; i++) { 558 msec_delay(10); 559 pcs_lstat_reg = IXGBE_READ_REG(hw, IXGBE_PCS1GLSTA); 560 if (pcs_lstat_reg & IXGBE_PCS1GLSTA_LINK_OK) { 561 if (pcs_lstat_reg & IXGBE_PCS1GLSTA_AN_COMPLETE) { 562 if (!(pcs_lstat_reg & 563 (IXGBE_PCS1GLSTA_AN_TIMED_OUT))) 564 hw->mac.autoneg_failed = 0; 565 else 566 hw->mac.autoneg_failed = 1; 567 break; 568 } else { 569 hw->mac.autoneg_failed = 1; 570 break; 571 } 572 } 573 } 574 575 if (hw->mac.autoneg_failed) { 576 /* 577 * AutoNeg failed to achieve a link, so we will turn 578 * flow control off. 579 */ 580 hw->fc.type = ixgbe_fc_none; 581 DEBUGOUT("Flow Control = NONE.\n"); 582 ret_val = ixgbe_setup_fc_82598(hw, 0); 583 goto out; 584 } 585 586 /* 587 * Read the AN advertisement and LP ability registers and resolve 588 * local flow control settings accordingly 589 */ 590 pcs_anadv_reg = IXGBE_READ_REG(hw, IXGBE_PCS1GANA); 591 pcs_lpab_reg = IXGBE_READ_REG(hw, IXGBE_PCS1GANLP); 592 if ((pcs_anadv_reg & IXGBE_PCS1GANA_SYM_PAUSE) && 593 (pcs_lpab_reg & IXGBE_PCS1GANA_SYM_PAUSE)) { 594 /* 595 * Now we need to check if the user selected Rx ONLY 596 * of pause frames. In this case, we had to advertise 597 * FULL flow control because we could not advertise RX 598 * ONLY. Hence, we must now check to see if we need to 599 * turn OFF the TRANSMISSION of PAUSE frames. 600 */ 601 if (hw->fc.original_type == ixgbe_fc_full) { 602 hw->fc.type = ixgbe_fc_full; 603 DEBUGOUT("Flow Control = FULL.\n"); 604 } else { 605 hw->fc.type = ixgbe_fc_rx_pause; 606 DEBUGOUT("Flow Control = RX PAUSE frames only.\n"); 607 } 608 } else if (!(pcs_anadv_reg & IXGBE_PCS1GANA_SYM_PAUSE) && 609 (pcs_anadv_reg & IXGBE_PCS1GANA_ASM_PAUSE) && 610 (pcs_lpab_reg & IXGBE_PCS1GANA_SYM_PAUSE) && 611 (pcs_lpab_reg & IXGBE_PCS1GANA_ASM_PAUSE)) { 612 hw->fc.type = ixgbe_fc_tx_pause; 613 DEBUGOUT("Flow Control = TX PAUSE frames only.\n"); 614 } else if ((pcs_anadv_reg & IXGBE_PCS1GANA_SYM_PAUSE) && 615 (pcs_anadv_reg & IXGBE_PCS1GANA_ASM_PAUSE) && 616 !(pcs_lpab_reg & IXGBE_PCS1GANA_SYM_PAUSE) && 617 (pcs_lpab_reg & IXGBE_PCS1GANA_ASM_PAUSE)) { 618 hw->fc.type = ixgbe_fc_rx_pause; 619 DEBUGOUT("Flow Control = RX PAUSE frames only.\n"); 620 } else { 621 hw->fc.type = ixgbe_fc_none; 622 DEBUGOUT("Flow Control = NONE.\n"); 623 } 624 625 ret_val = ixgbe_setup_fc_82598(hw, 0); 626 if (ret_val) { 627 DEBUGOUT("Error forcing flow control settings\n"); 628 goto out; 629 } 630 631 out: 632 return ret_val; 633 } 634 635 /** 636 * ixgbe_setup_fiber_serdes_link_82598 - Configure fiber serdes link 637 * @hw: pointer to hardware structure 638 * 639 * Sets up PCS registers and sets flow control settings, based on 640 * link-partner's abilities. 641 **/ 642 int32_t ixgbe_setup_fiber_serdes_link_82598(struct ixgbe_hw *hw) 643 { 644 uint32_t reg; 645 int32_t ret_val; 646 647 DEBUGFUNC("ixgbe_setup_fiber_serdes_link_82598"); 648 649 /* 650 * 10 gig parts do not have a word in the EEPROM to determine the 651 * default flow control setting, so we explicitly set it to full. 652 */ 653 if (hw->fc.type == ixgbe_fc_default) 654 hw->fc.type = ixgbe_fc_full; 655 656 /* 657 * 82598 fiber/serdes devices require that flow control be resolved in 658 * software. 659 */ 660 reg = IXGBE_READ_REG(hw, IXGBE_PCS1GANA); 661 662 /* 663 * The possible values of the "fc" parameter are: 664 * 0: Flow control is completely disabled 665 * 1: Rx flow control is enabled (we can receive pause frames, 666 * but not send pause frames). 667 * 2: Tx flow control is enabled (we can send pause frames but 668 * we do not support receiving pause frames). 669 * 3: Both Rx and Tx flow control (symmetric) are enabled. 670 */ 671 switch (hw->fc.type) { 672 case ixgbe_fc_none: 673 /* 674 * Flow control completely disabled by a software 675 * over-ride. 676 */ 677 reg &= ~(IXGBE_PCS1GANA_SYM_PAUSE | IXGBE_PCS1GANA_ASM_PAUSE); 678 break; 679 case ixgbe_fc_rx_pause: 680 /* 681 * Rx Flow control is enabled and Tx Flow control is 682 * disabled by a software over-ride. Since there really 683 * isn't a way to advertise that we are capable of RX 684 * Pause ONLY, we will advertise that we support both 685 * symmetric and asymmetric Rx PAUSE. Later, we will 686 * disable the adapter's ability to send PAUSE frames. 687 */ 688 reg |= (IXGBE_PCS1GANA_SYM_PAUSE | IXGBE_PCS1GANA_ASM_PAUSE); 689 break; 690 case ixgbe_fc_tx_pause: 691 /* 692 * Tx Flow control is enabled, and Rx Flow control is 693 * disabled, by a software over-ride. 694 */ 695 reg |= (IXGBE_PCS1GANA_ASM_PAUSE); 696 reg &= ~(IXGBE_PCS1GANA_SYM_PAUSE); 697 break; 698 case ixgbe_fc_full: 699 /* 700 * Flow control (both Rx and Tx) is enabled by a 701 * software over-ride. 702 */ 703 reg |= (IXGBE_PCS1GANA_SYM_PAUSE | IXGBE_PCS1GANA_ASM_PAUSE); 704 break; 705 default: 706 DEBUGOUT("Flow control param set incorrectly\n"); 707 ret_val = -IXGBE_ERR_CONFIG; 708 goto out; 709 break; 710 } 711 712 IXGBE_WRITE_REG(hw, IXGBE_PCS1GANA, reg); 713 reg = IXGBE_READ_REG(hw, IXGBE_PCS1GLCTL); 714 715 /* Set PCS register for autoneg */ 716 /* Enable and restart autoneg */ 717 reg |= IXGBE_PCS1GLCTL_AN_ENABLE | IXGBE_PCS1GLCTL_AN_RESTART; 718 719 reg &= ~IXGBE_PCS1GLCTL_AN_1G_TIMEOUT_EN; /* Disable AN timeout */ 720 DEBUGOUT1("Configuring Autoneg; PCS_LCTL = 0x%08X\n", reg); 721 IXGBE_WRITE_REG(hw, IXGBE_PCS1GLCTL, reg); 722 723 /* 724 * Configure flow control. If we aren't auto-negotiating, 725 * just setup the flow control and do not worry about PCS autoneg. 726 */ 727 ixgbe_configure_fiber_serdes_fc_82598(hw); 728 729 out: 730 return IXGBE_SUCCESS; 731 } 732 733 /** 734 * ixgbe_setup_mac_link_speed_82598 - Set MAC link speed 735 * @hw: pointer to hardware structure 736 * @speed: new link speed 737 * @autoneg: TRUE if auto-negotiation enabled 738 * @autoneg_wait_to_complete: TRUE if waiting is needed to complete 739 * 740 * Set the link speed in the AUTOC register and restarts link. 741 **/ 742 int32_t ixgbe_setup_mac_link_speed_82598(struct ixgbe_hw *hw, 743 ixgbe_link_speed speed, int autoneg, 744 int autoneg_wait_to_complete) 745 { 746 int32_t status = IXGBE_SUCCESS; 747 748 /* If speed is 10G, then check for CX4 or XAUI. */ 749 if ((speed == IXGBE_LINK_SPEED_10GB_FULL) && 750 (!(hw->mac.link_attach_type & IXGBE_AUTOC_10G_KX4))) { 751 hw->mac.link_mode_select = IXGBE_AUTOC_LMS_10G_LINK_NO_AN; 752 } else if ((speed == IXGBE_LINK_SPEED_1GB_FULL) && (!autoneg)) { 753 hw->mac.link_mode_select = IXGBE_AUTOC_LMS_1G_LINK_NO_AN; 754 } else if (autoneg) { 755 /* BX mode - Autonegotiate 1G */ 756 if (!(hw->mac.link_attach_type & IXGBE_AUTOC_1G_PMA_PMD)) 757 hw->mac.link_mode_select = IXGBE_AUTOC_LMS_1G_AN; 758 else /* KX/KX4 mode */ 759 hw->mac.link_mode_select = IXGBE_AUTOC_LMS_KX4_AN_1G_AN; 760 } else { 761 status = IXGBE_ERR_LINK_SETUP; 762 } 763 764 if (status == IXGBE_SUCCESS) { 765 hw->phy.autoneg_wait_to_complete = autoneg_wait_to_complete; 766 767 hw->mac.link_settings_loaded = TRUE; 768 /* 769 * Setup and restart the link based on the new values in 770 * ixgbe_hw This will write the AUTOC register based on the new 771 * stored values 772 */ 773 ixgbe_setup_mac_link_82598(hw); 774 } 775 776 return status; 777 } 778 779 780 /** 781 * ixgbe_setup_copper_link_82598 - Setup copper link settings 782 * @hw: pointer to hardware structure 783 * 784 * Configures link settings based on values in the ixgbe_hw struct. 785 * Restarts the link. Performs autonegotiation if needed. Restart 786 * phy and wait for autonegotiate to finish. Then synchronize the 787 * MAC and PHY. 788 **/ 789 int32_t ixgbe_setup_copper_link_82598(struct ixgbe_hw *hw) 790 { 791 int32_t status; 792 793 /* Restart autonegotiation on PHY */ 794 status = hw->phy.ops.setup_link(hw); 795 796 /* Set MAC to KX/KX4 autoneg, which defaults to Parallel detection */ 797 hw->mac.link_attach_type = (IXGBE_AUTOC_10G_KX4 | IXGBE_AUTOC_1G_KX); 798 hw->mac.link_mode_select = IXGBE_AUTOC_LMS_KX4_AN; 799 800 /* Set up MAC */ 801 ixgbe_setup_mac_link_82598(hw); 802 803 return status; 804 } 805 806 /** 807 * ixgbe_setup_copper_link_speed_82598 - Set the PHY autoneg advertised field 808 * @hw: pointer to hardware structure 809 * @speed: new link speed 810 * @autoneg: TRUE if autonegotiation enabled 811 * @autoneg_wait_to_complete: TRUE if waiting is needed to complete 812 * 813 * Sets the link speed in the AUTOC register in the MAC and restarts link. 814 **/ 815 int32_t ixgbe_setup_copper_link_speed_82598(struct ixgbe_hw *hw, 816 ixgbe_link_speed speed, 817 int autoneg, 818 int autoneg_wait_to_complete) 819 { 820 int32_t status; 821 822 /* Setup the PHY according to input speed */ 823 status = hw->phy.ops.setup_link_speed(hw, speed, autoneg, 824 autoneg_wait_to_complete); 825 826 /* Set MAC to KX/KX4 autoneg, which defaults to Parallel detection */ 827 hw->mac.link_attach_type = (IXGBE_AUTOC_10G_KX4 | IXGBE_AUTOC_1G_KX); 828 hw->mac.link_mode_select = IXGBE_AUTOC_LMS_KX4_AN; 829 830 /* Set up MAC */ 831 ixgbe_setup_mac_link_82598(hw); 832 833 return status; 834 } 835 836 #ifndef NO_82598_A0_SUPPORT 837 /** 838 * ixgbe_reset_hw_rev_0_82598 - Performs hardware reset 839 * @hw: pointer to hardware structure 840 * 841 * Resets the hardware by resetting the transmit and receive units, masks and 842 * clears all interrupts, performing a PHY reset, and performing a link (MAC) 843 * reset. 844 **/ 845 int32_t ixgbe_reset_hw_rev_0_82598(struct ixgbe_hw *hw) 846 { 847 int32_t status = IXGBE_SUCCESS; 848 uint32_t ctrl; 849 uint32_t gheccr; 850 uint32_t autoc; 851 uint32_t i; 852 uint32_t resets; 853 854 /* Call adapter stop to disable tx/rx and clear interrupts */ 855 hw->mac.ops.stop_adapter(hw); 856 857 /* Reset PHY */ 858 hw->phy.ops.reset(hw); 859 860 for (resets = 0; resets < 10; resets++) { 861 /* 862 * Prevent the PCI-E bus from from hanging by disabling PCI-E 863 * master access and verify no pending requests before reset 864 */ 865 if (ixgbe_disable_pcie_master(hw) != IXGBE_SUCCESS) { 866 status = IXGBE_ERR_MASTER_REQUESTS_PENDING; 867 DEBUGOUT("PCI-E Master disable polling has failed.\n"); 868 } 869 870 /* 871 * Issue global reset to the MAC. This needs to be a SW reset. 872 * If link reset is used, it might reset the MAC when mng is 873 * using it. 874 */ 875 ctrl = IXGBE_READ_REG(hw, IXGBE_CTRL); 876 IXGBE_WRITE_REG(hw, IXGBE_CTRL, (ctrl | IXGBE_CTRL_RST)); 877 IXGBE_WRITE_FLUSH(hw); 878 879 /* 880 * Poll for reset bit to self-clear indicating reset is 881 * complete 882 */ 883 for (i = 0; i < 10; i++) { 884 usec_delay(1); 885 ctrl = IXGBE_READ_REG(hw, IXGBE_CTRL); 886 if (!(ctrl & IXGBE_CTRL_RST)) 887 break; 888 } 889 if (ctrl & IXGBE_CTRL_RST) { 890 status = IXGBE_ERR_RESET_FAILED; 891 DEBUGOUT("Reset polling failed to complete.\n"); 892 } 893 } 894 895 msec_delay(50); 896 897 gheccr = IXGBE_READ_REG(hw, IXGBE_GHECCR); 898 gheccr &= ~((1 << 21) | (1 << 18) | (1 << 9) | (1 << 6)); 899 IXGBE_WRITE_REG(hw, IXGBE_GHECCR, gheccr); 900 901 /* 902 * AUTOC register which stores link settings gets cleared 903 * and reloaded from EEPROM after reset. We need to restore 904 * our stored value from init in case SW changed the attach 905 * type or speed. If this is the first time and link settings 906 * have not been stored, store default settings from AUTOC. 907 */ 908 autoc = IXGBE_READ_REG(hw, IXGBE_AUTOC); 909 if (hw->mac.link_settings_loaded) { 910 autoc &= ~(IXGBE_AUTOC_LMS_ATTACH_TYPE); 911 autoc &= ~(IXGBE_AUTOC_LMS_MASK); 912 autoc |= hw->mac.link_attach_type; 913 autoc |= hw->mac.link_mode_select; 914 IXGBE_WRITE_REG(hw, IXGBE_AUTOC, autoc); 915 } else { 916 hw->mac.link_attach_type = 917 (autoc & IXGBE_AUTOC_LMS_ATTACH_TYPE); 918 hw->mac.link_mode_select = (autoc & IXGBE_AUTOC_LMS_MASK); 919 hw->mac.link_settings_loaded = TRUE; 920 } 921 922 /* Store the permanent mac address */ 923 hw->mac.ops.get_mac_addr(hw, hw->mac.perm_addr); 924 925 return status; 926 } 927 928 #endif /* NO_A0_SUPPORT */ 929 /** 930 * ixgbe_reset_hw_82598 - Performs hardware reset 931 * @hw: pointer to hardware structure 932 * 933 * Resets the hardware by resetting the transmit and receive units, masks and 934 * clears all interrupts, performing a PHY reset, and performing a link (MAC) 935 * reset. 936 **/ 937 int32_t ixgbe_reset_hw_82598(struct ixgbe_hw *hw) 938 { 939 int32_t status = IXGBE_SUCCESS; 940 uint32_t ctrl; 941 uint32_t gheccr; 942 uint32_t i; 943 uint32_t autoc; 944 uint8_t analog_val; 945 946 /* Call adapter stop to disable tx/rx and clear interrupts */ 947 hw->mac.ops.stop_adapter(hw); 948 949 /* 950 * Power up the Atlas Tx lanes if they are currently powered down. 951 * Atlas Tx lanes are powered down for MAC loopback tests, but 952 * they are not automatically restored on reset. 953 */ 954 hw->mac.ops.read_analog_reg8(hw, IXGBE_ATLAS_PDN_LPBK, &analog_val); 955 if (analog_val & IXGBE_ATLAS_PDN_TX_REG_EN) { 956 /* Enable Tx Atlas so packets can be transmitted again */ 957 hw->mac.ops.read_analog_reg8(hw, IXGBE_ATLAS_PDN_LPBK, 958 &analog_val); 959 analog_val &= ~IXGBE_ATLAS_PDN_TX_REG_EN; 960 hw->mac.ops.write_analog_reg8(hw, IXGBE_ATLAS_PDN_LPBK, 961 analog_val); 962 963 hw->mac.ops.read_analog_reg8(hw, IXGBE_ATLAS_PDN_10G, 964 &analog_val); 965 analog_val &= ~ IXGBE_ATLAS_PDN_TX_10G_QL_ALL; 966 hw->mac.ops.write_analog_reg8(hw, IXGBE_ATLAS_PDN_10G, 967 analog_val); 968 969 hw->mac.ops.read_analog_reg8(hw, IXGBE_ATLAS_PDN_1G, 970 &analog_val); 971 analog_val &= ~IXGBE_ATLAS_PDN_TX_1G_QL_ALL; 972 hw->mac.ops.write_analog_reg8(hw, IXGBE_ATLAS_PDN_1G, 973 analog_val); 974 975 hw->mac.ops.read_analog_reg8(hw, IXGBE_ATLAS_PDN_AN, 976 &analog_val); 977 analog_val &= ~IXGBE_ATLAS_PDN_TX_AN_QL_ALL; 978 hw->mac.ops.write_analog_reg8(hw, IXGBE_ATLAS_PDN_AN, 979 analog_val); 980 } 981 982 /* Reset PHY */ 983 if (hw->phy.reset_disable == FALSE) 984 hw->phy.ops.reset(hw); 985 986 /* 987 * Prevent the PCI-E bus from from hanging by disabling PCI-E master 988 * access and verify no pending requests before reset 989 */ 990 if (ixgbe_disable_pcie_master(hw) != IXGBE_SUCCESS) { 991 status = IXGBE_ERR_MASTER_REQUESTS_PENDING; 992 DEBUGOUT("PCI-E Master disable polling has failed.\n"); 993 } 994 995 /* 996 * Issue global reset to the MAC. This needs to be a SW reset. 997 * If link reset is used, it might reset the MAC when mng is using it 998 */ 999 ctrl = IXGBE_READ_REG(hw, IXGBE_CTRL); 1000 IXGBE_WRITE_REG(hw, IXGBE_CTRL, (ctrl | IXGBE_CTRL_RST)); 1001 IXGBE_WRITE_FLUSH(hw); 1002 1003 /* Poll for reset bit to self-clear indicating reset is complete */ 1004 for (i = 0; i < 10; i++) { 1005 usec_delay(1); 1006 ctrl = IXGBE_READ_REG(hw, IXGBE_CTRL); 1007 if (!(ctrl & IXGBE_CTRL_RST)) 1008 break; 1009 } 1010 if (ctrl & IXGBE_CTRL_RST) { 1011 status = IXGBE_ERR_RESET_FAILED; 1012 DEBUGOUT("Reset polling failed to complete.\n"); 1013 } 1014 1015 msec_delay(50); 1016 1017 gheccr = IXGBE_READ_REG(hw, IXGBE_GHECCR); 1018 gheccr &= ~((1 << 21) | (1 << 18) | (1 << 9) | (1 << 6)); 1019 IXGBE_WRITE_REG(hw, IXGBE_GHECCR, gheccr); 1020 1021 /* 1022 * AUTOC register which stores link settings gets cleared 1023 * and reloaded from EEPROM after reset. We need to restore 1024 * our stored value from init in case SW changed the attach 1025 * type or speed. If this is the first time and link settings 1026 * have not been stored, store default settings from AUTOC. 1027 */ 1028 autoc = IXGBE_READ_REG(hw, IXGBE_AUTOC); 1029 if (hw->mac.link_settings_loaded) { 1030 autoc &= ~(IXGBE_AUTOC_LMS_ATTACH_TYPE); 1031 autoc &= ~(IXGBE_AUTOC_LMS_MASK); 1032 autoc |= hw->mac.link_attach_type; 1033 autoc |= hw->mac.link_mode_select; 1034 IXGBE_WRITE_REG(hw, IXGBE_AUTOC, autoc); 1035 } else { 1036 hw->mac.link_attach_type = 1037 (autoc & IXGBE_AUTOC_LMS_ATTACH_TYPE); 1038 hw->mac.link_mode_select = (autoc & IXGBE_AUTOC_LMS_MASK); 1039 hw->mac.link_settings_loaded = TRUE; 1040 } 1041 1042 /* Store the permanent mac address */ 1043 hw->mac.ops.get_mac_addr(hw, hw->mac.perm_addr); 1044 1045 return status; 1046 } 1047 1048 /** 1049 * ixgbe_set_vmdq_82598 - Associate a VMDq set index with a rx address 1050 * @hw: pointer to hardware struct 1051 * @rar: receive address register index to associate with a VMDq index 1052 * @vmdq: VMDq set index 1053 **/ 1054 int32_t ixgbe_set_vmdq_82598(struct ixgbe_hw *hw, uint32_t rar, uint32_t vmdq) 1055 { 1056 uint32_t rar_high; 1057 1058 rar_high = IXGBE_READ_REG(hw, IXGBE_RAH(rar)); 1059 rar_high &= ~IXGBE_RAH_VIND_MASK; 1060 rar_high |= ((vmdq << IXGBE_RAH_VIND_SHIFT) & IXGBE_RAH_VIND_MASK); 1061 IXGBE_WRITE_REG(hw, IXGBE_RAH(rar), rar_high); 1062 return IXGBE_SUCCESS; 1063 } 1064 1065 /** 1066 * ixgbe_blink_led_start_82598 - Blink LED based on index. 1067 * @hw: pointer to hardware structure 1068 * @index: led number to blink 1069 **/ 1070 int32_t ixgbe_blink_led_start_82598(struct ixgbe_hw *hw, uint32_t index) 1071 { 1072 ixgbe_link_speed speed = 0; 1073 int link_up = 0; 1074 uint32_t autoc_reg = IXGBE_READ_REG(hw, IXGBE_AUTOC); 1075 uint32_t led_reg = IXGBE_READ_REG(hw, IXGBE_LEDCTL); 1076 1077 /* 1078 * Link must be up to auto-blink the LEDs on the 82598EB MAC; 1079 * force it if link is down. 1080 */ 1081 hw->mac.ops.check_link(hw, &speed, &link_up, FALSE); 1082 1083 if (!link_up) { 1084 autoc_reg |= IXGBE_AUTOC_FLU; 1085 IXGBE_WRITE_REG(hw, IXGBE_AUTOC, autoc_reg); 1086 msec_delay(10); 1087 } 1088 1089 led_reg &= ~IXGBE_LED_MODE_MASK(index); 1090 led_reg |= IXGBE_LED_BLINK(index); 1091 IXGBE_WRITE_REG(hw, IXGBE_LEDCTL, led_reg); 1092 IXGBE_WRITE_FLUSH(hw); 1093 1094 return IXGBE_SUCCESS; 1095 } 1096 1097 /** 1098 * ixgbe_blink_led_stop_82598 - Stop blinking LED based on index. 1099 * @hw: pointer to hardware structure 1100 * @index: led number to stop blinking 1101 **/ 1102 int32_t ixgbe_blink_led_stop_82598(struct ixgbe_hw *hw, uint32_t index) 1103 { 1104 uint32_t autoc_reg = IXGBE_READ_REG(hw, IXGBE_AUTOC); 1105 uint32_t led_reg = IXGBE_READ_REG(hw, IXGBE_LEDCTL); 1106 1107 autoc_reg &= ~IXGBE_AUTOC_FLU; 1108 IXGBE_WRITE_REG(hw, IXGBE_AUTOC, autoc_reg); 1109 1110 led_reg &= ~IXGBE_LED_MODE_MASK(index); 1111 led_reg &= ~IXGBE_LED_BLINK(index); 1112 IXGBE_WRITE_REG(hw, IXGBE_LEDCTL, led_reg); 1113 IXGBE_WRITE_FLUSH(hw); 1114 1115 return IXGBE_SUCCESS; 1116 } 1117