1 /* $OpenBSD: ixgbe.c,v 1.3 2008/06/08 21:15:34 reyk Exp $ */ 2 3 /****************************************************************************** 4 5 Copyright (c) 2001-2008, Intel Corporation 6 All rights reserved. 7 8 Redistribution and use in source and binary forms, with or without 9 modification, are permitted provided that the following conditions are met: 10 11 1. Redistributions of source code must retain the above copyright notice, 12 this list of conditions and the following disclaimer. 13 14 2. Redistributions in binary form must reproduce the above copyright 15 notice, this list of conditions and the following disclaimer in the 16 documentation and/or other materials provided with the distribution. 17 18 3. Neither the name of the Intel Corporation nor the names of its 19 contributors may be used to endorse or promote products derived from 20 this software without specific prior written permission. 21 22 THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS" 23 AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE 24 IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE 25 ARE DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT OWNER OR CONTRIBUTORS BE 26 LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR 27 CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF 28 SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS 29 INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN 30 CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) 31 ARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE 32 POSSIBILITY OF SUCH DAMAGE. 33 34 ******************************************************************************/ 35 /*$FreeBSD: src/sys/dev/ixgbe/ixgbe_common.c,v 1.4 2008/05/16 18:46:30 jfv Exp $*/ 36 37 #include <dev/pci/ixgbe.h> 38 39 static int32_t ixgbe_poll_eeprom_eerd_done(struct ixgbe_hw *hw); 40 static int32_t ixgbe_acquire_eeprom(struct ixgbe_hw *hw); 41 static int32_t ixgbe_get_eeprom_semaphore(struct ixgbe_hw *hw); 42 static void ixgbe_release_eeprom_semaphore(struct ixgbe_hw *hw); 43 static int32_t ixgbe_ready_eeprom(struct ixgbe_hw *hw); 44 static void ixgbe_standby_eeprom(struct ixgbe_hw *hw); 45 static void ixgbe_shift_out_eeprom_bits(struct ixgbe_hw *hw, uint16_t data, 46 uint16_t count); 47 static uint16_t ixgbe_shift_in_eeprom_bits(struct ixgbe_hw *hw, uint16_t count); 48 static void ixgbe_raise_eeprom_clk(struct ixgbe_hw *hw, uint32_t *eec); 49 static void ixgbe_lower_eeprom_clk(struct ixgbe_hw *hw, uint32_t *eec); 50 static void ixgbe_release_eeprom(struct ixgbe_hw *hw); 51 static uint16_t ixgbe_calc_eeprom_checksum(struct ixgbe_hw *hw); 52 53 static void ixgbe_enable_rar(struct ixgbe_hw *hw, uint32_t index); 54 static void ixgbe_disable_rar(struct ixgbe_hw *hw, uint32_t index); 55 static int32_t ixgbe_mta_vector(struct ixgbe_hw *hw, uint8_t *mc_addr); 56 void ixgbe_add_mc_addr(struct ixgbe_hw *hw, uint8_t *mc_addr); 57 void ixgbe_add_uc_addr(struct ixgbe_hw *hw, uint8_t *addr, uint32_t vmdq); 58 59 /** 60 * ixgbe_init_ops_generic - Inits function ptrs 61 * @hw: pointer to the hardware structure 62 * 63 * Initialize the function pointers. 64 **/ 65 int32_t ixgbe_init_ops_generic(struct ixgbe_hw *hw) 66 { 67 struct ixgbe_eeprom_info *eeprom = &hw->eeprom; 68 struct ixgbe_mac_info *mac = &hw->mac; 69 uint32_t eec = IXGBE_READ_REG(hw, IXGBE_EEC); 70 71 /* EEPROM */ 72 eeprom->ops.init_params = &ixgbe_init_eeprom_params_generic; 73 /* If EEPROM is valid (bit 8 = 1), use EERD otherwise use bit bang */ 74 if (eec & (1 << 8)) 75 eeprom->ops.read = &ixgbe_read_eeprom_generic; 76 else 77 eeprom->ops.read = &ixgbe_read_eeprom_bit_bang_generic; 78 eeprom->ops.write = &ixgbe_write_eeprom_generic; 79 eeprom->ops.validate_checksum = 80 &ixgbe_validate_eeprom_checksum_generic; 81 eeprom->ops.update_checksum = &ixgbe_update_eeprom_checksum_generic; 82 83 /* MAC */ 84 mac->ops.init_hw = &ixgbe_init_hw_generic; 85 mac->ops.reset_hw = NULL; 86 mac->ops.start_hw = &ixgbe_start_hw_generic; 87 mac->ops.clear_hw_cntrs = &ixgbe_clear_hw_cntrs_generic; 88 mac->ops.get_media_type = NULL; 89 mac->ops.get_mac_addr = &ixgbe_get_mac_addr_generic; 90 mac->ops.stop_adapter = &ixgbe_stop_adapter_generic; 91 mac->ops.get_bus_info = &ixgbe_get_bus_info_generic; 92 mac->ops.read_analog_reg8 = &ixgbe_read_analog_reg8_generic; 93 mac->ops.write_analog_reg8 = &ixgbe_write_analog_reg8_generic; 94 95 /* LEDs */ 96 mac->ops.led_on = &ixgbe_led_on_generic; 97 mac->ops.led_off = &ixgbe_led_off_generic; 98 mac->ops.blink_led_start = NULL; 99 mac->ops.blink_led_stop = NULL; 100 101 /* RAR, Multicast, VLAN */ 102 mac->ops.set_rar = &ixgbe_set_rar_generic; 103 mac->ops.set_vmdq = NULL; 104 mac->ops.init_rx_addrs = &ixgbe_init_rx_addrs_generic; 105 mac->ops.update_uc_addr_list = &ixgbe_update_uc_addr_list_generic; 106 mac->ops.update_mc_addr_list = &ixgbe_update_mc_addr_list_generic; 107 mac->ops.enable_mc = &ixgbe_enable_mc_generic; 108 mac->ops.disable_mc = &ixgbe_disable_mc_generic; 109 mac->ops.clear_vfta = &ixgbe_clear_vfta_generic; 110 mac->ops.set_vfta = &ixgbe_set_vfta_generic; 111 112 /* Flow Control */ 113 mac->ops.setup_fc = NULL; 114 115 /* Link */ 116 mac->ops.get_link_capabilities = NULL; 117 mac->ops.setup_link = NULL; 118 mac->ops.setup_link_speed = NULL; 119 mac->ops.check_link = NULL; 120 121 return IXGBE_SUCCESS; 122 } 123 124 /** 125 * ixgbe_start_hw_generic - Prepare hardware for Tx/Rx 126 * @hw: pointer to hardware structure 127 * 128 * Starts the hardware by filling the bus info structure and media type, clears 129 * all on chip counters, initializes receive address registers, multicast 130 * table, VLAN filter table, calls routine to set up link and flow control 131 * settings, and leaves transmit and receive units disabled and uninitialized 132 **/ 133 int32_t ixgbe_start_hw_generic(struct ixgbe_hw *hw) 134 { 135 uint32_t ctrl_ext; 136 137 /* Set the media type */ 138 hw->phy.media_type = hw->mac.ops.get_media_type(hw); 139 140 /* Set bus info */ 141 hw->mac.ops.get_bus_info(hw); 142 143 /* Identify the PHY */ 144 hw->phy.ops.identify(hw); 145 146 /* 147 * Store MAC address from RAR0, clear receive address registers, and 148 * clear the multicast table 149 */ 150 hw->mac.ops.init_rx_addrs(hw); 151 152 /* Clear the VLAN filter table */ 153 hw->mac.ops.clear_vfta(hw); 154 155 /* Set up link */ 156 hw->mac.ops.setup_link(hw); 157 158 /* Clear statistics registers */ 159 hw->mac.ops.clear_hw_cntrs(hw); 160 161 /* Set No Snoop Disable */ 162 ctrl_ext = IXGBE_READ_REG(hw, IXGBE_CTRL_EXT); 163 ctrl_ext |= IXGBE_CTRL_EXT_NS_DIS; 164 IXGBE_WRITE_REG(hw, IXGBE_CTRL_EXT, ctrl_ext); 165 IXGBE_WRITE_FLUSH(hw); 166 167 /* Clear adapter stopped flag */ 168 hw->adapter_stopped = FALSE; 169 170 return IXGBE_SUCCESS; 171 } 172 173 /** 174 * ixgbe_init_hw_generic - Generic hardware initialization 175 * @hw: pointer to hardware structure 176 * 177 * Initialize the hardware by resetting the hardware, filling the bus info 178 * structure and media type, clears all on chip counters, initializes receive 179 * address registers, multicast table, VLAN filter table, calls routine to set 180 * up link and flow control settings, and leaves transmit and receive units 181 * disabled and uninitialized 182 **/ 183 int32_t ixgbe_init_hw_generic(struct ixgbe_hw *hw) 184 { 185 /* Reset the hardware */ 186 hw->mac.ops.reset_hw(hw); 187 188 /* Start the HW */ 189 hw->mac.ops.start_hw(hw); 190 191 return IXGBE_SUCCESS; 192 } 193 194 /** 195 * ixgbe_clear_hw_cntrs_generic - Generic clear hardware counters 196 * @hw: pointer to hardware structure 197 * 198 * Clears all hardware statistics counters by reading them from the hardware 199 * Statistics counters are clear on read. 200 **/ 201 int32_t ixgbe_clear_hw_cntrs_generic(struct ixgbe_hw *hw) 202 { 203 uint16_t i = 0; 204 205 IXGBE_READ_REG(hw, IXGBE_CRCERRS); 206 IXGBE_READ_REG(hw, IXGBE_ILLERRC); 207 IXGBE_READ_REG(hw, IXGBE_ERRBC); 208 IXGBE_READ_REG(hw, IXGBE_MSPDC); 209 for (i = 0; i < 8; i++) 210 IXGBE_READ_REG(hw, IXGBE_MPC(i)); 211 212 IXGBE_READ_REG(hw, IXGBE_MLFC); 213 IXGBE_READ_REG(hw, IXGBE_MRFC); 214 IXGBE_READ_REG(hw, IXGBE_RLEC); 215 IXGBE_READ_REG(hw, IXGBE_LXONTXC); 216 IXGBE_READ_REG(hw, IXGBE_LXONRXC); 217 IXGBE_READ_REG(hw, IXGBE_LXOFFTXC); 218 IXGBE_READ_REG(hw, IXGBE_LXOFFRXC); 219 220 for (i = 0; i < 8; i++) { 221 IXGBE_READ_REG(hw, IXGBE_PXONTXC(i)); 222 IXGBE_READ_REG(hw, IXGBE_PXONRXC(i)); 223 IXGBE_READ_REG(hw, IXGBE_PXOFFTXC(i)); 224 IXGBE_READ_REG(hw, IXGBE_PXOFFRXC(i)); 225 } 226 227 IXGBE_READ_REG(hw, IXGBE_PRC64); 228 IXGBE_READ_REG(hw, IXGBE_PRC127); 229 IXGBE_READ_REG(hw, IXGBE_PRC255); 230 IXGBE_READ_REG(hw, IXGBE_PRC511); 231 IXGBE_READ_REG(hw, IXGBE_PRC1023); 232 IXGBE_READ_REG(hw, IXGBE_PRC1522); 233 IXGBE_READ_REG(hw, IXGBE_GPRC); 234 IXGBE_READ_REG(hw, IXGBE_BPRC); 235 IXGBE_READ_REG(hw, IXGBE_MPRC); 236 IXGBE_READ_REG(hw, IXGBE_GPTC); 237 IXGBE_READ_REG(hw, IXGBE_GORCL); 238 IXGBE_READ_REG(hw, IXGBE_GORCH); 239 IXGBE_READ_REG(hw, IXGBE_GOTCL); 240 IXGBE_READ_REG(hw, IXGBE_GOTCH); 241 for (i = 0; i < 8; i++) 242 IXGBE_READ_REG(hw, IXGBE_RNBC(i)); 243 IXGBE_READ_REG(hw, IXGBE_RUC); 244 IXGBE_READ_REG(hw, IXGBE_RFC); 245 IXGBE_READ_REG(hw, IXGBE_ROC); 246 IXGBE_READ_REG(hw, IXGBE_RJC); 247 IXGBE_READ_REG(hw, IXGBE_MNGPRC); 248 IXGBE_READ_REG(hw, IXGBE_MNGPDC); 249 IXGBE_READ_REG(hw, IXGBE_MNGPTC); 250 IXGBE_READ_REG(hw, IXGBE_TORL); 251 IXGBE_READ_REG(hw, IXGBE_TORH); 252 IXGBE_READ_REG(hw, IXGBE_TPR); 253 IXGBE_READ_REG(hw, IXGBE_TPT); 254 IXGBE_READ_REG(hw, IXGBE_PTC64); 255 IXGBE_READ_REG(hw, IXGBE_PTC127); 256 IXGBE_READ_REG(hw, IXGBE_PTC255); 257 IXGBE_READ_REG(hw, IXGBE_PTC511); 258 IXGBE_READ_REG(hw, IXGBE_PTC1023); 259 IXGBE_READ_REG(hw, IXGBE_PTC1522); 260 IXGBE_READ_REG(hw, IXGBE_MPTC); 261 IXGBE_READ_REG(hw, IXGBE_BPTC); 262 for (i = 0; i < 16; i++) { 263 IXGBE_READ_REG(hw, IXGBE_QPRC(i)); 264 IXGBE_READ_REG(hw, IXGBE_QBRC(i)); 265 IXGBE_READ_REG(hw, IXGBE_QPTC(i)); 266 IXGBE_READ_REG(hw, IXGBE_QBTC(i)); 267 } 268 269 return IXGBE_SUCCESS; 270 } 271 272 /** 273 * ixgbe_read_pba_num - Reads part number from EEPROM 274 * @hw: pointer to hardware structure 275 * @pba_num: stores the part number from the EEPROM 276 * 277 * Reads the part number from the EEPROM. 278 **/ 279 int32_t ixgbe_read_pba_num_generic(struct ixgbe_hw *hw, uint32_t *pba_num) 280 { 281 int32_t ret_val; 282 uint16_t data; 283 284 DEBUGFUNC("ixgbe_read_pba_num_generic"); 285 286 ret_val = hw->eeprom.ops.read(hw, IXGBE_PBANUM0_PTR, &data); 287 if (ret_val) { 288 DEBUGOUT("NVM Read Error\n"); 289 return ret_val; 290 } 291 *pba_num = (uint32_t)(data << 16); 292 293 ret_val = hw->eeprom.ops.read(hw, IXGBE_PBANUM1_PTR, &data); 294 if (ret_val) { 295 DEBUGOUT("NVM Read Error\n"); 296 return ret_val; 297 } 298 *pba_num |= data; 299 300 return IXGBE_SUCCESS; 301 } 302 303 /** 304 * ixgbe_get_mac_addr_generic - Generic get MAC address 305 * @hw: pointer to hardware structure 306 * @mac_addr: Adapter MAC address 307 * 308 * Reads the adapter's MAC address from first Receive Address Register (RAR0) 309 * A reset of the adapter must be performed prior to calling this function 310 * in order for the MAC address to have been loaded from the EEPROM into RAR0 311 **/ 312 int32_t ixgbe_get_mac_addr_generic(struct ixgbe_hw *hw, uint8_t *mac_addr) 313 { 314 uint32_t rar_high; 315 uint32_t rar_low; 316 uint16_t i; 317 318 rar_high = IXGBE_READ_REG(hw, IXGBE_RAH(0)); 319 rar_low = IXGBE_READ_REG(hw, IXGBE_RAL(0)); 320 321 for (i = 0; i < 4; i++) 322 mac_addr[i] = (uint8_t)(rar_low >> (i*8)); 323 324 for (i = 0; i < 2; i++) 325 mac_addr[i+4] = (uint8_t)(rar_high >> (i*8)); 326 327 return IXGBE_SUCCESS; 328 } 329 330 /** 331 * ixgbe_get_bus_info_generic - Generic set PCI bus info 332 * @hw: pointer to hardware structure 333 * 334 * Sets the PCI bus info (speed, width, type) within the ixgbe_hw structure 335 **/ 336 int32_t ixgbe_get_bus_info_generic(struct ixgbe_hw *hw) 337 { 338 uint16_t link_status; 339 340 hw->bus.type = ixgbe_bus_type_pci_express; 341 342 /* Get the negotiated link width and speed from PCI config space */ 343 link_status = IXGBE_READ_PCIE_WORD(hw, IXGBE_PCI_LINK_STATUS); 344 345 switch (link_status & IXGBE_PCI_LINK_WIDTH) { 346 case IXGBE_PCI_LINK_WIDTH_1: 347 hw->bus.width = ixgbe_bus_width_pcie_x1; 348 break; 349 case IXGBE_PCI_LINK_WIDTH_2: 350 hw->bus.width = ixgbe_bus_width_pcie_x2; 351 break; 352 case IXGBE_PCI_LINK_WIDTH_4: 353 hw->bus.width = ixgbe_bus_width_pcie_x4; 354 break; 355 case IXGBE_PCI_LINK_WIDTH_8: 356 hw->bus.width = ixgbe_bus_width_pcie_x8; 357 break; 358 default: 359 hw->bus.width = ixgbe_bus_width_unknown; 360 break; 361 } 362 363 switch (link_status & IXGBE_PCI_LINK_SPEED) { 364 case IXGBE_PCI_LINK_SPEED_2500: 365 hw->bus.speed = ixgbe_bus_speed_2500; 366 break; 367 case IXGBE_PCI_LINK_SPEED_5000: 368 hw->bus.speed = ixgbe_bus_speed_5000; 369 break; 370 default: 371 hw->bus.speed = ixgbe_bus_speed_unknown; 372 break; 373 } 374 375 return IXGBE_SUCCESS; 376 } 377 378 /** 379 * ixgbe_stop_adapter_generic - Generic stop Tx/Rx units 380 * @hw: pointer to hardware structure 381 * 382 * Sets the adapter_stopped flag within ixgbe_hw struct. Clears interrupts, 383 * disables transmit and receive units. The adapter_stopped flag is used by 384 * the shared code and drivers to determine if the adapter is in a stopped 385 * state and should not touch the hardware. 386 **/ 387 int32_t ixgbe_stop_adapter_generic(struct ixgbe_hw *hw) 388 { 389 uint32_t number_of_queues; 390 uint32_t reg_val; 391 uint16_t i; 392 393 /* 394 * Set the adapter_stopped flag so other driver functions stop touching 395 * the hardware 396 */ 397 hw->adapter_stopped = TRUE; 398 399 /* Disable the receive unit */ 400 reg_val = IXGBE_READ_REG(hw, IXGBE_RXCTRL); 401 reg_val &= ~(IXGBE_RXCTRL_RXEN); 402 IXGBE_WRITE_REG(hw, IXGBE_RXCTRL, reg_val); 403 IXGBE_WRITE_FLUSH(hw); 404 msec_delay(2); 405 406 /* Clear interrupt mask to stop from interrupts being generated */ 407 IXGBE_WRITE_REG(hw, IXGBE_EIMC, IXGBE_IRQ_CLEAR_MASK); 408 409 /* Clear any pending interrupts */ 410 IXGBE_READ_REG(hw, IXGBE_EICR); 411 412 /* Disable the transmit unit. Each queue must be disabled. */ 413 number_of_queues = hw->mac.max_tx_queues; 414 for (i = 0; i < number_of_queues; i++) { 415 reg_val = IXGBE_READ_REG(hw, IXGBE_TXDCTL(i)); 416 if (reg_val & IXGBE_TXDCTL_ENABLE) { 417 reg_val &= ~IXGBE_TXDCTL_ENABLE; 418 IXGBE_WRITE_REG(hw, IXGBE_TXDCTL(i), reg_val); 419 } 420 } 421 422 /* 423 * Prevent the PCI-E bus from from hanging by disabling PCI-E master 424 * access and verify no pending requests 425 */ 426 if (ixgbe_disable_pcie_master(hw) != IXGBE_SUCCESS) { 427 DEBUGOUT("PCI-E Master disable polling has failed.\n"); 428 } 429 430 return IXGBE_SUCCESS; 431 } 432 433 /** 434 * ixgbe_led_on_generic - Turns on the software controllable LEDs. 435 * @hw: pointer to hardware structure 436 * @index: led number to turn on 437 **/ 438 int32_t ixgbe_led_on_generic(struct ixgbe_hw *hw, uint32_t index) 439 { 440 uint32_t led_reg = IXGBE_READ_REG(hw, IXGBE_LEDCTL); 441 442 /* To turn on the LED, set mode to ON. */ 443 led_reg &= ~IXGBE_LED_MODE_MASK(index); 444 led_reg |= IXGBE_LED_ON << IXGBE_LED_MODE_SHIFT(index); 445 IXGBE_WRITE_REG(hw, IXGBE_LEDCTL, led_reg); 446 IXGBE_WRITE_FLUSH(hw); 447 448 return IXGBE_SUCCESS; 449 } 450 451 /** 452 * ixgbe_led_off_generic - Turns off the software controllable LEDs. 453 * @hw: pointer to hardware structure 454 * @index: led number to turn off 455 **/ 456 int32_t ixgbe_led_off_generic(struct ixgbe_hw *hw, uint32_t index) 457 { 458 uint32_t led_reg = IXGBE_READ_REG(hw, IXGBE_LEDCTL); 459 460 /* To turn off the LED, set mode to OFF. */ 461 led_reg &= ~IXGBE_LED_MODE_MASK(index); 462 led_reg |= IXGBE_LED_OFF << IXGBE_LED_MODE_SHIFT(index); 463 IXGBE_WRITE_REG(hw, IXGBE_LEDCTL, led_reg); 464 IXGBE_WRITE_FLUSH(hw); 465 466 return IXGBE_SUCCESS; 467 } 468 469 /** 470 * ixgbe_init_eeprom_params_generic - Initialize EEPROM params 471 * @hw: pointer to hardware structure 472 * 473 * Initializes the EEPROM parameters ixgbe_eeprom_info within the 474 * ixgbe_hw struct in order to set up EEPROM access. 475 **/ 476 int32_t ixgbe_init_eeprom_params_generic(struct ixgbe_hw *hw) 477 { 478 struct ixgbe_eeprom_info *eeprom = &hw->eeprom; 479 uint32_t eec; 480 uint16_t eeprom_size; 481 482 if (eeprom->type == ixgbe_eeprom_uninitialized) { 483 eeprom->type = ixgbe_eeprom_none; 484 485 /* 486 * Check for EEPROM present first. 487 * If not present leave as none 488 */ 489 eec = IXGBE_READ_REG(hw, IXGBE_EEC); 490 if (eec & IXGBE_EEC_PRES) { 491 eeprom->type = ixgbe_eeprom_spi; 492 493 /* 494 * SPI EEPROM is assumed here. This code would need to 495 * change if a future EEPROM is not SPI. 496 */ 497 eeprom_size = (uint16_t)((eec & IXGBE_EEC_SIZE) >> 498 IXGBE_EEC_SIZE_SHIFT); 499 eeprom->word_size = 1 << (eeprom_size + 500 IXGBE_EEPROM_WORD_SIZE_SHIFT); 501 } 502 503 if (eec & IXGBE_EEC_ADDR_SIZE) 504 eeprom->address_bits = 16; 505 else 506 eeprom->address_bits = 8; 507 DEBUGOUT3("Eeprom params: type = %d, size = %d, address bits: " 508 "%d\n", eeprom->type, eeprom->word_size, 509 eeprom->address_bits); 510 } 511 512 return IXGBE_SUCCESS; 513 } 514 515 /** 516 * ixgbe_write_eeprom_generic - Writes 16 bit value to EEPROM 517 * @hw: pointer to hardware structure 518 * @offset: offset within the EEPROM to be written to 519 * @data: 16 bit word to be written to the EEPROM 520 * 521 * If ixgbe_eeprom_update_checksum is not called after this function, the 522 * EEPROM will most likely contain an invalid checksum. 523 **/ 524 int32_t ixgbe_write_eeprom_generic(struct ixgbe_hw *hw, uint16_t offset, uint16_t data) 525 { 526 int32_t status; 527 uint8_t write_opcode = IXGBE_EEPROM_WRITE_OPCODE_SPI; 528 529 hw->eeprom.ops.init_params(hw); 530 531 if (offset >= hw->eeprom.word_size) { 532 status = IXGBE_ERR_EEPROM; 533 goto out; 534 } 535 536 /* Prepare the EEPROM for writing */ 537 status = ixgbe_acquire_eeprom(hw); 538 539 if (status == IXGBE_SUCCESS) { 540 if (ixgbe_ready_eeprom(hw) != IXGBE_SUCCESS) { 541 ixgbe_release_eeprom(hw); 542 status = IXGBE_ERR_EEPROM; 543 } 544 } 545 546 if (status == IXGBE_SUCCESS) { 547 ixgbe_standby_eeprom(hw); 548 549 /* Send the WRITE ENABLE command (8 bit opcode ) */ 550 ixgbe_shift_out_eeprom_bits(hw, IXGBE_EEPROM_WREN_OPCODE_SPI, 551 IXGBE_EEPROM_OPCODE_BITS); 552 553 ixgbe_standby_eeprom(hw); 554 555 /* 556 * Some SPI eeproms use the 8th address bit embedded in the 557 * opcode 558 */ 559 if ((hw->eeprom.address_bits == 8) && (offset >= 128)) 560 write_opcode |= IXGBE_EEPROM_A8_OPCODE_SPI; 561 562 /* Send the Write command (8-bit opcode + addr) */ 563 ixgbe_shift_out_eeprom_bits(hw, write_opcode, 564 IXGBE_EEPROM_OPCODE_BITS); 565 ixgbe_shift_out_eeprom_bits(hw, (uint16_t)(offset*2), 566 hw->eeprom.address_bits); 567 568 /* Send the data */ 569 data = (data >> 8) | (data << 8); 570 ixgbe_shift_out_eeprom_bits(hw, data, 16); 571 ixgbe_standby_eeprom(hw); 572 573 msec_delay(10); 574 575 /* Done with writing - release the EEPROM */ 576 ixgbe_release_eeprom(hw); 577 } 578 579 out: 580 return status; 581 } 582 583 /** 584 * ixgbe_read_eeprom_bit_bang_generic - Read EEPROM word using bit-bang 585 * @hw: pointer to hardware structure 586 * @offset: offset within the EEPROM to be read 587 * @data: read 16 bit value from EEPROM 588 * 589 * Reads 16 bit value from EEPROM through bit-bang method 590 **/ 591 int32_t ixgbe_read_eeprom_bit_bang_generic(struct ixgbe_hw *hw, uint16_t offset, 592 uint16_t *data) 593 { 594 int32_t status; 595 uint16_t word_in; 596 uint8_t read_opcode = IXGBE_EEPROM_READ_OPCODE_SPI; 597 598 hw->eeprom.ops.init_params(hw); 599 600 if (offset >= hw->eeprom.word_size) { 601 status = IXGBE_ERR_EEPROM; 602 goto out; 603 } 604 605 /* Prepare the EEPROM for reading */ 606 status = ixgbe_acquire_eeprom(hw); 607 608 if (status == IXGBE_SUCCESS) { 609 if (ixgbe_ready_eeprom(hw) != IXGBE_SUCCESS) { 610 ixgbe_release_eeprom(hw); 611 status = IXGBE_ERR_EEPROM; 612 } 613 } 614 615 if (status == IXGBE_SUCCESS) { 616 ixgbe_standby_eeprom(hw); 617 618 /* 619 * Some SPI eeproms use the 8th address bit embedded in the 620 * opcode 621 */ 622 if ((hw->eeprom.address_bits == 8) && (offset >= 128)) 623 read_opcode |= IXGBE_EEPROM_A8_OPCODE_SPI; 624 625 /* Send the READ command (opcode + addr) */ 626 ixgbe_shift_out_eeprom_bits(hw, read_opcode, 627 IXGBE_EEPROM_OPCODE_BITS); 628 ixgbe_shift_out_eeprom_bits(hw, (uint16_t)(offset*2), 629 hw->eeprom.address_bits); 630 631 /* Read the data. */ 632 word_in = ixgbe_shift_in_eeprom_bits(hw, 16); 633 *data = (word_in >> 8) | (word_in << 8); 634 635 /* End this read operation */ 636 ixgbe_release_eeprom(hw); 637 } 638 639 out: 640 return status; 641 } 642 643 /** 644 * ixgbe_read_eeprom_generic - Read EEPROM word using EERD 645 * @hw: pointer to hardware structure 646 * @offset: offset of word in the EEPROM to read 647 * @data: word read from the EEPROM 648 * 649 * Reads a 16 bit word from the EEPROM using the EERD register. 650 **/ 651 int32_t ixgbe_read_eeprom_generic(struct ixgbe_hw *hw, uint16_t offset, uint16_t *data) 652 { 653 uint32_t eerd; 654 int32_t status; 655 656 hw->eeprom.ops.init_params(hw); 657 658 if (offset >= hw->eeprom.word_size) { 659 status = IXGBE_ERR_EEPROM; 660 goto out; 661 } 662 663 eerd = (offset << IXGBE_EEPROM_READ_ADDR_SHIFT) + 664 IXGBE_EEPROM_READ_REG_START; 665 666 IXGBE_WRITE_REG(hw, IXGBE_EERD, eerd); 667 status = ixgbe_poll_eeprom_eerd_done(hw); 668 669 if (status == IXGBE_SUCCESS) 670 *data = (IXGBE_READ_REG(hw, IXGBE_EERD) >> 671 IXGBE_EEPROM_READ_REG_DATA); 672 else 673 DEBUGOUT("Eeprom read timed out\n"); 674 675 out: 676 return status; 677 } 678 679 /** 680 * ixgbe_poll_eeprom_eerd_done - Poll EERD status 681 * @hw: pointer to hardware structure 682 * 683 * Polls the status bit (bit 1) of the EERD to determine when the read is done. 684 **/ 685 static int32_t ixgbe_poll_eeprom_eerd_done(struct ixgbe_hw *hw) 686 { 687 uint32_t i; 688 uint32_t reg; 689 int32_t status = IXGBE_ERR_EEPROM; 690 691 for (i = 0; i < IXGBE_EERD_ATTEMPTS; i++) { 692 reg = IXGBE_READ_REG(hw, IXGBE_EERD); 693 if (reg & IXGBE_EEPROM_READ_REG_DONE) { 694 status = IXGBE_SUCCESS; 695 break; 696 } 697 usec_delay(5); 698 } 699 return status; 700 } 701 702 /** 703 * ixgbe_acquire_eeprom - Acquire EEPROM using bit-bang 704 * @hw: pointer to hardware structure 705 * 706 * Prepares EEPROM for access using bit-bang method. This function should 707 * be called before issuing a command to the EEPROM. 708 **/ 709 static int32_t ixgbe_acquire_eeprom(struct ixgbe_hw *hw) 710 { 711 int32_t status = IXGBE_SUCCESS; 712 uint32_t eec; 713 uint32_t i; 714 715 if (ixgbe_acquire_swfw_sync(hw, IXGBE_GSSR_EEP_SM) != IXGBE_SUCCESS) 716 status = IXGBE_ERR_SWFW_SYNC; 717 718 if (status == IXGBE_SUCCESS) { 719 eec = IXGBE_READ_REG(hw, IXGBE_EEC); 720 721 /* Request EEPROM Access */ 722 eec |= IXGBE_EEC_REQ; 723 IXGBE_WRITE_REG(hw, IXGBE_EEC, eec); 724 725 for (i = 0; i < IXGBE_EEPROM_GRANT_ATTEMPTS; i++) { 726 eec = IXGBE_READ_REG(hw, IXGBE_EEC); 727 if (eec & IXGBE_EEC_GNT) 728 break; 729 usec_delay(5); 730 } 731 732 /* Release if grant not acquired */ 733 if (!(eec & IXGBE_EEC_GNT)) { 734 eec &= ~IXGBE_EEC_REQ; 735 IXGBE_WRITE_REG(hw, IXGBE_EEC, eec); 736 DEBUGOUT("Could not acquire EEPROM grant\n"); 737 738 ixgbe_release_swfw_sync(hw, IXGBE_GSSR_EEP_SM); 739 status = IXGBE_ERR_EEPROM; 740 } 741 } 742 743 /* Setup EEPROM for Read/Write */ 744 if (status == IXGBE_SUCCESS) { 745 /* Clear CS and SK */ 746 eec &= ~(IXGBE_EEC_CS | IXGBE_EEC_SK); 747 IXGBE_WRITE_REG(hw, IXGBE_EEC, eec); 748 IXGBE_WRITE_FLUSH(hw); 749 usec_delay(1); 750 } 751 return status; 752 } 753 754 /** 755 * ixgbe_get_eeprom_semaphore - Get hardware semaphore 756 * @hw: pointer to hardware structure 757 * 758 * Sets the hardware semaphores so EEPROM access can occur for bit-bang method 759 **/ 760 static int32_t ixgbe_get_eeprom_semaphore(struct ixgbe_hw *hw) 761 { 762 int32_t status = IXGBE_ERR_EEPROM; 763 uint32_t timeout; 764 uint32_t i; 765 uint32_t swsm; 766 767 /* Set timeout value based on size of EEPROM */ 768 timeout = hw->eeprom.word_size + 1; 769 770 /* Get SMBI software semaphore between device drivers first */ 771 for (i = 0; i < timeout; i++) { 772 /* 773 * If the SMBI bit is 0 when we read it, then the bit will be 774 * set and we have the semaphore 775 */ 776 swsm = IXGBE_READ_REG(hw, IXGBE_SWSM); 777 if (!(swsm & IXGBE_SWSM_SMBI)) { 778 status = IXGBE_SUCCESS; 779 break; 780 } 781 msec_delay(1); 782 } 783 784 /* Now get the semaphore between SW/FW through the SWESMBI bit */ 785 if (status == IXGBE_SUCCESS) { 786 for (i = 0; i < timeout; i++) { 787 swsm = IXGBE_READ_REG(hw, IXGBE_SWSM); 788 789 /* Set the SW EEPROM semaphore bit to request access */ 790 swsm |= IXGBE_SWSM_SWESMBI; 791 IXGBE_WRITE_REG(hw, IXGBE_SWSM, swsm); 792 793 /* 794 * If we set the bit successfully then we got the 795 * semaphore. 796 */ 797 swsm = IXGBE_READ_REG(hw, IXGBE_SWSM); 798 if (swsm & IXGBE_SWSM_SWESMBI) 799 break; 800 801 usec_delay(50); 802 } 803 804 /* 805 * Release semaphores and return error if SW EEPROM semaphore 806 * was not granted because we don't have access to the EEPROM 807 */ 808 if (i >= timeout) { 809 DEBUGOUT("Driver can't access the Eeprom - Semaphore " 810 "not granted.\n"); 811 ixgbe_release_eeprom_semaphore(hw); 812 status = IXGBE_ERR_EEPROM; 813 } 814 } 815 816 return status; 817 } 818 819 /** 820 * ixgbe_release_eeprom_semaphore - Release hardware semaphore 821 * @hw: pointer to hardware structure 822 * 823 * This function clears hardware semaphore bits. 824 **/ 825 static void ixgbe_release_eeprom_semaphore(struct ixgbe_hw *hw) 826 { 827 uint32_t swsm; 828 829 swsm = IXGBE_READ_REG(hw, IXGBE_SWSM); 830 831 /* Release both semaphores by writing 0 to the bits SWESMBI and SMBI */ 832 swsm &= ~(IXGBE_SWSM_SWESMBI | IXGBE_SWSM_SMBI); 833 IXGBE_WRITE_REG(hw, IXGBE_SWSM, swsm); 834 IXGBE_WRITE_FLUSH(hw); 835 } 836 837 /** 838 * ixgbe_ready_eeprom - Polls for EEPROM ready 839 * @hw: pointer to hardware structure 840 **/ 841 static int32_t ixgbe_ready_eeprom(struct ixgbe_hw *hw) 842 { 843 int32_t status = IXGBE_SUCCESS; 844 uint16_t i; 845 uint8_t spi_stat_reg; 846 847 /* 848 * Read "Status Register" repeatedly until the LSB is cleared. The 849 * EEPROM will signal that the command has been completed by clearing 850 * bit 0 of the internal status register. If it's not cleared within 851 * 5 milliseconds, then error out. 852 */ 853 for (i = 0; i < IXGBE_EEPROM_MAX_RETRY_SPI; i += 5) { 854 ixgbe_shift_out_eeprom_bits(hw, IXGBE_EEPROM_RDSR_OPCODE_SPI, 855 IXGBE_EEPROM_OPCODE_BITS); 856 spi_stat_reg = (uint8_t)ixgbe_shift_in_eeprom_bits(hw, 8); 857 if (!(spi_stat_reg & IXGBE_EEPROM_STATUS_RDY_SPI)) 858 break; 859 860 usec_delay(5); 861 ixgbe_standby_eeprom(hw); 862 }; 863 864 /* 865 * On some parts, SPI write time could vary from 0-20mSec on 3.3V 866 * devices (and only 0-5mSec on 5V devices) 867 */ 868 if (i >= IXGBE_EEPROM_MAX_RETRY_SPI) { 869 DEBUGOUT("SPI EEPROM Status error\n"); 870 status = IXGBE_ERR_EEPROM; 871 } 872 873 return status; 874 } 875 876 /** 877 * ixgbe_standby_eeprom - Returns EEPROM to a "standby" state 878 * @hw: pointer to hardware structure 879 **/ 880 static void ixgbe_standby_eeprom(struct ixgbe_hw *hw) 881 { 882 uint32_t eec; 883 884 eec = IXGBE_READ_REG(hw, IXGBE_EEC); 885 886 /* Toggle CS to flush commands */ 887 eec |= IXGBE_EEC_CS; 888 IXGBE_WRITE_REG(hw, IXGBE_EEC, eec); 889 IXGBE_WRITE_FLUSH(hw); 890 usec_delay(1); 891 eec &= ~IXGBE_EEC_CS; 892 IXGBE_WRITE_REG(hw, IXGBE_EEC, eec); 893 IXGBE_WRITE_FLUSH(hw); 894 usec_delay(1); 895 } 896 897 /** 898 * ixgbe_shift_out_eeprom_bits - Shift data bits out to the EEPROM. 899 * @hw: pointer to hardware structure 900 * @data: data to send to the EEPROM 901 * @count: number of bits to shift out 902 **/ 903 static void ixgbe_shift_out_eeprom_bits(struct ixgbe_hw *hw, uint16_t data, 904 uint16_t count) 905 { 906 uint32_t eec; 907 uint32_t mask; 908 uint32_t i; 909 910 eec = IXGBE_READ_REG(hw, IXGBE_EEC); 911 912 /* 913 * Mask is used to shift "count" bits of "data" out to the EEPROM 914 * one bit at a time. Determine the starting bit based on count 915 */ 916 mask = 0x01 << (count - 1); 917 918 for (i = 0; i < count; i++) { 919 /* 920 * A "1" is shifted out to the EEPROM by setting bit "DI" to a 921 * "1", and then raising and then lowering the clock (the SK 922 * bit controls the clock input to the EEPROM). A "0" is 923 * shifted out to the EEPROM by setting "DI" to "0" and then 924 * raising and then lowering the clock. 925 */ 926 if (data & mask) 927 eec |= IXGBE_EEC_DI; 928 else 929 eec &= ~IXGBE_EEC_DI; 930 931 IXGBE_WRITE_REG(hw, IXGBE_EEC, eec); 932 IXGBE_WRITE_FLUSH(hw); 933 934 usec_delay(1); 935 936 ixgbe_raise_eeprom_clk(hw, &eec); 937 ixgbe_lower_eeprom_clk(hw, &eec); 938 939 /* 940 * Shift mask to signify next bit of data to shift in to the 941 * EEPROM 942 */ 943 mask = mask >> 1; 944 }; 945 946 /* We leave the "DI" bit set to "0" when we leave this routine. */ 947 eec &= ~IXGBE_EEC_DI; 948 IXGBE_WRITE_REG(hw, IXGBE_EEC, eec); 949 IXGBE_WRITE_FLUSH(hw); 950 } 951 952 /** 953 * ixgbe_shift_in_eeprom_bits - Shift data bits in from the EEPROM 954 * @hw: pointer to hardware structure 955 **/ 956 static uint16_t ixgbe_shift_in_eeprom_bits(struct ixgbe_hw *hw, uint16_t count) 957 { 958 uint32_t eec; 959 uint32_t i; 960 uint16_t data = 0; 961 962 /* 963 * In order to read a register from the EEPROM, we need to shift 964 * 'count' bits in from the EEPROM. Bits are "shifted in" by raising 965 * the clock input to the EEPROM (setting the SK bit), and then reading 966 * the value of the "DO" bit. During this "shifting in" process the 967 * "DI" bit should always be clear. 968 */ 969 eec = IXGBE_READ_REG(hw, IXGBE_EEC); 970 971 eec &= ~(IXGBE_EEC_DO | IXGBE_EEC_DI); 972 973 for (i = 0; i < count; i++) { 974 data = data << 1; 975 ixgbe_raise_eeprom_clk(hw, &eec); 976 977 eec = IXGBE_READ_REG(hw, IXGBE_EEC); 978 979 eec &= ~(IXGBE_EEC_DI); 980 if (eec & IXGBE_EEC_DO) 981 data |= 1; 982 983 ixgbe_lower_eeprom_clk(hw, &eec); 984 } 985 986 return data; 987 } 988 989 /** 990 * ixgbe_raise_eeprom_clk - Raises the EEPROM's clock input. 991 * @hw: pointer to hardware structure 992 * @eec: EEC register's current value 993 **/ 994 static void ixgbe_raise_eeprom_clk(struct ixgbe_hw *hw, uint32_t *eec) 995 { 996 /* 997 * Raise the clock input to the EEPROM 998 * (setting the SK bit), then delay 999 */ 1000 *eec = *eec | IXGBE_EEC_SK; 1001 IXGBE_WRITE_REG(hw, IXGBE_EEC, *eec); 1002 IXGBE_WRITE_FLUSH(hw); 1003 usec_delay(1); 1004 } 1005 1006 /** 1007 * ixgbe_lower_eeprom_clk - Lowers the EEPROM's clock input. 1008 * @hw: pointer to hardware structure 1009 * @eecd: EECD's current value 1010 **/ 1011 static void ixgbe_lower_eeprom_clk(struct ixgbe_hw *hw, uint32_t *eec) 1012 { 1013 /* 1014 * Lower the clock input to the EEPROM (clearing the SK bit), then 1015 * delay 1016 */ 1017 *eec = *eec & ~IXGBE_EEC_SK; 1018 IXGBE_WRITE_REG(hw, IXGBE_EEC, *eec); 1019 IXGBE_WRITE_FLUSH(hw); 1020 usec_delay(1); 1021 } 1022 1023 /** 1024 * ixgbe_release_eeprom - Release EEPROM, release semaphores 1025 * @hw: pointer to hardware structure 1026 **/ 1027 static void ixgbe_release_eeprom(struct ixgbe_hw *hw) 1028 { 1029 uint32_t eec; 1030 1031 eec = IXGBE_READ_REG(hw, IXGBE_EEC); 1032 1033 eec |= IXGBE_EEC_CS; /* Pull CS high */ 1034 eec &= ~IXGBE_EEC_SK; /* Lower SCK */ 1035 1036 IXGBE_WRITE_REG(hw, IXGBE_EEC, eec); 1037 IXGBE_WRITE_FLUSH(hw); 1038 1039 usec_delay(1); 1040 1041 /* Stop requesting EEPROM access */ 1042 eec &= ~IXGBE_EEC_REQ; 1043 IXGBE_WRITE_REG(hw, IXGBE_EEC, eec); 1044 1045 ixgbe_release_swfw_sync(hw, IXGBE_GSSR_EEP_SM); 1046 } 1047 1048 /** 1049 * ixgbe_calc_eeprom_checksum - Calculates and returns the checksum 1050 * @hw: pointer to hardware structure 1051 **/ 1052 static uint16_t ixgbe_calc_eeprom_checksum(struct ixgbe_hw *hw) 1053 { 1054 uint16_t i; 1055 uint16_t j; 1056 uint16_t checksum = 0; 1057 uint16_t length = 0; 1058 uint16_t pointer = 0; 1059 uint16_t word = 0; 1060 1061 /* Include 0x0-0x3F in the checksum */ 1062 for (i = 0; i < IXGBE_EEPROM_CHECKSUM; i++) { 1063 if (hw->eeprom.ops.read(hw, i, &word) != IXGBE_SUCCESS) { 1064 DEBUGOUT("EEPROM read failed\n"); 1065 break; 1066 } 1067 checksum += word; 1068 } 1069 1070 /* Include all data from pointers except for the fw pointer */ 1071 for (i = IXGBE_PCIE_ANALOG_PTR; i < IXGBE_FW_PTR; i++) { 1072 hw->eeprom.ops.read(hw, i, &pointer); 1073 1074 /* Make sure the pointer seems valid */ 1075 if (pointer != 0xFFFF && pointer != 0) { 1076 hw->eeprom.ops.read(hw, pointer, &length); 1077 1078 if (length != 0xFFFF && length != 0) { 1079 for (j = pointer+1; j <= pointer+length; j++) { 1080 hw->eeprom.ops.read(hw, j, &word); 1081 checksum += word; 1082 } 1083 } 1084 } 1085 } 1086 1087 checksum = (uint16_t)IXGBE_EEPROM_SUM - checksum; 1088 1089 return checksum; 1090 } 1091 1092 /** 1093 * ixgbe_validate_eeprom_checksum_generic - Validate EEPROM checksum 1094 * @hw: pointer to hardware structure 1095 * @checksum_val: calculated checksum 1096 * 1097 * Performs checksum calculation and validates the EEPROM checksum. If the 1098 * caller does not need checksum_val, the value can be NULL. 1099 **/ 1100 int32_t ixgbe_validate_eeprom_checksum_generic(struct ixgbe_hw *hw, 1101 uint16_t *checksum_val) 1102 { 1103 int32_t status; 1104 uint16_t checksum; 1105 uint16_t read_checksum = 0; 1106 1107 /* 1108 * Read the first word from the EEPROM. If this times out or fails, do 1109 * not continue or we could be in for a very long wait while every 1110 * EEPROM read fails 1111 */ 1112 status = hw->eeprom.ops.read(hw, 0, &checksum); 1113 1114 if (status == IXGBE_SUCCESS) { 1115 checksum = ixgbe_calc_eeprom_checksum(hw); 1116 1117 hw->eeprom.ops.read(hw, IXGBE_EEPROM_CHECKSUM, &read_checksum); 1118 1119 /* 1120 * Verify read checksum from EEPROM is the same as 1121 * calculated checksum 1122 */ 1123 if (read_checksum != checksum) 1124 status = IXGBE_ERR_EEPROM_CHECKSUM; 1125 1126 /* If the user cares, return the calculated checksum */ 1127 if (checksum_val) 1128 *checksum_val = checksum; 1129 } else { 1130 DEBUGOUT("EEPROM read failed\n"); 1131 } 1132 1133 return status; 1134 } 1135 1136 /** 1137 * ixgbe_update_eeprom_checksum_generic - Updates the EEPROM checksum 1138 * @hw: pointer to hardware structure 1139 **/ 1140 int32_t ixgbe_update_eeprom_checksum_generic(struct ixgbe_hw *hw) 1141 { 1142 int32_t status; 1143 uint16_t checksum; 1144 1145 /* 1146 * Read the first word from the EEPROM. If this times out or fails, do 1147 * not continue or we could be in for a very long wait while every 1148 * EEPROM read fails 1149 */ 1150 status = hw->eeprom.ops.read(hw, 0, &checksum); 1151 1152 if (status == IXGBE_SUCCESS) { 1153 checksum = ixgbe_calc_eeprom_checksum(hw); 1154 status = hw->eeprom.ops.write(hw, IXGBE_EEPROM_CHECKSUM, 1155 checksum); 1156 } else { 1157 DEBUGOUT("EEPROM read failed\n"); 1158 } 1159 1160 return status; 1161 } 1162 1163 /** 1164 * ixgbe_validate_mac_addr - Validate MAC address 1165 * @mac_addr: pointer to MAC address. 1166 * 1167 * Tests a MAC address to ensure it is a valid Individual Address 1168 **/ 1169 int32_t ixgbe_validate_mac_addr(uint8_t *mac_addr) 1170 { 1171 int32_t status = IXGBE_SUCCESS; 1172 1173 /* Make sure it is not a multicast address */ 1174 if (IXGBE_IS_MULTICAST(mac_addr)) { 1175 DEBUGOUT("MAC address is multicast\n"); 1176 status = IXGBE_ERR_INVALID_MAC_ADDR; 1177 /* Not a broadcast address */ 1178 } else if (IXGBE_IS_BROADCAST(mac_addr)) { 1179 DEBUGOUT("MAC address is broadcast\n"); 1180 status = IXGBE_ERR_INVALID_MAC_ADDR; 1181 /* Reject the zero address */ 1182 } else if (mac_addr[0] == 0 && mac_addr[1] == 0 && mac_addr[2] == 0 && 1183 mac_addr[3] == 0 && mac_addr[4] == 0 && mac_addr[5] == 0) { 1184 DEBUGOUT("MAC address is all zeros\n"); 1185 status = IXGBE_ERR_INVALID_MAC_ADDR; 1186 } 1187 return status; 1188 } 1189 1190 /** 1191 * ixgbe_set_rar_generic - Set Rx address register 1192 * @hw: pointer to hardware structure 1193 * @index: Receive address register to write 1194 * @addr: Address to put into receive address register 1195 * @vmdq: VMDq "set" or "pool" index 1196 * @enable_addr: set flag that address is active 1197 * 1198 * Puts an ethernet address into a receive address register. 1199 **/ 1200 int32_t ixgbe_set_rar_generic(struct ixgbe_hw *hw, uint32_t index, uint8_t *addr, uint32_t vmdq, 1201 uint32_t enable_addr) 1202 { 1203 uint32_t rar_low, rar_high; 1204 uint32_t rar_entries = hw->mac.num_rar_entries; 1205 1206 /* setup VMDq pool selection before this RAR gets enabled */ 1207 hw->mac.ops.set_vmdq(hw, index, vmdq); 1208 1209 /* Make sure we are using a valid rar index range */ 1210 if (index < rar_entries) { 1211 /* 1212 * HW expects these in little endian so we reverse the byte 1213 * order from network order (big endian) to little endian 1214 */ 1215 rar_low = ((uint32_t)addr[0] | 1216 ((uint32_t)addr[1] << 8) | 1217 ((uint32_t)addr[2] << 16) | 1218 ((uint32_t)addr[3] << 24)); 1219 /* 1220 * Some parts put the VMDq setting in the extra RAH bits, 1221 * so save everything except the lower 16 bits that hold part 1222 * of the address and the address valid bit. 1223 */ 1224 rar_high = IXGBE_READ_REG(hw, IXGBE_RAH(index)); 1225 rar_high &= ~(0x0000FFFF | IXGBE_RAH_AV); 1226 rar_high |= ((uint32_t)addr[4] | ((uint32_t)addr[5] << 8)); 1227 1228 if (enable_addr != 0) 1229 rar_high |= IXGBE_RAH_AV; 1230 1231 IXGBE_WRITE_REG(hw, IXGBE_RAL(index), rar_low); 1232 IXGBE_WRITE_REG(hw, IXGBE_RAH(index), rar_high); 1233 } else { 1234 DEBUGOUT("Current RAR index is out of range."); 1235 } 1236 1237 return IXGBE_SUCCESS; 1238 } 1239 1240 /** 1241 * ixgbe_enable_rar - Enable Rx address register 1242 * @hw: pointer to hardware structure 1243 * @index: index into the RAR table 1244 * 1245 * Enables the select receive address register. 1246 **/ 1247 static void ixgbe_enable_rar(struct ixgbe_hw *hw, uint32_t index) 1248 { 1249 uint32_t rar_high; 1250 1251 rar_high = IXGBE_READ_REG(hw, IXGBE_RAH(index)); 1252 rar_high |= IXGBE_RAH_AV; 1253 IXGBE_WRITE_REG(hw, IXGBE_RAH(index), rar_high); 1254 } 1255 1256 /** 1257 * ixgbe_disable_rar - Disable Rx address register 1258 * @hw: pointer to hardware structure 1259 * @index: index into the RAR table 1260 * 1261 * Disables the select receive address register. 1262 **/ 1263 static void ixgbe_disable_rar(struct ixgbe_hw *hw, uint32_t index) 1264 { 1265 uint32_t rar_high; 1266 1267 rar_high = IXGBE_READ_REG(hw, IXGBE_RAH(index)); 1268 rar_high &= (~IXGBE_RAH_AV); 1269 IXGBE_WRITE_REG(hw, IXGBE_RAH(index), rar_high); 1270 } 1271 1272 /** 1273 * ixgbe_init_rx_addrs_generic - Initializes receive address filters. 1274 * @hw: pointer to hardware structure 1275 * 1276 * Places the MAC address in receive address register 0 and clears the rest 1277 * of the receive address registers. Clears the multicast table. Assumes 1278 * the receiver is in reset when the routine is called. 1279 **/ 1280 int32_t ixgbe_init_rx_addrs_generic(struct ixgbe_hw *hw) 1281 { 1282 uint32_t i; 1283 uint32_t rar_entries = hw->mac.num_rar_entries; 1284 1285 /* 1286 * If the current mac address is valid, assume it is a software override 1287 * to the permanent address. 1288 * Otherwise, use the permanent address from the eeprom. 1289 */ 1290 if (ixgbe_validate_mac_addr(hw->mac.addr) == 1291 IXGBE_ERR_INVALID_MAC_ADDR) { 1292 /* Get the MAC address from the RAR0 for later reference */ 1293 hw->mac.ops.get_mac_addr(hw, hw->mac.addr); 1294 1295 DEBUGOUT3(" Keeping Current RAR0 Addr =%.2X %.2X %.2X ", 1296 hw->mac.addr[0], hw->mac.addr[1], 1297 hw->mac.addr[2]); 1298 DEBUGOUT3("%.2X %.2X %.2X\n", hw->mac.addr[3], 1299 hw->mac.addr[4], hw->mac.addr[5]); 1300 } else { 1301 /* Setup the receive address. */ 1302 DEBUGOUT("Overriding MAC Address in RAR[0]\n"); 1303 DEBUGOUT3(" New MAC Addr =%.2X %.2X %.2X ", 1304 hw->mac.addr[0], hw->mac.addr[1], 1305 hw->mac.addr[2]); 1306 DEBUGOUT3("%.2X %.2X %.2X\n", hw->mac.addr[3], 1307 hw->mac.addr[4], hw->mac.addr[5]); 1308 1309 hw->mac.ops.set_rar(hw, 0, hw->mac.addr, 0, IXGBE_RAH_AV); 1310 } 1311 hw->addr_ctrl.overflow_promisc = 0; 1312 1313 hw->addr_ctrl.rar_used_count = 1; 1314 1315 /* Zero out the other receive addresses. */ 1316 DEBUGOUT1("Clearing RAR[1-%d]\n", rar_entries - 1); 1317 for (i = 1; i < rar_entries; i++) { 1318 IXGBE_WRITE_REG(hw, IXGBE_RAL(i), 0); 1319 IXGBE_WRITE_REG(hw, IXGBE_RAH(i), 0); 1320 } 1321 1322 /* Clear the MTA */ 1323 hw->addr_ctrl.mc_addr_in_rar_count = 0; 1324 hw->addr_ctrl.mta_in_use = 0; 1325 IXGBE_WRITE_REG(hw, IXGBE_MCSTCTRL, hw->mac.mc_filter_type); 1326 1327 DEBUGOUT(" Clearing MTA\n"); 1328 for (i = 0; i < hw->mac.mcft_size; i++) 1329 IXGBE_WRITE_REG(hw, IXGBE_MTA(i), 0); 1330 1331 return IXGBE_SUCCESS; 1332 } 1333 1334 /** 1335 * ixgbe_add_uc_addr - Adds a secondary unicast address. 1336 * @hw: pointer to hardware structure 1337 * @addr: new address 1338 * 1339 * Adds it to unused receive address register or goes into promiscuous mode. 1340 **/ 1341 void ixgbe_add_uc_addr(struct ixgbe_hw *hw, uint8_t *addr, uint32_t vmdq) 1342 { 1343 uint32_t rar_entries = hw->mac.num_rar_entries; 1344 uint32_t rar; 1345 1346 DEBUGOUT6(" UC Addr = %.2X %.2X %.2X %.2X %.2X %.2X\n", 1347 addr[0], addr[1], addr[2], addr[3], addr[4], addr[5]); 1348 1349 /* 1350 * Place this address in the RAR if there is room, 1351 * else put the controller into promiscuous mode 1352 */ 1353 if (hw->addr_ctrl.rar_used_count < rar_entries) { 1354 rar = hw->addr_ctrl.rar_used_count - 1355 hw->addr_ctrl.mc_addr_in_rar_count; 1356 hw->mac.ops.set_rar(hw, rar, addr, vmdq, IXGBE_RAH_AV); 1357 DEBUGOUT1("Added a secondary address to RAR[%d]\n", rar); 1358 hw->addr_ctrl.rar_used_count++; 1359 } else { 1360 hw->addr_ctrl.overflow_promisc++; 1361 } 1362 1363 DEBUGOUT("ixgbe_add_uc_addr Complete\n"); 1364 } 1365 1366 /** 1367 * ixgbe_update_uc_addr_list_generic - Updates MAC list of secondary addresses 1368 * @hw: pointer to hardware structure 1369 * @addr_list: the list of new addresses 1370 * @addr_count: number of addresses 1371 * @next: iterator function to walk the address list 1372 * 1373 * The given list replaces any existing list. Clears the secondary addrs from 1374 * receive address registers. Uses unused receive address registers for the 1375 * first secondary addresses, and falls back to promiscuous mode as needed. 1376 * 1377 * Drivers using secondary unicast addresses must set user_set_promisc when 1378 * manually putting the device into promiscuous mode. 1379 **/ 1380 int32_t ixgbe_update_uc_addr_list_generic(struct ixgbe_hw *hw, uint8_t *addr_list, 1381 uint32_t addr_count, ixgbe_mc_addr_itr next) 1382 { 1383 uint8_t *addr; 1384 uint32_t i; 1385 uint32_t old_promisc_setting = hw->addr_ctrl.overflow_promisc; 1386 uint32_t uc_addr_in_use; 1387 uint32_t fctrl; 1388 uint32_t vmdq; 1389 1390 /* 1391 * Clear accounting of old secondary address list, 1392 * don't count RAR[0] 1393 */ 1394 uc_addr_in_use = hw->addr_ctrl.rar_used_count - 1395 hw->addr_ctrl.mc_addr_in_rar_count - 1; 1396 hw->addr_ctrl.rar_used_count -= uc_addr_in_use; 1397 hw->addr_ctrl.overflow_promisc = 0; 1398 1399 /* Zero out the other receive addresses */ 1400 DEBUGOUT1("Clearing RAR[1-%d]\n", uc_addr_in_use); 1401 for (i = 1; i <= uc_addr_in_use; i++) { 1402 IXGBE_WRITE_REG(hw, IXGBE_RAL(i), 0); 1403 IXGBE_WRITE_REG(hw, IXGBE_RAH(i), 0); 1404 } 1405 1406 /* Add the new addresses */ 1407 for (i = 0; i < addr_count; i++) { 1408 DEBUGOUT(" Adding the secondary addresses:\n"); 1409 addr = next(hw, &addr_list, &vmdq); 1410 ixgbe_add_uc_addr(hw, addr, vmdq); 1411 } 1412 1413 if (hw->addr_ctrl.overflow_promisc) { 1414 /* enable promisc if not already in overflow or set by user */ 1415 if (!old_promisc_setting && !hw->addr_ctrl.user_set_promisc) { 1416 DEBUGOUT( " Entering address overflow promisc mode\n"); 1417 fctrl = IXGBE_READ_REG(hw, IXGBE_FCTRL); 1418 fctrl |= IXGBE_FCTRL_UPE; 1419 IXGBE_WRITE_REG(hw, IXGBE_FCTRL, fctrl); 1420 } 1421 } else { 1422 /* only disable if set by overflow, not by user */ 1423 if (old_promisc_setting && !hw->addr_ctrl.user_set_promisc) { 1424 DEBUGOUT(" Leaving address overflow promisc mode\n"); 1425 fctrl = IXGBE_READ_REG(hw, IXGBE_FCTRL); 1426 fctrl &= ~IXGBE_FCTRL_UPE; 1427 IXGBE_WRITE_REG(hw, IXGBE_FCTRL, fctrl); 1428 } 1429 } 1430 1431 DEBUGOUT("ixgbe_update_uc_addr_list_generic Complete\n"); 1432 return IXGBE_SUCCESS; 1433 } 1434 1435 /** 1436 * ixgbe_mta_vector - Determines bit-vector in multicast table to set 1437 * @hw: pointer to hardware structure 1438 * @mc_addr: the multicast address 1439 * 1440 * Extracts the 12 bits, from a multicast address, to determine which 1441 * bit-vector to set in the multicast table. The hardware uses 12 bits, from 1442 * incoming rx multicast addresses, to determine the bit-vector to check in 1443 * the MTA. Which of the 4 combination, of 12-bits, the hardware uses is set 1444 * by the MO field of the MCSTCTRL. The MO field is set during initialization 1445 * to mc_filter_type. 1446 **/ 1447 static int32_t ixgbe_mta_vector(struct ixgbe_hw *hw, uint8_t *mc_addr) 1448 { 1449 uint32_t vector = 0; 1450 1451 switch (hw->mac.mc_filter_type) { 1452 case 0: /* use bits [47:36] of the address */ 1453 vector = ((mc_addr[4] >> 4) | (((uint16_t)mc_addr[5]) << 4)); 1454 break; 1455 case 1: /* use bits [46:35] of the address */ 1456 vector = ((mc_addr[4] >> 3) | (((uint16_t)mc_addr[5]) << 5)); 1457 break; 1458 case 2: /* use bits [45:34] of the address */ 1459 vector = ((mc_addr[4] >> 2) | (((uint16_t)mc_addr[5]) << 6)); 1460 break; 1461 case 3: /* use bits [43:32] of the address */ 1462 vector = ((mc_addr[4]) | (((uint16_t)mc_addr[5]) << 8)); 1463 break; 1464 default: /* Invalid mc_filter_type */ 1465 DEBUGOUT("MC filter type param set incorrectly\n"); 1466 panic("ixgbe"); 1467 break; 1468 } 1469 1470 /* vector can only be 12-bits or boundary will be exceeded */ 1471 vector &= 0xFFF; 1472 return vector; 1473 } 1474 1475 /** 1476 * ixgbe_set_mta - Set bit-vector in multicast table 1477 * @hw: pointer to hardware structure 1478 * @hash_value: Multicast address hash value 1479 * 1480 * Sets the bit-vector in the multicast table. 1481 **/ 1482 void ixgbe_set_mta(struct ixgbe_hw *hw, uint8_t *mc_addr) 1483 { 1484 uint32_t vector; 1485 uint32_t vector_bit; 1486 uint32_t vector_reg; 1487 uint32_t mta_reg; 1488 1489 hw->addr_ctrl.mta_in_use++; 1490 1491 vector = ixgbe_mta_vector(hw, mc_addr); 1492 DEBUGOUT1(" bit-vector = 0x%03X\n", vector); 1493 1494 /* 1495 * The MTA is a register array of 128 32-bit registers. It is treated 1496 * like an array of 4096 bits. We want to set bit 1497 * BitArray[vector_value]. So we figure out what register the bit is 1498 * in, read it, OR in the new bit, then write back the new value. The 1499 * register is determined by the upper 7 bits of the vector value and 1500 * the bit within that register are determined by the lower 5 bits of 1501 * the value. 1502 */ 1503 vector_reg = (vector >> 5) & 0x7F; 1504 vector_bit = vector & 0x1F; 1505 mta_reg = IXGBE_READ_REG(hw, IXGBE_MTA(vector_reg)); 1506 mta_reg |= (1 << vector_bit); 1507 IXGBE_WRITE_REG(hw, IXGBE_MTA(vector_reg), mta_reg); 1508 } 1509 1510 /** 1511 * ixgbe_add_mc_addr - Adds a multicast address. 1512 * @hw: pointer to hardware structure 1513 * @mc_addr: new multicast address 1514 * 1515 * Adds it to unused receive address register or to the multicast table. 1516 **/ 1517 void ixgbe_add_mc_addr(struct ixgbe_hw *hw, uint8_t *mc_addr) 1518 { 1519 uint32_t rar_entries = hw->mac.num_rar_entries; 1520 uint32_t rar; 1521 1522 DEBUGOUT6(" MC Addr =%.2X %.2X %.2X %.2X %.2X %.2X\n", 1523 mc_addr[0], mc_addr[1], mc_addr[2], 1524 mc_addr[3], mc_addr[4], mc_addr[5]); 1525 1526 /* 1527 * Place this multicast address in the RAR if there is room, 1528 * else put it in the MTA 1529 */ 1530 if (hw->addr_ctrl.rar_used_count < rar_entries) { 1531 /* use RAR from the end up for multicast */ 1532 rar = rar_entries - hw->addr_ctrl.mc_addr_in_rar_count - 1; 1533 hw->mac.ops.set_rar(hw, rar, mc_addr, 0, IXGBE_RAH_AV); 1534 DEBUGOUT1("Added a multicast address to RAR[%d]\n", rar); 1535 hw->addr_ctrl.rar_used_count++; 1536 hw->addr_ctrl.mc_addr_in_rar_count++; 1537 } else { 1538 ixgbe_set_mta(hw, mc_addr); 1539 } 1540 1541 DEBUGOUT("ixgbe_add_mc_addr Complete\n"); 1542 } 1543 1544 /** 1545 * ixgbe_update_mc_addr_list_generic - Updates MAC list of multicast addresses 1546 * @hw: pointer to hardware structure 1547 * @mc_addr_list: the list of new multicast addresses 1548 * @mc_addr_count: number of addresses 1549 * @next: iterator function to walk the multicast address list 1550 * 1551 * The given list replaces any existing list. Clears the MC addrs from receive 1552 * address registers and the multicast table. Uses unused receive address 1553 * registers for the first multicast addresses, and hashes the rest into the 1554 * multicast table. 1555 **/ 1556 int32_t ixgbe_update_mc_addr_list_generic(struct ixgbe_hw *hw, uint8_t *mc_addr_list, 1557 uint32_t mc_addr_count, ixgbe_mc_addr_itr next) 1558 { 1559 uint32_t i; 1560 uint32_t rar_entries = hw->mac.num_rar_entries; 1561 uint32_t vmdq; 1562 1563 /* 1564 * Set the new number of MC addresses that we are being requested to 1565 * use. 1566 */ 1567 hw->addr_ctrl.num_mc_addrs = mc_addr_count; 1568 hw->addr_ctrl.rar_used_count -= hw->addr_ctrl.mc_addr_in_rar_count; 1569 hw->addr_ctrl.mc_addr_in_rar_count = 0; 1570 hw->addr_ctrl.mta_in_use = 0; 1571 1572 /* Zero out the other receive addresses. */ 1573 DEBUGOUT2("Clearing RAR[%d-%d]\n", hw->addr_ctrl.rar_used_count, 1574 rar_entries - 1); 1575 for (i = hw->addr_ctrl.rar_used_count; i < rar_entries; i++) { 1576 IXGBE_WRITE_REG(hw, IXGBE_RAL(i), 0); 1577 IXGBE_WRITE_REG(hw, IXGBE_RAH(i), 0); 1578 } 1579 1580 /* Clear the MTA */ 1581 DEBUGOUT(" Clearing MTA\n"); 1582 for (i = 0; i < hw->mac.mcft_size; i++) 1583 IXGBE_WRITE_REG(hw, IXGBE_MTA(i), 0); 1584 1585 /* Add the new addresses */ 1586 for (i = 0; i < mc_addr_count; i++) { 1587 DEBUGOUT(" Adding the multicast addresses:\n"); 1588 ixgbe_add_mc_addr(hw, next(hw, &mc_addr_list, &vmdq)); 1589 } 1590 1591 /* Enable mta */ 1592 if (hw->addr_ctrl.mta_in_use > 0) 1593 IXGBE_WRITE_REG(hw, IXGBE_MCSTCTRL, 1594 IXGBE_MCSTCTRL_MFE | hw->mac.mc_filter_type); 1595 1596 DEBUGOUT("ixgbe_update_mc_addr_list_generic Complete\n"); 1597 return IXGBE_SUCCESS; 1598 } 1599 1600 /** 1601 * ixgbe_enable_mc_generic - Enable multicast address in RAR 1602 * @hw: pointer to hardware structure 1603 * 1604 * Enables multicast address in RAR and the use of the multicast hash table. 1605 **/ 1606 int32_t ixgbe_enable_mc_generic(struct ixgbe_hw *hw) 1607 { 1608 uint32_t i; 1609 uint32_t rar_entries = hw->mac.num_rar_entries; 1610 struct ixgbe_addr_filter_info *a = &hw->addr_ctrl; 1611 1612 if (a->mc_addr_in_rar_count > 0) 1613 for (i = (rar_entries - a->mc_addr_in_rar_count); 1614 i < rar_entries; i++) 1615 ixgbe_enable_rar(hw, i); 1616 1617 if (a->mta_in_use > 0) 1618 IXGBE_WRITE_REG(hw, IXGBE_MCSTCTRL, IXGBE_MCSTCTRL_MFE | 1619 hw->mac.mc_filter_type); 1620 1621 return IXGBE_SUCCESS; 1622 } 1623 1624 /** 1625 * ixgbe_disable_mc_generic - Disable multicast address in RAR 1626 * @hw: pointer to hardware structure 1627 * 1628 * Disables multicast address in RAR and the use of the multicast hash table. 1629 **/ 1630 int32_t ixgbe_disable_mc_generic(struct ixgbe_hw *hw) 1631 { 1632 uint32_t i; 1633 uint32_t rar_entries = hw->mac.num_rar_entries; 1634 struct ixgbe_addr_filter_info *a = &hw->addr_ctrl; 1635 1636 if (a->mc_addr_in_rar_count > 0) 1637 for (i = (rar_entries - a->mc_addr_in_rar_count); 1638 i < rar_entries; i++) 1639 ixgbe_disable_rar(hw, i); 1640 1641 if (a->mta_in_use > 0) 1642 IXGBE_WRITE_REG(hw, IXGBE_MCSTCTRL, hw->mac.mc_filter_type); 1643 1644 return IXGBE_SUCCESS; 1645 } 1646 1647 /** 1648 * ixgbe_clear_vfta_generic - Clear VLAN filter table 1649 * @hw: pointer to hardware structure 1650 * 1651 * Clears the VLAN filer table, and the VMDq index associated with the filter 1652 **/ 1653 int32_t ixgbe_clear_vfta_generic(struct ixgbe_hw *hw) 1654 { 1655 uint32_t offset; 1656 uint32_t vlanbyte; 1657 1658 for (offset = 0; offset < hw->mac.vft_size; offset++) 1659 IXGBE_WRITE_REG(hw, IXGBE_VFTA(offset), 0); 1660 1661 for (vlanbyte = 0; vlanbyte < 4; vlanbyte++) 1662 for (offset = 0; offset < hw->mac.vft_size; offset++) 1663 IXGBE_WRITE_REG(hw, IXGBE_VFTAVIND(vlanbyte, offset), 1664 0); 1665 1666 return IXGBE_SUCCESS; 1667 } 1668 1669 /** 1670 * ixgbe_set_vfta_generic - Set VLAN filter table 1671 * @hw: pointer to hardware structure 1672 * @vlan: VLAN id to write to VLAN filter 1673 * @vind: VMDq output index that maps queue to VLAN id in VFTA 1674 * @vlan_on: intean flag to turn on/off VLAN in VFTA 1675 * 1676 * Turn on/off specified VLAN in the VLAN filter table. 1677 **/ 1678 int32_t ixgbe_set_vfta_generic(struct ixgbe_hw *hw, uint32_t vlan, uint32_t vind, 1679 int vlan_on) 1680 { 1681 uint32_t VftaIndex; 1682 uint32_t BitOffset; 1683 uint32_t VftaReg; 1684 uint32_t VftaByte; 1685 1686 /* Determine 32-bit word position in array */ 1687 VftaIndex = (vlan >> 5) & 0x7F; /* upper seven bits */ 1688 1689 /* Determine the location of the (VMD) queue index */ 1690 VftaByte = ((vlan >> 3) & 0x03); /* bits (4:3) indicating byte array */ 1691 BitOffset = (vlan & 0x7) << 2; /* lower 3 bits indicate nibble */ 1692 1693 /* Set the nibble for VMD queue index */ 1694 VftaReg = IXGBE_READ_REG(hw, IXGBE_VFTAVIND(VftaByte, VftaIndex)); 1695 VftaReg &= (~(0x0F << BitOffset)); 1696 VftaReg |= (vind << BitOffset); 1697 IXGBE_WRITE_REG(hw, IXGBE_VFTAVIND(VftaByte, VftaIndex), VftaReg); 1698 1699 /* Determine the location of the bit for this VLAN id */ 1700 BitOffset = vlan & 0x1F; /* lower five bits */ 1701 1702 VftaReg = IXGBE_READ_REG(hw, IXGBE_VFTA(VftaIndex)); 1703 if (vlan_on) 1704 /* Turn on this VLAN id */ 1705 VftaReg |= (1 << BitOffset); 1706 else 1707 /* Turn off this VLAN id */ 1708 VftaReg &= ~(1 << BitOffset); 1709 IXGBE_WRITE_REG(hw, IXGBE_VFTA(VftaIndex), VftaReg); 1710 1711 return IXGBE_SUCCESS; 1712 } 1713 1714 /** 1715 * ixgbe_disable_pcie_master - Disable PCI-express master access 1716 * @hw: pointer to hardware structure 1717 * 1718 * Disables PCI-Express master access and verifies there are no pending 1719 * requests. IXGBE_ERR_MASTER_REQUESTS_PENDING is returned if master disable 1720 * bit hasn't caused the master requests to be disabled, else IXGBE_SUCCESS 1721 * is returned signifying master requests disabled. 1722 **/ 1723 int32_t ixgbe_disable_pcie_master(struct ixgbe_hw *hw) 1724 { 1725 uint32_t ctrl; 1726 int32_t i; 1727 int32_t status = IXGBE_ERR_MASTER_REQUESTS_PENDING; 1728 1729 ctrl = IXGBE_READ_REG(hw, IXGBE_CTRL); 1730 ctrl |= IXGBE_CTRL_GIO_DIS; 1731 IXGBE_WRITE_REG(hw, IXGBE_CTRL, ctrl); 1732 1733 for (i = 0; i < IXGBE_PCI_MASTER_DISABLE_TIMEOUT; i++) { 1734 if (!(IXGBE_READ_REG(hw, IXGBE_STATUS) & IXGBE_STATUS_GIO)) { 1735 status = IXGBE_SUCCESS; 1736 break; 1737 } 1738 usec_delay(100); 1739 } 1740 1741 return status; 1742 } 1743 1744 1745 /** 1746 * ixgbe_acquire_swfw_sync - Acquire SWFW semaphore 1747 * @hw: pointer to hardware structure 1748 * @mask: Mask to specify which semaphore to acquire 1749 * 1750 * Acquires the SWFW semaphore thought the GSSR register for the specified 1751 * function (CSR, PHY0, PHY1, EEPROM, Flash) 1752 **/ 1753 int32_t ixgbe_acquire_swfw_sync(struct ixgbe_hw *hw, uint16_t mask) 1754 { 1755 uint32_t gssr; 1756 uint32_t swmask = mask; 1757 uint32_t fwmask = mask << 5; 1758 int32_t timeout = 200; 1759 1760 while (timeout) { 1761 if (ixgbe_get_eeprom_semaphore(hw)) 1762 return -IXGBE_ERR_SWFW_SYNC; 1763 1764 gssr = IXGBE_READ_REG(hw, IXGBE_GSSR); 1765 if (!(gssr & (fwmask | swmask))) 1766 break; 1767 1768 /* 1769 * Firmware currently using resource (fwmask) or other software 1770 * thread currently using resource (swmask) 1771 */ 1772 ixgbe_release_eeprom_semaphore(hw); 1773 msec_delay(5); 1774 timeout--; 1775 } 1776 1777 if (!timeout) { 1778 DEBUGOUT("Driver can't access resource, GSSR timeout.\n"); 1779 return -IXGBE_ERR_SWFW_SYNC; 1780 } 1781 1782 gssr |= swmask; 1783 IXGBE_WRITE_REG(hw, IXGBE_GSSR, gssr); 1784 1785 ixgbe_release_eeprom_semaphore(hw); 1786 return IXGBE_SUCCESS; 1787 } 1788 1789 /** 1790 * ixgbe_release_swfw_sync - Release SWFW semaphore 1791 * @hw: pointer to hardware structure 1792 * @mask: Mask to specify which semaphore to release 1793 * 1794 * Releases the SWFW semaphore thought the GSSR register for the specified 1795 * function (CSR, PHY0, PHY1, EEPROM, Flash) 1796 **/ 1797 void ixgbe_release_swfw_sync(struct ixgbe_hw *hw, uint16_t mask) 1798 { 1799 uint32_t gssr; 1800 uint32_t swmask = mask; 1801 1802 ixgbe_get_eeprom_semaphore(hw); 1803 1804 gssr = IXGBE_READ_REG(hw, IXGBE_GSSR); 1805 gssr &= ~swmask; 1806 IXGBE_WRITE_REG(hw, IXGBE_GSSR, gssr); 1807 1808 ixgbe_release_eeprom_semaphore(hw); 1809 } 1810 1811 /** 1812 * ixgbe_read_analog_reg8_generic - Reads 8 bit Atlas analog register 1813 * @hw: pointer to hardware structure 1814 * @reg: analog register to read 1815 * @val: read value 1816 * 1817 * Performs read operation to Atlas analog register specified. 1818 **/ 1819 int32_t ixgbe_read_analog_reg8_generic(struct ixgbe_hw *hw, uint32_t reg, uint8_t *val) 1820 { 1821 uint32_t atlas_ctl; 1822 1823 IXGBE_WRITE_REG(hw, IXGBE_ATLASCTL, IXGBE_ATLASCTL_WRITE_CMD | (reg << 8)); 1824 IXGBE_WRITE_FLUSH(hw); 1825 usec_delay(10); 1826 atlas_ctl = IXGBE_READ_REG(hw, IXGBE_ATLASCTL); 1827 *val = (uint8_t)atlas_ctl; 1828 1829 return IXGBE_SUCCESS; 1830 } 1831 1832 /** 1833 * ixgbe_write_analog_reg8_generic - Writes 8 bit Atlas analog register 1834 * @hw: pointer to hardware structure 1835 * @reg: atlas register to write 1836 * @val: value to write 1837 * 1838 * Performs write operation to Atlas analog register specified. 1839 **/ 1840 int32_t ixgbe_write_analog_reg8_generic(struct ixgbe_hw *hw, uint32_t reg, uint8_t val) 1841 { 1842 uint32_t atlas_ctl; 1843 1844 atlas_ctl = (reg << 8) | val; 1845 IXGBE_WRITE_REG(hw, IXGBE_ATLASCTL, atlas_ctl); 1846 IXGBE_WRITE_FLUSH(hw); 1847 usec_delay(10); 1848 1849 return IXGBE_SUCCESS; 1850 } 1851 1852