1 /******************************************************************************* 2 3 Copyright (c) 2001-2005, Intel Corporation 4 All rights reserved. 5 6 Redistribution and use in source and binary forms, with or without 7 modification, are permitted provided that the following conditions are met: 8 9 1. Redistributions of source code must retain the above copyright notice, 10 this list of conditions and the following disclaimer. 11 12 2. Redistributions in binary form must reproduce the above copyright 13 notice, this list of conditions and the following disclaimer in the 14 documentation and/or other materials provided with the distribution. 15 16 3. Neither the name of the Intel Corporation nor the names of its 17 contributors may be used to endorse or promote products derived from 18 this software without specific prior written permission. 19 20 THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS" 21 AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE 22 IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE 23 ARE DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT OWNER OR CONTRIBUTORS BE 24 LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR 25 CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF 26 SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS 27 INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN 28 CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) 29 ARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE 30 POSSIBILITY OF SUCH DAMAGE. 31 32 *******************************************************************************/ 33 34 /* $OpenBSD: ixgb_hw.c,v 1.4 2013/08/07 01:06:39 bluhm Exp $ */ 35 36 /* ixgb_hw.c 37 * Shared functions for accessing and configuring the adapter 38 */ 39 40 #include <sys/param.h> 41 #include <sys/systm.h> 42 #include <sys/sockio.h> 43 #include <sys/mbuf.h> 44 #include <sys/malloc.h> 45 #include <sys/kernel.h> 46 #include <sys/device.h> 47 #include <sys/socket.h> 48 49 #include <net/if.h> 50 #include <net/if_dl.h> 51 #include <net/if_media.h> 52 53 #ifdef INET 54 #include <netinet/in.h> 55 #include <netinet/in_systm.h> 56 #include <netinet/ip.h> 57 #include <netinet/if_ether.h> 58 #endif 59 60 #include <uvm/uvm_extern.h> 61 62 #include <dev/pci/pcireg.h> 63 #include <dev/pci/pcivar.h> 64 #include <dev/pci/pcidevs.h> 65 66 #include <dev/pci/ixgb_hw.h> 67 #include <dev/pci/ixgb_ids.h> 68 69 /* Local function prototypes */ 70 71 static uint32_t ixgb_hash_mc_addr(struct ixgb_hw *hw, uint8_t *mc_addr); 72 73 static void ixgb_mta_set(struct ixgb_hw *hw, uint32_t hash_value); 74 75 static void ixgb_get_bus_info(struct ixgb_hw *hw); 76 77 static boolean_t ixgb_link_reset(struct ixgb_hw *hw); 78 79 static void ixgb_optics_reset(struct ixgb_hw *hw); 80 81 static void ixgb_optics_reset_bcm(struct ixgb_hw *hw); 82 83 static ixgb_phy_type ixgb_identify_phy(struct ixgb_hw *hw); 84 85 uint32_t ixgb_mac_reset(struct ixgb_hw *hw); 86 87 uint32_t 88 ixgb_mac_reset(struct ixgb_hw *hw) 89 { 90 uint32_t ctrl_reg; 91 92 ctrl_reg = IXGB_CTRL0_RST | 93 IXGB_CTRL0_SDP3_DIR | /* All pins are Output=1 */ 94 IXGB_CTRL0_SDP2_DIR | 95 IXGB_CTRL0_SDP1_DIR | 96 IXGB_CTRL0_SDP0_DIR | 97 IXGB_CTRL0_SDP3 | /* Initial value 1101 */ 98 IXGB_CTRL0_SDP2 | 99 IXGB_CTRL0_SDP0; 100 101 #ifdef HP_ZX1 102 /* Workaround for 82597EX reset errata */ 103 IXGB_WRITE_REG_IO(hw, CTRL0, ctrl_reg); 104 #else 105 IXGB_WRITE_REG(hw, CTRL0, ctrl_reg); 106 #endif 107 108 /* Delay a few ms just to allow the reset to complete */ 109 msec_delay(IXGB_DELAY_AFTER_RESET); 110 ctrl_reg = IXGB_READ_REG(hw, CTRL0); 111 #ifdef DBG 112 /* Make sure the self-clearing global reset bit did self clear */ 113 ASSERT(!(ctrl_reg & IXGB_CTRL0_RST)); 114 #endif 115 116 if (hw->subsystem_vendor_id == SUN_SUBVENDOR_ID) { 117 ctrl_reg = /* Enable interrupt from XFP and SerDes */ 118 IXGB_CTRL1_GPI0_EN | 119 IXGB_CTRL1_SDP6_DIR | 120 IXGB_CTRL1_SDP7_DIR | 121 IXGB_CTRL1_SDP6 | 122 IXGB_CTRL1_SDP7; 123 IXGB_WRITE_REG(hw, CTRL1, ctrl_reg); 124 ixgb_optics_reset_bcm(hw); 125 } 126 127 if (hw->phy_type == ixgb_phy_type_txn17401) 128 ixgb_optics_reset(hw); 129 130 return ctrl_reg; 131 } 132 133 /****************************************************************************** 134 * Reset the transmit and receive units; mask and clear all interrupts. 135 * 136 * hw - Struct containing variables accessed by shared code 137 *****************************************************************************/ 138 boolean_t 139 ixgb_adapter_stop(struct ixgb_hw *hw) 140 { 141 uint32_t ctrl_reg; 142 uint32_t icr_reg; 143 144 DEBUGFUNC("ixgb_adapter_stop"); 145 146 /* If we are stopped or resetting exit gracefully and wait to be 147 * started again before accessing the hardware. */ 148 if(hw->adapter_stopped) { 149 DEBUGOUT("Exiting because the adapter is already stopped!!!\n"); 150 return FALSE; 151 } 152 153 /* Set the Adapter Stopped flag so other driver functions stop touching 154 * the Hardware. */ 155 hw->adapter_stopped = TRUE; 156 157 /* Clear interrupt mask to stop board from generating interrupts */ 158 DEBUGOUT("Masking off all interrupts\n"); 159 IXGB_WRITE_REG(hw, IMC, 0xFFFFFFFF); 160 161 /* Disable the Transmit and Receive units. Then delay to allow any 162 * pending transactions to complete before we hit the MAC with the 163 * global reset. */ 164 IXGB_WRITE_REG(hw, RCTL, IXGB_READ_REG(hw, RCTL) & ~IXGB_RCTL_RXEN); 165 IXGB_WRITE_REG(hw, TCTL, IXGB_READ_REG(hw, TCTL) & ~IXGB_TCTL_TXEN); 166 msec_delay(IXGB_DELAY_BEFORE_RESET); 167 168 /* Issue a global reset to the MAC. This will reset the chip's 169 * transmit, receive, DMA, and link units. It will not effect the 170 * current PCI configuration. The global reset bit is self- clearing, 171 * and should clear within a microsecond. */ 172 DEBUGOUT("Issuing a global reset to MAC\n"); 173 174 ctrl_reg = ixgb_mac_reset(hw); 175 176 /* Clear interrupt mask to stop board from generating interrupts */ 177 DEBUGOUT("Masking off all interrupts\n"); 178 IXGB_WRITE_REG(hw, IMC, 0xffffffff); 179 180 /* Clear any pending interrupt events. */ 181 icr_reg = IXGB_READ_REG(hw, ICR); 182 183 return (ctrl_reg & IXGB_CTRL0_RST); 184 } 185 186 /****************************************************************************** 187 * Identifies the vendor of the optics module on the adapter. The SR adapters 188 * support two different types of XPAK optics, so it is necessary to determine 189 * which optics are present before applying any optics-specific workarounds. 190 * 191 * hw - Struct containing variables accessed by shared code. 192 * 193 * Returns: the vendor of the XPAK optics module. 194 *****************************************************************************/ 195 static ixgb_xpak_vendor 196 ixgb_identify_xpak_vendor(struct ixgb_hw *hw) 197 { 198 uint32_t i; 199 uint16_t vendor_name[5]; 200 ixgb_xpak_vendor xpak_vendor; 201 202 DEBUGFUNC("ixgb_identify_xpak_vendor"); 203 204 /* Read the first few bytes of the vendor string from the XPAK NVR 205 * registers. These are standard XENPAK/XPAK registers, so all XPAK 206 * devices should implement them. */ 207 for(i = 0; i < 5; i++) { 208 vendor_name[i] = 209 ixgb_read_phy_reg(hw, MDIO_PMA_PMD_XPAK_VENDOR_NAME + i, 210 IXGB_PHY_ADDRESS, MDIO_PMA_PMD_DID); 211 } 212 213 /* Determine the actual vendor */ 214 if (vendor_name[0] == 'I' && 215 vendor_name[1] == 'N' && 216 vendor_name[2] == 'T' && 217 vendor_name[3] == 'E' && 218 vendor_name[4] == 'L') { 219 xpak_vendor = ixgb_xpak_vendor_intel; 220 } 221 else { 222 xpak_vendor = ixgb_xpak_vendor_infineon; 223 } 224 return (xpak_vendor); 225 } 226 227 /****************************************************************************** 228 * Determine the physical layer module on the adapter. 229 * 230 * hw - Struct containing variables accessed by shared code. The device_id 231 * field must be (correctly) populated before calling this routine. 232 * 233 * Returns: the phy type of the adapter. 234 *****************************************************************************/ 235 static ixgb_phy_type 236 ixgb_identify_phy(struct ixgb_hw *hw) 237 { 238 ixgb_phy_type phy_type; 239 ixgb_xpak_vendor xpak_vendor; 240 241 DEBUGFUNC("ixgb_identify_phy"); 242 243 /* Infer the transceiver/phy type from the device id */ 244 switch(hw->device_id) { 245 case IXGB_DEVICE_ID_82597EX: 246 DEBUGOUT("Identified TXN17401 optics\n"); 247 phy_type = ixgb_phy_type_txn17401; 248 break; 249 250 case IXGB_DEVICE_ID_82597EX_SR: 251 /* The SR adapters carry two different types of XPAK optics 252 * modules; read the vendor identifier to determine the exact 253 * type of optics. */ 254 xpak_vendor = ixgb_identify_xpak_vendor(hw); 255 if(xpak_vendor == ixgb_xpak_vendor_intel) { 256 DEBUGOUT("Identified TXN17201 optics\n"); 257 phy_type = ixgb_phy_type_txn17201; 258 } else { 259 DEBUGOUT("Identified G6005 optics\n"); 260 phy_type = ixgb_phy_type_g6005; 261 } 262 break; 263 264 case IXGB_DEVICE_ID_82597EX_LR: 265 DEBUGOUT("Identified G6104 optics\n"); 266 phy_type = ixgb_phy_type_g6104; 267 break; 268 269 case IXGB_DEVICE_ID_82597EX_CX4: 270 DEBUGOUT("Identified CX4\n"); 271 xpak_vendor = ixgb_identify_xpak_vendor(hw); 272 if(xpak_vendor == ixgb_xpak_vendor_intel) { 273 DEBUGOUT("Identified TXN17201 optics\n"); 274 phy_type = ixgb_phy_type_txn17201; 275 } else { 276 DEBUGOUT("Identified G6005 optics\n"); 277 phy_type = ixgb_phy_type_g6005; 278 } 279 break; 280 281 default: 282 DEBUGOUT("Unknown physical layer module\n"); 283 phy_type = ixgb_phy_type_unknown; 284 break; 285 } 286 287 /* update phy type for sun specific board */ 288 if (hw->subsystem_vendor_id == SUN_SUBVENDOR_ID) 289 phy_type = ixgb_phy_type_bcm; 290 291 return (phy_type); 292 } 293 294 /****************************************************************************** 295 * Performs basic configuration of the adapter. 296 * 297 * hw - Struct containing variables accessed by shared code 298 * 299 * Resets the controller. 300 * Reads and validates the EEPROM. 301 * Initializes the receive address registers. 302 * Initializes the multicast table. 303 * Clears all on-chip counters. 304 * Calls routine to setup flow control settings. 305 * Leaves the transmit and receive units disabled and uninitialized. 306 * 307 * Returns: 308 * TRUE if successful, 309 * FALSE if unrecoverable problems were encountered. 310 *****************************************************************************/ 311 boolean_t 312 ixgb_init_hw(struct ixgb_hw *hw) 313 { 314 uint32_t i; 315 uint32_t ctrl_reg; 316 boolean_t status; 317 318 DEBUGFUNC("ixgb_init_hw"); 319 320 /* Issue a global reset to the MAC. This will reset the chip's 321 * transmit, receive, DMA, and link units. It will not effect the 322 * current PCI configuration. The global reset bit is self- clearing, 323 * and should clear within a microsecond. */ 324 DEBUGOUT("Issuing a global reset to MAC\n"); 325 326 ctrl_reg = ixgb_mac_reset(hw); 327 328 DEBUGOUT("Issuing an EE reset to MAC\n"); 329 #ifdef HP_ZX1 330 /* Workaround for 82597EX reset errata */ 331 IXGB_WRITE_REG_IO(hw, CTRL1, IXGB_CTRL1_EE_RST); 332 #else 333 IXGB_WRITE_REG(hw, CTRL1, IXGB_CTRL1_EE_RST); 334 #endif 335 336 /* Delay a few ms just to allow the reset to complete */ 337 msec_delay(IXGB_DELAY_AFTER_EE_RESET); 338 339 if(ixgb_get_eeprom_data(hw) == FALSE) { 340 return (FALSE); 341 } 342 343 /* Use the device id to determine the type of phy/transceiver. */ 344 hw->device_id = ixgb_get_ee_device_id(hw); 345 hw->phy_type = ixgb_identify_phy(hw); 346 347 /* Setup the receive addresses. Receive Address Registers (RARs 0 - 348 * 15). */ 349 ixgb_init_rx_addrs(hw); 350 351 /* 352 * Check that a valid MAC address has been set. 353 * If it is not valid, we fail hardware init. 354 */ 355 if(!mac_addr_valid(hw->curr_mac_addr)) { 356 DEBUGOUT("MAC address invalid after ixgb_init_rx_addrs\n"); 357 return (FALSE); 358 } 359 360 /* tell the routines in this file they can access hardware again */ 361 hw->adapter_stopped = FALSE; 362 363 /* Fill in the bus_info structure */ 364 ixgb_get_bus_info(hw); 365 366 /* Zero out the Multicast HASH table */ 367 DEBUGOUT("Zeroing the MTA\n"); 368 for(i = 0; i < IXGB_MC_TBL_SIZE; i++) 369 IXGB_WRITE_REG_ARRAY(hw, MTA, i, 0); 370 371 /* Zero out the VLAN Filter Table Array */ 372 ixgb_clear_vfta(hw); 373 374 /* Zero all of the hardware counters */ 375 ixgb_clear_hw_cntrs(hw); 376 377 /* Call a subroutine to setup flow control. */ 378 status = ixgb_setup_fc(hw); 379 380 /* 82597EX errata: Call check-for-link in case lane deskew is locked */ 381 ixgb_check_for_link(hw); 382 383 return (status); 384 } 385 386 /****************************************************************************** 387 * Initializes receive address filters. 388 * 389 * hw - Struct containing variables accessed by shared code 390 * 391 * Places the MAC address in receive address register 0 and clears the rest 392 * of the receive addresss registers. Clears the multicast table. Assumes 393 * the receiver is in reset when the routine is called. 394 *****************************************************************************/ 395 void 396 ixgb_init_rx_addrs(struct ixgb_hw *hw) 397 { 398 uint32_t i; 399 400 DEBUGFUNC("ixgb_init_rx_addrs"); 401 402 /* 403 * If the current mac address is valid, assume it is a software override 404 * to the permanent address. 405 * Otherwise, use the permanent address from the eeprom. 406 */ 407 if(!mac_addr_valid(hw->curr_mac_addr)) { 408 409 /* Get the MAC address from the eeprom for later reference */ 410 ixgb_get_ee_mac_addr(hw, hw->curr_mac_addr); 411 412 DEBUGOUT3(" Keeping Permanent MAC Addr =%.2X %.2X %.2X ", 413 hw->curr_mac_addr[0], hw->curr_mac_addr[1], 414 hw->curr_mac_addr[2]); 415 DEBUGOUT3("%.2X %.2X %.2X\n", hw->curr_mac_addr[3], 416 hw->curr_mac_addr[4], hw->curr_mac_addr[5]); 417 } else { 418 419 /* Setup the receive address. */ 420 DEBUGOUT("Overriding MAC Address in RAR[0]\n"); 421 DEBUGOUT3(" New MAC Addr =%.2X %.2X %.2X ", 422 hw->curr_mac_addr[0], hw->curr_mac_addr[1], 423 hw->curr_mac_addr[2]); 424 DEBUGOUT3("%.2X %.2X %.2X\n", hw->curr_mac_addr[3], 425 hw->curr_mac_addr[4], hw->curr_mac_addr[5]); 426 427 ixgb_rar_set(hw, hw->curr_mac_addr, 0); 428 } 429 430 /* Zero out the other 15 receive addresses. */ 431 DEBUGOUT("Clearing RAR[1-15]\n"); 432 for(i = 1; i < IXGB_RAR_ENTRIES; i++) { 433 IXGB_WRITE_REG_ARRAY(hw, RA, (i << 1), 0); 434 IXGB_WRITE_REG_ARRAY(hw, RA, ((i << 1) + 1), 0); 435 } 436 437 return; 438 } 439 440 /****************************************************************************** 441 * Updates the MAC's list of multicast addresses. 442 * 443 * hw - Struct containing variables accessed by shared code 444 * mc_addr_list - the list of new multicast addresses 445 * mc_addr_count - number of addresses 446 * pad - number of bytes between addresses in the list 447 * 448 * The given list replaces any existing list. Clears the last 15 receive 449 * address registers and the multicast table. Uses receive address registers 450 * for the first 15 multicast addresses, and hashes the rest into the 451 * multicast table. 452 *****************************************************************************/ 453 void 454 ixgb_mc_addr_list_update(struct ixgb_hw *hw, uint8_t *mc_addr_list, 455 uint32_t mc_addr_count, uint32_t pad) 456 { 457 uint32_t hash_value; 458 uint32_t i; 459 uint32_t rar_used_count = 1; /* RAR[0] is used for our MAC address */ 460 461 DEBUGFUNC("ixgb_mc_addr_list_update"); 462 463 /* Set the new number of MC addresses that we are being requested to 464 * use. */ 465 hw->num_mc_addrs = mc_addr_count; 466 467 /* Clear RAR[1-15] */ 468 DEBUGOUT(" Clearing RAR[1-15]\n"); 469 for(i = rar_used_count; i < IXGB_RAR_ENTRIES; i++) { 470 IXGB_WRITE_REG_ARRAY(hw, RA, (i << 1), 0); 471 IXGB_WRITE_REG_ARRAY(hw, RA, ((i << 1) + 1), 0); 472 } 473 474 /* Clear the MTA */ 475 DEBUGOUT(" Clearing MTA\n"); 476 for(i = 0; i < IXGB_MC_TBL_SIZE; i++) { 477 IXGB_WRITE_REG_ARRAY(hw, MTA, i, 0); 478 } 479 480 /* Add the new addresses */ 481 for(i = 0; i < mc_addr_count; i++) { 482 DEBUGOUT(" Adding the multicast addresses:\n"); 483 DEBUGOUT7(" MC Addr #%d =%.2X %.2X %.2X %.2X %.2X %.2X\n", i, 484 mc_addr_list[i * (IXGB_ETH_LENGTH_OF_ADDRESS + pad)], 485 mc_addr_list[i * (IXGB_ETH_LENGTH_OF_ADDRESS + pad) + 1], 486 mc_addr_list[i * (IXGB_ETH_LENGTH_OF_ADDRESS + pad) + 2], 487 mc_addr_list[i * (IXGB_ETH_LENGTH_OF_ADDRESS + pad) + 3], 488 mc_addr_list[i * (IXGB_ETH_LENGTH_OF_ADDRESS + pad) + 4], 489 mc_addr_list[i * (IXGB_ETH_LENGTH_OF_ADDRESS + pad) + 5]); 490 491 /* Place this multicast address in the RAR if there is room, * 492 * else put it in the MTA */ 493 if(rar_used_count < IXGB_RAR_ENTRIES) { 494 ixgb_rar_set(hw, 495 mc_addr_list + 496 (i * (IXGB_ETH_LENGTH_OF_ADDRESS + pad)), 497 rar_used_count); 498 DEBUGOUT1("Added a multicast address to RAR[%d]\n", i); 499 rar_used_count++; 500 } else { 501 hash_value = 502 ixgb_hash_mc_addr(hw, 503 mc_addr_list + 504 (i * 505 (IXGB_ETH_LENGTH_OF_ADDRESS + 506 pad))); 507 508 DEBUGOUT1(" Hash value = 0x%03X\n", hash_value); 509 510 ixgb_mta_set(hw, hash_value); 511 } 512 } 513 514 DEBUGOUT("MC Update Complete\n"); 515 return; 516 } 517 518 /****************************************************************************** 519 * Hashes an address to determine its location in the multicast table 520 * 521 * hw - Struct containing variables accessed by shared code 522 * mc_addr - the multicast address to hash 523 * 524 * Returns: 525 * The hash value 526 *****************************************************************************/ 527 static uint32_t 528 ixgb_hash_mc_addr(struct ixgb_hw *hw, uint8_t *mc_addr) 529 { 530 uint32_t hash_value = 0; 531 532 DEBUGFUNC("ixgb_hash_mc_addr"); 533 534 /* The portion of the address that is used for the hash table is 535 * determined by the mc_filter_type setting. */ 536 switch(hw->mc_filter_type) { 537 /* [0] [1] [2] [3] [4] [5] 01 AA 00 12 34 56 LSB MSB - 538 * According to H/W docs */ 539 case 0: 540 /* [47:36] i.e. 0x563 for above example address */ 541 hash_value = 542 ((mc_addr[4] >> 4) | (((uint16_t)mc_addr[5]) << 4)); 543 break; 544 case 1: /* [46:35] i.e. 0xAC6 for above 545 * example address */ 546 hash_value = 547 ((mc_addr[4] >> 3) | (((uint16_t)mc_addr[5]) << 5)); 548 break; 549 case 2: /* [45:34] i.e. 0x5D8 for above 550 * example address */ 551 hash_value = 552 ((mc_addr[4] >> 2) | (((uint16_t)mc_addr[5]) << 6)); 553 break; 554 case 3: /* [43:32] i.e. 0x634 for above 555 * example address */ 556 hash_value = ((mc_addr[4]) | (((uint16_t)mc_addr[5]) << 8)); 557 break; 558 default: 559 /* Invalid mc_filter_type, what should we do? */ 560 DEBUGOUT("MC filter type param set incorrectly\n"); 561 ASSERT(0); 562 break; 563 } 564 565 hash_value &= 0xFFF; 566 return (hash_value); 567 } 568 569 /****************************************************************************** 570 * Sets the bit in the multicast table corresponding to the hash value. 571 * 572 * hw - Struct containing variables accessed by shared code 573 * hash_value - Multicast address hash value 574 *****************************************************************************/ 575 static void 576 ixgb_mta_set(struct ixgb_hw *hw, uint32_t hash_value) 577 { 578 uint32_t hash_bit, hash_reg; 579 uint32_t mta_reg; 580 581 /* The MTA is a register array of 128 32-bit registers. It is treated 582 * like an array of 4096 bits. We want to set bit 583 * BitArray[hash_value]. So we figure out what register the bit is in, 584 * read it, OR in the new bit, then write back the new value. The 585 * register is determined by the upper 7 bits of the hash value and the 586 * bit within that register are determined by the lower 5 bits of the 587 * value. */ 588 hash_reg = (hash_value >> 5) & 0x7F; 589 hash_bit = hash_value & 0x1F; 590 mta_reg = IXGB_READ_REG_ARRAY(hw, MTA, hash_reg); 591 mta_reg |= (1 << hash_bit); 592 IXGB_WRITE_REG_ARRAY(hw, MTA, hash_reg, mta_reg); 593 return; 594 } 595 596 /****************************************************************************** 597 * Puts an ethernet address into a receive address register. 598 * 599 * hw - Struct containing variables accessed by shared code 600 * addr - Address to put into receive address register 601 * index - Receive address register to write 602 *****************************************************************************/ 603 void 604 ixgb_rar_set(struct ixgb_hw *hw, uint8_t *addr, uint32_t index) 605 { 606 uint32_t rar_low, rar_high; 607 608 DEBUGFUNC("ixgb_rar_set"); 609 610 /* HW expects these in little endian so we reverse the byte order from 611 * network order (big endian) to little endian */ 612 rar_low = ((uint32_t)addr[0] | 613 ((uint32_t)addr[1] << 8) | 614 ((uint32_t)addr[2] << 16) | 615 ((uint32_t)addr[3] << 24)); 616 617 rar_high = ((uint32_t)addr[4] | 618 ((uint32_t)addr[5] << 8) | 619 IXGB_RAH_AV); 620 621 IXGB_WRITE_REG_ARRAY(hw, RA, (index << 1), rar_low); 622 IXGB_WRITE_REG_ARRAY(hw, RA, ((index << 1) + 1), rar_high); 623 return; 624 } 625 626 /****************************************************************************** 627 * Writes a value to the specified offset in the VLAN filter table. 628 * 629 * hw - Struct containing variables accessed by shared code 630 * offset - Offset in VLAN filer table to write 631 * value - Value to write into VLAN filter table 632 *****************************************************************************/ 633 void 634 ixgb_write_vfta(struct ixgb_hw *hw, uint32_t offset, uint32_t value) 635 { 636 IXGB_WRITE_REG_ARRAY(hw, VFTA, offset, value); 637 return; 638 } 639 640 /****************************************************************************** 641 * Clears the VLAN filer table 642 * 643 * hw - Struct containing variables accessed by shared code 644 *****************************************************************************/ 645 void 646 ixgb_clear_vfta(struct ixgb_hw *hw) 647 { 648 uint32_t offset; 649 650 for(offset = 0; offset < IXGB_VLAN_FILTER_TBL_SIZE; offset++) 651 IXGB_WRITE_REG_ARRAY(hw, VFTA, offset, 0); 652 return; 653 } 654 655 /****************************************************************************** 656 * Configures the flow control settings based on SW configuration. 657 * 658 * hw - Struct containing variables accessed by shared code 659 *****************************************************************************/ 660 661 boolean_t 662 ixgb_setup_fc(struct ixgb_hw *hw) 663 { 664 uint32_t ctrl_reg; 665 uint32_t pap_reg = 0; /* by default, assume no pause time */ 666 boolean_t status = TRUE; 667 668 DEBUGFUNC("ixgb_setup_fc"); 669 670 /* Get the current control reg 0 settings */ 671 ctrl_reg = IXGB_READ_REG(hw, CTRL0); 672 673 /* Clear the Receive Pause Enable and Transmit Pause Enable bits */ 674 ctrl_reg &= ~(IXGB_CTRL0_RPE | IXGB_CTRL0_TPE); 675 676 /* The possible values of the "flow_control" parameter are: 677 * 0: Flow control is completely disabled 678 * 1: Rx flow control is enabled (we can receive pause frames but not send 679 * pause frames). 680 * 2: Tx flow control is enabled (we can send pause frames but we do not 681 * support receiving pause frames) 682 * 3: Both Rx and TX flow control (symmetric) are enabled. 683 * other: Invalid. */ 684 switch(hw->fc.type) { 685 case ixgb_fc_none: /* 0 */ 686 /* Set CMDC bit to disable Rx Flow control */ 687 ctrl_reg |= (IXGB_CTRL0_CMDC); 688 break; 689 case ixgb_fc_rx_pause: /* 1 */ 690 /* RX Flow control is enabled, and TX Flow control is disabled. */ 691 ctrl_reg |= (IXGB_CTRL0_RPE); 692 break; 693 case ixgb_fc_tx_pause: /* 2 */ 694 /* TX Flow control is enabled, and RX Flow control is disabled, 695 * by a software over-ride. */ 696 ctrl_reg |= (IXGB_CTRL0_TPE); 697 pap_reg = hw->fc.pause_time; 698 break; 699 case ixgb_fc_full: /* 3 */ 700 /* Flow control (both RX and TX) is enabled by a software 701 * over-ride. */ 702 ctrl_reg |= (IXGB_CTRL0_RPE | IXGB_CTRL0_TPE); 703 pap_reg = hw->fc.pause_time; 704 break; 705 default: 706 /* We should never get here. The value should be 0-3. */ 707 DEBUGOUT("Flow control param set incorrectly\n"); 708 ASSERT(0); 709 break; 710 } 711 712 /* Write the new settings */ 713 IXGB_WRITE_REG(hw, CTRL0, ctrl_reg); 714 715 if(pap_reg != 0) { 716 IXGB_WRITE_REG(hw, PAP, pap_reg); 717 } 718 719 /* Set the flow control receive threshold registers. Normally, these 720 * registers will be set to a default threshold that may be adjusted 721 * later by the driver's runtime code. However, if the ability to 722 * transmit pause frames in not enabled, then these registers will be 723 * set to 0. */ 724 if(!(hw->fc.type & ixgb_fc_tx_pause)) { 725 IXGB_WRITE_REG(hw, FCRTL, 0); 726 IXGB_WRITE_REG(hw, FCRTH, 0); 727 } else { 728 /* We need to set up the Receive Threshold high and low water 729 * marks as well as (optionally) enabling the transmission of 730 * XON frames. */ 731 if(hw->fc.send_xon) { 732 IXGB_WRITE_REG(hw, FCRTL, 733 (hw->fc.low_water | IXGB_FCRTL_XONE)); 734 } else { 735 IXGB_WRITE_REG(hw, FCRTL, hw->fc.low_water); 736 } 737 IXGB_WRITE_REG(hw, FCRTH, hw->fc.high_water); 738 } 739 return (status); 740 } 741 742 /****************************************************************************** 743 * Reads a word from a device over the Management Data Interface (MDI) bus. 744 * This interface is used to manage Physical layer devices. 745 * 746 * hw - Struct containing variables accessed by hw code 747 * reg_address - Offset of device register being read. 748 * phy_address - Address of device on MDI. 749 * 750 * Returns: Data word (16 bits) from MDI device. 751 * 752 * The 82597EX has support for several MDI access methods. This routine 753 * uses the new protocol MDI Single Command and Address Operation. 754 * This requires that first an address cycle command is sent, followed by a 755 * read command. 756 *****************************************************************************/ 757 uint16_t 758 ixgb_read_phy_reg(struct ixgb_hw *hw, uint32_t reg_address, 759 uint32_t phy_address, uint32_t device_type) 760 { 761 uint32_t i; 762 uint32_t data; 763 uint32_t command = 0; 764 765 ASSERT(reg_address <= IXGB_MAX_PHY_REG_ADDRESS); 766 ASSERT(phy_address <= IXGB_MAX_PHY_ADDRESS); 767 ASSERT(device_type <= IXGB_MAX_PHY_DEV_TYPE); 768 769 /* Setup and write the address cycle command */ 770 command = ((reg_address << IXGB_MSCA_NP_ADDR_SHIFT) | 771 (device_type << IXGB_MSCA_DEV_TYPE_SHIFT) | 772 (phy_address << IXGB_MSCA_PHY_ADDR_SHIFT) | 773 (IXGB_MSCA_ADDR_CYCLE | IXGB_MSCA_MDI_COMMAND)); 774 775 IXGB_WRITE_REG(hw, MSCA, command); 776 777 /************************************************************** 778 ** Check every 10 usec to see if the address cycle completed 779 ** The COMMAND bit will clear when the operation is complete. 780 ** This may take as long as 64 usecs (we'll wait 100 usecs max) 781 ** from the CPU Write to the Ready bit assertion. 782 **************************************************************/ 783 784 for(i = 0; i < 10; i++) { 785 usec_delay(10); 786 787 command = IXGB_READ_REG(hw, MSCA); 788 789 if((command & IXGB_MSCA_MDI_COMMAND) == 0) 790 break; 791 } 792 793 ASSERT((command & IXGB_MSCA_MDI_COMMAND) == 0); 794 795 /* Address cycle complete, setup and write the read command */ 796 command = ((reg_address << IXGB_MSCA_NP_ADDR_SHIFT) | 797 (device_type << IXGB_MSCA_DEV_TYPE_SHIFT) | 798 (phy_address << IXGB_MSCA_PHY_ADDR_SHIFT) | 799 (IXGB_MSCA_READ | IXGB_MSCA_MDI_COMMAND)); 800 801 IXGB_WRITE_REG(hw, MSCA, command); 802 803 /************************************************************** 804 ** Check every 10 usec to see if the read command completed 805 ** The COMMAND bit will clear when the operation is complete. 806 ** The read may take as long as 64 usecs (we'll wait 100 usecs max) 807 ** from the CPU Write to the Ready bit assertion. 808 **************************************************************/ 809 810 for(i = 0; i < 10; i++) { 811 usec_delay(10); 812 813 command = IXGB_READ_REG(hw, MSCA); 814 815 if((command & IXGB_MSCA_MDI_COMMAND) == 0) 816 break; 817 } 818 819 ASSERT((command & IXGB_MSCA_MDI_COMMAND) == 0); 820 821 /* Operation is complete, get the data from the MDIO Read/Write Data 822 * register and return. */ 823 data = IXGB_READ_REG(hw, MSRWD); 824 data >>= IXGB_MSRWD_READ_DATA_SHIFT; 825 return ((uint16_t)data); 826 } 827 828 /****************************************************************************** 829 * Writes a word to a device over the Management Data Interface (MDI) bus. 830 * This interface is used to manage Physical layer devices. 831 * 832 * hw - Struct containing variables accessed by hw code 833 * reg_address - Offset of device register being read. 834 * phy_address - Address of device on MDI. 835 * device_type - Also known as the Device ID or DID. 836 * data - 16-bit value to be written 837 * 838 * Returns: void. 839 * 840 * The 82597EX has support for several MDI access methods. This routine 841 * uses the new protocol MDI Single Command and Address Operation. 842 * This requires that first an address cycle command is sent, followed by a 843 * write command. 844 *****************************************************************************/ 845 void 846 ixgb_write_phy_reg(struct ixgb_hw *hw, uint32_t reg_address, 847 uint32_t phy_address, uint32_t device_type, uint16_t data) 848 { 849 uint32_t i; 850 uint32_t command = 0; 851 852 ASSERT(reg_address <= IXGB_MAX_PHY_REG_ADDRESS); 853 ASSERT(phy_address <= IXGB_MAX_PHY_ADDRESS); 854 ASSERT(device_type <= IXGB_MAX_PHY_DEV_TYPE); 855 856 /* Put the data in the MDIO Read/Write Data register */ 857 IXGB_WRITE_REG(hw, MSRWD, (uint32_t)data); 858 859 /* Setup and write the address cycle command */ 860 command = ((reg_address << IXGB_MSCA_NP_ADDR_SHIFT) | 861 (device_type << IXGB_MSCA_DEV_TYPE_SHIFT) | 862 (phy_address << IXGB_MSCA_PHY_ADDR_SHIFT) | 863 (IXGB_MSCA_ADDR_CYCLE | IXGB_MSCA_MDI_COMMAND)); 864 865 IXGB_WRITE_REG(hw, MSCA, command); 866 867 /************************************************************** 868 ** Check every 10 usec to see if the address cycle completed 869 ** The COMMAND bit will clear when the operation is complete. 870 ** This may take as long as 64 usecs (we'll wait 100 usecs max) 871 ** from the CPU Write to the Ready bit assertion. 872 **************************************************************/ 873 874 for(i = 0; i < 10; i++) { 875 usec_delay(10); 876 877 command = IXGB_READ_REG(hw, MSCA); 878 879 if((command & IXGB_MSCA_MDI_COMMAND) == 0) 880 break; 881 } 882 883 ASSERT((command & IXGB_MSCA_MDI_COMMAND) == 0); 884 885 /* Address cycle complete, setup and write the write command */ 886 command = ((reg_address << IXGB_MSCA_NP_ADDR_SHIFT) | 887 (device_type << IXGB_MSCA_DEV_TYPE_SHIFT) | 888 (phy_address << IXGB_MSCA_PHY_ADDR_SHIFT) | 889 (IXGB_MSCA_WRITE | IXGB_MSCA_MDI_COMMAND)); 890 891 IXGB_WRITE_REG(hw, MSCA, command); 892 893 /************************************************************** 894 ** Check every 10 usec to see if the read command completed 895 ** The COMMAND bit will clear when the operation is complete. 896 ** The write may take as long as 64 usecs (we'll wait 100 usecs max) 897 ** from the CPU Write to the Ready bit assertion. 898 **************************************************************/ 899 900 for(i = 0; i < 10; i++) { 901 usec_delay(10); 902 903 command = IXGB_READ_REG(hw, MSCA); 904 905 if((command & IXGB_MSCA_MDI_COMMAND) == 0) 906 break; 907 } 908 909 ASSERT((command & IXGB_MSCA_MDI_COMMAND) == 0); 910 911 /* Operation is complete, return. */ 912 } 913 914 /****************************************************************************** 915 * Checks to see if the link status of the hardware has changed. 916 * 917 * hw - Struct containing variables accessed by hw code 918 * 919 * Called by any function that needs to check the link status of the adapter. 920 *****************************************************************************/ 921 void 922 ixgb_check_for_link(struct ixgb_hw *hw) 923 { 924 uint32_t status_reg; 925 uint32_t xpcss_reg; 926 927 DEBUGFUNC("ixgb_check_for_link"); 928 929 xpcss_reg = IXGB_READ_REG(hw, XPCSS); 930 status_reg = IXGB_READ_REG(hw, STATUS); 931 932 if((xpcss_reg & IXGB_XPCSS_ALIGN_STATUS) && 933 (status_reg & IXGB_STATUS_LU)) { 934 hw->link_up = TRUE; 935 } else if(!(xpcss_reg & IXGB_XPCSS_ALIGN_STATUS) && 936 (status_reg & IXGB_STATUS_LU)) { 937 DEBUGOUT("XPCSS Not Aligned while Status:LU is set.\n"); 938 hw->link_up = ixgb_link_reset(hw); 939 } else { 940 /* 941 * 82597EX errata. Since the lane deskew problem may prevent 942 * link, reset the link before reporting link down. 943 */ 944 hw->link_up = ixgb_link_reset(hw); 945 } 946 /* Anything else for 10 Gig?? */ 947 } 948 949 /****************************************************************************** 950 * Check for a bad link condition that may have occured. 951 * The indication is that the RFC / LFC registers may be incrementing 952 * continually. A full adapter reset is required to recover. 953 * 954 * hw - Struct containing variables accessed by hw code 955 * 956 * Called by any function that needs to check the link status of the adapter. 957 *****************************************************************************/ 958 boolean_t 959 ixgb_check_for_bad_link(struct ixgb_hw *hw) 960 { 961 uint32_t newLFC, newRFC; 962 boolean_t bad_link_returncode = FALSE; 963 964 if(hw->phy_type == ixgb_phy_type_txn17401) { 965 newLFC = IXGB_READ_REG(hw, LFC); 966 newRFC = IXGB_READ_REG(hw, RFC); 967 if((hw->lastLFC + 250 < newLFC) || (hw->lastRFC + 250 < newRFC)) { 968 DEBUGOUT("BAD LINK! too many LFC/RFC since last check\n"); 969 bad_link_returncode = TRUE; 970 } 971 hw->lastLFC = newLFC; 972 hw->lastRFC = newRFC; 973 } 974 975 return bad_link_returncode; 976 } 977 978 /****************************************************************************** 979 * Clears all hardware statistics counters. 980 * 981 * hw - Struct containing variables accessed by shared code 982 *****************************************************************************/ 983 void 984 ixgb_clear_hw_cntrs(struct ixgb_hw *hw) 985 { 986 volatile uint32_t temp_reg; 987 988 DEBUGFUNC("ixgb_clear_hw_cntrs"); 989 990 /* if we are stopped or resetting exit gracefully */ 991 if(hw->adapter_stopped) { 992 DEBUGOUT("Exiting because the adapter is stopped!!!\n"); 993 return; 994 } 995 996 temp_reg = IXGB_READ_REG(hw, TPRL); 997 temp_reg = IXGB_READ_REG(hw, TPRH); 998 temp_reg = IXGB_READ_REG(hw, GPRCL); 999 temp_reg = IXGB_READ_REG(hw, GPRCH); 1000 temp_reg = IXGB_READ_REG(hw, BPRCL); 1001 temp_reg = IXGB_READ_REG(hw, BPRCH); 1002 temp_reg = IXGB_READ_REG(hw, MPRCL); 1003 temp_reg = IXGB_READ_REG(hw, MPRCH); 1004 temp_reg = IXGB_READ_REG(hw, UPRCL); 1005 temp_reg = IXGB_READ_REG(hw, UPRCH); 1006 temp_reg = IXGB_READ_REG(hw, VPRCL); 1007 temp_reg = IXGB_READ_REG(hw, VPRCH); 1008 temp_reg = IXGB_READ_REG(hw, JPRCL); 1009 temp_reg = IXGB_READ_REG(hw, JPRCH); 1010 temp_reg = IXGB_READ_REG(hw, GORCL); 1011 temp_reg = IXGB_READ_REG(hw, GORCH); 1012 temp_reg = IXGB_READ_REG(hw, TORL); 1013 temp_reg = IXGB_READ_REG(hw, TORH); 1014 temp_reg = IXGB_READ_REG(hw, RNBC); 1015 temp_reg = IXGB_READ_REG(hw, RUC); 1016 temp_reg = IXGB_READ_REG(hw, ROC); 1017 temp_reg = IXGB_READ_REG(hw, RLEC); 1018 temp_reg = IXGB_READ_REG(hw, CRCERRS); 1019 temp_reg = IXGB_READ_REG(hw, ICBC); 1020 temp_reg = IXGB_READ_REG(hw, ECBC); 1021 temp_reg = IXGB_READ_REG(hw, MPC); 1022 temp_reg = IXGB_READ_REG(hw, TPTL); 1023 temp_reg = IXGB_READ_REG(hw, TPTH); 1024 temp_reg = IXGB_READ_REG(hw, GPTCL); 1025 temp_reg = IXGB_READ_REG(hw, GPTCH); 1026 temp_reg = IXGB_READ_REG(hw, BPTCL); 1027 temp_reg = IXGB_READ_REG(hw, BPTCH); 1028 temp_reg = IXGB_READ_REG(hw, MPTCL); 1029 temp_reg = IXGB_READ_REG(hw, MPTCH); 1030 temp_reg = IXGB_READ_REG(hw, UPTCL); 1031 temp_reg = IXGB_READ_REG(hw, UPTCH); 1032 temp_reg = IXGB_READ_REG(hw, VPTCL); 1033 temp_reg = IXGB_READ_REG(hw, VPTCH); 1034 temp_reg = IXGB_READ_REG(hw, JPTCL); 1035 temp_reg = IXGB_READ_REG(hw, JPTCH); 1036 temp_reg = IXGB_READ_REG(hw, GOTCL); 1037 temp_reg = IXGB_READ_REG(hw, GOTCH); 1038 temp_reg = IXGB_READ_REG(hw, TOTL); 1039 temp_reg = IXGB_READ_REG(hw, TOTH); 1040 temp_reg = IXGB_READ_REG(hw, DC); 1041 temp_reg = IXGB_READ_REG(hw, PLT64C); 1042 temp_reg = IXGB_READ_REG(hw, TSCTC); 1043 temp_reg = IXGB_READ_REG(hw, TSCTFC); 1044 temp_reg = IXGB_READ_REG(hw, IBIC); 1045 temp_reg = IXGB_READ_REG(hw, RFC); 1046 temp_reg = IXGB_READ_REG(hw, LFC); 1047 temp_reg = IXGB_READ_REG(hw, PFRC); 1048 temp_reg = IXGB_READ_REG(hw, PFTC); 1049 temp_reg = IXGB_READ_REG(hw, MCFRC); 1050 temp_reg = IXGB_READ_REG(hw, MCFTC); 1051 temp_reg = IXGB_READ_REG(hw, XONRXC); 1052 temp_reg = IXGB_READ_REG(hw, XONTXC); 1053 temp_reg = IXGB_READ_REG(hw, XOFFRXC); 1054 temp_reg = IXGB_READ_REG(hw, XOFFTXC); 1055 temp_reg = IXGB_READ_REG(hw, RJC); 1056 return; 1057 } 1058 1059 /****************************************************************************** 1060 * Turns on the software controllable LED 1061 * 1062 * hw - Struct containing variables accessed by shared code 1063 *****************************************************************************/ 1064 void 1065 ixgb_led_on(struct ixgb_hw *hw) 1066 { 1067 uint32_t ctrl0_reg = IXGB_READ_REG(hw, CTRL0); 1068 1069 /* To turn on the LED, clear software-definable pin 0 (SDP0). */ 1070 ctrl0_reg &= ~IXGB_CTRL0_SDP0; 1071 IXGB_WRITE_REG(hw, CTRL0, ctrl0_reg); 1072 return; 1073 } 1074 1075 /****************************************************************************** 1076 * Turns off the software controllable LED 1077 * 1078 * hw - Struct containing variables accessed by shared code 1079 *****************************************************************************/ 1080 void 1081 ixgb_led_off(struct ixgb_hw *hw) 1082 { 1083 uint32_t ctrl0_reg = IXGB_READ_REG(hw, CTRL0); 1084 1085 /* To turn off the LED, set software-definable pin 0 (SDP0). */ 1086 ctrl0_reg |= IXGB_CTRL0_SDP0; 1087 IXGB_WRITE_REG(hw, CTRL0, ctrl0_reg); 1088 return; 1089 } 1090 1091 /****************************************************************************** 1092 * Gets the current PCI bus type, speed, and width of the hardware 1093 * 1094 * hw - Struct containing variables accessed by shared code 1095 *****************************************************************************/ 1096 static void 1097 ixgb_get_bus_info(struct ixgb_hw *hw) 1098 { 1099 uint32_t status_reg; 1100 1101 status_reg = IXGB_READ_REG(hw, STATUS); 1102 1103 hw->bus.type = 1104 (status_reg & IXGB_STATUS_PCIX_MODE) ? ixgb_bus_type_pcix : 1105 ixgb_bus_type_pci; 1106 1107 if(hw->bus.type == ixgb_bus_type_pci) { 1108 hw->bus.speed = 1109 (status_reg & IXGB_STATUS_PCI_SPD) ? ixgb_bus_speed_66 : 1110 ixgb_bus_speed_33; 1111 } else { 1112 switch(status_reg & IXGB_STATUS_PCIX_SPD_MASK) { 1113 case IXGB_STATUS_PCIX_SPD_66: 1114 hw->bus.speed = ixgb_bus_speed_66; 1115 break; 1116 case IXGB_STATUS_PCIX_SPD_100: 1117 hw->bus.speed = ixgb_bus_speed_100; 1118 break; 1119 case IXGB_STATUS_PCIX_SPD_133: 1120 hw->bus.speed = ixgb_bus_speed_133; 1121 break; 1122 default: 1123 hw->bus.speed = ixgb_bus_speed_reserved; 1124 break; 1125 } 1126 } 1127 1128 hw->bus.width = 1129 (status_reg & IXGB_STATUS_BUS64) ? ixgb_bus_width_64 : 1130 ixgb_bus_width_32; 1131 1132 return; 1133 } 1134 1135 /****************************************************************************** 1136 * Tests a MAC address to ensure it is a valid Individual Address 1137 * 1138 * mac_addr - pointer to MAC address. 1139 * 1140 *****************************************************************************/ 1141 boolean_t 1142 mac_addr_valid(uint8_t *mac_addr) 1143 { 1144 boolean_t is_valid = TRUE; 1145 1146 DEBUGFUNC("mac_addr_valid"); 1147 1148 /* Make sure it is not a multicast address */ 1149 if(IS_MULTICAST(mac_addr)) { 1150 DEBUGOUT("MAC address is multicast\n"); 1151 is_valid = FALSE; 1152 } 1153 /* Not a broadcast address */ 1154 else if(IS_BROADCAST(mac_addr)) { 1155 DEBUGOUT("MAC address is broadcast\n"); 1156 is_valid = FALSE; 1157 } 1158 /* Reject the zero address */ 1159 else if (mac_addr[0] == 0 && 1160 mac_addr[1] == 0 && 1161 mac_addr[2] == 0 && 1162 mac_addr[3] == 0 && 1163 mac_addr[4] == 0 && 1164 mac_addr[5] == 0) { 1165 DEBUGOUT("MAC address is all zeros\n"); 1166 is_valid = FALSE; 1167 } 1168 return (is_valid); 1169 } 1170 1171 /****************************************************************************** 1172 * Resets the 10GbE link. Waits the settle time and returns the state of 1173 * the link. 1174 * 1175 * hw - Struct containing variables accessed by shared code 1176 *****************************************************************************/ 1177 boolean_t 1178 ixgb_link_reset(struct ixgb_hw *hw) 1179 { 1180 boolean_t link_status = FALSE; 1181 uint8_t wait_retries = MAX_RESET_ITERATIONS; 1182 uint8_t lrst_retries = MAX_RESET_ITERATIONS; 1183 1184 do { 1185 /* Reset the link */ 1186 IXGB_WRITE_REG(hw, CTRL0, 1187 IXGB_READ_REG(hw, CTRL0) | IXGB_CTRL0_LRST); 1188 1189 /* Wait for link-up and lane re-alignment */ 1190 do { 1191 usec_delay(IXGB_DELAY_USECS_AFTER_LINK_RESET); 1192 link_status = 1193 ((IXGB_READ_REG(hw, STATUS) & IXGB_STATUS_LU) && 1194 (IXGB_READ_REG(hw, XPCSS) & 1195 IXGB_XPCSS_ALIGN_STATUS)) ? TRUE : FALSE; 1196 } while(!link_status && --wait_retries); 1197 1198 } while(!link_status && --lrst_retries); 1199 1200 return link_status; 1201 } 1202 1203 /****************************************************************************** 1204 * Resets the 10GbE optics module. 1205 * 1206 * hw - Struct containing variables accessed by shared code 1207 *****************************************************************************/ 1208 void 1209 ixgb_optics_reset(struct ixgb_hw *hw) 1210 { 1211 if(hw->phy_type == ixgb_phy_type_txn17401) { 1212 uint16_t mdio_reg; 1213 1214 ixgb_write_phy_reg(hw, 1215 MDIO_PMA_PMD_CR1, 1216 IXGB_PHY_ADDRESS, 1217 MDIO_PMA_PMD_DID, 1218 MDIO_PMA_PMD_CR1_RESET); 1219 1220 mdio_reg = ixgb_read_phy_reg(hw, 1221 MDIO_PMA_PMD_CR1, 1222 IXGB_PHY_ADDRESS, 1223 MDIO_PMA_PMD_DID); 1224 } 1225 1226 return; 1227 } 1228 1229 /****************************************************************************** 1230 * Resets the 10GbE optics module for Sun variant NIC. 1231 * 1232 * hw - Struct containing variables accessed by shared code 1233 *****************************************************************************/ 1234 1235 #define IXGB_BCM8704_USER_PMD_TX_CTRL_REG 0xC803 1236 #define IXGB_BCM8704_USER_PMD_TX_CTRL_REG_VAL 0x0164 1237 #define IXGB_BCM8704_USER_CTRL_REG 0xC800 1238 #define IXGB_BCM8704_USER_CTRL_REG_VAL 0x7FBF 1239 #define IXGB_BCM8704_USER_DEV3_ADDR 0x0003 1240 #define IXGB_SUN_PHY_ADDRESS 0x0000 1241 #define IXGB_SUN_PHY_RESET_DELAY 305 1242 1243 static void 1244 ixgb_optics_reset_bcm(struct ixgb_hw *hw) 1245 { 1246 uint32_t ctrl = IXGB_READ_REG(hw, CTRL0); 1247 ctrl &= ~IXGB_CTRL0_SDP2; 1248 ctrl |= IXGB_CTRL0_SDP3; 1249 IXGB_WRITE_REG(hw, CTRL0, ctrl); 1250 1251 /* SerDes needs extra delay */ 1252 msec_delay(IXGB_SUN_PHY_RESET_DELAY); 1253 1254 /* Broadcom 7408L configuration */ 1255 /* Reference clock config */ 1256 ixgb_write_phy_reg(hw, 1257 IXGB_BCM8704_USER_PMD_TX_CTRL_REG, 1258 IXGB_SUN_PHY_ADDRESS, 1259 IXGB_BCM8704_USER_DEV3_ADDR, 1260 IXGB_BCM8704_USER_PMD_TX_CTRL_REG_VAL); 1261 /* we must read the registers twice */ 1262 ixgb_read_phy_reg(hw, 1263 IXGB_BCM8704_USER_PMD_TX_CTRL_REG, 1264 IXGB_SUN_PHY_ADDRESS, 1265 IXGB_BCM8704_USER_DEV3_ADDR); 1266 ixgb_read_phy_reg(hw, 1267 IXGB_BCM8704_USER_PMD_TX_CTRL_REG, 1268 IXGB_SUN_PHY_ADDRESS, 1269 IXGB_BCM8704_USER_DEV3_ADDR); 1270 1271 ixgb_write_phy_reg(hw, 1272 IXGB_BCM8704_USER_CTRL_REG, 1273 IXGB_SUN_PHY_ADDRESS, 1274 IXGB_BCM8704_USER_DEV3_ADDR, 1275 IXGB_BCM8704_USER_CTRL_REG_VAL); 1276 ixgb_read_phy_reg(hw, 1277 IXGB_BCM8704_USER_CTRL_REG, 1278 IXGB_SUN_PHY_ADDRESS, 1279 IXGB_BCM8704_USER_DEV3_ADDR); 1280 ixgb_read_phy_reg(hw, 1281 IXGB_BCM8704_USER_CTRL_REG, 1282 IXGB_SUN_PHY_ADDRESS, 1283 IXGB_BCM8704_USER_DEV3_ADDR); 1284 1285 /* SerDes needs extra delay */ 1286 msec_delay(IXGB_SUN_PHY_RESET_DELAY); 1287 1288 return; 1289 } 1290