1 /******************************************************************************* 2 3 Copyright (c) 2001-2005, Intel Corporation 4 All rights reserved. 5 6 Redistribution and use in source and binary forms, with or without 7 modification, are permitted provided that the following conditions are met: 8 9 1. Redistributions of source code must retain the above copyright notice, 10 this list of conditions and the following disclaimer. 11 12 2. Redistributions in binary form must reproduce the above copyright 13 notice, this list of conditions and the following disclaimer in the 14 documentation and/or other materials provided with the distribution. 15 16 3. Neither the name of the Intel Corporation nor the names of its 17 contributors may be used to endorse or promote products derived from 18 this software without specific prior written permission. 19 20 THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS" 21 AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE 22 IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE 23 ARE DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT OWNER OR CONTRIBUTORS BE 24 LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR 25 CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF 26 SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS 27 INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN 28 CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) 29 ARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE 30 POSSIBILITY OF SUCH DAMAGE. 31 32 *******************************************************************************/ 33 34 /* $OpenBSD: ixgb_hw.c,v 1.3 2008/02/19 18:47:18 brad Exp $ */ 35 36 /* ixgb_hw.c 37 * Shared functions for accessing and configuring the adapter 38 */ 39 40 #include <sys/param.h> 41 #include <sys/systm.h> 42 #include <sys/sockio.h> 43 #include <sys/mbuf.h> 44 #include <sys/malloc.h> 45 #include <sys/kernel.h> 46 #include <sys/device.h> 47 #include <sys/socket.h> 48 49 #include <net/if.h> 50 #include <net/if_dl.h> 51 #include <net/if_media.h> 52 53 #ifdef INET 54 #include <netinet/in.h> 55 #include <netinet/in_systm.h> 56 #include <netinet/in_var.h> 57 #include <netinet/ip.h> 58 #include <netinet/if_ether.h> 59 #endif 60 61 #include <uvm/uvm_extern.h> 62 63 #include <dev/pci/pcireg.h> 64 #include <dev/pci/pcivar.h> 65 #include <dev/pci/pcidevs.h> 66 67 #include <dev/pci/ixgb_hw.h> 68 #include <dev/pci/ixgb_ids.h> 69 70 /* Local function prototypes */ 71 72 static uint32_t ixgb_hash_mc_addr(struct ixgb_hw *hw, uint8_t *mc_addr); 73 74 static void ixgb_mta_set(struct ixgb_hw *hw, uint32_t hash_value); 75 76 static void ixgb_get_bus_info(struct ixgb_hw *hw); 77 78 static boolean_t ixgb_link_reset(struct ixgb_hw *hw); 79 80 static void ixgb_optics_reset(struct ixgb_hw *hw); 81 82 static void ixgb_optics_reset_bcm(struct ixgb_hw *hw); 83 84 static ixgb_phy_type ixgb_identify_phy(struct ixgb_hw *hw); 85 86 uint32_t ixgb_mac_reset(struct ixgb_hw *hw); 87 88 uint32_t 89 ixgb_mac_reset(struct ixgb_hw *hw) 90 { 91 uint32_t ctrl_reg; 92 93 ctrl_reg = IXGB_CTRL0_RST | 94 IXGB_CTRL0_SDP3_DIR | /* All pins are Output=1 */ 95 IXGB_CTRL0_SDP2_DIR | 96 IXGB_CTRL0_SDP1_DIR | 97 IXGB_CTRL0_SDP0_DIR | 98 IXGB_CTRL0_SDP3 | /* Initial value 1101 */ 99 IXGB_CTRL0_SDP2 | 100 IXGB_CTRL0_SDP0; 101 102 #ifdef HP_ZX1 103 /* Workaround for 82597EX reset errata */ 104 IXGB_WRITE_REG_IO(hw, CTRL0, ctrl_reg); 105 #else 106 IXGB_WRITE_REG(hw, CTRL0, ctrl_reg); 107 #endif 108 109 /* Delay a few ms just to allow the reset to complete */ 110 msec_delay(IXGB_DELAY_AFTER_RESET); 111 ctrl_reg = IXGB_READ_REG(hw, CTRL0); 112 #ifdef DBG 113 /* Make sure the self-clearing global reset bit did self clear */ 114 ASSERT(!(ctrl_reg & IXGB_CTRL0_RST)); 115 #endif 116 117 if (hw->subsystem_vendor_id == SUN_SUBVENDOR_ID) { 118 ctrl_reg = /* Enable interrupt from XFP and SerDes */ 119 IXGB_CTRL1_GPI0_EN | 120 IXGB_CTRL1_SDP6_DIR | 121 IXGB_CTRL1_SDP7_DIR | 122 IXGB_CTRL1_SDP6 | 123 IXGB_CTRL1_SDP7; 124 IXGB_WRITE_REG(hw, CTRL1, ctrl_reg); 125 ixgb_optics_reset_bcm(hw); 126 } 127 128 if (hw->phy_type == ixgb_phy_type_txn17401) 129 ixgb_optics_reset(hw); 130 131 return ctrl_reg; 132 } 133 134 /****************************************************************************** 135 * Reset the transmit and receive units; mask and clear all interrupts. 136 * 137 * hw - Struct containing variables accessed by shared code 138 *****************************************************************************/ 139 boolean_t 140 ixgb_adapter_stop(struct ixgb_hw *hw) 141 { 142 uint32_t ctrl_reg; 143 uint32_t icr_reg; 144 145 DEBUGFUNC("ixgb_adapter_stop"); 146 147 /* If we are stopped or resetting exit gracefully and wait to be 148 * started again before accessing the hardware. */ 149 if(hw->adapter_stopped) { 150 DEBUGOUT("Exiting because the adapter is already stopped!!!\n"); 151 return FALSE; 152 } 153 154 /* Set the Adapter Stopped flag so other driver functions stop touching 155 * the Hardware. */ 156 hw->adapter_stopped = TRUE; 157 158 /* Clear interrupt mask to stop board from generating interrupts */ 159 DEBUGOUT("Masking off all interrupts\n"); 160 IXGB_WRITE_REG(hw, IMC, 0xFFFFFFFF); 161 162 /* Disable the Transmit and Receive units. Then delay to allow any 163 * pending transactions to complete before we hit the MAC with the 164 * global reset. */ 165 IXGB_WRITE_REG(hw, RCTL, IXGB_READ_REG(hw, RCTL) & ~IXGB_RCTL_RXEN); 166 IXGB_WRITE_REG(hw, TCTL, IXGB_READ_REG(hw, TCTL) & ~IXGB_TCTL_TXEN); 167 msec_delay(IXGB_DELAY_BEFORE_RESET); 168 169 /* Issue a global reset to the MAC. This will reset the chip's 170 * transmit, receive, DMA, and link units. It will not effect the 171 * current PCI configuration. The global reset bit is self- clearing, 172 * and should clear within a microsecond. */ 173 DEBUGOUT("Issuing a global reset to MAC\n"); 174 175 ctrl_reg = ixgb_mac_reset(hw); 176 177 /* Clear interrupt mask to stop board from generating interrupts */ 178 DEBUGOUT("Masking off all interrupts\n"); 179 IXGB_WRITE_REG(hw, IMC, 0xffffffff); 180 181 /* Clear any pending interrupt events. */ 182 icr_reg = IXGB_READ_REG(hw, ICR); 183 184 return (ctrl_reg & IXGB_CTRL0_RST); 185 } 186 187 /****************************************************************************** 188 * Identifies the vendor of the optics module on the adapter. The SR adapters 189 * support two different types of XPAK optics, so it is necessary to determine 190 * which optics are present before applying any optics-specific workarounds. 191 * 192 * hw - Struct containing variables accessed by shared code. 193 * 194 * Returns: the vendor of the XPAK optics module. 195 *****************************************************************************/ 196 static ixgb_xpak_vendor 197 ixgb_identify_xpak_vendor(struct ixgb_hw *hw) 198 { 199 uint32_t i; 200 uint16_t vendor_name[5]; 201 ixgb_xpak_vendor xpak_vendor; 202 203 DEBUGFUNC("ixgb_identify_xpak_vendor"); 204 205 /* Read the first few bytes of the vendor string from the XPAK NVR 206 * registers. These are standard XENPAK/XPAK registers, so all XPAK 207 * devices should implement them. */ 208 for(i = 0; i < 5; i++) { 209 vendor_name[i] = 210 ixgb_read_phy_reg(hw, MDIO_PMA_PMD_XPAK_VENDOR_NAME + i, 211 IXGB_PHY_ADDRESS, MDIO_PMA_PMD_DID); 212 } 213 214 /* Determine the actual vendor */ 215 if (vendor_name[0] == 'I' && 216 vendor_name[1] == 'N' && 217 vendor_name[2] == 'T' && 218 vendor_name[3] == 'E' && 219 vendor_name[4] == 'L') { 220 xpak_vendor = ixgb_xpak_vendor_intel; 221 } 222 else { 223 xpak_vendor = ixgb_xpak_vendor_infineon; 224 } 225 return (xpak_vendor); 226 } 227 228 /****************************************************************************** 229 * Determine the physical layer module on the adapter. 230 * 231 * hw - Struct containing variables accessed by shared code. The device_id 232 * field must be (correctly) populated before calling this routine. 233 * 234 * Returns: the phy type of the adapter. 235 *****************************************************************************/ 236 static ixgb_phy_type 237 ixgb_identify_phy(struct ixgb_hw *hw) 238 { 239 ixgb_phy_type phy_type; 240 ixgb_xpak_vendor xpak_vendor; 241 242 DEBUGFUNC("ixgb_identify_phy"); 243 244 /* Infer the transceiver/phy type from the device id */ 245 switch(hw->device_id) { 246 case IXGB_DEVICE_ID_82597EX: 247 DEBUGOUT("Identified TXN17401 optics\n"); 248 phy_type = ixgb_phy_type_txn17401; 249 break; 250 251 case IXGB_DEVICE_ID_82597EX_SR: 252 /* The SR adapters carry two different types of XPAK optics 253 * modules; read the vendor identifier to determine the exact 254 * type of optics. */ 255 xpak_vendor = ixgb_identify_xpak_vendor(hw); 256 if(xpak_vendor == ixgb_xpak_vendor_intel) { 257 DEBUGOUT("Identified TXN17201 optics\n"); 258 phy_type = ixgb_phy_type_txn17201; 259 } else { 260 DEBUGOUT("Identified G6005 optics\n"); 261 phy_type = ixgb_phy_type_g6005; 262 } 263 break; 264 265 case IXGB_DEVICE_ID_82597EX_LR: 266 DEBUGOUT("Identified G6104 optics\n"); 267 phy_type = ixgb_phy_type_g6104; 268 break; 269 270 case IXGB_DEVICE_ID_82597EX_CX4: 271 DEBUGOUT("Identified CX4\n"); 272 xpak_vendor = ixgb_identify_xpak_vendor(hw); 273 if(xpak_vendor == ixgb_xpak_vendor_intel) { 274 DEBUGOUT("Identified TXN17201 optics\n"); 275 phy_type = ixgb_phy_type_txn17201; 276 } else { 277 DEBUGOUT("Identified G6005 optics\n"); 278 phy_type = ixgb_phy_type_g6005; 279 } 280 break; 281 282 default: 283 DEBUGOUT("Unknown physical layer module\n"); 284 phy_type = ixgb_phy_type_unknown; 285 break; 286 } 287 288 /* update phy type for sun specific board */ 289 if (hw->subsystem_vendor_id == SUN_SUBVENDOR_ID) 290 phy_type = ixgb_phy_type_bcm; 291 292 return (phy_type); 293 } 294 295 /****************************************************************************** 296 * Performs basic configuration of the adapter. 297 * 298 * hw - Struct containing variables accessed by shared code 299 * 300 * Resets the controller. 301 * Reads and validates the EEPROM. 302 * Initializes the receive address registers. 303 * Initializes the multicast table. 304 * Clears all on-chip counters. 305 * Calls routine to setup flow control settings. 306 * Leaves the transmit and receive units disabled and uninitialized. 307 * 308 * Returns: 309 * TRUE if successful, 310 * FALSE if unrecoverable problems were encountered. 311 *****************************************************************************/ 312 boolean_t 313 ixgb_init_hw(struct ixgb_hw *hw) 314 { 315 uint32_t i; 316 uint32_t ctrl_reg; 317 boolean_t status; 318 319 DEBUGFUNC("ixgb_init_hw"); 320 321 /* Issue a global reset to the MAC. This will reset the chip's 322 * transmit, receive, DMA, and link units. It will not effect the 323 * current PCI configuration. The global reset bit is self- clearing, 324 * and should clear within a microsecond. */ 325 DEBUGOUT("Issuing a global reset to MAC\n"); 326 327 ctrl_reg = ixgb_mac_reset(hw); 328 329 DEBUGOUT("Issuing an EE reset to MAC\n"); 330 #ifdef HP_ZX1 331 /* Workaround for 82597EX reset errata */ 332 IXGB_WRITE_REG_IO(hw, CTRL1, IXGB_CTRL1_EE_RST); 333 #else 334 IXGB_WRITE_REG(hw, CTRL1, IXGB_CTRL1_EE_RST); 335 #endif 336 337 /* Delay a few ms just to allow the reset to complete */ 338 msec_delay(IXGB_DELAY_AFTER_EE_RESET); 339 340 if(ixgb_get_eeprom_data(hw) == FALSE) { 341 return (FALSE); 342 } 343 344 /* Use the device id to determine the type of phy/transceiver. */ 345 hw->device_id = ixgb_get_ee_device_id(hw); 346 hw->phy_type = ixgb_identify_phy(hw); 347 348 /* Setup the receive addresses. Receive Address Registers (RARs 0 - 349 * 15). */ 350 ixgb_init_rx_addrs(hw); 351 352 /* 353 * Check that a valid MAC address has been set. 354 * If it is not valid, we fail hardware init. 355 */ 356 if(!mac_addr_valid(hw->curr_mac_addr)) { 357 DEBUGOUT("MAC address invalid after ixgb_init_rx_addrs\n"); 358 return (FALSE); 359 } 360 361 /* tell the routines in this file they can access hardware again */ 362 hw->adapter_stopped = FALSE; 363 364 /* Fill in the bus_info structure */ 365 ixgb_get_bus_info(hw); 366 367 /* Zero out the Multicast HASH table */ 368 DEBUGOUT("Zeroing the MTA\n"); 369 for(i = 0; i < IXGB_MC_TBL_SIZE; i++) 370 IXGB_WRITE_REG_ARRAY(hw, MTA, i, 0); 371 372 /* Zero out the VLAN Filter Table Array */ 373 ixgb_clear_vfta(hw); 374 375 /* Zero all of the hardware counters */ 376 ixgb_clear_hw_cntrs(hw); 377 378 /* Call a subroutine to setup flow control. */ 379 status = ixgb_setup_fc(hw); 380 381 /* 82597EX errata: Call check-for-link in case lane deskew is locked */ 382 ixgb_check_for_link(hw); 383 384 return (status); 385 } 386 387 /****************************************************************************** 388 * Initializes receive address filters. 389 * 390 * hw - Struct containing variables accessed by shared code 391 * 392 * Places the MAC address in receive address register 0 and clears the rest 393 * of the receive addresss registers. Clears the multicast table. Assumes 394 * the receiver is in reset when the routine is called. 395 *****************************************************************************/ 396 void 397 ixgb_init_rx_addrs(struct ixgb_hw *hw) 398 { 399 uint32_t i; 400 401 DEBUGFUNC("ixgb_init_rx_addrs"); 402 403 /* 404 * If the current mac address is valid, assume it is a software override 405 * to the permanent address. 406 * Otherwise, use the permanent address from the eeprom. 407 */ 408 if(!mac_addr_valid(hw->curr_mac_addr)) { 409 410 /* Get the MAC address from the eeprom for later reference */ 411 ixgb_get_ee_mac_addr(hw, hw->curr_mac_addr); 412 413 DEBUGOUT3(" Keeping Permanent MAC Addr =%.2X %.2X %.2X ", 414 hw->curr_mac_addr[0], hw->curr_mac_addr[1], 415 hw->curr_mac_addr[2]); 416 DEBUGOUT3("%.2X %.2X %.2X\n", hw->curr_mac_addr[3], 417 hw->curr_mac_addr[4], hw->curr_mac_addr[5]); 418 } else { 419 420 /* Setup the receive address. */ 421 DEBUGOUT("Overriding MAC Address in RAR[0]\n"); 422 DEBUGOUT3(" New MAC Addr =%.2X %.2X %.2X ", 423 hw->curr_mac_addr[0], hw->curr_mac_addr[1], 424 hw->curr_mac_addr[2]); 425 DEBUGOUT3("%.2X %.2X %.2X\n", hw->curr_mac_addr[3], 426 hw->curr_mac_addr[4], hw->curr_mac_addr[5]); 427 428 ixgb_rar_set(hw, hw->curr_mac_addr, 0); 429 } 430 431 /* Zero out the other 15 receive addresses. */ 432 DEBUGOUT("Clearing RAR[1-15]\n"); 433 for(i = 1; i < IXGB_RAR_ENTRIES; i++) { 434 IXGB_WRITE_REG_ARRAY(hw, RA, (i << 1), 0); 435 IXGB_WRITE_REG_ARRAY(hw, RA, ((i << 1) + 1), 0); 436 } 437 438 return; 439 } 440 441 /****************************************************************************** 442 * Updates the MAC's list of multicast addresses. 443 * 444 * hw - Struct containing variables accessed by shared code 445 * mc_addr_list - the list of new multicast addresses 446 * mc_addr_count - number of addresses 447 * pad - number of bytes between addresses in the list 448 * 449 * The given list replaces any existing list. Clears the last 15 receive 450 * address registers and the multicast table. Uses receive address registers 451 * for the first 15 multicast addresses, and hashes the rest into the 452 * multicast table. 453 *****************************************************************************/ 454 void 455 ixgb_mc_addr_list_update(struct ixgb_hw *hw, uint8_t *mc_addr_list, 456 uint32_t mc_addr_count, uint32_t pad) 457 { 458 uint32_t hash_value; 459 uint32_t i; 460 uint32_t rar_used_count = 1; /* RAR[0] is used for our MAC address */ 461 462 DEBUGFUNC("ixgb_mc_addr_list_update"); 463 464 /* Set the new number of MC addresses that we are being requested to 465 * use. */ 466 hw->num_mc_addrs = mc_addr_count; 467 468 /* Clear RAR[1-15] */ 469 DEBUGOUT(" Clearing RAR[1-15]\n"); 470 for(i = rar_used_count; i < IXGB_RAR_ENTRIES; i++) { 471 IXGB_WRITE_REG_ARRAY(hw, RA, (i << 1), 0); 472 IXGB_WRITE_REG_ARRAY(hw, RA, ((i << 1) + 1), 0); 473 } 474 475 /* Clear the MTA */ 476 DEBUGOUT(" Clearing MTA\n"); 477 for(i = 0; i < IXGB_MC_TBL_SIZE; i++) { 478 IXGB_WRITE_REG_ARRAY(hw, MTA, i, 0); 479 } 480 481 /* Add the new addresses */ 482 for(i = 0; i < mc_addr_count; i++) { 483 DEBUGOUT(" Adding the multicast addresses:\n"); 484 DEBUGOUT7(" MC Addr #%d =%.2X %.2X %.2X %.2X %.2X %.2X\n", i, 485 mc_addr_list[i * (IXGB_ETH_LENGTH_OF_ADDRESS + pad)], 486 mc_addr_list[i * (IXGB_ETH_LENGTH_OF_ADDRESS + pad) + 1], 487 mc_addr_list[i * (IXGB_ETH_LENGTH_OF_ADDRESS + pad) + 2], 488 mc_addr_list[i * (IXGB_ETH_LENGTH_OF_ADDRESS + pad) + 3], 489 mc_addr_list[i * (IXGB_ETH_LENGTH_OF_ADDRESS + pad) + 4], 490 mc_addr_list[i * (IXGB_ETH_LENGTH_OF_ADDRESS + pad) + 5]); 491 492 /* Place this multicast address in the RAR if there is room, * 493 * else put it in the MTA */ 494 if(rar_used_count < IXGB_RAR_ENTRIES) { 495 ixgb_rar_set(hw, 496 mc_addr_list + 497 (i * (IXGB_ETH_LENGTH_OF_ADDRESS + pad)), 498 rar_used_count); 499 DEBUGOUT1("Added a multicast address to RAR[%d]\n", i); 500 rar_used_count++; 501 } else { 502 hash_value = 503 ixgb_hash_mc_addr(hw, 504 mc_addr_list + 505 (i * 506 (IXGB_ETH_LENGTH_OF_ADDRESS + 507 pad))); 508 509 DEBUGOUT1(" Hash value = 0x%03X\n", hash_value); 510 511 ixgb_mta_set(hw, hash_value); 512 } 513 } 514 515 DEBUGOUT("MC Update Complete\n"); 516 return; 517 } 518 519 /****************************************************************************** 520 * Hashes an address to determine its location in the multicast table 521 * 522 * hw - Struct containing variables accessed by shared code 523 * mc_addr - the multicast address to hash 524 * 525 * Returns: 526 * The hash value 527 *****************************************************************************/ 528 static uint32_t 529 ixgb_hash_mc_addr(struct ixgb_hw *hw, uint8_t *mc_addr) 530 { 531 uint32_t hash_value = 0; 532 533 DEBUGFUNC("ixgb_hash_mc_addr"); 534 535 /* The portion of the address that is used for the hash table is 536 * determined by the mc_filter_type setting. */ 537 switch(hw->mc_filter_type) { 538 /* [0] [1] [2] [3] [4] [5] 01 AA 00 12 34 56 LSB MSB - 539 * According to H/W docs */ 540 case 0: 541 /* [47:36] i.e. 0x563 for above example address */ 542 hash_value = 543 ((mc_addr[4] >> 4) | (((uint16_t)mc_addr[5]) << 4)); 544 break; 545 case 1: /* [46:35] i.e. 0xAC6 for above 546 * example address */ 547 hash_value = 548 ((mc_addr[4] >> 3) | (((uint16_t)mc_addr[5]) << 5)); 549 break; 550 case 2: /* [45:34] i.e. 0x5D8 for above 551 * example address */ 552 hash_value = 553 ((mc_addr[4] >> 2) | (((uint16_t)mc_addr[5]) << 6)); 554 break; 555 case 3: /* [43:32] i.e. 0x634 for above 556 * example address */ 557 hash_value = ((mc_addr[4]) | (((uint16_t)mc_addr[5]) << 8)); 558 break; 559 default: 560 /* Invalid mc_filter_type, what should we do? */ 561 DEBUGOUT("MC filter type param set incorrectly\n"); 562 ASSERT(0); 563 break; 564 } 565 566 hash_value &= 0xFFF; 567 return (hash_value); 568 } 569 570 /****************************************************************************** 571 * Sets the bit in the multicast table corresponding to the hash value. 572 * 573 * hw - Struct containing variables accessed by shared code 574 * hash_value - Multicast address hash value 575 *****************************************************************************/ 576 static void 577 ixgb_mta_set(struct ixgb_hw *hw, uint32_t hash_value) 578 { 579 uint32_t hash_bit, hash_reg; 580 uint32_t mta_reg; 581 582 /* The MTA is a register array of 128 32-bit registers. It is treated 583 * like an array of 4096 bits. We want to set bit 584 * BitArray[hash_value]. So we figure out what register the bit is in, 585 * read it, OR in the new bit, then write back the new value. The 586 * register is determined by the upper 7 bits of the hash value and the 587 * bit within that register are determined by the lower 5 bits of the 588 * value. */ 589 hash_reg = (hash_value >> 5) & 0x7F; 590 hash_bit = hash_value & 0x1F; 591 mta_reg = IXGB_READ_REG_ARRAY(hw, MTA, hash_reg); 592 mta_reg |= (1 << hash_bit); 593 IXGB_WRITE_REG_ARRAY(hw, MTA, hash_reg, mta_reg); 594 return; 595 } 596 597 /****************************************************************************** 598 * Puts an ethernet address into a receive address register. 599 * 600 * hw - Struct containing variables accessed by shared code 601 * addr - Address to put into receive address register 602 * index - Receive address register to write 603 *****************************************************************************/ 604 void 605 ixgb_rar_set(struct ixgb_hw *hw, uint8_t *addr, uint32_t index) 606 { 607 uint32_t rar_low, rar_high; 608 609 DEBUGFUNC("ixgb_rar_set"); 610 611 /* HW expects these in little endian so we reverse the byte order from 612 * network order (big endian) to little endian */ 613 rar_low = ((uint32_t)addr[0] | 614 ((uint32_t)addr[1] << 8) | 615 ((uint32_t)addr[2] << 16) | 616 ((uint32_t)addr[3] << 24)); 617 618 rar_high = ((uint32_t)addr[4] | 619 ((uint32_t)addr[5] << 8) | 620 IXGB_RAH_AV); 621 622 IXGB_WRITE_REG_ARRAY(hw, RA, (index << 1), rar_low); 623 IXGB_WRITE_REG_ARRAY(hw, RA, ((index << 1) + 1), rar_high); 624 return; 625 } 626 627 /****************************************************************************** 628 * Writes a value to the specified offset in the VLAN filter table. 629 * 630 * hw - Struct containing variables accessed by shared code 631 * offset - Offset in VLAN filer table to write 632 * value - Value to write into VLAN filter table 633 *****************************************************************************/ 634 void 635 ixgb_write_vfta(struct ixgb_hw *hw, uint32_t offset, uint32_t value) 636 { 637 IXGB_WRITE_REG_ARRAY(hw, VFTA, offset, value); 638 return; 639 } 640 641 /****************************************************************************** 642 * Clears the VLAN filer table 643 * 644 * hw - Struct containing variables accessed by shared code 645 *****************************************************************************/ 646 void 647 ixgb_clear_vfta(struct ixgb_hw *hw) 648 { 649 uint32_t offset; 650 651 for(offset = 0; offset < IXGB_VLAN_FILTER_TBL_SIZE; offset++) 652 IXGB_WRITE_REG_ARRAY(hw, VFTA, offset, 0); 653 return; 654 } 655 656 /****************************************************************************** 657 * Configures the flow control settings based on SW configuration. 658 * 659 * hw - Struct containing variables accessed by shared code 660 *****************************************************************************/ 661 662 boolean_t 663 ixgb_setup_fc(struct ixgb_hw *hw) 664 { 665 uint32_t ctrl_reg; 666 uint32_t pap_reg = 0; /* by default, assume no pause time */ 667 boolean_t status = TRUE; 668 669 DEBUGFUNC("ixgb_setup_fc"); 670 671 /* Get the current control reg 0 settings */ 672 ctrl_reg = IXGB_READ_REG(hw, CTRL0); 673 674 /* Clear the Receive Pause Enable and Transmit Pause Enable bits */ 675 ctrl_reg &= ~(IXGB_CTRL0_RPE | IXGB_CTRL0_TPE); 676 677 /* The possible values of the "flow_control" parameter are: 678 * 0: Flow control is completely disabled 679 * 1: Rx flow control is enabled (we can receive pause frames but not send 680 * pause frames). 681 * 2: Tx flow control is enabled (we can send pause frames but we do not 682 * support receiving pause frames) 683 * 3: Both Rx and TX flow control (symmetric) are enabled. 684 * other: Invalid. */ 685 switch(hw->fc.type) { 686 case ixgb_fc_none: /* 0 */ 687 /* Set CMDC bit to disable Rx Flow control */ 688 ctrl_reg |= (IXGB_CTRL0_CMDC); 689 break; 690 case ixgb_fc_rx_pause: /* 1 */ 691 /* RX Flow control is enabled, and TX Flow control is disabled. */ 692 ctrl_reg |= (IXGB_CTRL0_RPE); 693 break; 694 case ixgb_fc_tx_pause: /* 2 */ 695 /* TX Flow control is enabled, and RX Flow control is disabled, 696 * by a software over-ride. */ 697 ctrl_reg |= (IXGB_CTRL0_TPE); 698 pap_reg = hw->fc.pause_time; 699 break; 700 case ixgb_fc_full: /* 3 */ 701 /* Flow control (both RX and TX) is enabled by a software 702 * over-ride. */ 703 ctrl_reg |= (IXGB_CTRL0_RPE | IXGB_CTRL0_TPE); 704 pap_reg = hw->fc.pause_time; 705 break; 706 default: 707 /* We should never get here. The value should be 0-3. */ 708 DEBUGOUT("Flow control param set incorrectly\n"); 709 ASSERT(0); 710 break; 711 } 712 713 /* Write the new settings */ 714 IXGB_WRITE_REG(hw, CTRL0, ctrl_reg); 715 716 if(pap_reg != 0) { 717 IXGB_WRITE_REG(hw, PAP, pap_reg); 718 } 719 720 /* Set the flow control receive threshold registers. Normally, these 721 * registers will be set to a default threshold that may be adjusted 722 * later by the driver's runtime code. However, if the ability to 723 * transmit pause frames in not enabled, then these registers will be 724 * set to 0. */ 725 if(!(hw->fc.type & ixgb_fc_tx_pause)) { 726 IXGB_WRITE_REG(hw, FCRTL, 0); 727 IXGB_WRITE_REG(hw, FCRTH, 0); 728 } else { 729 /* We need to set up the Receive Threshold high and low water 730 * marks as well as (optionally) enabling the transmission of 731 * XON frames. */ 732 if(hw->fc.send_xon) { 733 IXGB_WRITE_REG(hw, FCRTL, 734 (hw->fc.low_water | IXGB_FCRTL_XONE)); 735 } else { 736 IXGB_WRITE_REG(hw, FCRTL, hw->fc.low_water); 737 } 738 IXGB_WRITE_REG(hw, FCRTH, hw->fc.high_water); 739 } 740 return (status); 741 } 742 743 /****************************************************************************** 744 * Reads a word from a device over the Management Data Interface (MDI) bus. 745 * This interface is used to manage Physical layer devices. 746 * 747 * hw - Struct containing variables accessed by hw code 748 * reg_address - Offset of device register being read. 749 * phy_address - Address of device on MDI. 750 * 751 * Returns: Data word (16 bits) from MDI device. 752 * 753 * The 82597EX has support for several MDI access methods. This routine 754 * uses the new protocol MDI Single Command and Address Operation. 755 * This requires that first an address cycle command is sent, followed by a 756 * read command. 757 *****************************************************************************/ 758 uint16_t 759 ixgb_read_phy_reg(struct ixgb_hw *hw, uint32_t reg_address, 760 uint32_t phy_address, uint32_t device_type) 761 { 762 uint32_t i; 763 uint32_t data; 764 uint32_t command = 0; 765 766 ASSERT(reg_address <= IXGB_MAX_PHY_REG_ADDRESS); 767 ASSERT(phy_address <= IXGB_MAX_PHY_ADDRESS); 768 ASSERT(device_type <= IXGB_MAX_PHY_DEV_TYPE); 769 770 /* Setup and write the address cycle command */ 771 command = ((reg_address << IXGB_MSCA_NP_ADDR_SHIFT) | 772 (device_type << IXGB_MSCA_DEV_TYPE_SHIFT) | 773 (phy_address << IXGB_MSCA_PHY_ADDR_SHIFT) | 774 (IXGB_MSCA_ADDR_CYCLE | IXGB_MSCA_MDI_COMMAND)); 775 776 IXGB_WRITE_REG(hw, MSCA, command); 777 778 /************************************************************** 779 ** Check every 10 usec to see if the address cycle completed 780 ** The COMMAND bit will clear when the operation is complete. 781 ** This may take as long as 64 usecs (we'll wait 100 usecs max) 782 ** from the CPU Write to the Ready bit assertion. 783 **************************************************************/ 784 785 for(i = 0; i < 10; i++) { 786 usec_delay(10); 787 788 command = IXGB_READ_REG(hw, MSCA); 789 790 if((command & IXGB_MSCA_MDI_COMMAND) == 0) 791 break; 792 } 793 794 ASSERT((command & IXGB_MSCA_MDI_COMMAND) == 0); 795 796 /* Address cycle complete, setup and write the read command */ 797 command = ((reg_address << IXGB_MSCA_NP_ADDR_SHIFT) | 798 (device_type << IXGB_MSCA_DEV_TYPE_SHIFT) | 799 (phy_address << IXGB_MSCA_PHY_ADDR_SHIFT) | 800 (IXGB_MSCA_READ | IXGB_MSCA_MDI_COMMAND)); 801 802 IXGB_WRITE_REG(hw, MSCA, command); 803 804 /************************************************************** 805 ** Check every 10 usec to see if the read command completed 806 ** The COMMAND bit will clear when the operation is complete. 807 ** The read may take as long as 64 usecs (we'll wait 100 usecs max) 808 ** from the CPU Write to the Ready bit assertion. 809 **************************************************************/ 810 811 for(i = 0; i < 10; i++) { 812 usec_delay(10); 813 814 command = IXGB_READ_REG(hw, MSCA); 815 816 if((command & IXGB_MSCA_MDI_COMMAND) == 0) 817 break; 818 } 819 820 ASSERT((command & IXGB_MSCA_MDI_COMMAND) == 0); 821 822 /* Operation is complete, get the data from the MDIO Read/Write Data 823 * register and return. */ 824 data = IXGB_READ_REG(hw, MSRWD); 825 data >>= IXGB_MSRWD_READ_DATA_SHIFT; 826 return ((uint16_t)data); 827 } 828 829 /****************************************************************************** 830 * Writes a word to a device over the Management Data Interface (MDI) bus. 831 * This interface is used to manage Physical layer devices. 832 * 833 * hw - Struct containing variables accessed by hw code 834 * reg_address - Offset of device register being read. 835 * phy_address - Address of device on MDI. 836 * device_type - Also known as the Device ID or DID. 837 * data - 16-bit value to be written 838 * 839 * Returns: void. 840 * 841 * The 82597EX has support for several MDI access methods. This routine 842 * uses the new protocol MDI Single Command and Address Operation. 843 * This requires that first an address cycle command is sent, followed by a 844 * write command. 845 *****************************************************************************/ 846 void 847 ixgb_write_phy_reg(struct ixgb_hw *hw, uint32_t reg_address, 848 uint32_t phy_address, uint32_t device_type, uint16_t data) 849 { 850 uint32_t i; 851 uint32_t command = 0; 852 853 ASSERT(reg_address <= IXGB_MAX_PHY_REG_ADDRESS); 854 ASSERT(phy_address <= IXGB_MAX_PHY_ADDRESS); 855 ASSERT(device_type <= IXGB_MAX_PHY_DEV_TYPE); 856 857 /* Put the data in the MDIO Read/Write Data register */ 858 IXGB_WRITE_REG(hw, MSRWD, (uint32_t)data); 859 860 /* Setup and write the address cycle command */ 861 command = ((reg_address << IXGB_MSCA_NP_ADDR_SHIFT) | 862 (device_type << IXGB_MSCA_DEV_TYPE_SHIFT) | 863 (phy_address << IXGB_MSCA_PHY_ADDR_SHIFT) | 864 (IXGB_MSCA_ADDR_CYCLE | IXGB_MSCA_MDI_COMMAND)); 865 866 IXGB_WRITE_REG(hw, MSCA, command); 867 868 /************************************************************** 869 ** Check every 10 usec to see if the address cycle completed 870 ** The COMMAND bit will clear when the operation is complete. 871 ** This may take as long as 64 usecs (we'll wait 100 usecs max) 872 ** from the CPU Write to the Ready bit assertion. 873 **************************************************************/ 874 875 for(i = 0; i < 10; i++) { 876 usec_delay(10); 877 878 command = IXGB_READ_REG(hw, MSCA); 879 880 if((command & IXGB_MSCA_MDI_COMMAND) == 0) 881 break; 882 } 883 884 ASSERT((command & IXGB_MSCA_MDI_COMMAND) == 0); 885 886 /* Address cycle complete, setup and write the write command */ 887 command = ((reg_address << IXGB_MSCA_NP_ADDR_SHIFT) | 888 (device_type << IXGB_MSCA_DEV_TYPE_SHIFT) | 889 (phy_address << IXGB_MSCA_PHY_ADDR_SHIFT) | 890 (IXGB_MSCA_WRITE | IXGB_MSCA_MDI_COMMAND)); 891 892 IXGB_WRITE_REG(hw, MSCA, command); 893 894 /************************************************************** 895 ** Check every 10 usec to see if the read command completed 896 ** The COMMAND bit will clear when the operation is complete. 897 ** The write may take as long as 64 usecs (we'll wait 100 usecs max) 898 ** from the CPU Write to the Ready bit assertion. 899 **************************************************************/ 900 901 for(i = 0; i < 10; i++) { 902 usec_delay(10); 903 904 command = IXGB_READ_REG(hw, MSCA); 905 906 if((command & IXGB_MSCA_MDI_COMMAND) == 0) 907 break; 908 } 909 910 ASSERT((command & IXGB_MSCA_MDI_COMMAND) == 0); 911 912 /* Operation is complete, return. */ 913 } 914 915 /****************************************************************************** 916 * Checks to see if the link status of the hardware has changed. 917 * 918 * hw - Struct containing variables accessed by hw code 919 * 920 * Called by any function that needs to check the link status of the adapter. 921 *****************************************************************************/ 922 void 923 ixgb_check_for_link(struct ixgb_hw *hw) 924 { 925 uint32_t status_reg; 926 uint32_t xpcss_reg; 927 928 DEBUGFUNC("ixgb_check_for_link"); 929 930 xpcss_reg = IXGB_READ_REG(hw, XPCSS); 931 status_reg = IXGB_READ_REG(hw, STATUS); 932 933 if((xpcss_reg & IXGB_XPCSS_ALIGN_STATUS) && 934 (status_reg & IXGB_STATUS_LU)) { 935 hw->link_up = TRUE; 936 } else if(!(xpcss_reg & IXGB_XPCSS_ALIGN_STATUS) && 937 (status_reg & IXGB_STATUS_LU)) { 938 DEBUGOUT("XPCSS Not Aligned while Status:LU is set.\n"); 939 hw->link_up = ixgb_link_reset(hw); 940 } else { 941 /* 942 * 82597EX errata. Since the lane deskew problem may prevent 943 * link, reset the link before reporting link down. 944 */ 945 hw->link_up = ixgb_link_reset(hw); 946 } 947 /* Anything else for 10 Gig?? */ 948 } 949 950 /****************************************************************************** 951 * Check for a bad link condition that may have occured. 952 * The indication is that the RFC / LFC registers may be incrementing 953 * continually. A full adapter reset is required to recover. 954 * 955 * hw - Struct containing variables accessed by hw code 956 * 957 * Called by any function that needs to check the link status of the adapter. 958 *****************************************************************************/ 959 boolean_t 960 ixgb_check_for_bad_link(struct ixgb_hw *hw) 961 { 962 uint32_t newLFC, newRFC; 963 boolean_t bad_link_returncode = FALSE; 964 965 if(hw->phy_type == ixgb_phy_type_txn17401) { 966 newLFC = IXGB_READ_REG(hw, LFC); 967 newRFC = IXGB_READ_REG(hw, RFC); 968 if((hw->lastLFC + 250 < newLFC) || (hw->lastRFC + 250 < newRFC)) { 969 DEBUGOUT("BAD LINK! too many LFC/RFC since last check\n"); 970 bad_link_returncode = TRUE; 971 } 972 hw->lastLFC = newLFC; 973 hw->lastRFC = newRFC; 974 } 975 976 return bad_link_returncode; 977 } 978 979 /****************************************************************************** 980 * Clears all hardware statistics counters. 981 * 982 * hw - Struct containing variables accessed by shared code 983 *****************************************************************************/ 984 void 985 ixgb_clear_hw_cntrs(struct ixgb_hw *hw) 986 { 987 volatile uint32_t temp_reg; 988 989 DEBUGFUNC("ixgb_clear_hw_cntrs"); 990 991 /* if we are stopped or resetting exit gracefully */ 992 if(hw->adapter_stopped) { 993 DEBUGOUT("Exiting because the adapter is stopped!!!\n"); 994 return; 995 } 996 997 temp_reg = IXGB_READ_REG(hw, TPRL); 998 temp_reg = IXGB_READ_REG(hw, TPRH); 999 temp_reg = IXGB_READ_REG(hw, GPRCL); 1000 temp_reg = IXGB_READ_REG(hw, GPRCH); 1001 temp_reg = IXGB_READ_REG(hw, BPRCL); 1002 temp_reg = IXGB_READ_REG(hw, BPRCH); 1003 temp_reg = IXGB_READ_REG(hw, MPRCL); 1004 temp_reg = IXGB_READ_REG(hw, MPRCH); 1005 temp_reg = IXGB_READ_REG(hw, UPRCL); 1006 temp_reg = IXGB_READ_REG(hw, UPRCH); 1007 temp_reg = IXGB_READ_REG(hw, VPRCL); 1008 temp_reg = IXGB_READ_REG(hw, VPRCH); 1009 temp_reg = IXGB_READ_REG(hw, JPRCL); 1010 temp_reg = IXGB_READ_REG(hw, JPRCH); 1011 temp_reg = IXGB_READ_REG(hw, GORCL); 1012 temp_reg = IXGB_READ_REG(hw, GORCH); 1013 temp_reg = IXGB_READ_REG(hw, TORL); 1014 temp_reg = IXGB_READ_REG(hw, TORH); 1015 temp_reg = IXGB_READ_REG(hw, RNBC); 1016 temp_reg = IXGB_READ_REG(hw, RUC); 1017 temp_reg = IXGB_READ_REG(hw, ROC); 1018 temp_reg = IXGB_READ_REG(hw, RLEC); 1019 temp_reg = IXGB_READ_REG(hw, CRCERRS); 1020 temp_reg = IXGB_READ_REG(hw, ICBC); 1021 temp_reg = IXGB_READ_REG(hw, ECBC); 1022 temp_reg = IXGB_READ_REG(hw, MPC); 1023 temp_reg = IXGB_READ_REG(hw, TPTL); 1024 temp_reg = IXGB_READ_REG(hw, TPTH); 1025 temp_reg = IXGB_READ_REG(hw, GPTCL); 1026 temp_reg = IXGB_READ_REG(hw, GPTCH); 1027 temp_reg = IXGB_READ_REG(hw, BPTCL); 1028 temp_reg = IXGB_READ_REG(hw, BPTCH); 1029 temp_reg = IXGB_READ_REG(hw, MPTCL); 1030 temp_reg = IXGB_READ_REG(hw, MPTCH); 1031 temp_reg = IXGB_READ_REG(hw, UPTCL); 1032 temp_reg = IXGB_READ_REG(hw, UPTCH); 1033 temp_reg = IXGB_READ_REG(hw, VPTCL); 1034 temp_reg = IXGB_READ_REG(hw, VPTCH); 1035 temp_reg = IXGB_READ_REG(hw, JPTCL); 1036 temp_reg = IXGB_READ_REG(hw, JPTCH); 1037 temp_reg = IXGB_READ_REG(hw, GOTCL); 1038 temp_reg = IXGB_READ_REG(hw, GOTCH); 1039 temp_reg = IXGB_READ_REG(hw, TOTL); 1040 temp_reg = IXGB_READ_REG(hw, TOTH); 1041 temp_reg = IXGB_READ_REG(hw, DC); 1042 temp_reg = IXGB_READ_REG(hw, PLT64C); 1043 temp_reg = IXGB_READ_REG(hw, TSCTC); 1044 temp_reg = IXGB_READ_REG(hw, TSCTFC); 1045 temp_reg = IXGB_READ_REG(hw, IBIC); 1046 temp_reg = IXGB_READ_REG(hw, RFC); 1047 temp_reg = IXGB_READ_REG(hw, LFC); 1048 temp_reg = IXGB_READ_REG(hw, PFRC); 1049 temp_reg = IXGB_READ_REG(hw, PFTC); 1050 temp_reg = IXGB_READ_REG(hw, MCFRC); 1051 temp_reg = IXGB_READ_REG(hw, MCFTC); 1052 temp_reg = IXGB_READ_REG(hw, XONRXC); 1053 temp_reg = IXGB_READ_REG(hw, XONTXC); 1054 temp_reg = IXGB_READ_REG(hw, XOFFRXC); 1055 temp_reg = IXGB_READ_REG(hw, XOFFTXC); 1056 temp_reg = IXGB_READ_REG(hw, RJC); 1057 return; 1058 } 1059 1060 /****************************************************************************** 1061 * Turns on the software controllable LED 1062 * 1063 * hw - Struct containing variables accessed by shared code 1064 *****************************************************************************/ 1065 void 1066 ixgb_led_on(struct ixgb_hw *hw) 1067 { 1068 uint32_t ctrl0_reg = IXGB_READ_REG(hw, CTRL0); 1069 1070 /* To turn on the LED, clear software-definable pin 0 (SDP0). */ 1071 ctrl0_reg &= ~IXGB_CTRL0_SDP0; 1072 IXGB_WRITE_REG(hw, CTRL0, ctrl0_reg); 1073 return; 1074 } 1075 1076 /****************************************************************************** 1077 * Turns off the software controllable LED 1078 * 1079 * hw - Struct containing variables accessed by shared code 1080 *****************************************************************************/ 1081 void 1082 ixgb_led_off(struct ixgb_hw *hw) 1083 { 1084 uint32_t ctrl0_reg = IXGB_READ_REG(hw, CTRL0); 1085 1086 /* To turn off the LED, set software-definable pin 0 (SDP0). */ 1087 ctrl0_reg |= IXGB_CTRL0_SDP0; 1088 IXGB_WRITE_REG(hw, CTRL0, ctrl0_reg); 1089 return; 1090 } 1091 1092 /****************************************************************************** 1093 * Gets the current PCI bus type, speed, and width of the hardware 1094 * 1095 * hw - Struct containing variables accessed by shared code 1096 *****************************************************************************/ 1097 static void 1098 ixgb_get_bus_info(struct ixgb_hw *hw) 1099 { 1100 uint32_t status_reg; 1101 1102 status_reg = IXGB_READ_REG(hw, STATUS); 1103 1104 hw->bus.type = 1105 (status_reg & IXGB_STATUS_PCIX_MODE) ? ixgb_bus_type_pcix : 1106 ixgb_bus_type_pci; 1107 1108 if(hw->bus.type == ixgb_bus_type_pci) { 1109 hw->bus.speed = 1110 (status_reg & IXGB_STATUS_PCI_SPD) ? ixgb_bus_speed_66 : 1111 ixgb_bus_speed_33; 1112 } else { 1113 switch(status_reg & IXGB_STATUS_PCIX_SPD_MASK) { 1114 case IXGB_STATUS_PCIX_SPD_66: 1115 hw->bus.speed = ixgb_bus_speed_66; 1116 break; 1117 case IXGB_STATUS_PCIX_SPD_100: 1118 hw->bus.speed = ixgb_bus_speed_100; 1119 break; 1120 case IXGB_STATUS_PCIX_SPD_133: 1121 hw->bus.speed = ixgb_bus_speed_133; 1122 break; 1123 default: 1124 hw->bus.speed = ixgb_bus_speed_reserved; 1125 break; 1126 } 1127 } 1128 1129 hw->bus.width = 1130 (status_reg & IXGB_STATUS_BUS64) ? ixgb_bus_width_64 : 1131 ixgb_bus_width_32; 1132 1133 return; 1134 } 1135 1136 /****************************************************************************** 1137 * Tests a MAC address to ensure it is a valid Individual Address 1138 * 1139 * mac_addr - pointer to MAC address. 1140 * 1141 *****************************************************************************/ 1142 boolean_t 1143 mac_addr_valid(uint8_t *mac_addr) 1144 { 1145 boolean_t is_valid = TRUE; 1146 1147 DEBUGFUNC("mac_addr_valid"); 1148 1149 /* Make sure it is not a multicast address */ 1150 if(IS_MULTICAST(mac_addr)) { 1151 DEBUGOUT("MAC address is multicast\n"); 1152 is_valid = FALSE; 1153 } 1154 /* Not a broadcast address */ 1155 else if(IS_BROADCAST(mac_addr)) { 1156 DEBUGOUT("MAC address is broadcast\n"); 1157 is_valid = FALSE; 1158 } 1159 /* Reject the zero address */ 1160 else if (mac_addr[0] == 0 && 1161 mac_addr[1] == 0 && 1162 mac_addr[2] == 0 && 1163 mac_addr[3] == 0 && 1164 mac_addr[4] == 0 && 1165 mac_addr[5] == 0) { 1166 DEBUGOUT("MAC address is all zeros\n"); 1167 is_valid = FALSE; 1168 } 1169 return (is_valid); 1170 } 1171 1172 /****************************************************************************** 1173 * Resets the 10GbE link. Waits the settle time and returns the state of 1174 * the link. 1175 * 1176 * hw - Struct containing variables accessed by shared code 1177 *****************************************************************************/ 1178 boolean_t 1179 ixgb_link_reset(struct ixgb_hw *hw) 1180 { 1181 boolean_t link_status = FALSE; 1182 uint8_t wait_retries = MAX_RESET_ITERATIONS; 1183 uint8_t lrst_retries = MAX_RESET_ITERATIONS; 1184 1185 do { 1186 /* Reset the link */ 1187 IXGB_WRITE_REG(hw, CTRL0, 1188 IXGB_READ_REG(hw, CTRL0) | IXGB_CTRL0_LRST); 1189 1190 /* Wait for link-up and lane re-alignment */ 1191 do { 1192 usec_delay(IXGB_DELAY_USECS_AFTER_LINK_RESET); 1193 link_status = 1194 ((IXGB_READ_REG(hw, STATUS) & IXGB_STATUS_LU) && 1195 (IXGB_READ_REG(hw, XPCSS) & 1196 IXGB_XPCSS_ALIGN_STATUS)) ? TRUE : FALSE; 1197 } while(!link_status && --wait_retries); 1198 1199 } while(!link_status && --lrst_retries); 1200 1201 return link_status; 1202 } 1203 1204 /****************************************************************************** 1205 * Resets the 10GbE optics module. 1206 * 1207 * hw - Struct containing variables accessed by shared code 1208 *****************************************************************************/ 1209 void 1210 ixgb_optics_reset(struct ixgb_hw *hw) 1211 { 1212 if(hw->phy_type == ixgb_phy_type_txn17401) { 1213 uint16_t mdio_reg; 1214 1215 ixgb_write_phy_reg(hw, 1216 MDIO_PMA_PMD_CR1, 1217 IXGB_PHY_ADDRESS, 1218 MDIO_PMA_PMD_DID, 1219 MDIO_PMA_PMD_CR1_RESET); 1220 1221 mdio_reg = ixgb_read_phy_reg(hw, 1222 MDIO_PMA_PMD_CR1, 1223 IXGB_PHY_ADDRESS, 1224 MDIO_PMA_PMD_DID); 1225 } 1226 1227 return; 1228 } 1229 1230 /****************************************************************************** 1231 * Resets the 10GbE optics module for Sun variant NIC. 1232 * 1233 * hw - Struct containing variables accessed by shared code 1234 *****************************************************************************/ 1235 1236 #define IXGB_BCM8704_USER_PMD_TX_CTRL_REG 0xC803 1237 #define IXGB_BCM8704_USER_PMD_TX_CTRL_REG_VAL 0x0164 1238 #define IXGB_BCM8704_USER_CTRL_REG 0xC800 1239 #define IXGB_BCM8704_USER_CTRL_REG_VAL 0x7FBF 1240 #define IXGB_BCM8704_USER_DEV3_ADDR 0x0003 1241 #define IXGB_SUN_PHY_ADDRESS 0x0000 1242 #define IXGB_SUN_PHY_RESET_DELAY 305 1243 1244 static void 1245 ixgb_optics_reset_bcm(struct ixgb_hw *hw) 1246 { 1247 uint32_t ctrl = IXGB_READ_REG(hw, CTRL0); 1248 ctrl &= ~IXGB_CTRL0_SDP2; 1249 ctrl |= IXGB_CTRL0_SDP3; 1250 IXGB_WRITE_REG(hw, CTRL0, ctrl); 1251 1252 /* SerDes needs extra delay */ 1253 msec_delay(IXGB_SUN_PHY_RESET_DELAY); 1254 1255 /* Broadcom 7408L configuration */ 1256 /* Reference clock config */ 1257 ixgb_write_phy_reg(hw, 1258 IXGB_BCM8704_USER_PMD_TX_CTRL_REG, 1259 IXGB_SUN_PHY_ADDRESS, 1260 IXGB_BCM8704_USER_DEV3_ADDR, 1261 IXGB_BCM8704_USER_PMD_TX_CTRL_REG_VAL); 1262 /* we must read the registers twice */ 1263 ixgb_read_phy_reg(hw, 1264 IXGB_BCM8704_USER_PMD_TX_CTRL_REG, 1265 IXGB_SUN_PHY_ADDRESS, 1266 IXGB_BCM8704_USER_DEV3_ADDR); 1267 ixgb_read_phy_reg(hw, 1268 IXGB_BCM8704_USER_PMD_TX_CTRL_REG, 1269 IXGB_SUN_PHY_ADDRESS, 1270 IXGB_BCM8704_USER_DEV3_ADDR); 1271 1272 ixgb_write_phy_reg(hw, 1273 IXGB_BCM8704_USER_CTRL_REG, 1274 IXGB_SUN_PHY_ADDRESS, 1275 IXGB_BCM8704_USER_DEV3_ADDR, 1276 IXGB_BCM8704_USER_CTRL_REG_VAL); 1277 ixgb_read_phy_reg(hw, 1278 IXGB_BCM8704_USER_CTRL_REG, 1279 IXGB_SUN_PHY_ADDRESS, 1280 IXGB_BCM8704_USER_DEV3_ADDR); 1281 ixgb_read_phy_reg(hw, 1282 IXGB_BCM8704_USER_CTRL_REG, 1283 IXGB_SUN_PHY_ADDRESS, 1284 IXGB_BCM8704_USER_DEV3_ADDR); 1285 1286 /* SerDes needs extra delay */ 1287 msec_delay(IXGB_SUN_PHY_RESET_DELAY); 1288 1289 return; 1290 } 1291