1 /******************************************************************************* 2 3 Copyright (c) 2001-2005, Intel Corporation 4 All rights reserved. 5 6 Redistribution and use in source and binary forms, with or without 7 modification, are permitted provided that the following conditions are met: 8 9 1. Redistributions of source code must retain the above copyright notice, 10 this list of conditions and the following disclaimer. 11 12 2. Redistributions in binary form must reproduce the above copyright 13 notice, this list of conditions and the following disclaimer in the 14 documentation and/or other materials provided with the distribution. 15 16 3. Neither the name of the Intel Corporation nor the names of its 17 contributors may be used to endorse or promote products derived from 18 this software without specific prior written permission. 19 20 THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS" 21 AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE 22 IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE 23 ARE DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT OWNER OR CONTRIBUTORS BE 24 LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR 25 CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF 26 SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS 27 INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN 28 CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) 29 ARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE 30 POSSIBILITY OF SUCH DAMAGE. 31 32 *******************************************************************************/ 33 34 /* $OpenBSD: ixgb_ee.c,v 1.3 2013/08/07 01:06:39 bluhm Exp $ */ 35 36 #include <sys/param.h> 37 #include <sys/systm.h> 38 #include <sys/sockio.h> 39 #include <sys/mbuf.h> 40 #include <sys/malloc.h> 41 #include <sys/kernel.h> 42 #include <sys/device.h> 43 #include <sys/socket.h> 44 45 #include <net/if.h> 46 #include <net/if_dl.h> 47 #include <net/if_media.h> 48 49 #ifdef INET 50 #include <netinet/in.h> 51 #include <netinet/in_systm.h> 52 #include <netinet/ip.h> 53 #include <netinet/if_ether.h> 54 #endif 55 56 #include <uvm/uvm_extern.h> 57 58 #include <dev/pci/pcireg.h> 59 #include <dev/pci/pcivar.h> 60 #include <dev/pci/pcidevs.h> 61 62 #include <dev/pci/ixgb_hw.h> 63 #include <dev/pci/ixgb_ee.h> 64 65 /* Local prototypes */ 66 static uint16_t ixgb_shift_in_bits(struct ixgb_hw *hw); 67 68 static void ixgb_shift_out_bits(struct ixgb_hw *hw, uint16_t data, 69 uint16_t count); 70 static void ixgb_standby_eeprom(struct ixgb_hw *hw); 71 72 static boolean_t ixgb_wait_eeprom_command(struct ixgb_hw *hw); 73 74 static void ixgb_cleanup_eeprom(struct ixgb_hw *hw); 75 76 /****************************************************************************** 77 * Raises the EEPROM's clock input. 78 * 79 * hw - Struct containing variables accessed by shared code 80 * eecd_reg - EECD's current value 81 *****************************************************************************/ 82 static void 83 ixgb_raise_clock(struct ixgb_hw *hw, uint32_t *eecd_reg) 84 { 85 /* Raise the clock input to the EEPROM (by setting the SK bit), and 86 * then wait 50 microseconds. */ 87 *eecd_reg = *eecd_reg | IXGB_EECD_SK; 88 IXGB_WRITE_REG(hw, EECD, *eecd_reg); 89 usec_delay(50); 90 return; 91 } 92 93 /****************************************************************************** 94 * Lowers the EEPROM's clock input. 95 * 96 * hw - Struct containing variables accessed by shared code 97 * eecd_reg - EECD's current value 98 *****************************************************************************/ 99 static void 100 ixgb_lower_clock(struct ixgb_hw *hw, uint32_t *eecd_reg) 101 { 102 /* Lower the clock input to the EEPROM (by clearing the SK bit), and 103 * then wait 50 microseconds. */ 104 *eecd_reg = *eecd_reg & ~IXGB_EECD_SK; 105 IXGB_WRITE_REG(hw, EECD, *eecd_reg); 106 usec_delay(50); 107 return; 108 } 109 110 /****************************************************************************** 111 * Shift data bits out to the EEPROM. 112 * 113 * hw - Struct containing variables accessed by shared code 114 * data - data to send to the EEPROM 115 * count - number of bits to shift out 116 *****************************************************************************/ 117 static void 118 ixgb_shift_out_bits(struct ixgb_hw *hw, uint16_t data, uint16_t count) 119 { 120 uint32_t eecd_reg; 121 uint32_t mask; 122 123 /* We need to shift "count" bits out to the EEPROM. So, value in the 124 * "data" parameter will be shifted out to the EEPROM one bit at a 125 * time. In order to do this, "data" must be broken down into bits. */ 126 mask = 0x01 << (count - 1); 127 eecd_reg = IXGB_READ_REG(hw, EECD); 128 eecd_reg &= ~(IXGB_EECD_DO | IXGB_EECD_DI); 129 do { 130 /* A "1" is shifted out to the EEPROM by setting bit "DI" to a 131 * "1", and then raising and then lowering the clock (the SK 132 * bit controls the clock input to the EEPROM). A "0" is 133 * shifted out to the EEPROM by setting "DI" to "0" and then 134 * raising and then lowering the clock. */ 135 eecd_reg &= ~IXGB_EECD_DI; 136 137 if(data & mask) 138 eecd_reg |= IXGB_EECD_DI; 139 140 IXGB_WRITE_REG(hw, EECD, eecd_reg); 141 142 usec_delay(50); 143 144 ixgb_raise_clock(hw, &eecd_reg); 145 ixgb_lower_clock(hw, &eecd_reg); 146 147 mask = mask >> 1; 148 149 } while(mask); 150 151 /* We leave the "DI" bit set to "0" when we leave this routine. */ 152 eecd_reg &= ~IXGB_EECD_DI; 153 IXGB_WRITE_REG(hw, EECD, eecd_reg); 154 return; 155 } 156 157 /****************************************************************************** 158 * Shift data bits in from the EEPROM 159 * 160 * hw - Struct containing variables accessed by shared code 161 *****************************************************************************/ 162 static uint16_t 163 ixgb_shift_in_bits(struct ixgb_hw *hw) 164 { 165 uint32_t eecd_reg; 166 uint32_t i; 167 uint16_t data; 168 169 /* In order to read a register from the EEPROM, we need to shift 16 170 * bits in from the EEPROM. Bits are "shifted in" by raising the clock 171 * input to the EEPROM (setting the SK bit), and then reading the value 172 * of the "DO" bit. During this "shifting in" process the "DI" bit 173 * should always be clear.. */ 174 175 eecd_reg = IXGB_READ_REG(hw, EECD); 176 177 eecd_reg &= ~(IXGB_EECD_DO | IXGB_EECD_DI); 178 data = 0; 179 180 for(i = 0; i < 16; i++) { 181 data = data << 1; 182 ixgb_raise_clock(hw, &eecd_reg); 183 184 eecd_reg = IXGB_READ_REG(hw, EECD); 185 186 eecd_reg &= ~(IXGB_EECD_DI); 187 if(eecd_reg & IXGB_EECD_DO) 188 data |= 1; 189 190 ixgb_lower_clock(hw, &eecd_reg); 191 } 192 193 return data; 194 } 195 196 /****************************************************************************** 197 * Prepares EEPROM for access 198 * 199 * hw - Struct containing variables accessed by shared code 200 * 201 * Lowers EEPROM clock. Clears input pin. Sets the chip select pin. This 202 * function should be called before issuing a command to the EEPROM. 203 *****************************************************************************/ 204 static void 205 ixgb_setup_eeprom(struct ixgb_hw *hw) 206 { 207 uint32_t eecd_reg; 208 209 eecd_reg = IXGB_READ_REG(hw, EECD); 210 211 /* Clear SK and DI */ 212 eecd_reg &= ~(IXGB_EECD_SK | IXGB_EECD_DI); 213 IXGB_WRITE_REG(hw, EECD, eecd_reg); 214 215 /* Set CS */ 216 eecd_reg |= IXGB_EECD_CS; 217 IXGB_WRITE_REG(hw, EECD, eecd_reg); 218 return; 219 } 220 221 /****************************************************************************** 222 * Returns EEPROM to a "standby" state 223 * 224 * hw - Struct containing variables accessed by shared code 225 *****************************************************************************/ 226 static void 227 ixgb_standby_eeprom(struct ixgb_hw *hw) 228 { 229 uint32_t eecd_reg; 230 231 eecd_reg = IXGB_READ_REG(hw, EECD); 232 233 /* Deselct EEPROM */ 234 eecd_reg &= ~(IXGB_EECD_CS | IXGB_EECD_SK); 235 IXGB_WRITE_REG(hw, EECD, eecd_reg); 236 usec_delay(50); 237 238 /* Clock high */ 239 eecd_reg |= IXGB_EECD_SK; 240 IXGB_WRITE_REG(hw, EECD, eecd_reg); 241 usec_delay(50); 242 243 /* Select EEPROM */ 244 eecd_reg |= IXGB_EECD_CS; 245 IXGB_WRITE_REG(hw, EECD, eecd_reg); 246 usec_delay(50); 247 248 /* Clock low */ 249 eecd_reg &= ~IXGB_EECD_SK; 250 IXGB_WRITE_REG(hw, EECD, eecd_reg); 251 usec_delay(50); 252 return; 253 } 254 255 /****************************************************************************** 256 * Raises then lowers the EEPROM's clock pin 257 * 258 * hw - Struct containing variables accessed by shared code 259 *****************************************************************************/ 260 static void 261 ixgb_clock_eeprom(struct ixgb_hw *hw) 262 { 263 uint32_t eecd_reg; 264 265 eecd_reg = IXGB_READ_REG(hw, EECD); 266 267 /* Rising edge of clock */ 268 eecd_reg |= IXGB_EECD_SK; 269 IXGB_WRITE_REG(hw, EECD, eecd_reg); 270 usec_delay(50); 271 272 /* Falling edge of clock */ 273 eecd_reg &= ~IXGB_EECD_SK; 274 IXGB_WRITE_REG(hw, EECD, eecd_reg); 275 usec_delay(50); 276 return; 277 } 278 279 /****************************************************************************** 280 * Terminates a command by lowering the EEPROM's chip select pin 281 * 282 * hw - Struct containing variables accessed by shared code 283 *****************************************************************************/ 284 static void 285 ixgb_cleanup_eeprom(struct ixgb_hw *hw) 286 { 287 uint32_t eecd_reg; 288 289 eecd_reg = IXGB_READ_REG(hw, EECD); 290 291 eecd_reg &= ~(IXGB_EECD_CS | IXGB_EECD_DI); 292 293 IXGB_WRITE_REG(hw, EECD, eecd_reg); 294 295 ixgb_clock_eeprom(hw); 296 return; 297 } 298 299 /****************************************************************************** 300 * Waits for the EEPROM to finish the current command. 301 * 302 * hw - Struct containing variables accessed by shared code 303 * 304 * The command is done when the EEPROM's data out pin goes high. 305 * 306 * Returns: 307 * TRUE: EEPROM data pin is high before timeout. 308 * FALSE: Time expired. 309 *****************************************************************************/ 310 static boolean_t 311 ixgb_wait_eeprom_command(struct ixgb_hw *hw) 312 { 313 uint32_t eecd_reg; 314 uint32_t i; 315 316 /* Toggle the CS line. This in effect tells to EEPROM to actually 317 * execute the command in question. */ 318 ixgb_standby_eeprom(hw); 319 320 /* Now read DO repeatedly until is high (equal to '1'). The EEEPROM 321 * will signal that the command has been completed by raising the DO 322 * signal. If DO does not go high in 10 milliseconds, then error out. */ 323 for(i = 0; i < 200; i++) { 324 eecd_reg = IXGB_READ_REG(hw, EECD); 325 326 if(eecd_reg & IXGB_EECD_DO) 327 return (TRUE); 328 329 usec_delay(50); 330 } 331 ASSERT(0); 332 return (FALSE); 333 } 334 335 /****************************************************************************** 336 * Verifies that the EEPROM has a valid checksum 337 * 338 * hw - Struct containing variables accessed by shared code 339 * 340 * Reads the first 64 16 bit words of the EEPROM and sums the values read. 341 * If the sum of the 64 16 bit words is 0xBABA, the EEPROM's checksum is 342 * valid. 343 * 344 * Returns: 345 * TRUE: Checksum is valid 346 * FALSE: Checksum is not valid. 347 *****************************************************************************/ 348 boolean_t 349 ixgb_validate_eeprom_checksum(struct ixgb_hw *hw) 350 { 351 uint16_t checksum = 0; 352 uint16_t i; 353 354 for(i = 0; i < (EEPROM_CHECKSUM_REG + 1); i++) 355 checksum += ixgb_read_eeprom(hw, i); 356 357 if(checksum == (uint16_t)EEPROM_SUM) 358 return (TRUE); 359 else 360 return (FALSE); 361 } 362 363 /****************************************************************************** 364 * Calculates the EEPROM checksum and writes it to the EEPROM 365 * 366 * hw - Struct containing variables accessed by shared code 367 * 368 * Sums the first 63 16 bit words of the EEPROM. Subtracts the sum from 0xBABA. 369 * Writes the difference to word offset 63 of the EEPROM. 370 *****************************************************************************/ 371 void 372 ixgb_update_eeprom_checksum(struct ixgb_hw *hw) 373 { 374 uint16_t checksum = 0; 375 uint16_t i; 376 377 for(i = 0; i < EEPROM_CHECKSUM_REG; i++) 378 checksum += ixgb_read_eeprom(hw, i); 379 380 checksum = (uint16_t)EEPROM_SUM - checksum; 381 382 ixgb_write_eeprom(hw, EEPROM_CHECKSUM_REG, checksum); 383 return; 384 } 385 386 /****************************************************************************** 387 * Writes a 16 bit word to a given offset in the EEPROM. 388 * 389 * hw - Struct containing variables accessed by shared code 390 * reg - offset within the EEPROM to be written to 391 * data - 16 bit word to be writen to the EEPROM 392 * 393 * If ixgb_update_eeprom_checksum is not called after this function, the 394 * EEPROM will most likely contain an invalid checksum. 395 * 396 *****************************************************************************/ 397 void 398 ixgb_write_eeprom(struct ixgb_hw *hw, uint16_t offset, uint16_t data) 399 { 400 struct ixgb_ee_map_type *ee_map = (struct ixgb_ee_map_type *)hw->eeprom; 401 402 /* Prepare the EEPROM for writing */ 403 ixgb_setup_eeprom(hw); 404 405 /* Send the 9-bit EWEN (write enable) command to the EEPROM (5-bit 406 * opcode plus 4-bit dummy). This puts the EEPROM into write/erase 407 * mode. */ 408 ixgb_shift_out_bits(hw, EEPROM_EWEN_OPCODE, 5); 409 ixgb_shift_out_bits(hw, 0, 4); 410 411 /* Prepare the EEPROM */ 412 ixgb_standby_eeprom(hw); 413 414 /* Send the Write command (3-bit opcode + 6-bit addr) */ 415 ixgb_shift_out_bits(hw, EEPROM_WRITE_OPCODE, 3); 416 ixgb_shift_out_bits(hw, offset, 6); 417 418 /* Send the data */ 419 ixgb_shift_out_bits(hw, data, 16); 420 421 ixgb_wait_eeprom_command(hw); 422 423 /* Recover from write */ 424 ixgb_standby_eeprom(hw); 425 426 /* Send the 9-bit EWDS (write disable) command to the EEPROM (5-bit 427 * opcode plus 4-bit dummy). This takes the EEPROM out of write/erase 428 * mode. */ 429 ixgb_shift_out_bits(hw, EEPROM_EWDS_OPCODE, 5); 430 ixgb_shift_out_bits(hw, 0, 4); 431 432 /* Done with writing */ 433 ixgb_cleanup_eeprom(hw); 434 435 /* clear the init_ctrl_reg_1 to signify that the cache is invalidated */ 436 ee_map->init_ctrl_reg_1 = le16_to_cpu(EEPROM_ICW1_SIGNATURE_CLEAR); 437 438 return; 439 } 440 441 /****************************************************************************** 442 * Reads a 16 bit word from the EEPROM. 443 * 444 * hw - Struct containing variables accessed by shared code 445 * offset - offset of 16 bit word in the EEPROM to read 446 * 447 * Returns: 448 * The 16-bit value read from the eeprom 449 *****************************************************************************/ 450 uint16_t 451 ixgb_read_eeprom(struct ixgb_hw *hw, uint16_t offset) 452 { 453 uint16_t data; 454 455 /* Prepare the EEPROM for reading */ 456 ixgb_setup_eeprom(hw); 457 458 /* Send the READ command (opcode + addr) */ 459 ixgb_shift_out_bits(hw, EEPROM_READ_OPCODE, 3); 460 /* 461 * We have a 64 word EEPROM, there are 6 address bits 462 */ 463 ixgb_shift_out_bits(hw, offset, 6); 464 465 /* Read the data */ 466 data = ixgb_shift_in_bits(hw); 467 468 /* End this read operation */ 469 ixgb_standby_eeprom(hw); 470 471 return (data); 472 } 473 474 /****************************************************************************** 475 * Reads eeprom and stores data in shared structure. 476 * Validates eeprom checksum and eeprom signature. 477 * 478 * hw - Struct containing variables accessed by shared code 479 * 480 * Returns: 481 * TRUE: if eeprom read is successful 482 * FALSE: otherwise. 483 *****************************************************************************/ 484 boolean_t 485 ixgb_get_eeprom_data(struct ixgb_hw *hw) 486 { 487 uint16_t i; 488 uint16_t checksum = 0; 489 struct ixgb_ee_map_type *ee_map; 490 491 DEBUGFUNC("ixgb_get_eeprom_data"); 492 493 ee_map = (struct ixgb_ee_map_type *)hw->eeprom; 494 495 DEBUGOUT("ixgb_ee: Reading eeprom data\n"); 496 for(i = 0; i < IXGB_EEPROM_SIZE; i++) { 497 uint16_t ee_data; 498 499 ee_data = ixgb_read_eeprom(hw, i); 500 checksum += ee_data; 501 hw->eeprom[i] = le16_to_cpu(ee_data); 502 } 503 504 if(checksum != (uint16_t)EEPROM_SUM) { 505 DEBUGOUT("ixgb_ee: Checksum invalid.\n"); 506 /* clear the init_ctrl_reg_1 to signify that the cache is 507 * invalidated */ 508 ee_map->init_ctrl_reg_1 = le16_to_cpu(EEPROM_ICW1_SIGNATURE_CLEAR); 509 return (FALSE); 510 } 511 512 if((ee_map->init_ctrl_reg_1 & le16_to_cpu(EEPROM_ICW1_SIGNATURE_MASK)) 513 != le16_to_cpu(EEPROM_ICW1_SIGNATURE_VALID)) { 514 DEBUGOUT("ixgb_ee: Signature invalid.\n"); 515 return (FALSE); 516 } 517 518 return (TRUE); 519 } 520 521 /****************************************************************************** 522 * Local function to check if the eeprom signature is good 523 * If the eeprom signature is good, calls ixgb)get_eeprom_data. 524 * 525 * hw - Struct containing variables accessed by shared code 526 * 527 * Returns: 528 * TRUE: eeprom signature was good and the eeprom read was successful 529 * FALSE: otherwise. 530 ******************************************************************************/ 531 static boolean_t 532 ixgb_check_and_get_eeprom_data(struct ixgb_hw *hw) 533 { 534 struct ixgb_ee_map_type *ee_map = (struct ixgb_ee_map_type *)hw->eeprom; 535 536 if((ee_map->init_ctrl_reg_1 & le16_to_cpu(EEPROM_ICW1_SIGNATURE_MASK)) 537 == le16_to_cpu(EEPROM_ICW1_SIGNATURE_VALID)) { 538 return (TRUE); 539 } else { 540 return ixgb_get_eeprom_data(hw); 541 } 542 } 543 544 /****************************************************************************** 545 * return a word from the eeprom 546 * 547 * hw - Struct containing variables accessed by shared code 548 * index - Offset of eeprom word 549 * 550 * Returns: 551 * Word at indexed offset in eeprom, if valid, 0 otherwise. 552 ******************************************************************************/ 553 uint16_t 554 ixgb_get_eeprom_word(struct ixgb_hw *hw, uint16_t index) 555 { 556 557 if((index < IXGB_EEPROM_SIZE) && 558 (ixgb_check_and_get_eeprom_data(hw) == TRUE)) { 559 return (hw->eeprom[index]); 560 } 561 562 return (0); 563 } 564 565 /****************************************************************************** 566 * return the mac address from EEPROM 567 * 568 * hw - Struct containing variables accessed by shared code 569 * mac_addr - Ethernet Address if EEPROM contents are valid, 0 otherwise 570 * 571 * Returns: None. 572 ******************************************************************************/ 573 void 574 ixgb_get_ee_mac_addr(struct ixgb_hw *hw, uint8_t *mac_addr) 575 { 576 int i; 577 struct ixgb_ee_map_type *ee_map = (struct ixgb_ee_map_type *)hw->eeprom; 578 579 DEBUGFUNC("ixgb_get_ee_mac_addr"); 580 581 if(ixgb_check_and_get_eeprom_data(hw) == TRUE) { 582 for(i = 0; i < IXGB_ETH_LENGTH_OF_ADDRESS; i++) { 583 mac_addr[i] = ee_map->mac_addr[i]; 584 DEBUGOUT2("mac(%d) = %.2X\n", i, mac_addr[i]); 585 } 586 } 587 } 588 589 590 /****************************************************************************** 591 * return the Printed Board Assembly number from EEPROM 592 * 593 * hw - Struct containing variables accessed by shared code 594 * 595 * Returns: 596 * PBA number if EEPROM contents are valid, 0 otherwise 597 ******************************************************************************/ 598 uint32_t 599 ixgb_get_ee_pba_number(struct ixgb_hw *hw) 600 { 601 if(ixgb_check_and_get_eeprom_data(hw) == TRUE) 602 return (le16_to_cpu(hw->eeprom[EEPROM_PBA_1_2_REG]) 603 | (le16_to_cpu(hw->eeprom[EEPROM_PBA_3_4_REG]) << 16)); 604 605 return (0); 606 } 607 608 609 /****************************************************************************** 610 * return the Device Id from EEPROM 611 * 612 * hw - Struct containing variables accessed by shared code 613 * 614 * Returns: 615 * Device Id if EEPROM contents are valid, 0 otherwise 616 ******************************************************************************/ 617 uint16_t 618 ixgb_get_ee_device_id(struct ixgb_hw *hw) 619 { 620 struct ixgb_ee_map_type *ee_map = (struct ixgb_ee_map_type *)hw->eeprom; 621 622 if(ixgb_check_and_get_eeprom_data(hw) == TRUE) 623 return (le16_to_cpu(ee_map->device_id)); 624 625 return (0); 626 } 627 628