1 /* $OpenBSD: igc_i225.c,v 1.3 2022/05/11 06:14:15 kevlo Exp $ */ 2 /*- 3 * Copyright 2021 Intel Corp 4 * Copyright 2021 Rubicon Communications, LLC (Netgate) 5 * SPDX-License-Identifier: BSD-3-Clause 6 */ 7 8 #include <dev/pci/igc_api.h> 9 10 int igc_init_nvm_params_i225(struct igc_hw *); 11 int igc_init_mac_params_i225(struct igc_hw *); 12 int igc_init_phy_params_i225(struct igc_hw *); 13 int igc_reset_hw_i225(struct igc_hw *); 14 int igc_acquire_nvm_i225(struct igc_hw *); 15 void igc_release_nvm_i225(struct igc_hw *); 16 int igc_get_hw_semaphore_i225(struct igc_hw *); 17 int __igc_write_nvm_srwr(struct igc_hw *, uint16_t, uint16_t, uint16_t *); 18 int igc_pool_flash_update_done_i225(struct igc_hw *); 19 20 /** 21 * igc_init_nvm_params_i225 - Init NVM func ptrs. 22 * @hw: pointer to the HW structure 23 **/ 24 int 25 igc_init_nvm_params_i225(struct igc_hw *hw) 26 { 27 struct igc_nvm_info *nvm = &hw->nvm; 28 uint32_t eecd = IGC_READ_REG(hw, IGC_EECD); 29 uint16_t size; 30 31 DEBUGFUNC("igc_init_nvm_params_i225"); 32 33 size = (uint16_t)((eecd & IGC_EECD_SIZE_EX_MASK) >> 34 IGC_EECD_SIZE_EX_SHIFT); 35 /* 36 * Added to a constant, "size" becomes the left-shift value 37 * for setting word_size. 38 */ 39 size += NVM_WORD_SIZE_BASE_SHIFT; 40 41 /* Just in case size is out of range, cap it to the largest 42 * EEPROM size supported. 43 */ 44 if (size > 15) 45 size = 15; 46 47 nvm->word_size = 1 << size; 48 nvm->opcode_bits = 8; 49 nvm->delay_usec = 1; 50 nvm->type = igc_nvm_eeprom_spi; 51 52 nvm->page_size = eecd & IGC_EECD_ADDR_BITS ? 32 : 8; 53 nvm->address_bits = eecd & IGC_EECD_ADDR_BITS ? 16 : 8; 54 55 if (nvm->word_size == (1 << 15)) 56 nvm->page_size = 128; 57 58 nvm->ops.acquire = igc_acquire_nvm_i225; 59 nvm->ops.release = igc_release_nvm_i225; 60 if (igc_get_flash_presence_i225(hw)) { 61 hw->nvm.type = igc_nvm_flash_hw; 62 nvm->ops.read = igc_read_nvm_srrd_i225; 63 nvm->ops.write = igc_write_nvm_srwr_i225; 64 nvm->ops.validate = igc_validate_nvm_checksum_i225; 65 nvm->ops.update = igc_update_nvm_checksum_i225; 66 } else { 67 hw->nvm.type = igc_nvm_invm; 68 nvm->ops.write = igc_null_write_nvm; 69 nvm->ops.validate = igc_null_ops_generic; 70 nvm->ops.update = igc_null_ops_generic; 71 } 72 73 return IGC_SUCCESS; 74 } 75 76 /** 77 * igc_init_mac_params_i225 - Init MAC func ptrs. 78 * @hw: pointer to the HW structure 79 **/ 80 int 81 igc_init_mac_params_i225(struct igc_hw *hw) 82 { 83 struct igc_mac_info *mac = &hw->mac; 84 struct igc_dev_spec_i225 *dev_spec = &hw->dev_spec._i225; 85 86 DEBUGFUNC("igc_init_mac_params_i225"); 87 88 /* Initialize function pointer */ 89 igc_init_mac_ops_generic(hw); 90 91 /* Set media type */ 92 hw->phy.media_type = igc_media_type_copper; 93 /* Set mta register count */ 94 mac->mta_reg_count = 128; 95 /* Set rar entry count */ 96 mac->rar_entry_count = IGC_RAR_ENTRIES_BASE; 97 98 /* reset */ 99 mac->ops.reset_hw = igc_reset_hw_i225; 100 /* hw initialization */ 101 mac->ops.init_hw = igc_init_hw_i225; 102 /* link setup */ 103 mac->ops.setup_link = igc_setup_link_generic; 104 /* check for link */ 105 mac->ops.check_for_link = igc_check_for_link_i225; 106 /* link info */ 107 mac->ops.get_link_up_info = igc_get_speed_and_duplex_copper_generic; 108 /* acquire SW_FW sync */ 109 mac->ops.acquire_swfw_sync = igc_acquire_swfw_sync_i225; 110 /* release SW_FW sync */ 111 mac->ops.release_swfw_sync = igc_release_swfw_sync_i225; 112 113 /* Allow a single clear of the SW semaphore on I225 */ 114 dev_spec->clear_semaphore_once = true; 115 mac->ops.setup_physical_interface = igc_setup_copper_link_i225; 116 117 /* Set if part includes ASF firmware */ 118 mac->asf_firmware_present = true; 119 120 /* multicast address update */ 121 mac->ops.update_mc_addr_list = igc_update_mc_addr_list_generic; 122 123 mac->ops.write_vfta = igc_write_vfta_generic; 124 125 return IGC_SUCCESS; 126 } 127 128 /** 129 * igc_init_phy_params_i225 - Init PHY func ptrs. 130 * @hw: pointer to the HW structure 131 **/ 132 int 133 igc_init_phy_params_i225(struct igc_hw *hw) 134 { 135 struct igc_phy_info *phy = &hw->phy; 136 int ret_val = IGC_SUCCESS; 137 138 DEBUGFUNC("igc_init_phy_params_i225"); 139 140 if (hw->phy.media_type != igc_media_type_copper) { 141 phy->type = igc_phy_none; 142 goto out; 143 } 144 145 phy->ops.power_up = igc_power_up_phy_copper; 146 phy->ops.power_down = igc_power_down_phy_copper_base; 147 phy->autoneg_mask = AUTONEG_ADVERTISE_SPEED_DEFAULT_2500; 148 phy->reset_delay_us = 100; 149 phy->ops.acquire = igc_acquire_phy_base; 150 phy->ops.check_reset_block = igc_check_reset_block_generic; 151 phy->ops.release = igc_release_phy_base; 152 phy->ops.reset = igc_phy_hw_reset_generic; 153 phy->ops.read_reg = igc_read_phy_reg_gpy; 154 phy->ops.write_reg = igc_write_phy_reg_gpy; 155 156 /* Make sure the PHY is in a good state. Several people have reported 157 * firmware leaving the PHY's page select register set to something 158 * other than the default of zero, which causes the PHY ID read to 159 * access something other than the intended register. 160 */ 161 ret_val = hw->phy.ops.reset(hw); 162 if (ret_val) 163 goto out; 164 165 ret_val = igc_get_phy_id(hw); 166 /* Verify phy id and set remaining function pointers */ 167 switch (phy->id) { 168 case I225_I_PHY_ID: 169 default: 170 phy->type = igc_phy_i225; 171 phy->ops.set_d0_lplu_state = igc_set_d0_lplu_state_i225; 172 phy->ops.set_d3_lplu_state = igc_set_d3_lplu_state_i225; 173 /* TODO - complete with GPY PHY information */ 174 break; 175 } 176 177 out: 178 return ret_val; 179 } 180 181 /** 182 * igc_reset_hw_i225 - Reset hardware 183 * @hw: pointer to the HW structure 184 * 185 * This resets the hardware into a known state. 186 **/ 187 int 188 igc_reset_hw_i225(struct igc_hw *hw) 189 { 190 uint32_t ctrl; 191 int ret_val; 192 193 DEBUGFUNC("igc_reset_hw_i225"); 194 195 /* 196 * Prevent the PCI-E bus from sticking if there is no TLP connection 197 * on the last TLP read/write transaction when MAC is reset. 198 */ 199 ret_val = igc_disable_pcie_master_generic(hw); 200 if (ret_val) 201 DEBUGOUT("PCI-E Master disable polling has failed.\n"); 202 203 DEBUGOUT("Masking off all interrupts\n"); 204 IGC_WRITE_REG(hw, IGC_IMC, 0xffffffff); 205 206 IGC_WRITE_REG(hw, IGC_RCTL, 0); 207 IGC_WRITE_REG(hw, IGC_TCTL, IGC_TCTL_PSP); 208 IGC_WRITE_FLUSH(hw); 209 210 msec_delay(10); 211 212 ctrl = IGC_READ_REG(hw, IGC_CTRL); 213 214 DEBUGOUT("Issuing a global reset to MAC\n"); 215 IGC_WRITE_REG(hw, IGC_CTRL, ctrl | IGC_CTRL_DEV_RST); 216 217 ret_val = igc_get_auto_rd_done_generic(hw); 218 if (ret_val) { 219 /* 220 * When auto config read does not complete, do not 221 * return with an error. This can happen in situations 222 * where there is no eeprom and prevents getting link. 223 */ 224 DEBUGOUT("Auto Read Done did not complete\n"); 225 } 226 227 /* Clear any pending interrupt events. */ 228 IGC_WRITE_REG(hw, IGC_IMC, 0xffffffff); 229 IGC_READ_REG(hw, IGC_ICR); 230 231 /* Install any alternate MAC address into RAR0 */ 232 ret_val = igc_check_alt_mac_addr_generic(hw); 233 234 return ret_val; 235 } 236 237 /* igc_acquire_nvm_i225 - Request for access to EEPROM 238 * @hw: pointer to the HW structure 239 * 240 * Acquire the necessary semaphores for exclusive access to the EEPROM. 241 * Set the EEPROM access request bit and wait for EEPROM access grant bit. 242 * Return successful if access grant bit set, else clear the request for 243 * EEPROM access and return -IGC_ERR_NVM (-1). 244 */ 245 int 246 igc_acquire_nvm_i225(struct igc_hw *hw) 247 { 248 int ret_val; 249 250 DEBUGFUNC("igc_acquire_nvm_i225"); 251 252 ret_val = igc_acquire_swfw_sync_i225(hw, IGC_SWFW_EEP_SM); 253 254 return ret_val; 255 } 256 257 /* igc_release_nvm_i225 - Release exclusive access to EEPROM 258 * @hw: pointer to the HW structure 259 * 260 * Stop any current commands to the EEPROM and clear the EEPROM request bit, 261 * then release the semaphores acquired. 262 */ 263 void 264 igc_release_nvm_i225(struct igc_hw *hw) 265 { 266 DEBUGFUNC("igc_release_nvm_i225"); 267 268 igc_release_swfw_sync_i225(hw, IGC_SWFW_EEP_SM); 269 } 270 271 /* igc_acquire_swfw_sync_i225 - Acquire SW/FW semaphore 272 * @hw: pointer to the HW structure 273 * @mask: specifies which semaphore to acquire 274 * 275 * Acquire the SW/FW semaphore to access the PHY or NVM. The mask 276 * will also specify which port we're acquiring the lock for. 277 */ 278 int 279 igc_acquire_swfw_sync_i225(struct igc_hw *hw, uint16_t mask) 280 { 281 uint32_t swfw_sync; 282 uint32_t swmask = mask; 283 uint32_t fwmask = mask << 16; 284 int ret_val = IGC_SUCCESS; 285 int i = 0, timeout = 200; /* FIXME: find real value to use here */ 286 287 DEBUGFUNC("igc_acquire_swfw_sync_i225"); 288 289 while (i < timeout) { 290 if (igc_get_hw_semaphore_i225(hw)) { 291 ret_val = -IGC_ERR_SWFW_SYNC; 292 goto out; 293 } 294 295 swfw_sync = IGC_READ_REG(hw, IGC_SW_FW_SYNC); 296 if (!(swfw_sync & (fwmask | swmask))) 297 break; 298 299 /* Firmware currently using resource (fwmask) 300 * or other software thread using resource (swmask) 301 */ 302 igc_put_hw_semaphore_generic(hw); 303 msec_delay(5); 304 i++; 305 } 306 307 if (i == timeout) { 308 DEBUGOUT("Driver can't access resource, SW_FW_SYNC timeout.\n"); 309 ret_val = -IGC_ERR_SWFW_SYNC; 310 goto out; 311 } 312 313 swfw_sync |= swmask; 314 IGC_WRITE_REG(hw, IGC_SW_FW_SYNC, swfw_sync); 315 316 igc_put_hw_semaphore_generic(hw); 317 318 out: 319 return ret_val; 320 } 321 322 /* igc_release_swfw_sync_i225 - Release SW/FW semaphore 323 * @hw: pointer to the HW structure 324 * @mask: specifies which semaphore to acquire 325 * 326 * Release the SW/FW semaphore used to access the PHY or NVM. The mask 327 * will also specify which port we're releasing the lock for. 328 */ 329 void 330 igc_release_swfw_sync_i225(struct igc_hw *hw, uint16_t mask) 331 { 332 uint32_t swfw_sync; 333 334 DEBUGFUNC("igc_release_swfw_sync_i225"); 335 336 while (igc_get_hw_semaphore_i225(hw) != IGC_SUCCESS) 337 ; /* Empty */ 338 339 swfw_sync = IGC_READ_REG(hw, IGC_SW_FW_SYNC); 340 swfw_sync &= ~mask; 341 IGC_WRITE_REG(hw, IGC_SW_FW_SYNC, swfw_sync); 342 343 igc_put_hw_semaphore_generic(hw); 344 } 345 346 /* 347 * igc_setup_copper_link_i225 - Configure copper link settings 348 * @hw: pointer to the HW structure 349 * 350 * Configures the link for auto-neg or forced speed and duplex. Then we check 351 * for link, once link is established calls to configure collision distance 352 * and flow control are called. 353 */ 354 int 355 igc_setup_copper_link_i225(struct igc_hw *hw) 356 { 357 uint32_t ctrl, phpm_reg; 358 int ret_val; 359 360 DEBUGFUNC("igc_setup_copper_link_i225"); 361 362 ctrl = IGC_READ_REG(hw, IGC_CTRL); 363 ctrl |= IGC_CTRL_SLU; 364 ctrl &= ~(IGC_CTRL_FRCSPD | IGC_CTRL_FRCDPX); 365 IGC_WRITE_REG(hw, IGC_CTRL, ctrl); 366 367 phpm_reg = IGC_READ_REG(hw, IGC_I225_PHPM); 368 phpm_reg &= ~IGC_I225_PHPM_GO_LINKD; 369 IGC_WRITE_REG(hw, IGC_I225_PHPM, phpm_reg); 370 371 ret_val = igc_setup_copper_link_generic(hw); 372 373 return ret_val; 374 } 375 376 /* igc_get_hw_semaphore_i225 - Acquire hardware semaphore 377 * @hw: pointer to the HW structure 378 * 379 * Acquire the HW semaphore to access the PHY or NVM 380 */ 381 int 382 igc_get_hw_semaphore_i225(struct igc_hw *hw) 383 { 384 uint32_t swsm; 385 int timeout = hw->nvm.word_size + 1; 386 int i = 0; 387 388 DEBUGFUNC("igc_get_hw_semaphore_i225"); 389 390 /* Get the SW semaphore */ 391 while (i < timeout) { 392 swsm = IGC_READ_REG(hw, IGC_SWSM); 393 if (!(swsm & IGC_SWSM_SMBI)) 394 break; 395 396 DELAY(50); 397 i++; 398 } 399 400 if (i == timeout) { 401 /* In rare circumstances, the SW semaphore may already be held 402 * unintentionally. Clear the semaphore once before giving up. 403 */ 404 if (hw->dev_spec._i225.clear_semaphore_once) { 405 hw->dev_spec._i225.clear_semaphore_once = false; 406 igc_put_hw_semaphore_generic(hw); 407 for (i = 0; i < timeout; i++) { 408 swsm = IGC_READ_REG(hw, IGC_SWSM); 409 if (!(swsm & IGC_SWSM_SMBI)) 410 break; 411 412 DELAY(50); 413 } 414 } 415 416 /* If we do not have the semaphore here, we have to give up. */ 417 if (i == timeout) { 418 DEBUGOUT("Driver can't access device -\n"); 419 DEBUGOUT("SMBI bit is set.\n"); 420 return -IGC_ERR_NVM; 421 } 422 } 423 424 /* Get the FW semaphore. */ 425 for (i = 0; i < timeout; i++) { 426 swsm = IGC_READ_REG(hw, IGC_SWSM); 427 IGC_WRITE_REG(hw, IGC_SWSM, swsm | IGC_SWSM_SWESMBI); 428 429 /* Semaphore acquired if bit latched */ 430 if (IGC_READ_REG(hw, IGC_SWSM) & IGC_SWSM_SWESMBI) 431 break; 432 433 DELAY(50); 434 } 435 436 if (i == timeout) { 437 /* Release semaphores */ 438 igc_put_hw_semaphore_generic(hw); 439 DEBUGOUT("Driver can't access the NVM\n"); 440 return -IGC_ERR_NVM; 441 } 442 443 return IGC_SUCCESS; 444 } 445 446 /* igc_read_nvm_srrd_i225 - Reads Shadow Ram using EERD register 447 * @hw: pointer to the HW structure 448 * @offset: offset of word in the Shadow Ram to read 449 * @words: number of words to read 450 * @data: word read from the Shadow Ram 451 * 452 * Reads a 16 bit word from the Shadow Ram using the EERD register. 453 * Uses necessary synchronization semaphores. 454 */ 455 int 456 igc_read_nvm_srrd_i225(struct igc_hw *hw, uint16_t offset, uint16_t words, 457 uint16_t *data) 458 { 459 uint16_t i, count; 460 int status = IGC_SUCCESS; 461 462 DEBUGFUNC("igc_read_nvm_srrd_i225"); 463 464 /* We cannot hold synchronization semaphores for too long, 465 * because of forceful takeover procedure. However it is more efficient 466 * to read in bursts than synchronizing access for each word. 467 */ 468 for (i = 0; i < words; i += IGC_EERD_EEWR_MAX_COUNT) { 469 count = (words - i) / IGC_EERD_EEWR_MAX_COUNT > 0 ? 470 IGC_EERD_EEWR_MAX_COUNT : (words - i); 471 if (hw->nvm.ops.acquire(hw) == IGC_SUCCESS) { 472 status = igc_read_nvm_eerd(hw, offset, count, data + i); 473 hw->nvm.ops.release(hw); 474 } else { 475 status = IGC_ERR_SWFW_SYNC; 476 } 477 478 if (status != IGC_SUCCESS) 479 break; 480 } 481 482 return status; 483 } 484 485 /* igc_write_nvm_srwr_i225 - Write to Shadow RAM using EEWR 486 * @hw: pointer to the HW structure 487 * @offset: offset within the Shadow RAM to be written to 488 * @words: number of words to write 489 * @data: 16 bit word(s) to be written to the Shadow RAM 490 * 491 * Writes data to Shadow RAM at offset using EEWR register. 492 * 493 * If igc_update_nvm_checksum is not called after this function , the 494 * data will not be committed to FLASH and also Shadow RAM will most likely 495 * contain an invalid checksum. 496 * 497 * If error code is returned, data and Shadow RAM may be inconsistent - buffer 498 * partially written. 499 */ 500 int 501 igc_write_nvm_srwr_i225(struct igc_hw *hw, uint16_t offset, uint16_t words, 502 uint16_t *data) 503 { 504 uint16_t i, count; 505 int status = IGC_SUCCESS; 506 507 DEBUGFUNC("igc_write_nvm_srwr_i225"); 508 509 /* We cannot hold synchronization semaphores for too long, 510 * because of forceful takeover procedure. However it is more efficient 511 * to write in bursts than synchronizing access for each word. 512 */ 513 for (i = 0; i < words; i += IGC_EERD_EEWR_MAX_COUNT) { 514 count = (words - i) / IGC_EERD_EEWR_MAX_COUNT > 0 ? 515 IGC_EERD_EEWR_MAX_COUNT : (words - i); 516 if (hw->nvm.ops.acquire(hw) == IGC_SUCCESS) { 517 status = __igc_write_nvm_srwr(hw, offset, count, 518 data + i); 519 hw->nvm.ops.release(hw); 520 } else 521 status = IGC_ERR_SWFW_SYNC; 522 523 if (status != IGC_SUCCESS) 524 break; 525 } 526 527 return status; 528 } 529 530 /* __igc_write_nvm_srwr - Write to Shadow Ram using EEWR 531 * @hw: pointer to the HW structure 532 * @offset: offset within the Shadow Ram to be written to 533 * @words: number of words to write 534 * @data: 16 bit word(s) to be written to the Shadow Ram 535 * 536 * Writes data to Shadow Ram at offset using EEWR register. 537 * 538 * If igc_update_nvm_checksum is not called after this function , the 539 * Shadow Ram will most likely contain an invalid checksum. 540 */ 541 int 542 __igc_write_nvm_srwr(struct igc_hw *hw, uint16_t offset, uint16_t words, 543 uint16_t *data) 544 { 545 struct igc_nvm_info *nvm = &hw->nvm; 546 uint32_t i, k, eewr = 0; 547 uint32_t attempts = 100000; 548 int ret_val = IGC_SUCCESS; 549 550 DEBUGFUNC("__igc_write_nvm_srwr"); 551 552 /* A check for invalid values: offset too large, too many words, 553 * too many words for the offset, and not enough words. 554 */ 555 if ((offset >= nvm->word_size) || (words > (nvm->word_size - offset)) || 556 (words == 0)) { 557 DEBUGOUT("nvm parameter(s) out of bounds\n"); 558 ret_val = -IGC_ERR_NVM; 559 goto out; 560 } 561 562 for (i = 0; i < words; i++) { 563 eewr = ((offset + i) << IGC_NVM_RW_ADDR_SHIFT) | 564 (data[i] << IGC_NVM_RW_REG_DATA) | IGC_NVM_RW_REG_START; 565 566 IGC_WRITE_REG(hw, IGC_SRWR, eewr); 567 568 for (k = 0; k < attempts; k++) { 569 if (IGC_NVM_RW_REG_DONE & IGC_READ_REG(hw, IGC_SRWR)) { 570 ret_val = IGC_SUCCESS; 571 break; 572 } 573 DELAY(5); 574 } 575 576 if (ret_val != IGC_SUCCESS) { 577 DEBUGOUT("Shadow RAM write EEWR timed out\n"); 578 break; 579 } 580 } 581 582 out: 583 return ret_val; 584 } 585 586 /* igc_validate_nvm_checksum_i225 - Validate EEPROM checksum 587 * @hw: pointer to the HW structure 588 * 589 * Calculates the EEPROM checksum by reading/adding each word of the EEPROM 590 * and then verifies that the sum of the EEPROM is equal to 0xBABA. 591 */ 592 int 593 igc_validate_nvm_checksum_i225(struct igc_hw *hw) 594 { 595 int status = IGC_SUCCESS; 596 int (*read_op_ptr)(struct igc_hw *, uint16_t, uint16_t, uint16_t *); 597 598 DEBUGFUNC("igc_validate_nvm_checksum_i225"); 599 600 if (hw->nvm.ops.acquire(hw) == IGC_SUCCESS) { 601 /* Replace the read function with semaphore grabbing with 602 * the one that skips this for a while. 603 * We have semaphore taken already here. 604 */ 605 read_op_ptr = hw->nvm.ops.read; 606 hw->nvm.ops.read = igc_read_nvm_eerd; 607 608 status = igc_validate_nvm_checksum_generic(hw); 609 610 /* Revert original read operation. */ 611 hw->nvm.ops.read = read_op_ptr; 612 613 hw->nvm.ops.release(hw); 614 } else { 615 status = IGC_ERR_SWFW_SYNC; 616 } 617 618 return status; 619 } 620 621 /* igc_update_nvm_checksum_i225 - Update EEPROM checksum 622 * @hw: pointer to the HW structure 623 * 624 * Updates the EEPROM checksum by reading/adding each word of the EEPROM 625 * up to the checksum. Then calculates the EEPROM checksum and writes the 626 * value to the EEPROM. Next commit EEPROM data onto the Flash. 627 */ 628 int 629 igc_update_nvm_checksum_i225(struct igc_hw *hw) 630 { 631 uint16_t checksum = 0; 632 uint16_t i, nvm_data; 633 int ret_val; 634 635 DEBUGFUNC("igc_update_nvm_checksum_i225"); 636 637 /* Read the first word from the EEPROM. If this times out or fails, do 638 * not continue or we could be in for a very long wait while every 639 * EEPROM read fails 640 */ 641 ret_val = igc_read_nvm_eerd(hw, 0, 1, &nvm_data); 642 if (ret_val != IGC_SUCCESS) { 643 DEBUGOUT("EEPROM read failed\n"); 644 goto out; 645 } 646 647 if (hw->nvm.ops.acquire(hw) == IGC_SUCCESS) { 648 /* Do not use hw->nvm.ops.write, hw->nvm.ops.read 649 * because we do not want to take the synchronization 650 * semaphores twice here. 651 */ 652 653 for (i = 0; i < NVM_CHECKSUM_REG; i++) { 654 ret_val = igc_read_nvm_eerd(hw, i, 1, &nvm_data); 655 if (ret_val) { 656 hw->nvm.ops.release(hw); 657 DEBUGOUT("NVM Read Error while updating\n"); 658 DEBUGOUT("checksum.\n"); 659 goto out; 660 } 661 checksum += nvm_data; 662 } 663 checksum = (uint16_t)NVM_SUM - checksum; 664 ret_val = __igc_write_nvm_srwr(hw, NVM_CHECKSUM_REG, 1, 665 &checksum); 666 if (ret_val != IGC_SUCCESS) { 667 hw->nvm.ops.release(hw); 668 DEBUGOUT("NVM Write Error while updating checksum.\n"); 669 goto out; 670 } 671 672 hw->nvm.ops.release(hw); 673 674 ret_val = igc_update_flash_i225(hw); 675 } else { 676 ret_val = IGC_ERR_SWFW_SYNC; 677 } 678 out: 679 return ret_val; 680 } 681 682 /* igc_get_flash_presence_i225 - Check if flash device is detected. 683 * @hw: pointer to the HW structure 684 */ 685 bool 686 igc_get_flash_presence_i225(struct igc_hw *hw) 687 { 688 uint32_t eec = 0; 689 bool ret_val = false; 690 691 DEBUGFUNC("igc_get_flash_presence_i225"); 692 693 eec = IGC_READ_REG(hw, IGC_EECD); 694 695 if (eec & IGC_EECD_FLASH_DETECTED_I225) 696 ret_val = true; 697 698 return ret_val; 699 } 700 701 /* igc_set_flsw_flash_burst_counter_i225 - sets FLSW NVM Burst 702 * Counter in FLSWCNT register. 703 * 704 * @hw: pointer to the HW structure 705 * @burst_counter: size in bytes of the Flash burst to read or write 706 */ 707 int 708 igc_set_flsw_flash_burst_counter_i225(struct igc_hw *hw, uint32_t burst_counter) 709 { 710 int ret_val = IGC_SUCCESS; 711 712 DEBUGFUNC("igc_set_flsw_flash_burst_counter_i225"); 713 714 /* Validate input data */ 715 if (burst_counter < IGC_I225_SHADOW_RAM_SIZE) { 716 /* Write FLSWCNT - burst counter */ 717 IGC_WRITE_REG(hw, IGC_I225_FLSWCNT, burst_counter); 718 } else { 719 ret_val = IGC_ERR_INVALID_ARGUMENT; 720 } 721 722 return ret_val; 723 } 724 725 726 /* igc_write_erase_flash_command_i225 - write/erase to a sector 727 * region on a given address. 728 * 729 * @hw: pointer to the HW structure 730 * @opcode: opcode to be used for the write command 731 * @address: the offset to write into the FLASH image 732 */ 733 int 734 igc_write_erase_flash_command_i225(struct igc_hw *hw, uint32_t opcode, 735 uint32_t address) 736 { 737 uint32_t flswctl = 0; 738 int timeout = IGC_NVM_GRANT_ATTEMPTS; 739 int ret_val = IGC_SUCCESS; 740 741 DEBUGFUNC("igc_write_erase_flash_command_i225"); 742 743 flswctl = IGC_READ_REG(hw, IGC_I225_FLSWCTL); 744 /* Polling done bit on FLSWCTL register */ 745 while (timeout) { 746 if (flswctl & IGC_FLSWCTL_DONE) 747 break; 748 DELAY(5); 749 flswctl = IGC_READ_REG(hw, IGC_I225_FLSWCTL); 750 timeout--; 751 } 752 753 if (!timeout) { 754 DEBUGOUT("Flash transaction was not done\n"); 755 return -IGC_ERR_NVM; 756 } 757 758 /* Build and issue command on FLSWCTL register */ 759 flswctl = address | opcode; 760 IGC_WRITE_REG(hw, IGC_I225_FLSWCTL, flswctl); 761 762 /* Check if issued command is valid on FLSWCTL register */ 763 flswctl = IGC_READ_REG(hw, IGC_I225_FLSWCTL); 764 if (!(flswctl & IGC_FLSWCTL_CMDV)) { 765 DEBUGOUT("Write flash command failed\n"); 766 ret_val = IGC_ERR_INVALID_ARGUMENT; 767 } 768 769 return ret_val; 770 } 771 772 /* igc_update_flash_i225 - Commit EEPROM to the flash 773 * if fw_valid_bit is set, FW is active. setting FLUPD bit in EEC 774 * register makes the FW load the internal shadow RAM into the flash. 775 * Otherwise, fw_valid_bit is 0. if FL_SECU.block_prtotected_sw = 0 776 * then FW is not active so the SW is responsible shadow RAM dump. 777 * 778 * @hw: pointer to the HW structure 779 */ 780 int 781 igc_update_flash_i225(struct igc_hw *hw) 782 { 783 uint32_t block_sw_protect = 1; 784 uint32_t i, flup, fw_valid_bit; 785 uint16_t current_offset; 786 uint16_t base_address = 0x0; 787 uint16_t current_offset_data = 0; 788 int ret_val = 0; 789 790 DEBUGFUNC("igc_update_flash_i225"); 791 792 block_sw_protect = IGC_READ_REG(hw, IGC_I225_FLSECU) & 793 IGC_FLSECU_BLK_SW_ACCESS_I225; 794 795 fw_valid_bit = IGC_READ_REG(hw, IGC_FWSM) & IGC_FWSM_FW_VALID_I225; 796 if (fw_valid_bit) { 797 ret_val = igc_pool_flash_update_done_i225(hw); 798 if (ret_val == -IGC_ERR_NVM) { 799 DEBUGOUT("Flash update time out\n"); 800 goto out; 801 } 802 803 flup = IGC_READ_REG(hw, IGC_EECD) | IGC_EECD_FLUPD_I225; 804 IGC_WRITE_REG(hw, IGC_EECD, flup); 805 806 ret_val = igc_pool_flash_update_done_i225(hw); 807 if (ret_val == IGC_SUCCESS) 808 DEBUGOUT("Flash update complete\n"); 809 else 810 DEBUGOUT("Flash update time out\n"); 811 } else if (!block_sw_protect) { 812 /* FW is not active and security protection is disabled. 813 * therefore, SW is in charge of shadow RAM dump. 814 * Check which sector is valid. if sector 0 is valid, 815 * base address remains 0x0. otherwise, sector 1 is 816 * valid and its base address is 0x1000 817 */ 818 if (IGC_READ_REG(hw, IGC_EECD) & IGC_EECD_SEC1VAL_I225) 819 base_address = 0x1000; 820 821 /* Valid sector erase */ 822 ret_val = igc_write_erase_flash_command_i225(hw, 823 IGC_I225_ERASE_CMD_OPCODE, base_address); 824 if (!ret_val) { 825 DEBUGOUT("Sector erase failed\n"); 826 goto out; 827 } 828 829 current_offset = base_address; 830 831 /* Write */ 832 for (i = 0; i < IGC_I225_SHADOW_RAM_SIZE / 2; i++) { 833 /* Set burst write length */ 834 ret_val = igc_set_flsw_flash_burst_counter_i225(hw, 835 0x2); 836 if (ret_val != IGC_SUCCESS) 837 break; 838 839 /* Set address and opcode */ 840 ret_val = igc_write_erase_flash_command_i225(hw, 841 IGC_I225_WRITE_CMD_OPCODE, 2 * current_offset); 842 if (ret_val != IGC_SUCCESS) 843 break; 844 845 ret_val = igc_read_nvm_eerd(hw, current_offset, 1, 846 ¤t_offset_data); 847 if (ret_val) { 848 DEBUGOUT("Failed to read from EEPROM\n"); 849 goto out; 850 } 851 852 /* Write CurrentOffseData to FLSWDATA register */ 853 IGC_WRITE_REG(hw, IGC_I225_FLSWDATA, 854 current_offset_data); 855 current_offset++; 856 857 /* Wait till operation has finished */ 858 ret_val = igc_poll_eerd_eewr_done(hw, 859 IGC_NVM_POLL_READ); 860 if (ret_val) 861 break; 862 863 DELAY(1000); 864 } 865 } 866 out: 867 return ret_val; 868 } 869 870 /* igc_pool_flash_update_done_i225 - Pool FLUDONE status. 871 * @hw: pointer to the HW structure 872 */ 873 int 874 igc_pool_flash_update_done_i225(struct igc_hw *hw) 875 { 876 uint32_t i, reg; 877 int ret_val = -IGC_ERR_NVM; 878 879 DEBUGFUNC("igc_pool_flash_update_done_i225"); 880 881 for (i = 0; i < IGC_FLUDONE_ATTEMPTS; i++) { 882 reg = IGC_READ_REG(hw, IGC_EECD); 883 if (reg & IGC_EECD_FLUDONE_I225) { 884 ret_val = IGC_SUCCESS; 885 break; 886 } 887 DELAY(5); 888 } 889 890 return ret_val; 891 } 892 893 /* igc_set_ltr_i225 - Set Latency Tolerance Reporting thresholds. 894 * @hw: pointer to the HW structure 895 * @link: bool indicating link status 896 * 897 * Set the LTR thresholds based on the link speed (Mbps), EEE, and DMAC 898 * settings, otherwise specify that there is no LTR requirement. 899 */ 900 int 901 igc_set_ltr_i225(struct igc_hw *hw, bool link) 902 { 903 uint16_t speed, duplex; 904 uint32_t tw_system, ltrc, ltrv, ltr_min, ltr_max, scale_min, scale_max; 905 int size; 906 907 DEBUGFUNC("igc_set_ltr_i225"); 908 909 /* If we do not have link, LTR thresholds are zero. */ 910 if (link) { 911 hw->mac.ops.get_link_up_info(hw, &speed, &duplex); 912 913 /* Check if using copper interface with EEE enabled or if the 914 * link speed is 10 Mbps. 915 */ 916 if ((hw->phy.media_type == igc_media_type_copper) && 917 !(hw->dev_spec._i225.eee_disable) && 918 (speed != SPEED_10)) { 919 /* EEE enabled, so send LTRMAX threshold. */ 920 ltrc = IGC_READ_REG(hw, IGC_LTRC) | IGC_LTRC_EEEMS_EN; 921 IGC_WRITE_REG(hw, IGC_LTRC, ltrc); 922 923 /* Calculate tw_system (nsec). */ 924 if (speed == SPEED_100) { 925 tw_system = ((IGC_READ_REG(hw, IGC_EEE_SU) & 926 IGC_TW_SYSTEM_100_MASK) >> 927 IGC_TW_SYSTEM_100_SHIFT) * 500; 928 } else { 929 tw_system = (IGC_READ_REG(hw, IGC_EEE_SU) & 930 IGC_TW_SYSTEM_1000_MASK) * 500; 931 } 932 } else { 933 tw_system = 0; 934 } 935 936 /* Get the Rx packet buffer size. */ 937 size = IGC_READ_REG(hw, IGC_RXPBS) & IGC_RXPBS_SIZE_I225_MASK; 938 939 /* Calculations vary based on DMAC settings. */ 940 if (IGC_READ_REG(hw, IGC_DMACR) & IGC_DMACR_DMAC_EN) { 941 size -= (IGC_READ_REG(hw, IGC_DMACR) & 942 IGC_DMACR_DMACTHR_MASK) >> IGC_DMACR_DMACTHR_SHIFT; 943 /* Convert size to bits. */ 944 size *= 1024 * 8; 945 } else { 946 /* Convert size to bytes, subtract the MTU, and then 947 * convert the size to bits. 948 */ 949 size *= 1024; 950 size -= hw->dev_spec._i225.mtu; 951 size *= 8; 952 } 953 954 if (size < 0) { 955 DEBUGOUT1("Invalid effective Rx buffer size %d\n", 956 size); 957 return -IGC_ERR_CONFIG; 958 } 959 960 /* Calculate the thresholds. Since speed is in Mbps, simplify 961 * the calculation by multiplying size/speed by 1000 for result 962 * to be in nsec before dividing by the scale in nsec. Set the 963 * scale such that the LTR threshold fits in the register. 964 */ 965 ltr_min = (1000 * size) / speed; 966 ltr_max = ltr_min + tw_system; 967 scale_min = (ltr_min / 1024) < 1024 ? IGC_LTRMINV_SCALE_1024 : 968 IGC_LTRMINV_SCALE_32768; 969 scale_max = (ltr_max / 1024) < 1024 ? IGC_LTRMAXV_SCALE_1024 : 970 IGC_LTRMAXV_SCALE_32768; 971 ltr_min /= scale_min == IGC_LTRMINV_SCALE_1024 ? 1024 : 32768; 972 ltr_max /= scale_max == IGC_LTRMAXV_SCALE_1024 ? 1024 : 32768; 973 974 /* Only write the LTR thresholds if they differ from before. */ 975 ltrv = IGC_READ_REG(hw, IGC_LTRMINV); 976 if (ltr_min != (ltrv & IGC_LTRMINV_LTRV_MASK)) { 977 ltrv = IGC_LTRMINV_LSNP_REQ | ltr_min | 978 (scale_min << IGC_LTRMINV_SCALE_SHIFT); 979 IGC_WRITE_REG(hw, IGC_LTRMINV, ltrv); 980 } 981 982 ltrv = IGC_READ_REG(hw, IGC_LTRMAXV); 983 if (ltr_max != (ltrv & IGC_LTRMAXV_LTRV_MASK)) { 984 ltrv = IGC_LTRMAXV_LSNP_REQ | ltr_max | 985 (scale_min << IGC_LTRMAXV_SCALE_SHIFT); 986 IGC_WRITE_REG(hw, IGC_LTRMAXV, ltrv); 987 } 988 } 989 990 return IGC_SUCCESS; 991 } 992 993 /* igc_check_for_link_i225 - Check for link 994 * @hw: pointer to the HW structure 995 * 996 * Checks to see of the link status of the hardware has changed. If a 997 * change in link status has been detected, then we read the PHY registers 998 * to get the current speed/duplex if link exists. 999 */ 1000 int 1001 igc_check_for_link_i225(struct igc_hw *hw) 1002 { 1003 struct igc_mac_info *mac = &hw->mac; 1004 int ret_val; 1005 bool link = false; 1006 1007 DEBUGFUNC("igc_check_for_link_i225"); 1008 1009 /* We only want to go out to the PHY registers to see if 1010 * Auto-Neg has completed and/or if our link status has 1011 * changed. The get_link_status flag is set upon receiving 1012 * a Link Status Change or Rx Sequence Error interrupt. 1013 */ 1014 if (!mac->get_link_status) { 1015 ret_val = IGC_SUCCESS; 1016 goto out; 1017 } 1018 1019 /* First we want to see if the MII Status Register reports 1020 * link. If so, then we want to get the current speed/duplex 1021 * of the PHY. 1022 */ 1023 ret_val = igc_phy_has_link_generic(hw, 1, 0, &link); 1024 if (ret_val) 1025 goto out; 1026 1027 if (!link) 1028 goto out; /* No link detected */ 1029 1030 /* First we want to see if the MII Status Register reports 1031 * link. If so, then we want to get the current speed/duplex 1032 * of the PHY. 1033 */ 1034 ret_val = igc_phy_has_link_generic(hw, 1, 0, &link); 1035 if (ret_val) 1036 goto out; 1037 1038 if (!link) 1039 goto out; /* No link detected */ 1040 1041 mac->get_link_status = false; 1042 1043 /* Check if there was DownShift, must be checked 1044 * immediately after link-up 1045 */ 1046 igc_check_downshift_generic(hw); 1047 1048 /* If we are forcing speed/duplex, then we simply return since 1049 * we have already determined whether we have link or not. 1050 */ 1051 if (!mac->autoneg) 1052 goto out; 1053 1054 /* Auto-Neg is enabled. Auto Speed Detection takes care 1055 * of MAC speed/duplex configuration. So we only need to 1056 * configure Collision Distance in the MAC. 1057 */ 1058 mac->ops.config_collision_dist(hw); 1059 1060 /* Configure Flow Control now that Auto-Neg has completed. 1061 * First, we need to restore the desired flow control 1062 * settings because we may have had to re-autoneg with a 1063 * different link partner. 1064 */ 1065 ret_val = igc_config_fc_after_link_up_generic(hw); 1066 if (ret_val) 1067 DEBUGOUT("Error configuring flow control\n"); 1068 out: 1069 /* Now that we are aware of our link settings, we can set the LTR 1070 * thresholds. 1071 */ 1072 ret_val = igc_set_ltr_i225(hw, link); 1073 1074 return ret_val; 1075 } 1076 1077 /* igc_init_function_pointers_i225 - Init func ptrs. 1078 * @hw: pointer to the HW structure 1079 * 1080 * Called to initialize all function pointers and parameters. 1081 */ 1082 void 1083 igc_init_function_pointers_i225(struct igc_hw *hw) 1084 { 1085 igc_init_mac_ops_generic(hw); 1086 igc_init_phy_ops_generic(hw); 1087 igc_init_nvm_ops_generic(hw); 1088 hw->mac.ops.init_params = igc_init_mac_params_i225; 1089 hw->nvm.ops.init_params = igc_init_nvm_params_i225; 1090 hw->phy.ops.init_params = igc_init_phy_params_i225; 1091 } 1092 1093 /* igc_init_hw_i225 - Init hw for I225 1094 * @hw: pointer to the HW structure 1095 * 1096 * Called to initialize hw for i225 hw family. 1097 */ 1098 int 1099 igc_init_hw_i225(struct igc_hw *hw) 1100 { 1101 int ret_val; 1102 1103 DEBUGFUNC("igc_init_hw_i225"); 1104 1105 ret_val = igc_init_hw_base(hw); 1106 return ret_val; 1107 } 1108 1109 /* 1110 * igc_set_d0_lplu_state_i225 - Set Low-Power-Link-Up (LPLU) D0 state 1111 * @hw: pointer to the HW structure 1112 * @active: true to enable LPLU, false to disable 1113 * 1114 * Note: since I225 does not actually support LPLU, this function 1115 * simply enables/disables 1G and 2.5G speeds in D0. 1116 */ 1117 int 1118 igc_set_d0_lplu_state_i225(struct igc_hw *hw, bool active) 1119 { 1120 uint32_t data; 1121 1122 DEBUGFUNC("igc_set_d0_lplu_state_i225"); 1123 1124 data = IGC_READ_REG(hw, IGC_I225_PHPM); 1125 1126 if (active) { 1127 data |= IGC_I225_PHPM_DIS_1000; 1128 data |= IGC_I225_PHPM_DIS_2500; 1129 } else { 1130 data &= ~IGC_I225_PHPM_DIS_1000; 1131 data &= ~IGC_I225_PHPM_DIS_2500; 1132 } 1133 1134 IGC_WRITE_REG(hw, IGC_I225_PHPM, data); 1135 return IGC_SUCCESS; 1136 } 1137 1138 /* 1139 * igc_set_d3_lplu_state_i225 - Set Low-Power-Link-Up (LPLU) D3 state 1140 * @hw: pointer to the HW structure 1141 * @active: true to enable LPLU, false to disable 1142 * 1143 * Note: since I225 does not actually support LPLU, this function 1144 * simply enables/disables 100M, 1G and 2.5G speeds in D3. 1145 */ 1146 int 1147 igc_set_d3_lplu_state_i225(struct igc_hw *hw, bool active) 1148 { 1149 uint32_t data; 1150 1151 DEBUGFUNC("igc_set_d3_lplu_state_i225"); 1152 1153 data = IGC_READ_REG(hw, IGC_I225_PHPM); 1154 1155 if (active) { 1156 data |= IGC_I225_PHPM_DIS_100_D3; 1157 data |= IGC_I225_PHPM_DIS_1000_D3; 1158 data |= IGC_I225_PHPM_DIS_2500_D3; 1159 } else { 1160 data &= ~IGC_I225_PHPM_DIS_100_D3; 1161 data &= ~IGC_I225_PHPM_DIS_1000_D3; 1162 data &= ~IGC_I225_PHPM_DIS_2500_D3; 1163 } 1164 1165 IGC_WRITE_REG(hw, IGC_I225_PHPM, data); 1166 return IGC_SUCCESS; 1167 } 1168 1169 /** 1170 * igc_set_eee_i225 - Enable/disable EEE support 1171 * @hw: pointer to the HW structure 1172 * @adv2p5G: boolean flag enabling 2.5G EEE advertisement 1173 * @adv1G: boolean flag enabling 1G EEE advertisement 1174 * @adv100M: boolean flag enabling 100M EEE advertisement 1175 * 1176 * Enable/disable EEE based on setting in dev_spec structure. 1177 * 1178 **/ 1179 int 1180 igc_set_eee_i225(struct igc_hw *hw, bool adv2p5G, bool adv1G, 1181 bool adv100M) 1182 { 1183 uint32_t ipcnfg, eeer; 1184 1185 DEBUGFUNC("igc_set_eee_i225"); 1186 1187 if (hw->mac.type != igc_i225 || 1188 hw->phy.media_type != igc_media_type_copper) 1189 goto out; 1190 ipcnfg = IGC_READ_REG(hw, IGC_IPCNFG); 1191 eeer = IGC_READ_REG(hw, IGC_EEER); 1192 1193 /* enable or disable per user setting */ 1194 if (!(hw->dev_spec._i225.eee_disable)) { 1195 uint32_t eee_su = IGC_READ_REG(hw, IGC_EEE_SU); 1196 1197 if (adv100M) 1198 ipcnfg |= IGC_IPCNFG_EEE_100M_AN; 1199 else 1200 ipcnfg &= ~IGC_IPCNFG_EEE_100M_AN; 1201 1202 if (adv1G) 1203 ipcnfg |= IGC_IPCNFG_EEE_1G_AN; 1204 else 1205 ipcnfg &= ~IGC_IPCNFG_EEE_1G_AN; 1206 1207 if (adv2p5G) 1208 ipcnfg |= IGC_IPCNFG_EEE_2_5G_AN; 1209 else 1210 ipcnfg &= ~IGC_IPCNFG_EEE_2_5G_AN; 1211 1212 eeer |= (IGC_EEER_TX_LPI_EN | IGC_EEER_RX_LPI_EN | 1213 IGC_EEER_LPI_FC); 1214 1215 /* This bit should not be set in normal operation. */ 1216 if (eee_su & IGC_EEE_SU_LPI_CLK_STP) 1217 DEBUGOUT("LPI Clock Stop Bit should not be set!\n"); 1218 } else { 1219 ipcnfg &= ~(IGC_IPCNFG_EEE_2_5G_AN | IGC_IPCNFG_EEE_1G_AN | 1220 IGC_IPCNFG_EEE_100M_AN); 1221 eeer &= ~(IGC_EEER_TX_LPI_EN | IGC_EEER_RX_LPI_EN | 1222 IGC_EEER_LPI_FC); 1223 } 1224 IGC_WRITE_REG(hw, IGC_IPCNFG, ipcnfg); 1225 IGC_WRITE_REG(hw, IGC_EEER, eeer); 1226 IGC_READ_REG(hw, IGC_IPCNFG); 1227 IGC_READ_REG(hw, IGC_EEER); 1228 out: 1229 1230 return IGC_SUCCESS; 1231 } 1232