1 /* $OpenBSD: igc_base.c,v 1.2 2024/05/24 06:02:57 jsg Exp $ */ 2 /*- 3 * Copyright 2021 Intel Corp 4 * Copyright 2021 Rubicon Communications, LLC (Netgate) 5 * SPDX-License-Identifier: BSD-3-Clause 6 */ 7 8 #include <dev/pci/igc_hw.h> 9 #include <dev/pci/if_igc.h> 10 #include <dev/pci/igc_mac.h> 11 #include <dev/pci/igc_base.h> 12 13 /** 14 * igc_acquire_phy_base - Acquire rights to access PHY 15 * @hw: pointer to the HW structure 16 * 17 * Acquire access rights to the correct PHY. 18 **/ 19 int 20 igc_acquire_phy_base(struct igc_hw *hw) 21 { 22 uint16_t mask = IGC_SWFW_PHY0_SM; 23 24 DEBUGFUNC("igc_acquire_phy_base"); 25 26 if (hw->bus.func == IGC_FUNC_1) 27 mask = IGC_SWFW_PHY1_SM; 28 29 return hw->mac.ops.acquire_swfw_sync(hw, mask); 30 } 31 32 /** 33 * igc_release_phy_base - Release rights to access PHY 34 * @hw: pointer to the HW structure 35 * 36 * A wrapper to release access rights to the correct PHY. 37 **/ 38 void 39 igc_release_phy_base(struct igc_hw *hw) 40 { 41 uint16_t mask = IGC_SWFW_PHY0_SM; 42 43 DEBUGFUNC("igc_release_phy_base"); 44 45 if (hw->bus.func == IGC_FUNC_1) 46 mask = IGC_SWFW_PHY1_SM; 47 48 hw->mac.ops.release_swfw_sync(hw, mask); 49 } 50 51 /** 52 * igc_init_hw_base - Initialize hardware 53 * @hw: pointer to the HW structure 54 * 55 * This inits the hardware readying it for operation. 56 **/ 57 int 58 igc_init_hw_base(struct igc_hw *hw) 59 { 60 struct igc_mac_info *mac = &hw->mac; 61 uint16_t i, rar_count = mac->rar_entry_count; 62 int ret_val; 63 64 DEBUGFUNC("igc_init_hw_base"); 65 66 /* Setup the receive address */ 67 igc_init_rx_addrs_generic(hw, rar_count); 68 69 /* Zero out the Multicast HASH table */ 70 DEBUGOUT("Zeroing the MTA\n"); 71 for (i = 0; i < mac->mta_reg_count; i++) 72 IGC_WRITE_REG_ARRAY(hw, IGC_MTA, i, 0); 73 74 /* Zero out the Unicast HASH table */ 75 DEBUGOUT("Zeroing the UTA\n"); 76 for (i = 0; i < mac->uta_reg_count; i++) 77 IGC_WRITE_REG_ARRAY(hw, IGC_UTA, i, 0); 78 79 /* Setup link and flow control */ 80 ret_val = mac->ops.setup_link(hw); 81 /* 82 * Clear all of the statistics registers (clear on read). It is 83 * important that we do this after we have tried to establish link 84 * because the symbol error count will increment wildly if there 85 * is no link. 86 */ 87 igc_clear_hw_cntrs_base_generic(hw); 88 89 return ret_val; 90 } 91 92 /** 93 * igc_power_down_phy_copper_base - Remove link during PHY power down 94 * @hw: pointer to the HW structure 95 * 96 * In the case of a PHY power down to save power, or to turn off link during a 97 * driver unload, or wake on lan is not enabled, remove the link. 98 **/ 99 void 100 igc_power_down_phy_copper_base(struct igc_hw *hw) 101 { 102 struct igc_phy_info *phy = &hw->phy; 103 104 if (!(phy->ops.check_reset_block)) 105 return; 106 107 /* If the management interface is not enabled, then power down */ 108 if (phy->ops.check_reset_block(hw)) 109 igc_power_down_phy_copper(hw); 110 111 return; 112 } 113