1 /* $OpenBSD: if_xl_pci.c,v 1.8 2001/08/12 20:03:49 mickey Exp $ */ 2 3 /* 4 * Copyright (c) 1997, 1998, 1999 5 * Bill Paul <wpaul@ctr.columbia.edu>. All rights reserved. 6 * 7 * Redistribution and use in source and binary forms, with or without 8 * modification, are permitted provided that the following conditions 9 * are met: 10 * 1. Redistributions of source code must retain the above copyright 11 * notice, this list of conditions and the following disclaimer. 12 * 2. Redistributions in binary form must reproduce the above copyright 13 * notice, this list of conditions and the following disclaimer in the 14 * documentation and/or other materials provided with the distribution. 15 * 3. All advertising materials mentioning features or use of this software 16 * must display the following acknowledgement: 17 * This product includes software developed by Bill Paul. 18 * 4. Neither the name of the author nor the names of any co-contributors 19 * may be used to endorse or promote products derived from this software 20 * without specific prior written permission. 21 * 22 * THIS SOFTWARE IS PROVIDED BY Bill Paul AND CONTRIBUTORS ``AS IS'' AND 23 * ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE 24 * IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE 25 * ARE DISCLAIMED. IN NO EVENT SHALL Bill Paul OR THE VOICES IN HIS HEAD 26 * BE LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR 27 * CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF 28 * SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS 29 * INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN 30 * CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) 31 * ARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF 32 * THE POSSIBILITY OF SUCH DAMAGE. 33 * 34 * $FreeBSD: if_xl.c,v 1.72 2000/01/09 21:12:59 wpaul Exp $ 35 */ 36 37 #include "bpfilter.h" 38 39 #include <sys/param.h> 40 #include <sys/systm.h> 41 #include <sys/mbuf.h> 42 #include <sys/protosw.h> 43 #include <sys/socket.h> 44 #include <sys/ioctl.h> 45 #include <sys/errno.h> 46 #include <sys/malloc.h> 47 #include <sys/kernel.h> 48 #include <sys/proc.h> /* only for declaration of wakeup() used by vm.h */ 49 #include <sys/device.h> 50 51 #include <net/if.h> 52 #include <net/if_dl.h> 53 #include <net/if_types.h> 54 #include <net/if_media.h> 55 56 #ifdef INET 57 #include <netinet/in.h> 58 #include <netinet/in_systm.h> 59 #include <netinet/in_var.h> 60 #include <netinet/ip.h> 61 #include <netinet/if_ether.h> 62 #endif 63 64 #include <dev/mii/mii.h> 65 #include <dev/mii/miivar.h> 66 #include <dev/pci/pcireg.h> 67 #include <dev/pci/pcivar.h> 68 #include <dev/pci/pcidevs.h> 69 70 #if NBPFILTER > 0 71 #include <net/bpf.h> 72 #endif 73 74 #include <vm/vm.h> /* for vtophys */ 75 76 /* 77 * The following #define causes the code to use PIO to access the 78 * chip's registers instead of memory mapped mode. The reason PIO mode 79 * is on by default is that the Etherlink XL manual seems to indicate 80 * that only the newer revision chips (3c905B) support both PIO and 81 * memory mapped access. Since we want to be compatible with the older 82 * bus master chips, we use PIO here. If you comment this out, the 83 * driver will use memory mapped I/O, which may be faster but which 84 * might not work on some devices. 85 */ 86 #define XL_USEIOSPACE 87 88 #define XL_PCI_FUNCMEM 0x0018 89 #define XL_PCI_INTR 0x0004 90 #define XL_PCI_INTRACK 0x8000 91 92 #include <dev/ic/xlreg.h> 93 94 int xl_pci_match __P((struct device *, void *, void *)); 95 void xl_pci_attach __P((struct device *, struct device *, void *)); 96 void xl_pci_intr_ack __P((struct xl_softc *)); 97 98 struct cfattach xl_pci_ca = { 99 sizeof(struct xl_softc), xl_pci_match, xl_pci_attach, 100 }; 101 102 int 103 xl_pci_match(parent, match, aux) 104 struct device *parent; 105 void *match; 106 void *aux; 107 { 108 struct pci_attach_args *pa = (struct pci_attach_args *) aux; 109 110 if (PCI_VENDOR(pa->pa_id) != PCI_VENDOR_3COM) 111 return (0); 112 113 switch (PCI_PRODUCT(pa->pa_id)) { 114 case PCI_PRODUCT_3COM_3CSOHO100TX: 115 case PCI_PRODUCT_3COM_3C900TPO: 116 case PCI_PRODUCT_3COM_3C900COMBO: 117 case PCI_PRODUCT_3COM_3C900B: 118 case PCI_PRODUCT_3COM_3C900BCOMBO: 119 case PCI_PRODUCT_3COM_3C900BTPC: 120 case PCI_PRODUCT_3COM_3C900BFL: 121 case PCI_PRODUCT_3COM_3C905TX: 122 case PCI_PRODUCT_3COM_3C905T4: 123 case PCI_PRODUCT_3COM_3C905BTX: 124 case PCI_PRODUCT_3COM_3C905BT4: 125 case PCI_PRODUCT_3COM_3C905BCOMBO: 126 case PCI_PRODUCT_3COM_3C905BFX: 127 case PCI_PRODUCT_3COM_3C980TX: 128 case PCI_PRODUCT_3COM_3C980CTX: 129 case PCI_PRODUCT_3COM_3C905CTX: 130 case PCI_PRODUCT_3COM_3C450: 131 case PCI_PRODUCT_3COM_3C555: 132 case PCI_PRODUCT_3COM_3C556: 133 case PCI_PRODUCT_3COM_3C556B: 134 return (1); 135 } 136 137 return (0); 138 } 139 140 void 141 xl_pci_attach(parent, self, aux) 142 struct device *parent, *self; 143 void *aux; 144 { 145 struct xl_softc *sc = (struct xl_softc *)self; 146 struct pci_attach_args *pa = aux; 147 pci_chipset_tag_t pc = pa->pa_pc; 148 pci_intr_handle_t ih; 149 const char *intrstr = NULL; 150 bus_addr_t iobase; 151 bus_size_t iosize; 152 u_int32_t command; 153 154 sc->xl_unit = sc->sc_dev.dv_unit; 155 156 sc->xl_flags = 0; 157 158 /* set flags required for 3Com MiniPCI adapters */ 159 switch (PCI_PRODUCT(pa->pa_id)) { 160 case TC_DEVICEID_HURRICANE_555: 161 sc->xl_flags |= XL_FLAG_EEPROM_OFFSET_30 | XL_FLAG_8BITROM; 162 break; 163 case TC_DEVICEID_HURRICANE_556: 164 sc->xl_flags |= XL_FLAG_FUNCREG | XL_FLAG_PHYOK | 165 XL_FLAG_EEPROM_OFFSET_30 | XL_FLAG_WEIRDRESET; 166 sc->xl_flags |= XL_FLAG_INVERT_LED_PWR|XL_FLAG_INVERT_MII_PWR; 167 sc->xl_flags |= XL_FLAG_8BITROM; 168 break; 169 case TC_DEVICEID_HURRICANE_556B: 170 sc->xl_flags |= XL_FLAG_FUNCREG | XL_FLAG_PHYOK | 171 XL_FLAG_EEPROM_OFFSET_30 | XL_FLAG_WEIRDRESET; 172 sc->xl_flags |= XL_FLAG_INVERT_LED_PWR|XL_FLAG_INVERT_MII_PWR; 173 break; 174 default: 175 break; 176 } 177 178 /* 179 * If this is a 3c905B, we have to check one extra thing. 180 * The 905B supports power management and may be placed in 181 * a low-power mode (D3 mode), typically by certain operating 182 * systems which shall not be named. The PCI BIOS is supposed 183 * to reset the NIC and bring it out of low-power mode, but 184 * some do not. Consequently, we have to see if this chip 185 * supports power management, and if so, make sure it's not 186 * in low-power mode. If power management is available, the 187 * capid byte will be 0x01. 188 * 189 * I _think_ that what actually happens is that the chip 190 * loses its PCI configuration during the transition from 191 * D3 back to D0; this means that it should be possible for 192 * us to save the PCI iobase, membase and IRQ, put the chip 193 * back in the D0 state, then restore the PCI config ourselves. 194 */ 195 command = pci_conf_read(pc, pa->pa_tag, XL_PCI_CAPID) & 0xff; 196 if (command == 0x01) { 197 198 command = pci_conf_read(pc, pa->pa_tag, 199 XL_PCI_PWRMGMTCTRL); 200 if (command & XL_PSTATE_MASK) { 201 u_int32_t io, mem, irq; 202 203 /* Save PCI config */ 204 io = pci_conf_read(pc, pa->pa_tag, XL_PCI_LOIO); 205 mem = pci_conf_read(pc, pa->pa_tag, XL_PCI_LOMEM); 206 irq = pci_conf_read(pc, pa->pa_tag, XL_PCI_INTLINE); 207 208 /* Reset the power state. */ 209 printf("%s: chip is in D%d power mode " 210 "-- setting to D0\n", 211 sc->sc_dev.dv_xname, command & XL_PSTATE_MASK); 212 command &= 0xFFFFFFFC; 213 pci_conf_write(pc, pa->pa_tag, 214 XL_PCI_PWRMGMTCTRL, command); 215 216 pci_conf_write(pc, pa->pa_tag, XL_PCI_LOIO, io); 217 pci_conf_write(pc, pa->pa_tag, XL_PCI_LOMEM, mem); 218 pci_conf_write(pc, pa->pa_tag, XL_PCI_INTLINE, irq); 219 } 220 } 221 222 /* 223 * Map control/status registers. 224 */ 225 command = pci_conf_read(pc, pa->pa_tag, PCI_COMMAND_STATUS_REG); 226 command |= PCI_COMMAND_IO_ENABLE | 227 PCI_COMMAND_MEM_ENABLE | 228 PCI_COMMAND_MASTER_ENABLE; 229 pci_conf_write(pc, pa->pa_tag, PCI_COMMAND_STATUS_REG, command); 230 command = pci_conf_read(pc, pa->pa_tag, PCI_COMMAND_STATUS_REG); 231 232 #ifdef XL_USEIOSPACE 233 if (!(command & PCI_COMMAND_IO_ENABLE)) { 234 printf("%s: failed to enable i/o ports\n", 235 sc->sc_dev.dv_xname); 236 return; 237 } 238 /* 239 * Map control/status registers. 240 */ 241 if (pci_io_find(pc, pa->pa_tag, XL_PCI_LOIO, &iobase, &iosize)) { 242 printf(": can't find i/o space\n"); 243 return; 244 } 245 if (bus_space_map(pa->pa_iot, iobase, iosize, 0, &sc->xl_bhandle)) { 246 printf(": can't map i/o space\n"); 247 return; 248 } 249 sc->xl_btag = pa->pa_iot; 250 #else 251 if (!(command & PCI_COMMAND_MEM_ENABLE)) { 252 printf(": failed to enable memory mapping\n"); 253 return; 254 } 255 if (pci_mem_find(pc, pa->pa_tag, XL_PCI_LOMEM, &iobase, &iosize, NULL)){ 256 printf(": can't find mem space\n"); 257 return; 258 } 259 if (bus_space_map(pa->pa_memt, iobase, iosize, 0, &sc->xl_bhandle)) { 260 printf(": can't map mem space\n"); 261 return; 262 } 263 sc->xl_btag = pa->pa_memt; 264 #endif 265 266 if (sc->xl_flags & XL_FLAG_FUNCREG) { 267 if (pci_mem_find(pc, pa->pa_tag, XL_PCI_FUNCMEM, &iobase, 268 &iosize, NULL)) { 269 printf(": can't find func space\n"); 270 return; 271 } 272 if (bus_space_map(pa->pa_memt, iobase, iosize, 0, 273 &sc->xl_funch)) { 274 printf(": can't map func space\n"); 275 return; 276 } 277 sc->xl_funct = pa->pa_memt; 278 sc->intr_ack = xl_pci_intr_ack; 279 } 280 281 /* 282 * Allocate our interrupt. 283 */ 284 if (pci_intr_map(pc, pa->pa_intrtag, pa->pa_intrpin, 285 pa->pa_intrline, &ih)) { 286 printf(": couldn't map interrupt\n"); 287 return; 288 } 289 290 intrstr = pci_intr_string(pc, ih); 291 sc->xl_intrhand = pci_intr_establish(pc, ih, IPL_NET, xl_intr, sc, 292 self->dv_xname); 293 if (sc->xl_intrhand == NULL) { 294 printf(": couldn't establish interrupt"); 295 if (intrstr != NULL) 296 printf(" at %s", intrstr); 297 return; 298 } 299 printf(": %s", intrstr); 300 301 xl_attach(sc); 302 } 303 304 305 void 306 xl_pci_intr_ack(sc) 307 struct xl_softc *sc; 308 { 309 bus_space_write_4(sc->xl_funct, sc->xl_funch, XL_PCI_INTR, 310 XL_PCI_INTRACK); 311 } 312