1 /* $OpenBSD: if_xge.c,v 1.73 2016/05/16 04:34:25 dlg Exp $ */ 2 /* $NetBSD: if_xge.c,v 1.1 2005/09/09 10:30:27 ragge Exp $ */ 3 4 /* 5 * Copyright (c) 2004, SUNET, Swedish University Computer Network. 6 * All rights reserved. 7 * 8 * Written by Anders Magnusson for SUNET, Swedish University Computer Network. 9 * 10 * Redistribution and use in source and binary forms, with or without 11 * modification, are permitted provided that the following conditions 12 * are met: 13 * 1. Redistributions of source code must retain the above copyright 14 * notice, this list of conditions and the following disclaimer. 15 * 2. Redistributions in binary form must reproduce the above copyright 16 * notice, this list of conditions and the following disclaimer in the 17 * documentation and/or other materials provided with the distribution. 18 * 3. All advertising materials mentioning features or use of this software 19 * must display the following acknowledgement: 20 * This product includes software developed for the NetBSD Project by 21 * SUNET, Swedish University Computer Network. 22 * 4. The name of SUNET may not be used to endorse or promote products 23 * derived from this software without specific prior written permission. 24 * 25 * THIS SOFTWARE IS PROVIDED BY SUNET ``AS IS'' AND 26 * ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED 27 * TO, THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR 28 * PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL SUNET 29 * BE LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR 30 * CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF 31 * SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS 32 * INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN 33 * CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) 34 * ARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE 35 * POSSIBILITY OF SUCH DAMAGE. 36 */ 37 38 /* 39 * Driver for the Neterion Xframe Ten Gigabit Ethernet controller. 40 */ 41 42 #include "bpfilter.h" 43 #include "vlan.h" 44 45 #include <sys/param.h> 46 #include <sys/systm.h> 47 #include <sys/sockio.h> 48 #include <sys/mbuf.h> 49 #include <sys/malloc.h> 50 #include <sys/kernel.h> 51 #include <sys/socket.h> 52 #include <sys/device.h> 53 #include <sys/endian.h> 54 55 #include <net/if.h> 56 #include <net/if_media.h> 57 58 #include <netinet/in.h> 59 #include <netinet/if_ether.h> 60 61 #if NBPFILTER > 0 62 #include <net/bpf.h> 63 #endif 64 65 #include <machine/bus.h> 66 #include <machine/intr.h> 67 68 #include <dev/mii/miivar.h> 69 70 #include <dev/pci/pcivar.h> 71 #include <dev/pci/pcireg.h> 72 #include <dev/pci/pcidevs.h> 73 74 #include <sys/lock.h> 75 76 #include <dev/pci/if_xgereg.h> 77 78 /* Xframe chipset revisions */ 79 #define XGE_TYPE_XENA 1 /* Xframe */ 80 #define XGE_TYPE_HERC 2 /* Xframe-II */ 81 82 #define XGE_PCISIZE_XENA 26 83 #define XGE_PCISIZE_HERC 64 84 85 /* 86 * Some tunable constants, tune with care! 87 */ 88 #define RX_MODE RX_MODE_1 /* Receive mode (buffer usage, see below) */ 89 #define NRXDESCS 1016 /* # of receive descriptors (requested) */ 90 #define NTXDESCS 2048 /* Number of transmit descriptors */ 91 #define NTXFRAGS 100 /* Max fragments per packet */ 92 93 /* 94 * Receive buffer modes; 1, 3 or 5 buffers. 95 */ 96 #define RX_MODE_1 1 97 #define RX_MODE_3 3 98 #define RX_MODE_5 5 99 100 /* 101 * Use clever macros to avoid a bunch of #ifdef's. 102 */ 103 #define XCONCAT3(x,y,z) x ## y ## z 104 #define CONCAT3(x,y,z) XCONCAT3(x,y,z) 105 #define NDESC_BUFMODE CONCAT3(NDESC_,RX_MODE,BUFMODE) 106 #define rxd_4k CONCAT3(rxd,RX_MODE,_4k) 107 /* XXX */ 108 #if 0 109 #define rxdesc ___CONCAT(rxd,RX_MODE) 110 #endif 111 #define rxdesc rxd1 112 113 #define NEXTTX(x) (((x)+1) % NTXDESCS) 114 #define NRXFRAGS RX_MODE /* hardware imposed frags */ 115 #define NRXPAGES ((NRXDESCS/NDESC_BUFMODE)+1) 116 #define NRXREAL (NRXPAGES*NDESC_BUFMODE) 117 #define RXMAPSZ (NRXPAGES*PAGE_SIZE) 118 119 /* 120 * Magic to fix a bug when the MAC address cannot be read correctly. 121 * This came from the Linux driver. 122 */ 123 static const uint64_t xge_fix_mac[] = { 124 0x0060000000000000ULL, 0x0060600000000000ULL, 125 0x0040600000000000ULL, 0x0000600000000000ULL, 126 0x0020600000000000ULL, 0x0060600000000000ULL, 127 0x0020600000000000ULL, 0x0060600000000000ULL, 128 0x0020600000000000ULL, 0x0060600000000000ULL, 129 0x0020600000000000ULL, 0x0060600000000000ULL, 130 0x0020600000000000ULL, 0x0060600000000000ULL, 131 0x0020600000000000ULL, 0x0060600000000000ULL, 132 0x0020600000000000ULL, 0x0060600000000000ULL, 133 0x0020600000000000ULL, 0x0060600000000000ULL, 134 0x0020600000000000ULL, 0x0060600000000000ULL, 135 0x0020600000000000ULL, 0x0060600000000000ULL, 136 0x0020600000000000ULL, 0x0000600000000000ULL, 137 0x0040600000000000ULL, 0x0060600000000000ULL, 138 }; 139 140 /* 141 * Constants to be programmed into Hercules's registers, to configure 142 * the XGXS transciever. 143 */ 144 static const uint64_t xge_herc_dtx_cfg[] = { 145 0x8000051536750000ULL, 0x80000515367500E0ULL, 146 0x8000051536750004ULL, 0x80000515367500E4ULL, 147 148 0x80010515003F0000ULL, 0x80010515003F00E0ULL, 149 0x80010515003F0004ULL, 0x80010515003F00E4ULL, 150 151 0x801205150D440000ULL, 0x801205150D4400E0ULL, 152 0x801205150D440004ULL, 0x801205150D4400E4ULL, 153 154 0x80020515F2100000ULL, 0x80020515F21000E0ULL, 155 0x80020515F2100004ULL, 0x80020515F21000E4ULL, 156 }; 157 158 static const uint64_t xge_xena_dtx_cfg[] = { 159 0x8000051500000000ULL, 0x80000515000000E0ULL, 160 0x80000515D9350004ULL, 0x80000515D93500E4ULL, 161 162 0x8001051500000000ULL, 0x80010515000000E0ULL, 163 0x80010515001E0004ULL, 0x80010515001E00E4ULL, 164 165 0x8002051500000000ULL, 0x80020515000000E0ULL, 166 0x80020515F2100004ULL, 0x80020515F21000E4ULL, 167 }; 168 169 struct xge_softc { 170 struct device sc_dev; 171 struct arpcom sc_arpcom; 172 struct ifmedia xena_media; 173 174 void *sc_ih; 175 176 bus_dma_tag_t sc_dmat; 177 bus_space_tag_t sc_st; 178 bus_space_handle_t sc_sh; 179 bus_space_tag_t sc_txt; 180 bus_space_handle_t sc_txh; 181 182 pcireg_t sc_pciregs[16]; 183 184 int xge_type; /* chip type */ 185 int xge_if_flags; 186 187 /* Transmit structures */ 188 struct txd *sc_txd[NTXDESCS]; /* transmit frags array */ 189 bus_addr_t sc_txdp[NTXDESCS]; /* dva of transmit frags */ 190 bus_dmamap_t sc_txm[NTXDESCS]; /* transmit frags map */ 191 struct mbuf *sc_txb[NTXDESCS]; /* transmit mbuf pointer */ 192 int sc_nexttx, sc_lasttx; 193 bus_dmamap_t sc_txmap; /* transmit descriptor map */ 194 195 /* Receive data */ 196 bus_dmamap_t sc_rxmap; /* receive descriptor map */ 197 struct rxd_4k *sc_rxd_4k[NRXPAGES]; /* receive desc pages */ 198 bus_dmamap_t sc_rxm[NRXREAL]; /* receive buffer map */ 199 struct mbuf *sc_rxb[NRXREAL]; /* mbufs on rx descriptors */ 200 int sc_nextrx; /* next descriptor to check */ 201 }; 202 203 #ifdef XGE_DEBUG 204 #define DPRINTF(x) do { if (xgedebug) printf x ; } while (0) 205 #define DPRINTFN(n,x) do { if (xgedebug >= (n)) printf x ; } while (0) 206 int xgedebug = 0; 207 #else 208 #define DPRINTF(x) 209 #define DPRINTFN(n,x) 210 #endif 211 212 int xge_match(struct device *, void *, void *); 213 void xge_attach(struct device *, struct device *, void *); 214 int xge_alloc_txmem(struct xge_softc *); 215 int xge_alloc_rxmem(struct xge_softc *); 216 void xge_start(struct ifnet *); 217 void xge_stop(struct ifnet *, int); 218 int xge_add_rxbuf(struct xge_softc *, int); 219 void xge_setmulti(struct xge_softc *); 220 void xge_setpromisc(struct xge_softc *); 221 int xge_setup_xgxs_xena(struct xge_softc *); 222 int xge_setup_xgxs_herc(struct xge_softc *); 223 int xge_ioctl(struct ifnet *, u_long, caddr_t); 224 int xge_init(struct ifnet *); 225 void xge_ifmedia_status(struct ifnet *, struct ifmediareq *); 226 int xge_xgmii_mediachange(struct ifnet *); 227 void xge_enable(struct xge_softc *); 228 int xge_intr(void *); 229 230 /* 231 * Helpers to address registers. 232 */ 233 #define PIF_WCSR(csr, val) pif_wcsr(sc, csr, val) 234 #define PIF_RCSR(csr) pif_rcsr(sc, csr) 235 #define TXP_WCSR(csr, val) txp_wcsr(sc, csr, val) 236 #define PIF_WKEY(csr, val) pif_wkey(sc, csr, val) 237 238 static inline void 239 pif_wcsr(struct xge_softc *sc, bus_size_t csr, uint64_t val) 240 { 241 #if defined(__LP64__) 242 bus_space_write_raw_8(sc->sc_st, sc->sc_sh, csr, val); 243 #else 244 uint32_t lval, hval; 245 246 lval = val&0xffffffff; 247 hval = val>>32; 248 249 #if BYTE_ORDER == LITTLE_ENDIAN 250 bus_space_write_raw_4(sc->sc_st, sc->sc_sh, csr, lval); 251 bus_space_write_raw_4(sc->sc_st, sc->sc_sh, csr+4, hval); 252 #else 253 bus_space_write_raw_4(sc->sc_st, sc->sc_sh, csr+4, lval); 254 bus_space_write_raw_4(sc->sc_st, sc->sc_sh, csr, hval); 255 #endif 256 #endif 257 } 258 259 static inline uint64_t 260 pif_rcsr(struct xge_softc *sc, bus_size_t csr) 261 { 262 uint64_t val; 263 #if defined(__LP64__) 264 val = bus_space_read_raw_8(sc->sc_st, sc->sc_sh, csr); 265 #else 266 uint64_t val2; 267 268 val = bus_space_read_raw_4(sc->sc_st, sc->sc_sh, csr); 269 val2 = bus_space_read_raw_4(sc->sc_st, sc->sc_sh, csr+4); 270 #if BYTE_ORDER == LITTLE_ENDIAN 271 val |= (val2 << 32); 272 #else 273 val = (val << 32 | val2); 274 #endif 275 #endif 276 return (val); 277 } 278 279 static inline void 280 txp_wcsr(struct xge_softc *sc, bus_size_t csr, uint64_t val) 281 { 282 #if defined(__LP64__) 283 bus_space_write_raw_8(sc->sc_txt, sc->sc_txh, csr, val); 284 #else 285 uint32_t lval, hval; 286 287 lval = val&0xffffffff; 288 hval = val>>32; 289 290 #if BYTE_ORDER == LITTLE_ENDIAN 291 bus_space_write_raw_4(sc->sc_txt, sc->sc_txh, csr, lval); 292 bus_space_write_raw_4(sc->sc_txt, sc->sc_txh, csr+4, hval); 293 #else 294 bus_space_write_raw_4(sc->sc_txt, sc->sc_txh, csr, hval); 295 bus_space_write_raw_4(sc->sc_txt, sc->sc_txh, csr+4, lval); 296 #endif 297 #endif 298 } 299 300 static inline void 301 pif_wkey(struct xge_softc *sc, bus_size_t csr, uint64_t val) 302 { 303 #if defined(__LP64__) 304 if (sc->xge_type == XGE_TYPE_XENA) 305 PIF_WCSR(RMAC_CFG_KEY, RMAC_KEY_VALUE); 306 307 bus_space_write_raw_8(sc->sc_st, sc->sc_sh, csr, val); 308 #else 309 uint32_t lval, hval; 310 311 lval = val&0xffffffff; 312 hval = val>>32; 313 314 if (sc->xge_type == XGE_TYPE_XENA) 315 PIF_WCSR(RMAC_CFG_KEY, RMAC_KEY_VALUE); 316 317 #if BYTE_ORDER == LITTLE_ENDIAN 318 bus_space_write_raw_4(sc->sc_st, sc->sc_sh, csr, lval); 319 #else 320 bus_space_write_raw_4(sc->sc_st, sc->sc_sh, csr, hval); 321 #endif 322 323 if (sc->xge_type == XGE_TYPE_XENA) 324 PIF_WCSR(RMAC_CFG_KEY, RMAC_KEY_VALUE); 325 #if BYTE_ORDER == LITTLE_ENDIAN 326 bus_space_write_raw_4(sc->sc_st, sc->sc_sh, csr+4, hval); 327 #else 328 bus_space_write_raw_4(sc->sc_st, sc->sc_sh, csr+4, lval); 329 #endif 330 #endif 331 } 332 333 struct cfattach xge_ca = { 334 sizeof(struct xge_softc), xge_match, xge_attach 335 }; 336 337 struct cfdriver xge_cd = { 338 NULL, "xge", DV_IFNET 339 }; 340 341 #define XNAME sc->sc_dev.dv_xname 342 343 #define XGE_RXSYNC(desc, what) \ 344 bus_dmamap_sync(sc->sc_dmat, sc->sc_rxmap, \ 345 (desc/NDESC_BUFMODE) * XGE_PAGE + sizeof(struct rxdesc) * \ 346 (desc%NDESC_BUFMODE), sizeof(struct rxdesc), what) 347 #define XGE_RXD(desc) &sc->sc_rxd_4k[desc/NDESC_BUFMODE]-> \ 348 r4_rxd[desc%NDESC_BUFMODE] 349 350 /* 351 * Non-tunable constants. 352 */ 353 #define XGE_MAX_FRAMELEN 9622 354 #define XGE_MAX_MTU (XGE_MAX_FRAMELEN - ETHER_HDR_LEN - \ 355 ETHER_CRC_LEN - ETHER_VLAN_ENCAP_LEN) 356 357 const struct pci_matchid xge_devices[] = { 358 { PCI_VENDOR_NETERION, PCI_PRODUCT_NETERION_XFRAME }, 359 { PCI_VENDOR_NETERION, PCI_PRODUCT_NETERION_XFRAME_2 } 360 }; 361 362 int 363 xge_match(struct device *parent, void *match, void *aux) 364 { 365 return (pci_matchbyid((struct pci_attach_args *)aux, xge_devices, 366 nitems(xge_devices))); 367 } 368 369 void 370 xge_attach(struct device *parent, struct device *self, void *aux) 371 { 372 struct pci_attach_args *pa = aux; 373 struct xge_softc *sc; 374 struct ifnet *ifp; 375 pcireg_t memtype; 376 pci_intr_handle_t ih; 377 const char *intrstr = NULL; 378 pci_chipset_tag_t pc = pa->pa_pc; 379 uint8_t enaddr[ETHER_ADDR_LEN]; 380 uint64_t val; 381 int i; 382 383 sc = (struct xge_softc *)self; 384 385 sc->sc_dmat = pa->pa_dmat; 386 387 if (PCI_PRODUCT(pa->pa_id) == PCI_PRODUCT_NETERION_XFRAME) 388 sc->xge_type = XGE_TYPE_XENA; 389 else 390 sc->xge_type = XGE_TYPE_HERC; 391 392 /* Get BAR0 address */ 393 memtype = pci_mapreg_type(pa->pa_pc, pa->pa_tag, XGE_PIF_BAR); 394 if (pci_mapreg_map(pa, XGE_PIF_BAR, memtype, 0, 395 &sc->sc_st, &sc->sc_sh, 0, 0, 0)) { 396 printf(": unable to map PIF BAR registers\n"); 397 return; 398 } 399 400 memtype = pci_mapreg_type(pa->pa_pc, pa->pa_tag, XGE_TXP_BAR); 401 if (pci_mapreg_map(pa, XGE_TXP_BAR, memtype, 0, 402 &sc->sc_txt, &sc->sc_txh, 0, 0, 0)) { 403 printf(": unable to map TXP BAR registers\n"); 404 return; 405 } 406 407 if (sc->xge_type == XGE_TYPE_XENA) { 408 /* Save PCI config space */ 409 for (i = 0; i < XGE_PCISIZE_XENA; i += 4) 410 sc->sc_pciregs[i/4] = pci_conf_read(pa->pa_pc, pa->pa_tag, i); 411 sc->sc_pciregs[i/4] = pci_conf_read(pa->pa_pc, pa->pa_tag, i); 412 } 413 414 #if BYTE_ORDER == LITTLE_ENDIAN 415 val = (uint64_t)0xFFFFFFFFFFFFFFFFULL; 416 val &= ~(TxF_R_SE|RxF_W_SE); 417 PIF_WCSR(SWAPPER_CTRL, val); 418 PIF_WCSR(SWAPPER_CTRL, val); 419 #endif 420 if ((val = PIF_RCSR(PIF_RD_SWAPPER_Fb)) != SWAPPER_MAGIC) { 421 printf(": failed configuring endian (read), %llx != %llx!\n", 422 (unsigned long long)val, SWAPPER_MAGIC); 423 } 424 425 PIF_WCSR(XMSI_ADDRESS, SWAPPER_MAGIC); 426 if ((val = PIF_RCSR(XMSI_ADDRESS)) != SWAPPER_MAGIC) { 427 printf(": failed configuring endian (write), %llx != %llx!\n", 428 (unsigned long long)val, SWAPPER_MAGIC); 429 } 430 431 /* 432 * Fix for all "FFs" MAC address problems observed on 433 * Alpha platforms. Not needed for Herc. 434 */ 435 if (sc->xge_type == XGE_TYPE_XENA) { 436 /* 437 * The MAC addr may be all FF's, which is not good. 438 * Resolve it by writing some magics to GPIO_CONTROL and 439 * force a chip reset to read in the serial eeprom again. 440 */ 441 for (i = 0; i < nitems(xge_fix_mac); i++) { 442 PIF_WCSR(GPIO_CONTROL, xge_fix_mac[i]); 443 PIF_RCSR(GPIO_CONTROL); 444 } 445 446 /* 447 * Reset the chip and restore the PCI registers. 448 */ 449 PIF_WCSR(SW_RESET, 0xa5a5a50000000000ULL); 450 DELAY(500000); 451 for (i = 0; i < XGE_PCISIZE_XENA; i += 4) 452 pci_conf_write(pa->pa_pc, pa->pa_tag, i, sc->sc_pciregs[i/4]); 453 454 /* 455 * Restore the byte order registers. 456 */ 457 #if BYTE_ORDER == LITTLE_ENDIAN 458 val = (uint64_t)0xFFFFFFFFFFFFFFFFULL; 459 val &= ~(TxF_R_SE|RxF_W_SE); 460 PIF_WCSR(SWAPPER_CTRL, val); 461 PIF_WCSR(SWAPPER_CTRL, val); 462 #endif 463 464 if ((val = PIF_RCSR(PIF_RD_SWAPPER_Fb)) != SWAPPER_MAGIC) { 465 printf(": failed configuring endian2 (read), %llx != %llx!\n", 466 (unsigned long long)val, SWAPPER_MAGIC); 467 return; 468 } 469 470 PIF_WCSR(XMSI_ADDRESS, SWAPPER_MAGIC); 471 if ((val = PIF_RCSR(XMSI_ADDRESS)) != SWAPPER_MAGIC) { 472 printf(": failed configuring endian2 (write), %llx != %llx!\n", 473 (unsigned long long)val, SWAPPER_MAGIC); 474 return; 475 } 476 } 477 478 /* 479 * XGXS initialization. 480 */ 481 482 /* 483 * For Herc, bring EOI out of reset before XGXS. 484 */ 485 if (sc->xge_type == XGE_TYPE_HERC) { 486 val = PIF_RCSR(SW_RESET); 487 val &= 0xffff00ffffffffffULL; 488 PIF_WCSR(SW_RESET,val); 489 delay(1000*1000); /* wait for 1 sec */ 490 } 491 492 /* 29, Bring adapter out of reset */ 493 val = PIF_RCSR(SW_RESET); 494 val &= 0xffffff00ffffffffULL; 495 PIF_WCSR(SW_RESET, val); 496 DELAY(500000); 497 498 /* Ensure that it's safe to access registers by checking 499 * RIC_RUNNING bit is reset. Check is valid only for XframeII. 500 */ 501 if (sc->xge_type == XGE_TYPE_HERC){ 502 for (i = 0; i < 50; i++) { 503 val = PIF_RCSR(ADAPTER_STATUS); 504 if (!(val & RIC_RUNNING)) 505 break; 506 delay(20*1000); 507 } 508 509 if (i == 50) { 510 printf(": not safe to access registers\n"); 511 return; 512 } 513 } 514 515 /* 30, configure XGXS transceiver */ 516 if (sc->xge_type == XGE_TYPE_XENA) 517 xge_setup_xgxs_xena(sc); 518 else if(sc->xge_type == XGE_TYPE_HERC) 519 xge_setup_xgxs_herc(sc); 520 521 /* 33, program MAC address (not needed here) */ 522 /* Get ethernet address */ 523 PIF_WCSR(RMAC_ADDR_CMD_MEM, 524 RMAC_ADDR_CMD_MEM_STR|RMAC_ADDR_CMD_MEM_OFF(0)); 525 while (PIF_RCSR(RMAC_ADDR_CMD_MEM) & RMAC_ADDR_CMD_MEM_STR) 526 ; 527 val = PIF_RCSR(RMAC_ADDR_DATA0_MEM); 528 for (i = 0; i < ETHER_ADDR_LEN; i++) 529 enaddr[i] = (uint8_t)(val >> (56 - (8*i))); 530 531 /* 532 * Get memory for transmit descriptor lists. 533 */ 534 if (xge_alloc_txmem(sc)) { 535 printf(": failed allocating txmem.\n"); 536 return; 537 } 538 539 /* 9 and 10 - set FIFO number/prio */ 540 PIF_WCSR(TX_FIFO_P0, TX_FIFO_LEN0(NTXDESCS)); 541 PIF_WCSR(TX_FIFO_P1, 0ULL); 542 PIF_WCSR(TX_FIFO_P2, 0ULL); 543 PIF_WCSR(TX_FIFO_P3, 0ULL); 544 545 /* 11, XXX set round-robin prio? */ 546 547 /* 12, enable transmit FIFO */ 548 val = PIF_RCSR(TX_FIFO_P0); 549 val |= TX_FIFO_ENABLE; 550 PIF_WCSR(TX_FIFO_P0, val); 551 552 /* 13, disable some error checks */ 553 PIF_WCSR(TX_PA_CFG, 554 TX_PA_CFG_IFR|TX_PA_CFG_ISO|TX_PA_CFG_ILC|TX_PA_CFG_ILE); 555 556 /* Create transmit DMA maps */ 557 for (i = 0; i < NTXDESCS; i++) { 558 if (bus_dmamap_create(sc->sc_dmat, XGE_MAX_FRAMELEN, 559 NTXFRAGS, XGE_MAX_FRAMELEN, 0, BUS_DMA_NOWAIT, 560 &sc->sc_txm[i])) { 561 printf(": cannot create TX DMA maps\n"); 562 return; 563 } 564 } 565 566 sc->sc_lasttx = NTXDESCS-1; 567 568 /* 569 * RxDMA initialization. 570 * Only use one out of 8 possible receive queues. 571 */ 572 /* allocate rx descriptor memory */ 573 if (xge_alloc_rxmem(sc)) { 574 printf(": failed allocating rxmem\n"); 575 return; 576 } 577 578 /* Create receive buffer DMA maps */ 579 for (i = 0; i < NRXREAL; i++) { 580 if (bus_dmamap_create(sc->sc_dmat, XGE_MAX_FRAMELEN, 581 NRXFRAGS, XGE_MAX_FRAMELEN, 0, BUS_DMA_NOWAIT, 582 &sc->sc_rxm[i])) { 583 printf(": cannot create RX DMA maps\n"); 584 return; 585 } 586 } 587 588 /* allocate mbufs to receive descriptors */ 589 for (i = 0; i < NRXREAL; i++) 590 if (xge_add_rxbuf(sc, i)) 591 panic("out of mbufs too early"); 592 593 /* 14, setup receive ring priority */ 594 PIF_WCSR(RX_QUEUE_PRIORITY, 0ULL); /* only use one ring */ 595 596 /* 15, setup receive ring round-robin calendar */ 597 PIF_WCSR(RX_W_ROUND_ROBIN_0, 0ULL); /* only use one ring */ 598 PIF_WCSR(RX_W_ROUND_ROBIN_1, 0ULL); 599 PIF_WCSR(RX_W_ROUND_ROBIN_2, 0ULL); 600 PIF_WCSR(RX_W_ROUND_ROBIN_3, 0ULL); 601 PIF_WCSR(RX_W_ROUND_ROBIN_4, 0ULL); 602 603 /* 16, write receive ring start address */ 604 PIF_WCSR(PRC_RXD0_0, (uint64_t)sc->sc_rxmap->dm_segs[0].ds_addr); 605 /* PRC_RXD0_[1-7] are not used */ 606 607 /* 17, Setup alarm registers */ 608 PIF_WCSR(PRC_ALARM_ACTION, 0ULL); /* Default everything to retry */ 609 610 /* 18, init receive ring controller */ 611 #if RX_MODE == RX_MODE_1 612 val = RING_MODE_1; 613 #elif RX_MODE == RX_MODE_3 614 val = RING_MODE_3; 615 #else /* RX_MODE == RX_MODE_5 */ 616 val = RING_MODE_5; 617 #endif 618 PIF_WCSR(PRC_CTRL_0, RC_IN_SVC|val); 619 /* leave 1-7 disabled */ 620 /* XXXX snoop configuration? */ 621 622 /* 19, set chip memory assigned to the queue */ 623 if (sc->xge_type == XGE_TYPE_XENA) { 624 /* all 64M to queue 0 */ 625 PIF_WCSR(RX_QUEUE_CFG, MC_QUEUE(0, 64)); 626 } else { 627 /* all 32M to queue 0 */ 628 PIF_WCSR(RX_QUEUE_CFG, MC_QUEUE(0, 32)); 629 } 630 631 /* 20, setup RLDRAM parameters */ 632 /* do not touch it for now */ 633 634 /* 21, setup pause frame thresholds */ 635 /* so not touch the defaults */ 636 /* XXX - must 0xff be written as stated in the manual? */ 637 638 /* 22, configure RED */ 639 /* we do not want to drop packets, so ignore */ 640 641 /* 23, initiate RLDRAM */ 642 val = PIF_RCSR(MC_RLDRAM_MRS); 643 val |= MC_QUEUE_SIZE_ENABLE|MC_RLDRAM_MRS_ENABLE; 644 PIF_WCSR(MC_RLDRAM_MRS, val); 645 DELAY(1000); 646 647 /* 648 * Setup interrupt policies. 649 */ 650 /* 40, Transmit interrupts */ 651 PIF_WCSR(TTI_DATA1_MEM, TX_TIMER_VAL(0x1ff) | TX_TIMER_AC | 652 TX_URNG_A(5) | TX_URNG_B(20) | TX_URNG_C(48)); 653 PIF_WCSR(TTI_DATA2_MEM, 654 TX_UFC_A(25) | TX_UFC_B(64) | TX_UFC_C(128) | TX_UFC_D(512)); 655 PIF_WCSR(TTI_COMMAND_MEM, TTI_CMD_MEM_WE | TTI_CMD_MEM_STROBE); 656 while (PIF_RCSR(TTI_COMMAND_MEM) & TTI_CMD_MEM_STROBE) 657 ; 658 659 /* 41, Receive interrupts */ 660 PIF_WCSR(RTI_DATA1_MEM, RX_TIMER_VAL(0x800) | RX_TIMER_AC | 661 RX_URNG_A(5) | RX_URNG_B(20) | RX_URNG_C(50)); 662 PIF_WCSR(RTI_DATA2_MEM, 663 RX_UFC_A(64) | RX_UFC_B(128) | RX_UFC_C(256) | RX_UFC_D(512)); 664 PIF_WCSR(RTI_COMMAND_MEM, RTI_CMD_MEM_WE | RTI_CMD_MEM_STROBE); 665 while (PIF_RCSR(RTI_COMMAND_MEM) & RTI_CMD_MEM_STROBE) 666 ; 667 668 /* 669 * Setup media stuff. 670 */ 671 ifmedia_init(&sc->xena_media, IFM_IMASK, xge_xgmii_mediachange, 672 xge_ifmedia_status); 673 ifmedia_add(&sc->xena_media, IFM_ETHER|IFM_10G_SR, 0, NULL); 674 ifmedia_set(&sc->xena_media, IFM_ETHER|IFM_10G_SR); 675 676 ifp = &sc->sc_arpcom.ac_if; 677 strlcpy(ifp->if_xname, XNAME, IFNAMSIZ); 678 memcpy(sc->sc_arpcom.ac_enaddr, enaddr, ETHER_ADDR_LEN); 679 ifp->if_baudrate = IF_Gbps(10); 680 ifp->if_softc = sc; 681 ifp->if_flags = IFF_BROADCAST | IFF_SIMPLEX | IFF_MULTICAST; 682 ifp->if_ioctl = xge_ioctl; 683 ifp->if_start = xge_start; 684 ifp->if_hardmtu = XGE_MAX_MTU; 685 IFQ_SET_MAXLEN(&ifp->if_snd, NTXDESCS - 1); 686 687 ifp->if_capabilities = IFCAP_VLAN_MTU | IFCAP_CSUM_IPv4 | 688 IFCAP_CSUM_TCPv4 | IFCAP_CSUM_UDPv4; 689 690 #if NVLAN > 0 691 ifp->if_capabilities |= IFCAP_VLAN_HWTAGGING; 692 #endif 693 694 /* 695 * Attach the interface. 696 */ 697 if_attach(ifp); 698 ether_ifattach(ifp); 699 700 /* 701 * Setup interrupt vector before initializing. 702 */ 703 if (pci_intr_map(pa, &ih)) { 704 printf(": unable to map interrupt\n"); 705 return; 706 } 707 intrstr = pci_intr_string(pc, ih); 708 if ((sc->sc_ih = 709 pci_intr_establish(pc, ih, IPL_NET, xge_intr, sc, XNAME)) == NULL) { 710 printf(": unable to establish interrupt at %s\n", 711 intrstr ? intrstr : "<unknown>"); 712 return; 713 } 714 printf(": %s, address %s\n", intrstr, ether_sprintf(enaddr)); 715 } 716 717 void 718 xge_ifmedia_status(struct ifnet *ifp, struct ifmediareq *ifmr) 719 { 720 struct xge_softc *sc = ifp->if_softc; 721 uint64_t reg; 722 723 ifmr->ifm_status = IFM_AVALID; 724 ifmr->ifm_active = IFM_ETHER|IFM_10G_SR; 725 726 reg = PIF_RCSR(ADAPTER_STATUS); 727 if ((reg & (RMAC_REMOTE_FAULT|RMAC_LOCAL_FAULT)) == 0) 728 ifmr->ifm_status |= IFM_ACTIVE; 729 } 730 731 int 732 xge_xgmii_mediachange(struct ifnet *ifp) 733 { 734 return (0); 735 } 736 737 void 738 xge_enable(struct xge_softc *sc) 739 { 740 uint64_t val; 741 742 /* 2, enable adapter */ 743 val = PIF_RCSR(ADAPTER_CONTROL); 744 val |= ADAPTER_EN; 745 PIF_WCSR(ADAPTER_CONTROL, val); 746 747 /* 3, light the card enable led */ 748 val = PIF_RCSR(ADAPTER_CONTROL); 749 val |= LED_ON; 750 PIF_WCSR(ADAPTER_CONTROL, val); 751 #ifdef XGE_DEBUG 752 printf("%s: link up\n", XNAME); 753 #endif 754 } 755 756 int 757 xge_init(struct ifnet *ifp) 758 { 759 struct xge_softc *sc = ifp->if_softc; 760 uint64_t val; 761 int s; 762 763 s = splnet(); 764 765 /* 766 * Cancel any pending I/O 767 */ 768 xge_stop(ifp, 0); 769 770 /* 31+32, setup MAC config */ 771 PIF_WKEY(MAC_CFG, TMAC_EN|RMAC_EN|TMAC_APPEND_PAD|RMAC_STRIP_FCS| 772 RMAC_BCAST_EN|RMAC_DISCARD_PFRM); 773 774 DELAY(1000); 775 776 /* 54, ensure that the adapter is 'quiescent' */ 777 val = PIF_RCSR(ADAPTER_STATUS); 778 if ((val & QUIESCENT) != QUIESCENT) { 779 #if 0 780 char buf[200]; 781 #endif 782 printf("%s: adapter not quiescent, aborting\n", XNAME); 783 val = (val & QUIESCENT) ^ QUIESCENT; 784 #if 0 785 bitmask_snprintf(val, QUIESCENT_BMSK, buf, sizeof buf); 786 printf("%s: ADAPTER_STATUS missing bits %s\n", XNAME, buf); 787 #endif 788 splx(s); 789 return (1); 790 } 791 792 if (!(ifp->if_capabilities & IFCAP_VLAN_HWTAGGING)) { 793 /* disable VLAN tag stripping */ 794 val = PIF_RCSR(RX_PA_CFG); 795 val &= ~STRIP_VLAN_TAG; 796 PIF_WCSR(RX_PA_CFG, val); 797 } 798 799 /* set MRU */ 800 PIF_WCSR(RMAC_MAX_PYLD_LEN, RMAC_PYLD_LEN(XGE_MAX_FRAMELEN)); 801 802 /* 56, enable the transmit laser */ 803 val = PIF_RCSR(ADAPTER_CONTROL); 804 val |= EOI_TX_ON; 805 PIF_WCSR(ADAPTER_CONTROL, val); 806 807 xge_enable(sc); 808 809 /* 810 * Enable all interrupts 811 */ 812 PIF_WCSR(TX_TRAFFIC_MASK, 0); 813 PIF_WCSR(RX_TRAFFIC_MASK, 0); 814 PIF_WCSR(TXPIC_INT_MASK, 0); 815 PIF_WCSR(RXPIC_INT_MASK, 0); 816 817 PIF_WCSR(MAC_INT_MASK, MAC_TMAC_INT); /* only from RMAC */ 818 PIF_WCSR(MAC_RMAC_ERR_REG, RMAC_LINK_STATE_CHANGE_INT); 819 PIF_WCSR(MAC_RMAC_ERR_MASK, ~RMAC_LINK_STATE_CHANGE_INT); 820 PIF_WCSR(GENERAL_INT_MASK, 0); 821 822 xge_setpromisc(sc); 823 824 xge_setmulti(sc); 825 826 /* Done... */ 827 ifp->if_flags |= IFF_RUNNING; 828 ifq_clr_oactive(&ifp->if_snd); 829 830 splx(s); 831 832 return (0); 833 } 834 835 void 836 xge_stop(struct ifnet *ifp, int disable) 837 { 838 struct xge_softc *sc = ifp->if_softc; 839 uint64_t val; 840 841 ifp->if_flags &= ~IFF_RUNNING; 842 ifq_clr_oactive(&ifp->if_snd); 843 844 val = PIF_RCSR(ADAPTER_CONTROL); 845 val &= ~ADAPTER_EN; 846 PIF_WCSR(ADAPTER_CONTROL, val); 847 848 while ((PIF_RCSR(ADAPTER_STATUS) & QUIESCENT) != QUIESCENT) 849 ; 850 } 851 852 int 853 xge_intr(void *pv) 854 { 855 struct xge_softc *sc = pv; 856 struct txd *txd; 857 struct ifnet *ifp = &sc->sc_arpcom.ac_if; 858 struct mbuf_list ml = MBUF_LIST_INITIALIZER(); 859 bus_dmamap_t dmp; 860 uint64_t val; 861 int i, lasttx, plen; 862 863 val = PIF_RCSR(GENERAL_INT_STATUS); 864 if (val == 0) 865 return (0); /* no interrupt here */ 866 867 PIF_WCSR(GENERAL_INT_STATUS, val); 868 869 if ((val = PIF_RCSR(MAC_RMAC_ERR_REG)) & RMAC_LINK_STATE_CHANGE_INT) { 870 /* Wait for quiescence */ 871 #ifdef XGE_DEBUG 872 printf("%s: link down\n", XNAME); 873 #endif 874 while ((PIF_RCSR(ADAPTER_STATUS) & QUIESCENT) != QUIESCENT) 875 ; 876 PIF_WCSR(MAC_RMAC_ERR_REG, RMAC_LINK_STATE_CHANGE_INT); 877 878 val = PIF_RCSR(ADAPTER_STATUS); 879 if ((val & (RMAC_REMOTE_FAULT|RMAC_LOCAL_FAULT)) == 0) 880 xge_enable(sc); /* Only if link restored */ 881 } 882 883 if ((val = PIF_RCSR(TX_TRAFFIC_INT))) 884 PIF_WCSR(TX_TRAFFIC_INT, val); /* clear interrupt bits */ 885 /* 886 * Collect sent packets. 887 */ 888 lasttx = sc->sc_lasttx; 889 while ((i = NEXTTX(sc->sc_lasttx)) != sc->sc_nexttx) { 890 txd = sc->sc_txd[i]; 891 dmp = sc->sc_txm[i]; 892 893 bus_dmamap_sync(sc->sc_dmat, dmp, 0, 894 dmp->dm_mapsize, 895 BUS_DMASYNC_POSTREAD|BUS_DMASYNC_POSTWRITE); 896 897 if (txd->txd_control1 & TXD_CTL1_OWN) { 898 bus_dmamap_sync(sc->sc_dmat, dmp, 0, 899 dmp->dm_mapsize, BUS_DMASYNC_PREREAD); 900 break; 901 } 902 bus_dmamap_unload(sc->sc_dmat, dmp); 903 m_freem(sc->sc_txb[i]); 904 ifp->if_opackets++; 905 sc->sc_lasttx = i; 906 } 907 908 if (sc->sc_lasttx != lasttx) 909 ifq_clr_oactive(&ifp->if_snd); 910 911 /* Try to get more packets on the wire */ 912 xge_start(ifp); 913 914 /* clear interrupt bits */ 915 if ((val = PIF_RCSR(RX_TRAFFIC_INT))) 916 PIF_WCSR(RX_TRAFFIC_INT, val); 917 918 for (;;) { 919 struct rxdesc *rxd; 920 struct mbuf *m; 921 922 XGE_RXSYNC(sc->sc_nextrx, 923 BUS_DMASYNC_POSTREAD|BUS_DMASYNC_POSTWRITE); 924 925 rxd = XGE_RXD(sc->sc_nextrx); 926 if (rxd->rxd_control1 & RXD_CTL1_OWN) { 927 XGE_RXSYNC(sc->sc_nextrx, BUS_DMASYNC_PREREAD); 928 break; 929 } 930 931 /* got a packet */ 932 m = sc->sc_rxb[sc->sc_nextrx]; 933 #if RX_MODE == RX_MODE_1 934 plen = m->m_len = RXD_CTL2_BUF0SIZ(rxd->rxd_control2); 935 #elif RX_MODE == RX_MODE_3 936 #error Fix rxmodes in xge_intr 937 #elif RX_MODE == RX_MODE_5 938 plen = m->m_len = RXD_CTL2_BUF0SIZ(rxd->rxd_control2); 939 plen += m->m_next->m_len = RXD_CTL2_BUF1SIZ(rxd->rxd_control2); 940 plen += m->m_next->m_next->m_len = 941 RXD_CTL2_BUF2SIZ(rxd->rxd_control2); 942 plen += m->m_next->m_next->m_next->m_len = 943 RXD_CTL3_BUF3SIZ(rxd->rxd_control3); 944 plen += m->m_next->m_next->m_next->m_next->m_len = 945 RXD_CTL3_BUF4SIZ(rxd->rxd_control3); 946 #endif 947 m->m_pkthdr.len = plen; 948 949 val = rxd->rxd_control1; 950 951 if (xge_add_rxbuf(sc, sc->sc_nextrx)) { 952 /* Failed, recycle this mbuf */ 953 #if RX_MODE == RX_MODE_1 954 rxd->rxd_control2 = RXD_MKCTL2(MCLBYTES, 0, 0); 955 rxd->rxd_control1 = RXD_CTL1_OWN; 956 #elif RX_MODE == RX_MODE_3 957 #elif RX_MODE == RX_MODE_5 958 #endif 959 XGE_RXSYNC(sc->sc_nextrx, 960 BUS_DMASYNC_PREREAD|BUS_DMASYNC_PREWRITE); 961 ifp->if_ierrors++; 962 break; 963 } 964 965 if (RXD_CTL1_PROTOS(val) & RXD_CTL1_P_IPv4) 966 m->m_pkthdr.csum_flags |= M_IPV4_CSUM_IN_OK; 967 if (RXD_CTL1_PROTOS(val) & RXD_CTL1_P_TCP) 968 m->m_pkthdr.csum_flags |= M_TCP_CSUM_IN_OK; 969 if (RXD_CTL1_PROTOS(val) & RXD_CTL1_P_UDP) 970 m->m_pkthdr.csum_flags |= M_UDP_CSUM_IN_OK; 971 972 #if NVLAN > 0 973 if (RXD_CTL1_PROTOS(val) & RXD_CTL1_P_VLAN) { 974 m->m_pkthdr.ether_vtag = 975 RXD_CTL2_VLANTAG(rxd->rxd_control2); 976 m->m_flags |= M_VLANTAG; 977 } 978 #endif 979 980 ml_enqueue(&ml, m); 981 982 if (++sc->sc_nextrx == NRXREAL) 983 sc->sc_nextrx = 0; 984 } 985 986 if_input(ifp, &ml); 987 988 return (1); 989 } 990 991 int 992 xge_ioctl(struct ifnet *ifp, u_long cmd, caddr_t data) 993 { 994 struct xge_softc *sc = ifp->if_softc; 995 struct ifreq *ifr = (struct ifreq *) data; 996 int s, error = 0; 997 998 s = splnet(); 999 1000 switch (cmd) { 1001 case SIOCSIFADDR: 1002 ifp->if_flags |= IFF_UP; 1003 if (!(ifp->if_flags & IFF_RUNNING)) 1004 xge_init(ifp); 1005 break; 1006 1007 case SIOCSIFFLAGS: 1008 if (ifp->if_flags & IFF_UP) { 1009 if (ifp->if_flags & IFF_RUNNING && 1010 (ifp->if_flags ^ sc->xge_if_flags) & 1011 IFF_PROMISC) { 1012 xge_setpromisc(sc); 1013 } else { 1014 if (!(ifp->if_flags & IFF_RUNNING)) 1015 xge_init(ifp); 1016 } 1017 } else { 1018 if (ifp->if_flags & IFF_RUNNING) 1019 xge_stop(ifp, 1); 1020 } 1021 sc->xge_if_flags = ifp->if_flags; 1022 break; 1023 1024 case SIOCGIFMEDIA: 1025 case SIOCSIFMEDIA: 1026 error = ifmedia_ioctl(ifp, ifr, &sc->xena_media, cmd); 1027 break; 1028 1029 default: 1030 error = ether_ioctl(ifp, &sc->sc_arpcom, cmd, data); 1031 } 1032 1033 if (error == ENETRESET) { 1034 if (ifp->if_flags & IFF_RUNNING) 1035 xge_setmulti(sc); 1036 error = 0; 1037 } 1038 1039 splx(s); 1040 return (error); 1041 } 1042 1043 void 1044 xge_setmulti(struct xge_softc *sc) 1045 { 1046 struct ifnet *ifp = &sc->sc_arpcom.ac_if; 1047 struct arpcom *ac = &sc->sc_arpcom; 1048 struct ether_multi *enm; 1049 struct ether_multistep step; 1050 int i, numaddr = 1; /* first slot used for card unicast address */ 1051 uint64_t val; 1052 1053 if (ac->ac_multirangecnt > 0) 1054 goto allmulti; 1055 1056 ETHER_FIRST_MULTI(step, ac, enm); 1057 while (enm != NULL) { 1058 if (numaddr == MAX_MCAST_ADDR) 1059 goto allmulti; 1060 for (val = 0, i = 0; i < ETHER_ADDR_LEN; i++) { 1061 val <<= 8; 1062 val |= enm->enm_addrlo[i]; 1063 } 1064 PIF_WCSR(RMAC_ADDR_DATA0_MEM, val << 16); 1065 PIF_WCSR(RMAC_ADDR_DATA1_MEM, 0xFFFFFFFFFFFFFFFFULL); 1066 PIF_WCSR(RMAC_ADDR_CMD_MEM, RMAC_ADDR_CMD_MEM_WE| 1067 RMAC_ADDR_CMD_MEM_STR|RMAC_ADDR_CMD_MEM_OFF(numaddr)); 1068 while (PIF_RCSR(RMAC_ADDR_CMD_MEM) & RMAC_ADDR_CMD_MEM_STR) 1069 ; 1070 numaddr++; 1071 ETHER_NEXT_MULTI(step, enm); 1072 } 1073 /* set the remaining entries to the broadcast address */ 1074 for (i = numaddr; i < MAX_MCAST_ADDR; i++) { 1075 PIF_WCSR(RMAC_ADDR_DATA0_MEM, 0xffffffffffff0000ULL); 1076 PIF_WCSR(RMAC_ADDR_DATA1_MEM, 0xFFFFFFFFFFFFFFFFULL); 1077 PIF_WCSR(RMAC_ADDR_CMD_MEM, RMAC_ADDR_CMD_MEM_WE| 1078 RMAC_ADDR_CMD_MEM_STR|RMAC_ADDR_CMD_MEM_OFF(i)); 1079 while (PIF_RCSR(RMAC_ADDR_CMD_MEM) & RMAC_ADDR_CMD_MEM_STR) 1080 ; 1081 } 1082 ifp->if_flags &= ~IFF_ALLMULTI; 1083 return; 1084 1085 allmulti: 1086 /* Just receive everything with the multicast bit set */ 1087 ifp->if_flags |= IFF_ALLMULTI; 1088 PIF_WCSR(RMAC_ADDR_DATA0_MEM, 0x8000000000000000ULL); 1089 PIF_WCSR(RMAC_ADDR_DATA1_MEM, 0xF000000000000000ULL); 1090 PIF_WCSR(RMAC_ADDR_CMD_MEM, RMAC_ADDR_CMD_MEM_WE| 1091 RMAC_ADDR_CMD_MEM_STR|RMAC_ADDR_CMD_MEM_OFF(1)); 1092 while (PIF_RCSR(RMAC_ADDR_CMD_MEM) & RMAC_ADDR_CMD_MEM_STR) 1093 ; 1094 } 1095 1096 void 1097 xge_setpromisc(struct xge_softc *sc) 1098 { 1099 struct ifnet *ifp = &sc->sc_arpcom.ac_if; 1100 uint64_t val; 1101 1102 val = PIF_RCSR(MAC_CFG); 1103 1104 if (ifp->if_flags & IFF_PROMISC) 1105 val |= RMAC_PROM_EN; 1106 else 1107 val &= ~RMAC_PROM_EN; 1108 1109 PIF_WCSR(MAC_CFG, val); 1110 } 1111 1112 void 1113 xge_start(struct ifnet *ifp) 1114 { 1115 struct xge_softc *sc = ifp->if_softc; 1116 struct txd *txd = NULL; /* XXX - gcc */ 1117 bus_dmamap_t dmp; 1118 struct mbuf *m; 1119 uint64_t par, lcr; 1120 int nexttx = 0, ntxd, error, i; 1121 1122 if (!(ifp->if_flags & IFF_RUNNING) || ifq_is_oactive(&ifp->if_snd)) 1123 return; 1124 1125 par = lcr = 0; 1126 for (;;) { 1127 m = ifq_deq_begin(&ifp->if_snd); 1128 if (m == NULL) 1129 break; /* out of packets */ 1130 1131 if (sc->sc_nexttx == sc->sc_lasttx) { 1132 ifq_deq_rollback(&ifp->if_snd, m); 1133 break; /* No more space */ 1134 } 1135 1136 nexttx = sc->sc_nexttx; 1137 dmp = sc->sc_txm[nexttx]; 1138 1139 if ((error = bus_dmamap_load_mbuf(sc->sc_dmat, dmp, m, 1140 BUS_DMA_WRITE|BUS_DMA_NOWAIT)) != 0) { 1141 ifq_deq_rollback(&ifp->if_snd, m); 1142 printf("%s: bus_dmamap_load_mbuf error %d\n", 1143 XNAME, error); 1144 break; 1145 } 1146 ifq_deq_commit(&ifp->if_snd, m); 1147 1148 bus_dmamap_sync(sc->sc_dmat, dmp, 0, dmp->dm_mapsize, 1149 BUS_DMASYNC_PREWRITE); 1150 1151 txd = sc->sc_txd[nexttx]; 1152 sc->sc_txb[nexttx] = m; 1153 for (i = 0; i < dmp->dm_nsegs; i++) { 1154 if (dmp->dm_segs[i].ds_len == 0) 1155 continue; 1156 txd->txd_control1 = dmp->dm_segs[i].ds_len; 1157 txd->txd_control2 = 0; 1158 txd->txd_bufaddr = dmp->dm_segs[i].ds_addr; 1159 txd++; 1160 } 1161 ntxd = txd - sc->sc_txd[nexttx] - 1; 1162 txd = sc->sc_txd[nexttx]; 1163 txd->txd_control1 |= TXD_CTL1_OWN|TXD_CTL1_GCF; 1164 txd->txd_control2 = TXD_CTL2_UTIL; 1165 1166 #if NVLAN > 0 1167 if (m->m_flags & M_VLANTAG) { 1168 txd->txd_control2 |= TXD_CTL2_VLANE; 1169 txd->txd_control2 |= 1170 TXD_CTL2_VLANT(m->m_pkthdr.ether_vtag); 1171 } 1172 #endif 1173 1174 if (m->m_pkthdr.csum_flags & M_IPV4_CSUM_OUT) 1175 txd->txd_control2 |= TXD_CTL2_CIPv4; 1176 if (m->m_pkthdr.csum_flags & M_TCP_CSUM_OUT) 1177 txd->txd_control2 |= TXD_CTL2_CTCP; 1178 if (m->m_pkthdr.csum_flags & M_UDP_CSUM_OUT) 1179 txd->txd_control2 |= TXD_CTL2_CUDP; 1180 1181 txd[ntxd].txd_control1 |= TXD_CTL1_GCL; 1182 1183 bus_dmamap_sync(sc->sc_dmat, dmp, 0, dmp->dm_mapsize, 1184 BUS_DMASYNC_PREREAD|BUS_DMASYNC_PREWRITE); 1185 1186 par = sc->sc_txdp[nexttx]; 1187 lcr = TXDL_NUMTXD(ntxd) | TXDL_LGC_FIRST | TXDL_LGC_LAST; 1188 TXP_WCSR(TXDL_PAR, par); 1189 TXP_WCSR(TXDL_LCR, lcr); 1190 1191 #if NBPFILTER > 0 1192 if (ifp->if_bpf) 1193 bpf_mtap_ether(ifp->if_bpf, m, BPF_DIRECTION_OUT); 1194 #endif /* NBPFILTER > 0 */ 1195 1196 sc->sc_nexttx = NEXTTX(nexttx); 1197 } 1198 } 1199 1200 /* 1201 * Allocate DMA memory for transmit descriptor fragments. 1202 * Only one map is used for all descriptors. 1203 */ 1204 int 1205 xge_alloc_txmem(struct xge_softc *sc) 1206 { 1207 struct txd *txp; 1208 bus_dma_segment_t seg; 1209 bus_addr_t txdp; 1210 caddr_t kva; 1211 int i, rseg, state; 1212 1213 #define TXMAPSZ (NTXDESCS*NTXFRAGS*sizeof(struct txd)) 1214 state = 0; 1215 if (bus_dmamem_alloc(sc->sc_dmat, TXMAPSZ, PAGE_SIZE, 0, 1216 &seg, 1, &rseg, BUS_DMA_NOWAIT)) 1217 goto err; 1218 state++; 1219 if (bus_dmamem_map(sc->sc_dmat, &seg, rseg, TXMAPSZ, &kva, 1220 BUS_DMA_NOWAIT)) 1221 goto err; 1222 1223 state++; 1224 if (bus_dmamap_create(sc->sc_dmat, TXMAPSZ, 1, TXMAPSZ, 0, 1225 BUS_DMA_NOWAIT, &sc->sc_txmap)) 1226 goto err; 1227 state++; 1228 if (bus_dmamap_load(sc->sc_dmat, sc->sc_txmap, 1229 kva, TXMAPSZ, NULL, BUS_DMA_NOWAIT)) 1230 goto err; 1231 1232 /* setup transmit array pointers */ 1233 txp = (struct txd *)kva; 1234 txdp = seg.ds_addr; 1235 for (i = 0; i < NTXDESCS; i++) { 1236 sc->sc_txd[i] = txp; 1237 sc->sc_txdp[i] = txdp; 1238 txp += NTXFRAGS; 1239 txdp += (NTXFRAGS * sizeof(struct txd)); 1240 } 1241 1242 return (0); 1243 1244 err: 1245 if (state > 2) 1246 bus_dmamap_destroy(sc->sc_dmat, sc->sc_txmap); 1247 if (state > 1) 1248 bus_dmamem_unmap(sc->sc_dmat, kva, TXMAPSZ); 1249 if (state > 0) 1250 bus_dmamem_free(sc->sc_dmat, &seg, rseg); 1251 return (ENOBUFS); 1252 } 1253 1254 /* 1255 * Allocate DMA memory for receive descriptor, 1256 * only one map is used for all descriptors. 1257 * link receive descriptor pages together. 1258 */ 1259 int 1260 xge_alloc_rxmem(struct xge_softc *sc) 1261 { 1262 struct rxd_4k *rxpp; 1263 bus_dma_segment_t seg; 1264 caddr_t kva; 1265 int i, rseg, state; 1266 1267 /* sanity check */ 1268 if (sizeof(struct rxd_4k) != XGE_PAGE) { 1269 printf("bad compiler struct alignment, %d != %d\n", 1270 (int)sizeof(struct rxd_4k), XGE_PAGE); 1271 return (EINVAL); 1272 } 1273 1274 state = 0; 1275 if (bus_dmamem_alloc(sc->sc_dmat, RXMAPSZ, PAGE_SIZE, 0, 1276 &seg, 1, &rseg, BUS_DMA_NOWAIT)) 1277 goto err; 1278 state++; 1279 if (bus_dmamem_map(sc->sc_dmat, &seg, rseg, RXMAPSZ, &kva, 1280 BUS_DMA_NOWAIT)) 1281 goto err; 1282 1283 state++; 1284 if (bus_dmamap_create(sc->sc_dmat, RXMAPSZ, 1, RXMAPSZ, 0, 1285 BUS_DMA_NOWAIT, &sc->sc_rxmap)) 1286 goto err; 1287 state++; 1288 if (bus_dmamap_load(sc->sc_dmat, sc->sc_rxmap, 1289 kva, RXMAPSZ, NULL, BUS_DMA_NOWAIT)) 1290 goto err; 1291 1292 /* setup receive page link pointers */ 1293 for (rxpp = (struct rxd_4k *)kva, i = 0; i < NRXPAGES; i++, rxpp++) { 1294 sc->sc_rxd_4k[i] = rxpp; 1295 rxpp->r4_next = (uint64_t)sc->sc_rxmap->dm_segs[0].ds_addr + 1296 (i*sizeof(struct rxd_4k)) + sizeof(struct rxd_4k); 1297 } 1298 sc->sc_rxd_4k[NRXPAGES-1]->r4_next = 1299 (uint64_t)sc->sc_rxmap->dm_segs[0].ds_addr; 1300 1301 return (0); 1302 1303 err: 1304 if (state > 2) 1305 bus_dmamap_destroy(sc->sc_dmat, sc->sc_rxmap); 1306 if (state > 1) 1307 bus_dmamem_unmap(sc->sc_dmat, kva, RXMAPSZ); 1308 if (state > 0) 1309 bus_dmamem_free(sc->sc_dmat, &seg, rseg); 1310 return (ENOBUFS); 1311 } 1312 1313 1314 /* 1315 * Add a new mbuf chain to descriptor id. 1316 */ 1317 int 1318 xge_add_rxbuf(struct xge_softc *sc, int id) 1319 { 1320 struct rxdesc *rxd; 1321 struct mbuf *m[5]; 1322 int page, desc, error; 1323 #if RX_MODE == RX_MODE_5 1324 int i; 1325 #endif 1326 1327 page = id/NDESC_BUFMODE; 1328 desc = id%NDESC_BUFMODE; 1329 1330 rxd = &sc->sc_rxd_4k[page]->r4_rxd[desc]; 1331 1332 /* 1333 * Allocate mbufs. 1334 * Currently five mbufs and two clusters are used, 1335 * the hardware will put (ethernet, ip, tcp/udp) headers in 1336 * their own buffer and the clusters are only used for data. 1337 */ 1338 #if RX_MODE == RX_MODE_1 1339 MGETHDR(m[0], M_DONTWAIT, MT_DATA); 1340 if (m[0] == NULL) 1341 return (ENOBUFS); 1342 MCLGETI(m[0], M_DONTWAIT, NULL, XGE_MAX_FRAMELEN + ETHER_ALIGN); 1343 if ((m[0]->m_flags & M_EXT) == 0) { 1344 m_freem(m[0]); 1345 return (ENOBUFS); 1346 } 1347 m[0]->m_len = m[0]->m_pkthdr.len = XGE_MAX_FRAMELEN + ETHER_ALIGN; 1348 #elif RX_MODE == RX_MODE_3 1349 #error missing rxmode 3. 1350 #elif RX_MODE == RX_MODE_5 1351 MGETHDR(m[0], M_DONTWAIT, MT_DATA); 1352 for (i = 1; i < 5; i++) { 1353 MGET(m[i], M_DONTWAIT, MT_DATA); 1354 } 1355 if (m[3]) 1356 MCLGET(m[3], M_DONTWAIT); 1357 if (m[4]) 1358 MCLGET(m[4], M_DONTWAIT); 1359 if (!m[0] || !m[1] || !m[2] || !m[3] || !m[4] || 1360 ((m[3]->m_flags & M_EXT) == 0) || ((m[4]->m_flags & M_EXT) == 0)) { 1361 /* Out of something */ 1362 for (i = 0; i < 5; i++) 1363 if (m[i] != NULL) 1364 m_free(m[i]); 1365 return (ENOBUFS); 1366 } 1367 /* Link'em together */ 1368 m[0]->m_next = m[1]; 1369 m[1]->m_next = m[2]; 1370 m[2]->m_next = m[3]; 1371 m[3]->m_next = m[4]; 1372 #else 1373 #error bad mode RX_MODE 1374 #endif 1375 1376 if (sc->sc_rxb[id]) 1377 bus_dmamap_unload(sc->sc_dmat, sc->sc_rxm[id]); 1378 sc->sc_rxb[id] = m[0]; 1379 1380 m_adj(m[0], ETHER_ALIGN); 1381 1382 error = bus_dmamap_load_mbuf(sc->sc_dmat, sc->sc_rxm[id], m[0], 1383 BUS_DMA_READ|BUS_DMA_NOWAIT); 1384 if (error) 1385 return (error); 1386 bus_dmamap_sync(sc->sc_dmat, sc->sc_rxm[id], 0, 1387 sc->sc_rxm[id]->dm_mapsize, BUS_DMASYNC_PREREAD); 1388 1389 #if RX_MODE == RX_MODE_1 1390 rxd->rxd_control2 = RXD_MKCTL2(m[0]->m_len, 0, 0); 1391 rxd->rxd_buf0 = (uint64_t)sc->sc_rxm[id]->dm_segs[0].ds_addr; 1392 rxd->rxd_control1 = RXD_CTL1_OWN; 1393 #elif RX_MODE == RX_MODE_3 1394 #elif RX_MODE == RX_MODE_5 1395 rxd->rxd_control3 = RXD_MKCTL3(0, m[3]->m_len, m[4]->m_len); 1396 rxd->rxd_control2 = RXD_MKCTL2(m[0]->m_len, m[1]->m_len, m[2]->m_len); 1397 rxd->rxd_buf0 = (uint64_t)sc->sc_rxm[id]->dm_segs[0].ds_addr; 1398 rxd->rxd_buf1 = (uint64_t)sc->sc_rxm[id]->dm_segs[1].ds_addr; 1399 rxd->rxd_buf2 = (uint64_t)sc->sc_rxm[id]->dm_segs[2].ds_addr; 1400 rxd->rxd_buf3 = (uint64_t)sc->sc_rxm[id]->dm_segs[3].ds_addr; 1401 rxd->rxd_buf4 = (uint64_t)sc->sc_rxm[id]->dm_segs[4].ds_addr; 1402 rxd->rxd_control1 = RXD_CTL1_OWN; 1403 #endif 1404 1405 XGE_RXSYNC(id, BUS_DMASYNC_PREREAD|BUS_DMASYNC_PREWRITE); 1406 return (0); 1407 } 1408 1409 /* 1410 * This magic comes from the FreeBSD driver. 1411 */ 1412 int 1413 xge_setup_xgxs_xena(struct xge_softc *sc) 1414 { 1415 int i; 1416 1417 for (i = 0; i < nitems(xge_xena_dtx_cfg); i++) { 1418 PIF_WCSR(DTX_CONTROL, xge_xena_dtx_cfg[i]); 1419 DELAY(100); 1420 } 1421 1422 return (0); 1423 } 1424 1425 int 1426 xge_setup_xgxs_herc(struct xge_softc *sc) 1427 { 1428 int i; 1429 1430 for (i = 0; i < nitems(xge_herc_dtx_cfg); i++) { 1431 PIF_WCSR(DTX_CONTROL, xge_herc_dtx_cfg[i]); 1432 DELAY(100); 1433 } 1434 1435 return (0); 1436 } 1437