1 /* $OpenBSD: if_xge.c,v 1.56 2013/11/26 09:50:33 mpi Exp $ */ 2 /* $NetBSD: if_xge.c,v 1.1 2005/09/09 10:30:27 ragge Exp $ */ 3 4 /* 5 * Copyright (c) 2004, SUNET, Swedish University Computer Network. 6 * All rights reserved. 7 * 8 * Written by Anders Magnusson for SUNET, Swedish University Computer Network. 9 * 10 * Redistribution and use in source and binary forms, with or without 11 * modification, are permitted provided that the following conditions 12 * are met: 13 * 1. Redistributions of source code must retain the above copyright 14 * notice, this list of conditions and the following disclaimer. 15 * 2. Redistributions in binary form must reproduce the above copyright 16 * notice, this list of conditions and the following disclaimer in the 17 * documentation and/or other materials provided with the distribution. 18 * 3. All advertising materials mentioning features or use of this software 19 * must display the following acknowledgement: 20 * This product includes software developed for the NetBSD Project by 21 * SUNET, Swedish University Computer Network. 22 * 4. The name of SUNET may not be used to endorse or promote products 23 * derived from this software without specific prior written permission. 24 * 25 * THIS SOFTWARE IS PROVIDED BY SUNET ``AS IS'' AND 26 * ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED 27 * TO, THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR 28 * PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL SUNET 29 * BE LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR 30 * CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF 31 * SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS 32 * INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN 33 * CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) 34 * ARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE 35 * POSSIBILITY OF SUCH DAMAGE. 36 */ 37 38 /* 39 * Driver for the Neterion Xframe Ten Gigabit Ethernet controller. 40 */ 41 42 #include "bpfilter.h" 43 #include "vlan.h" 44 45 #include <sys/param.h> 46 #include <sys/systm.h> 47 #include <sys/sockio.h> 48 #include <sys/mbuf.h> 49 #include <sys/malloc.h> 50 #include <sys/kernel.h> 51 #include <sys/socket.h> 52 #include <sys/device.h> 53 54 #include <net/if.h> 55 #include <net/if_dl.h> 56 #include <net/if_media.h> 57 58 #ifdef INET 59 #include <netinet/in.h> 60 #include <netinet/in_systm.h> 61 #include <netinet/ip.h> 62 #include <netinet/if_ether.h> 63 #include <netinet/tcp.h> 64 #include <netinet/udp.h> 65 #endif 66 67 #if NVLAN > 0 68 #include <net/if_types.h> 69 #include <net/if_vlan_var.h> 70 #endif 71 72 #if NBPFILTER > 0 73 #include <net/bpf.h> 74 #endif 75 76 #include <machine/bus.h> 77 #include <machine/intr.h> 78 #include <machine/endian.h> 79 80 #include <dev/mii/mii.h> 81 #include <dev/mii/miivar.h> 82 83 #include <dev/pci/pcivar.h> 84 #include <dev/pci/pcireg.h> 85 #include <dev/pci/pcidevs.h> 86 87 #include <sys/lock.h> 88 89 #include <dev/pci/if_xgereg.h> 90 91 /* Xframe chipset revisions */ 92 #define XGE_TYPE_XENA 1 /* Xframe */ 93 #define XGE_TYPE_HERC 2 /* Xframe-II */ 94 95 #define XGE_PCISIZE_XENA 26 96 #define XGE_PCISIZE_HERC 64 97 98 /* 99 * Some tunable constants, tune with care! 100 */ 101 #define RX_MODE RX_MODE_1 /* Receive mode (buffer usage, see below) */ 102 #define NRXDESCS 1016 /* # of receive descriptors (requested) */ 103 #define NTXDESCS 2048 /* Number of transmit descriptors */ 104 #define NTXFRAGS 100 /* Max fragments per packet */ 105 106 /* 107 * Receive buffer modes; 1, 3 or 5 buffers. 108 */ 109 #define RX_MODE_1 1 110 #define RX_MODE_3 3 111 #define RX_MODE_5 5 112 113 /* 114 * Use clever macros to avoid a bunch of #ifdef's. 115 */ 116 #define XCONCAT3(x,y,z) x ## y ## z 117 #define CONCAT3(x,y,z) XCONCAT3(x,y,z) 118 #define NDESC_BUFMODE CONCAT3(NDESC_,RX_MODE,BUFMODE) 119 #define rxd_4k CONCAT3(rxd,RX_MODE,_4k) 120 /* XXX */ 121 #if 0 122 #define rxdesc ___CONCAT(rxd,RX_MODE) 123 #endif 124 #define rxdesc rxd1 125 126 #define NEXTTX(x) (((x)+1) % NTXDESCS) 127 #define NRXFRAGS RX_MODE /* hardware imposed frags */ 128 #define NRXPAGES ((NRXDESCS/NDESC_BUFMODE)+1) 129 #define NRXREAL (NRXPAGES*NDESC_BUFMODE) 130 #define RXMAPSZ (NRXPAGES*PAGE_SIZE) 131 132 /* 133 * Magic to fix a bug when the MAC address cannot be read correctly. 134 * This came from the Linux driver. 135 */ 136 static uint64_t fix_mac[] = { 137 0x0060000000000000ULL, 0x0060600000000000ULL, 138 0x0040600000000000ULL, 0x0000600000000000ULL, 139 0x0020600000000000ULL, 0x0060600000000000ULL, 140 0x0020600000000000ULL, 0x0060600000000000ULL, 141 0x0020600000000000ULL, 0x0060600000000000ULL, 142 0x0020600000000000ULL, 0x0060600000000000ULL, 143 0x0020600000000000ULL, 0x0060600000000000ULL, 144 0x0020600000000000ULL, 0x0060600000000000ULL, 145 0x0020600000000000ULL, 0x0060600000000000ULL, 146 0x0020600000000000ULL, 0x0060600000000000ULL, 147 0x0020600000000000ULL, 0x0060600000000000ULL, 148 0x0020600000000000ULL, 0x0060600000000000ULL, 149 0x0020600000000000ULL, 0x0000600000000000ULL, 150 0x0040600000000000ULL, 0x0060600000000000ULL, 151 }; 152 153 /* 154 * Constants to be programmed into Hercules's registers, to configure 155 * the XGXS transciever. 156 */ 157 #define END_SIGN 0x0 158 static uint64_t herc_dtx_cfg[] = { 159 0x8000051536750000ULL, 0x80000515367500E0ULL, 160 0x8000051536750004ULL, 0x80000515367500E4ULL, 161 162 0x80010515003F0000ULL, 0x80010515003F00E0ULL, 163 0x80010515003F0004ULL, 0x80010515003F00E4ULL, 164 165 0x801205150D440000ULL, 0x801205150D4400E0ULL, 166 0x801205150D440004ULL, 0x801205150D4400E4ULL, 167 168 0x80020515F2100000ULL, 0x80020515F21000E0ULL, 169 0x80020515F2100004ULL, 0x80020515F21000E4ULL, 170 171 END_SIGN 172 }; 173 174 struct xge_softc { 175 struct device sc_dev; 176 struct arpcom sc_arpcom; 177 struct ifmedia xena_media; 178 179 void *sc_ih; 180 181 bus_dma_tag_t sc_dmat; 182 bus_space_tag_t sc_st; 183 bus_space_handle_t sc_sh; 184 bus_space_tag_t sc_txt; 185 bus_space_handle_t sc_txh; 186 187 pcireg_t sc_pciregs[16]; 188 189 int xge_type; /* chip type */ 190 int xge_if_flags; 191 192 /* Transmit structures */ 193 struct txd *sc_txd[NTXDESCS]; /* transmit frags array */ 194 bus_addr_t sc_txdp[NTXDESCS]; /* dva of transmit frags */ 195 bus_dmamap_t sc_txm[NTXDESCS]; /* transmit frags map */ 196 struct mbuf *sc_txb[NTXDESCS]; /* transmit mbuf pointer */ 197 int sc_nexttx, sc_lasttx; 198 bus_dmamap_t sc_txmap; /* transmit descriptor map */ 199 200 /* Receive data */ 201 bus_dmamap_t sc_rxmap; /* receive descriptor map */ 202 struct rxd_4k *sc_rxd_4k[NRXPAGES]; /* receive desc pages */ 203 bus_dmamap_t sc_rxm[NRXREAL]; /* receive buffer map */ 204 struct mbuf *sc_rxb[NRXREAL]; /* mbufs on rx descriptors */ 205 int sc_nextrx; /* next descriptor to check */ 206 }; 207 208 #ifdef XGE_DEBUG 209 #define DPRINTF(x) do { if (xgedebug) printf x ; } while (0) 210 #define DPRINTFN(n,x) do { if (xgedebug >= (n)) printf x ; } while (0) 211 int xgedebug = 0; 212 #else 213 #define DPRINTF(x) 214 #define DPRINTFN(n,x) 215 #endif 216 217 int xge_match(struct device *, void *, void *); 218 void xge_attach(struct device *, struct device *, void *); 219 int xge_alloc_txmem(struct xge_softc *); 220 int xge_alloc_rxmem(struct xge_softc *); 221 void xge_start(struct ifnet *); 222 void xge_stop(struct ifnet *, int); 223 int xge_add_rxbuf(struct xge_softc *, int); 224 void xge_setmulti(struct xge_softc *); 225 void xge_setpromisc(struct xge_softc *); 226 int xge_setup_xgxs_xena(struct xge_softc *); 227 int xge_setup_xgxs_herc(struct xge_softc *); 228 int xge_ioctl(struct ifnet *, u_long, caddr_t); 229 int xge_init(struct ifnet *); 230 void xge_ifmedia_status(struct ifnet *, struct ifmediareq *); 231 int xge_xgmii_mediachange(struct ifnet *); 232 void xge_enable(struct xge_softc *); 233 int xge_intr(void *); 234 235 /* 236 * Helpers to address registers. 237 */ 238 #define PIF_WCSR(csr, val) pif_wcsr(sc, csr, val) 239 #define PIF_RCSR(csr) pif_rcsr(sc, csr) 240 #define TXP_WCSR(csr, val) txp_wcsr(sc, csr, val) 241 #define PIF_WKEY(csr, val) pif_wkey(sc, csr, val) 242 243 static inline void 244 pif_wcsr(struct xge_softc *sc, bus_size_t csr, uint64_t val) 245 { 246 uint32_t lval, hval; 247 248 lval = val&0xffffffff; 249 hval = val>>32; 250 251 bus_space_write_4(sc->sc_st, sc->sc_sh, csr, lval); 252 bus_space_write_4(sc->sc_st, sc->sc_sh, csr+4, hval); 253 } 254 255 static inline uint64_t 256 pif_rcsr(struct xge_softc *sc, bus_size_t csr) 257 { 258 uint64_t val, val2; 259 260 val = bus_space_read_4(sc->sc_st, sc->sc_sh, csr); 261 val2 = bus_space_read_4(sc->sc_st, sc->sc_sh, csr+4); 262 val |= (val2 << 32); 263 return (val); 264 } 265 266 static inline void 267 txp_wcsr(struct xge_softc *sc, bus_size_t csr, uint64_t val) 268 { 269 uint32_t lval, hval; 270 271 lval = val&0xffffffff; 272 hval = val>>32; 273 274 bus_space_write_4(sc->sc_txt, sc->sc_txh, csr, lval); 275 bus_space_write_4(sc->sc_txt, sc->sc_txh, csr+4, hval); 276 } 277 278 279 static inline void 280 pif_wkey(struct xge_softc *sc, bus_size_t csr, uint64_t val) 281 { 282 uint32_t lval, hval; 283 284 lval = val&0xffffffff; 285 hval = val>>32; 286 287 if (sc->xge_type == XGE_TYPE_XENA) 288 PIF_WCSR(RMAC_CFG_KEY, RMAC_KEY_VALUE); 289 290 bus_space_write_4(sc->sc_st, sc->sc_sh, csr, lval); 291 292 if (sc->xge_type == XGE_TYPE_XENA) 293 PIF_WCSR(RMAC_CFG_KEY, RMAC_KEY_VALUE); 294 295 bus_space_write_4(sc->sc_st, sc->sc_sh, csr+4, hval); 296 } 297 298 struct cfattach xge_ca = { 299 sizeof(struct xge_softc), xge_match, xge_attach 300 }; 301 302 struct cfdriver xge_cd = { 303 NULL, "xge", DV_IFNET 304 }; 305 306 #define XNAME sc->sc_dev.dv_xname 307 308 #define XGE_RXSYNC(desc, what) \ 309 bus_dmamap_sync(sc->sc_dmat, sc->sc_rxmap, \ 310 (desc/NDESC_BUFMODE) * XGE_PAGE + sizeof(struct rxdesc) * \ 311 (desc%NDESC_BUFMODE), sizeof(struct rxdesc), what) 312 #define XGE_RXD(desc) &sc->sc_rxd_4k[desc/NDESC_BUFMODE]-> \ 313 r4_rxd[desc%NDESC_BUFMODE] 314 315 /* 316 * Non-tunable constants. 317 */ 318 #define XGE_MAX_FRAMELEN 9622 319 #define XGE_MAX_MTU (XGE_MAX_FRAMELEN - ETHER_HDR_LEN - \ 320 ETHER_CRC_LEN - ETHER_VLAN_ENCAP_LEN) 321 322 const struct pci_matchid xge_devices[] = { 323 { PCI_VENDOR_NETERION, PCI_PRODUCT_NETERION_XFRAME }, 324 { PCI_VENDOR_NETERION, PCI_PRODUCT_NETERION_XFRAME_2 } 325 }; 326 327 int 328 xge_match(struct device *parent, void *match, void *aux) 329 { 330 return (pci_matchbyid((struct pci_attach_args *)aux, xge_devices, 331 nitems(xge_devices))); 332 } 333 334 void 335 xge_attach(struct device *parent, struct device *self, void *aux) 336 { 337 struct pci_attach_args *pa = aux; 338 struct xge_softc *sc; 339 struct ifnet *ifp; 340 pcireg_t memtype; 341 pci_intr_handle_t ih; 342 const char *intrstr = NULL; 343 pci_chipset_tag_t pc = pa->pa_pc; 344 uint8_t enaddr[ETHER_ADDR_LEN]; 345 uint64_t val; 346 int i; 347 348 sc = (struct xge_softc *)self; 349 350 sc->sc_dmat = pa->pa_dmat; 351 352 if (PCI_PRODUCT(pa->pa_id) == PCI_PRODUCT_NETERION_XFRAME) 353 sc->xge_type = XGE_TYPE_XENA; 354 else 355 sc->xge_type = XGE_TYPE_HERC; 356 357 /* Get BAR0 address */ 358 memtype = pci_mapreg_type(pa->pa_pc, pa->pa_tag, XGE_PIF_BAR); 359 if (pci_mapreg_map(pa, XGE_PIF_BAR, memtype, 0, 360 &sc->sc_st, &sc->sc_sh, 0, 0, 0)) { 361 printf(": unable to map PIF BAR registers\n"); 362 return; 363 } 364 365 memtype = pci_mapreg_type(pa->pa_pc, pa->pa_tag, XGE_TXP_BAR); 366 if (pci_mapreg_map(pa, XGE_TXP_BAR, memtype, 0, 367 &sc->sc_txt, &sc->sc_txh, 0, 0, 0)) { 368 printf(": unable to map TXP BAR registers\n"); 369 return; 370 } 371 372 if (sc->xge_type == XGE_TYPE_XENA) { 373 /* Save PCI config space */ 374 for (i = 0; i < XGE_PCISIZE_XENA; i += 4) 375 sc->sc_pciregs[i/4] = pci_conf_read(pa->pa_pc, pa->pa_tag, i); 376 } 377 378 #if BYTE_ORDER == LITTLE_ENDIAN 379 val = (uint64_t)0xFFFFFFFFFFFFFFFFULL; 380 val &= ~(TxF_R_SE|RxF_W_SE); 381 PIF_WCSR(SWAPPER_CTRL, val); 382 PIF_WCSR(SWAPPER_CTRL, val); 383 #endif 384 385 if ((val = PIF_RCSR(PIF_RD_SWAPPER_Fb)) != SWAPPER_MAGIC) { 386 printf(": failed configuring endian, %llx != %llx!\n", 387 (unsigned long long)val, SWAPPER_MAGIC); 388 return; 389 } 390 391 /* 392 * Fix for all "FFs" MAC address problems observed on 393 * Alpha platforms. Not needed for Herc. 394 */ 395 if (sc->xge_type == XGE_TYPE_XENA) { 396 /* 397 * The MAC addr may be all FF's, which is not good. 398 * Resolve it by writing some magics to GPIO_CONTROL and 399 * force a chip reset to read in the serial eeprom again. 400 */ 401 for (i = 0; i < nitems(fix_mac); i++) { 402 PIF_WCSR(GPIO_CONTROL, fix_mac[i]); 403 PIF_RCSR(GPIO_CONTROL); 404 } 405 406 /* 407 * Reset the chip and restore the PCI registers. 408 */ 409 PIF_WCSR(SW_RESET, 0xa5a5a50000000000ULL); 410 DELAY(500000); 411 for (i = 0; i < XGE_PCISIZE_XENA; i += 4) 412 pci_conf_write(pa->pa_pc, pa->pa_tag, i, sc->sc_pciregs[i/4]); 413 414 /* 415 * Restore the byte order registers. 416 */ 417 #if BYTE_ORDER == LITTLE_ENDIAN 418 val = (uint64_t)0xFFFFFFFFFFFFFFFFULL; 419 val &= ~(TxF_R_SE|RxF_W_SE); 420 PIF_WCSR(SWAPPER_CTRL, val); 421 PIF_WCSR(SWAPPER_CTRL, val); 422 #endif 423 424 if ((val = PIF_RCSR(PIF_RD_SWAPPER_Fb)) != SWAPPER_MAGIC) { 425 printf(": failed configuring endian2, %llx != %llx!\n", 426 (unsigned long long)val, SWAPPER_MAGIC); 427 return; 428 } 429 } 430 431 /* 432 * XGXS initialization. 433 */ 434 435 /* 436 * For Herc, bring EOI out of reset before XGXS. 437 */ 438 if (sc->xge_type == XGE_TYPE_HERC) { 439 val = PIF_RCSR(SW_RESET); 440 val &= 0xffff00ffffffffffULL; 441 PIF_WCSR(SW_RESET,val); 442 delay(1000*1000); /* wait for 1 sec */ 443 } 444 445 /* 29, Bring adapter out of reset */ 446 val = PIF_RCSR(SW_RESET); 447 val &= 0xffffff00ffffffffULL; 448 PIF_WCSR(SW_RESET, val); 449 DELAY(500000); 450 451 /* Ensure that it's safe to access registers by checking 452 * RIC_RUNNING bit is reset. Check is valid only for XframeII. 453 */ 454 if (sc->xge_type == XGE_TYPE_HERC){ 455 for (i = 0; i < 50; i++) { 456 val = PIF_RCSR(ADAPTER_STATUS); 457 if (!(val & RIC_RUNNING)) 458 break; 459 delay(20*1000); 460 } 461 462 if (i == 50) { 463 printf(": not safe to access registers\n"); 464 return; 465 } 466 } 467 468 /* 30, configure XGXS transceiver */ 469 if (sc->xge_type == XGE_TYPE_XENA) 470 xge_setup_xgxs_xena(sc); 471 else if(sc->xge_type == XGE_TYPE_HERC) 472 xge_setup_xgxs_herc(sc); 473 474 /* 33, program MAC address (not needed here) */ 475 /* Get ethernet address */ 476 PIF_WCSR(RMAC_ADDR_CMD_MEM, 477 RMAC_ADDR_CMD_MEM_STR|RMAC_ADDR_CMD_MEM_OFF(0)); 478 while (PIF_RCSR(RMAC_ADDR_CMD_MEM) & RMAC_ADDR_CMD_MEM_STR) 479 ; 480 val = PIF_RCSR(RMAC_ADDR_DATA0_MEM); 481 for (i = 0; i < ETHER_ADDR_LEN; i++) 482 enaddr[i] = (uint8_t)(val >> (56 - (8*i))); 483 484 /* 485 * Get memory for transmit descriptor lists. 486 */ 487 if (xge_alloc_txmem(sc)) { 488 printf(": failed allocating txmem.\n"); 489 return; 490 } 491 492 /* 9 and 10 - set FIFO number/prio */ 493 PIF_WCSR(TX_FIFO_P0, TX_FIFO_LEN0(NTXDESCS)); 494 PIF_WCSR(TX_FIFO_P1, 0ULL); 495 PIF_WCSR(TX_FIFO_P2, 0ULL); 496 PIF_WCSR(TX_FIFO_P3, 0ULL); 497 498 /* 11, XXX set round-robin prio? */ 499 500 /* 12, enable transmit FIFO */ 501 val = PIF_RCSR(TX_FIFO_P0); 502 val |= TX_FIFO_ENABLE; 503 PIF_WCSR(TX_FIFO_P0, val); 504 505 /* 13, disable some error checks */ 506 PIF_WCSR(TX_PA_CFG, 507 TX_PA_CFG_IFR|TX_PA_CFG_ISO|TX_PA_CFG_ILC|TX_PA_CFG_ILE); 508 509 /* Create transmit DMA maps */ 510 for (i = 0; i < NTXDESCS; i++) { 511 if (bus_dmamap_create(sc->sc_dmat, XGE_MAX_FRAMELEN, 512 NTXFRAGS, MCLBYTES, 0, BUS_DMA_NOWAIT, &sc->sc_txm[i])) { 513 printf(": cannot create TX DMA maps\n"); 514 return; 515 } 516 } 517 518 sc->sc_lasttx = NTXDESCS-1; 519 520 /* 521 * RxDMA initialization. 522 * Only use one out of 8 possible receive queues. 523 */ 524 /* allocate rx descriptor memory */ 525 if (xge_alloc_rxmem(sc)) { 526 printf(": failed allocating rxmem\n"); 527 return; 528 } 529 530 /* Create receive buffer DMA maps */ 531 for (i = 0; i < NRXREAL; i++) { 532 if (bus_dmamap_create(sc->sc_dmat, XGE_MAX_FRAMELEN, 533 NRXFRAGS, MCLBYTES, 0, BUS_DMA_NOWAIT, &sc->sc_rxm[i])) { 534 printf(": cannot create RX DMA maps\n"); 535 return; 536 } 537 } 538 539 /* allocate mbufs to receive descriptors */ 540 for (i = 0; i < NRXREAL; i++) 541 if (xge_add_rxbuf(sc, i)) 542 panic("out of mbufs too early"); 543 544 /* 14, setup receive ring priority */ 545 PIF_WCSR(RX_QUEUE_PRIORITY, 0ULL); /* only use one ring */ 546 547 /* 15, setup receive ring round-robin calendar */ 548 PIF_WCSR(RX_W_ROUND_ROBIN_0, 0ULL); /* only use one ring */ 549 PIF_WCSR(RX_W_ROUND_ROBIN_1, 0ULL); 550 PIF_WCSR(RX_W_ROUND_ROBIN_2, 0ULL); 551 PIF_WCSR(RX_W_ROUND_ROBIN_3, 0ULL); 552 PIF_WCSR(RX_W_ROUND_ROBIN_4, 0ULL); 553 554 /* 16, write receive ring start address */ 555 PIF_WCSR(PRC_RXD0_0, (uint64_t)sc->sc_rxmap->dm_segs[0].ds_addr); 556 /* PRC_RXD0_[1-7] are not used */ 557 558 /* 17, Setup alarm registers */ 559 PIF_WCSR(PRC_ALARM_ACTION, 0ULL); /* Default everything to retry */ 560 561 /* 18, init receive ring controller */ 562 #if RX_MODE == RX_MODE_1 563 val = RING_MODE_1; 564 #elif RX_MODE == RX_MODE_3 565 val = RING_MODE_3; 566 #else /* RX_MODE == RX_MODE_5 */ 567 val = RING_MODE_5; 568 #endif 569 PIF_WCSR(PRC_CTRL_0, RC_IN_SVC|val); 570 /* leave 1-7 disabled */ 571 /* XXXX snoop configuration? */ 572 573 /* 19, set chip memory assigned to the queue */ 574 if (sc->xge_type == XGE_TYPE_XENA) { 575 /* all 64M to queue 0 */ 576 PIF_WCSR(RX_QUEUE_CFG, MC_QUEUE(0, 64)); 577 } else { 578 /* all 32M to queue 0 */ 579 PIF_WCSR(RX_QUEUE_CFG, MC_QUEUE(0, 32)); 580 } 581 582 /* 20, setup RLDRAM parameters */ 583 /* do not touch it for now */ 584 585 /* 21, setup pause frame thresholds */ 586 /* so not touch the defaults */ 587 /* XXX - must 0xff be written as stated in the manual? */ 588 589 /* 22, configure RED */ 590 /* we do not want to drop packets, so ignore */ 591 592 /* 23, initiate RLDRAM */ 593 val = PIF_RCSR(MC_RLDRAM_MRS); 594 val |= MC_QUEUE_SIZE_ENABLE|MC_RLDRAM_MRS_ENABLE; 595 PIF_WCSR(MC_RLDRAM_MRS, val); 596 DELAY(1000); 597 598 /* 599 * Setup interrupt policies. 600 */ 601 /* 40, Transmit interrupts */ 602 PIF_WCSR(TTI_DATA1_MEM, TX_TIMER_VAL(0x1ff) | TX_TIMER_AC | 603 TX_URNG_A(5) | TX_URNG_B(20) | TX_URNG_C(48)); 604 PIF_WCSR(TTI_DATA2_MEM, 605 TX_UFC_A(25) | TX_UFC_B(64) | TX_UFC_C(128) | TX_UFC_D(512)); 606 PIF_WCSR(TTI_COMMAND_MEM, TTI_CMD_MEM_WE | TTI_CMD_MEM_STROBE); 607 while (PIF_RCSR(TTI_COMMAND_MEM) & TTI_CMD_MEM_STROBE) 608 ; 609 610 /* 41, Receive interrupts */ 611 PIF_WCSR(RTI_DATA1_MEM, RX_TIMER_VAL(0x800) | RX_TIMER_AC | 612 RX_URNG_A(5) | RX_URNG_B(20) | RX_URNG_C(50)); 613 PIF_WCSR(RTI_DATA2_MEM, 614 RX_UFC_A(64) | RX_UFC_B(128) | RX_UFC_C(256) | RX_UFC_D(512)); 615 PIF_WCSR(RTI_COMMAND_MEM, RTI_CMD_MEM_WE | RTI_CMD_MEM_STROBE); 616 while (PIF_RCSR(RTI_COMMAND_MEM) & RTI_CMD_MEM_STROBE) 617 ; 618 619 /* 620 * Setup media stuff. 621 */ 622 ifmedia_init(&sc->xena_media, IFM_IMASK, xge_xgmii_mediachange, 623 xge_ifmedia_status); 624 ifmedia_add(&sc->xena_media, IFM_ETHER|IFM_10G_SR, 0, NULL); 625 ifmedia_set(&sc->xena_media, IFM_ETHER|IFM_10G_SR); 626 627 ifp = &sc->sc_arpcom.ac_if; 628 strlcpy(ifp->if_xname, XNAME, IFNAMSIZ); 629 memcpy(sc->sc_arpcom.ac_enaddr, enaddr, ETHER_ADDR_LEN); 630 ifp->if_baudrate = IF_Gbps(10); 631 ifp->if_softc = sc; 632 ifp->if_flags = IFF_BROADCAST | IFF_SIMPLEX | IFF_MULTICAST; 633 ifp->if_ioctl = xge_ioctl; 634 ifp->if_start = xge_start; 635 #ifdef XGE_JUMBO 636 ifp->if_hardmtu = XGE_MAX_MTU; 637 #endif 638 IFQ_SET_MAXLEN(&ifp->if_snd, NTXDESCS - 1); 639 IFQ_SET_READY(&ifp->if_snd); 640 641 ifp->if_capabilities = IFCAP_VLAN_MTU | IFCAP_CSUM_IPv4 | 642 IFCAP_CSUM_TCPv4 | IFCAP_CSUM_UDPv4; 643 644 #if NVLAN > 0 645 ifp->if_capabilities |= IFCAP_VLAN_HWTAGGING; 646 #endif 647 648 /* 649 * Attach the interface. 650 */ 651 if_attach(ifp); 652 ether_ifattach(ifp); 653 654 /* 655 * Setup interrupt vector before initializing. 656 */ 657 if (pci_intr_map(pa, &ih)) { 658 printf(": unable to map interrupt\n"); 659 return; 660 } 661 intrstr = pci_intr_string(pc, ih); 662 if ((sc->sc_ih = 663 pci_intr_establish(pc, ih, IPL_NET, xge_intr, sc, XNAME)) == NULL) { 664 printf(": unable to establish interrupt at %s\n", 665 intrstr ? intrstr : "<unknown>"); 666 return; 667 } 668 printf(": %s, address %s\n", intrstr, ether_sprintf(enaddr)); 669 } 670 671 void 672 xge_ifmedia_status(struct ifnet *ifp, struct ifmediareq *ifmr) 673 { 674 struct xge_softc *sc = ifp->if_softc; 675 uint64_t reg; 676 677 ifmr->ifm_status = IFM_AVALID; 678 ifmr->ifm_active = IFM_ETHER|IFM_10G_SR; 679 680 reg = PIF_RCSR(ADAPTER_STATUS); 681 if ((reg & (RMAC_REMOTE_FAULT|RMAC_LOCAL_FAULT)) == 0) 682 ifmr->ifm_status |= IFM_ACTIVE; 683 } 684 685 int 686 xge_xgmii_mediachange(struct ifnet *ifp) 687 { 688 return (0); 689 } 690 691 void 692 xge_enable(struct xge_softc *sc) 693 { 694 uint64_t val; 695 696 /* 2, enable adapter */ 697 val = PIF_RCSR(ADAPTER_CONTROL); 698 val |= ADAPTER_EN; 699 PIF_WCSR(ADAPTER_CONTROL, val); 700 701 /* 3, light the card enable led */ 702 val = PIF_RCSR(ADAPTER_CONTROL); 703 val |= LED_ON; 704 PIF_WCSR(ADAPTER_CONTROL, val); 705 #ifdef XGE_DEBUG 706 printf("%s: link up\n", XNAME); 707 #endif 708 } 709 710 int 711 xge_init(struct ifnet *ifp) 712 { 713 struct xge_softc *sc = ifp->if_softc; 714 uint64_t val; 715 int s; 716 717 s = splnet(); 718 719 /* 720 * Cancel any pending I/O 721 */ 722 xge_stop(ifp, 0); 723 724 /* 31+32, setup MAC config */ 725 PIF_WKEY(MAC_CFG, TMAC_EN|RMAC_EN|TMAC_APPEND_PAD|RMAC_STRIP_FCS| 726 RMAC_BCAST_EN|RMAC_DISCARD_PFRM); 727 728 DELAY(1000); 729 730 /* 54, ensure that the adapter is 'quiescent' */ 731 val = PIF_RCSR(ADAPTER_STATUS); 732 if ((val & QUIESCENT) != QUIESCENT) { 733 #if 0 734 char buf[200]; 735 #endif 736 printf("%s: adapter not quiescent, aborting\n", XNAME); 737 val = (val & QUIESCENT) ^ QUIESCENT; 738 #if 0 739 bitmask_snprintf(val, QUIESCENT_BMSK, buf, sizeof buf); 740 printf("%s: ADAPTER_STATUS missing bits %s\n", XNAME, buf); 741 #endif 742 splx(s); 743 return (1); 744 } 745 746 if (!(ifp->if_capabilities & IFCAP_VLAN_HWTAGGING)) { 747 /* disable VLAN tag stripping */ 748 val = PIF_RCSR(RX_PA_CFG); 749 val &= ~STRIP_VLAN_TAG; 750 PIF_WCSR(RX_PA_CFG, val); 751 } 752 753 /* set MRU */ 754 #ifdef XGE_JUMBO 755 PIF_WCSR(RMAC_MAX_PYLD_LEN, RMAC_PYLD_LEN(XGE_MAX_FRAMELEN)); 756 #else 757 PIF_WCSR(RMAC_MAX_PYLD_LEN, RMAC_PYLD_LEN(ETHER_MAX_LEN + ETHER_VLAN_ENCAP_LEN)); 758 #endif 759 760 /* 56, enable the transmit laser */ 761 val = PIF_RCSR(ADAPTER_CONTROL); 762 val |= EOI_TX_ON; 763 PIF_WCSR(ADAPTER_CONTROL, val); 764 765 xge_enable(sc); 766 767 /* 768 * Enable all interrupts 769 */ 770 PIF_WCSR(TX_TRAFFIC_MASK, 0); 771 PIF_WCSR(RX_TRAFFIC_MASK, 0); 772 PIF_WCSR(GENERAL_INT_MASK, 0); 773 PIF_WCSR(TXPIC_INT_MASK, 0); 774 PIF_WCSR(RXPIC_INT_MASK, 0); 775 776 PIF_WCSR(MAC_INT_MASK, MAC_TMAC_INT); /* only from RMAC */ 777 PIF_WCSR(MAC_RMAC_ERR_MASK, ~RMAC_LINK_STATE_CHANGE_INT); 778 779 xge_setpromisc(sc); 780 781 xge_setmulti(sc); 782 783 /* Done... */ 784 ifp->if_flags |= IFF_RUNNING; 785 ifp->if_flags &= ~IFF_OACTIVE; 786 787 splx(s); 788 789 return (0); 790 } 791 792 void 793 xge_stop(struct ifnet *ifp, int disable) 794 { 795 struct xge_softc *sc = ifp->if_softc; 796 uint64_t val; 797 798 ifp->if_flags &= ~(IFF_RUNNING | IFF_OACTIVE); 799 800 val = PIF_RCSR(ADAPTER_CONTROL); 801 val &= ~ADAPTER_EN; 802 PIF_WCSR(ADAPTER_CONTROL, val); 803 804 while ((PIF_RCSR(ADAPTER_STATUS) & QUIESCENT) != QUIESCENT) 805 ; 806 } 807 808 int 809 xge_intr(void *pv) 810 { 811 struct xge_softc *sc = pv; 812 struct txd *txd; 813 struct ifnet *ifp = &sc->sc_arpcom.ac_if; 814 bus_dmamap_t dmp; 815 uint64_t val; 816 int i, lasttx, plen; 817 818 val = PIF_RCSR(GENERAL_INT_STATUS); 819 if (val == 0) 820 return (0); /* no interrupt here */ 821 822 PIF_WCSR(GENERAL_INT_STATUS, val); 823 824 if ((val = PIF_RCSR(MAC_RMAC_ERR_REG)) & RMAC_LINK_STATE_CHANGE_INT) { 825 /* Wait for quiescence */ 826 #ifdef XGE_DEBUG 827 printf("%s: link down\n", XNAME); 828 #endif 829 while ((PIF_RCSR(ADAPTER_STATUS) & QUIESCENT) != QUIESCENT) 830 ; 831 PIF_WCSR(MAC_RMAC_ERR_REG, RMAC_LINK_STATE_CHANGE_INT); 832 833 val = PIF_RCSR(ADAPTER_STATUS); 834 if ((val & (RMAC_REMOTE_FAULT|RMAC_LOCAL_FAULT)) == 0) 835 xge_enable(sc); /* Only if link restored */ 836 } 837 838 if ((val = PIF_RCSR(TX_TRAFFIC_INT))) 839 PIF_WCSR(TX_TRAFFIC_INT, val); /* clear interrupt bits */ 840 /* 841 * Collect sent packets. 842 */ 843 lasttx = sc->sc_lasttx; 844 while ((i = NEXTTX(sc->sc_lasttx)) != sc->sc_nexttx) { 845 txd = sc->sc_txd[i]; 846 dmp = sc->sc_txm[i]; 847 848 bus_dmamap_sync(sc->sc_dmat, dmp, 0, 849 dmp->dm_mapsize, 850 BUS_DMASYNC_POSTREAD|BUS_DMASYNC_POSTWRITE); 851 852 if (txd->txd_control1 & TXD_CTL1_OWN) { 853 bus_dmamap_sync(sc->sc_dmat, dmp, 0, 854 dmp->dm_mapsize, BUS_DMASYNC_PREREAD); 855 break; 856 } 857 bus_dmamap_unload(sc->sc_dmat, dmp); 858 m_freem(sc->sc_txb[i]); 859 ifp->if_opackets++; 860 sc->sc_lasttx = i; 861 } 862 863 if (sc->sc_lasttx != lasttx) 864 ifp->if_flags &= ~IFF_OACTIVE; 865 866 /* Try to get more packets on the wire */ 867 xge_start(ifp); 868 869 /* clear interrupt bits */ 870 if ((val = PIF_RCSR(RX_TRAFFIC_INT))) 871 PIF_WCSR(RX_TRAFFIC_INT, val); 872 873 for (;;) { 874 struct rxdesc *rxd; 875 struct mbuf *m; 876 877 XGE_RXSYNC(sc->sc_nextrx, 878 BUS_DMASYNC_POSTREAD|BUS_DMASYNC_POSTWRITE); 879 880 rxd = XGE_RXD(sc->sc_nextrx); 881 if (rxd->rxd_control1 & RXD_CTL1_OWN) { 882 XGE_RXSYNC(sc->sc_nextrx, BUS_DMASYNC_PREREAD); 883 break; 884 } 885 886 /* got a packet */ 887 m = sc->sc_rxb[sc->sc_nextrx]; 888 #if RX_MODE == RX_MODE_1 889 plen = m->m_len = RXD_CTL2_BUF0SIZ(rxd->rxd_control2); 890 #elif RX_MODE == RX_MODE_3 891 #error Fix rxmodes in xge_intr 892 #elif RX_MODE == RX_MODE_5 893 plen = m->m_len = RXD_CTL2_BUF0SIZ(rxd->rxd_control2); 894 plen += m->m_next->m_len = RXD_CTL2_BUF1SIZ(rxd->rxd_control2); 895 plen += m->m_next->m_next->m_len = 896 RXD_CTL2_BUF2SIZ(rxd->rxd_control2); 897 plen += m->m_next->m_next->m_next->m_len = 898 RXD_CTL3_BUF3SIZ(rxd->rxd_control3); 899 plen += m->m_next->m_next->m_next->m_next->m_len = 900 RXD_CTL3_BUF4SIZ(rxd->rxd_control3); 901 #endif 902 m->m_pkthdr.rcvif = ifp; 903 m->m_pkthdr.len = plen; 904 905 val = rxd->rxd_control1; 906 907 if (xge_add_rxbuf(sc, sc->sc_nextrx)) { 908 /* Failed, recycle this mbuf */ 909 #if RX_MODE == RX_MODE_1 910 rxd->rxd_control2 = RXD_MKCTL2(MCLBYTES, 0, 0); 911 rxd->rxd_control1 = RXD_CTL1_OWN; 912 #elif RX_MODE == RX_MODE_3 913 #elif RX_MODE == RX_MODE_5 914 #endif 915 XGE_RXSYNC(sc->sc_nextrx, 916 BUS_DMASYNC_PREREAD|BUS_DMASYNC_PREWRITE); 917 ifp->if_ierrors++; 918 break; 919 } 920 921 ifp->if_ipackets++; 922 923 if (RXD_CTL1_PROTOS(val) & RXD_CTL1_P_IPv4) 924 m->m_pkthdr.csum_flags |= M_IPV4_CSUM_IN_OK; 925 if (RXD_CTL1_PROTOS(val) & RXD_CTL1_P_TCP) 926 m->m_pkthdr.csum_flags |= M_TCP_CSUM_IN_OK; 927 if (RXD_CTL1_PROTOS(val) & RXD_CTL1_P_UDP) 928 m->m_pkthdr.csum_flags |= M_UDP_CSUM_IN_OK; 929 930 #if NVLAN > 0 931 if (RXD_CTL1_PROTOS(val) & RXD_CTL1_P_VLAN) { 932 m->m_pkthdr.ether_vtag = 933 RXD_CTL2_VLANTAG(rxd->rxd_control2); 934 m->m_flags |= M_VLANTAG; 935 } 936 #endif 937 938 #if NBPFILTER > 0 939 if (ifp->if_bpf) 940 bpf_mtap_ether(ifp->if_bpf, m, BPF_DIRECTION_IN); 941 #endif /* NBPFILTER > 0 */ 942 943 ether_input_mbuf(ifp, m); 944 945 if (++sc->sc_nextrx == NRXREAL) 946 sc->sc_nextrx = 0; 947 } 948 949 return (1); 950 } 951 952 int 953 xge_ioctl(struct ifnet *ifp, u_long cmd, caddr_t data) 954 { 955 struct xge_softc *sc = ifp->if_softc; 956 struct ifaddr *ifa = (struct ifaddr *) data; 957 struct ifreq *ifr = (struct ifreq *) data; 958 int s, error = 0; 959 960 s = splnet(); 961 962 switch (cmd) { 963 case SIOCSIFADDR: 964 ifp->if_flags |= IFF_UP; 965 if (!(ifp->if_flags & IFF_RUNNING)) 966 xge_init(ifp); 967 #ifdef INET 968 if (ifa->ifa_addr->sa_family == AF_INET) 969 arp_ifinit(&sc->sc_arpcom, ifa); 970 #endif /* INET */ 971 break; 972 973 case SIOCSIFFLAGS: 974 if (ifp->if_flags & IFF_UP) { 975 if (ifp->if_flags & IFF_RUNNING && 976 (ifp->if_flags ^ sc->xge_if_flags) & 977 IFF_PROMISC) { 978 xge_setpromisc(sc); 979 } else { 980 if (!(ifp->if_flags & IFF_RUNNING)) 981 xge_init(ifp); 982 } 983 } else { 984 if (ifp->if_flags & IFF_RUNNING) 985 xge_stop(ifp, 1); 986 } 987 sc->xge_if_flags = ifp->if_flags; 988 break; 989 990 case SIOCGIFMEDIA: 991 case SIOCSIFMEDIA: 992 error = ifmedia_ioctl(ifp, ifr, &sc->xena_media, cmd); 993 break; 994 995 default: 996 error = ether_ioctl(ifp, &sc->sc_arpcom, cmd, data); 997 } 998 999 if (error == ENETRESET) { 1000 if (ifp->if_flags & IFF_RUNNING) 1001 xge_setmulti(sc); 1002 error = 0; 1003 } 1004 1005 splx(s); 1006 return (error); 1007 } 1008 1009 void 1010 xge_setmulti(struct xge_softc *sc) 1011 { 1012 struct ifnet *ifp = &sc->sc_arpcom.ac_if; 1013 struct arpcom *ac = &sc->sc_arpcom; 1014 struct ether_multi *enm; 1015 struct ether_multistep step; 1016 int i, numaddr = 1; /* first slot used for card unicast address */ 1017 uint64_t val; 1018 1019 if (ac->ac_multirangecnt > 0) 1020 goto allmulti; 1021 1022 ETHER_FIRST_MULTI(step, ac, enm); 1023 while (enm != NULL) { 1024 if (numaddr == MAX_MCAST_ADDR) 1025 goto allmulti; 1026 for (val = 0, i = 0; i < ETHER_ADDR_LEN; i++) { 1027 val <<= 8; 1028 val |= enm->enm_addrlo[i]; 1029 } 1030 PIF_WCSR(RMAC_ADDR_DATA0_MEM, val << 16); 1031 PIF_WCSR(RMAC_ADDR_DATA1_MEM, 0xFFFFFFFFFFFFFFFFULL); 1032 PIF_WCSR(RMAC_ADDR_CMD_MEM, RMAC_ADDR_CMD_MEM_WE| 1033 RMAC_ADDR_CMD_MEM_STR|RMAC_ADDR_CMD_MEM_OFF(numaddr)); 1034 while (PIF_RCSR(RMAC_ADDR_CMD_MEM) & RMAC_ADDR_CMD_MEM_STR) 1035 ; 1036 numaddr++; 1037 ETHER_NEXT_MULTI(step, enm); 1038 } 1039 /* set the remaining entries to the broadcast address */ 1040 for (i = numaddr; i < MAX_MCAST_ADDR; i++) { 1041 PIF_WCSR(RMAC_ADDR_DATA0_MEM, 0xffffffffffff0000ULL); 1042 PIF_WCSR(RMAC_ADDR_DATA1_MEM, 0xFFFFFFFFFFFFFFFFULL); 1043 PIF_WCSR(RMAC_ADDR_CMD_MEM, RMAC_ADDR_CMD_MEM_WE| 1044 RMAC_ADDR_CMD_MEM_STR|RMAC_ADDR_CMD_MEM_OFF(i)); 1045 while (PIF_RCSR(RMAC_ADDR_CMD_MEM) & RMAC_ADDR_CMD_MEM_STR) 1046 ; 1047 } 1048 ifp->if_flags &= ~IFF_ALLMULTI; 1049 return; 1050 1051 allmulti: 1052 /* Just receive everything with the multicast bit set */ 1053 ifp->if_flags |= IFF_ALLMULTI; 1054 PIF_WCSR(RMAC_ADDR_DATA0_MEM, 0x8000000000000000ULL); 1055 PIF_WCSR(RMAC_ADDR_DATA1_MEM, 0xF000000000000000ULL); 1056 PIF_WCSR(RMAC_ADDR_CMD_MEM, RMAC_ADDR_CMD_MEM_WE| 1057 RMAC_ADDR_CMD_MEM_STR|RMAC_ADDR_CMD_MEM_OFF(1)); 1058 while (PIF_RCSR(RMAC_ADDR_CMD_MEM) & RMAC_ADDR_CMD_MEM_STR) 1059 ; 1060 } 1061 1062 void 1063 xge_setpromisc(struct xge_softc *sc) 1064 { 1065 struct ifnet *ifp = &sc->sc_arpcom.ac_if; 1066 uint64_t val; 1067 1068 val = PIF_RCSR(MAC_CFG); 1069 1070 if (ifp->if_flags & IFF_PROMISC) 1071 val |= RMAC_PROM_EN; 1072 else 1073 val &= ~RMAC_PROM_EN; 1074 1075 PIF_WCSR(MAC_CFG, val); 1076 } 1077 1078 void 1079 xge_start(struct ifnet *ifp) 1080 { 1081 struct xge_softc *sc = ifp->if_softc; 1082 struct txd *txd = NULL; /* XXX - gcc */ 1083 bus_dmamap_t dmp; 1084 struct mbuf *m; 1085 uint64_t par, lcr; 1086 int nexttx = 0, ntxd, error, i; 1087 1088 if ((ifp->if_flags & (IFF_RUNNING|IFF_OACTIVE)) != IFF_RUNNING) 1089 return; 1090 1091 par = lcr = 0; 1092 for (;;) { 1093 IFQ_POLL(&ifp->if_snd, m); 1094 if (m == NULL) 1095 break; /* out of packets */ 1096 1097 if (sc->sc_nexttx == sc->sc_lasttx) 1098 break; /* No more space */ 1099 1100 nexttx = sc->sc_nexttx; 1101 dmp = sc->sc_txm[nexttx]; 1102 1103 if ((error = bus_dmamap_load_mbuf(sc->sc_dmat, dmp, m, 1104 BUS_DMA_WRITE|BUS_DMA_NOWAIT)) != 0) { 1105 printf("%s: bus_dmamap_load_mbuf error %d\n", 1106 XNAME, error); 1107 break; 1108 } 1109 IFQ_DEQUEUE(&ifp->if_snd, m); 1110 1111 bus_dmamap_sync(sc->sc_dmat, dmp, 0, dmp->dm_mapsize, 1112 BUS_DMASYNC_PREWRITE); 1113 1114 txd = sc->sc_txd[nexttx]; 1115 sc->sc_txb[nexttx] = m; 1116 for (i = 0; i < dmp->dm_nsegs; i++) { 1117 if (dmp->dm_segs[i].ds_len == 0) 1118 continue; 1119 txd->txd_control1 = dmp->dm_segs[i].ds_len; 1120 txd->txd_control2 = 0; 1121 txd->txd_bufaddr = dmp->dm_segs[i].ds_addr; 1122 txd++; 1123 } 1124 ntxd = txd - sc->sc_txd[nexttx] - 1; 1125 txd = sc->sc_txd[nexttx]; 1126 txd->txd_control1 |= TXD_CTL1_OWN|TXD_CTL1_GCF; 1127 txd->txd_control2 = TXD_CTL2_UTIL; 1128 1129 #if NVLAN > 0 1130 if (m->m_flags & M_VLANTAG) { 1131 txd->txd_control2 |= TXD_CTL2_VLANE; 1132 txd->txd_control2 |= 1133 TXD_CTL2_VLANT(m->m_pkthdr.ether_vtag); 1134 } 1135 #endif 1136 1137 if (m->m_pkthdr.csum_flags & M_IPV4_CSUM_OUT) 1138 txd->txd_control2 |= TXD_CTL2_CIPv4; 1139 if (m->m_pkthdr.csum_flags & M_TCP_CSUM_OUT) 1140 txd->txd_control2 |= TXD_CTL2_CTCP; 1141 if (m->m_pkthdr.csum_flags & M_UDP_CSUM_OUT) 1142 txd->txd_control2 |= TXD_CTL2_CUDP; 1143 1144 txd[ntxd].txd_control1 |= TXD_CTL1_GCL; 1145 1146 bus_dmamap_sync(sc->sc_dmat, dmp, 0, dmp->dm_mapsize, 1147 BUS_DMASYNC_PREREAD|BUS_DMASYNC_PREWRITE); 1148 1149 par = sc->sc_txdp[nexttx]; 1150 lcr = TXDL_NUMTXD(ntxd) | TXDL_LGC_FIRST | TXDL_LGC_LAST; 1151 TXP_WCSR(TXDL_PAR, par); 1152 TXP_WCSR(TXDL_LCR, lcr); 1153 1154 #if NBPFILTER > 0 1155 if (ifp->if_bpf) 1156 bpf_mtap_ether(ifp->if_bpf, m, BPF_DIRECTION_OUT); 1157 #endif /* NBPFILTER > 0 */ 1158 1159 sc->sc_nexttx = NEXTTX(nexttx); 1160 } 1161 } 1162 1163 /* 1164 * Allocate DMA memory for transmit descriptor fragments. 1165 * Only one map is used for all descriptors. 1166 */ 1167 int 1168 xge_alloc_txmem(struct xge_softc *sc) 1169 { 1170 struct txd *txp; 1171 bus_dma_segment_t seg; 1172 bus_addr_t txdp; 1173 caddr_t kva; 1174 int i, rseg, state; 1175 1176 #define TXMAPSZ (NTXDESCS*NTXFRAGS*sizeof(struct txd)) 1177 state = 0; 1178 if (bus_dmamem_alloc(sc->sc_dmat, TXMAPSZ, PAGE_SIZE, 0, 1179 &seg, 1, &rseg, BUS_DMA_NOWAIT)) 1180 goto err; 1181 state++; 1182 if (bus_dmamem_map(sc->sc_dmat, &seg, rseg, TXMAPSZ, &kva, 1183 BUS_DMA_NOWAIT)) 1184 goto err; 1185 1186 state++; 1187 if (bus_dmamap_create(sc->sc_dmat, TXMAPSZ, 1, TXMAPSZ, 0, 1188 BUS_DMA_NOWAIT, &sc->sc_txmap)) 1189 goto err; 1190 state++; 1191 if (bus_dmamap_load(sc->sc_dmat, sc->sc_txmap, 1192 kva, TXMAPSZ, NULL, BUS_DMA_NOWAIT)) 1193 goto err; 1194 1195 /* setup transmit array pointers */ 1196 txp = (struct txd *)kva; 1197 txdp = seg.ds_addr; 1198 for (i = 0; i < NTXDESCS; i++) { 1199 sc->sc_txd[i] = txp; 1200 sc->sc_txdp[i] = txdp; 1201 txp += NTXFRAGS; 1202 txdp += (NTXFRAGS * sizeof(struct txd)); 1203 } 1204 1205 return (0); 1206 1207 err: 1208 if (state > 2) 1209 bus_dmamap_destroy(sc->sc_dmat, sc->sc_txmap); 1210 if (state > 1) 1211 bus_dmamem_unmap(sc->sc_dmat, kva, TXMAPSZ); 1212 if (state > 0) 1213 bus_dmamem_free(sc->sc_dmat, &seg, rseg); 1214 return (ENOBUFS); 1215 } 1216 1217 /* 1218 * Allocate DMA memory for receive descriptor, 1219 * only one map is used for all descriptors. 1220 * link receive descriptor pages together. 1221 */ 1222 int 1223 xge_alloc_rxmem(struct xge_softc *sc) 1224 { 1225 struct rxd_4k *rxpp; 1226 bus_dma_segment_t seg; 1227 caddr_t kva; 1228 int i, rseg, state; 1229 1230 /* sanity check */ 1231 if (sizeof(struct rxd_4k) != XGE_PAGE) { 1232 printf("bad compiler struct alignment, %d != %d\n", 1233 (int)sizeof(struct rxd_4k), XGE_PAGE); 1234 return (EINVAL); 1235 } 1236 1237 state = 0; 1238 if (bus_dmamem_alloc(sc->sc_dmat, RXMAPSZ, PAGE_SIZE, 0, 1239 &seg, 1, &rseg, BUS_DMA_NOWAIT)) 1240 goto err; 1241 state++; 1242 if (bus_dmamem_map(sc->sc_dmat, &seg, rseg, RXMAPSZ, &kva, 1243 BUS_DMA_NOWAIT)) 1244 goto err; 1245 1246 state++; 1247 if (bus_dmamap_create(sc->sc_dmat, RXMAPSZ, 1, RXMAPSZ, 0, 1248 BUS_DMA_NOWAIT, &sc->sc_rxmap)) 1249 goto err; 1250 state++; 1251 if (bus_dmamap_load(sc->sc_dmat, sc->sc_rxmap, 1252 kva, RXMAPSZ, NULL, BUS_DMA_NOWAIT)) 1253 goto err; 1254 1255 /* setup receive page link pointers */ 1256 for (rxpp = (struct rxd_4k *)kva, i = 0; i < NRXPAGES; i++, rxpp++) { 1257 sc->sc_rxd_4k[i] = rxpp; 1258 rxpp->r4_next = (uint64_t)sc->sc_rxmap->dm_segs[0].ds_addr + 1259 (i*sizeof(struct rxd_4k)) + sizeof(struct rxd_4k); 1260 } 1261 sc->sc_rxd_4k[NRXPAGES-1]->r4_next = 1262 (uint64_t)sc->sc_rxmap->dm_segs[0].ds_addr; 1263 1264 return (0); 1265 1266 err: 1267 if (state > 2) 1268 bus_dmamap_destroy(sc->sc_dmat, sc->sc_rxmap); 1269 if (state > 1) 1270 bus_dmamem_unmap(sc->sc_dmat, kva, RXMAPSZ); 1271 if (state > 0) 1272 bus_dmamem_free(sc->sc_dmat, &seg, rseg); 1273 return (ENOBUFS); 1274 } 1275 1276 1277 /* 1278 * Add a new mbuf chain to descriptor id. 1279 */ 1280 int 1281 xge_add_rxbuf(struct xge_softc *sc, int id) 1282 { 1283 struct rxdesc *rxd; 1284 struct mbuf *m[5]; 1285 int page, desc, error; 1286 #if RX_MODE == RX_MODE_5 1287 int i; 1288 #endif 1289 1290 page = id/NDESC_BUFMODE; 1291 desc = id%NDESC_BUFMODE; 1292 1293 rxd = &sc->sc_rxd_4k[page]->r4_rxd[desc]; 1294 1295 /* 1296 * Allocate mbufs. 1297 * Currently five mbufs and two clusters are used, 1298 * the hardware will put (ethernet, ip, tcp/udp) headers in 1299 * their own buffer and the clusters are only used for data. 1300 */ 1301 #if RX_MODE == RX_MODE_1 1302 MGETHDR(m[0], M_DONTWAIT, MT_DATA); 1303 if (m[0] == NULL) 1304 return (ENOBUFS); 1305 MCLGET(m[0], M_DONTWAIT); 1306 if ((m[0]->m_flags & M_EXT) == 0) { 1307 m_freem(m[0]); 1308 return (ENOBUFS); 1309 } 1310 m[0]->m_len = m[0]->m_pkthdr.len = m[0]->m_ext.ext_size; 1311 #elif RX_MODE == RX_MODE_3 1312 #error missing rxmode 3. 1313 #elif RX_MODE == RX_MODE_5 1314 MGETHDR(m[0], M_DONTWAIT, MT_DATA); 1315 for (i = 1; i < 5; i++) { 1316 MGET(m[i], M_DONTWAIT, MT_DATA); 1317 } 1318 if (m[3]) 1319 MCLGET(m[3], M_DONTWAIT); 1320 if (m[4]) 1321 MCLGET(m[4], M_DONTWAIT); 1322 if (!m[0] || !m[1] || !m[2] || !m[3] || !m[4] || 1323 ((m[3]->m_flags & M_EXT) == 0) || ((m[4]->m_flags & M_EXT) == 0)) { 1324 /* Out of something */ 1325 for (i = 0; i < 5; i++) 1326 if (m[i] != NULL) 1327 m_free(m[i]); 1328 return (ENOBUFS); 1329 } 1330 /* Link'em together */ 1331 m[0]->m_next = m[1]; 1332 m[1]->m_next = m[2]; 1333 m[2]->m_next = m[3]; 1334 m[3]->m_next = m[4]; 1335 #else 1336 #error bad mode RX_MODE 1337 #endif 1338 1339 if (sc->sc_rxb[id]) 1340 bus_dmamap_unload(sc->sc_dmat, sc->sc_rxm[id]); 1341 sc->sc_rxb[id] = m[0]; 1342 1343 error = bus_dmamap_load_mbuf(sc->sc_dmat, sc->sc_rxm[id], m[0], 1344 BUS_DMA_READ|BUS_DMA_NOWAIT); 1345 if (error) 1346 return (error); 1347 bus_dmamap_sync(sc->sc_dmat, sc->sc_rxm[id], 0, 1348 sc->sc_rxm[id]->dm_mapsize, BUS_DMASYNC_PREREAD); 1349 1350 #if RX_MODE == RX_MODE_1 1351 rxd->rxd_control2 = RXD_MKCTL2(m[0]->m_len, 0, 0); 1352 rxd->rxd_buf0 = (uint64_t)sc->sc_rxm[id]->dm_segs[0].ds_addr; 1353 rxd->rxd_control1 = RXD_CTL1_OWN; 1354 #elif RX_MODE == RX_MODE_3 1355 #elif RX_MODE == RX_MODE_5 1356 rxd->rxd_control3 = RXD_MKCTL3(0, m[3]->m_len, m[4]->m_len); 1357 rxd->rxd_control2 = RXD_MKCTL2(m[0]->m_len, m[1]->m_len, m[2]->m_len); 1358 rxd->rxd_buf0 = (uint64_t)sc->sc_rxm[id]->dm_segs[0].ds_addr; 1359 rxd->rxd_buf1 = (uint64_t)sc->sc_rxm[id]->dm_segs[1].ds_addr; 1360 rxd->rxd_buf2 = (uint64_t)sc->sc_rxm[id]->dm_segs[2].ds_addr; 1361 rxd->rxd_buf3 = (uint64_t)sc->sc_rxm[id]->dm_segs[3].ds_addr; 1362 rxd->rxd_buf4 = (uint64_t)sc->sc_rxm[id]->dm_segs[4].ds_addr; 1363 rxd->rxd_control1 = RXD_CTL1_OWN; 1364 #endif 1365 1366 XGE_RXSYNC(id, BUS_DMASYNC_PREREAD|BUS_DMASYNC_PREWRITE); 1367 return (0); 1368 } 1369 1370 /* 1371 * This magic comes from the FreeBSD driver. 1372 */ 1373 int 1374 xge_setup_xgxs_xena(struct xge_softc *sc) 1375 { 1376 /* The magic numbers are described in the users guide */ 1377 1378 /* Writing to MDIO 0x8000 (Global Config 0) */ 1379 PIF_WCSR(DTX_CONTROL, 0x8000051500000000ULL); DELAY(50); 1380 PIF_WCSR(DTX_CONTROL, 0x80000515000000E0ULL); DELAY(50); 1381 PIF_WCSR(DTX_CONTROL, 0x80000515D93500E4ULL); DELAY(50); 1382 1383 /* Writing to MDIO 0x8000 (Global Config 1) */ 1384 PIF_WCSR(DTX_CONTROL, 0x8001051500000000ULL); DELAY(50); 1385 PIF_WCSR(DTX_CONTROL, 0x80010515000000e0ULL); DELAY(50); 1386 PIF_WCSR(DTX_CONTROL, 0x80010515001e00e4ULL); DELAY(50); 1387 1388 /* Reset the Gigablaze */ 1389 PIF_WCSR(DTX_CONTROL, 0x8002051500000000ULL); DELAY(50); 1390 PIF_WCSR(DTX_CONTROL, 0x80020515000000E0ULL); DELAY(50); 1391 PIF_WCSR(DTX_CONTROL, 0x80020515F21000E4ULL); DELAY(50); 1392 1393 /* read the pole settings */ 1394 PIF_WCSR(DTX_CONTROL, 0x8000051500000000ULL); DELAY(50); 1395 PIF_WCSR(DTX_CONTROL, 0x80000515000000e0ULL); DELAY(50); 1396 PIF_WCSR(DTX_CONTROL, 0x80000515000000ecULL); DELAY(50); 1397 1398 PIF_WCSR(DTX_CONTROL, 0x8001051500000000ULL); DELAY(50); 1399 PIF_WCSR(DTX_CONTROL, 0x80010515000000e0ULL); DELAY(50); 1400 PIF_WCSR(DTX_CONTROL, 0x80010515000000ecULL); DELAY(50); 1401 1402 PIF_WCSR(DTX_CONTROL, 0x8002051500000000ULL); DELAY(50); 1403 PIF_WCSR(DTX_CONTROL, 0x80020515000000e0ULL); DELAY(50); 1404 PIF_WCSR(DTX_CONTROL, 0x80020515000000ecULL); DELAY(50); 1405 1406 /* Workaround for TX Lane XAUI initialization error. 1407 Read Xpak PHY register 24 for XAUI lane status */ 1408 PIF_WCSR(DTX_CONTROL, 0x0018040000000000ULL); DELAY(50); 1409 PIF_WCSR(DTX_CONTROL, 0x00180400000000e0ULL); DELAY(50); 1410 PIF_WCSR(DTX_CONTROL, 0x00180400000000ecULL); DELAY(50); 1411 1412 /* 1413 * Reading the MDIO control with value 0x1804001c0F001c 1414 * means the TxLanes were already in sync 1415 * Reading the MDIO control with value 0x1804000c0x001c 1416 * means some TxLanes are not in sync where x is a 4-bit 1417 * value representing each lanes 1418 */ 1419 #if 0 1420 val = PIF_RCSR(MDIO_CONTROL); 1421 if (val != 0x1804001c0F001cULL) { 1422 printf("%s: MDIO_CONTROL: %llx != %llx\n", 1423 XNAME, val, 0x1804001c0F001cULL); 1424 return (1); 1425 } 1426 #endif 1427 1428 /* Set and remove the DTE XS INTLoopBackN */ 1429 PIF_WCSR(DTX_CONTROL, 0x0000051500000000ULL); DELAY(50); 1430 PIF_WCSR(DTX_CONTROL, 0x00000515604000e0ULL); DELAY(50); 1431 PIF_WCSR(DTX_CONTROL, 0x00000515604000e4ULL); DELAY(50); 1432 PIF_WCSR(DTX_CONTROL, 0x00000515204000e4ULL); DELAY(50); 1433 PIF_WCSR(DTX_CONTROL, 0x00000515204000ecULL); DELAY(50); 1434 1435 #if 0 1436 /* Reading the DTX control register Should be 0x5152040001c */ 1437 val = PIF_RCSR(DTX_CONTROL); 1438 if (val != 0x5152040001cULL) { 1439 printf("%s: DTX_CONTROL: %llx != %llx\n", 1440 XNAME, val, 0x5152040001cULL); 1441 return (1); 1442 } 1443 #endif 1444 1445 PIF_WCSR(MDIO_CONTROL, 0x0018040000000000ULL); DELAY(50); 1446 PIF_WCSR(MDIO_CONTROL, 0x00180400000000e0ULL); DELAY(50); 1447 PIF_WCSR(MDIO_CONTROL, 0x00180400000000ecULL); DELAY(50); 1448 1449 #if 0 1450 /* Reading the MIOD control should be 0x1804001c0f001c */ 1451 val = PIF_RCSR(MDIO_CONTROL); 1452 if (val != 0x1804001c0f001cULL) { 1453 printf("%s: MDIO_CONTROL2: %llx != %llx\n", 1454 XNAME, val, 0x1804001c0f001cULL); 1455 return (1); 1456 } 1457 #endif 1458 return (0); 1459 } 1460 1461 int 1462 xge_setup_xgxs_herc(struct xge_softc *sc) 1463 { 1464 int dtx_cnt = 0; 1465 1466 while (herc_dtx_cfg[dtx_cnt] != END_SIGN) { 1467 PIF_WCSR(DTX_CONTROL, herc_dtx_cfg[dtx_cnt]); 1468 DELAY(100); 1469 dtx_cnt++; 1470 } 1471 1472 return (0); 1473 } 1474