1 /* $OpenBSD: if_wb.c,v 1.12 2001/08/12 20:03:49 mickey Exp $ */ 2 3 /* 4 * Copyright (c) 1997, 1998 5 * Bill Paul <wpaul@ctr.columbia.edu>. All rights reserved. 6 * 7 * Redistribution and use in source and binary forms, with or without 8 * modification, are permitted provided that the following conditions 9 * are met: 10 * 1. Redistributions of source code must retain the above copyright 11 * notice, this list of conditions and the following disclaimer. 12 * 2. Redistributions in binary form must reproduce the above copyright 13 * notice, this list of conditions and the following disclaimer in the 14 * documentation and/or other materials provided with the distribution. 15 * 3. All advertising materials mentioning features or use of this software 16 * must display the following acknowledgement: 17 * This product includes software developed by Bill Paul. 18 * 4. Neither the name of the author nor the names of any co-contributors 19 * may be used to endorse or promote products derived from this software 20 * without specific prior written permission. 21 * 22 * THIS SOFTWARE IS PROVIDED BY Bill Paul AND CONTRIBUTORS ``AS IS'' AND 23 * ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE 24 * IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE 25 * ARE DISCLAIMED. IN NO EVENT SHALL Bill Paul OR THE VOICES IN HIS HEAD 26 * BE LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR 27 * CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF 28 * SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS 29 * INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN 30 * CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) 31 * ARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF 32 * THE POSSIBILITY OF SUCH DAMAGE. 33 * 34 * $FreeBSD: src/sys/pci/if_wb.c,v 1.26 1999/09/25 17:29:02 wpaul Exp $ 35 */ 36 37 /* 38 * Winbond fast ethernet PCI NIC driver 39 * 40 * Supports various cheap network adapters based on the Winbond W89C840F 41 * fast ethernet controller chip. This includes adapters manufactured by 42 * Winbond itself and some made by Linksys. 43 * 44 * Written by Bill Paul <wpaul@ctr.columbia.edu> 45 * Electrical Engineering Department 46 * Columbia University, New York City 47 */ 48 49 /* 50 * The Winbond W89C840F chip is a bus master; in some ways it resembles 51 * a DEC 'tulip' chip, only not as complicated. Unfortunately, it has 52 * one major difference which is that while the registers do many of 53 * the same things as a tulip adapter, the offsets are different: where 54 * tulip registers are typically spaced 8 bytes apart, the Winbond 55 * registers are spaced 4 bytes apart. The receiver filter is also 56 * programmed differently. 57 * 58 * Like the tulip, the Winbond chip uses small descriptors containing 59 * a status word, a control word and 32-bit areas that can either be used 60 * to point to two external data blocks, or to point to a single block 61 * and another descriptor in a linked list. Descriptors can be grouped 62 * together in blocks to form fixed length rings or can be chained 63 * together in linked lists. A single packet may be spread out over 64 * several descriptors if necessary. 65 * 66 * For the receive ring, this driver uses a linked list of descriptors, 67 * each pointing to a single mbuf cluster buffer, which us large enough 68 * to hold an entire packet. The link list is looped back to created a 69 * closed ring. 70 * 71 * For transmission, the driver creates a linked list of 'super descriptors' 72 * which each contain several individual descriptors linked toghether. 73 * Each 'super descriptor' contains WB_MAXFRAGS descriptors, which we 74 * abuse as fragment pointers. This allows us to use a buffer managment 75 * scheme very similar to that used in the ThunderLAN and Etherlink XL 76 * drivers. 77 * 78 * Autonegotiation is performed using the external PHY via the MII bus. 79 * The sample boards I have all use a Davicom PHY. 80 * 81 * Note: the author of the Linux driver for the Winbond chip alludes 82 * to some sort of flaw in the chip's design that seems to mandate some 83 * drastic workaround which signigicantly impairs transmit performance. 84 * I have no idea what he's on about: transmit performance with all 85 * three of my test boards seems fine. 86 */ 87 88 #include "bpfilter.h" 89 90 #include <sys/param.h> 91 #include <sys/systm.h> 92 #include <sys/sockio.h> 93 #include <sys/mbuf.h> 94 #include <sys/malloc.h> 95 #include <sys/kernel.h> 96 #include <sys/socket.h> 97 #include <sys/device.h> 98 #include <sys/queue.h> 99 #include <sys/timeout.h> 100 101 #include <net/if.h> 102 #include <net/if_dl.h> 103 #include <net/if_types.h> 104 105 #ifdef INET 106 #include <netinet/in.h> 107 #include <netinet/in_systm.h> 108 #include <netinet/in_var.h> 109 #include <netinet/ip.h> 110 #include <netinet/if_ether.h> 111 #endif 112 113 #include <net/if_media.h> 114 115 #if NBPFILTER > 0 116 #include <net/bpf.h> 117 #endif 118 119 #include <vm/vm.h> /* for vtophys */ 120 #include <vm/vm_kern.h> 121 122 #include <dev/mii/mii.h> 123 #include <dev/mii/miivar.h> 124 #include <dev/pci/pcireg.h> 125 #include <dev/pci/pcivar.h> 126 #include <dev/pci/pcidevs.h> 127 128 #define WB_USEIOSPACE 129 130 /* #define WB_BACKGROUND_AUTONEG */ 131 132 #include <dev/pci/if_wbreg.h> 133 134 int wb_probe __P((struct device *, void *, void *)); 135 void wb_attach __P((struct device *, struct device *, void *)); 136 137 void wb_bfree __P((caddr_t, u_int, void *)); 138 int wb_newbuf __P((struct wb_softc *, struct wb_chain_onefrag *, 139 struct mbuf *)); 140 int wb_encap __P((struct wb_softc *, struct wb_chain *, 141 struct mbuf *)); 142 143 void wb_rxeof __P((struct wb_softc *)); 144 void wb_rxeoc __P((struct wb_softc *)); 145 void wb_txeof __P((struct wb_softc *)); 146 void wb_txeoc __P((struct wb_softc *)); 147 int wb_intr __P((void *)); 148 void wb_tick __P((void *)); 149 void wb_start __P((struct ifnet *)); 150 int wb_ioctl __P((struct ifnet *, u_long, caddr_t)); 151 void wb_init __P((void *)); 152 void wb_stop __P((struct wb_softc *)); 153 void wb_watchdog __P((struct ifnet *)); 154 void wb_shutdown __P((void *)); 155 int wb_ifmedia_upd __P((struct ifnet *)); 156 void wb_ifmedia_sts __P((struct ifnet *, struct ifmediareq *)); 157 158 void wb_eeprom_putbyte __P((struct wb_softc *, int)); 159 void wb_eeprom_getword __P((struct wb_softc *, int, u_int16_t *)); 160 void wb_read_eeprom __P((struct wb_softc *, caddr_t, int, int, int)); 161 void wb_mii_sync __P((struct wb_softc *)); 162 void wb_mii_send __P((struct wb_softc *, u_int32_t, int)); 163 int wb_mii_readreg __P((struct wb_softc *, struct wb_mii_frame *)); 164 int wb_mii_writereg __P((struct wb_softc *, struct wb_mii_frame *)); 165 166 void wb_setcfg __P((struct wb_softc *, u_int32_t)); 167 u_int8_t wb_calchash __P((caddr_t)); 168 void wb_setmulti __P((struct wb_softc *)); 169 void wb_reset __P((struct wb_softc *)); 170 void wb_fixmedia __P((struct wb_softc *)); 171 int wb_list_rx_init __P((struct wb_softc *)); 172 int wb_list_tx_init __P((struct wb_softc *)); 173 174 int wb_miibus_readreg __P((struct device *, int, int)); 175 void wb_miibus_writereg __P((struct device *, int, int, int)); 176 void wb_miibus_statchg __P((struct device *)); 177 178 #define WB_SETBIT(sc, reg, x) \ 179 CSR_WRITE_4(sc, reg, \ 180 CSR_READ_4(sc, reg) | x) 181 182 #define WB_CLRBIT(sc, reg, x) \ 183 CSR_WRITE_4(sc, reg, \ 184 CSR_READ_4(sc, reg) & ~x) 185 186 #define SIO_SET(x) \ 187 CSR_WRITE_4(sc, WB_SIO, \ 188 CSR_READ_4(sc, WB_SIO) | x) 189 190 #define SIO_CLR(x) \ 191 CSR_WRITE_4(sc, WB_SIO, \ 192 CSR_READ_4(sc, WB_SIO) & ~x) 193 194 /* 195 * Send a read command and address to the EEPROM, check for ACK. 196 */ 197 void wb_eeprom_putbyte(sc, addr) 198 struct wb_softc *sc; 199 int addr; 200 { 201 register int d, i; 202 203 d = addr | WB_EECMD_READ; 204 205 /* 206 * Feed in each bit and stobe the clock. 207 */ 208 for (i = 0x400; i; i >>= 1) { 209 if (d & i) { 210 SIO_SET(WB_SIO_EE_DATAIN); 211 } else { 212 SIO_CLR(WB_SIO_EE_DATAIN); 213 } 214 DELAY(100); 215 SIO_SET(WB_SIO_EE_CLK); 216 DELAY(150); 217 SIO_CLR(WB_SIO_EE_CLK); 218 DELAY(100); 219 } 220 221 return; 222 } 223 224 /* 225 * Read a word of data stored in the EEPROM at address 'addr.' 226 */ 227 void wb_eeprom_getword(sc, addr, dest) 228 struct wb_softc *sc; 229 int addr; 230 u_int16_t *dest; 231 { 232 register int i; 233 u_int16_t word = 0; 234 235 /* Enter EEPROM access mode. */ 236 CSR_WRITE_4(sc, WB_SIO, WB_SIO_EESEL|WB_SIO_EE_CS); 237 238 /* 239 * Send address of word we want to read. 240 */ 241 wb_eeprom_putbyte(sc, addr); 242 243 CSR_WRITE_4(sc, WB_SIO, WB_SIO_EESEL|WB_SIO_EE_CS); 244 245 /* 246 * Start reading bits from EEPROM. 247 */ 248 for (i = 0x8000; i; i >>= 1) { 249 SIO_SET(WB_SIO_EE_CLK); 250 DELAY(100); 251 if (CSR_READ_4(sc, WB_SIO) & WB_SIO_EE_DATAOUT) 252 word |= i; 253 SIO_CLR(WB_SIO_EE_CLK); 254 DELAY(100); 255 } 256 257 /* Turn off EEPROM access mode. */ 258 CSR_WRITE_4(sc, WB_SIO, 0); 259 260 *dest = word; 261 262 return; 263 } 264 265 /* 266 * Read a sequence of words from the EEPROM. 267 */ 268 void wb_read_eeprom(sc, dest, off, cnt, swap) 269 struct wb_softc *sc; 270 caddr_t dest; 271 int off; 272 int cnt; 273 int swap; 274 { 275 int i; 276 u_int16_t word = 0, *ptr; 277 278 for (i = 0; i < cnt; i++) { 279 wb_eeprom_getword(sc, off + i, &word); 280 ptr = (u_int16_t *)(dest + (i * 2)); 281 if (swap) 282 *ptr = ntohs(word); 283 else 284 *ptr = word; 285 } 286 287 return; 288 } 289 290 /* 291 * Sync the PHYs by setting data bit and strobing the clock 32 times. 292 */ 293 void wb_mii_sync(sc) 294 struct wb_softc *sc; 295 { 296 register int i; 297 298 SIO_SET(WB_SIO_MII_DIR|WB_SIO_MII_DATAIN); 299 300 for (i = 0; i < 32; i++) { 301 SIO_SET(WB_SIO_MII_CLK); 302 DELAY(1); 303 SIO_CLR(WB_SIO_MII_CLK); 304 DELAY(1); 305 } 306 307 return; 308 } 309 310 /* 311 * Clock a series of bits through the MII. 312 */ 313 void wb_mii_send(sc, bits, cnt) 314 struct wb_softc *sc; 315 u_int32_t bits; 316 int cnt; 317 { 318 int i; 319 320 SIO_CLR(WB_SIO_MII_CLK); 321 322 for (i = (0x1 << (cnt - 1)); i; i >>= 1) { 323 if (bits & i) { 324 SIO_SET(WB_SIO_MII_DATAIN); 325 } else { 326 SIO_CLR(WB_SIO_MII_DATAIN); 327 } 328 DELAY(1); 329 SIO_CLR(WB_SIO_MII_CLK); 330 DELAY(1); 331 SIO_SET(WB_SIO_MII_CLK); 332 } 333 } 334 335 /* 336 * Read an PHY register through the MII. 337 */ 338 int wb_mii_readreg(sc, frame) 339 struct wb_softc *sc; 340 struct wb_mii_frame *frame; 341 342 { 343 int i, ack, s; 344 345 s = splimp(); 346 347 /* 348 * Set up frame for RX. 349 */ 350 frame->mii_stdelim = WB_MII_STARTDELIM; 351 frame->mii_opcode = WB_MII_READOP; 352 frame->mii_turnaround = 0; 353 frame->mii_data = 0; 354 355 CSR_WRITE_4(sc, WB_SIO, 0); 356 357 /* 358 * Turn on data xmit. 359 */ 360 SIO_SET(WB_SIO_MII_DIR); 361 362 wb_mii_sync(sc); 363 364 /* 365 * Send command/address info. 366 */ 367 wb_mii_send(sc, frame->mii_stdelim, 2); 368 wb_mii_send(sc, frame->mii_opcode, 2); 369 wb_mii_send(sc, frame->mii_phyaddr, 5); 370 wb_mii_send(sc, frame->mii_regaddr, 5); 371 372 /* Idle bit */ 373 SIO_CLR((WB_SIO_MII_CLK|WB_SIO_MII_DATAIN)); 374 DELAY(1); 375 SIO_SET(WB_SIO_MII_CLK); 376 DELAY(1); 377 378 /* Turn off xmit. */ 379 SIO_CLR(WB_SIO_MII_DIR); 380 /* Check for ack */ 381 SIO_CLR(WB_SIO_MII_CLK); 382 DELAY(1); 383 SIO_SET(WB_SIO_MII_CLK); 384 DELAY(1); 385 ack = CSR_READ_4(sc, WB_SIO) & WB_SIO_MII_DATAOUT; 386 SIO_CLR(WB_SIO_MII_CLK); 387 DELAY(1); 388 SIO_SET(WB_SIO_MII_CLK); 389 DELAY(1); 390 391 /* 392 * Now try reading data bits. If the ack failed, we still 393 * need to clock through 16 cycles to keep the PHY(s) in sync. 394 */ 395 if (ack) { 396 for(i = 0; i < 16; i++) { 397 SIO_CLR(WB_SIO_MII_CLK); 398 DELAY(1); 399 SIO_SET(WB_SIO_MII_CLK); 400 DELAY(1); 401 } 402 goto fail; 403 } 404 405 for (i = 0x8000; i; i >>= 1) { 406 SIO_CLR(WB_SIO_MII_CLK); 407 DELAY(1); 408 if (!ack) { 409 if (CSR_READ_4(sc, WB_SIO) & WB_SIO_MII_DATAOUT) 410 frame->mii_data |= i; 411 DELAY(1); 412 } 413 SIO_SET(WB_SIO_MII_CLK); 414 DELAY(1); 415 } 416 417 fail: 418 419 SIO_CLR(WB_SIO_MII_CLK); 420 DELAY(1); 421 SIO_SET(WB_SIO_MII_CLK); 422 DELAY(1); 423 424 splx(s); 425 426 if (ack) 427 return(1); 428 return(0); 429 } 430 431 /* 432 * Write to a PHY register through the MII. 433 */ 434 int wb_mii_writereg(sc, frame) 435 struct wb_softc *sc; 436 struct wb_mii_frame *frame; 437 438 { 439 int s; 440 441 s = splimp(); 442 /* 443 * Set up frame for TX. 444 */ 445 446 frame->mii_stdelim = WB_MII_STARTDELIM; 447 frame->mii_opcode = WB_MII_WRITEOP; 448 frame->mii_turnaround = WB_MII_TURNAROUND; 449 450 /* 451 * Turn on data output. 452 */ 453 SIO_SET(WB_SIO_MII_DIR); 454 455 wb_mii_sync(sc); 456 457 wb_mii_send(sc, frame->mii_stdelim, 2); 458 wb_mii_send(sc, frame->mii_opcode, 2); 459 wb_mii_send(sc, frame->mii_phyaddr, 5); 460 wb_mii_send(sc, frame->mii_regaddr, 5); 461 wb_mii_send(sc, frame->mii_turnaround, 2); 462 wb_mii_send(sc, frame->mii_data, 16); 463 464 /* Idle bit. */ 465 SIO_SET(WB_SIO_MII_CLK); 466 DELAY(1); 467 SIO_CLR(WB_SIO_MII_CLK); 468 DELAY(1); 469 470 /* 471 * Turn off xmit. 472 */ 473 SIO_CLR(WB_SIO_MII_DIR); 474 475 splx(s); 476 477 return(0); 478 } 479 480 int 481 wb_miibus_readreg(dev, phy, reg) 482 struct device *dev; 483 int phy, reg; 484 { 485 struct wb_softc *sc = (struct wb_softc *)dev; 486 struct wb_mii_frame frame; 487 488 bzero((char *)&frame, sizeof(frame)); 489 490 frame.mii_phyaddr = phy; 491 frame.mii_regaddr = reg; 492 wb_mii_readreg(sc, &frame); 493 494 return(frame.mii_data); 495 } 496 497 void 498 wb_miibus_writereg(dev, phy, reg, data) 499 struct device *dev; 500 int phy, reg, data; 501 { 502 struct wb_softc *sc = (struct wb_softc *)dev; 503 struct wb_mii_frame frame; 504 505 bzero((char *)&frame, sizeof(frame)); 506 507 frame.mii_phyaddr = phy; 508 frame.mii_regaddr = reg; 509 frame.mii_data = data; 510 511 wb_mii_writereg(sc, &frame); 512 513 return; 514 } 515 516 void 517 wb_miibus_statchg(dev) 518 struct device *dev; 519 { 520 struct wb_softc *sc = (struct wb_softc *)dev; 521 522 wb_setcfg(sc, sc->sc_mii.mii_media_active); 523 } 524 525 u_int8_t wb_calchash(addr) 526 caddr_t addr; 527 { 528 u_int32_t crc, carry; 529 int i, j; 530 u_int8_t c; 531 532 /* Compute CRC for the address value. */ 533 crc = 0xFFFFFFFF; /* initial value */ 534 535 for (i = 0; i < 6; i++) { 536 c = *(addr + i); 537 for (j = 0; j < 8; j++) { 538 carry = ((crc & 0x80000000) ? 1 : 0) ^ (c & 0x01); 539 crc <<= 1; 540 c >>= 1; 541 if (carry) 542 crc = (crc ^ 0x04c11db6) | carry; 543 } 544 } 545 546 /* 547 * return the filter bit position 548 * Note: I arrived at the following nonsense 549 * through experimentation. It's not the usual way to 550 * generate the bit position but it's the only thing 551 * I could come up with that works. 552 */ 553 return(~(crc >> 26) & 0x0000003F); 554 } 555 556 /* 557 * Program the 64-bit multicast hash filter. 558 */ 559 void wb_setmulti(sc) 560 struct wb_softc *sc; 561 { 562 struct ifnet *ifp; 563 int h = 0; 564 u_int32_t hashes[2] = { 0, 0 }; 565 struct arpcom *ac = &sc->arpcom; 566 struct ether_multi *enm; 567 struct ether_multistep step; 568 u_int32_t rxfilt; 569 int mcnt = 0; 570 571 ifp = &sc->arpcom.ac_if; 572 573 rxfilt = CSR_READ_4(sc, WB_NETCFG); 574 575 if (ifp->if_flags & IFF_ALLMULTI || ifp->if_flags & IFF_PROMISC) { 576 rxfilt |= WB_NETCFG_RX_MULTI; 577 CSR_WRITE_4(sc, WB_NETCFG, rxfilt); 578 CSR_WRITE_4(sc, WB_MAR0, 0xFFFFFFFF); 579 CSR_WRITE_4(sc, WB_MAR1, 0xFFFFFFFF); 580 return; 581 } 582 583 /* first, zot all the existing hash bits */ 584 CSR_WRITE_4(sc, WB_MAR0, 0); 585 CSR_WRITE_4(sc, WB_MAR1, 0); 586 587 /* now program new ones */ 588 ETHER_FIRST_MULTI(step, ac, enm); 589 while (enm != NULL) { 590 h = wb_calchash(enm->enm_addrlo); 591 if (h < 32) 592 hashes[0] |= (1 << h); 593 else 594 hashes[1] |= (1 << (h - 32)); 595 mcnt++; 596 ETHER_NEXT_MULTI(step, enm); 597 } 598 599 if (mcnt) 600 rxfilt |= WB_NETCFG_RX_MULTI; 601 else 602 rxfilt &= ~WB_NETCFG_RX_MULTI; 603 604 CSR_WRITE_4(sc, WB_MAR0, hashes[0]); 605 CSR_WRITE_4(sc, WB_MAR1, hashes[1]); 606 CSR_WRITE_4(sc, WB_NETCFG, rxfilt); 607 608 return; 609 } 610 611 /* 612 * The Winbond manual states that in order to fiddle with the 613 * 'full-duplex' and '100Mbps' bits in the netconfig register, we 614 * first have to put the transmit and/or receive logic in the idle state. 615 */ 616 void 617 wb_setcfg(sc, media) 618 struct wb_softc *sc; 619 u_int32_t media; 620 { 621 int i, restart = 0; 622 623 if (CSR_READ_4(sc, WB_NETCFG) & (WB_NETCFG_TX_ON|WB_NETCFG_RX_ON)) { 624 restart = 1; 625 WB_CLRBIT(sc, WB_NETCFG, (WB_NETCFG_TX_ON|WB_NETCFG_RX_ON)); 626 627 for (i = 0; i < WB_TIMEOUT; i++) { 628 DELAY(10); 629 if ((CSR_READ_4(sc, WB_ISR) & WB_ISR_TX_IDLE) && 630 (CSR_READ_4(sc, WB_ISR) & WB_ISR_RX_IDLE)) 631 break; 632 } 633 634 if (i == WB_TIMEOUT) 635 printf("%s: failed to force tx and " 636 "rx to idle state\n", sc->sc_dev.dv_xname); 637 } 638 639 if (IFM_SUBTYPE(media) == IFM_10_T) 640 WB_CLRBIT(sc, WB_NETCFG, WB_NETCFG_100MBPS); 641 else 642 WB_SETBIT(sc, WB_NETCFG, WB_NETCFG_100MBPS); 643 644 if ((media & IFM_GMASK) == IFM_FDX) 645 WB_SETBIT(sc, WB_NETCFG, WB_NETCFG_FULLDUPLEX); 646 else 647 WB_CLRBIT(sc, WB_NETCFG, WB_NETCFG_FULLDUPLEX); 648 649 if (restart) 650 WB_SETBIT(sc, WB_NETCFG, WB_NETCFG_TX_ON|WB_NETCFG_RX_ON); 651 652 return; 653 } 654 655 void 656 wb_reset(sc) 657 struct wb_softc *sc; 658 { 659 register int i; 660 struct mii_data *mii = &sc->sc_mii; 661 662 CSR_WRITE_4(sc, WB_NETCFG, 0); 663 CSR_WRITE_4(sc, WB_BUSCTL, 0); 664 CSR_WRITE_4(sc, WB_TXADDR, 0); 665 CSR_WRITE_4(sc, WB_RXADDR, 0); 666 667 WB_SETBIT(sc, WB_BUSCTL, WB_BUSCTL_RESET); 668 WB_SETBIT(sc, WB_BUSCTL, WB_BUSCTL_RESET); 669 670 for (i = 0; i < WB_TIMEOUT; i++) { 671 DELAY(10); 672 if (!(CSR_READ_4(sc, WB_BUSCTL) & WB_BUSCTL_RESET)) 673 break; 674 } 675 if (i == WB_TIMEOUT) 676 printf("%s: reset never completed!\n", sc->sc_dev.dv_xname); 677 678 /* Wait a little while for the chip to get its brains in order. */ 679 DELAY(1000); 680 681 if (mii->mii_instance) { 682 struct mii_softc *miisc; 683 for (miisc = LIST_FIRST(&mii->mii_phys); miisc != NULL; 684 miisc = LIST_NEXT(miisc, mii_list)) 685 mii_phy_reset(miisc); 686 } 687 } 688 689 void 690 wb_fixmedia(sc) 691 struct wb_softc *sc; 692 { 693 struct mii_data *mii = &sc->sc_mii; 694 u_int32_t media; 695 696 if (LIST_FIRST(&mii->mii_phys) == NULL) 697 return; 698 699 mii_pollstat(mii); 700 if (IFM_SUBTYPE(mii->mii_media_active) == IFM_10_T) { 701 media = mii->mii_media_active & ~IFM_10_T; 702 media |= IFM_100_TX; 703 } if (IFM_SUBTYPE(mii->mii_media_active) == IFM_100_TX) { 704 media = mii->mii_media_active & ~IFM_100_TX; 705 media |= IFM_10_T; 706 } else 707 return; 708 709 ifmedia_set(&mii->mii_media, media); 710 } 711 712 /* 713 * Probe for a Winbond chip. Check the PCI vendor and device 714 * IDs against our list and return a device name if we find a match. 715 */ 716 int 717 wb_probe(parent, match, aux) 718 struct device *parent; 719 void *match, *aux; 720 { 721 struct pci_attach_args *pa = (struct pci_attach_args *)aux; 722 723 if (PCI_VENDOR(pa->pa_id) == PCI_VENDOR_WINBOND) { 724 switch (PCI_PRODUCT(pa->pa_id)) { 725 case PCI_PRODUCT_WINBOND_W89C840F: 726 return (1); 727 } 728 } 729 730 if (PCI_VENDOR(pa->pa_id) == PCI_VENDOR_COMPEX) { 731 switch (PCI_PRODUCT(pa->pa_id)) { 732 case PCI_PRODUCT_COMPEX_RL100ATX: 733 return (1); 734 } 735 } 736 737 return (0); 738 } 739 740 /* 741 * Attach the interface. Allocate softc structures, do ifmedia 742 * setup and ethernet/BPF attach. 743 */ 744 void 745 wb_attach(parent, self, aux) 746 struct device *parent, *self; 747 void *aux; 748 { 749 struct wb_softc *sc = (struct wb_softc *)self; 750 struct pci_attach_args *pa = aux; 751 pci_chipset_tag_t pc = pa->pa_pc; 752 pci_intr_handle_t ih; 753 const char *intrstr = NULL; 754 struct ifnet *ifp = &sc->arpcom.ac_if; 755 bus_addr_t iobase; 756 bus_size_t iosize; 757 int s, rseg; 758 u_int32_t command; 759 bus_dma_segment_t seg; 760 bus_dmamap_t dmamap; 761 caddr_t kva; 762 763 s = splimp(); 764 765 /* 766 * Handle power management nonsense. 767 */ 768 769 command = pci_conf_read(pc, pa->pa_tag, WB_PCI_CAPID) & 0x000000FF; 770 if (command == 0x01) { 771 772 command = pci_conf_read(pc, pa->pa_tag, WB_PCI_PWRMGMTCTRL); 773 if (command & WB_PSTATE_MASK) { 774 u_int32_t io, mem, irq; 775 776 /* Save important PCI config data. */ 777 io = pci_conf_read(pc, pa->pa_tag, WB_PCI_LOIO); 778 mem = pci_conf_read(pc, pa->pa_tag, WB_PCI_LOMEM); 779 irq = pci_conf_read(pc, pa->pa_tag, WB_PCI_INTLINE); 780 781 /* Reset the power state. */ 782 printf("%s: chip is in D%d power mode " 783 "-- setting to D0\n", sc->sc_dev.dv_xname, 784 command & WB_PSTATE_MASK); 785 command &= 0xFFFFFFFC; 786 pci_conf_write(pc, pa->pa_tag, WB_PCI_PWRMGMTCTRL, 787 command); 788 789 /* Restore PCI config data. */ 790 pci_conf_write(pc, pa->pa_tag, WB_PCI_LOIO, io); 791 pci_conf_write(pc, pa->pa_tag, WB_PCI_LOMEM, mem); 792 pci_conf_write(pc, pa->pa_tag, WB_PCI_INTLINE, irq); 793 } 794 } 795 796 /* 797 * Map control/status registers. 798 */ 799 command = pci_conf_read(pc, pa->pa_tag, PCI_COMMAND_STATUS_REG); 800 command |= PCI_COMMAND_IO_ENABLE | PCI_COMMAND_MEM_ENABLE | 801 PCI_COMMAND_MASTER_ENABLE; 802 pci_conf_write(pc, pa->pa_tag, PCI_COMMAND_STATUS_REG, command); 803 command = pci_conf_read(pc, pa->pa_tag, PCI_COMMAND_STATUS_REG); 804 805 #ifdef WB_USEIOSPACE 806 if (!(command & PCI_COMMAND_IO_ENABLE)) { 807 printf(": failed to enable I/O ports!\n"); 808 goto fail; 809 } 810 if (pci_io_find(pc, pa->pa_tag, WB_PCI_LOIO, &iobase, &iosize)) { 811 printf(": can't find i/o space\n"); 812 goto fail; 813 } 814 if (bus_space_map(pa->pa_iot, iobase, iosize, 0, &sc->wb_bhandle)) { 815 printf(": can't map i/o space\n"); 816 goto fail; 817 } 818 sc->wb_btag = pa->pa_iot; 819 #else 820 if (!(command & PCI_COMMAND_MEM_ENABLE)) { 821 printf(": failed to enable memory mapping!\n"); 822 goto fail; 823 } 824 if (pci_mem_find(pc, pa->pa_tag, WB_PCI_LOMEM, &iobase, &iosize, NULL)){ 825 printf(": can't find mem space\n"); 826 goto fail; 827 } 828 if (bus_space_map(pa->pa_memt, iobase, iosize, 0, &sc->wb_bhandle)) { 829 printf(": can't map mem space\n"); 830 goto fail; 831 } 832 sc->wb_btag = pa->pa_memt; 833 #endif 834 835 /* Allocate interrupt */ 836 if (pci_intr_map(pc, pa->pa_intrtag, pa->pa_intrpin, 837 pa->pa_intrline, &ih)) { 838 printf(": couldn't map interrupt\n"); 839 goto fail; 840 } 841 intrstr = pci_intr_string(pc, ih); 842 sc->sc_ih = pci_intr_establish(pc, ih, IPL_NET, wb_intr, sc, 843 self->dv_xname); 844 if (sc->sc_ih == NULL) { 845 printf(": couldn't establish interrupt"); 846 if (intrstr != NULL) 847 printf(" at %s", intrstr); 848 printf("\n"); 849 goto fail; 850 } 851 printf(": %s", intrstr); 852 853 sc->wb_cachesize = pci_conf_read(pc, pa->pa_tag, WB_PCI_CACHELEN)&0xff; 854 855 /* Reset the adapter. */ 856 wb_reset(sc); 857 858 /* 859 * Get station address from the EEPROM. 860 */ 861 wb_read_eeprom(sc, (caddr_t)&sc->arpcom.ac_enaddr, 0, 3, 0); 862 printf(" address %s\n", ether_sprintf(sc->arpcom.ac_enaddr)); 863 864 if (bus_dmamem_alloc(pa->pa_dmat, sizeof(struct wb_list_data), 865 PAGE_SIZE, 0, &seg, 1, &rseg, BUS_DMA_NOWAIT)) { 866 printf("%s: can't alloc list data\n", sc->sc_dev.dv_xname); 867 goto fail; 868 } 869 if (bus_dmamem_map(pa->pa_dmat, &seg, rseg, 870 sizeof(struct wb_list_data), &kva, BUS_DMA_NOWAIT)) { 871 printf("%s: can't map list data, size %d\n", 872 sc->sc_dev.dv_xname, sizeof(struct wb_list_data)); 873 bus_dmamem_free(pa->pa_dmat, &seg, rseg); 874 goto fail; 875 } 876 if (bus_dmamap_create(pa->pa_dmat, sizeof(struct wb_list_data), 1, 877 sizeof(struct wb_list_data), 0, BUS_DMA_NOWAIT, &dmamap)) { 878 printf("%s: can't create dma map\n", sc->sc_dev.dv_xname); 879 bus_dmamem_unmap(pa->pa_dmat, kva, 880 sizeof(struct wb_list_data)); 881 bus_dmamem_free(pa->pa_dmat, &seg, rseg); 882 goto fail; 883 } 884 if (bus_dmamap_load(pa->pa_dmat, dmamap, kva, 885 sizeof(struct wb_list_data), NULL, BUS_DMA_NOWAIT)) { 886 printf("%s: can't load dma map\n", sc->sc_dev.dv_xname); 887 bus_dmamap_destroy(pa->pa_dmat, dmamap); 888 bus_dmamem_unmap(pa->pa_dmat, kva, 889 sizeof(struct wb_list_data)); 890 bus_dmamem_free(pa->pa_dmat, &seg, rseg); 891 goto fail; 892 } 893 sc->wb_ldata = (struct wb_list_data *)kva; 894 bzero(sc->wb_ldata, sizeof(struct wb_list_data)); 895 896 ifp->if_softc = sc; 897 ifp->if_mtu = ETHERMTU; 898 ifp->if_flags = IFF_BROADCAST | IFF_SIMPLEX | IFF_MULTICAST; 899 ifp->if_ioctl = wb_ioctl; 900 ifp->if_output = ether_output; 901 ifp->if_start = wb_start; 902 ifp->if_watchdog = wb_watchdog; 903 ifp->if_baudrate = 10000000; 904 IFQ_SET_MAXLEN(&ifp->if_snd, WB_TX_LIST_CNT - 1); 905 IFQ_SET_READY(&ifp->if_snd); 906 907 bcopy(sc->sc_dev.dv_xname, ifp->if_xname, IFNAMSIZ); 908 909 /* 910 * Do ifmedia setup. 911 */ 912 wb_stop(sc); 913 914 ifmedia_init(&sc->sc_mii.mii_media, 0, wb_ifmedia_upd, wb_ifmedia_sts); 915 sc->sc_mii.mii_ifp = ifp; 916 sc->sc_mii.mii_readreg = wb_miibus_readreg; 917 sc->sc_mii.mii_writereg = wb_miibus_writereg; 918 sc->sc_mii.mii_statchg = wb_miibus_statchg; 919 mii_attach(self, &sc->sc_mii, 0xffffffff, MII_PHY_ANY, MII_OFFSET_ANY, 920 0); 921 if (LIST_FIRST(&sc->sc_mii.mii_phys) == NULL) { 922 ifmedia_add(&sc->sc_mii.mii_media, IFM_ETHER|IFM_NONE,0,NULL); 923 ifmedia_set(&sc->sc_mii.mii_media, IFM_ETHER|IFM_NONE); 924 } else 925 ifmedia_set(&sc->sc_mii.mii_media, IFM_ETHER|IFM_AUTO); 926 927 /* 928 * Call MI attach routines. 929 */ 930 if_attach(ifp); 931 ether_ifattach(ifp); 932 933 shutdownhook_establish(wb_shutdown, sc); 934 935 fail: 936 splx(s); 937 return; 938 } 939 940 /* 941 * Initialize the transmit descriptors. 942 */ 943 int wb_list_tx_init(sc) 944 struct wb_softc *sc; 945 { 946 struct wb_chain_data *cd; 947 struct wb_list_data *ld; 948 int i; 949 950 cd = &sc->wb_cdata; 951 ld = sc->wb_ldata; 952 953 for (i = 0; i < WB_TX_LIST_CNT; i++) { 954 cd->wb_tx_chain[i].wb_ptr = &ld->wb_tx_list[i]; 955 if (i == (WB_TX_LIST_CNT - 1)) { 956 cd->wb_tx_chain[i].wb_nextdesc = 957 &cd->wb_tx_chain[0]; 958 } else { 959 cd->wb_tx_chain[i].wb_nextdesc = 960 &cd->wb_tx_chain[i + 1]; 961 } 962 } 963 964 cd->wb_tx_free = &cd->wb_tx_chain[0]; 965 cd->wb_tx_tail = cd->wb_tx_head = NULL; 966 967 return(0); 968 } 969 970 971 /* 972 * Initialize the RX descriptors and allocate mbufs for them. Note that 973 * we arrange the descriptors in a closed ring, so that the last descriptor 974 * points back to the first. 975 */ 976 int wb_list_rx_init(sc) 977 struct wb_softc *sc; 978 { 979 struct wb_chain_data *cd; 980 struct wb_list_data *ld; 981 int i; 982 983 cd = &sc->wb_cdata; 984 ld = sc->wb_ldata; 985 986 for (i = 0; i < WB_RX_LIST_CNT; i++) { 987 cd->wb_rx_chain[i].wb_ptr = 988 (struct wb_desc *)&ld->wb_rx_list[i]; 989 cd->wb_rx_chain[i].wb_buf = (void *)&ld->wb_rxbufs[i]; 990 if (wb_newbuf(sc, &cd->wb_rx_chain[i], NULL) == ENOBUFS) 991 return(ENOBUFS); 992 if (i == (WB_RX_LIST_CNT - 1)) { 993 cd->wb_rx_chain[i].wb_nextdesc = &cd->wb_rx_chain[0]; 994 ld->wb_rx_list[i].wb_next = 995 vtophys(&ld->wb_rx_list[0]); 996 } else { 997 cd->wb_rx_chain[i].wb_nextdesc = 998 &cd->wb_rx_chain[i + 1]; 999 ld->wb_rx_list[i].wb_next = 1000 vtophys(&ld->wb_rx_list[i + 1]); 1001 } 1002 } 1003 1004 cd->wb_rx_head = &cd->wb_rx_chain[0]; 1005 1006 return(0); 1007 } 1008 1009 void 1010 wb_bfree(buf, size, arg) 1011 caddr_t buf; 1012 u_int size; 1013 void *arg; 1014 { 1015 } 1016 1017 /* 1018 * Initialize an RX descriptor and attach an MBUF cluster. 1019 */ 1020 int 1021 wb_newbuf(sc, c, m) 1022 struct wb_softc *sc; 1023 struct wb_chain_onefrag *c; 1024 struct mbuf *m; 1025 { 1026 struct mbuf *m_new = NULL; 1027 1028 if (m == NULL) { 1029 MGETHDR(m_new, M_DONTWAIT, MT_DATA); 1030 if (m_new == NULL) 1031 return(ENOBUFS); 1032 m_new->m_data = m_new->m_ext.ext_buf = c->wb_buf; 1033 m_new->m_flags |= M_EXT; 1034 m_new->m_ext.ext_size = m_new->m_pkthdr.len = 1035 m_new->m_len = WB_BUFBYTES; 1036 m_new->m_ext.ext_free = wb_bfree; 1037 m_new->m_ext.ext_arg = NULL; 1038 MCLINITREFERENCE(m_new); 1039 } else { 1040 m_new = m; 1041 m_new->m_len = m_new->m_pkthdr.len = WB_BUFBYTES; 1042 m_new->m_data = m_new->m_ext.ext_buf; 1043 } 1044 1045 m_adj(m_new, sizeof(u_int64_t)); 1046 1047 c->wb_mbuf = m_new; 1048 c->wb_ptr->wb_data = vtophys(mtod(m_new, caddr_t)); 1049 c->wb_ptr->wb_ctl = WB_RXCTL_RLINK | 1536; 1050 c->wb_ptr->wb_status = WB_RXSTAT; 1051 1052 return(0); 1053 } 1054 1055 /* 1056 * A frame has been uploaded: pass the resulting mbuf chain up to 1057 * the higher level protocols. 1058 */ 1059 void wb_rxeof(sc) 1060 struct wb_softc *sc; 1061 { 1062 struct mbuf *m = NULL; 1063 struct ifnet *ifp; 1064 struct wb_chain_onefrag *cur_rx; 1065 int total_len = 0; 1066 u_int32_t rxstat; 1067 1068 ifp = &sc->arpcom.ac_if; 1069 1070 while(!((rxstat = sc->wb_cdata.wb_rx_head->wb_ptr->wb_status) & 1071 WB_RXSTAT_OWN)) { 1072 struct mbuf *m0 = NULL; 1073 1074 cur_rx = sc->wb_cdata.wb_rx_head; 1075 sc->wb_cdata.wb_rx_head = cur_rx->wb_nextdesc; 1076 1077 m = cur_rx->wb_mbuf; 1078 1079 if ((rxstat & WB_RXSTAT_MIIERR) || 1080 (WB_RXBYTES(cur_rx->wb_ptr->wb_status) < WB_MIN_FRAMELEN) || 1081 (WB_RXBYTES(cur_rx->wb_ptr->wb_status) > 1536) || 1082 !(rxstat & WB_RXSTAT_LASTFRAG) || 1083 !(rxstat & WB_RXSTAT_RXCMP)) { 1084 ifp->if_ierrors++; 1085 wb_newbuf(sc, cur_rx, m); 1086 printf("%s: receiver babbling: possible chip " 1087 "bug, forcing reset\n", sc->sc_dev.dv_xname); 1088 wb_fixmedia(sc); 1089 wb_reset(sc); 1090 wb_init(sc); 1091 return; 1092 } 1093 1094 if (rxstat & WB_RXSTAT_RXERR) { 1095 ifp->if_ierrors++; 1096 wb_newbuf(sc, cur_rx, m); 1097 break; 1098 } 1099 1100 /* No errors; receive the packet. */ 1101 total_len = WB_RXBYTES(cur_rx->wb_ptr->wb_status); 1102 1103 /* 1104 * XXX The Winbond chip includes the CRC with every 1105 * received frame, and there's no way to turn this 1106 * behavior off (at least, I can't find anything in 1107 * the manual that explains how to do it) so we have 1108 * to trim off the CRC manually. 1109 */ 1110 total_len -= ETHER_CRC_LEN; 1111 1112 m0 = m_devget(mtod(m, char *) - ETHER_ALIGN, 1113 total_len + ETHER_ALIGN, 0, ifp, NULL); 1114 wb_newbuf(sc, cur_rx, m); 1115 if (m0 == NULL) { 1116 ifp->if_ierrors++; 1117 break; 1118 } 1119 m_adj(m0, ETHER_ALIGN); 1120 m = m0; 1121 1122 ifp->if_ipackets++; 1123 1124 #if NBPFILTER > 0 1125 /* 1126 * Handle BPF listeners. Let the BPF user see the packet. 1127 */ 1128 if (ifp->if_bpf) 1129 bpf_mtap(ifp->if_bpf, m); 1130 #endif 1131 /* pass it on. */ 1132 ether_input_mbuf(ifp, m); 1133 } 1134 1135 return; 1136 } 1137 1138 void wb_rxeoc(sc) 1139 struct wb_softc *sc; 1140 { 1141 wb_rxeof(sc); 1142 1143 WB_CLRBIT(sc, WB_NETCFG, WB_NETCFG_RX_ON); 1144 CSR_WRITE_4(sc, WB_RXADDR, vtophys(&sc->wb_ldata->wb_rx_list[0])); 1145 WB_SETBIT(sc, WB_NETCFG, WB_NETCFG_RX_ON); 1146 if (CSR_READ_4(sc, WB_ISR) & WB_RXSTATE_SUSPEND) 1147 CSR_WRITE_4(sc, WB_RXSTART, 0xFFFFFFFF); 1148 1149 return; 1150 } 1151 1152 /* 1153 * A frame was downloaded to the chip. It's safe for us to clean up 1154 * the list buffers. 1155 */ 1156 void wb_txeof(sc) 1157 struct wb_softc *sc; 1158 { 1159 struct wb_chain *cur_tx; 1160 struct ifnet *ifp; 1161 1162 ifp = &sc->arpcom.ac_if; 1163 1164 /* Clear the timeout timer. */ 1165 ifp->if_timer = 0; 1166 1167 if (sc->wb_cdata.wb_tx_head == NULL) 1168 return; 1169 1170 /* 1171 * Go through our tx list and free mbufs for those 1172 * frames that have been transmitted. 1173 */ 1174 while(sc->wb_cdata.wb_tx_head->wb_mbuf != NULL) { 1175 u_int32_t txstat; 1176 1177 cur_tx = sc->wb_cdata.wb_tx_head; 1178 txstat = WB_TXSTATUS(cur_tx); 1179 1180 if ((txstat & WB_TXSTAT_OWN) || txstat == WB_UNSENT) 1181 break; 1182 1183 if (txstat & WB_TXSTAT_TXERR) { 1184 ifp->if_oerrors++; 1185 if (txstat & WB_TXSTAT_ABORT) 1186 ifp->if_collisions++; 1187 if (txstat & WB_TXSTAT_LATECOLL) 1188 ifp->if_collisions++; 1189 } 1190 1191 ifp->if_collisions += (txstat & WB_TXSTAT_COLLCNT) >> 3; 1192 1193 ifp->if_opackets++; 1194 m_freem(cur_tx->wb_mbuf); 1195 cur_tx->wb_mbuf = NULL; 1196 1197 if (sc->wb_cdata.wb_tx_head == sc->wb_cdata.wb_tx_tail) { 1198 sc->wb_cdata.wb_tx_head = NULL; 1199 sc->wb_cdata.wb_tx_tail = NULL; 1200 break; 1201 } 1202 1203 sc->wb_cdata.wb_tx_head = cur_tx->wb_nextdesc; 1204 } 1205 1206 return; 1207 } 1208 1209 /* 1210 * TX 'end of channel' interrupt handler. 1211 */ 1212 void wb_txeoc(sc) 1213 struct wb_softc *sc; 1214 { 1215 struct ifnet *ifp; 1216 1217 ifp = &sc->arpcom.ac_if; 1218 1219 ifp->if_timer = 0; 1220 1221 if (sc->wb_cdata.wb_tx_head == NULL) { 1222 ifp->if_flags &= ~IFF_OACTIVE; 1223 sc->wb_cdata.wb_tx_tail = NULL; 1224 } else { 1225 if (WB_TXOWN(sc->wb_cdata.wb_tx_head) == WB_UNSENT) { 1226 WB_TXOWN(sc->wb_cdata.wb_tx_head) = WB_TXSTAT_OWN; 1227 ifp->if_timer = 5; 1228 CSR_WRITE_4(sc, WB_TXSTART, 0xFFFFFFFF); 1229 } 1230 } 1231 1232 return; 1233 } 1234 1235 int wb_intr(arg) 1236 void *arg; 1237 { 1238 struct wb_softc *sc; 1239 struct ifnet *ifp; 1240 u_int32_t status; 1241 int r = 0; 1242 1243 sc = arg; 1244 ifp = &sc->arpcom.ac_if; 1245 1246 if (!(ifp->if_flags & IFF_UP)) 1247 return (r); 1248 1249 /* Disable interrupts. */ 1250 CSR_WRITE_4(sc, WB_IMR, 0x00000000); 1251 1252 for (;;) { 1253 1254 status = CSR_READ_4(sc, WB_ISR); 1255 if (status) 1256 CSR_WRITE_4(sc, WB_ISR, status); 1257 1258 if ((status & WB_INTRS) == 0) 1259 break; 1260 1261 r = 1; 1262 1263 if ((status & WB_ISR_RX_NOBUF) || (status & WB_ISR_RX_ERR)) { 1264 ifp->if_ierrors++; 1265 wb_reset(sc); 1266 if (status & WB_ISR_RX_ERR) 1267 wb_fixmedia(sc); 1268 wb_init(sc); 1269 continue; 1270 } 1271 1272 if (status & WB_ISR_RX_OK) 1273 wb_rxeof(sc); 1274 1275 if (status & WB_ISR_RX_IDLE) 1276 wb_rxeoc(sc); 1277 1278 if (status & WB_ISR_TX_OK) 1279 wb_txeof(sc); 1280 1281 if (status & WB_ISR_TX_NOBUF) 1282 wb_txeoc(sc); 1283 1284 if (status & WB_ISR_TX_IDLE) { 1285 wb_txeof(sc); 1286 if (sc->wb_cdata.wb_tx_head != NULL) { 1287 WB_SETBIT(sc, WB_NETCFG, WB_NETCFG_TX_ON); 1288 CSR_WRITE_4(sc, WB_TXSTART, 0xFFFFFFFF); 1289 } 1290 } 1291 1292 if (status & WB_ISR_TX_UNDERRUN) { 1293 ifp->if_oerrors++; 1294 wb_txeof(sc); 1295 WB_CLRBIT(sc, WB_NETCFG, WB_NETCFG_TX_ON); 1296 /* Jack up TX threshold */ 1297 sc->wb_txthresh += WB_TXTHRESH_CHUNK; 1298 WB_CLRBIT(sc, WB_NETCFG, WB_NETCFG_TX_THRESH); 1299 WB_SETBIT(sc, WB_NETCFG, WB_TXTHRESH(sc->wb_txthresh)); 1300 WB_SETBIT(sc, WB_NETCFG, WB_NETCFG_TX_ON); 1301 } 1302 1303 if (status & WB_ISR_BUS_ERR) { 1304 wb_reset(sc); 1305 wb_init(sc); 1306 } 1307 1308 } 1309 1310 /* Re-enable interrupts. */ 1311 CSR_WRITE_4(sc, WB_IMR, WB_INTRS); 1312 1313 if (!IFQ_IS_EMPTY(&ifp->if_snd)) { 1314 wb_start(ifp); 1315 } 1316 1317 return (r); 1318 } 1319 1320 void 1321 wb_tick(xsc) 1322 void *xsc; 1323 { 1324 struct wb_softc *sc = xsc; 1325 int s; 1326 1327 s = splimp(); 1328 mii_tick(&sc->sc_mii); 1329 splx(s); 1330 timeout_add(&sc->wb_tick_tmo, hz); 1331 } 1332 1333 /* 1334 * Encapsulate an mbuf chain in a descriptor by coupling the mbuf data 1335 * pointers to the fragment pointers. 1336 */ 1337 int wb_encap(sc, c, m_head) 1338 struct wb_softc *sc; 1339 struct wb_chain *c; 1340 struct mbuf *m_head; 1341 { 1342 int frag = 0; 1343 struct wb_desc *f = NULL; 1344 int total_len; 1345 struct mbuf *m; 1346 1347 /* 1348 * Start packing the mbufs in this chain into 1349 * the fragment pointers. Stop when we run out 1350 * of fragments or hit the end of the mbuf chain. 1351 */ 1352 m = m_head; 1353 total_len = 0; 1354 1355 for (m = m_head, frag = 0; m != NULL; m = m->m_next) { 1356 if (m->m_len != 0) { 1357 if (frag == WB_MAXFRAGS) 1358 break; 1359 total_len += m->m_len; 1360 f = &c->wb_ptr->wb_frag[frag]; 1361 f->wb_ctl = WB_TXCTL_TLINK | m->m_len; 1362 if (frag == 0) { 1363 f->wb_ctl |= WB_TXCTL_FIRSTFRAG; 1364 f->wb_status = 0; 1365 } else 1366 f->wb_status = WB_TXSTAT_OWN; 1367 f->wb_next = vtophys(&c->wb_ptr->wb_frag[frag + 1]); 1368 f->wb_data = vtophys(mtod(m, vm_offset_t)); 1369 frag++; 1370 } 1371 } 1372 1373 /* 1374 * Handle special case: we used up all 16 fragments, 1375 * but we have more mbufs left in the chain. Copy the 1376 * data into an mbuf cluster. Note that we don't 1377 * bother clearing the values in the other fragment 1378 * pointers/counters; it wouldn't gain us anything, 1379 * and would waste cycles. 1380 */ 1381 if (m != NULL) { 1382 struct mbuf *m_new = NULL; 1383 1384 MGETHDR(m_new, M_DONTWAIT, MT_DATA); 1385 if (m_new == NULL) 1386 return(1); 1387 if (m_head->m_pkthdr.len > MHLEN) { 1388 MCLGET(m_new, M_DONTWAIT); 1389 if (!(m_new->m_flags & M_EXT)) { 1390 m_freem(m_new); 1391 return(1); 1392 } 1393 } 1394 m_copydata(m_head, 0, m_head->m_pkthdr.len, 1395 mtod(m_new, caddr_t)); 1396 m_new->m_pkthdr.len = m_new->m_len = m_head->m_pkthdr.len; 1397 m_freem(m_head); 1398 m_head = m_new; 1399 f = &c->wb_ptr->wb_frag[0]; 1400 f->wb_status = 0; 1401 f->wb_data = vtophys(mtod(m_new, caddr_t)); 1402 f->wb_ctl = total_len = m_new->m_len; 1403 f->wb_ctl |= WB_TXCTL_TLINK|WB_TXCTL_FIRSTFRAG; 1404 frag = 1; 1405 } 1406 1407 if (total_len < WB_MIN_FRAMELEN) { 1408 f = &c->wb_ptr->wb_frag[frag]; 1409 f->wb_ctl = WB_MIN_FRAMELEN - total_len; 1410 f->wb_data = vtophys(&sc->wb_cdata.wb_pad); 1411 f->wb_ctl |= WB_TXCTL_TLINK; 1412 f->wb_status = WB_TXSTAT_OWN; 1413 frag++; 1414 } 1415 1416 c->wb_mbuf = m_head; 1417 c->wb_lastdesc = frag - 1; 1418 WB_TXCTL(c) |= WB_TXCTL_LASTFRAG; 1419 WB_TXNEXT(c) = vtophys(&c->wb_nextdesc->wb_ptr->wb_frag[0]); 1420 1421 return(0); 1422 } 1423 1424 /* 1425 * Main transmit routine. To avoid having to do mbuf copies, we put pointers 1426 * to the mbuf data regions directly in the transmit lists. We also save a 1427 * copy of the pointers since the transmit list fragment pointers are 1428 * physical addresses. 1429 */ 1430 1431 void wb_start(ifp) 1432 struct ifnet *ifp; 1433 { 1434 struct wb_softc *sc; 1435 struct mbuf *m_head = NULL; 1436 struct wb_chain *cur_tx = NULL, *start_tx; 1437 1438 sc = ifp->if_softc; 1439 1440 /* 1441 * Check for an available queue slot. If there are none, 1442 * punt. 1443 */ 1444 if (sc->wb_cdata.wb_tx_free->wb_mbuf != NULL) { 1445 ifp->if_flags |= IFF_OACTIVE; 1446 return; 1447 } 1448 1449 start_tx = sc->wb_cdata.wb_tx_free; 1450 1451 while(sc->wb_cdata.wb_tx_free->wb_mbuf == NULL) { 1452 IFQ_DEQUEUE(&ifp->if_snd, m_head); 1453 if (m_head == NULL) 1454 break; 1455 1456 /* Pick a descriptor off the free list. */ 1457 cur_tx = sc->wb_cdata.wb_tx_free; 1458 sc->wb_cdata.wb_tx_free = cur_tx->wb_nextdesc; 1459 1460 /* Pack the data into the descriptor. */ 1461 wb_encap(sc, cur_tx, m_head); 1462 1463 if (cur_tx != start_tx) 1464 WB_TXOWN(cur_tx) = WB_TXSTAT_OWN; 1465 1466 #if NBPFILTER > 0 1467 /* 1468 * If there's a BPF listener, bounce a copy of this frame 1469 * to him. 1470 */ 1471 if (ifp->if_bpf) 1472 bpf_mtap(ifp->if_bpf, cur_tx->wb_mbuf); 1473 #endif 1474 } 1475 1476 /* 1477 * If there are no packets queued, bail. 1478 */ 1479 if (cur_tx == NULL) 1480 return; 1481 1482 /* 1483 * Place the request for the upload interrupt 1484 * in the last descriptor in the chain. This way, if 1485 * we're chaining several packets at once, we'll only 1486 * get an interupt once for the whole chain rather than 1487 * once for each packet. 1488 */ 1489 WB_TXCTL(cur_tx) |= WB_TXCTL_FINT; 1490 cur_tx->wb_ptr->wb_frag[0].wb_ctl |= WB_TXCTL_FINT; 1491 sc->wb_cdata.wb_tx_tail = cur_tx; 1492 1493 if (sc->wb_cdata.wb_tx_head == NULL) { 1494 sc->wb_cdata.wb_tx_head = start_tx; 1495 WB_TXOWN(start_tx) = WB_TXSTAT_OWN; 1496 CSR_WRITE_4(sc, WB_TXSTART, 0xFFFFFFFF); 1497 } else { 1498 /* 1499 * We need to distinguish between the case where 1500 * the own bit is clear because the chip cleared it 1501 * and where the own bit is clear because we haven't 1502 * set it yet. The magic value WB_UNSET is just some 1503 * ramdomly chosen number which doesn't have the own 1504 * bit set. When we actually transmit the frame, the 1505 * status word will have _only_ the own bit set, so 1506 * the txeoc handler will be able to tell if it needs 1507 * to initiate another transmission to flush out pending 1508 * frames. 1509 */ 1510 WB_TXOWN(start_tx) = WB_UNSENT; 1511 } 1512 1513 /* 1514 * Set a timeout in case the chip goes out to lunch. 1515 */ 1516 ifp->if_timer = 5; 1517 1518 return; 1519 } 1520 1521 void wb_init(xsc) 1522 void *xsc; 1523 { 1524 struct wb_softc *sc = xsc; 1525 struct ifnet *ifp = &sc->arpcom.ac_if; 1526 int s, i; 1527 1528 s = splimp(); 1529 1530 /* 1531 * Cancel pending I/O and free all RX/TX buffers. 1532 */ 1533 wb_stop(sc); 1534 wb_reset(sc); 1535 1536 sc->wb_txthresh = WB_TXTHRESH_INIT; 1537 1538 /* 1539 * Set cache alignment and burst length. 1540 */ 1541 #ifdef foo 1542 CSR_WRITE_4(sc, WB_BUSCTL, WB_BUSCTL_CONFIG); 1543 WB_CLRBIT(sc, WB_NETCFG, WB_NETCFG_TX_THRESH); 1544 WB_SETBIT(sc, WB_NETCFG, WB_TXTHRESH(sc->wb_txthresh)); 1545 #endif 1546 1547 CSR_WRITE_4(sc, WB_BUSCTL, WB_BUSCTL_MUSTBEONE|WB_BUSCTL_ARBITRATION); 1548 WB_SETBIT(sc, WB_BUSCTL, WB_BURSTLEN_16LONG); 1549 switch(sc->wb_cachesize) { 1550 case 32: 1551 WB_SETBIT(sc, WB_BUSCTL, WB_CACHEALIGN_32LONG); 1552 break; 1553 case 16: 1554 WB_SETBIT(sc, WB_BUSCTL, WB_CACHEALIGN_16LONG); 1555 break; 1556 case 8: 1557 WB_SETBIT(sc, WB_BUSCTL, WB_CACHEALIGN_8LONG); 1558 break; 1559 case 0: 1560 default: 1561 WB_SETBIT(sc, WB_BUSCTL, WB_CACHEALIGN_NONE); 1562 break; 1563 } 1564 1565 /* This doesn't tend to work too well at 100Mbps. */ 1566 WB_CLRBIT(sc, WB_NETCFG, WB_NETCFG_TX_EARLY_ON); 1567 1568 /* Init our MAC address */ 1569 for (i = 0; i < ETHER_ADDR_LEN; i++) { 1570 CSR_WRITE_1(sc, WB_NODE0 + i, sc->arpcom.ac_enaddr[i]); 1571 } 1572 1573 /* Init circular RX list. */ 1574 if (wb_list_rx_init(sc) == ENOBUFS) { 1575 printf("%s: initialization failed: no " 1576 "memory for rx buffers\n", sc->sc_dev.dv_xname); 1577 wb_stop(sc); 1578 (void)splx(s); 1579 return; 1580 } 1581 1582 /* Init TX descriptors. */ 1583 wb_list_tx_init(sc); 1584 1585 /* If we want promiscuous mode, set the allframes bit. */ 1586 if (ifp->if_flags & IFF_PROMISC) { 1587 WB_SETBIT(sc, WB_NETCFG, WB_NETCFG_RX_ALLPHYS); 1588 } else { 1589 WB_CLRBIT(sc, WB_NETCFG, WB_NETCFG_RX_ALLPHYS); 1590 } 1591 1592 /* 1593 * Set capture broadcast bit to capture broadcast frames. 1594 */ 1595 if (ifp->if_flags & IFF_BROADCAST) { 1596 WB_SETBIT(sc, WB_NETCFG, WB_NETCFG_RX_BROAD); 1597 } else { 1598 WB_CLRBIT(sc, WB_NETCFG, WB_NETCFG_RX_BROAD); 1599 } 1600 1601 /* 1602 * Program the multicast filter, if necessary. 1603 */ 1604 wb_setmulti(sc); 1605 1606 /* 1607 * Load the address of the RX list. 1608 */ 1609 WB_CLRBIT(sc, WB_NETCFG, WB_NETCFG_RX_ON); 1610 CSR_WRITE_4(sc, WB_RXADDR, vtophys(&sc->wb_ldata->wb_rx_list[0])); 1611 1612 /* 1613 * Enable interrupts. 1614 */ 1615 CSR_WRITE_4(sc, WB_IMR, WB_INTRS); 1616 CSR_WRITE_4(sc, WB_ISR, 0xFFFFFFFF); 1617 1618 /* Enable receiver and transmitter. */ 1619 WB_SETBIT(sc, WB_NETCFG, WB_NETCFG_RX_ON); 1620 CSR_WRITE_4(sc, WB_RXSTART, 0xFFFFFFFF); 1621 1622 WB_CLRBIT(sc, WB_NETCFG, WB_NETCFG_TX_ON); 1623 CSR_WRITE_4(sc, WB_TXADDR, vtophys(&sc->wb_ldata->wb_tx_list[0])); 1624 WB_SETBIT(sc, WB_NETCFG, WB_NETCFG_TX_ON); 1625 1626 ifp->if_flags |= IFF_RUNNING; 1627 ifp->if_flags &= ~IFF_OACTIVE; 1628 1629 (void)splx(s); 1630 1631 timeout_set(&sc->wb_tick_tmo, wb_tick, sc); 1632 timeout_add(&sc->wb_tick_tmo, hz); 1633 1634 return; 1635 } 1636 1637 /* 1638 * Set media options. 1639 */ 1640 int 1641 wb_ifmedia_upd(ifp) 1642 struct ifnet *ifp; 1643 { 1644 struct wb_softc *sc = ifp->if_softc; 1645 1646 if (ifp->if_flags & IFF_UP) 1647 wb_init(sc); 1648 1649 return(0); 1650 } 1651 1652 /* 1653 * Report current media status. 1654 */ 1655 void 1656 wb_ifmedia_sts(ifp, ifmr) 1657 struct ifnet *ifp; 1658 struct ifmediareq *ifmr; 1659 { 1660 struct wb_softc *sc = ifp->if_softc; 1661 struct mii_data *mii = &sc->sc_mii; 1662 1663 mii_pollstat(mii); 1664 ifmr->ifm_active = mii->mii_media_active; 1665 ifmr->ifm_status = mii->mii_media_status; 1666 } 1667 1668 int wb_ioctl(ifp, command, data) 1669 struct ifnet *ifp; 1670 u_long command; 1671 caddr_t data; 1672 { 1673 struct wb_softc *sc = ifp->if_softc; 1674 struct ifreq *ifr = (struct ifreq *) data; 1675 struct ifaddr *ifa = (struct ifaddr *)data; 1676 int s, error = 0; 1677 1678 s = splimp(); 1679 1680 if ((error = ether_ioctl(ifp, &sc->arpcom, command, data)) > 0) { 1681 splx(s); 1682 return (error); 1683 } 1684 1685 switch(command) { 1686 case SIOCSIFADDR: 1687 ifp->if_flags |= IFF_UP; 1688 switch (ifa->ifa_addr->sa_family) { 1689 #ifdef INET 1690 case AF_INET: 1691 wb_init(sc); 1692 arp_ifinit(&sc->arpcom, ifa); 1693 break; 1694 #endif /* INET */ 1695 default: 1696 wb_init(sc); 1697 } 1698 case SIOCSIFFLAGS: 1699 if (ifp->if_flags & IFF_UP) { 1700 wb_init(sc); 1701 } else { 1702 if (ifp->if_flags & IFF_RUNNING) 1703 wb_stop(sc); 1704 } 1705 error = 0; 1706 break; 1707 case SIOCADDMULTI: 1708 case SIOCDELMULTI: 1709 error = (command == SIOCADDMULTI) ? 1710 ether_addmulti(ifr, &sc->arpcom) : 1711 ether_delmulti(ifr, &sc->arpcom); 1712 1713 if (error == ENETRESET) { 1714 /* 1715 * Multicast list has changed; set the hardware 1716 * filter accordingly. 1717 */ 1718 wb_setmulti(sc); 1719 error = 0; 1720 } 1721 break; 1722 case SIOCGIFMEDIA: 1723 case SIOCSIFMEDIA: 1724 error = ifmedia_ioctl(ifp, ifr, &sc->sc_mii.mii_media, command); 1725 break; 1726 default: 1727 error = EINVAL; 1728 break; 1729 } 1730 1731 (void)splx(s); 1732 1733 return(error); 1734 } 1735 1736 void wb_watchdog(ifp) 1737 struct ifnet *ifp; 1738 { 1739 struct wb_softc *sc; 1740 1741 sc = ifp->if_softc; 1742 1743 ifp->if_oerrors++; 1744 printf("%s: watchdog timeout\n", sc->sc_dev.dv_xname); 1745 1746 #ifdef foo 1747 if (!(wb_phy_readreg(sc, PHY_BMSR) & PHY_BMSR_LINKSTAT)) 1748 printf("%s: no carrier - transceiver cable problem?\n", 1749 sc->sc_dev.dv_xname); 1750 #endif 1751 wb_stop(sc); 1752 wb_reset(sc); 1753 wb_init(sc); 1754 1755 if (!IFQ_IS_EMPTY(&ifp->if_snd)) 1756 wb_start(ifp); 1757 1758 return; 1759 } 1760 1761 /* 1762 * Stop the adapter and free any mbufs allocated to the 1763 * RX and TX lists. 1764 */ 1765 void wb_stop(sc) 1766 struct wb_softc *sc; 1767 { 1768 register int i; 1769 struct ifnet *ifp; 1770 1771 ifp = &sc->arpcom.ac_if; 1772 ifp->if_timer = 0; 1773 1774 timeout_del(&sc->wb_tick_tmo); 1775 1776 WB_CLRBIT(sc, WB_NETCFG, (WB_NETCFG_RX_ON|WB_NETCFG_TX_ON)); 1777 CSR_WRITE_4(sc, WB_IMR, 0x00000000); 1778 CSR_WRITE_4(sc, WB_TXADDR, 0x00000000); 1779 CSR_WRITE_4(sc, WB_RXADDR, 0x00000000); 1780 1781 /* 1782 * Free data in the RX lists. 1783 */ 1784 for (i = 0; i < WB_RX_LIST_CNT; i++) { 1785 if (sc->wb_cdata.wb_rx_chain[i].wb_mbuf != NULL) { 1786 m_freem(sc->wb_cdata.wb_rx_chain[i].wb_mbuf); 1787 sc->wb_cdata.wb_rx_chain[i].wb_mbuf = NULL; 1788 } 1789 } 1790 bzero((char *)&sc->wb_ldata->wb_rx_list, 1791 sizeof(sc->wb_ldata->wb_rx_list)); 1792 1793 /* 1794 * Free the TX list buffers. 1795 */ 1796 for (i = 0; i < WB_TX_LIST_CNT; i++) { 1797 if (sc->wb_cdata.wb_tx_chain[i].wb_mbuf != NULL) { 1798 m_freem(sc->wb_cdata.wb_tx_chain[i].wb_mbuf); 1799 sc->wb_cdata.wb_tx_chain[i].wb_mbuf = NULL; 1800 } 1801 } 1802 1803 bzero((char *)&sc->wb_ldata->wb_tx_list, 1804 sizeof(sc->wb_ldata->wb_tx_list)); 1805 1806 ifp->if_flags &= ~(IFF_RUNNING | IFF_OACTIVE); 1807 1808 return; 1809 } 1810 1811 /* 1812 * Stop all chip I/O so that the kernel's probe routines don't 1813 * get confused by errant DMAs when rebooting. 1814 */ 1815 void wb_shutdown(arg) 1816 void *arg; 1817 { 1818 struct wb_softc *sc = (struct wb_softc *)arg; 1819 1820 wb_stop(sc); 1821 1822 return; 1823 } 1824 1825 struct cfattach wb_ca = { 1826 sizeof(struct wb_softc), wb_probe, wb_attach 1827 }; 1828 1829 struct cfdriver wb_cd = { 1830 0, "wb", DV_IFNET 1831 }; 1832