1 /* $OpenBSD: if_wb.c,v 1.43 2008/11/28 02:44:18 brad Exp $ */ 2 3 /* 4 * Copyright (c) 1997, 1998 5 * Bill Paul <wpaul@ctr.columbia.edu>. All rights reserved. 6 * 7 * Redistribution and use in source and binary forms, with or without 8 * modification, are permitted provided that the following conditions 9 * are met: 10 * 1. Redistributions of source code must retain the above copyright 11 * notice, this list of conditions and the following disclaimer. 12 * 2. Redistributions in binary form must reproduce the above copyright 13 * notice, this list of conditions and the following disclaimer in the 14 * documentation and/or other materials provided with the distribution. 15 * 3. All advertising materials mentioning features or use of this software 16 * must display the following acknowledgement: 17 * This product includes software developed by Bill Paul. 18 * 4. Neither the name of the author nor the names of any co-contributors 19 * may be used to endorse or promote products derived from this software 20 * without specific prior written permission. 21 * 22 * THIS SOFTWARE IS PROVIDED BY Bill Paul AND CONTRIBUTORS ``AS IS'' AND 23 * ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE 24 * IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE 25 * ARE DISCLAIMED. IN NO EVENT SHALL Bill Paul OR THE VOICES IN HIS HEAD 26 * BE LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR 27 * CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF 28 * SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS 29 * INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN 30 * CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) 31 * ARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF 32 * THE POSSIBILITY OF SUCH DAMAGE. 33 * 34 * $FreeBSD: src/sys/pci/if_wb.c,v 1.26 1999/09/25 17:29:02 wpaul Exp $ 35 */ 36 37 /* 38 * Winbond fast ethernet PCI NIC driver 39 * 40 * Supports various cheap network adapters based on the Winbond W89C840F 41 * fast ethernet controller chip. This includes adapters manufactured by 42 * Winbond itself and some made by Linksys. 43 * 44 * Written by Bill Paul <wpaul@ctr.columbia.edu> 45 * Electrical Engineering Department 46 * Columbia University, New York City 47 */ 48 49 /* 50 * The Winbond W89C840F chip is a bus master; in some ways it resembles 51 * a DEC 'tulip' chip, only not as complicated. Unfortunately, it has 52 * one major difference which is that while the registers do many of 53 * the same things as a tulip adapter, the offsets are different: where 54 * tulip registers are typically spaced 8 bytes apart, the Winbond 55 * registers are spaced 4 bytes apart. The receiver filter is also 56 * programmed differently. 57 * 58 * Like the tulip, the Winbond chip uses small descriptors containing 59 * a status word, a control word and 32-bit areas that can either be used 60 * to point to two external data blocks, or to point to a single block 61 * and another descriptor in a linked list. Descriptors can be grouped 62 * together in blocks to form fixed length rings or can be chained 63 * together in linked lists. A single packet may be spread out over 64 * several descriptors if necessary. 65 * 66 * For the receive ring, this driver uses a linked list of descriptors, 67 * each pointing to a single mbuf cluster buffer, which us large enough 68 * to hold an entire packet. The link list is looped back to created a 69 * closed ring. 70 * 71 * For transmission, the driver creates a linked list of 'super descriptors' 72 * which each contain several individual descriptors linked together. 73 * Each 'super descriptor' contains WB_MAXFRAGS descriptors, which we 74 * abuse as fragment pointers. This allows us to use a buffer management 75 * scheme very similar to that used in the ThunderLAN and Etherlink XL 76 * drivers. 77 * 78 * Autonegotiation is performed using the external PHY via the MII bus. 79 * The sample boards I have all use a Davicom PHY. 80 * 81 * Note: the author of the Linux driver for the Winbond chip alludes 82 * to some sort of flaw in the chip's design that seems to mandate some 83 * drastic workaround which significantly impairs transmit performance. 84 * I have no idea what he's on about: transmit performance with all 85 * three of my test boards seems fine. 86 */ 87 88 #include "bpfilter.h" 89 90 #include <sys/param.h> 91 #include <sys/systm.h> 92 #include <sys/sockio.h> 93 #include <sys/mbuf.h> 94 #include <sys/malloc.h> 95 #include <sys/kernel.h> 96 #include <sys/socket.h> 97 #include <sys/device.h> 98 #include <sys/queue.h> 99 #include <sys/timeout.h> 100 101 #include <net/if.h> 102 #include <net/if_dl.h> 103 #include <net/if_types.h> 104 105 #ifdef INET 106 #include <netinet/in.h> 107 #include <netinet/in_systm.h> 108 #include <netinet/in_var.h> 109 #include <netinet/ip.h> 110 #include <netinet/if_ether.h> 111 #endif 112 113 #include <net/if_media.h> 114 115 #if NBPFILTER > 0 116 #include <net/bpf.h> 117 #endif 118 119 #include <uvm/uvm_extern.h> /* for vtophys */ 120 #define VTOPHYS(v) vtophys((vaddr_t)(v)) 121 122 #include <dev/mii/mii.h> 123 #include <dev/mii/miivar.h> 124 #include <dev/pci/pcireg.h> 125 #include <dev/pci/pcivar.h> 126 #include <dev/pci/pcidevs.h> 127 128 #define WB_USEIOSPACE 129 130 /* #define WB_BACKGROUND_AUTONEG */ 131 132 #include <dev/pci/if_wbreg.h> 133 134 int wb_probe(struct device *, void *, void *); 135 void wb_attach(struct device *, struct device *, void *); 136 137 void wb_bfree(caddr_t, u_int, void *); 138 void wb_newbuf(struct wb_softc *, struct wb_chain_onefrag *); 139 int wb_encap(struct wb_softc *, struct wb_chain *, struct mbuf *); 140 141 void wb_rxeof(struct wb_softc *); 142 void wb_rxeoc(struct wb_softc *); 143 void wb_txeof(struct wb_softc *); 144 void wb_txeoc(struct wb_softc *); 145 int wb_intr(void *); 146 void wb_tick(void *); 147 void wb_start(struct ifnet *); 148 int wb_ioctl(struct ifnet *, u_long, caddr_t); 149 void wb_init(void *); 150 void wb_stop(struct wb_softc *); 151 void wb_watchdog(struct ifnet *); 152 void wb_shutdown(void *); 153 int wb_ifmedia_upd(struct ifnet *); 154 void wb_ifmedia_sts(struct ifnet *, struct ifmediareq *); 155 156 void wb_eeprom_putbyte(struct wb_softc *, int); 157 void wb_eeprom_getword(struct wb_softc *, int, u_int16_t *); 158 void wb_read_eeprom(struct wb_softc *, caddr_t, int, int, int); 159 void wb_mii_sync(struct wb_softc *); 160 void wb_mii_send(struct wb_softc *, u_int32_t, int); 161 int wb_mii_readreg(struct wb_softc *, struct wb_mii_frame *); 162 int wb_mii_writereg(struct wb_softc *, struct wb_mii_frame *); 163 164 void wb_setcfg(struct wb_softc *, u_int32_t); 165 u_int8_t wb_calchash(caddr_t); 166 void wb_setmulti(struct wb_softc *); 167 void wb_reset(struct wb_softc *); 168 void wb_fixmedia(struct wb_softc *); 169 int wb_list_rx_init(struct wb_softc *); 170 int wb_list_tx_init(struct wb_softc *); 171 172 int wb_miibus_readreg(struct device *, int, int); 173 void wb_miibus_writereg(struct device *, int, int, int); 174 void wb_miibus_statchg(struct device *); 175 176 #define WB_SETBIT(sc, reg, x) \ 177 CSR_WRITE_4(sc, reg, \ 178 CSR_READ_4(sc, reg) | x) 179 180 #define WB_CLRBIT(sc, reg, x) \ 181 CSR_WRITE_4(sc, reg, \ 182 CSR_READ_4(sc, reg) & ~x) 183 184 #define SIO_SET(x) \ 185 CSR_WRITE_4(sc, WB_SIO, \ 186 CSR_READ_4(sc, WB_SIO) | x) 187 188 #define SIO_CLR(x) \ 189 CSR_WRITE_4(sc, WB_SIO, \ 190 CSR_READ_4(sc, WB_SIO) & ~x) 191 192 /* 193 * Send a read command and address to the EEPROM, check for ACK. 194 */ 195 void wb_eeprom_putbyte(sc, addr) 196 struct wb_softc *sc; 197 int addr; 198 { 199 int d, i; 200 201 d = addr | WB_EECMD_READ; 202 203 /* 204 * Feed in each bit and strobe the clock. 205 */ 206 for (i = 0x400; i; i >>= 1) { 207 if (d & i) { 208 SIO_SET(WB_SIO_EE_DATAIN); 209 } else { 210 SIO_CLR(WB_SIO_EE_DATAIN); 211 } 212 DELAY(100); 213 SIO_SET(WB_SIO_EE_CLK); 214 DELAY(150); 215 SIO_CLR(WB_SIO_EE_CLK); 216 DELAY(100); 217 } 218 219 return; 220 } 221 222 /* 223 * Read a word of data stored in the EEPROM at address 'addr.' 224 */ 225 void wb_eeprom_getword(sc, addr, dest) 226 struct wb_softc *sc; 227 int addr; 228 u_int16_t *dest; 229 { 230 int i; 231 u_int16_t word = 0; 232 233 /* Enter EEPROM access mode. */ 234 CSR_WRITE_4(sc, WB_SIO, WB_SIO_EESEL|WB_SIO_EE_CS); 235 236 /* 237 * Send address of word we want to read. 238 */ 239 wb_eeprom_putbyte(sc, addr); 240 241 CSR_WRITE_4(sc, WB_SIO, WB_SIO_EESEL|WB_SIO_EE_CS); 242 243 /* 244 * Start reading bits from EEPROM. 245 */ 246 for (i = 0x8000; i; i >>= 1) { 247 SIO_SET(WB_SIO_EE_CLK); 248 DELAY(100); 249 if (CSR_READ_4(sc, WB_SIO) & WB_SIO_EE_DATAOUT) 250 word |= i; 251 SIO_CLR(WB_SIO_EE_CLK); 252 DELAY(100); 253 } 254 255 /* Turn off EEPROM access mode. */ 256 CSR_WRITE_4(sc, WB_SIO, 0); 257 258 *dest = word; 259 260 return; 261 } 262 263 /* 264 * Read a sequence of words from the EEPROM. 265 */ 266 void wb_read_eeprom(sc, dest, off, cnt, swap) 267 struct wb_softc *sc; 268 caddr_t dest; 269 int off; 270 int cnt; 271 int swap; 272 { 273 int i; 274 u_int16_t word = 0, *ptr; 275 276 for (i = 0; i < cnt; i++) { 277 wb_eeprom_getword(sc, off + i, &word); 278 ptr = (u_int16_t *)(dest + (i * 2)); 279 if (swap) 280 *ptr = ntohs(word); 281 else 282 *ptr = word; 283 } 284 285 return; 286 } 287 288 /* 289 * Sync the PHYs by setting data bit and strobing the clock 32 times. 290 */ 291 void wb_mii_sync(sc) 292 struct wb_softc *sc; 293 { 294 int i; 295 296 SIO_SET(WB_SIO_MII_DIR|WB_SIO_MII_DATAIN); 297 298 for (i = 0; i < 32; i++) { 299 SIO_SET(WB_SIO_MII_CLK); 300 DELAY(1); 301 SIO_CLR(WB_SIO_MII_CLK); 302 DELAY(1); 303 } 304 305 return; 306 } 307 308 /* 309 * Clock a series of bits through the MII. 310 */ 311 void wb_mii_send(sc, bits, cnt) 312 struct wb_softc *sc; 313 u_int32_t bits; 314 int cnt; 315 { 316 int i; 317 318 SIO_CLR(WB_SIO_MII_CLK); 319 320 for (i = (0x1 << (cnt - 1)); i; i >>= 1) { 321 if (bits & i) { 322 SIO_SET(WB_SIO_MII_DATAIN); 323 } else { 324 SIO_CLR(WB_SIO_MII_DATAIN); 325 } 326 DELAY(1); 327 SIO_CLR(WB_SIO_MII_CLK); 328 DELAY(1); 329 SIO_SET(WB_SIO_MII_CLK); 330 } 331 } 332 333 /* 334 * Read an PHY register through the MII. 335 */ 336 int wb_mii_readreg(sc, frame) 337 struct wb_softc *sc; 338 struct wb_mii_frame *frame; 339 340 { 341 int i, ack, s; 342 343 s = splnet(); 344 345 /* 346 * Set up frame for RX. 347 */ 348 frame->mii_stdelim = WB_MII_STARTDELIM; 349 frame->mii_opcode = WB_MII_READOP; 350 frame->mii_turnaround = 0; 351 frame->mii_data = 0; 352 353 CSR_WRITE_4(sc, WB_SIO, 0); 354 355 /* 356 * Turn on data xmit. 357 */ 358 SIO_SET(WB_SIO_MII_DIR); 359 360 wb_mii_sync(sc); 361 362 /* 363 * Send command/address info. 364 */ 365 wb_mii_send(sc, frame->mii_stdelim, 2); 366 wb_mii_send(sc, frame->mii_opcode, 2); 367 wb_mii_send(sc, frame->mii_phyaddr, 5); 368 wb_mii_send(sc, frame->mii_regaddr, 5); 369 370 /* Idle bit */ 371 SIO_CLR((WB_SIO_MII_CLK|WB_SIO_MII_DATAIN)); 372 DELAY(1); 373 SIO_SET(WB_SIO_MII_CLK); 374 DELAY(1); 375 376 /* Turn off xmit. */ 377 SIO_CLR(WB_SIO_MII_DIR); 378 /* Check for ack */ 379 SIO_CLR(WB_SIO_MII_CLK); 380 DELAY(1); 381 ack = CSR_READ_4(sc, WB_SIO) & WB_SIO_MII_DATAOUT; 382 SIO_SET(WB_SIO_MII_CLK); 383 DELAY(1); 384 SIO_CLR(WB_SIO_MII_CLK); 385 DELAY(1); 386 SIO_SET(WB_SIO_MII_CLK); 387 DELAY(1); 388 389 /* 390 * Now try reading data bits. If the ack failed, we still 391 * need to clock through 16 cycles to keep the PHY(s) in sync. 392 */ 393 if (ack) { 394 for(i = 0; i < 16; i++) { 395 SIO_CLR(WB_SIO_MII_CLK); 396 DELAY(1); 397 SIO_SET(WB_SIO_MII_CLK); 398 DELAY(1); 399 } 400 goto fail; 401 } 402 403 for (i = 0x8000; i; i >>= 1) { 404 SIO_CLR(WB_SIO_MII_CLK); 405 DELAY(1); 406 if (!ack) { 407 if (CSR_READ_4(sc, WB_SIO) & WB_SIO_MII_DATAOUT) 408 frame->mii_data |= i; 409 DELAY(1); 410 } 411 SIO_SET(WB_SIO_MII_CLK); 412 DELAY(1); 413 } 414 415 fail: 416 417 SIO_CLR(WB_SIO_MII_CLK); 418 DELAY(1); 419 SIO_SET(WB_SIO_MII_CLK); 420 DELAY(1); 421 422 splx(s); 423 424 if (ack) 425 return(1); 426 return(0); 427 } 428 429 /* 430 * Write to a PHY register through the MII. 431 */ 432 int wb_mii_writereg(sc, frame) 433 struct wb_softc *sc; 434 struct wb_mii_frame *frame; 435 436 { 437 int s; 438 439 s = splnet(); 440 /* 441 * Set up frame for TX. 442 */ 443 444 frame->mii_stdelim = WB_MII_STARTDELIM; 445 frame->mii_opcode = WB_MII_WRITEOP; 446 frame->mii_turnaround = WB_MII_TURNAROUND; 447 448 /* 449 * Turn on data output. 450 */ 451 SIO_SET(WB_SIO_MII_DIR); 452 453 wb_mii_sync(sc); 454 455 wb_mii_send(sc, frame->mii_stdelim, 2); 456 wb_mii_send(sc, frame->mii_opcode, 2); 457 wb_mii_send(sc, frame->mii_phyaddr, 5); 458 wb_mii_send(sc, frame->mii_regaddr, 5); 459 wb_mii_send(sc, frame->mii_turnaround, 2); 460 wb_mii_send(sc, frame->mii_data, 16); 461 462 /* Idle bit. */ 463 SIO_SET(WB_SIO_MII_CLK); 464 DELAY(1); 465 SIO_CLR(WB_SIO_MII_CLK); 466 DELAY(1); 467 468 /* 469 * Turn off xmit. 470 */ 471 SIO_CLR(WB_SIO_MII_DIR); 472 473 splx(s); 474 475 return(0); 476 } 477 478 int 479 wb_miibus_readreg(dev, phy, reg) 480 struct device *dev; 481 int phy, reg; 482 { 483 struct wb_softc *sc = (struct wb_softc *)dev; 484 struct wb_mii_frame frame; 485 486 bzero((char *)&frame, sizeof(frame)); 487 488 frame.mii_phyaddr = phy; 489 frame.mii_regaddr = reg; 490 wb_mii_readreg(sc, &frame); 491 492 return(frame.mii_data); 493 } 494 495 void 496 wb_miibus_writereg(dev, phy, reg, data) 497 struct device *dev; 498 int phy, reg, data; 499 { 500 struct wb_softc *sc = (struct wb_softc *)dev; 501 struct wb_mii_frame frame; 502 503 bzero((char *)&frame, sizeof(frame)); 504 505 frame.mii_phyaddr = phy; 506 frame.mii_regaddr = reg; 507 frame.mii_data = data; 508 509 wb_mii_writereg(sc, &frame); 510 511 return; 512 } 513 514 void 515 wb_miibus_statchg(dev) 516 struct device *dev; 517 { 518 struct wb_softc *sc = (struct wb_softc *)dev; 519 520 wb_setcfg(sc, sc->sc_mii.mii_media_active); 521 } 522 523 /* 524 * Program the 64-bit multicast hash filter. 525 */ 526 void wb_setmulti(sc) 527 struct wb_softc *sc; 528 { 529 struct ifnet *ifp; 530 int h = 0; 531 u_int32_t hashes[2] = { 0, 0 }; 532 struct arpcom *ac = &sc->arpcom; 533 struct ether_multi *enm; 534 struct ether_multistep step; 535 u_int32_t rxfilt; 536 int mcnt = 0; 537 538 ifp = &sc->arpcom.ac_if; 539 540 rxfilt = CSR_READ_4(sc, WB_NETCFG); 541 542 allmulti: 543 if (ifp->if_flags & IFF_ALLMULTI || ifp->if_flags & IFF_PROMISC) { 544 rxfilt |= WB_NETCFG_RX_MULTI; 545 CSR_WRITE_4(sc, WB_NETCFG, rxfilt); 546 CSR_WRITE_4(sc, WB_MAR0, 0xFFFFFFFF); 547 CSR_WRITE_4(sc, WB_MAR1, 0xFFFFFFFF); 548 return; 549 } 550 551 /* first, zot all the existing hash bits */ 552 CSR_WRITE_4(sc, WB_MAR0, 0); 553 CSR_WRITE_4(sc, WB_MAR1, 0); 554 555 /* now program new ones */ 556 ETHER_FIRST_MULTI(step, ac, enm); 557 while (enm != NULL) { 558 if (bcmp(enm->enm_addrlo, enm->enm_addrhi, ETHER_ADDR_LEN)) { 559 ifp->if_flags |= IFF_ALLMULTI; 560 goto allmulti; 561 } 562 h = ~(ether_crc32_be(enm->enm_addrlo, ETHER_ADDR_LEN) >> 26); 563 if (h < 32) 564 hashes[0] |= (1 << h); 565 else 566 hashes[1] |= (1 << (h - 32)); 567 mcnt++; 568 ETHER_NEXT_MULTI(step, enm); 569 } 570 571 if (mcnt) 572 rxfilt |= WB_NETCFG_RX_MULTI; 573 else 574 rxfilt &= ~WB_NETCFG_RX_MULTI; 575 576 CSR_WRITE_4(sc, WB_MAR0, hashes[0]); 577 CSR_WRITE_4(sc, WB_MAR1, hashes[1]); 578 CSR_WRITE_4(sc, WB_NETCFG, rxfilt); 579 580 return; 581 } 582 583 /* 584 * The Winbond manual states that in order to fiddle with the 585 * 'full-duplex' and '100Mbps' bits in the netconfig register, we 586 * first have to put the transmit and/or receive logic in the idle state. 587 */ 588 void 589 wb_setcfg(sc, media) 590 struct wb_softc *sc; 591 u_int32_t media; 592 { 593 int i, restart = 0; 594 595 if (CSR_READ_4(sc, WB_NETCFG) & (WB_NETCFG_TX_ON|WB_NETCFG_RX_ON)) { 596 restart = 1; 597 WB_CLRBIT(sc, WB_NETCFG, (WB_NETCFG_TX_ON|WB_NETCFG_RX_ON)); 598 599 for (i = 0; i < WB_TIMEOUT; i++) { 600 DELAY(10); 601 if ((CSR_READ_4(sc, WB_ISR) & WB_ISR_TX_IDLE) && 602 (CSR_READ_4(sc, WB_ISR) & WB_ISR_RX_IDLE)) 603 break; 604 } 605 606 if (i == WB_TIMEOUT) 607 printf("%s: failed to force tx and " 608 "rx to idle state\n", sc->sc_dev.dv_xname); 609 } 610 611 if (IFM_SUBTYPE(media) == IFM_10_T) 612 WB_CLRBIT(sc, WB_NETCFG, WB_NETCFG_100MBPS); 613 else 614 WB_SETBIT(sc, WB_NETCFG, WB_NETCFG_100MBPS); 615 616 if ((media & IFM_GMASK) == IFM_FDX) 617 WB_SETBIT(sc, WB_NETCFG, WB_NETCFG_FULLDUPLEX); 618 else 619 WB_CLRBIT(sc, WB_NETCFG, WB_NETCFG_FULLDUPLEX); 620 621 if (restart) 622 WB_SETBIT(sc, WB_NETCFG, WB_NETCFG_TX_ON|WB_NETCFG_RX_ON); 623 624 return; 625 } 626 627 void 628 wb_reset(sc) 629 struct wb_softc *sc; 630 { 631 int i; 632 struct mii_data *mii = &sc->sc_mii; 633 634 CSR_WRITE_4(sc, WB_NETCFG, 0); 635 CSR_WRITE_4(sc, WB_BUSCTL, 0); 636 CSR_WRITE_4(sc, WB_TXADDR, 0); 637 CSR_WRITE_4(sc, WB_RXADDR, 0); 638 639 WB_SETBIT(sc, WB_BUSCTL, WB_BUSCTL_RESET); 640 WB_SETBIT(sc, WB_BUSCTL, WB_BUSCTL_RESET); 641 642 for (i = 0; i < WB_TIMEOUT; i++) { 643 DELAY(10); 644 if (!(CSR_READ_4(sc, WB_BUSCTL) & WB_BUSCTL_RESET)) 645 break; 646 } 647 if (i == WB_TIMEOUT) 648 printf("%s: reset never completed!\n", sc->sc_dev.dv_xname); 649 650 /* Wait a little while for the chip to get its brains in order. */ 651 DELAY(1000); 652 653 if (mii->mii_instance) { 654 struct mii_softc *miisc; 655 LIST_FOREACH(miisc, &mii->mii_phys, mii_list) 656 mii_phy_reset(miisc); 657 } 658 } 659 660 void 661 wb_fixmedia(sc) 662 struct wb_softc *sc; 663 { 664 struct mii_data *mii = &sc->sc_mii; 665 u_int32_t media; 666 667 if (LIST_FIRST(&mii->mii_phys) == NULL) 668 return; 669 670 mii_pollstat(mii); 671 if (IFM_SUBTYPE(mii->mii_media_active) == IFM_10_T) { 672 media = mii->mii_media_active & ~IFM_10_T; 673 media |= IFM_100_TX; 674 } if (IFM_SUBTYPE(mii->mii_media_active) == IFM_100_TX) { 675 media = mii->mii_media_active & ~IFM_100_TX; 676 media |= IFM_10_T; 677 } else 678 return; 679 680 ifmedia_set(&mii->mii_media, media); 681 } 682 683 const struct pci_matchid wb_devices[] = { 684 { PCI_VENDOR_WINBOND, PCI_PRODUCT_WINBOND_W89C840F }, 685 { PCI_VENDOR_COMPEX, PCI_PRODUCT_COMPEX_RL100ATX }, 686 }; 687 688 /* 689 * Probe for a Winbond chip. Check the PCI vendor and device 690 * IDs against our list and return a device name if we find a match. 691 */ 692 int 693 wb_probe(parent, match, aux) 694 struct device *parent; 695 void *match, *aux; 696 { 697 return (pci_matchbyid((struct pci_attach_args *)aux, wb_devices, 698 sizeof(wb_devices)/sizeof(wb_devices[0]))); 699 } 700 701 /* 702 * Attach the interface. Allocate softc structures, do ifmedia 703 * setup and ethernet/BPF attach. 704 */ 705 void 706 wb_attach(parent, self, aux) 707 struct device *parent, *self; 708 void *aux; 709 { 710 struct wb_softc *sc = (struct wb_softc *)self; 711 struct pci_attach_args *pa = aux; 712 pci_chipset_tag_t pc = pa->pa_pc; 713 pci_intr_handle_t ih; 714 const char *intrstr = NULL; 715 struct ifnet *ifp = &sc->arpcom.ac_if; 716 bus_size_t size; 717 int rseg; 718 pcireg_t command; 719 bus_dma_segment_t seg; 720 bus_dmamap_t dmamap; 721 caddr_t kva; 722 723 /* 724 * Handle power management nonsense. 725 */ 726 727 command = pci_conf_read(pc, pa->pa_tag, WB_PCI_CAPID) & 0x000000FF; 728 if (command == 0x01) { 729 730 command = pci_conf_read(pc, pa->pa_tag, WB_PCI_PWRMGMTCTRL); 731 if (command & WB_PSTATE_MASK) { 732 u_int32_t io, mem, irq; 733 734 /* Save important PCI config data. */ 735 io = pci_conf_read(pc, pa->pa_tag, WB_PCI_LOIO); 736 mem = pci_conf_read(pc, pa->pa_tag, WB_PCI_LOMEM); 737 irq = pci_conf_read(pc, pa->pa_tag, WB_PCI_INTLINE); 738 739 /* Reset the power state. */ 740 printf("%s: chip is in D%d power mode " 741 "-- setting to D0\n", sc->sc_dev.dv_xname, 742 command & WB_PSTATE_MASK); 743 command &= 0xFFFFFFFC; 744 pci_conf_write(pc, pa->pa_tag, WB_PCI_PWRMGMTCTRL, 745 command); 746 747 /* Restore PCI config data. */ 748 pci_conf_write(pc, pa->pa_tag, WB_PCI_LOIO, io); 749 pci_conf_write(pc, pa->pa_tag, WB_PCI_LOMEM, mem); 750 pci_conf_write(pc, pa->pa_tag, WB_PCI_INTLINE, irq); 751 } 752 } 753 754 /* 755 * Map control/status registers. 756 */ 757 758 #ifdef WB_USEIOSPACE 759 if (pci_mapreg_map(pa, WB_PCI_LOIO, PCI_MAPREG_TYPE_IO, 0, 760 &sc->wb_btag, &sc->wb_bhandle, NULL, &size, 0)) { 761 printf(": can't map i/o space\n"); 762 return; 763 } 764 #else 765 if (pci_mapreg_map(pa, WB_PCI_LOMEM, PCI_MAPREG_TYPE_MEM, 0, 766 &sc->wb_btag, &sc->wb_bhandle, NULL, &size, 0)){ 767 printf(": can't map mem space\n"); 768 return; 769 } 770 #endif 771 772 /* Allocate interrupt */ 773 if (pci_intr_map(pa, &ih)) { 774 printf(": couldn't map interrupt\n"); 775 goto fail_1; 776 } 777 intrstr = pci_intr_string(pc, ih); 778 sc->sc_ih = pci_intr_establish(pc, ih, IPL_NET, wb_intr, sc, 779 self->dv_xname); 780 if (sc->sc_ih == NULL) { 781 printf(": couldn't establish interrupt"); 782 if (intrstr != NULL) 783 printf(" at %s", intrstr); 784 printf("\n"); 785 goto fail_1; 786 } 787 printf(": %s", intrstr); 788 789 sc->wb_cachesize = pci_conf_read(pc, pa->pa_tag, WB_PCI_CACHELEN)&0xff; 790 791 /* Reset the adapter. */ 792 wb_reset(sc); 793 794 /* 795 * Get station address from the EEPROM. 796 */ 797 wb_read_eeprom(sc, (caddr_t)&sc->arpcom.ac_enaddr, 0, 3, 0); 798 printf(", address %s\n", ether_sprintf(sc->arpcom.ac_enaddr)); 799 800 if (bus_dmamem_alloc(pa->pa_dmat, sizeof(struct wb_list_data), 801 PAGE_SIZE, 0, &seg, 1, &rseg, BUS_DMA_NOWAIT)) { 802 printf(": can't alloc list data\n"); 803 goto fail_2; 804 } 805 if (bus_dmamem_map(pa->pa_dmat, &seg, rseg, 806 sizeof(struct wb_list_data), &kva, BUS_DMA_NOWAIT)) { 807 printf(": can't map list data, size %d\n", 808 sizeof(struct wb_list_data)); 809 goto fail_3; 810 } 811 if (bus_dmamap_create(pa->pa_dmat, sizeof(struct wb_list_data), 1, 812 sizeof(struct wb_list_data), 0, BUS_DMA_NOWAIT, &dmamap)) { 813 printf(": can't create dma map\n"); 814 goto fail_4; 815 } 816 if (bus_dmamap_load(pa->pa_dmat, dmamap, kva, 817 sizeof(struct wb_list_data), NULL, BUS_DMA_NOWAIT)) { 818 printf(": can't load dma map\n"); 819 goto fail_5; 820 } 821 sc->wb_ldata = (struct wb_list_data *)kva; 822 bzero(sc->wb_ldata, sizeof(struct wb_list_data)); 823 824 ifp->if_softc = sc; 825 ifp->if_flags = IFF_BROADCAST | IFF_SIMPLEX | IFF_MULTICAST; 826 ifp->if_ioctl = wb_ioctl; 827 ifp->if_start = wb_start; 828 ifp->if_watchdog = wb_watchdog; 829 ifp->if_baudrate = 10000000; 830 IFQ_SET_MAXLEN(&ifp->if_snd, WB_TX_LIST_CNT - 1); 831 IFQ_SET_READY(&ifp->if_snd); 832 833 bcopy(sc->sc_dev.dv_xname, ifp->if_xname, IFNAMSIZ); 834 835 /* 836 * Do ifmedia setup. 837 */ 838 wb_stop(sc); 839 840 ifmedia_init(&sc->sc_mii.mii_media, 0, wb_ifmedia_upd, wb_ifmedia_sts); 841 sc->sc_mii.mii_ifp = ifp; 842 sc->sc_mii.mii_readreg = wb_miibus_readreg; 843 sc->sc_mii.mii_writereg = wb_miibus_writereg; 844 sc->sc_mii.mii_statchg = wb_miibus_statchg; 845 mii_attach(self, &sc->sc_mii, 0xffffffff, MII_PHY_ANY, MII_OFFSET_ANY, 846 0); 847 if (LIST_FIRST(&sc->sc_mii.mii_phys) == NULL) { 848 ifmedia_add(&sc->sc_mii.mii_media, IFM_ETHER|IFM_NONE,0,NULL); 849 ifmedia_set(&sc->sc_mii.mii_media, IFM_ETHER|IFM_NONE); 850 } else 851 ifmedia_set(&sc->sc_mii.mii_media, IFM_ETHER|IFM_AUTO); 852 853 /* 854 * Call MI attach routines. 855 */ 856 if_attach(ifp); 857 ether_ifattach(ifp); 858 859 shutdownhook_establish(wb_shutdown, sc); 860 return; 861 862 fail_5: 863 bus_dmamap_destroy(pa->pa_dmat, dmamap); 864 865 fail_4: 866 bus_dmamem_unmap(pa->pa_dmat, kva, 867 sizeof(struct wb_list_data)); 868 869 fail_3: 870 bus_dmamem_free(pa->pa_dmat, &seg, rseg); 871 872 fail_2: 873 pci_intr_disestablish(pc, sc->sc_ih); 874 875 fail_1: 876 bus_space_unmap(sc->wb_btag, sc->wb_bhandle, size); 877 } 878 879 /* 880 * Initialize the transmit descriptors. 881 */ 882 int wb_list_tx_init(sc) 883 struct wb_softc *sc; 884 { 885 struct wb_chain_data *cd; 886 struct wb_list_data *ld; 887 int i; 888 889 cd = &sc->wb_cdata; 890 ld = sc->wb_ldata; 891 892 for (i = 0; i < WB_TX_LIST_CNT; i++) { 893 cd->wb_tx_chain[i].wb_ptr = &ld->wb_tx_list[i]; 894 if (i == (WB_TX_LIST_CNT - 1)) { 895 cd->wb_tx_chain[i].wb_nextdesc = 896 &cd->wb_tx_chain[0]; 897 } else { 898 cd->wb_tx_chain[i].wb_nextdesc = 899 &cd->wb_tx_chain[i + 1]; 900 } 901 } 902 903 cd->wb_tx_free = &cd->wb_tx_chain[0]; 904 cd->wb_tx_tail = cd->wb_tx_head = NULL; 905 906 return(0); 907 } 908 909 910 /* 911 * Initialize the RX descriptors and allocate mbufs for them. Note that 912 * we arrange the descriptors in a closed ring, so that the last descriptor 913 * points back to the first. 914 */ 915 int wb_list_rx_init(sc) 916 struct wb_softc *sc; 917 { 918 struct wb_chain_data *cd; 919 struct wb_list_data *ld; 920 int i; 921 922 cd = &sc->wb_cdata; 923 ld = sc->wb_ldata; 924 925 for (i = 0; i < WB_RX_LIST_CNT; i++) { 926 cd->wb_rx_chain[i].wb_ptr = 927 (struct wb_desc *)&ld->wb_rx_list[i]; 928 cd->wb_rx_chain[i].wb_buf = (void *)&ld->wb_rxbufs[i]; 929 wb_newbuf(sc, &cd->wb_rx_chain[i]); 930 if (i == (WB_RX_LIST_CNT - 1)) { 931 cd->wb_rx_chain[i].wb_nextdesc = &cd->wb_rx_chain[0]; 932 ld->wb_rx_list[i].wb_next = 933 VTOPHYS(&ld->wb_rx_list[0]); 934 } else { 935 cd->wb_rx_chain[i].wb_nextdesc = 936 &cd->wb_rx_chain[i + 1]; 937 ld->wb_rx_list[i].wb_next = 938 VTOPHYS(&ld->wb_rx_list[i + 1]); 939 } 940 } 941 942 cd->wb_rx_head = &cd->wb_rx_chain[0]; 943 944 return(0); 945 } 946 947 /* 948 * Initialize an RX descriptor and attach an MBUF cluster. 949 */ 950 void 951 wb_newbuf(sc, c) 952 struct wb_softc *sc; 953 struct wb_chain_onefrag *c; 954 { 955 c->wb_ptr->wb_data = VTOPHYS(c->wb_buf + sizeof(u_int64_t)); 956 c->wb_ptr->wb_ctl = WB_RXCTL_RLINK | ETHER_MAX_DIX_LEN; 957 c->wb_ptr->wb_status = WB_RXSTAT; 958 } 959 960 /* 961 * A frame has been uploaded: pass the resulting mbuf chain up to 962 * the higher level protocols. 963 */ 964 void wb_rxeof(sc) 965 struct wb_softc *sc; 966 { 967 struct ifnet *ifp; 968 struct wb_chain_onefrag *cur_rx; 969 int total_len = 0; 970 u_int32_t rxstat; 971 972 ifp = &sc->arpcom.ac_if; 973 974 while(!((rxstat = sc->wb_cdata.wb_rx_head->wb_ptr->wb_status) & 975 WB_RXSTAT_OWN)) { 976 struct mbuf *m; 977 978 cur_rx = sc->wb_cdata.wb_rx_head; 979 sc->wb_cdata.wb_rx_head = cur_rx->wb_nextdesc; 980 981 if ((rxstat & WB_RXSTAT_MIIERR) || 982 (WB_RXBYTES(cur_rx->wb_ptr->wb_status) < WB_MIN_FRAMELEN) || 983 (WB_RXBYTES(cur_rx->wb_ptr->wb_status) > ETHER_MAX_DIX_LEN) || 984 !(rxstat & WB_RXSTAT_LASTFRAG) || 985 !(rxstat & WB_RXSTAT_RXCMP)) { 986 ifp->if_ierrors++; 987 wb_newbuf(sc, cur_rx); 988 printf("%s: receiver babbling: possible chip " 989 "bug, forcing reset\n", sc->sc_dev.dv_xname); 990 wb_fixmedia(sc); 991 wb_reset(sc); 992 wb_init(sc); 993 return; 994 } 995 996 if (rxstat & WB_RXSTAT_RXERR) { 997 ifp->if_ierrors++; 998 wb_newbuf(sc, cur_rx); 999 break; 1000 } 1001 1002 /* No errors; receive the packet. */ 1003 total_len = WB_RXBYTES(cur_rx->wb_ptr->wb_status); 1004 1005 /* 1006 * XXX The Winbond chip includes the CRC with every 1007 * received frame, and there's no way to turn this 1008 * behavior off (at least, I can't find anything in 1009 * the manual that explains how to do it) so we have 1010 * to trim off the CRC manually. 1011 */ 1012 total_len -= ETHER_CRC_LEN; 1013 1014 m = m_devget(cur_rx->wb_buf + sizeof(u_int64_t), total_len, 1015 ETHER_ALIGN, ifp, NULL); 1016 wb_newbuf(sc, cur_rx); 1017 if (m == NULL) { 1018 ifp->if_ierrors++; 1019 break; 1020 } 1021 1022 ifp->if_ipackets++; 1023 1024 #if NBPFILTER > 0 1025 /* 1026 * Handle BPF listeners. Let the BPF user see the packet. 1027 */ 1028 if (ifp->if_bpf) 1029 bpf_mtap(ifp->if_bpf, m, BPF_DIRECTION_IN); 1030 #endif 1031 /* pass it on. */ 1032 ether_input_mbuf(ifp, m); 1033 } 1034 1035 return; 1036 } 1037 1038 void wb_rxeoc(sc) 1039 struct wb_softc *sc; 1040 { 1041 wb_rxeof(sc); 1042 1043 WB_CLRBIT(sc, WB_NETCFG, WB_NETCFG_RX_ON); 1044 CSR_WRITE_4(sc, WB_RXADDR, VTOPHYS(&sc->wb_ldata->wb_rx_list[0])); 1045 WB_SETBIT(sc, WB_NETCFG, WB_NETCFG_RX_ON); 1046 if (CSR_READ_4(sc, WB_ISR) & WB_RXSTATE_SUSPEND) 1047 CSR_WRITE_4(sc, WB_RXSTART, 0xFFFFFFFF); 1048 1049 return; 1050 } 1051 1052 /* 1053 * A frame was downloaded to the chip. It's safe for us to clean up 1054 * the list buffers. 1055 */ 1056 void wb_txeof(sc) 1057 struct wb_softc *sc; 1058 { 1059 struct wb_chain *cur_tx; 1060 struct ifnet *ifp; 1061 1062 ifp = &sc->arpcom.ac_if; 1063 1064 /* Clear the timeout timer. */ 1065 ifp->if_timer = 0; 1066 1067 if (sc->wb_cdata.wb_tx_head == NULL) 1068 return; 1069 1070 /* 1071 * Go through our tx list and free mbufs for those 1072 * frames that have been transmitted. 1073 */ 1074 while(sc->wb_cdata.wb_tx_head->wb_mbuf != NULL) { 1075 u_int32_t txstat; 1076 1077 cur_tx = sc->wb_cdata.wb_tx_head; 1078 txstat = WB_TXSTATUS(cur_tx); 1079 1080 if ((txstat & WB_TXSTAT_OWN) || txstat == WB_UNSENT) 1081 break; 1082 1083 if (txstat & WB_TXSTAT_TXERR) { 1084 ifp->if_oerrors++; 1085 if (txstat & WB_TXSTAT_ABORT) 1086 ifp->if_collisions++; 1087 if (txstat & WB_TXSTAT_LATECOLL) 1088 ifp->if_collisions++; 1089 } 1090 1091 ifp->if_collisions += (txstat & WB_TXSTAT_COLLCNT) >> 3; 1092 1093 ifp->if_opackets++; 1094 m_freem(cur_tx->wb_mbuf); 1095 cur_tx->wb_mbuf = NULL; 1096 1097 if (sc->wb_cdata.wb_tx_head == sc->wb_cdata.wb_tx_tail) { 1098 sc->wb_cdata.wb_tx_head = NULL; 1099 sc->wb_cdata.wb_tx_tail = NULL; 1100 break; 1101 } 1102 1103 sc->wb_cdata.wb_tx_head = cur_tx->wb_nextdesc; 1104 } 1105 1106 return; 1107 } 1108 1109 /* 1110 * TX 'end of channel' interrupt handler. 1111 */ 1112 void wb_txeoc(sc) 1113 struct wb_softc *sc; 1114 { 1115 struct ifnet *ifp; 1116 1117 ifp = &sc->arpcom.ac_if; 1118 1119 ifp->if_timer = 0; 1120 1121 if (sc->wb_cdata.wb_tx_head == NULL) { 1122 ifp->if_flags &= ~IFF_OACTIVE; 1123 sc->wb_cdata.wb_tx_tail = NULL; 1124 } else { 1125 if (WB_TXOWN(sc->wb_cdata.wb_tx_head) == WB_UNSENT) { 1126 WB_TXOWN(sc->wb_cdata.wb_tx_head) = WB_TXSTAT_OWN; 1127 ifp->if_timer = 5; 1128 CSR_WRITE_4(sc, WB_TXSTART, 0xFFFFFFFF); 1129 } 1130 } 1131 1132 return; 1133 } 1134 1135 int wb_intr(arg) 1136 void *arg; 1137 { 1138 struct wb_softc *sc; 1139 struct ifnet *ifp; 1140 u_int32_t status; 1141 int r = 0; 1142 1143 sc = arg; 1144 ifp = &sc->arpcom.ac_if; 1145 1146 if (!(ifp->if_flags & IFF_UP)) 1147 return (r); 1148 1149 /* Disable interrupts. */ 1150 CSR_WRITE_4(sc, WB_IMR, 0x00000000); 1151 1152 for (;;) { 1153 1154 status = CSR_READ_4(sc, WB_ISR); 1155 if (status) 1156 CSR_WRITE_4(sc, WB_ISR, status); 1157 1158 if ((status & WB_INTRS) == 0) 1159 break; 1160 1161 r = 1; 1162 1163 if ((status & WB_ISR_RX_NOBUF) || (status & WB_ISR_RX_ERR)) { 1164 ifp->if_ierrors++; 1165 wb_reset(sc); 1166 if (status & WB_ISR_RX_ERR) 1167 wb_fixmedia(sc); 1168 wb_init(sc); 1169 continue; 1170 } 1171 1172 if (status & WB_ISR_RX_OK) 1173 wb_rxeof(sc); 1174 1175 if (status & WB_ISR_RX_IDLE) 1176 wb_rxeoc(sc); 1177 1178 if (status & WB_ISR_TX_OK) 1179 wb_txeof(sc); 1180 1181 if (status & WB_ISR_TX_NOBUF) 1182 wb_txeoc(sc); 1183 1184 if (status & WB_ISR_TX_IDLE) { 1185 wb_txeof(sc); 1186 if (sc->wb_cdata.wb_tx_head != NULL) { 1187 WB_SETBIT(sc, WB_NETCFG, WB_NETCFG_TX_ON); 1188 CSR_WRITE_4(sc, WB_TXSTART, 0xFFFFFFFF); 1189 } 1190 } 1191 1192 if (status & WB_ISR_TX_UNDERRUN) { 1193 ifp->if_oerrors++; 1194 wb_txeof(sc); 1195 WB_CLRBIT(sc, WB_NETCFG, WB_NETCFG_TX_ON); 1196 /* Jack up TX threshold */ 1197 sc->wb_txthresh += WB_TXTHRESH_CHUNK; 1198 WB_CLRBIT(sc, WB_NETCFG, WB_NETCFG_TX_THRESH); 1199 WB_SETBIT(sc, WB_NETCFG, WB_TXTHRESH(sc->wb_txthresh)); 1200 WB_SETBIT(sc, WB_NETCFG, WB_NETCFG_TX_ON); 1201 } 1202 1203 if (status & WB_ISR_BUS_ERR) { 1204 wb_reset(sc); 1205 wb_init(sc); 1206 } 1207 1208 } 1209 1210 /* Re-enable interrupts. */ 1211 CSR_WRITE_4(sc, WB_IMR, WB_INTRS); 1212 1213 if (!IFQ_IS_EMPTY(&ifp->if_snd)) { 1214 wb_start(ifp); 1215 } 1216 1217 return (r); 1218 } 1219 1220 void 1221 wb_tick(xsc) 1222 void *xsc; 1223 { 1224 struct wb_softc *sc = xsc; 1225 int s; 1226 1227 s = splnet(); 1228 mii_tick(&sc->sc_mii); 1229 splx(s); 1230 timeout_add_sec(&sc->wb_tick_tmo, 1); 1231 } 1232 1233 /* 1234 * Encapsulate an mbuf chain in a descriptor by coupling the mbuf data 1235 * pointers to the fragment pointers. 1236 */ 1237 int wb_encap(sc, c, m_head) 1238 struct wb_softc *sc; 1239 struct wb_chain *c; 1240 struct mbuf *m_head; 1241 { 1242 int frag = 0; 1243 struct wb_desc *f = NULL; 1244 int total_len; 1245 struct mbuf *m; 1246 1247 /* 1248 * Start packing the mbufs in this chain into 1249 * the fragment pointers. Stop when we run out 1250 * of fragments or hit the end of the mbuf chain. 1251 */ 1252 m = m_head; 1253 total_len = 0; 1254 1255 for (m = m_head, frag = 0; m != NULL; m = m->m_next) { 1256 if (m->m_len != 0) { 1257 if (frag == WB_MAXFRAGS) 1258 break; 1259 total_len += m->m_len; 1260 f = &c->wb_ptr->wb_frag[frag]; 1261 f->wb_ctl = WB_TXCTL_TLINK | m->m_len; 1262 if (frag == 0) { 1263 f->wb_ctl |= WB_TXCTL_FIRSTFRAG; 1264 f->wb_status = 0; 1265 } else 1266 f->wb_status = WB_TXSTAT_OWN; 1267 f->wb_next = VTOPHYS(&c->wb_ptr->wb_frag[frag + 1]); 1268 f->wb_data = VTOPHYS(mtod(m, vaddr_t)); 1269 frag++; 1270 } 1271 } 1272 1273 /* 1274 * Handle special case: we used up all 16 fragments, 1275 * but we have more mbufs left in the chain. Copy the 1276 * data into an mbuf cluster. Note that we don't 1277 * bother clearing the values in the other fragment 1278 * pointers/counters; it wouldn't gain us anything, 1279 * and would waste cycles. 1280 */ 1281 if (m != NULL) { 1282 struct mbuf *m_new = NULL; 1283 1284 MGETHDR(m_new, M_DONTWAIT, MT_DATA); 1285 if (m_new == NULL) 1286 return(1); 1287 if (m_head->m_pkthdr.len > MHLEN) { 1288 MCLGET(m_new, M_DONTWAIT); 1289 if (!(m_new->m_flags & M_EXT)) { 1290 m_freem(m_new); 1291 return(1); 1292 } 1293 } 1294 m_copydata(m_head, 0, m_head->m_pkthdr.len, 1295 mtod(m_new, caddr_t)); 1296 m_new->m_pkthdr.len = m_new->m_len = m_head->m_pkthdr.len; 1297 m_freem(m_head); 1298 m_head = m_new; 1299 f = &c->wb_ptr->wb_frag[0]; 1300 f->wb_status = 0; 1301 f->wb_data = VTOPHYS(mtod(m_new, caddr_t)); 1302 f->wb_ctl = total_len = m_new->m_len; 1303 f->wb_ctl |= WB_TXCTL_TLINK|WB_TXCTL_FIRSTFRAG; 1304 frag = 1; 1305 } 1306 1307 if (total_len < WB_MIN_FRAMELEN) { 1308 f = &c->wb_ptr->wb_frag[frag]; 1309 f->wb_ctl = WB_MIN_FRAMELEN - total_len; 1310 f->wb_data = VTOPHYS(&sc->wb_cdata.wb_pad); 1311 f->wb_ctl |= WB_TXCTL_TLINK; 1312 f->wb_status = WB_TXSTAT_OWN; 1313 frag++; 1314 } 1315 1316 c->wb_mbuf = m_head; 1317 c->wb_lastdesc = frag - 1; 1318 WB_TXCTL(c) |= WB_TXCTL_LASTFRAG; 1319 WB_TXNEXT(c) = VTOPHYS(&c->wb_nextdesc->wb_ptr->wb_frag[0]); 1320 1321 return(0); 1322 } 1323 1324 /* 1325 * Main transmit routine. To avoid having to do mbuf copies, we put pointers 1326 * to the mbuf data regions directly in the transmit lists. We also save a 1327 * copy of the pointers since the transmit list fragment pointers are 1328 * physical addresses. 1329 */ 1330 1331 void wb_start(ifp) 1332 struct ifnet *ifp; 1333 { 1334 struct wb_softc *sc; 1335 struct mbuf *m_head = NULL; 1336 struct wb_chain *cur_tx = NULL, *start_tx; 1337 1338 sc = ifp->if_softc; 1339 1340 /* 1341 * Check for an available queue slot. If there are none, 1342 * punt. 1343 */ 1344 if (sc->wb_cdata.wb_tx_free->wb_mbuf != NULL) { 1345 ifp->if_flags |= IFF_OACTIVE; 1346 return; 1347 } 1348 1349 start_tx = sc->wb_cdata.wb_tx_free; 1350 1351 while(sc->wb_cdata.wb_tx_free->wb_mbuf == NULL) { 1352 IFQ_DEQUEUE(&ifp->if_snd, m_head); 1353 if (m_head == NULL) 1354 break; 1355 1356 /* Pick a descriptor off the free list. */ 1357 cur_tx = sc->wb_cdata.wb_tx_free; 1358 sc->wb_cdata.wb_tx_free = cur_tx->wb_nextdesc; 1359 1360 /* Pack the data into the descriptor. */ 1361 wb_encap(sc, cur_tx, m_head); 1362 1363 if (cur_tx != start_tx) 1364 WB_TXOWN(cur_tx) = WB_TXSTAT_OWN; 1365 1366 #if NBPFILTER > 0 1367 /* 1368 * If there's a BPF listener, bounce a copy of this frame 1369 * to him. 1370 */ 1371 if (ifp->if_bpf) 1372 bpf_mtap(ifp->if_bpf, cur_tx->wb_mbuf, 1373 BPF_DIRECTION_OUT); 1374 #endif 1375 } 1376 1377 /* 1378 * If there are no packets queued, bail. 1379 */ 1380 if (cur_tx == NULL) 1381 return; 1382 1383 /* 1384 * Place the request for the upload interrupt 1385 * in the last descriptor in the chain. This way, if 1386 * we're chaining several packets at once, we'll only 1387 * get an interrupt once for the whole chain rather than 1388 * once for each packet. 1389 */ 1390 WB_TXCTL(cur_tx) |= WB_TXCTL_FINT; 1391 cur_tx->wb_ptr->wb_frag[0].wb_ctl |= WB_TXCTL_FINT; 1392 sc->wb_cdata.wb_tx_tail = cur_tx; 1393 1394 if (sc->wb_cdata.wb_tx_head == NULL) { 1395 sc->wb_cdata.wb_tx_head = start_tx; 1396 WB_TXOWN(start_tx) = WB_TXSTAT_OWN; 1397 CSR_WRITE_4(sc, WB_TXSTART, 0xFFFFFFFF); 1398 } else { 1399 /* 1400 * We need to distinguish between the case where 1401 * the own bit is clear because the chip cleared it 1402 * and where the own bit is clear because we haven't 1403 * set it yet. The magic value WB_UNSET is just some 1404 * ramdomly chosen number which doesn't have the own 1405 * bit set. When we actually transmit the frame, the 1406 * status word will have _only_ the own bit set, so 1407 * the txeoc handler will be able to tell if it needs 1408 * to initiate another transmission to flush out pending 1409 * frames. 1410 */ 1411 WB_TXOWN(start_tx) = WB_UNSENT; 1412 } 1413 1414 /* 1415 * Set a timeout in case the chip goes out to lunch. 1416 */ 1417 ifp->if_timer = 5; 1418 1419 return; 1420 } 1421 1422 void wb_init(xsc) 1423 void *xsc; 1424 { 1425 struct wb_softc *sc = xsc; 1426 struct ifnet *ifp = &sc->arpcom.ac_if; 1427 int s, i; 1428 1429 s = splnet(); 1430 1431 /* 1432 * Cancel pending I/O and free all RX/TX buffers. 1433 */ 1434 wb_stop(sc); 1435 wb_reset(sc); 1436 1437 sc->wb_txthresh = WB_TXTHRESH_INIT; 1438 1439 /* 1440 * Set cache alignment and burst length. 1441 */ 1442 #ifdef foo 1443 CSR_WRITE_4(sc, WB_BUSCTL, WB_BUSCTL_CONFIG); 1444 WB_CLRBIT(sc, WB_NETCFG, WB_NETCFG_TX_THRESH); 1445 WB_SETBIT(sc, WB_NETCFG, WB_TXTHRESH(sc->wb_txthresh)); 1446 #endif 1447 1448 CSR_WRITE_4(sc, WB_BUSCTL, WB_BUSCTL_MUSTBEONE|WB_BUSCTL_ARBITRATION); 1449 WB_SETBIT(sc, WB_BUSCTL, WB_BURSTLEN_16LONG); 1450 switch(sc->wb_cachesize) { 1451 case 32: 1452 WB_SETBIT(sc, WB_BUSCTL, WB_CACHEALIGN_32LONG); 1453 break; 1454 case 16: 1455 WB_SETBIT(sc, WB_BUSCTL, WB_CACHEALIGN_16LONG); 1456 break; 1457 case 8: 1458 WB_SETBIT(sc, WB_BUSCTL, WB_CACHEALIGN_8LONG); 1459 break; 1460 case 0: 1461 default: 1462 WB_SETBIT(sc, WB_BUSCTL, WB_CACHEALIGN_NONE); 1463 break; 1464 } 1465 1466 /* This doesn't tend to work too well at 100Mbps. */ 1467 WB_CLRBIT(sc, WB_NETCFG, WB_NETCFG_TX_EARLY_ON); 1468 1469 /* Init our MAC address */ 1470 for (i = 0; i < ETHER_ADDR_LEN; i++) { 1471 CSR_WRITE_1(sc, WB_NODE0 + i, sc->arpcom.ac_enaddr[i]); 1472 } 1473 1474 /* Init circular RX list. */ 1475 if (wb_list_rx_init(sc) == ENOBUFS) { 1476 printf("%s: initialization failed: no " 1477 "memory for rx buffers\n", sc->sc_dev.dv_xname); 1478 wb_stop(sc); 1479 splx(s); 1480 return; 1481 } 1482 1483 /* Init TX descriptors. */ 1484 wb_list_tx_init(sc); 1485 1486 /* If we want promiscuous mode, set the allframes bit. */ 1487 if (ifp->if_flags & IFF_PROMISC) { 1488 WB_SETBIT(sc, WB_NETCFG, WB_NETCFG_RX_ALLPHYS); 1489 } else { 1490 WB_CLRBIT(sc, WB_NETCFG, WB_NETCFG_RX_ALLPHYS); 1491 } 1492 1493 /* 1494 * Set capture broadcast bit to capture broadcast frames. 1495 */ 1496 if (ifp->if_flags & IFF_BROADCAST) { 1497 WB_SETBIT(sc, WB_NETCFG, WB_NETCFG_RX_BROAD); 1498 } else { 1499 WB_CLRBIT(sc, WB_NETCFG, WB_NETCFG_RX_BROAD); 1500 } 1501 1502 /* 1503 * Program the multicast filter, if necessary. 1504 */ 1505 wb_setmulti(sc); 1506 1507 /* 1508 * Load the address of the RX list. 1509 */ 1510 WB_CLRBIT(sc, WB_NETCFG, WB_NETCFG_RX_ON); 1511 CSR_WRITE_4(sc, WB_RXADDR, VTOPHYS(&sc->wb_ldata->wb_rx_list[0])); 1512 1513 /* 1514 * Enable interrupts. 1515 */ 1516 CSR_WRITE_4(sc, WB_IMR, WB_INTRS); 1517 CSR_WRITE_4(sc, WB_ISR, 0xFFFFFFFF); 1518 1519 /* Enable receiver and transmitter. */ 1520 WB_SETBIT(sc, WB_NETCFG, WB_NETCFG_RX_ON); 1521 CSR_WRITE_4(sc, WB_RXSTART, 0xFFFFFFFF); 1522 1523 WB_CLRBIT(sc, WB_NETCFG, WB_NETCFG_TX_ON); 1524 CSR_WRITE_4(sc, WB_TXADDR, VTOPHYS(&sc->wb_ldata->wb_tx_list[0])); 1525 WB_SETBIT(sc, WB_NETCFG, WB_NETCFG_TX_ON); 1526 1527 ifp->if_flags |= IFF_RUNNING; 1528 ifp->if_flags &= ~IFF_OACTIVE; 1529 1530 splx(s); 1531 1532 timeout_set(&sc->wb_tick_tmo, wb_tick, sc); 1533 timeout_add_sec(&sc->wb_tick_tmo, 1); 1534 1535 return; 1536 } 1537 1538 /* 1539 * Set media options. 1540 */ 1541 int 1542 wb_ifmedia_upd(ifp) 1543 struct ifnet *ifp; 1544 { 1545 struct wb_softc *sc = ifp->if_softc; 1546 1547 if (ifp->if_flags & IFF_UP) 1548 wb_init(sc); 1549 1550 return(0); 1551 } 1552 1553 /* 1554 * Report current media status. 1555 */ 1556 void 1557 wb_ifmedia_sts(ifp, ifmr) 1558 struct ifnet *ifp; 1559 struct ifmediareq *ifmr; 1560 { 1561 struct wb_softc *sc = ifp->if_softc; 1562 struct mii_data *mii = &sc->sc_mii; 1563 1564 mii_pollstat(mii); 1565 ifmr->ifm_active = mii->mii_media_active; 1566 ifmr->ifm_status = mii->mii_media_status; 1567 } 1568 1569 int wb_ioctl(ifp, command, data) 1570 struct ifnet *ifp; 1571 u_long command; 1572 caddr_t data; 1573 { 1574 struct wb_softc *sc = ifp->if_softc; 1575 struct ifaddr *ifa = (struct ifaddr *) data; 1576 struct ifreq *ifr = (struct ifreq *) data; 1577 int s, error = 0; 1578 1579 s = splnet(); 1580 1581 switch(command) { 1582 case SIOCSIFADDR: 1583 ifp->if_flags |= IFF_UP; 1584 switch (ifa->ifa_addr->sa_family) { 1585 #ifdef INET 1586 case AF_INET: 1587 wb_init(sc); 1588 arp_ifinit(&sc->arpcom, ifa); 1589 break; 1590 #endif /* INET */ 1591 default: 1592 wb_init(sc); 1593 } 1594 break; 1595 1596 case SIOCSIFFLAGS: 1597 if (ifp->if_flags & IFF_UP) { 1598 wb_init(sc); 1599 } else { 1600 if (ifp->if_flags & IFF_RUNNING) 1601 wb_stop(sc); 1602 } 1603 error = 0; 1604 break; 1605 1606 case SIOCGIFMEDIA: 1607 case SIOCSIFMEDIA: 1608 error = ifmedia_ioctl(ifp, ifr, &sc->sc_mii.mii_media, command); 1609 break; 1610 1611 default: 1612 error = ether_ioctl(ifp, &sc->arpcom, command, data); 1613 } 1614 1615 if (error == ENETRESET) { 1616 if (ifp->if_flags & IFF_RUNNING) 1617 wb_setmulti(sc); 1618 error = 0; 1619 } 1620 1621 splx(s); 1622 return(error); 1623 } 1624 1625 void wb_watchdog(ifp) 1626 struct ifnet *ifp; 1627 { 1628 struct wb_softc *sc; 1629 1630 sc = ifp->if_softc; 1631 1632 ifp->if_oerrors++; 1633 printf("%s: watchdog timeout\n", sc->sc_dev.dv_xname); 1634 1635 #ifdef foo 1636 if (!(wb_phy_readreg(sc, PHY_BMSR) & PHY_BMSR_LINKSTAT)) 1637 printf("%s: no carrier - transceiver cable problem?\n", 1638 sc->sc_dev.dv_xname); 1639 #endif 1640 wb_stop(sc); 1641 wb_reset(sc); 1642 wb_init(sc); 1643 1644 if (!IFQ_IS_EMPTY(&ifp->if_snd)) 1645 wb_start(ifp); 1646 1647 return; 1648 } 1649 1650 /* 1651 * Stop the adapter and free any mbufs allocated to the 1652 * RX and TX lists. 1653 */ 1654 void wb_stop(sc) 1655 struct wb_softc *sc; 1656 { 1657 int i; 1658 struct ifnet *ifp; 1659 1660 ifp = &sc->arpcom.ac_if; 1661 ifp->if_timer = 0; 1662 1663 timeout_del(&sc->wb_tick_tmo); 1664 1665 ifp->if_flags &= ~(IFF_RUNNING | IFF_OACTIVE); 1666 1667 WB_CLRBIT(sc, WB_NETCFG, (WB_NETCFG_RX_ON|WB_NETCFG_TX_ON)); 1668 CSR_WRITE_4(sc, WB_IMR, 0x00000000); 1669 CSR_WRITE_4(sc, WB_TXADDR, 0x00000000); 1670 CSR_WRITE_4(sc, WB_RXADDR, 0x00000000); 1671 1672 /* 1673 * Free data in the RX lists. 1674 */ 1675 bzero((char *)&sc->wb_ldata->wb_rx_list, 1676 sizeof(sc->wb_ldata->wb_rx_list)); 1677 1678 /* 1679 * Free the TX list buffers. 1680 */ 1681 for (i = 0; i < WB_TX_LIST_CNT; i++) { 1682 if (sc->wb_cdata.wb_tx_chain[i].wb_mbuf != NULL) { 1683 m_freem(sc->wb_cdata.wb_tx_chain[i].wb_mbuf); 1684 sc->wb_cdata.wb_tx_chain[i].wb_mbuf = NULL; 1685 } 1686 } 1687 1688 bzero((char *)&sc->wb_ldata->wb_tx_list, 1689 sizeof(sc->wb_ldata->wb_tx_list)); 1690 } 1691 1692 /* 1693 * Stop all chip I/O so that the kernel's probe routines don't 1694 * get confused by errant DMAs when rebooting. 1695 */ 1696 void wb_shutdown(arg) 1697 void *arg; 1698 { 1699 struct wb_softc *sc = (struct wb_softc *)arg; 1700 1701 wb_stop(sc); 1702 1703 return; 1704 } 1705 1706 struct cfattach wb_ca = { 1707 sizeof(struct wb_softc), wb_probe, wb_attach 1708 }; 1709 1710 struct cfdriver wb_cd = { 1711 0, "wb", DV_IFNET 1712 }; 1713