1 /* $OpenBSD: if_wb.c,v 1.55 2013/11/26 09:50:33 mpi Exp $ */ 2 3 /* 4 * Copyright (c) 1997, 1998 5 * Bill Paul <wpaul@ctr.columbia.edu>. All rights reserved. 6 * 7 * Redistribution and use in source and binary forms, with or without 8 * modification, are permitted provided that the following conditions 9 * are met: 10 * 1. Redistributions of source code must retain the above copyright 11 * notice, this list of conditions and the following disclaimer. 12 * 2. Redistributions in binary form must reproduce the above copyright 13 * notice, this list of conditions and the following disclaimer in the 14 * documentation and/or other materials provided with the distribution. 15 * 3. All advertising materials mentioning features or use of this software 16 * must display the following acknowledgement: 17 * This product includes software developed by Bill Paul. 18 * 4. Neither the name of the author nor the names of any co-contributors 19 * may be used to endorse or promote products derived from this software 20 * without specific prior written permission. 21 * 22 * THIS SOFTWARE IS PROVIDED BY Bill Paul AND CONTRIBUTORS ``AS IS'' AND 23 * ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE 24 * IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE 25 * ARE DISCLAIMED. IN NO EVENT SHALL Bill Paul OR THE VOICES IN HIS HEAD 26 * BE LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR 27 * CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF 28 * SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS 29 * INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN 30 * CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) 31 * ARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF 32 * THE POSSIBILITY OF SUCH DAMAGE. 33 * 34 * $FreeBSD: src/sys/pci/if_wb.c,v 1.26 1999/09/25 17:29:02 wpaul Exp $ 35 */ 36 37 /* 38 * Winbond fast ethernet PCI NIC driver 39 * 40 * Supports various cheap network adapters based on the Winbond W89C840F 41 * fast ethernet controller chip. This includes adapters manufactured by 42 * Winbond itself and some made by Linksys. 43 * 44 * Written by Bill Paul <wpaul@ctr.columbia.edu> 45 * Electrical Engineering Department 46 * Columbia University, New York City 47 */ 48 49 /* 50 * The Winbond W89C840F chip is a bus master; in some ways it resembles 51 * a DEC 'tulip' chip, only not as complicated. Unfortunately, it has 52 * one major difference which is that while the registers do many of 53 * the same things as a tulip adapter, the offsets are different: where 54 * tulip registers are typically spaced 8 bytes apart, the Winbond 55 * registers are spaced 4 bytes apart. The receiver filter is also 56 * programmed differently. 57 * 58 * Like the tulip, the Winbond chip uses small descriptors containing 59 * a status word, a control word and 32-bit areas that can either be used 60 * to point to two external data blocks, or to point to a single block 61 * and another descriptor in a linked list. Descriptors can be grouped 62 * together in blocks to form fixed length rings or can be chained 63 * together in linked lists. A single packet may be spread out over 64 * several descriptors if necessary. 65 * 66 * For the receive ring, this driver uses a linked list of descriptors, 67 * each pointing to a single mbuf cluster buffer, which us large enough 68 * to hold an entire packet. The link list is looped back to created a 69 * closed ring. 70 * 71 * For transmission, the driver creates a linked list of 'super descriptors' 72 * which each contain several individual descriptors linked together. 73 * Each 'super descriptor' contains WB_MAXFRAGS descriptors, which we 74 * abuse as fragment pointers. This allows us to use a buffer management 75 * scheme very similar to that used in the ThunderLAN and Etherlink XL 76 * drivers. 77 * 78 * Autonegotiation is performed using the external PHY via the MII bus. 79 * The sample boards I have all use a Davicom PHY. 80 * 81 * Note: the author of the Linux driver for the Winbond chip alludes 82 * to some sort of flaw in the chip's design that seems to mandate some 83 * drastic workaround which significantly impairs transmit performance. 84 * I have no idea what he's on about: transmit performance with all 85 * three of my test boards seems fine. 86 */ 87 88 #include "bpfilter.h" 89 90 #include <sys/param.h> 91 #include <sys/systm.h> 92 #include <sys/sockio.h> 93 #include <sys/mbuf.h> 94 #include <sys/malloc.h> 95 #include <sys/kernel.h> 96 #include <sys/socket.h> 97 #include <sys/device.h> 98 #include <sys/queue.h> 99 #include <sys/timeout.h> 100 101 #include <net/if.h> 102 #include <net/if_dl.h> 103 #include <net/if_types.h> 104 105 #ifdef INET 106 #include <netinet/in.h> 107 #include <netinet/in_systm.h> 108 #include <netinet/ip.h> 109 #include <netinet/if_ether.h> 110 #endif 111 112 #include <net/if_media.h> 113 114 #if NBPFILTER > 0 115 #include <net/bpf.h> 116 #endif 117 118 #include <uvm/uvm_extern.h> /* for vtophys */ 119 #define VTOPHYS(v) vtophys((vaddr_t)(v)) 120 121 #include <dev/mii/mii.h> 122 #include <dev/mii/miivar.h> 123 #include <dev/pci/pcireg.h> 124 #include <dev/pci/pcivar.h> 125 #include <dev/pci/pcidevs.h> 126 127 #define WB_USEIOSPACE 128 129 /* #define WB_BACKGROUND_AUTONEG */ 130 131 #include <dev/pci/if_wbreg.h> 132 133 int wb_probe(struct device *, void *, void *); 134 void wb_attach(struct device *, struct device *, void *); 135 136 void wb_bfree(caddr_t, u_int, void *); 137 void wb_newbuf(struct wb_softc *, struct wb_chain_onefrag *); 138 int wb_encap(struct wb_softc *, struct wb_chain *, struct mbuf *); 139 140 void wb_rxeof(struct wb_softc *); 141 void wb_rxeoc(struct wb_softc *); 142 void wb_txeof(struct wb_softc *); 143 void wb_txeoc(struct wb_softc *); 144 int wb_intr(void *); 145 void wb_tick(void *); 146 void wb_start(struct ifnet *); 147 int wb_ioctl(struct ifnet *, u_long, caddr_t); 148 void wb_init(void *); 149 void wb_stop(struct wb_softc *); 150 void wb_watchdog(struct ifnet *); 151 int wb_ifmedia_upd(struct ifnet *); 152 void wb_ifmedia_sts(struct ifnet *, struct ifmediareq *); 153 154 void wb_eeprom_putbyte(struct wb_softc *, int); 155 void wb_eeprom_getword(struct wb_softc *, int, u_int16_t *); 156 void wb_read_eeprom(struct wb_softc *, caddr_t, int, int, int); 157 void wb_mii_sync(struct wb_softc *); 158 void wb_mii_send(struct wb_softc *, u_int32_t, int); 159 int wb_mii_readreg(struct wb_softc *, struct wb_mii_frame *); 160 int wb_mii_writereg(struct wb_softc *, struct wb_mii_frame *); 161 162 void wb_setcfg(struct wb_softc *, u_int32_t); 163 u_int8_t wb_calchash(caddr_t); 164 void wb_setmulti(struct wb_softc *); 165 void wb_reset(struct wb_softc *); 166 void wb_fixmedia(struct wb_softc *); 167 int wb_list_rx_init(struct wb_softc *); 168 int wb_list_tx_init(struct wb_softc *); 169 170 int wb_miibus_readreg(struct device *, int, int); 171 void wb_miibus_writereg(struct device *, int, int, int); 172 void wb_miibus_statchg(struct device *); 173 174 #define WB_SETBIT(sc, reg, x) \ 175 CSR_WRITE_4(sc, reg, \ 176 CSR_READ_4(sc, reg) | x) 177 178 #define WB_CLRBIT(sc, reg, x) \ 179 CSR_WRITE_4(sc, reg, \ 180 CSR_READ_4(sc, reg) & ~x) 181 182 #define SIO_SET(x) \ 183 CSR_WRITE_4(sc, WB_SIO, \ 184 CSR_READ_4(sc, WB_SIO) | x) 185 186 #define SIO_CLR(x) \ 187 CSR_WRITE_4(sc, WB_SIO, \ 188 CSR_READ_4(sc, WB_SIO) & ~x) 189 190 /* 191 * Send a read command and address to the EEPROM, check for ACK. 192 */ 193 void wb_eeprom_putbyte(sc, addr) 194 struct wb_softc *sc; 195 int addr; 196 { 197 int d, i; 198 199 d = addr | WB_EECMD_READ; 200 201 /* 202 * Feed in each bit and strobe the clock. 203 */ 204 for (i = 0x400; i; i >>= 1) { 205 if (d & i) { 206 SIO_SET(WB_SIO_EE_DATAIN); 207 } else { 208 SIO_CLR(WB_SIO_EE_DATAIN); 209 } 210 DELAY(100); 211 SIO_SET(WB_SIO_EE_CLK); 212 DELAY(150); 213 SIO_CLR(WB_SIO_EE_CLK); 214 DELAY(100); 215 } 216 217 return; 218 } 219 220 /* 221 * Read a word of data stored in the EEPROM at address 'addr.' 222 */ 223 void wb_eeprom_getword(sc, addr, dest) 224 struct wb_softc *sc; 225 int addr; 226 u_int16_t *dest; 227 { 228 int i; 229 u_int16_t word = 0; 230 231 /* Enter EEPROM access mode. */ 232 CSR_WRITE_4(sc, WB_SIO, WB_SIO_EESEL|WB_SIO_EE_CS); 233 234 /* 235 * Send address of word we want to read. 236 */ 237 wb_eeprom_putbyte(sc, addr); 238 239 CSR_WRITE_4(sc, WB_SIO, WB_SIO_EESEL|WB_SIO_EE_CS); 240 241 /* 242 * Start reading bits from EEPROM. 243 */ 244 for (i = 0x8000; i; i >>= 1) { 245 SIO_SET(WB_SIO_EE_CLK); 246 DELAY(100); 247 if (CSR_READ_4(sc, WB_SIO) & WB_SIO_EE_DATAOUT) 248 word |= i; 249 SIO_CLR(WB_SIO_EE_CLK); 250 DELAY(100); 251 } 252 253 /* Turn off EEPROM access mode. */ 254 CSR_WRITE_4(sc, WB_SIO, 0); 255 256 *dest = word; 257 258 return; 259 } 260 261 /* 262 * Read a sequence of words from the EEPROM. 263 */ 264 void wb_read_eeprom(sc, dest, off, cnt, swap) 265 struct wb_softc *sc; 266 caddr_t dest; 267 int off; 268 int cnt; 269 int swap; 270 { 271 int i; 272 u_int16_t word = 0, *ptr; 273 274 for (i = 0; i < cnt; i++) { 275 wb_eeprom_getword(sc, off + i, &word); 276 ptr = (u_int16_t *)(dest + (i * 2)); 277 if (swap) 278 *ptr = ntohs(word); 279 else 280 *ptr = word; 281 } 282 283 return; 284 } 285 286 /* 287 * Sync the PHYs by setting data bit and strobing the clock 32 times. 288 */ 289 void wb_mii_sync(sc) 290 struct wb_softc *sc; 291 { 292 int i; 293 294 SIO_SET(WB_SIO_MII_DIR|WB_SIO_MII_DATAIN); 295 296 for (i = 0; i < 32; i++) { 297 SIO_SET(WB_SIO_MII_CLK); 298 DELAY(1); 299 SIO_CLR(WB_SIO_MII_CLK); 300 DELAY(1); 301 } 302 303 return; 304 } 305 306 /* 307 * Clock a series of bits through the MII. 308 */ 309 void wb_mii_send(sc, bits, cnt) 310 struct wb_softc *sc; 311 u_int32_t bits; 312 int cnt; 313 { 314 int i; 315 316 SIO_CLR(WB_SIO_MII_CLK); 317 318 for (i = (0x1 << (cnt - 1)); i; i >>= 1) { 319 if (bits & i) { 320 SIO_SET(WB_SIO_MII_DATAIN); 321 } else { 322 SIO_CLR(WB_SIO_MII_DATAIN); 323 } 324 DELAY(1); 325 SIO_CLR(WB_SIO_MII_CLK); 326 DELAY(1); 327 SIO_SET(WB_SIO_MII_CLK); 328 } 329 } 330 331 /* 332 * Read an PHY register through the MII. 333 */ 334 int wb_mii_readreg(sc, frame) 335 struct wb_softc *sc; 336 struct wb_mii_frame *frame; 337 338 { 339 int i, ack, s; 340 341 s = splnet(); 342 343 /* 344 * Set up frame for RX. 345 */ 346 frame->mii_stdelim = WB_MII_STARTDELIM; 347 frame->mii_opcode = WB_MII_READOP; 348 frame->mii_turnaround = 0; 349 frame->mii_data = 0; 350 351 CSR_WRITE_4(sc, WB_SIO, 0); 352 353 /* 354 * Turn on data xmit. 355 */ 356 SIO_SET(WB_SIO_MII_DIR); 357 358 wb_mii_sync(sc); 359 360 /* 361 * Send command/address info. 362 */ 363 wb_mii_send(sc, frame->mii_stdelim, 2); 364 wb_mii_send(sc, frame->mii_opcode, 2); 365 wb_mii_send(sc, frame->mii_phyaddr, 5); 366 wb_mii_send(sc, frame->mii_regaddr, 5); 367 368 /* Idle bit */ 369 SIO_CLR((WB_SIO_MII_CLK|WB_SIO_MII_DATAIN)); 370 DELAY(1); 371 SIO_SET(WB_SIO_MII_CLK); 372 DELAY(1); 373 374 /* Turn off xmit. */ 375 SIO_CLR(WB_SIO_MII_DIR); 376 /* Check for ack */ 377 SIO_CLR(WB_SIO_MII_CLK); 378 DELAY(1); 379 ack = CSR_READ_4(sc, WB_SIO) & WB_SIO_MII_DATAOUT; 380 SIO_SET(WB_SIO_MII_CLK); 381 DELAY(1); 382 SIO_CLR(WB_SIO_MII_CLK); 383 DELAY(1); 384 SIO_SET(WB_SIO_MII_CLK); 385 DELAY(1); 386 387 /* 388 * Now try reading data bits. If the ack failed, we still 389 * need to clock through 16 cycles to keep the PHY(s) in sync. 390 */ 391 if (ack) { 392 for(i = 0; i < 16; i++) { 393 SIO_CLR(WB_SIO_MII_CLK); 394 DELAY(1); 395 SIO_SET(WB_SIO_MII_CLK); 396 DELAY(1); 397 } 398 goto fail; 399 } 400 401 for (i = 0x8000; i; i >>= 1) { 402 SIO_CLR(WB_SIO_MII_CLK); 403 DELAY(1); 404 if (!ack) { 405 if (CSR_READ_4(sc, WB_SIO) & WB_SIO_MII_DATAOUT) 406 frame->mii_data |= i; 407 DELAY(1); 408 } 409 SIO_SET(WB_SIO_MII_CLK); 410 DELAY(1); 411 } 412 413 fail: 414 415 SIO_CLR(WB_SIO_MII_CLK); 416 DELAY(1); 417 SIO_SET(WB_SIO_MII_CLK); 418 DELAY(1); 419 420 splx(s); 421 422 if (ack) 423 return(1); 424 return(0); 425 } 426 427 /* 428 * Write to a PHY register through the MII. 429 */ 430 int wb_mii_writereg(sc, frame) 431 struct wb_softc *sc; 432 struct wb_mii_frame *frame; 433 434 { 435 int s; 436 437 s = splnet(); 438 /* 439 * Set up frame for TX. 440 */ 441 442 frame->mii_stdelim = WB_MII_STARTDELIM; 443 frame->mii_opcode = WB_MII_WRITEOP; 444 frame->mii_turnaround = WB_MII_TURNAROUND; 445 446 /* 447 * Turn on data output. 448 */ 449 SIO_SET(WB_SIO_MII_DIR); 450 451 wb_mii_sync(sc); 452 453 wb_mii_send(sc, frame->mii_stdelim, 2); 454 wb_mii_send(sc, frame->mii_opcode, 2); 455 wb_mii_send(sc, frame->mii_phyaddr, 5); 456 wb_mii_send(sc, frame->mii_regaddr, 5); 457 wb_mii_send(sc, frame->mii_turnaround, 2); 458 wb_mii_send(sc, frame->mii_data, 16); 459 460 /* Idle bit. */ 461 SIO_SET(WB_SIO_MII_CLK); 462 DELAY(1); 463 SIO_CLR(WB_SIO_MII_CLK); 464 DELAY(1); 465 466 /* 467 * Turn off xmit. 468 */ 469 SIO_CLR(WB_SIO_MII_DIR); 470 471 splx(s); 472 473 return(0); 474 } 475 476 int 477 wb_miibus_readreg(dev, phy, reg) 478 struct device *dev; 479 int phy, reg; 480 { 481 struct wb_softc *sc = (struct wb_softc *)dev; 482 struct wb_mii_frame frame; 483 484 bzero(&frame, sizeof(frame)); 485 486 frame.mii_phyaddr = phy; 487 frame.mii_regaddr = reg; 488 wb_mii_readreg(sc, &frame); 489 490 return(frame.mii_data); 491 } 492 493 void 494 wb_miibus_writereg(dev, phy, reg, data) 495 struct device *dev; 496 int phy, reg, data; 497 { 498 struct wb_softc *sc = (struct wb_softc *)dev; 499 struct wb_mii_frame frame; 500 501 bzero(&frame, sizeof(frame)); 502 503 frame.mii_phyaddr = phy; 504 frame.mii_regaddr = reg; 505 frame.mii_data = data; 506 507 wb_mii_writereg(sc, &frame); 508 509 return; 510 } 511 512 void 513 wb_miibus_statchg(dev) 514 struct device *dev; 515 { 516 struct wb_softc *sc = (struct wb_softc *)dev; 517 518 wb_setcfg(sc, sc->sc_mii.mii_media_active); 519 } 520 521 /* 522 * Program the 64-bit multicast hash filter. 523 */ 524 void wb_setmulti(sc) 525 struct wb_softc *sc; 526 { 527 struct ifnet *ifp; 528 int h = 0; 529 u_int32_t hashes[2] = { 0, 0 }; 530 struct arpcom *ac = &sc->arpcom; 531 struct ether_multi *enm; 532 struct ether_multistep step; 533 u_int32_t rxfilt; 534 int mcnt = 0; 535 536 ifp = &sc->arpcom.ac_if; 537 538 rxfilt = CSR_READ_4(sc, WB_NETCFG); 539 540 if (ac->ac_multirangecnt > 0) 541 ifp->if_flags |= IFF_ALLMULTI; 542 543 if (ifp->if_flags & IFF_ALLMULTI || ifp->if_flags & IFF_PROMISC) { 544 rxfilt |= WB_NETCFG_RX_MULTI; 545 CSR_WRITE_4(sc, WB_NETCFG, rxfilt); 546 CSR_WRITE_4(sc, WB_MAR0, 0xFFFFFFFF); 547 CSR_WRITE_4(sc, WB_MAR1, 0xFFFFFFFF); 548 return; 549 } 550 551 /* first, zot all the existing hash bits */ 552 CSR_WRITE_4(sc, WB_MAR0, 0); 553 CSR_WRITE_4(sc, WB_MAR1, 0); 554 555 /* now program new ones */ 556 ETHER_FIRST_MULTI(step, ac, enm); 557 while (enm != NULL) { 558 h = ~(ether_crc32_be(enm->enm_addrlo, ETHER_ADDR_LEN) >> 26); 559 if (h < 32) 560 hashes[0] |= (1 << h); 561 else 562 hashes[1] |= (1 << (h - 32)); 563 mcnt++; 564 ETHER_NEXT_MULTI(step, enm); 565 } 566 567 if (mcnt) 568 rxfilt |= WB_NETCFG_RX_MULTI; 569 else 570 rxfilt &= ~WB_NETCFG_RX_MULTI; 571 572 CSR_WRITE_4(sc, WB_MAR0, hashes[0]); 573 CSR_WRITE_4(sc, WB_MAR1, hashes[1]); 574 CSR_WRITE_4(sc, WB_NETCFG, rxfilt); 575 576 return; 577 } 578 579 /* 580 * The Winbond manual states that in order to fiddle with the 581 * 'full-duplex' and '100Mbps' bits in the netconfig register, we 582 * first have to put the transmit and/or receive logic in the idle state. 583 */ 584 void 585 wb_setcfg(sc, media) 586 struct wb_softc *sc; 587 u_int32_t media; 588 { 589 int i, restart = 0; 590 591 if (CSR_READ_4(sc, WB_NETCFG) & (WB_NETCFG_TX_ON|WB_NETCFG_RX_ON)) { 592 restart = 1; 593 WB_CLRBIT(sc, WB_NETCFG, (WB_NETCFG_TX_ON|WB_NETCFG_RX_ON)); 594 595 for (i = 0; i < WB_TIMEOUT; i++) { 596 DELAY(10); 597 if ((CSR_READ_4(sc, WB_ISR) & WB_ISR_TX_IDLE) && 598 (CSR_READ_4(sc, WB_ISR) & WB_ISR_RX_IDLE)) 599 break; 600 } 601 602 if (i == WB_TIMEOUT) 603 printf("%s: failed to force tx and " 604 "rx to idle state\n", sc->sc_dev.dv_xname); 605 } 606 607 if (IFM_SUBTYPE(media) == IFM_10_T) 608 WB_CLRBIT(sc, WB_NETCFG, WB_NETCFG_100MBPS); 609 else 610 WB_SETBIT(sc, WB_NETCFG, WB_NETCFG_100MBPS); 611 612 if ((media & IFM_GMASK) == IFM_FDX) 613 WB_SETBIT(sc, WB_NETCFG, WB_NETCFG_FULLDUPLEX); 614 else 615 WB_CLRBIT(sc, WB_NETCFG, WB_NETCFG_FULLDUPLEX); 616 617 if (restart) 618 WB_SETBIT(sc, WB_NETCFG, WB_NETCFG_TX_ON|WB_NETCFG_RX_ON); 619 620 return; 621 } 622 623 void 624 wb_reset(sc) 625 struct wb_softc *sc; 626 { 627 int i; 628 struct mii_data *mii = &sc->sc_mii; 629 630 CSR_WRITE_4(sc, WB_NETCFG, 0); 631 CSR_WRITE_4(sc, WB_BUSCTL, 0); 632 CSR_WRITE_4(sc, WB_TXADDR, 0); 633 CSR_WRITE_4(sc, WB_RXADDR, 0); 634 635 WB_SETBIT(sc, WB_BUSCTL, WB_BUSCTL_RESET); 636 WB_SETBIT(sc, WB_BUSCTL, WB_BUSCTL_RESET); 637 638 for (i = 0; i < WB_TIMEOUT; i++) { 639 DELAY(10); 640 if (!(CSR_READ_4(sc, WB_BUSCTL) & WB_BUSCTL_RESET)) 641 break; 642 } 643 if (i == WB_TIMEOUT) 644 printf("%s: reset never completed!\n", sc->sc_dev.dv_xname); 645 646 /* Wait a little while for the chip to get its brains in order. */ 647 DELAY(1000); 648 649 if (mii->mii_instance) { 650 struct mii_softc *miisc; 651 LIST_FOREACH(miisc, &mii->mii_phys, mii_list) 652 mii_phy_reset(miisc); 653 } 654 } 655 656 void 657 wb_fixmedia(sc) 658 struct wb_softc *sc; 659 { 660 struct mii_data *mii = &sc->sc_mii; 661 u_int32_t media; 662 663 if (LIST_FIRST(&mii->mii_phys) == NULL) 664 return; 665 666 mii_pollstat(mii); 667 if (IFM_SUBTYPE(mii->mii_media_active) == IFM_10_T) { 668 media = mii->mii_media_active & ~IFM_10_T; 669 media |= IFM_100_TX; 670 } if (IFM_SUBTYPE(mii->mii_media_active) == IFM_100_TX) { 671 media = mii->mii_media_active & ~IFM_100_TX; 672 media |= IFM_10_T; 673 } else 674 return; 675 676 ifmedia_set(&mii->mii_media, media); 677 } 678 679 const struct pci_matchid wb_devices[] = { 680 { PCI_VENDOR_WINBOND, PCI_PRODUCT_WINBOND_W89C840F }, 681 { PCI_VENDOR_COMPEX, PCI_PRODUCT_COMPEX_RL100ATX }, 682 }; 683 684 /* 685 * Probe for a Winbond chip. Check the PCI vendor and device 686 * IDs against our list and return a device name if we find a match. 687 */ 688 int 689 wb_probe(parent, match, aux) 690 struct device *parent; 691 void *match, *aux; 692 { 693 return (pci_matchbyid((struct pci_attach_args *)aux, wb_devices, 694 nitems(wb_devices))); 695 } 696 697 /* 698 * Attach the interface. Allocate softc structures, do ifmedia 699 * setup and ethernet/BPF attach. 700 */ 701 void 702 wb_attach(parent, self, aux) 703 struct device *parent, *self; 704 void *aux; 705 { 706 struct wb_softc *sc = (struct wb_softc *)self; 707 struct pci_attach_args *pa = aux; 708 pci_chipset_tag_t pc = pa->pa_pc; 709 pci_intr_handle_t ih; 710 const char *intrstr = NULL; 711 struct ifnet *ifp = &sc->arpcom.ac_if; 712 bus_size_t size; 713 int rseg; 714 bus_dma_segment_t seg; 715 bus_dmamap_t dmamap; 716 caddr_t kva; 717 718 pci_set_powerstate(pa->pa_pc, pa->pa_tag, PCI_PMCSR_STATE_D0); 719 720 /* 721 * Map control/status registers. 722 */ 723 724 #ifdef WB_USEIOSPACE 725 if (pci_mapreg_map(pa, WB_PCI_LOIO, PCI_MAPREG_TYPE_IO, 0, 726 &sc->wb_btag, &sc->wb_bhandle, NULL, &size, 0)) { 727 printf(": can't map i/o space\n"); 728 return; 729 } 730 #else 731 if (pci_mapreg_map(pa, WB_PCI_LOMEM, PCI_MAPREG_TYPE_MEM, 0, 732 &sc->wb_btag, &sc->wb_bhandle, NULL, &size, 0)){ 733 printf(": can't map mem space\n"); 734 return; 735 } 736 #endif 737 738 /* Allocate interrupt */ 739 if (pci_intr_map(pa, &ih)) { 740 printf(": couldn't map interrupt\n"); 741 goto fail_1; 742 } 743 intrstr = pci_intr_string(pc, ih); 744 sc->sc_ih = pci_intr_establish(pc, ih, IPL_NET, wb_intr, sc, 745 self->dv_xname); 746 if (sc->sc_ih == NULL) { 747 printf(": couldn't establish interrupt"); 748 if (intrstr != NULL) 749 printf(" at %s", intrstr); 750 printf("\n"); 751 goto fail_1; 752 } 753 printf(": %s", intrstr); 754 755 sc->wb_cachesize = pci_conf_read(pc, pa->pa_tag, WB_PCI_CACHELEN)&0xff; 756 757 /* Reset the adapter. */ 758 wb_reset(sc); 759 760 /* 761 * Get station address from the EEPROM. 762 */ 763 wb_read_eeprom(sc, (caddr_t)&sc->arpcom.ac_enaddr, 0, 3, 0); 764 printf(", address %s\n", ether_sprintf(sc->arpcom.ac_enaddr)); 765 766 if (bus_dmamem_alloc(pa->pa_dmat, sizeof(struct wb_list_data), 767 PAGE_SIZE, 0, &seg, 1, &rseg, BUS_DMA_NOWAIT | BUS_DMA_ZERO)) { 768 printf(": can't alloc list data\n"); 769 goto fail_2; 770 } 771 if (bus_dmamem_map(pa->pa_dmat, &seg, rseg, 772 sizeof(struct wb_list_data), &kva, BUS_DMA_NOWAIT)) { 773 printf(": can't map list data, size %zd\n", 774 sizeof(struct wb_list_data)); 775 goto fail_3; 776 } 777 if (bus_dmamap_create(pa->pa_dmat, sizeof(struct wb_list_data), 1, 778 sizeof(struct wb_list_data), 0, BUS_DMA_NOWAIT, &dmamap)) { 779 printf(": can't create dma map\n"); 780 goto fail_4; 781 } 782 if (bus_dmamap_load(pa->pa_dmat, dmamap, kva, 783 sizeof(struct wb_list_data), NULL, BUS_DMA_NOWAIT)) { 784 printf(": can't load dma map\n"); 785 goto fail_5; 786 } 787 sc->wb_ldata = (struct wb_list_data *)kva; 788 789 ifp->if_softc = sc; 790 ifp->if_flags = IFF_BROADCAST | IFF_SIMPLEX | IFF_MULTICAST; 791 ifp->if_ioctl = wb_ioctl; 792 ifp->if_start = wb_start; 793 ifp->if_watchdog = wb_watchdog; 794 IFQ_SET_MAXLEN(&ifp->if_snd, WB_TX_LIST_CNT - 1); 795 IFQ_SET_READY(&ifp->if_snd); 796 797 bcopy(sc->sc_dev.dv_xname, ifp->if_xname, IFNAMSIZ); 798 799 /* 800 * Do ifmedia setup. 801 */ 802 wb_stop(sc); 803 804 ifmedia_init(&sc->sc_mii.mii_media, 0, wb_ifmedia_upd, wb_ifmedia_sts); 805 sc->sc_mii.mii_ifp = ifp; 806 sc->sc_mii.mii_readreg = wb_miibus_readreg; 807 sc->sc_mii.mii_writereg = wb_miibus_writereg; 808 sc->sc_mii.mii_statchg = wb_miibus_statchg; 809 mii_attach(self, &sc->sc_mii, 0xffffffff, MII_PHY_ANY, MII_OFFSET_ANY, 810 0); 811 if (LIST_FIRST(&sc->sc_mii.mii_phys) == NULL) { 812 ifmedia_add(&sc->sc_mii.mii_media, IFM_ETHER|IFM_NONE,0,NULL); 813 ifmedia_set(&sc->sc_mii.mii_media, IFM_ETHER|IFM_NONE); 814 } else 815 ifmedia_set(&sc->sc_mii.mii_media, IFM_ETHER|IFM_AUTO); 816 817 /* 818 * Call MI attach routines. 819 */ 820 if_attach(ifp); 821 ether_ifattach(ifp); 822 return; 823 824 fail_5: 825 bus_dmamap_destroy(pa->pa_dmat, dmamap); 826 827 fail_4: 828 bus_dmamem_unmap(pa->pa_dmat, kva, 829 sizeof(struct wb_list_data)); 830 831 fail_3: 832 bus_dmamem_free(pa->pa_dmat, &seg, rseg); 833 834 fail_2: 835 pci_intr_disestablish(pc, sc->sc_ih); 836 837 fail_1: 838 bus_space_unmap(sc->wb_btag, sc->wb_bhandle, size); 839 } 840 841 /* 842 * Initialize the transmit descriptors. 843 */ 844 int wb_list_tx_init(sc) 845 struct wb_softc *sc; 846 { 847 struct wb_chain_data *cd; 848 struct wb_list_data *ld; 849 int i; 850 851 cd = &sc->wb_cdata; 852 ld = sc->wb_ldata; 853 854 for (i = 0; i < WB_TX_LIST_CNT; i++) { 855 cd->wb_tx_chain[i].wb_ptr = &ld->wb_tx_list[i]; 856 if (i == (WB_TX_LIST_CNT - 1)) { 857 cd->wb_tx_chain[i].wb_nextdesc = 858 &cd->wb_tx_chain[0]; 859 } else { 860 cd->wb_tx_chain[i].wb_nextdesc = 861 &cd->wb_tx_chain[i + 1]; 862 } 863 } 864 865 cd->wb_tx_free = &cd->wb_tx_chain[0]; 866 cd->wb_tx_tail = cd->wb_tx_head = NULL; 867 868 return(0); 869 } 870 871 872 /* 873 * Initialize the RX descriptors and allocate mbufs for them. Note that 874 * we arrange the descriptors in a closed ring, so that the last descriptor 875 * points back to the first. 876 */ 877 int wb_list_rx_init(sc) 878 struct wb_softc *sc; 879 { 880 struct wb_chain_data *cd; 881 struct wb_list_data *ld; 882 int i; 883 884 cd = &sc->wb_cdata; 885 ld = sc->wb_ldata; 886 887 for (i = 0; i < WB_RX_LIST_CNT; i++) { 888 cd->wb_rx_chain[i].wb_ptr = 889 (struct wb_desc *)&ld->wb_rx_list[i]; 890 cd->wb_rx_chain[i].wb_buf = (void *)&ld->wb_rxbufs[i]; 891 wb_newbuf(sc, &cd->wb_rx_chain[i]); 892 if (i == (WB_RX_LIST_CNT - 1)) { 893 cd->wb_rx_chain[i].wb_nextdesc = &cd->wb_rx_chain[0]; 894 ld->wb_rx_list[i].wb_next = 895 VTOPHYS(&ld->wb_rx_list[0]); 896 } else { 897 cd->wb_rx_chain[i].wb_nextdesc = 898 &cd->wb_rx_chain[i + 1]; 899 ld->wb_rx_list[i].wb_next = 900 VTOPHYS(&ld->wb_rx_list[i + 1]); 901 } 902 } 903 904 cd->wb_rx_head = &cd->wb_rx_chain[0]; 905 906 return(0); 907 } 908 909 /* 910 * Initialize an RX descriptor and attach an MBUF cluster. 911 */ 912 void 913 wb_newbuf(sc, c) 914 struct wb_softc *sc; 915 struct wb_chain_onefrag *c; 916 { 917 c->wb_ptr->wb_data = VTOPHYS(c->wb_buf + sizeof(u_int64_t)); 918 c->wb_ptr->wb_ctl = WB_RXCTL_RLINK | ETHER_MAX_DIX_LEN; 919 c->wb_ptr->wb_status = WB_RXSTAT; 920 } 921 922 /* 923 * A frame has been uploaded: pass the resulting mbuf chain up to 924 * the higher level protocols. 925 */ 926 void wb_rxeof(sc) 927 struct wb_softc *sc; 928 { 929 struct ifnet *ifp; 930 struct wb_chain_onefrag *cur_rx; 931 int total_len = 0; 932 u_int32_t rxstat; 933 934 ifp = &sc->arpcom.ac_if; 935 936 while(!((rxstat = sc->wb_cdata.wb_rx_head->wb_ptr->wb_status) & 937 WB_RXSTAT_OWN)) { 938 struct mbuf *m; 939 940 cur_rx = sc->wb_cdata.wb_rx_head; 941 sc->wb_cdata.wb_rx_head = cur_rx->wb_nextdesc; 942 943 if ((rxstat & WB_RXSTAT_MIIERR) || 944 (WB_RXBYTES(cur_rx->wb_ptr->wb_status) < WB_MIN_FRAMELEN) || 945 (WB_RXBYTES(cur_rx->wb_ptr->wb_status) > ETHER_MAX_DIX_LEN) || 946 !(rxstat & WB_RXSTAT_LASTFRAG) || 947 !(rxstat & WB_RXSTAT_RXCMP)) { 948 ifp->if_ierrors++; 949 wb_newbuf(sc, cur_rx); 950 printf("%s: receiver babbling: possible chip " 951 "bug, forcing reset\n", sc->sc_dev.dv_xname); 952 wb_fixmedia(sc); 953 wb_reset(sc); 954 wb_init(sc); 955 return; 956 } 957 958 if (rxstat & WB_RXSTAT_RXERR) { 959 ifp->if_ierrors++; 960 wb_newbuf(sc, cur_rx); 961 break; 962 } 963 964 /* No errors; receive the packet. */ 965 total_len = WB_RXBYTES(cur_rx->wb_ptr->wb_status); 966 967 /* 968 * XXX The Winbond chip includes the CRC with every 969 * received frame, and there's no way to turn this 970 * behavior off (at least, I can't find anything in 971 * the manual that explains how to do it) so we have 972 * to trim off the CRC manually. 973 */ 974 total_len -= ETHER_CRC_LEN; 975 976 m = m_devget(cur_rx->wb_buf + sizeof(u_int64_t), total_len, 977 ETHER_ALIGN, ifp); 978 wb_newbuf(sc, cur_rx); 979 if (m == NULL) { 980 ifp->if_ierrors++; 981 break; 982 } 983 984 ifp->if_ipackets++; 985 986 #if NBPFILTER > 0 987 /* 988 * Handle BPF listeners. Let the BPF user see the packet. 989 */ 990 if (ifp->if_bpf) 991 bpf_mtap(ifp->if_bpf, m, BPF_DIRECTION_IN); 992 #endif 993 /* pass it on. */ 994 ether_input_mbuf(ifp, m); 995 } 996 997 return; 998 } 999 1000 void wb_rxeoc(sc) 1001 struct wb_softc *sc; 1002 { 1003 wb_rxeof(sc); 1004 1005 WB_CLRBIT(sc, WB_NETCFG, WB_NETCFG_RX_ON); 1006 CSR_WRITE_4(sc, WB_RXADDR, VTOPHYS(&sc->wb_ldata->wb_rx_list[0])); 1007 WB_SETBIT(sc, WB_NETCFG, WB_NETCFG_RX_ON); 1008 if (CSR_READ_4(sc, WB_ISR) & WB_RXSTATE_SUSPEND) 1009 CSR_WRITE_4(sc, WB_RXSTART, 0xFFFFFFFF); 1010 1011 return; 1012 } 1013 1014 /* 1015 * A frame was downloaded to the chip. It's safe for us to clean up 1016 * the list buffers. 1017 */ 1018 void wb_txeof(sc) 1019 struct wb_softc *sc; 1020 { 1021 struct wb_chain *cur_tx; 1022 struct ifnet *ifp; 1023 1024 ifp = &sc->arpcom.ac_if; 1025 1026 /* Clear the timeout timer. */ 1027 ifp->if_timer = 0; 1028 1029 if (sc->wb_cdata.wb_tx_head == NULL) 1030 return; 1031 1032 /* 1033 * Go through our tx list and free mbufs for those 1034 * frames that have been transmitted. 1035 */ 1036 while(sc->wb_cdata.wb_tx_head->wb_mbuf != NULL) { 1037 u_int32_t txstat; 1038 1039 cur_tx = sc->wb_cdata.wb_tx_head; 1040 txstat = WB_TXSTATUS(cur_tx); 1041 1042 if ((txstat & WB_TXSTAT_OWN) || txstat == WB_UNSENT) 1043 break; 1044 1045 if (txstat & WB_TXSTAT_TXERR) { 1046 ifp->if_oerrors++; 1047 if (txstat & WB_TXSTAT_ABORT) 1048 ifp->if_collisions++; 1049 if (txstat & WB_TXSTAT_LATECOLL) 1050 ifp->if_collisions++; 1051 } 1052 1053 ifp->if_collisions += (txstat & WB_TXSTAT_COLLCNT) >> 3; 1054 1055 ifp->if_opackets++; 1056 m_freem(cur_tx->wb_mbuf); 1057 cur_tx->wb_mbuf = NULL; 1058 1059 if (sc->wb_cdata.wb_tx_head == sc->wb_cdata.wb_tx_tail) { 1060 sc->wb_cdata.wb_tx_head = NULL; 1061 sc->wb_cdata.wb_tx_tail = NULL; 1062 break; 1063 } 1064 1065 sc->wb_cdata.wb_tx_head = cur_tx->wb_nextdesc; 1066 } 1067 1068 return; 1069 } 1070 1071 /* 1072 * TX 'end of channel' interrupt handler. 1073 */ 1074 void wb_txeoc(sc) 1075 struct wb_softc *sc; 1076 { 1077 struct ifnet *ifp; 1078 1079 ifp = &sc->arpcom.ac_if; 1080 1081 ifp->if_timer = 0; 1082 1083 if (sc->wb_cdata.wb_tx_head == NULL) { 1084 ifp->if_flags &= ~IFF_OACTIVE; 1085 sc->wb_cdata.wb_tx_tail = NULL; 1086 } else { 1087 if (WB_TXOWN(sc->wb_cdata.wb_tx_head) == WB_UNSENT) { 1088 WB_TXOWN(sc->wb_cdata.wb_tx_head) = WB_TXSTAT_OWN; 1089 ifp->if_timer = 5; 1090 CSR_WRITE_4(sc, WB_TXSTART, 0xFFFFFFFF); 1091 } 1092 } 1093 1094 return; 1095 } 1096 1097 int wb_intr(arg) 1098 void *arg; 1099 { 1100 struct wb_softc *sc; 1101 struct ifnet *ifp; 1102 u_int32_t status; 1103 int r = 0; 1104 1105 sc = arg; 1106 ifp = &sc->arpcom.ac_if; 1107 1108 if (!(ifp->if_flags & IFF_UP)) 1109 return (r); 1110 1111 /* Disable interrupts. */ 1112 CSR_WRITE_4(sc, WB_IMR, 0x00000000); 1113 1114 for (;;) { 1115 1116 status = CSR_READ_4(sc, WB_ISR); 1117 if (status) 1118 CSR_WRITE_4(sc, WB_ISR, status); 1119 1120 if ((status & WB_INTRS) == 0) 1121 break; 1122 1123 r = 1; 1124 1125 if ((status & WB_ISR_RX_NOBUF) || (status & WB_ISR_RX_ERR)) { 1126 ifp->if_ierrors++; 1127 wb_reset(sc); 1128 if (status & WB_ISR_RX_ERR) 1129 wb_fixmedia(sc); 1130 wb_init(sc); 1131 continue; 1132 } 1133 1134 if (status & WB_ISR_RX_OK) 1135 wb_rxeof(sc); 1136 1137 if (status & WB_ISR_RX_IDLE) 1138 wb_rxeoc(sc); 1139 1140 if (status & WB_ISR_TX_OK) 1141 wb_txeof(sc); 1142 1143 if (status & WB_ISR_TX_NOBUF) 1144 wb_txeoc(sc); 1145 1146 if (status & WB_ISR_TX_IDLE) { 1147 wb_txeof(sc); 1148 if (sc->wb_cdata.wb_tx_head != NULL) { 1149 WB_SETBIT(sc, WB_NETCFG, WB_NETCFG_TX_ON); 1150 CSR_WRITE_4(sc, WB_TXSTART, 0xFFFFFFFF); 1151 } 1152 } 1153 1154 if (status & WB_ISR_TX_UNDERRUN) { 1155 ifp->if_oerrors++; 1156 wb_txeof(sc); 1157 WB_CLRBIT(sc, WB_NETCFG, WB_NETCFG_TX_ON); 1158 /* Jack up TX threshold */ 1159 sc->wb_txthresh += WB_TXTHRESH_CHUNK; 1160 WB_CLRBIT(sc, WB_NETCFG, WB_NETCFG_TX_THRESH); 1161 WB_SETBIT(sc, WB_NETCFG, WB_TXTHRESH(sc->wb_txthresh)); 1162 WB_SETBIT(sc, WB_NETCFG, WB_NETCFG_TX_ON); 1163 } 1164 1165 if (status & WB_ISR_BUS_ERR) { 1166 wb_reset(sc); 1167 wb_init(sc); 1168 } 1169 1170 } 1171 1172 /* Re-enable interrupts. */ 1173 CSR_WRITE_4(sc, WB_IMR, WB_INTRS); 1174 1175 if (!IFQ_IS_EMPTY(&ifp->if_snd)) { 1176 wb_start(ifp); 1177 } 1178 1179 return (r); 1180 } 1181 1182 void 1183 wb_tick(xsc) 1184 void *xsc; 1185 { 1186 struct wb_softc *sc = xsc; 1187 int s; 1188 1189 s = splnet(); 1190 mii_tick(&sc->sc_mii); 1191 splx(s); 1192 timeout_add_sec(&sc->wb_tick_tmo, 1); 1193 } 1194 1195 /* 1196 * Encapsulate an mbuf chain in a descriptor by coupling the mbuf data 1197 * pointers to the fragment pointers. 1198 */ 1199 int wb_encap(sc, c, m_head) 1200 struct wb_softc *sc; 1201 struct wb_chain *c; 1202 struct mbuf *m_head; 1203 { 1204 int frag = 0; 1205 struct wb_desc *f = NULL; 1206 int total_len; 1207 struct mbuf *m; 1208 1209 /* 1210 * Start packing the mbufs in this chain into 1211 * the fragment pointers. Stop when we run out 1212 * of fragments or hit the end of the mbuf chain. 1213 */ 1214 m = m_head; 1215 total_len = 0; 1216 1217 for (m = m_head, frag = 0; m != NULL; m = m->m_next) { 1218 if (m->m_len != 0) { 1219 if (frag == WB_MAXFRAGS) 1220 break; 1221 total_len += m->m_len; 1222 f = &c->wb_ptr->wb_frag[frag]; 1223 f->wb_ctl = WB_TXCTL_TLINK | m->m_len; 1224 if (frag == 0) { 1225 f->wb_ctl |= WB_TXCTL_FIRSTFRAG; 1226 f->wb_status = 0; 1227 } else 1228 f->wb_status = WB_TXSTAT_OWN; 1229 f->wb_next = VTOPHYS(&c->wb_ptr->wb_frag[frag + 1]); 1230 f->wb_data = VTOPHYS(mtod(m, vaddr_t)); 1231 frag++; 1232 } 1233 } 1234 1235 /* 1236 * Handle special case: we used up all 16 fragments, 1237 * but we have more mbufs left in the chain. Copy the 1238 * data into an mbuf cluster. Note that we don't 1239 * bother clearing the values in the other fragment 1240 * pointers/counters; it wouldn't gain us anything, 1241 * and would waste cycles. 1242 */ 1243 if (m != NULL) { 1244 struct mbuf *m_new = NULL; 1245 1246 MGETHDR(m_new, M_DONTWAIT, MT_DATA); 1247 if (m_new == NULL) 1248 return(1); 1249 if (m_head->m_pkthdr.len > MHLEN) { 1250 MCLGET(m_new, M_DONTWAIT); 1251 if (!(m_new->m_flags & M_EXT)) { 1252 m_freem(m_new); 1253 return(1); 1254 } 1255 } 1256 m_copydata(m_head, 0, m_head->m_pkthdr.len, 1257 mtod(m_new, caddr_t)); 1258 m_new->m_pkthdr.len = m_new->m_len = m_head->m_pkthdr.len; 1259 m_freem(m_head); 1260 m_head = m_new; 1261 f = &c->wb_ptr->wb_frag[0]; 1262 f->wb_status = 0; 1263 f->wb_data = VTOPHYS(mtod(m_new, caddr_t)); 1264 f->wb_ctl = total_len = m_new->m_len; 1265 f->wb_ctl |= WB_TXCTL_TLINK|WB_TXCTL_FIRSTFRAG; 1266 frag = 1; 1267 } 1268 1269 if (total_len < WB_MIN_FRAMELEN) { 1270 f = &c->wb_ptr->wb_frag[frag]; 1271 f->wb_ctl = WB_MIN_FRAMELEN - total_len; 1272 f->wb_data = VTOPHYS(&sc->wb_cdata.wb_pad); 1273 f->wb_ctl |= WB_TXCTL_TLINK; 1274 f->wb_status = WB_TXSTAT_OWN; 1275 frag++; 1276 } 1277 1278 c->wb_mbuf = m_head; 1279 c->wb_lastdesc = frag - 1; 1280 WB_TXCTL(c) |= WB_TXCTL_LASTFRAG; 1281 WB_TXNEXT(c) = VTOPHYS(&c->wb_nextdesc->wb_ptr->wb_frag[0]); 1282 1283 return(0); 1284 } 1285 1286 /* 1287 * Main transmit routine. To avoid having to do mbuf copies, we put pointers 1288 * to the mbuf data regions directly in the transmit lists. We also save a 1289 * copy of the pointers since the transmit list fragment pointers are 1290 * physical addresses. 1291 */ 1292 1293 void wb_start(ifp) 1294 struct ifnet *ifp; 1295 { 1296 struct wb_softc *sc; 1297 struct mbuf *m_head = NULL; 1298 struct wb_chain *cur_tx = NULL, *start_tx; 1299 1300 sc = ifp->if_softc; 1301 1302 /* 1303 * Check for an available queue slot. If there are none, 1304 * punt. 1305 */ 1306 if (sc->wb_cdata.wb_tx_free->wb_mbuf != NULL) { 1307 ifp->if_flags |= IFF_OACTIVE; 1308 return; 1309 } 1310 1311 start_tx = sc->wb_cdata.wb_tx_free; 1312 1313 while(sc->wb_cdata.wb_tx_free->wb_mbuf == NULL) { 1314 IFQ_DEQUEUE(&ifp->if_snd, m_head); 1315 if (m_head == NULL) 1316 break; 1317 1318 /* Pick a descriptor off the free list. */ 1319 cur_tx = sc->wb_cdata.wb_tx_free; 1320 sc->wb_cdata.wb_tx_free = cur_tx->wb_nextdesc; 1321 1322 /* Pack the data into the descriptor. */ 1323 wb_encap(sc, cur_tx, m_head); 1324 1325 if (cur_tx != start_tx) 1326 WB_TXOWN(cur_tx) = WB_TXSTAT_OWN; 1327 1328 #if NBPFILTER > 0 1329 /* 1330 * If there's a BPF listener, bounce a copy of this frame 1331 * to him. 1332 */ 1333 if (ifp->if_bpf) 1334 bpf_mtap(ifp->if_bpf, cur_tx->wb_mbuf, 1335 BPF_DIRECTION_OUT); 1336 #endif 1337 } 1338 1339 /* 1340 * If there are no packets queued, bail. 1341 */ 1342 if (cur_tx == NULL) 1343 return; 1344 1345 /* 1346 * Place the request for the upload interrupt 1347 * in the last descriptor in the chain. This way, if 1348 * we're chaining several packets at once, we'll only 1349 * get an interrupt once for the whole chain rather than 1350 * once for each packet. 1351 */ 1352 WB_TXCTL(cur_tx) |= WB_TXCTL_FINT; 1353 cur_tx->wb_ptr->wb_frag[0].wb_ctl |= WB_TXCTL_FINT; 1354 sc->wb_cdata.wb_tx_tail = cur_tx; 1355 1356 if (sc->wb_cdata.wb_tx_head == NULL) { 1357 sc->wb_cdata.wb_tx_head = start_tx; 1358 WB_TXOWN(start_tx) = WB_TXSTAT_OWN; 1359 CSR_WRITE_4(sc, WB_TXSTART, 0xFFFFFFFF); 1360 } else { 1361 /* 1362 * We need to distinguish between the case where 1363 * the own bit is clear because the chip cleared it 1364 * and where the own bit is clear because we haven't 1365 * set it yet. The magic value WB_UNSET is just some 1366 * ramdomly chosen number which doesn't have the own 1367 * bit set. When we actually transmit the frame, the 1368 * status word will have _only_ the own bit set, so 1369 * the txeoc handler will be able to tell if it needs 1370 * to initiate another transmission to flush out pending 1371 * frames. 1372 */ 1373 WB_TXOWN(start_tx) = WB_UNSENT; 1374 } 1375 1376 /* 1377 * Set a timeout in case the chip goes out to lunch. 1378 */ 1379 ifp->if_timer = 5; 1380 1381 return; 1382 } 1383 1384 void wb_init(xsc) 1385 void *xsc; 1386 { 1387 struct wb_softc *sc = xsc; 1388 struct ifnet *ifp = &sc->arpcom.ac_if; 1389 int s, i; 1390 1391 s = splnet(); 1392 1393 /* 1394 * Cancel pending I/O and free all RX/TX buffers. 1395 */ 1396 wb_stop(sc); 1397 wb_reset(sc); 1398 1399 sc->wb_txthresh = WB_TXTHRESH_INIT; 1400 1401 /* 1402 * Set cache alignment and burst length. 1403 */ 1404 #ifdef foo 1405 CSR_WRITE_4(sc, WB_BUSCTL, WB_BUSCTL_CONFIG); 1406 WB_CLRBIT(sc, WB_NETCFG, WB_NETCFG_TX_THRESH); 1407 WB_SETBIT(sc, WB_NETCFG, WB_TXTHRESH(sc->wb_txthresh)); 1408 #endif 1409 1410 CSR_WRITE_4(sc, WB_BUSCTL, WB_BUSCTL_MUSTBEONE|WB_BUSCTL_ARBITRATION); 1411 WB_SETBIT(sc, WB_BUSCTL, WB_BURSTLEN_16LONG); 1412 switch(sc->wb_cachesize) { 1413 case 32: 1414 WB_SETBIT(sc, WB_BUSCTL, WB_CACHEALIGN_32LONG); 1415 break; 1416 case 16: 1417 WB_SETBIT(sc, WB_BUSCTL, WB_CACHEALIGN_16LONG); 1418 break; 1419 case 8: 1420 WB_SETBIT(sc, WB_BUSCTL, WB_CACHEALIGN_8LONG); 1421 break; 1422 case 0: 1423 default: 1424 WB_SETBIT(sc, WB_BUSCTL, WB_CACHEALIGN_NONE); 1425 break; 1426 } 1427 1428 /* This doesn't tend to work too well at 100Mbps. */ 1429 WB_CLRBIT(sc, WB_NETCFG, WB_NETCFG_TX_EARLY_ON); 1430 1431 /* Init our MAC address */ 1432 for (i = 0; i < ETHER_ADDR_LEN; i++) { 1433 CSR_WRITE_1(sc, WB_NODE0 + i, sc->arpcom.ac_enaddr[i]); 1434 } 1435 1436 /* Init circular RX list. */ 1437 if (wb_list_rx_init(sc) == ENOBUFS) { 1438 printf("%s: initialization failed: no " 1439 "memory for rx buffers\n", sc->sc_dev.dv_xname); 1440 wb_stop(sc); 1441 splx(s); 1442 return; 1443 } 1444 1445 /* Init TX descriptors. */ 1446 wb_list_tx_init(sc); 1447 1448 /* If we want promiscuous mode, set the allframes bit. */ 1449 if (ifp->if_flags & IFF_PROMISC) { 1450 WB_SETBIT(sc, WB_NETCFG, WB_NETCFG_RX_ALLPHYS); 1451 } else { 1452 WB_CLRBIT(sc, WB_NETCFG, WB_NETCFG_RX_ALLPHYS); 1453 } 1454 1455 /* 1456 * Set capture broadcast bit to capture broadcast frames. 1457 */ 1458 if (ifp->if_flags & IFF_BROADCAST) { 1459 WB_SETBIT(sc, WB_NETCFG, WB_NETCFG_RX_BROAD); 1460 } else { 1461 WB_CLRBIT(sc, WB_NETCFG, WB_NETCFG_RX_BROAD); 1462 } 1463 1464 /* 1465 * Program the multicast filter, if necessary. 1466 */ 1467 wb_setmulti(sc); 1468 1469 /* 1470 * Load the address of the RX list. 1471 */ 1472 WB_CLRBIT(sc, WB_NETCFG, WB_NETCFG_RX_ON); 1473 CSR_WRITE_4(sc, WB_RXADDR, VTOPHYS(&sc->wb_ldata->wb_rx_list[0])); 1474 1475 /* 1476 * Enable interrupts. 1477 */ 1478 CSR_WRITE_4(sc, WB_IMR, WB_INTRS); 1479 CSR_WRITE_4(sc, WB_ISR, 0xFFFFFFFF); 1480 1481 /* Enable receiver and transmitter. */ 1482 WB_SETBIT(sc, WB_NETCFG, WB_NETCFG_RX_ON); 1483 CSR_WRITE_4(sc, WB_RXSTART, 0xFFFFFFFF); 1484 1485 WB_CLRBIT(sc, WB_NETCFG, WB_NETCFG_TX_ON); 1486 CSR_WRITE_4(sc, WB_TXADDR, VTOPHYS(&sc->wb_ldata->wb_tx_list[0])); 1487 WB_SETBIT(sc, WB_NETCFG, WB_NETCFG_TX_ON); 1488 1489 ifp->if_flags |= IFF_RUNNING; 1490 ifp->if_flags &= ~IFF_OACTIVE; 1491 1492 splx(s); 1493 1494 timeout_set(&sc->wb_tick_tmo, wb_tick, sc); 1495 timeout_add_sec(&sc->wb_tick_tmo, 1); 1496 1497 return; 1498 } 1499 1500 /* 1501 * Set media options. 1502 */ 1503 int 1504 wb_ifmedia_upd(ifp) 1505 struct ifnet *ifp; 1506 { 1507 struct wb_softc *sc = ifp->if_softc; 1508 1509 if (ifp->if_flags & IFF_UP) 1510 wb_init(sc); 1511 1512 return(0); 1513 } 1514 1515 /* 1516 * Report current media status. 1517 */ 1518 void 1519 wb_ifmedia_sts(ifp, ifmr) 1520 struct ifnet *ifp; 1521 struct ifmediareq *ifmr; 1522 { 1523 struct wb_softc *sc = ifp->if_softc; 1524 struct mii_data *mii = &sc->sc_mii; 1525 1526 mii_pollstat(mii); 1527 ifmr->ifm_active = mii->mii_media_active; 1528 ifmr->ifm_status = mii->mii_media_status; 1529 } 1530 1531 int wb_ioctl(ifp, command, data) 1532 struct ifnet *ifp; 1533 u_long command; 1534 caddr_t data; 1535 { 1536 struct wb_softc *sc = ifp->if_softc; 1537 struct ifaddr *ifa = (struct ifaddr *) data; 1538 struct ifreq *ifr = (struct ifreq *) data; 1539 int s, error = 0; 1540 1541 s = splnet(); 1542 1543 switch(command) { 1544 case SIOCSIFADDR: 1545 ifp->if_flags |= IFF_UP; 1546 switch (ifa->ifa_addr->sa_family) { 1547 #ifdef INET 1548 case AF_INET: 1549 wb_init(sc); 1550 arp_ifinit(&sc->arpcom, ifa); 1551 break; 1552 #endif /* INET */ 1553 default: 1554 wb_init(sc); 1555 } 1556 break; 1557 1558 case SIOCSIFFLAGS: 1559 if (ifp->if_flags & IFF_UP) { 1560 wb_init(sc); 1561 } else { 1562 if (ifp->if_flags & IFF_RUNNING) 1563 wb_stop(sc); 1564 } 1565 error = 0; 1566 break; 1567 1568 case SIOCGIFMEDIA: 1569 case SIOCSIFMEDIA: 1570 error = ifmedia_ioctl(ifp, ifr, &sc->sc_mii.mii_media, command); 1571 break; 1572 1573 default: 1574 error = ether_ioctl(ifp, &sc->arpcom, command, data); 1575 } 1576 1577 if (error == ENETRESET) { 1578 if (ifp->if_flags & IFF_RUNNING) 1579 wb_setmulti(sc); 1580 error = 0; 1581 } 1582 1583 splx(s); 1584 return(error); 1585 } 1586 1587 void wb_watchdog(ifp) 1588 struct ifnet *ifp; 1589 { 1590 struct wb_softc *sc; 1591 1592 sc = ifp->if_softc; 1593 1594 ifp->if_oerrors++; 1595 printf("%s: watchdog timeout\n", sc->sc_dev.dv_xname); 1596 1597 #ifdef foo 1598 if (!(wb_phy_readreg(sc, PHY_BMSR) & PHY_BMSR_LINKSTAT)) 1599 printf("%s: no carrier - transceiver cable problem?\n", 1600 sc->sc_dev.dv_xname); 1601 #endif 1602 wb_stop(sc); 1603 wb_reset(sc); 1604 wb_init(sc); 1605 1606 if (!IFQ_IS_EMPTY(&ifp->if_snd)) 1607 wb_start(ifp); 1608 1609 return; 1610 } 1611 1612 /* 1613 * Stop the adapter and free any mbufs allocated to the 1614 * RX and TX lists. 1615 */ 1616 void wb_stop(sc) 1617 struct wb_softc *sc; 1618 { 1619 int i; 1620 struct ifnet *ifp; 1621 1622 ifp = &sc->arpcom.ac_if; 1623 ifp->if_timer = 0; 1624 1625 timeout_del(&sc->wb_tick_tmo); 1626 1627 ifp->if_flags &= ~(IFF_RUNNING | IFF_OACTIVE); 1628 1629 WB_CLRBIT(sc, WB_NETCFG, (WB_NETCFG_RX_ON|WB_NETCFG_TX_ON)); 1630 CSR_WRITE_4(sc, WB_IMR, 0x00000000); 1631 CSR_WRITE_4(sc, WB_TXADDR, 0x00000000); 1632 CSR_WRITE_4(sc, WB_RXADDR, 0x00000000); 1633 1634 /* 1635 * Free data in the RX lists. 1636 */ 1637 bzero(&sc->wb_ldata->wb_rx_list, sizeof(sc->wb_ldata->wb_rx_list)); 1638 1639 /* 1640 * Free the TX list buffers. 1641 */ 1642 for (i = 0; i < WB_TX_LIST_CNT; i++) { 1643 if (sc->wb_cdata.wb_tx_chain[i].wb_mbuf != NULL) { 1644 m_freem(sc->wb_cdata.wb_tx_chain[i].wb_mbuf); 1645 sc->wb_cdata.wb_tx_chain[i].wb_mbuf = NULL; 1646 } 1647 } 1648 1649 bzero(&sc->wb_ldata->wb_tx_list, sizeof(sc->wb_ldata->wb_tx_list)); 1650 } 1651 1652 struct cfattach wb_ca = { 1653 sizeof(struct wb_softc), wb_probe, wb_attach 1654 }; 1655 1656 struct cfdriver wb_cd = { 1657 NULL, "wb", DV_IFNET 1658 }; 1659