1 /* $OpenBSD: if_vrreg.h,v 1.5 2001/05/16 13:41:27 aaron Exp $ */ 2 3 /* 4 * Copyright (c) 1997, 1998 5 * Bill Paul <wpaul@ctr.columbia.edu>. All rights reserved. 6 * 7 * Redistribution and use in source and binary forms, with or without 8 * modification, are permitted provided that the following conditions 9 * are met: 10 * 1. Redistributions of source code must retain the above copyright 11 * notice, this list of conditions and the following disclaimer. 12 * 2. Redistributions in binary form must reproduce the above copyright 13 * notice, this list of conditions and the following disclaimer in the 14 * documentation and/or other materials provided with the distribution. 15 * 3. All advertising materials mentioning features or use of this software 16 * must display the following acknowledgement: 17 * This product includes software developed by Bill Paul. 18 * 4. Neither the name of the author nor the names of any co-contributors 19 * may be used to endorse or promote products derived from this software 20 * without specific prior written permission. 21 * 22 * THIS SOFTWARE IS PROVIDED BY Bill Paul AND CONTRIBUTORS ``AS IS'' AND 23 * ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE 24 * IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE 25 * ARE DISCLAIMED. IN NO EVENT SHALL Bill Paul OR THE VOICES IN HIS HEAD 26 * BE LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR 27 * CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF 28 * SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS 29 * INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN 30 * CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) 31 * ARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF 32 * THE POSSIBILITY OF SUCH DAMAGE. 33 * 34 * $FreeBSD: src/sys/pci/if_vrreg.h,v 1.10 2001/02/09 06:11:21 bmilekic Exp $ 35 */ 36 37 /* 38 * Rhine register definitions. 39 */ 40 41 #define VR_PAR0 0x00 /* node address 0 to 4 */ 42 #define VR_PAR1 0x04 /* node address 2 to 6 */ 43 #define VR_RXCFG 0x06 /* receiver config register */ 44 #define VR_TXCFG 0x07 /* transmit config register */ 45 #define VR_COMMAND 0x08 /* command register */ 46 #define VR_ISR 0x0C /* interrupt/status register */ 47 #define VR_IMR 0x0E /* interrupt mask register */ 48 #define VR_MAR0 0x10 /* multicast hash 0 */ 49 #define VR_MAR1 0x14 /* multicast hash 1 */ 50 #define VR_RXADDR 0x18 /* rx descriptor list start addr */ 51 #define VR_TXADDR 0x1C /* tx descriptor list start addr */ 52 #define VR_CURRXDESC0 0x20 53 #define VR_CURRXDESC1 0x24 54 #define VR_CURRXDESC2 0x28 55 #define VR_CURRXDESC3 0x2C 56 #define VR_NEXTRXDESC0 0x30 57 #define VR_NEXTRXDESC1 0x34 58 #define VR_NEXTRXDESC2 0x38 59 #define VR_NEXTRXDESC3 0x3C 60 #define VR_CURTXDESC0 0x40 61 #define VR_CURTXDESC1 0x44 62 #define VR_CURTXDESC2 0x48 63 #define VR_CURTXDESC3 0x4C 64 #define VR_NEXTTXDESC0 0x50 65 #define VR_NEXTTXDESC1 0x54 66 #define VR_NEXTTXDESC2 0x58 67 #define VR_NEXTTXDESC3 0x5C 68 #define VR_CURRXDMA 0x60 /* current RX DMA address */ 69 #define VR_CURTXDMA 0x64 /* current TX DMA address */ 70 #define VR_TALLYCNT 0x68 /* tally counter test register */ 71 #define VR_PHYADDR 0x6C 72 #define VR_MIISTAT 0x6D 73 #define VR_BCR0 0x6E 74 #define VR_BCR1 0x6F 75 #define VR_MIICMD 0x70 76 #define VR_MIIADDR 0x71 77 #define VR_MIIDATA 0x72 78 #define VR_EECSR 0x74 79 #define VR_TEST 0x75 80 #define VR_GPIO 0x76 81 #define VR_CONFIG 0x78 82 #define VR_MPA_CNT 0x7C 83 #define VR_CRC_CNT 0x7E 84 #define VR_STICKHW 0x83 85 86 /* 87 * RX config bits. 88 */ 89 #define VR_RXCFG_RX_ERRPKTS 0x01 90 #define VR_RXCFG_RX_RUNT 0x02 91 #define VR_RXCFG_RX_MULTI 0x04 92 #define VR_RXCFG_RX_BROAD 0x08 93 #define VR_RXCFG_RX_PROMISC 0x10 94 #define VR_RXCFG_RX_THRESH 0xE0 95 96 #define VR_RXTHRESH_32BYTES 0x00 97 #define VR_RXTHRESH_64BYTES 0x20 98 #define VR_RXTHRESH_128BYTES 0x40 99 #define VR_RXTHRESH_256BYTES 0x60 100 #define VR_RXTHRESH_512BYTES 0x80 101 #define VR_RXTHRESH_768BYTES 0xA0 102 #define VR_RXTHRESH_1024BYTES 0xC0 103 #define VR_RXTHRESH_STORENFWD 0xE0 104 105 /* 106 * TX config bits. 107 */ 108 #define VR_TXCFG_RSVD0 0x01 109 #define VR_TXCFG_LOOPBKMODE 0x06 110 #define VR_TXCFG_BACKOFF 0x08 111 #define VR_TXCFG_RSVD1 0x10 112 #define VR_TXCFG_TX_THRESH 0xE0 113 114 #define VR_TXTHRESH_32BYTES 0x00 115 #define VR_TXTHRESH_64BYTES 0x20 116 #define VR_TXTHRESH_128BYTES 0x40 117 #define VR_TXTHRESH_256BYTES 0x60 118 #define VR_TXTHRESH_512BYTES 0x80 119 #define VR_TXTHRESH_768BYTES 0xA0 120 #define VR_TXTHRESH_1024BYTES 0xC0 121 #define VR_TXTHRESH_STORENFWD 0xE0 122 123 /* 124 * Command register bits. 125 */ 126 #define VR_CMD_INIT 0x0001 127 #define VR_CMD_START 0x0002 128 #define VR_CMD_STOP 0x0004 129 #define VR_CMD_RX_ON 0x0008 130 #define VR_CMD_TX_ON 0x0010 131 #define VR_CMD_TX_GO 0x0020 132 #define VR_CMD_RX_GO 0x0040 133 #define VR_CMD_RSVD 0x0080 134 #define VR_CMD_RX_EARLY 0x0100 135 #define VR_CMD_TX_EARLY 0x0200 136 #define VR_CMD_FULLDUPLEX 0x0400 137 #define VR_CMD_TX_NOPOLL 0x0800 138 139 #define VR_CMD_RESET 0x8000 140 141 /* 142 * Interrupt status bits. 143 */ 144 #define VR_ISR_RX_OK 0x0001 /* packet rx ok */ 145 #define VR_ISR_TX_OK 0x0002 /* packet tx ok */ 146 #define VR_ISR_RX_ERR 0x0004 /* packet rx with err */ 147 #define VR_ISR_TX_ABRT 0x0008 /* tx aborted due to excess colls */ 148 #define VR_ISR_TX_UNDERRUN 0x0010 /* tx buffer underflow */ 149 #define VR_ISR_RX_NOBUF 0x0020 /* no rx buffer available */ 150 #define VR_ISR_BUSERR 0x0040 /* PCI bus error */ 151 #define VR_ISR_STATSOFLOW 0x0080 /* stats counter oflow */ 152 #define VR_ISR_RX_EARLY 0x0100 /* rx early */ 153 #define VR_ISR_LINKSTAT 0x0200 /* MII status change */ 154 #define VR_ISR_RX_OFLOW 0x0400 /* rx FIFO overflow */ 155 #define VR_ISR_RX_DROPPED 0x0800 156 #define VR_ISR_RX_NOBUF2 0x1000 157 #define VR_ISR_TX_ABRT2 0x2000 158 #define VR_ISR_LINKSTAT2 0x4000 159 #define VR_ISR_MAGICPACKET 0x8000 160 161 /* 162 * Interrupt mask bits. 163 */ 164 #define VR_IMR_RX_OK 0x0001 /* packet rx ok */ 165 #define VR_IMR_TX_OK 0x0002 /* packet tx ok */ 166 #define VR_IMR_RX_ERR 0x0004 /* packet rx with err */ 167 #define VR_IMR_TX_ABRT 0x0008 /* tx aborted due to excess colls */ 168 #define VR_IMR_TX_UNDERRUN 0x0010 /* tx buffer underflow */ 169 #define VR_IMR_RX_NOBUF 0x0020 /* no rx buffer available */ 170 #define VR_IMR_BUSERR 0x0040 /* PCI bus error */ 171 #define VR_IMR_STATSOFLOW 0x0080 /* stats counter oflow */ 172 #define VR_IMR_RX_EARLY 0x0100 /* rx early */ 173 #define VR_IMR_LINKSTAT 0x0200 /* MII status change */ 174 #define VR_IMR_RX_OFLOW 0x0400 /* rx FIFO overflow */ 175 #define VR_IMR_RX_DROPPED 0x0800 176 #define VR_IMR_RX_NOBUF2 0x1000 177 #define VR_IMR_TX_ABRT2 0x2000 178 #define VR_IMR_LINKSTAT2 0x4000 179 #define VR_IMR_MAGICPACKET 0x8000 180 181 #define VR_INTRS \ 182 (VR_IMR_RX_OK|VR_IMR_TX_OK|VR_IMR_RX_NOBUF| \ 183 VR_IMR_TX_ABRT|VR_IMR_TX_UNDERRUN|VR_IMR_BUSERR| \ 184 VR_IMR_RX_ERR|VR_ISR_RX_DROPPED) 185 186 /* 187 * MII status register. 188 */ 189 190 #define VR_MIISTAT_SPEED 0x01 191 #define VR_MIISTAT_LINKFAULT 0x02 192 #define VR_MIISTAT_MGTREADERR 0x04 193 #define VR_MIISTAT_MIIERR 0x08 194 #define VR_MIISTAT_PHYOPT 0x10 195 #define VR_MIISTAT_MDC_SPEED 0x20 196 #define VR_MIISTAT_RSVD 0x40 197 #define VR_MIISTAT_GPIO1POLL 0x80 198 199 /* 200 * MII command register bits. 201 */ 202 #define VR_MIICMD_CLK 0x01 203 #define VR_MIICMD_DATAOUT 0x02 204 #define VR_MIICMD_DATAIN 0x04 205 #define VR_MIICMD_DIR 0x08 206 #define VR_MIICMD_DIRECTPGM 0x10 207 #define VR_MIICMD_WRITE_ENB 0x20 208 #define VR_MIICMD_READ_ENB 0x40 209 #define VR_MIICMD_AUTOPOLL 0x80 210 211 /* 212 * EEPROM control bits. 213 */ 214 #define VR_EECSR_DATAIN 0x01 /* data out */ 215 #define VR_EECSR_DATAOUT 0x02 /* data in */ 216 #define VR_EECSR_CLK 0x04 /* clock */ 217 #define VR_EECSR_CS 0x08 /* chip select */ 218 #define VR_EECSR_DPM 0x10 219 #define VR_EECSR_LOAD 0x20 220 #define VR_EECSR_EMBP 0x40 221 #define VR_EECSR_EEPR 0x80 222 223 #define VR_EECMD_WRITE 0x140 224 #define VR_EECMD_READ 0x180 225 #define VR_EECMD_ERASE 0x1c0 226 227 /* 228 * Test register bits. 229 */ 230 #define VR_TEST_TEST0 0x01 231 #define VR_TEST_TEST1 0x02 232 #define VR_TEST_TEST2 0x04 233 #define VR_TEST_TSTUD 0x08 234 #define VR_TEST_TSTOV 0x10 235 #define VR_TEST_BKOFF 0x20 236 #define VR_TEST_FCOL 0x40 237 #define VR_TEST_HBDES 0x80 238 239 /* 240 * Config register bits. 241 */ 242 #define VR_CFG_GPIO2OUTENB 0x00000001 243 #define VR_CFG_GPIO2OUT 0x00000002 /* gen. purp. pin */ 244 #define VR_CFG_GPIO2IN 0x00000004 /* gen. purp. pin */ 245 #define VR_CFG_AUTOOPT 0x00000008 /* enable rx/tx autopoll */ 246 #define VR_CFG_MIIOPT 0x00000010 247 #define VR_CFG_MMIENB 0x00000020 /* memory mapped mode enb */ 248 #define VR_CFG_JUMPER 0x00000040 /* PHY and oper. mode select */ 249 #define VR_CFG_EELOAD 0x00000080 /* enable EEPROM programming */ 250 #define VR_CFG_LATMENB 0x00000100 /* larency timer effect enb. */ 251 #define VR_CFG_MRREADWAIT 0x00000200 252 #define VR_CFG_MRWRITEWAIT 0x00000400 253 #define VR_CFG_RX_ARB 0x00000800 254 #define VR_CFG_TX_ARB 0x00001000 255 #define VR_CFG_READMULTI 0x00002000 256 #define VR_CFG_TX_PACE 0x00004000 257 #define VR_CFG_TX_QDIS 0x00008000 258 #define VR_CFG_ROMSEL0 0x00010000 259 #define VR_CFG_ROMSEL1 0x00020000 260 #define VR_CFG_ROMSEL2 0x00040000 261 #define VR_CFG_ROMTIMESEL 0x00080000 262 #define VR_CFG_RSVD0 0x00100000 263 #define VR_CFG_ROMDLY 0x00200000 264 #define VR_CFG_ROMOPT 0x00400000 265 #define VR_CFG_RSVD1 0x00800000 266 #define VR_CFG_BACKOFFOPT 0x01000000 267 #define VR_CFG_BACKOFFMOD 0x02000000 268 #define VR_CFG_CAPEFFECT 0x04000000 269 #define VR_CFG_BACKOFFRAND 0x08000000 270 #define VR_CFG_MAGICKPACKET 0x10000000 271 #define VR_CFG_PCIREADLINE 0x20000000 272 #define VR_CFG_DIAG 0x40000000 273 #define VR_CFG_GPIOEN 0x80000000 274 275 /* Sticky HW bits */ 276 #define VR_STICKHW_DS0 0x01 277 #define VR_STICKHW_DS1 0x02 278 #define VR_STICKHW_WOL_ENB 0x04 279 #define VR_STICKHW_WOL_STS 0x08 280 #define VR_STICKHW_LEGWOL_ENB 0x80 281 282 /* 283 * Rhine TX/RX list structure. 284 */ 285 286 struct vr_desc { 287 u_int32_t vr_status; 288 u_int32_t vr_ctl; 289 u_int32_t vr_ptr1; 290 u_int32_t vr_ptr2; 291 }; 292 293 #define vr_data vr_ptr1 294 #define vr_next vr_ptr2 295 296 297 #define VR_RXSTAT_RXERR 0x00000001 298 #define VR_RXSTAT_CRCERR 0x00000002 299 #define VR_RXSTAT_FRAMEALIGNERR 0x00000004 300 #define VR_RXSTAT_FIFOOFLOW 0x00000008 301 #define VR_RXSTAT_GIANT 0x00000010 302 #define VR_RXSTAT_RUNT 0x00000020 303 #define VR_RXSTAT_BUSERR 0x00000040 304 #define VR_RXSTAT_BUFFERR 0x00000080 305 #define VR_RXSTAT_LASTFRAG 0x00000100 306 #define VR_RXSTAT_FIRSTFRAG 0x00000200 307 #define VR_RXSTAT_RLINK 0x00000400 308 #define VR_RXSTAT_RX_PHYS 0x00000800 309 #define VR_RXSTAT_RX_BROAD 0x00001000 310 #define VR_RXSTAT_RX_MULTI 0x00002000 311 #define VR_RXSTAT_RX_OK 0x00004000 312 #define VR_RXSTAT_RXLEN 0x07FF0000 313 #define VR_RXSTAT_RXLEN_EXT 0x78000000 314 #define VR_RXSTAT_OWN 0x80000000 315 316 #define VR_RXBYTES(x) ((x & VR_RXSTAT_RXLEN) >> 16) 317 #define VR_RXSTAT (VR_RXSTAT_FIRSTFRAG|VR_RXSTAT_LASTFRAG|VR_RXSTAT_OWN) 318 319 #define VR_RXCTL_BUFLEN 0x000007FF 320 #define VR_RXCTL_BUFLEN_EXT 0x00007800 321 #define VR_RXCTL_CHAIN 0x00008000 322 #define VR_RXCTL_RX_INTR 0x00800000 323 324 #define VR_RXCTL (VR_RXCTL_CHAIN|VR_RXCTL_RX_INTR) 325 326 #define VR_TXSTAT_DEFER 0x00000001 327 #define VR_TXSTAT_UNDERRUN 0x00000002 328 #define VR_TXSTAT_COLLCNT 0x00000078 329 #define VR_TXSTAT_SQE 0x00000080 330 #define VR_TXSTAT_ABRT 0x00000100 331 #define VR_TXSTAT_LATECOLL 0x00000200 332 #define VR_TXSTAT_CARRLOST 0x00000400 333 #define VR_TXSTAT_BUSERR 0x00002000 334 #define VR_TXSTAT_JABTIMEO 0x00004000 335 #define VR_TXSTAT_ERRSUM 0x00008000 336 #define VR_TXSTAT_OWN 0x80000000 337 338 #define VR_TXCTL_BUFLEN 0x000007FF 339 #define VR_TXCTL_BUFLEN_EXT 0x00007800 340 #define VR_TXCTL_TLINK 0x00008000 341 #define VR_TXCTL_FIRSTFRAG 0x00200000 342 #define VR_TXCTL_LASTFRAG 0x00400000 343 #define VR_TXCTL_FINT 0x00800000 344 345 #define VR_MAXFRAGS 16 346 #define VR_RX_LIST_CNT 64 347 #define VR_TX_LIST_CNT 128 348 #define VR_MIN_FRAMELEN 60 349 #define VR_FRAMELEN 1536 350 #define VR_RXLEN 1520 351 352 #define VR_TXOWN(x) x->vr_ptr->vr_status 353 354 struct vr_list_data { 355 struct vr_desc vr_rx_list[VR_RX_LIST_CNT]; 356 struct vr_desc vr_tx_list[VR_TX_LIST_CNT]; 357 }; 358 359 struct vr_chain { 360 struct vr_desc *vr_ptr; 361 struct mbuf *vr_mbuf; 362 struct vr_chain *vr_nextdesc; 363 }; 364 365 struct vr_chain_onefrag { 366 struct vr_desc *vr_ptr; 367 struct mbuf *vr_mbuf; 368 struct vr_chain_onefrag *vr_nextdesc; 369 }; 370 371 struct vr_chain_data { 372 struct vr_chain_onefrag vr_rx_chain[VR_RX_LIST_CNT]; 373 struct vr_chain vr_tx_chain[VR_TX_LIST_CNT]; 374 375 struct vr_chain_onefrag *vr_rx_head; 376 377 struct vr_chain *vr_tx_head; 378 struct vr_chain *vr_tx_tail; 379 struct vr_chain *vr_tx_free; 380 }; 381 382 struct vr_type { 383 u_int16_t vr_vid; 384 u_int16_t vr_did; 385 char *vr_name; 386 }; 387 388 struct vr_mii_frame { 389 u_int8_t mii_stdelim; 390 u_int8_t mii_opcode; 391 u_int8_t mii_phyaddr; 392 u_int8_t mii_regaddr; 393 u_int8_t mii_turnaround; 394 u_int16_t mii_data; 395 }; 396 397 /* 398 * MII constants 399 */ 400 #define VR_MII_STARTDELIM 0x01 401 #define VR_MII_READOP 0x02 402 #define VR_MII_WRITEOP 0x01 403 #define VR_MII_TURNAROUND 0x02 404 405 #define VR_FLAG_FORCEDELAY 1 406 #define VR_FLAG_SCHEDDELAY 2 407 #define VR_FLAG_DELAYTIMEO 3 408 409 struct vr_softc { 410 struct device sc_dev; /* generic device structure */ 411 void * sc_ih; /* interrupt handler cookie */ 412 struct arpcom arpcom; /* interface info */ 413 bus_space_handle_t vr_bhandle; /* bus space handle */ 414 bus_space_tag_t vr_btag; /* bus space tag */ 415 bus_dma_tag_t sc_dmat; 416 struct vr_type *vr_info; /* Rhine adapter info */ 417 struct vr_list_data *vr_ldata; 418 struct vr_chain_data vr_cdata; 419 struct mii_data sc_mii; 420 struct timeout sc_to; 421 }; 422 423 /* 424 * register space access macros 425 */ 426 #define CSR_WRITE_4(sc, reg, val) \ 427 bus_space_write_4(sc->vr_btag, sc->vr_bhandle, reg, val) 428 #define CSR_WRITE_2(sc, reg, val) \ 429 bus_space_write_2(sc->vr_btag, sc->vr_bhandle, reg, val) 430 #define CSR_WRITE_1(sc, reg, val) \ 431 bus_space_write_1(sc->vr_btag, sc->vr_bhandle, reg, val) 432 433 #define CSR_READ_4(sc, reg) \ 434 bus_space_read_4(sc->vr_btag, sc->vr_bhandle, reg) 435 #define CSR_READ_2(sc, reg) \ 436 bus_space_read_2(sc->vr_btag, sc->vr_bhandle, reg) 437 #define CSR_READ_1(sc, reg) \ 438 bus_space_read_1(sc->vr_btag, sc->vr_bhandle, reg) 439 440 #define VR_TIMEOUT 1000 441 #define ETHER_ALIGN 2 442 443 /* 444 * General constants that are fun to know. 445 * 446 * VIA vendor ID 447 */ 448 #define VIA_VENDORID 0x1106 449 450 /* 451 * VIA Rhine device IDs. 452 */ 453 #define VIA_DEVICEID_RHINE 0x3043 454 #define VIA_DEVICEID_RHINE_II 0x6100 455 #define VIA_DEVICEID_RHINE_II_2 0x3065 456 457 /* 458 * Delta Electronics device ID. 459 */ 460 #define DELTA_VENDORID 0x1500 461 462 /* 463 * Delta device IDs. 464 */ 465 #define DELTA_DEVICEID_RHINE_II 0x1320 466 467 /* 468 * Addtron vendor ID. 469 */ 470 #define ADDTRON_VENDORID 0x4033 471 472 /* 473 * Addtron device IDs. 474 */ 475 #define ADDTRON_DEVICEID_RHINE_II 0x1320 476 477 478 /* 479 * PCI low memory base and low I/O base register, and 480 * other PCI registers. 481 */ 482 483 #define VR_PCI_VENDOR_ID 0x00 484 #define VR_PCI_DEVICE_ID 0x02 485 #define VR_PCI_COMMAND 0x04 486 #define VR_PCI_STATUS 0x06 487 #define VR_PCI_CLASSCODE 0x09 488 #define VR_PCI_LATENCY_TIMER 0x0D 489 #define VR_PCI_HEADER_TYPE 0x0E 490 #define VR_PCI_LOIO 0x10 491 #define VR_PCI_LOMEM 0x14 492 #define VR_PCI_BIOSROM 0x30 493 #define VR_PCI_INTLINE 0x3C 494 #define VR_PCI_INTPIN 0x3D 495 #define VR_PCI_MINGNT 0x3E 496 #define VR_PCI_MINLAT 0x0F 497 #define VR_PCI_RESETOPT 0x48 498 #define VR_PCI_EEPROM_DATA 0x4C 499 500 /* power management registers */ 501 #define VR_PCI_CAPID 0xDC /* 8 bits */ 502 #define VR_PCI_NEXTPTR 0xDD /* 8 bits */ 503 #define VR_PCI_PWRMGMTCAP 0xDE /* 16 bits */ 504 #define VR_PCI_PWRMGMTCTRL 0xE0 /* 16 bits */ 505 506 #define VR_PSTATE_MASK 0x0003 507 #define VR_PSTATE_D0 0x0000 508 #define VR_PSTATE_D1 0x0002 509 #define VR_PSTATE_D2 0x0002 510 #define VR_PSTATE_D3 0x0003 511 #define VR_PME_EN 0x0010 512 #define VR_PME_STATUS 0x8000 513 514 #ifndef ETHER_CRC_LEN 515 #define ETHER_CRC_LEN 4 516 #endif 517 518 #ifdef __alpha__ 519 #undef vtophys 520 #define vtophys(va) alpha_XXX_dmamap((vm_offset_t)va) 521 #endif 522