1 /* $OpenBSD: if_vr.c,v 1.31 2003/02/19 14:38:22 miod Exp $ */ 2 3 /* 4 * Copyright (c) 1997, 1998 5 * Bill Paul <wpaul@ctr.columbia.edu>. All rights reserved. 6 * 7 * Redistribution and use in source and binary forms, with or without 8 * modification, are permitted provided that the following conditions 9 * are met: 10 * 1. Redistributions of source code must retain the above copyright 11 * notice, this list of conditions and the following disclaimer. 12 * 2. Redistributions in binary form must reproduce the above copyright 13 * notice, this list of conditions and the following disclaimer in the 14 * documentation and/or other materials provided with the distribution. 15 * 3. All advertising materials mentioning features or use of this software 16 * must display the following acknowledgement: 17 * This product includes software developed by Bill Paul. 18 * 4. Neither the name of the author nor the names of any co-contributors 19 * may be used to endorse or promote products derived from this software 20 * without specific prior written permission. 21 * 22 * THIS SOFTWARE IS PROVIDED BY Bill Paul AND CONTRIBUTORS ``AS IS'' AND 23 * ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE 24 * IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE 25 * ARE DISCLAIMED. IN NO EVENT SHALL Bill Paul OR THE VOICES IN HIS HEAD 26 * BE LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR 27 * CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF 28 * SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS 29 * INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN 30 * CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) 31 * ARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF 32 * THE POSSIBILITY OF SUCH DAMAGE. 33 * 34 * $FreeBSD: src/sys/pci/if_vr.c,v 1.61 2003/02/01 01:27:05 silby Exp $ 35 */ 36 37 /* 38 * VIA Rhine fast ethernet PCI NIC driver 39 * 40 * Supports various network adapters based on the VIA Rhine 41 * and Rhine II PCI controllers, including the D-Link DFE530TX. 42 * Datasheets are available at http://www.via.com.tw. 43 * 44 * Written by Bill Paul <wpaul@ctr.columbia.edu> 45 * Electrical Engineering Department 46 * Columbia University, New York City 47 */ 48 49 /* 50 * The VIA Rhine controllers are similar in some respects to the 51 * the DEC tulip chips, except less complicated. The controller 52 * uses an MII bus and an external physical layer interface. The 53 * receiver has a one entry perfect filter and a 64-bit hash table 54 * multicast filter. Transmit and receive descriptors are similar 55 * to the tulip. 56 * 57 * The Rhine has a serious flaw in its transmit DMA mechanism: 58 * transmit buffers must be longword aligned. Unfortunately, 59 * FreeBSD doesn't guarantee that mbufs will be filled in starting 60 * at longword boundaries, so we have to do a buffer copy before 61 * transmission. 62 */ 63 64 #include "bpfilter.h" 65 66 #include <sys/param.h> 67 #include <sys/systm.h> 68 #include <sys/sockio.h> 69 #include <sys/mbuf.h> 70 #include <sys/malloc.h> 71 #include <sys/kernel.h> 72 #include <sys/socket.h> 73 74 #include <net/if.h> 75 #include <sys/device.h> 76 #ifdef INET 77 #include <netinet/in.h> 78 #include <netinet/in_systm.h> 79 #include <netinet/in_var.h> 80 #include <netinet/ip.h> 81 #include <netinet/if_ether.h> 82 #endif /* INET */ 83 #include <net/if_dl.h> 84 #include <net/if_media.h> 85 86 #if NBPFILTER > 0 87 #include <net/bpf.h> 88 #endif 89 90 #include <uvm/uvm_extern.h> /* for vtophys */ 91 92 #include <dev/mii/mii.h> 93 #include <dev/mii/miivar.h> 94 95 #include <dev/pci/pcireg.h> 96 #include <dev/pci/pcivar.h> 97 #include <dev/pci/pcidevs.h> 98 99 #define VR_USEIOSPACE 100 #undef VR_USESWSHIFT 101 102 #include <dev/pci/if_vrreg.h> 103 104 int vr_probe(struct device *, void *, void *); 105 void vr_attach(struct device *, struct device *, void *); 106 107 struct cfattach vr_ca = { 108 sizeof(struct vr_softc), vr_probe, vr_attach 109 }; 110 struct cfdriver vr_cd = { 111 0, "vr", DV_IFNET 112 }; 113 114 int vr_newbuf(struct vr_softc *, 115 struct vr_chain_onefrag *, 116 struct mbuf *); 117 int vr_encap(struct vr_softc *, struct vr_chain *, 118 struct mbuf * ); 119 120 void vr_rxeof(struct vr_softc *); 121 void vr_rxeoc(struct vr_softc *); 122 void vr_txeof(struct vr_softc *); 123 void vr_txeoc(struct vr_softc *); 124 void vr_tick(void *); 125 int vr_intr(void *); 126 void vr_start(struct ifnet *); 127 int vr_ioctl(struct ifnet *, u_long, caddr_t); 128 void vr_init(void *); 129 void vr_stop(struct vr_softc *); 130 void vr_watchdog(struct ifnet *); 131 void vr_shutdown(void *); 132 int vr_ifmedia_upd(struct ifnet *); 133 void vr_ifmedia_sts(struct ifnet *, struct ifmediareq *); 134 135 void vr_mii_sync(struct vr_softc *); 136 void vr_mii_send(struct vr_softc *, u_int32_t, int); 137 int vr_mii_readreg(struct vr_softc *, struct vr_mii_frame *); 138 int vr_mii_writereg(struct vr_softc *, struct vr_mii_frame *); 139 int vr_miibus_readreg(struct device *, int, int); 140 void vr_miibus_writereg(struct device *, int, int, int); 141 void vr_miibus_statchg(struct device *); 142 143 void vr_setcfg(struct vr_softc *, int); 144 u_int8_t vr_calchash(u_int8_t *); 145 void vr_setmulti(struct vr_softc *); 146 void vr_reset(struct vr_softc *); 147 int vr_list_rx_init(struct vr_softc *); 148 int vr_list_tx_init(struct vr_softc *); 149 150 #define VR_SETBIT(sc, reg, x) \ 151 CSR_WRITE_1(sc, reg, \ 152 CSR_READ_1(sc, reg) | (x)) 153 154 #define VR_CLRBIT(sc, reg, x) \ 155 CSR_WRITE_1(sc, reg, \ 156 CSR_READ_1(sc, reg) & ~(x)) 157 158 #define VR_SETBIT16(sc, reg, x) \ 159 CSR_WRITE_2(sc, reg, \ 160 CSR_READ_2(sc, reg) | (x)) 161 162 #define VR_CLRBIT16(sc, reg, x) \ 163 CSR_WRITE_2(sc, reg, \ 164 CSR_READ_2(sc, reg) & ~(x)) 165 166 #define VR_SETBIT32(sc, reg, x) \ 167 CSR_WRITE_4(sc, reg, \ 168 CSR_READ_4(sc, reg) | (x)) 169 170 #define VR_CLRBIT32(sc, reg, x) \ 171 CSR_WRITE_4(sc, reg, \ 172 CSR_READ_4(sc, reg) & ~(x)) 173 174 #define SIO_SET(x) \ 175 CSR_WRITE_1(sc, VR_MIICMD, \ 176 CSR_READ_1(sc, VR_MIICMD) | (x)) 177 178 #define SIO_CLR(x) \ 179 CSR_WRITE_1(sc, VR_MIICMD, \ 180 CSR_READ_1(sc, VR_MIICMD) & ~(x)) 181 182 #ifdef VR_USESWSHIFT 183 /* 184 * Sync the PHYs by setting data bit and strobing the clock 32 times. 185 */ 186 void 187 vr_mii_sync(sc) 188 struct vr_softc *sc; 189 { 190 register int i; 191 192 SIO_SET(VR_MIICMD_DIR|VR_MIICMD_DATAIN); 193 194 for (i = 0; i < 32; i++) { 195 SIO_SET(VR_MIICMD_CLK); 196 DELAY(1); 197 SIO_CLR(VR_MIICMD_CLK); 198 DELAY(1); 199 } 200 201 return; 202 } 203 204 /* 205 * Clock a series of bits through the MII. 206 */ 207 void 208 vr_mii_send(sc, bits, cnt) 209 struct vr_softc *sc; 210 u_int32_t bits; 211 int cnt; 212 { 213 int i; 214 215 SIO_CLR(VR_MIICMD_CLK); 216 217 for (i = (0x1 << (cnt - 1)); i; i >>= 1) { 218 if (bits & i) { 219 SIO_SET(VR_MIICMD_DATAIN); 220 } else { 221 SIO_CLR(VR_MIICMD_DATAIN); 222 } 223 DELAY(1); 224 SIO_CLR(VR_MIICMD_CLK); 225 DELAY(1); 226 SIO_SET(VR_MIICMD_CLK); 227 } 228 } 229 #endif 230 231 /* 232 * Read an PHY register through the MII. 233 */ 234 int 235 vr_mii_readreg(sc, frame) 236 struct vr_softc *sc; 237 struct vr_mii_frame *frame; 238 239 #ifdef VR_USESWSHIFT 240 { 241 int i, ack, s; 242 243 s = splimp(); 244 245 /* 246 * Set up frame for RX. 247 */ 248 frame->mii_stdelim = VR_MII_STARTDELIM; 249 frame->mii_opcode = VR_MII_READOP; 250 frame->mii_turnaround = 0; 251 frame->mii_data = 0; 252 253 CSR_WRITE_1(sc, VR_MIICMD, 0); 254 VR_SETBIT(sc, VR_MIICMD, VR_MIICMD_DIRECTPGM); 255 256 /* 257 * Turn on data xmit. 258 */ 259 SIO_SET(VR_MIICMD_DIR); 260 261 vr_mii_sync(sc); 262 263 /* 264 * Send command/address info. 265 */ 266 vr_mii_send(sc, frame->mii_stdelim, 2); 267 vr_mii_send(sc, frame->mii_opcode, 2); 268 vr_mii_send(sc, frame->mii_phyaddr, 5); 269 vr_mii_send(sc, frame->mii_regaddr, 5); 270 271 /* Idle bit */ 272 SIO_CLR((VR_MIICMD_CLK|VR_MIICMD_DATAIN)); 273 DELAY(1); 274 SIO_SET(VR_MIICMD_CLK); 275 DELAY(1); 276 277 /* Turn off xmit. */ 278 SIO_CLR(VR_MIICMD_DIR); 279 280 /* Check for ack */ 281 SIO_CLR(VR_MIICMD_CLK); 282 DELAY(1); 283 ack = CSR_READ_4(sc, VR_MIICMD) & VR_MIICMD_DATAOUT; 284 SIO_SET(VR_MIICMD_CLK); 285 DELAY(1); 286 287 /* 288 * Now try reading data bits. If the ack failed, we still 289 * need to clock through 16 cycles to keep the PHY(s) in sync. 290 */ 291 if (ack) { 292 for(i = 0; i < 16; i++) { 293 SIO_CLR(VR_MIICMD_CLK); 294 DELAY(1); 295 SIO_SET(VR_MIICMD_CLK); 296 DELAY(1); 297 } 298 goto fail; 299 } 300 301 for (i = 0x8000; i; i >>= 1) { 302 SIO_CLR(VR_MIICMD_CLK); 303 DELAY(1); 304 if (!ack) { 305 if (CSR_READ_4(sc, VR_MIICMD) & VR_MIICMD_DATAOUT) 306 frame->mii_data |= i; 307 DELAY(1); 308 } 309 SIO_SET(VR_MIICMD_CLK); 310 DELAY(1); 311 } 312 313 fail: 314 315 SIO_CLR(VR_MIICMD_CLK); 316 DELAY(1); 317 SIO_SET(VR_MIICMD_CLK); 318 DELAY(1); 319 320 splx(s); 321 322 if (ack) 323 return(1); 324 return(0); 325 } 326 #else 327 { 328 int s, i; 329 330 s = splimp(); 331 332 /* Set the PHY-address */ 333 CSR_WRITE_1(sc, VR_PHYADDR, (CSR_READ_1(sc, VR_PHYADDR)& 0xe0)| 334 frame->mii_phyaddr); 335 336 /* Set the register-address */ 337 CSR_WRITE_1(sc, VR_MIIADDR, frame->mii_regaddr); 338 VR_SETBIT(sc, VR_MIICMD, VR_MIICMD_READ_ENB); 339 340 for (i = 0; i < 10000; i++) { 341 if ((CSR_READ_1(sc, VR_MIICMD) & VR_MIICMD_READ_ENB) == 0) 342 break; 343 DELAY(1); 344 } 345 346 frame->mii_data = CSR_READ_2(sc, VR_MIIDATA); 347 348 (void)splx(s); 349 350 return(0); 351 } 352 #endif 353 354 355 /* 356 * Write to a PHY register through the MII. 357 */ 358 int 359 vr_mii_writereg(sc, frame) 360 struct vr_softc *sc; 361 struct vr_mii_frame *frame; 362 363 #ifdef VR_USESWSHIFT 364 { 365 int s; 366 367 s = splimp(); 368 369 CSR_WRITE_1(sc, VR_MIICMD, 0); 370 VR_SETBIT(sc, VR_MIICMD, VR_MIICMD_DIRECTPGM); 371 372 /* 373 * Set up frame for TX. 374 */ 375 376 frame->mii_stdelim = VR_MII_STARTDELIM; 377 frame->mii_opcode = VR_MII_WRITEOP; 378 frame->mii_turnaround = VR_MII_TURNAROUND; 379 380 /* 381 * Turn on data output. 382 */ 383 SIO_SET(VR_MIICMD_DIR); 384 385 vr_mii_sync(sc); 386 387 vr_mii_send(sc, frame->mii_stdelim, 2); 388 vr_mii_send(sc, frame->mii_opcode, 2); 389 vr_mii_send(sc, frame->mii_phyaddr, 5); 390 vr_mii_send(sc, frame->mii_regaddr, 5); 391 vr_mii_send(sc, frame->mii_turnaround, 2); 392 vr_mii_send(sc, frame->mii_data, 16); 393 394 /* Idle bit. */ 395 SIO_SET(VR_MIICMD_CLK); 396 DELAY(1); 397 SIO_CLR(VR_MIICMD_CLK); 398 DELAY(1); 399 400 /* 401 * Turn off xmit. 402 */ 403 SIO_CLR(VR_MIICMD_DIR); 404 405 splx(s); 406 407 return(0); 408 } 409 #else 410 { 411 int s, i; 412 413 s = splimp(); 414 415 /* Set the PHY-address */ 416 CSR_WRITE_1(sc, VR_PHYADDR, (CSR_READ_1(sc, VR_PHYADDR)& 0xe0)| 417 frame->mii_phyaddr); 418 419 /* Set the register-address and data to write */ 420 CSR_WRITE_1(sc, VR_MIIADDR, frame->mii_regaddr); 421 CSR_WRITE_2(sc, VR_MIIDATA, frame->mii_data); 422 423 VR_SETBIT(sc, VR_MIICMD, VR_MIICMD_WRITE_ENB); 424 425 for (i = 0; i < 10000; i++) { 426 if ((CSR_READ_1(sc, VR_MIICMD) & VR_MIICMD_WRITE_ENB) == 0) 427 break; 428 DELAY(1); 429 } 430 431 (void)splx(s); 432 433 return(0); 434 } 435 #endif 436 437 int 438 vr_miibus_readreg(dev, phy, reg) 439 struct device *dev; 440 int phy, reg; 441 { 442 struct vr_softc *sc = (struct vr_softc *)dev; 443 struct vr_mii_frame frame; 444 445 switch (sc->vr_revid) { 446 case REV_ID_VT6102_APOLLO: 447 if (phy != 1) 448 return 0; 449 default: 450 break; 451 } 452 453 bzero((char *)&frame, sizeof(frame)); 454 455 frame.mii_phyaddr = phy; 456 frame.mii_regaddr = reg; 457 vr_mii_readreg(sc, &frame); 458 459 return(frame.mii_data); 460 } 461 462 void 463 vr_miibus_writereg(dev, phy, reg, data) 464 struct device *dev; 465 int phy, reg, data; 466 { 467 struct vr_softc *sc = (struct vr_softc *)dev; 468 struct vr_mii_frame frame; 469 470 switch (sc->vr_revid) { 471 case REV_ID_VT6102_APOLLO: 472 if (phy != 1) 473 return; 474 default: 475 break; 476 } 477 478 bzero((char *)&frame, sizeof(frame)); 479 480 frame.mii_phyaddr = phy; 481 frame.mii_regaddr = reg; 482 frame.mii_data = data; 483 484 vr_mii_writereg(sc, &frame); 485 486 return; 487 } 488 489 void 490 vr_miibus_statchg(dev) 491 struct device *dev; 492 { 493 struct vr_softc *sc = (struct vr_softc *)dev; 494 495 vr_setcfg(sc, sc->sc_mii.mii_media_active); 496 } 497 498 /* 499 * Calculate CRC of a multicast group address, return the lower 6 bits. 500 */ 501 u_int8_t 502 vr_calchash(addr) 503 u_int8_t *addr; 504 { 505 u_int32_t crc, carry; 506 int i, j; 507 u_int8_t c; 508 509 /* Compute CRC for the address value. */ 510 crc = 0xFFFFFFFF; /* initial value */ 511 512 for (i = 0; i < 6; i++) { 513 c = *(addr + i); 514 for (j = 0; j < 8; j++) { 515 carry = ((crc & 0x80000000) ? 1 : 0) ^ (c & 0x01); 516 crc <<= 1; 517 c >>= 1; 518 if (carry) 519 crc = (crc ^ 0x04c11db6) | carry; 520 } 521 } 522 523 /* return the filter bit position */ 524 return((crc >> 26) & 0x0000003F); 525 } 526 527 /* 528 * Program the 64-bit multicast hash filter. 529 */ 530 void 531 vr_setmulti(sc) 532 struct vr_softc *sc; 533 { 534 struct ifnet *ifp; 535 int h = 0; 536 u_int32_t hashes[2] = { 0, 0 }; 537 struct arpcom *ac = &sc->arpcom; 538 struct ether_multi *enm; 539 struct ether_multistep step; 540 u_int8_t rxfilt; 541 int mcnt = 0; 542 543 ifp = &sc->arpcom.ac_if; 544 545 rxfilt = CSR_READ_1(sc, VR_RXCFG); 546 547 if (ifp->if_flags & IFF_ALLMULTI || ifp->if_flags & IFF_PROMISC) { 548 rxfilt |= VR_RXCFG_RX_MULTI; 549 CSR_WRITE_1(sc, VR_RXCFG, rxfilt); 550 CSR_WRITE_4(sc, VR_MAR0, 0xFFFFFFFF); 551 CSR_WRITE_4(sc, VR_MAR1, 0xFFFFFFFF); 552 return; 553 } 554 555 /* first, zot all the existing hash bits */ 556 CSR_WRITE_4(sc, VR_MAR0, 0); 557 CSR_WRITE_4(sc, VR_MAR1, 0); 558 559 /* now program new ones */ 560 ETHER_FIRST_MULTI(step, ac, enm); 561 while (enm != NULL) { 562 h = vr_calchash(enm->enm_addrlo); 563 if (h < 32) 564 hashes[0] |= (1 << h); 565 else 566 hashes[1] |= (1 << (h - 32)); 567 mcnt++; 568 569 ETHER_NEXT_MULTI(step, enm); 570 } 571 572 if (mcnt) 573 rxfilt |= VR_RXCFG_RX_MULTI; 574 else 575 rxfilt &= ~VR_RXCFG_RX_MULTI; 576 577 CSR_WRITE_4(sc, VR_MAR0, hashes[0]); 578 CSR_WRITE_4(sc, VR_MAR1, hashes[1]); 579 CSR_WRITE_1(sc, VR_RXCFG, rxfilt); 580 581 return; 582 } 583 584 /* 585 * In order to fiddle with the 586 * 'full-duplex' and '100Mbps' bits in the netconfig register, we 587 * first have to put the transmit and/or receive logic in the idle state. 588 */ 589 void 590 vr_setcfg(sc, media) 591 struct vr_softc *sc; 592 int media; 593 { 594 int restart = 0; 595 596 if (CSR_READ_2(sc, VR_COMMAND) & (VR_CMD_TX_ON|VR_CMD_RX_ON)) { 597 restart = 1; 598 VR_CLRBIT16(sc, VR_COMMAND, (VR_CMD_TX_ON|VR_CMD_RX_ON)); 599 } 600 601 if ((media & IFM_GMASK) == IFM_FDX) 602 VR_SETBIT16(sc, VR_COMMAND, VR_CMD_FULLDUPLEX); 603 else 604 VR_CLRBIT16(sc, VR_COMMAND, VR_CMD_FULLDUPLEX); 605 606 if (restart) 607 VR_SETBIT16(sc, VR_COMMAND, VR_CMD_TX_ON|VR_CMD_RX_ON); 608 609 return; 610 } 611 612 void 613 vr_reset(sc) 614 struct vr_softc *sc; 615 { 616 register int i; 617 618 VR_SETBIT16(sc, VR_COMMAND, VR_CMD_RESET); 619 620 for (i = 0; i < VR_TIMEOUT; i++) { 621 DELAY(10); 622 if (!(CSR_READ_2(sc, VR_COMMAND) & VR_CMD_RESET)) 623 break; 624 } 625 if (i == VR_TIMEOUT) { 626 if (sc->vr_revid < REV_ID_VT3065_A) 627 printf("%s: reset never completed!\n", 628 sc->sc_dev.dv_xname); 629 else { 630 /* Use newer force reset command */ 631 printf("%s: Using force reset command.\n", 632 sc->sc_dev.dv_xname); 633 VR_SETBIT(sc, VR_MISC_CR1, VR_MISCCR1_FORSRST); 634 } 635 } 636 637 /* Wait a little while for the chip to get its brains in order. */ 638 DELAY(1000); 639 } 640 641 const struct pci_matchid vr_devices[] = { 642 { PCI_VENDOR_VIATECH, PCI_PRODUCT_VIATECH_RHINE }, 643 { PCI_VENDOR_VIATECH, PCI_PRODUCT_VIATECH_RHINEII }, 644 { PCI_VENDOR_VIATECH, PCI_PRODUCT_VIATECH_RHINEII_2 }, 645 { PCI_VENDOR_VIATECH, PCI_PRODUCT_VIATECH_VT6105 }, 646 { PCI_VENDOR_DELTA, PCI_PRODUCT_DELTA_RHINEII }, 647 { PCI_VENDOR_ADDTRON, PCI_PRODUCT_ADDTRON_RHINEII }, 648 }; 649 650 /* 651 * Probe for a VIA Rhine chip. 652 */ 653 int 654 vr_probe(parent, match, aux) 655 struct device *parent; 656 void *match, *aux; 657 { 658 return (pci_matchbyid((struct pci_attach_args *)aux, vr_devices, 659 sizeof(vr_devices)/sizeof(vr_devices[0]))); 660 } 661 662 /* 663 * Attach the interface. Allocate softc structures, do ifmedia 664 * setup and ethernet/BPF attach. 665 */ 666 void 667 vr_attach(parent, self, aux) 668 struct device *parent, *self; 669 void *aux; 670 { 671 int s, i; 672 u_int32_t command; 673 struct vr_softc *sc = (struct vr_softc *)self; 674 struct pci_attach_args *pa = aux; 675 pci_chipset_tag_t pc = pa->pa_pc; 676 pci_intr_handle_t ih; 677 const char *intrstr = NULL; 678 struct ifnet *ifp = &sc->arpcom.ac_if; 679 bus_addr_t iobase; 680 bus_size_t iosize; 681 bus_dma_segment_t seg; 682 bus_dmamap_t dmamap; 683 int rseg; 684 caddr_t kva; 685 686 s = splimp(); 687 688 /* 689 * Handle power management nonsense. 690 */ 691 command = pci_conf_read(pa->pa_pc, pa->pa_tag, 692 VR_PCI_CAPID) & 0x000000ff; 693 if (command == 0x01) { 694 command = pci_conf_read(pa->pa_pc, pa->pa_tag, 695 VR_PCI_PWRMGMTCTRL); 696 if (command & VR_PSTATE_MASK) { 697 u_int32_t iobase, membase, irq; 698 699 /* Save important PCI config data. */ 700 iobase = pci_conf_read(pa->pa_pc, pa->pa_tag, 701 VR_PCI_LOIO); 702 membase = pci_conf_read(pa->pa_pc, pa->pa_tag, 703 VR_PCI_LOMEM); 704 irq = pci_conf_read(pa->pa_pc, pa->pa_tag, 705 VR_PCI_INTLINE); 706 707 /* Reset the power state. */ 708 command &= 0xFFFFFFFC; 709 pci_conf_write(pa->pa_pc, pa->pa_tag, 710 VR_PCI_PWRMGMTCTRL, command); 711 712 /* Restore PCI config data. */ 713 pci_conf_write(pa->pa_pc, pa->pa_tag, 714 VR_PCI_LOIO, iobase); 715 pci_conf_write(pa->pa_pc, pa->pa_tag, 716 VR_PCI_LOMEM, membase); 717 pci_conf_write(pa->pa_pc, pa->pa_tag, 718 VR_PCI_INTLINE, irq); 719 } 720 } 721 722 /* 723 * Map control/status registers. 724 */ 725 command = pci_conf_read(pa->pa_pc, pa->pa_tag, PCI_COMMAND_STATUS_REG); 726 727 #ifdef VR_USEIOSPACE 728 if (!(command & PCI_COMMAND_IO_ENABLE)) { 729 printf(": failed to enable I/O ports\n"); 730 goto fail; 731 } 732 if (pci_io_find(pc, pa->pa_tag, VR_PCI_LOIO, &iobase, &iosize)) { 733 printf(": failed to find i/o space\n"); 734 goto fail; 735 } 736 if (bus_space_map(pa->pa_iot, iobase, iosize, 0, &sc->vr_bhandle)) { 737 printf(": failed map i/o space\n"); 738 goto fail; 739 } 740 sc->vr_btag = pa->pa_iot; 741 #else 742 if (!(command & PCI_COMMAND_MEM_ENABLE)) { 743 printf(": failed to enable memory mapping\n"); 744 goto fail; 745 } 746 if (pci_mem_find(pc, pa->pa_tag, VR_PCI_LOMEM, &iobase, &iosize)) { 747 printf(": failed to find memory space\n"); 748 goto fail; 749 } 750 if (bus_space_map(pa->pa_memt, iobase, iosize, 0, &sc->vr_bhandle)) { 751 printf(": failed map memory space\n"); 752 goto fail; 753 } 754 sc->vr_btag = pa->pa_memt; 755 #endif 756 757 /* Allocate interrupt */ 758 if (pci_intr_map(pa, &ih)) { 759 printf(": couldn't map interrupt\n"); 760 goto fail; 761 } 762 intrstr = pci_intr_string(pc, ih); 763 sc->sc_ih = pci_intr_establish(pc, ih, IPL_NET, vr_intr, sc, 764 self->dv_xname); 765 if (sc->sc_ih == NULL) { 766 printf(": could not establish interrupt"); 767 if (intrstr != NULL) 768 printf(" at %s", intrstr); 769 printf("\n"); 770 goto fail; 771 } 772 printf(": %s", intrstr); 773 774 /* 775 * Windows may put the chip in suspend mode when it 776 * shuts down. Be sure to kick it in the head to wake it 777 * up again. 778 */ 779 VR_CLRBIT(sc, VR_STICKHW, (VR_STICKHW_DS0|VR_STICKHW_DS1)); 780 781 /* Reset the adapter. */ 782 vr_reset(sc); 783 784 /* 785 * Turn on bit2 (MIION) in PCI configuration register 0x53 during 786 * initialization and disable AUTOPOLL. 787 */ 788 pci_conf_write(pa->pa_pc, pa->pa_tag, VR_PCI_MODE, 789 pci_conf_read(pa->pa_pc, pa->pa_tag, VR_PCI_MODE) | 790 (VR_MODE3_MIION << 24)); 791 VR_CLRBIT(sc, VR_MIICMD, VR_MIICMD_AUTOPOLL); 792 793 /* 794 * Get station address. The way the Rhine chips work, 795 * you're not allowed to directly access the EEPROM once 796 * they've been programmed a special way. Consequently, 797 * we need to read the node address from the PAR0 and PAR1 798 * registers. 799 */ 800 VR_SETBIT(sc, VR_EECSR, VR_EECSR_LOAD); 801 DELAY(1000); 802 for (i = 0; i < ETHER_ADDR_LEN; i++) 803 sc->arpcom.ac_enaddr[i] = CSR_READ_1(sc, VR_PAR0 + i); 804 805 /* 806 * A Rhine chip was detected. Inform the world. 807 */ 808 printf(" address %s\n", ether_sprintf(sc->arpcom.ac_enaddr)); 809 810 sc->sc_dmat = pa->pa_dmat; 811 if (bus_dmamem_alloc(sc->sc_dmat, sizeof(struct vr_list_data), 812 PAGE_SIZE, 0, &seg, 1, &rseg, BUS_DMA_NOWAIT)) { 813 printf("%s: can't alloc list\n", sc->sc_dev.dv_xname); 814 goto fail; 815 } 816 if (bus_dmamem_map(sc->sc_dmat, &seg, rseg, sizeof(struct vr_list_data), 817 &kva, BUS_DMA_NOWAIT)) { 818 printf("%s: can't map dma buffers (%d bytes)\n", 819 sc->sc_dev.dv_xname, sizeof(struct vr_list_data)); 820 bus_dmamem_free(sc->sc_dmat, &seg, rseg); 821 goto fail; 822 } 823 if (bus_dmamap_create(sc->sc_dmat, sizeof(struct vr_list_data), 1, 824 sizeof(struct vr_list_data), 0, BUS_DMA_NOWAIT, &dmamap)) { 825 printf("%s: can't create dma map\n", sc->sc_dev.dv_xname); 826 bus_dmamem_unmap(sc->sc_dmat, kva, sizeof(struct vr_list_data)); 827 bus_dmamem_free(sc->sc_dmat, &seg, rseg); 828 goto fail; 829 } 830 if (bus_dmamap_load(sc->sc_dmat, dmamap, kva, 831 sizeof(struct vr_list_data), NULL, BUS_DMA_NOWAIT)) { 832 printf("%s: can't load dma map\n", sc->sc_dev.dv_xname); 833 bus_dmamap_destroy(sc->sc_dmat, dmamap); 834 bus_dmamem_unmap(sc->sc_dmat, kva, sizeof(struct vr_list_data)); 835 bus_dmamem_free(sc->sc_dmat, &seg, rseg); 836 goto fail; 837 } 838 sc->vr_ldata = (struct vr_list_data *)kva; 839 bzero(sc->vr_ldata, sizeof(struct vr_list_data)); 840 841 ifp = &sc->arpcom.ac_if; 842 ifp->if_softc = sc; 843 ifp->if_mtu = ETHERMTU; 844 ifp->if_flags = IFF_BROADCAST | IFF_SIMPLEX | IFF_MULTICAST; 845 ifp->if_ioctl = vr_ioctl; 846 ifp->if_output = ether_output; 847 ifp->if_start = vr_start; 848 ifp->if_watchdog = vr_watchdog; 849 ifp->if_baudrate = 10000000; 850 IFQ_SET_READY(&ifp->if_snd); 851 bcopy(sc->sc_dev.dv_xname, ifp->if_xname, IFNAMSIZ); 852 853 /* 854 * Do MII setup. 855 */ 856 sc->sc_mii.mii_ifp = ifp; 857 sc->sc_mii.mii_readreg = vr_miibus_readreg; 858 sc->sc_mii.mii_writereg = vr_miibus_writereg; 859 sc->sc_mii.mii_statchg = vr_miibus_statchg; 860 ifmedia_init(&sc->sc_mii.mii_media, 0, vr_ifmedia_upd, vr_ifmedia_sts); 861 mii_attach(self, &sc->sc_mii, 0xffffffff, MII_PHY_ANY, MII_OFFSET_ANY, 862 0); 863 if (LIST_FIRST(&sc->sc_mii.mii_phys) == NULL) { 864 ifmedia_add(&sc->sc_mii.mii_media, IFM_ETHER|IFM_NONE, 0, NULL); 865 ifmedia_set(&sc->sc_mii.mii_media, IFM_ETHER|IFM_NONE); 866 } else 867 ifmedia_set(&sc->sc_mii.mii_media, IFM_ETHER|IFM_AUTO); 868 timeout_set(&sc->sc_to, vr_tick, sc); 869 870 /* 871 * Call MI attach routines. 872 */ 873 if_attach(ifp); 874 ether_ifattach(ifp); 875 876 shutdownhook_establish(vr_shutdown, sc); 877 878 fail: 879 splx(s); 880 return; 881 } 882 883 /* 884 * Initialize the transmit descriptors. 885 */ 886 int 887 vr_list_tx_init(sc) 888 struct vr_softc *sc; 889 { 890 struct vr_chain_data *cd; 891 struct vr_list_data *ld; 892 int i; 893 894 cd = &sc->vr_cdata; 895 ld = sc->vr_ldata; 896 for (i = 0; i < VR_TX_LIST_CNT; i++) { 897 cd->vr_tx_chain[i].vr_ptr = &ld->vr_tx_list[i]; 898 if (i == (VR_TX_LIST_CNT - 1)) 899 cd->vr_tx_chain[i].vr_nextdesc = 900 &cd->vr_tx_chain[0]; 901 else 902 cd->vr_tx_chain[i].vr_nextdesc = 903 &cd->vr_tx_chain[i + 1]; 904 } 905 906 cd->vr_tx_free = &cd->vr_tx_chain[0]; 907 cd->vr_tx_tail = cd->vr_tx_head = NULL; 908 909 return(0); 910 } 911 912 913 /* 914 * Initialize the RX descriptors and allocate mbufs for them. Note that 915 * we arrange the descriptors in a closed ring, so that the last descriptor 916 * points back to the first. 917 */ 918 int 919 vr_list_rx_init(sc) 920 struct vr_softc *sc; 921 { 922 struct vr_chain_data *cd; 923 struct vr_list_data *ld; 924 int i; 925 926 cd = &sc->vr_cdata; 927 ld = sc->vr_ldata; 928 929 for (i = 0; i < VR_RX_LIST_CNT; i++) { 930 cd->vr_rx_chain[i].vr_ptr = 931 (struct vr_desc *)&ld->vr_rx_list[i]; 932 if (vr_newbuf(sc, &cd->vr_rx_chain[i], NULL) == ENOBUFS) 933 return(ENOBUFS); 934 if (i == (VR_RX_LIST_CNT - 1)) { 935 cd->vr_rx_chain[i].vr_nextdesc = 936 &cd->vr_rx_chain[0]; 937 ld->vr_rx_list[i].vr_next = 938 vtophys(&ld->vr_rx_list[0]); 939 } else { 940 cd->vr_rx_chain[i].vr_nextdesc = 941 &cd->vr_rx_chain[i + 1]; 942 ld->vr_rx_list[i].vr_next = 943 vtophys(&ld->vr_rx_list[i + 1]); 944 } 945 } 946 947 cd->vr_rx_head = &cd->vr_rx_chain[0]; 948 949 return(0); 950 } 951 952 /* 953 * Initialize an RX descriptor and attach an MBUF cluster. 954 * Note: the length fields are only 11 bits wide, which means the 955 * largest size we can specify is 2047. This is important because 956 * MCLBYTES is 2048, so we have to subtract one otherwise we'll 957 * overflow the field and make a mess. 958 */ 959 int 960 vr_newbuf(sc, c, m) 961 struct vr_softc *sc; 962 struct vr_chain_onefrag *c; 963 struct mbuf *m; 964 { 965 struct mbuf *m_new = NULL; 966 967 if (m == NULL) { 968 MGETHDR(m_new, M_DONTWAIT, MT_DATA); 969 if (m_new == NULL) 970 return(ENOBUFS); 971 972 MCLGET(m_new, M_DONTWAIT); 973 if (!(m_new->m_flags & M_EXT)) { 974 m_freem(m_new); 975 return(ENOBUFS); 976 } 977 m_new->m_len = m_new->m_pkthdr.len = MCLBYTES; 978 } else { 979 m_new = m; 980 m_new->m_len = m_new->m_pkthdr.len = MCLBYTES; 981 m_new->m_data = m_new->m_ext.ext_buf; 982 } 983 984 m_adj(m_new, sizeof(u_int64_t)); 985 986 c->vr_mbuf = m_new; 987 c->vr_ptr->vr_status = VR_RXSTAT; 988 c->vr_ptr->vr_data = vtophys(mtod(m_new, caddr_t)); 989 c->vr_ptr->vr_ctl = VR_RXCTL | VR_RXLEN; 990 991 return(0); 992 } 993 994 /* 995 * A frame has been uploaded: pass the resulting mbuf chain up to 996 * the higher level protocols. 997 */ 998 void 999 vr_rxeof(sc) 1000 struct vr_softc *sc; 1001 { 1002 struct mbuf *m; 1003 struct ifnet *ifp; 1004 struct vr_chain_onefrag *cur_rx; 1005 int total_len = 0; 1006 u_int32_t rxstat; 1007 1008 ifp = &sc->arpcom.ac_if; 1009 1010 while(!((rxstat = sc->vr_cdata.vr_rx_head->vr_ptr->vr_status) & 1011 VR_RXSTAT_OWN)) { 1012 struct mbuf *m0 = NULL; 1013 1014 cur_rx = sc->vr_cdata.vr_rx_head; 1015 sc->vr_cdata.vr_rx_head = cur_rx->vr_nextdesc; 1016 m = cur_rx->vr_mbuf; 1017 1018 /* 1019 * If an error occurs, update stats, clear the 1020 * status word and leave the mbuf cluster in place: 1021 * it should simply get re-used next time this descriptor 1022 * comes up in the ring. 1023 */ 1024 if (rxstat & VR_RXSTAT_RXERR) { 1025 ifp->if_ierrors++; 1026 printf("%s: rx error (%02x):", 1027 sc->sc_dev.dv_xname, rxstat & 0x000000ff); 1028 if (rxstat & VR_RXSTAT_CRCERR) 1029 printf(" crc error"); 1030 if (rxstat & VR_RXSTAT_FRAMEALIGNERR) 1031 printf(" frame alignment error"); 1032 if (rxstat & VR_RXSTAT_FIFOOFLOW) 1033 printf(" FIFO overflow"); 1034 if (rxstat & VR_RXSTAT_GIANT) 1035 printf(" received giant packet"); 1036 if (rxstat & VR_RXSTAT_RUNT) 1037 printf(" received runt packet"); 1038 if (rxstat & VR_RXSTAT_BUSERR) 1039 printf(" system bus error"); 1040 if (rxstat & VR_RXSTAT_BUFFERR) 1041 printf(" rx buffer error"); 1042 printf("\n"); 1043 vr_newbuf(sc, cur_rx, m); 1044 continue; 1045 } 1046 1047 /* No errors; receive the packet. */ 1048 total_len = VR_RXBYTES(cur_rx->vr_ptr->vr_status); 1049 1050 /* 1051 * XXX The VIA Rhine chip includes the CRC with every 1052 * received frame, and there's no way to turn this 1053 * behavior off (at least, I can't find anything in 1054 * the manual that explains how to do it) so we have 1055 * to trim off the CRC manually. 1056 */ 1057 total_len -= ETHER_CRC_LEN; 1058 1059 m0 = m_devget(mtod(m, char *) - ETHER_ALIGN, 1060 total_len + ETHER_ALIGN, 0, ifp, NULL); 1061 vr_newbuf(sc, cur_rx, m); 1062 if (m0 == NULL) { 1063 ifp->if_ierrors++; 1064 continue; 1065 } 1066 m_adj(m0, ETHER_ALIGN); 1067 m = m0; 1068 1069 ifp->if_ipackets++; 1070 1071 #if NBPFILTER > 0 1072 /* 1073 * Handle BPF listeners. Let the BPF user see the packet. 1074 */ 1075 if (ifp->if_bpf) 1076 bpf_mtap(ifp->if_bpf, m); 1077 #endif 1078 /* pass it on. */ 1079 ether_input_mbuf(ifp, m); 1080 } 1081 1082 return; 1083 } 1084 1085 void 1086 vr_rxeoc(sc) 1087 struct vr_softc *sc; 1088 { 1089 struct ifnet *ifp; 1090 int i; 1091 1092 ifp = &sc->arpcom.ac_if; 1093 1094 ifp->if_ierrors++; 1095 1096 VR_CLRBIT16(sc, VR_COMMAND, VR_CMD_RX_ON); 1097 DELAY(10000); 1098 1099 for (i = 0x400; 1100 i && (CSR_READ_2(sc, VR_COMMAND) & VR_CMD_RX_ON); 1101 i--) 1102 ; /* Wait for receiver to stop */ 1103 1104 if (!i) { 1105 printf("%s: rx shutdown error!\n", sc->sc_dev.dv_xname); 1106 sc->vr_flags |= VR_F_RESTART; 1107 return; 1108 } 1109 1110 vr_rxeof(sc); 1111 1112 CSR_WRITE_4(sc, VR_RXADDR, vtophys(sc->vr_cdata.vr_rx_head->vr_ptr)); 1113 VR_SETBIT16(sc, VR_COMMAND, VR_CMD_RX_ON); 1114 VR_SETBIT16(sc, VR_COMMAND, VR_CMD_RX_GO); 1115 1116 return; 1117 } 1118 1119 /* 1120 * A frame was downloaded to the chip. It's safe for us to clean up 1121 * the list buffers. 1122 */ 1123 1124 void 1125 vr_txeof(sc) 1126 struct vr_softc *sc; 1127 { 1128 struct vr_chain *cur_tx; 1129 struct ifnet *ifp; 1130 1131 ifp = &sc->arpcom.ac_if; 1132 1133 /* Reset the timeout timer; if_txeoc will clear it. */ 1134 ifp->if_timer = 5; 1135 1136 /* Sanity check. */ 1137 if (sc->vr_cdata.vr_tx_head == NULL) 1138 return; 1139 1140 /* 1141 * Go through our tx list and free mbufs for those 1142 * frames that have been transmitted. 1143 */ 1144 while(sc->vr_cdata.vr_tx_head->vr_mbuf != NULL) { 1145 u_int32_t txstat; 1146 int i; 1147 1148 cur_tx = sc->vr_cdata.vr_tx_head; 1149 txstat = cur_tx->vr_ptr->vr_status; 1150 1151 if ((txstat & VR_TXSTAT_ABRT) || 1152 (txstat & VR_TXSTAT_UDF)) { 1153 for (i = 0x400; 1154 i && (CSR_READ_2(sc, VR_COMMAND) & VR_CMD_TX_ON); 1155 i--) 1156 ; /* Wait for chip to shutdown */ 1157 if (!i) { 1158 printf("%s: tx shutdown timeout\n", 1159 sc->sc_dev.dv_xname); 1160 sc->vr_flags |= VR_F_RESTART; 1161 break; 1162 } 1163 VR_TXOWN(cur_tx) = VR_TXSTAT_OWN; 1164 CSR_WRITE_4(sc, VR_TXADDR, vtophys(cur_tx->vr_ptr)); 1165 break; 1166 } 1167 1168 if (txstat & VR_TXSTAT_OWN) 1169 break; 1170 1171 if (txstat & VR_TXSTAT_ERRSUM) { 1172 ifp->if_oerrors++; 1173 if (txstat & VR_TXSTAT_DEFER) 1174 ifp->if_collisions++; 1175 if (txstat & VR_TXSTAT_LATECOLL) 1176 ifp->if_collisions++; 1177 } 1178 1179 ifp->if_collisions +=(txstat & VR_TXSTAT_COLLCNT) >> 3; 1180 1181 ifp->if_opackets++; 1182 if (cur_tx->vr_mbuf != NULL) { 1183 m_freem(cur_tx->vr_mbuf); 1184 cur_tx->vr_mbuf = NULL; 1185 } 1186 1187 if (sc->vr_cdata.vr_tx_head == sc->vr_cdata.vr_tx_tail) { 1188 sc->vr_cdata.vr_tx_head = NULL; 1189 sc->vr_cdata.vr_tx_tail = NULL; 1190 break; 1191 } 1192 1193 sc->vr_cdata.vr_tx_head = cur_tx->vr_nextdesc; 1194 } 1195 1196 return; 1197 } 1198 1199 /* 1200 * TX 'end of channel' interrupt handler. 1201 */ 1202 void 1203 vr_txeoc(sc) 1204 struct vr_softc *sc; 1205 { 1206 struct ifnet *ifp; 1207 1208 ifp = &sc->arpcom.ac_if; 1209 1210 if (sc->vr_cdata.vr_tx_head == NULL) { 1211 ifp->if_flags &= ~IFF_OACTIVE; 1212 sc->vr_cdata.vr_tx_tail = NULL; 1213 ifp->if_timer = 0; 1214 } 1215 1216 return; 1217 } 1218 1219 void 1220 vr_tick(xsc) 1221 void *xsc; 1222 { 1223 struct vr_softc *sc = xsc; 1224 int s; 1225 1226 s = splimp(); 1227 if (sc->vr_flags & VR_F_RESTART) { 1228 printf("%s: restarting\n", sc->sc_dev.dv_xname); 1229 vr_stop(sc); 1230 vr_reset(sc); 1231 vr_init(sc); 1232 sc->vr_flags &= ~VR_F_RESTART; 1233 } 1234 1235 mii_tick(&sc->sc_mii); 1236 timeout_add(&sc->sc_to, hz); 1237 splx(s); 1238 } 1239 1240 int 1241 vr_intr(arg) 1242 void *arg; 1243 { 1244 struct vr_softc *sc; 1245 struct ifnet *ifp; 1246 u_int16_t status; 1247 int claimed = 0; 1248 1249 sc = arg; 1250 ifp = &sc->arpcom.ac_if; 1251 1252 /* Supress unwanted interrupts. */ 1253 if (!(ifp->if_flags & IFF_UP)) { 1254 vr_stop(sc); 1255 return 0; 1256 } 1257 1258 /* Disable interrupts. */ 1259 CSR_WRITE_2(sc, VR_IMR, 0x0000); 1260 1261 for (;;) { 1262 1263 status = CSR_READ_2(sc, VR_ISR); 1264 if (status) 1265 CSR_WRITE_2(sc, VR_ISR, status); 1266 1267 if ((status & VR_INTRS) == 0) 1268 break; 1269 1270 claimed = 1; 1271 1272 if (status & VR_ISR_RX_OK) 1273 vr_rxeof(sc); 1274 1275 if (status & VR_ISR_RX_DROPPED) { 1276 printf("%s: rx packet lost\n", sc->sc_dev.dv_xname); 1277 ifp->if_ierrors++; 1278 } 1279 1280 if ((status & VR_ISR_RX_ERR) || (status & VR_ISR_RX_NOBUF) || 1281 (status & VR_ISR_RX_NOBUF) || (status & VR_ISR_RX_OFLOW)) { 1282 printf("%s: receive error (%04x)", 1283 sc->sc_dev.dv_xname, status); 1284 if (status & VR_ISR_RX_NOBUF) 1285 printf(" no buffers"); 1286 if (status & VR_ISR_RX_OFLOW) 1287 printf(" overflow"); 1288 if (status & VR_ISR_RX_DROPPED) 1289 printf(" packet lost"); 1290 printf("\n"); 1291 vr_rxeoc(sc); 1292 } 1293 1294 if ((status & VR_ISR_BUSERR) || (status & VR_ISR_TX_UNDERRUN)) { 1295 vr_reset(sc); 1296 vr_init(sc); 1297 break; 1298 } 1299 1300 if ((status & VR_ISR_TX_OK) || (status & VR_ISR_TX_ABRT) || 1301 (status & VR_ISR_TX_ABRT2) || (status & VR_ISR_UDFI)) { 1302 vr_txeof(sc); 1303 if ((status & VR_ISR_UDFI) || 1304 (status & VR_ISR_TX_ABRT2) || 1305 (status & VR_ISR_TX_ABRT)) { 1306 ifp->if_oerrors++; 1307 if (sc->vr_cdata.vr_tx_head != NULL) { 1308 VR_SETBIT16(sc, VR_COMMAND, 1309 VR_CMD_TX_ON); 1310 VR_SETBIT16(sc, VR_COMMAND, 1311 VR_CMD_TX_GO); 1312 } 1313 } else 1314 vr_txeoc(sc); 1315 } 1316 } 1317 1318 /* Re-enable interrupts. */ 1319 CSR_WRITE_2(sc, VR_IMR, VR_INTRS); 1320 1321 if (!IFQ_IS_EMPTY(&ifp->if_snd)) { 1322 vr_start(ifp); 1323 } 1324 1325 return (claimed); 1326 } 1327 1328 /* 1329 * Encapsulate an mbuf chain in a descriptor by coupling the mbuf data 1330 * pointers to the fragment pointers. 1331 */ 1332 int 1333 vr_encap(sc, c, m_head) 1334 struct vr_softc *sc; 1335 struct vr_chain *c; 1336 struct mbuf *m_head; 1337 { 1338 int frag = 0; 1339 struct vr_desc *f = NULL; 1340 int total_len; 1341 struct mbuf *m; 1342 1343 m = m_head; 1344 total_len = 0; 1345 1346 /* 1347 * The VIA Rhine wants packet buffers to be longword 1348 * aligned, but very often our mbufs aren't. Rather than 1349 * waste time trying to decide when to copy and when not 1350 * to copy, just do it all the time. 1351 */ 1352 if (m != NULL) { 1353 struct mbuf *m_new = NULL; 1354 1355 MGETHDR(m_new, M_DONTWAIT, MT_DATA); 1356 if (m_new == NULL) { 1357 return(1); 1358 } 1359 if (m_head->m_pkthdr.len > MHLEN) { 1360 MCLGET(m_new, M_DONTWAIT); 1361 if (!(m_new->m_flags & M_EXT)) { 1362 m_freem(m_new); 1363 return(1); 1364 } 1365 } 1366 m_copydata(m_head, 0, m_head->m_pkthdr.len, 1367 mtod(m_new, caddr_t)); 1368 m_new->m_pkthdr.len = m_new->m_len = m_head->m_pkthdr.len; 1369 m_freem(m_head); 1370 m_head = m_new; 1371 /* 1372 * The Rhine chip doesn't auto-pad, so we have to make 1373 * sure to pad short frames out to the minimum frame length 1374 * ourselves. 1375 */ 1376 if (m_head->m_len < VR_MIN_FRAMELEN) { 1377 /* data field should be padded with octets of zero */ 1378 bzero(&m_new->m_data[m_head->m_len], 1379 VR_MIN_FRAMELEN-m_head->m_len); 1380 m_new->m_pkthdr.len += VR_MIN_FRAMELEN - m_new->m_len; 1381 m_new->m_len = m_new->m_pkthdr.len; 1382 } 1383 f = c->vr_ptr; 1384 f->vr_data = vtophys(mtod(m_new, caddr_t)); 1385 f->vr_ctl = total_len = m_new->m_len; 1386 f->vr_ctl |= VR_TXCTL_TLINK|VR_TXCTL_FIRSTFRAG; 1387 f->vr_status = 0; 1388 frag = 1; 1389 } 1390 1391 c->vr_mbuf = m_head; 1392 c->vr_ptr->vr_ctl |= VR_TXCTL_LASTFRAG|VR_TXCTL_FINT; 1393 c->vr_ptr->vr_next = vtophys(c->vr_nextdesc->vr_ptr); 1394 1395 return(0); 1396 } 1397 1398 /* 1399 * Main transmit routine. To avoid having to do mbuf copies, we put pointers 1400 * to the mbuf data regions directly in the transmit lists. We also save a 1401 * copy of the pointers since the transmit list fragment pointers are 1402 * physical addresses. 1403 */ 1404 1405 void 1406 vr_start(ifp) 1407 struct ifnet *ifp; 1408 { 1409 struct vr_softc *sc; 1410 struct mbuf *m_head = NULL; 1411 struct vr_chain *cur_tx = NULL, *start_tx; 1412 1413 sc = ifp->if_softc; 1414 1415 if (ifp->if_flags & IFF_OACTIVE) 1416 return; 1417 1418 /* 1419 * Check for an available queue slot. If there are none, 1420 * punt. 1421 */ 1422 if (sc->vr_cdata.vr_tx_free->vr_mbuf != NULL) { 1423 ifp->if_flags |= IFF_OACTIVE; 1424 return; 1425 } 1426 1427 start_tx = sc->vr_cdata.vr_tx_free; 1428 1429 while(sc->vr_cdata.vr_tx_free->vr_mbuf == NULL) { 1430 IFQ_DEQUEUE(&ifp->if_snd, m_head); 1431 if (m_head == NULL) 1432 break; 1433 1434 /* Pick a descriptor off the free list. */ 1435 cur_tx = sc->vr_cdata.vr_tx_free; 1436 sc->vr_cdata.vr_tx_free = cur_tx->vr_nextdesc; 1437 1438 /* Pack the data into the descriptor. */ 1439 if (vr_encap(sc, cur_tx, m_head)) { 1440 if (ALTQ_IS_ENABLED(&ifp->if_snd)) { 1441 m_freem(m_head); 1442 } else { 1443 IF_PREPEND(&ifp->if_snd, m_head); 1444 ifp->if_flags |= IFF_OACTIVE; 1445 } 1446 cur_tx = NULL; 1447 break; 1448 } 1449 1450 if (cur_tx != start_tx) 1451 VR_TXOWN(cur_tx) = VR_TXSTAT_OWN; 1452 1453 #if NBPFILTER > 0 1454 /* 1455 * If there's a BPF listener, bounce a copy of this frame 1456 * to him. 1457 */ 1458 if (ifp->if_bpf) 1459 bpf_mtap(ifp->if_bpf, cur_tx->vr_mbuf); 1460 #endif 1461 VR_TXOWN(cur_tx) = VR_TXSTAT_OWN; 1462 VR_SETBIT16(sc, VR_COMMAND, /*VR_CMD_TX_ON|*/VR_CMD_TX_GO); 1463 } 1464 1465 /* 1466 * If there are no frames queued, bail. 1467 */ 1468 if (cur_tx == NULL) 1469 return; 1470 1471 sc->vr_cdata.vr_tx_tail = cur_tx; 1472 1473 if (sc->vr_cdata.vr_tx_head == NULL) 1474 sc->vr_cdata.vr_tx_head = start_tx; 1475 1476 /* 1477 * Set a timeout in case the chip goes out to lunch. 1478 */ 1479 ifp->if_timer = 5; 1480 } 1481 1482 void 1483 vr_init(xsc) 1484 void *xsc; 1485 { 1486 struct vr_softc *sc = xsc; 1487 struct ifnet *ifp = &sc->arpcom.ac_if; 1488 struct mii_data *mii = &sc->sc_mii; 1489 int s, i; 1490 1491 s = splimp(); 1492 1493 /* 1494 * Cancel pending I/O and free all RX/TX buffers. 1495 */ 1496 vr_stop(sc); 1497 vr_reset(sc); 1498 1499 /* 1500 * Set our station address. 1501 */ 1502 for (i = 0; i < ETHER_ADDR_LEN; i++) 1503 CSR_WRITE_1(sc, VR_PAR0 + i, sc->arpcom.ac_enaddr[i]); 1504 1505 /* Set DMA size */ 1506 VR_CLRBIT(sc, VR_BCR0, VR_BCR0_DMA_LENGTH); 1507 VR_SETBIT(sc, VR_BCR0, VR_BCR0_DMA_STORENFWD); 1508 1509 /* 1510 * BCR0 and BCR1 can override the RXCFG and TXCFG registers, 1511 * so we must set both. 1512 */ 1513 VR_CLRBIT(sc, VR_BCR0, VR_BCR0_RX_THRESH); 1514 VR_SETBIT(sc, VR_BCR0, VR_BCR0_RXTHRESH128BYTES); 1515 1516 VR_CLRBIT(sc, VR_BCR1, VR_BCR1_TX_THRESH); 1517 VR_SETBIT(sc, VR_BCR1, VR_BCR1_TXTHRESHSTORENFWD); 1518 1519 VR_CLRBIT(sc, VR_RXCFG, VR_RXCFG_RX_THRESH); 1520 VR_SETBIT(sc, VR_RXCFG, VR_RXTHRESH_128BYTES); 1521 1522 VR_CLRBIT(sc, VR_TXCFG, VR_TXCFG_TX_THRESH); 1523 VR_SETBIT(sc, VR_TXCFG, VR_TXTHRESH_STORENFWD); 1524 1525 /* Init circular RX list. */ 1526 if (vr_list_rx_init(sc) == ENOBUFS) { 1527 printf("%s: initialization failed: no memory for rx buffers\n", 1528 sc->sc_dev.dv_xname); 1529 vr_stop(sc); 1530 splx(s); 1531 return; 1532 } 1533 1534 /* 1535 * Init tx descriptors. 1536 */ 1537 vr_list_tx_init(sc); 1538 1539 /* If we want promiscuous mode, set the allframes bit. */ 1540 if (ifp->if_flags & IFF_PROMISC) 1541 VR_SETBIT(sc, VR_RXCFG, VR_RXCFG_RX_PROMISC); 1542 else 1543 VR_CLRBIT(sc, VR_RXCFG, VR_RXCFG_RX_PROMISC); 1544 1545 /* Set capture broadcast bit to capture broadcast frames. */ 1546 if (ifp->if_flags & IFF_BROADCAST) 1547 VR_SETBIT(sc, VR_RXCFG, VR_RXCFG_RX_BROAD); 1548 else 1549 VR_CLRBIT(sc, VR_RXCFG, VR_RXCFG_RX_BROAD); 1550 1551 /* 1552 * Program the multicast filter, if necessary. 1553 */ 1554 vr_setmulti(sc); 1555 1556 /* 1557 * Load the address of the RX list. 1558 */ 1559 CSR_WRITE_4(sc, VR_RXADDR, vtophys(sc->vr_cdata.vr_rx_head->vr_ptr)); 1560 1561 /* Enable receiver and transmitter. */ 1562 CSR_WRITE_2(sc, VR_COMMAND, VR_CMD_TX_NOPOLL|VR_CMD_START| 1563 VR_CMD_TX_ON|VR_CMD_RX_ON| 1564 VR_CMD_RX_GO); 1565 1566 CSR_WRITE_4(sc, VR_TXADDR, vtophys(&sc->vr_ldata->vr_tx_list[0])); 1567 1568 /* 1569 * Enable interrupts. 1570 */ 1571 CSR_WRITE_2(sc, VR_ISR, 0xFFFF); 1572 CSR_WRITE_2(sc, VR_IMR, VR_INTRS); 1573 1574 /* Restore state of BMCR */ 1575 mii_mediachg(mii); 1576 1577 ifp->if_flags |= IFF_RUNNING; 1578 ifp->if_flags &= ~IFF_OACTIVE; 1579 1580 if (!timeout_pending(&sc->sc_to)) 1581 timeout_add(&sc->sc_to, hz); 1582 1583 splx(s); 1584 } 1585 1586 /* 1587 * Set media options. 1588 */ 1589 int 1590 vr_ifmedia_upd(ifp) 1591 struct ifnet *ifp; 1592 { 1593 struct vr_softc *sc = ifp->if_softc; 1594 1595 if (ifp->if_flags & IFF_UP) 1596 vr_init(sc); 1597 1598 return(0); 1599 } 1600 1601 /* 1602 * Report current media status. 1603 */ 1604 void 1605 vr_ifmedia_sts(ifp, ifmr) 1606 struct ifnet *ifp; 1607 struct ifmediareq *ifmr; 1608 { 1609 struct vr_softc *sc = ifp->if_softc; 1610 struct mii_data *mii = &sc->sc_mii; 1611 1612 mii_pollstat(mii); 1613 ifmr->ifm_active = mii->mii_media_active; 1614 ifmr->ifm_status = mii->mii_media_status; 1615 } 1616 1617 int 1618 vr_ioctl(ifp, command, data) 1619 struct ifnet *ifp; 1620 u_long command; 1621 caddr_t data; 1622 { 1623 struct vr_softc *sc = ifp->if_softc; 1624 struct ifreq *ifr = (struct ifreq *) data; 1625 int s, error = 0; 1626 struct ifaddr *ifa = (struct ifaddr *)data; 1627 1628 s = splimp(); 1629 1630 if ((error = ether_ioctl(ifp, &sc->arpcom, command, data)) > 0) { 1631 splx(s); 1632 return error; 1633 } 1634 1635 switch(command) { 1636 case SIOCSIFADDR: 1637 ifp->if_flags |= IFF_UP; 1638 switch (ifa->ifa_addr->sa_family) { 1639 #ifdef INET 1640 case AF_INET: 1641 vr_init(sc); 1642 arp_ifinit(&sc->arpcom, ifa); 1643 break; 1644 #endif /* INET */ 1645 default: 1646 vr_init(sc); 1647 break; 1648 } 1649 break; 1650 case SIOCSIFFLAGS: 1651 if (ifp->if_flags & IFF_UP) { 1652 vr_init(sc); 1653 } else { 1654 if (ifp->if_flags & IFF_RUNNING) 1655 vr_stop(sc); 1656 } 1657 error = 0; 1658 break; 1659 case SIOCADDMULTI: 1660 case SIOCDELMULTI: 1661 error = (command == SIOCADDMULTI) ? 1662 ether_addmulti(ifr, &sc->arpcom) : 1663 ether_delmulti(ifr, &sc->arpcom); 1664 1665 if (error == ENETRESET) { 1666 /* 1667 * Multicast list has changed; set the hardware 1668 * filter accordingly. 1669 */ 1670 vr_setmulti(sc); 1671 error = 0; 1672 } 1673 break; 1674 case SIOCGIFMEDIA: 1675 case SIOCSIFMEDIA: 1676 error = ifmedia_ioctl(ifp, ifr, &sc->sc_mii.mii_media, command); 1677 break; 1678 default: 1679 error = EINVAL; 1680 break; 1681 } 1682 1683 splx(s); 1684 1685 return(error); 1686 } 1687 1688 void 1689 vr_watchdog(ifp) 1690 struct ifnet *ifp; 1691 { 1692 struct vr_softc *sc; 1693 1694 sc = ifp->if_softc; 1695 1696 ifp->if_oerrors++; 1697 printf("%s: watchdog timeout\n", sc->sc_dev.dv_xname); 1698 1699 vr_stop(sc); 1700 vr_reset(sc); 1701 vr_init(sc); 1702 1703 if (!IFQ_IS_EMPTY(&ifp->if_snd)) 1704 vr_start(ifp); 1705 1706 return; 1707 } 1708 1709 /* 1710 * Stop the adapter and free any mbufs allocated to the 1711 * RX and TX lists. 1712 */ 1713 void 1714 vr_stop(sc) 1715 struct vr_softc *sc; 1716 { 1717 register int i; 1718 struct ifnet *ifp; 1719 1720 ifp = &sc->arpcom.ac_if; 1721 ifp->if_timer = 0; 1722 1723 if (timeout_pending(&sc->sc_to)) 1724 timeout_del(&sc->sc_to); 1725 1726 VR_SETBIT16(sc, VR_COMMAND, VR_CMD_STOP); 1727 VR_CLRBIT16(sc, VR_COMMAND, (VR_CMD_RX_ON|VR_CMD_TX_ON)); 1728 CSR_WRITE_2(sc, VR_IMR, 0x0000); 1729 CSR_WRITE_4(sc, VR_TXADDR, 0x00000000); 1730 CSR_WRITE_4(sc, VR_RXADDR, 0x00000000); 1731 1732 /* 1733 * Free data in the RX lists. 1734 */ 1735 for (i = 0; i < VR_RX_LIST_CNT; i++) { 1736 if (sc->vr_cdata.vr_rx_chain[i].vr_mbuf != NULL) { 1737 m_freem(sc->vr_cdata.vr_rx_chain[i].vr_mbuf); 1738 sc->vr_cdata.vr_rx_chain[i].vr_mbuf = NULL; 1739 } 1740 } 1741 bzero((char *)&sc->vr_ldata->vr_rx_list, 1742 sizeof(sc->vr_ldata->vr_rx_list)); 1743 1744 /* 1745 * Free the TX list buffers. 1746 */ 1747 for (i = 0; i < VR_TX_LIST_CNT; i++) { 1748 if (sc->vr_cdata.vr_tx_chain[i].vr_mbuf != NULL) { 1749 m_freem(sc->vr_cdata.vr_tx_chain[i].vr_mbuf); 1750 sc->vr_cdata.vr_tx_chain[i].vr_mbuf = NULL; 1751 } 1752 } 1753 1754 bzero((char *)&sc->vr_ldata->vr_tx_list, 1755 sizeof(sc->vr_ldata->vr_tx_list)); 1756 1757 ifp->if_flags &= ~(IFF_RUNNING | IFF_OACTIVE); 1758 1759 return; 1760 } 1761 1762 /* 1763 * Stop all chip I/O so that the kernel's probe routines don't 1764 * get confused by errant DMAs when rebooting. 1765 */ 1766 void 1767 vr_shutdown(arg) 1768 void *arg; 1769 { 1770 struct vr_softc *sc = (struct vr_softc *)arg; 1771 1772 vr_stop(sc); 1773 } 1774