1 /* $OpenBSD: if_vmxreg.h,v 1.3 2013/08/28 10:19:19 reyk Exp $ */ 2 3 /* 4 * Copyright (c) 2013 Tsubai Masanari 5 * 6 * Permission to use, copy, modify, and distribute this software for any 7 * purpose with or without fee is hereby granted, provided that the above 8 * copyright notice and this permission notice appear in all copies. 9 * 10 * THE SOFTWARE IS PROVIDED "AS IS" AND THE AUTHOR DISCLAIMS ALL WARRANTIES 11 * WITH REGARD TO THIS SOFTWARE INCLUDING ALL IMPLIED WARRANTIES OF 12 * MERCHANTABILITY AND FITNESS. IN NO EVENT SHALL THE AUTHOR BE LIABLE FOR 13 * ANY SPECIAL, DIRECT, INDIRECT, OR CONSEQUENTIAL DAMAGES OR ANY DAMAGES 14 * WHATSOEVER RESULTING FROM LOSS OF USE, DATA OR PROFITS, WHETHER IN AN 15 * ACTION OF CONTRACT, NEGLIGENCE OR OTHER TORTIOUS ACTION, ARISING OUT OF 16 * OR IN CONNECTION WITH THE USE OR PERFORMANCE OF THIS SOFTWARE. 17 */ 18 19 struct UPT1_TxStats { 20 u_int64_t TSO_packets; 21 u_int64_t TSO_bytes; 22 u_int64_t ucast_packets; 23 u_int64_t ucast_bytes; 24 u_int64_t mcast_packets; 25 u_int64_t mcast_bytes; 26 u_int64_t bcast_packets; 27 u_int64_t bcast_bytes; 28 u_int64_t error; 29 u_int64_t discard; 30 } __packed; 31 32 struct UPT1_RxStats { 33 u_int64_t LRO_packets; 34 u_int64_t LRO_bytes; 35 u_int64_t ucast_packets; 36 u_int64_t ucast_bytes; 37 u_int64_t mcast_packets; 38 u_int64_t mcast_bytes; 39 u_int64_t bcast_packets; 40 u_int64_t bcast_bytes; 41 u_int64_t nobuffer; 42 u_int64_t error; 43 } __packed; 44 45 /* interrupt moderation levels */ 46 #define UPT1_IMOD_NONE 0 /* no moderation */ 47 #define UPT1_IMOD_HIGHEST 7 /* least interrupts */ 48 #define UPT1_IMOD_ADAPTIVE 8 /* adaptive interrupt moderation */ 49 50 /* hardware features */ 51 #define UPT1_F_CSUM 0x0001 /* Rx checksum verification */ 52 #define UPT1_F_RSS 0x0002 /* receive side scaling */ 53 #define UPT1_F_VLAN 0x0004 /* VLAN tag stripping */ 54 #define UPT1_F_LRO 0x0008 /* large receive offloading */ 55 56 #define VMXNET3_BAR0_IMASK(irq) (0x000 + (irq) * 8) /* interrupt mask */ 57 #define VMXNET3_BAR0_TXH(q) (0x600 + (q) * 8) /* Tx head */ 58 #define VMXNET3_BAR0_RXH1(q) (0x800 + (q) * 8) /* ring1 Rx head */ 59 #define VMXNET3_BAR0_RXH2(q) (0xa00 + (q) * 8) /* ring2 Rx head */ 60 #define VMXNET3_BAR1_VRRS 0x000 /* VMXNET3 revision report selection */ 61 #define VMXNET3_BAR1_UVRS 0x008 /* UPT version report selection */ 62 #define VMXNET3_BAR1_DSL 0x010 /* driver shared address low */ 63 #define VMXNET3_BAR1_DSH 0x018 /* driver shared address high */ 64 #define VMXNET3_BAR1_CMD 0x020 /* command */ 65 #define VMXNET3_BAR1_MACL 0x028 /* MAC address low */ 66 #define VMXNET3_BAR1_MACH 0x030 /* MAC address high */ 67 #define VMXNET3_BAR1_INTR 0x038 /* interrupt status */ 68 #define VMXNET3_BAR1_EVENT 0x040 /* event status */ 69 70 #define VMXNET3_CMD_ENABLE 0xcafe0000 /* enable VMXNET3 */ 71 #define VMXNET3_CMD_DISABLE 0xcafe0001 /* disable VMXNET3 */ 72 #define VMXNET3_CMD_RESET 0xcafe0002 /* reset device */ 73 #define VMXNET3_CMD_SET_RXMODE 0xcafe0003 /* set interface flags */ 74 #define VMXNET3_CMD_SET_FILTER 0xcafe0004 /* set address filter */ 75 #define VMXNET3_CMD_GET_STATUS 0xf00d0000 /* get queue errors */ 76 #define VMXNET3_CMD_GET_LINK 0xf00d0002 /* get link status */ 77 #define VMXNET3_CMD_GET_MACL 0xf00d0003 78 #define VMXNET3_CMD_GET_MACH 0xf00d0004 79 80 #define VMXNET3_DMADESC_ALIGN 128 81 82 /* All descriptors are in little-endian format. */ 83 struct vmxnet3_txdesc { 84 u_int64_t tx_addr; 85 86 u_int32_t tx_word2; 87 #define VMXNET3_TX_LEN_M 0x00003fff 88 #define VMXNET3_TX_LEN_S 0 89 #define VMXNET3_TX_GEN_M 0x00000001 /* generation */ 90 #define VMXNET3_TX_GEN_S 14 91 #define VMXNET3_TX_RES0 0x00008000 92 #define VMXNET3_TX_DTYPE_M 0x00000001 /* descriptor type */ 93 #define VMXNET3_TX_DTYPE_S 16 /* descriptor type */ 94 #define VMXNET3_TX_RES1 0x00000002 95 #define VMXNET3_TX_OP_M 0x00003fff /* offloading position */ 96 #define VMXNET3_TX_OP_S 18 97 98 u_int32_t tx_word3; 99 #define VMXNET3_TX_HLEN_M 0x000003ff /* header len */ 100 #define VMXNET3_TX_HLEN_S 0 101 #define VMXNET3_TX_OM_M 0x00000003 /* offloading mode */ 102 #define VMXNET3_TX_OM_S 10 103 #define VMXNET3_TX_EOP 0x00001000 /* end of packet */ 104 #define VMXNET3_TX_COMPREQ 0x00002000 /* completion request */ 105 #define VMXNET3_TX_RES2 0x00004000 106 #define VMXNET3_TX_VTAG_MODE 0x00008000 /* VLAN tag insertion mode */ 107 #define VMXNET3_TX_VLANTAG_M 0x0000ffff 108 #define VMXNET3_TX_VLANTAG_S 16 109 } __packed; 110 111 /* offloading modes */ 112 #define VMXNET3_OM_NONE 0 113 #define VMXNET3_OM_CSUM 2 114 #define VMXNET3_OM_TSO 3 115 116 struct vmxnet3_txcompdesc { 117 u_int32_t txc_word0; 118 #define VMXNET3_TXC_EOPIDX_M 0x00000fff /* eop index in Tx ring */ 119 #define VMXNET3_TXC_EOPIDX_S 0 120 #define VMXNET3_TXC_RES0_M 0x000fffff 121 #define VMXNET3_TXC_RES0_S 12 122 123 u_int32_t txc_word1; 124 u_int32_t txc_word2; 125 126 u_int32_t txc_word3; 127 #define VMXNET3_TXC_RES2_M 0x00ffffff 128 #define VMXNET3_TXC_TYPE_M 0x0000007f 129 #define VMXNET3_TXC_TYPE_S 24 130 #define VMXNET3_TXC_GEN_M 0x00000001 131 #define VMXNET3_TXC_GEN_S 31 132 } __packed; 133 134 struct vmxnet3_rxdesc { 135 u_int64_t rx_addr; 136 137 u_int32_t rx_word2; 138 #define VMXNET3_RX_LEN_M 0x00003fff 139 #define VMXNET3_RX_LEN_S 0 140 #define VMXNET3_RX_BTYPE_M 0x00000001 /* buffer type */ 141 #define VMXNET3_RX_BTYPE_S 14 142 #define VMXNET3_RX_DTYPE_M 0x00000001 /* descriptor type */ 143 #define VMXNET3_RX_DTYPE_S 15 144 #define VMXNET3_RX_RES0_M 0x00007fff 145 #define VMXNET3_RX_RES0_S 16 146 #define VMXNET3_RX_GEN_M 0x00000001 147 #define VMXNET3_RX_GEN_S 31 148 149 u_int32_t rx_word3; 150 } __packed; 151 152 /* buffer types */ 153 #define VMXNET3_BTYPE_HEAD 0 /* head only */ 154 #define VMXNET3_BTYPE_BODY 1 /* body only */ 155 156 struct vmxnet3_rxcompdesc { 157 u_int32_t rxc_word0; 158 #define VMXNET3_RXC_IDX_M 0x00000fff /* Rx descriptor index */ 159 #define VMXNET3_RXC_IDX_S 0 160 #define VMXNET3_RXC_RES0_M 0x00000003 161 #define VMXNET3_RXC_RES0_S 12 162 #define VMXNET3_RXC_EOP 0x00004000 /* end of packet */ 163 #define VMXNET3_RXC_SOP 0x00008000 /* start of packet */ 164 #define VMXNET3_RXC_QID_M 0x000003ff 165 #define VMXNET3_RXC_QID_S 16 166 #define VMXNET3_RXC_RSSTYPE_M 0x0000000f 167 #define VMXNET3_RXC_RSSTYPE_S 26 168 #define VMXNET3_RXC_NOCSUM 0x40000000 /* no checksum calculated */ 169 #define VMXNET3_RXC_RES1 0x80000000 170 171 u_int32_t rxc_word1; 172 #define VMXNET3_RXC_RSSHASH_M 0xffffffff /* RSS hash value */ 173 #define VMXNET3_RXC_RSSHASH_S 0 174 175 u_int32_t rxc_word2; 176 #define VMXNET3_RXC_LEN_M 0x00003fff 177 #define VMXNET3_RXC_LEN_S 0 178 #define VMXNET3_RXC_ERROR 0x00004000 179 #define VMXNET3_RXC_VLAN 0x00008000 /* 802.1Q VLAN frame */ 180 #define VMXNET3_RXC_VLANTAG_M 0x0000ffff /* VLAN tag */ 181 #define VMXNET3_RXC_VLANTAG_S 16 182 183 u_int32_t rxc_word3; 184 #define VMXNET3_RXC_CSUM_M 0x0000ffff /* TCP/UDP checksum */ 185 #define VMXNET3_RXC_CSUM_S 16 186 #define VMXNET3_RXC_CSUM_OK 0x00010000 /* TCP/UDP checksum ok */ 187 #define VMXNET3_RXC_UDP 0x00020000 188 #define VMXNET3_RXC_TCP 0x00040000 189 #define VMXNET3_RXC_IPSUM_OK 0x00080000 /* IP checksum ok */ 190 #define VMXNET3_RXC_IPV6 0x00100000 191 #define VMXNET3_RXC_IPV4 0x00200000 192 #define VMXNET3_RXC_FRAGMENT 0x00400000 /* IP fragment */ 193 #define VMXNET3_RXC_FCS 0x00800000 /* frame CRC correct */ 194 #define VMXNET3_RXC_TYPE_M 0x7f000000 195 #define VMXNET3_RXC_GEN_M 0x00000001 196 #define VMXNET3_RXC_GEN_S 31 197 } __packed; 198 199 #define VMXNET3_REV1_MAGIC 0xbabefee1 200 201 #define VMXNET3_GOS_UNKNOWN 0x00 202 #define VMXNET3_GOS_LINUX 0x04 203 #define VMXNET3_GOS_WINDOWS 0x08 204 #define VMXNET3_GOS_SOLARIS 0x0c 205 #define VMXNET3_GOS_FREEBSD 0x10 206 #define VMXNET3_GOS_PXE 0x14 207 208 #define VMXNET3_GOS_32BIT 0x01 209 #define VMXNET3_GOS_64BIT 0x02 210 211 #define VMXNET3_MAX_TX_QUEUES 8 212 #define VMXNET3_MAX_RX_QUEUES 16 213 #define VMXNET3_MAX_INTRS (VMXNET3_MAX_TX_QUEUES + VMXNET3_MAX_RX_QUEUES + 1) 214 #define VMXNET3_NINTR 1 215 216 #define VMXNET3_ICTRL_DISABLE_ALL 0x01 217 218 #define VMXNET3_RXMODE_UCAST 0x01 219 #define VMXNET3_RXMODE_MCAST 0x02 220 #define VMXNET3_RXMODE_BCAST 0x04 221 #define VMXNET3_RXMODE_ALLMULTI 0x08 222 #define VMXNET3_RXMODE_PROMISC 0x10 223 224 #define VMXNET3_EVENT_RQERROR 0x01 225 #define VMXNET3_EVENT_TQERROR 0x02 226 #define VMXNET3_EVENT_LINK 0x04 227 #define VMXNET3_EVENT_DIC 0x08 228 #define VMXNET3_EVENT_DEBUG 0x10 229 230 #define VMXNET3_MAX_MTU 9000 231 #define VMXNET3_MIN_MTU 60 232 233 struct vmxnet3_driver_shared { 234 u_int32_t magic; 235 u_int32_t pad1; 236 237 u_int32_t version; /* driver version */ 238 u_int32_t guest; /* guest OS */ 239 u_int32_t vmxnet3_revision; /* supported VMXNET3 revision */ 240 u_int32_t upt_version; /* supported UPT version */ 241 u_int64_t upt_features; 242 u_int64_t driver_data; 243 u_int64_t queue_shared; 244 u_int32_t driver_data_len; 245 u_int32_t queue_shared_len; 246 u_int32_t mtu; 247 u_int16_t nrxsg_max; 248 u_int8_t ntxqueue; 249 u_int8_t nrxqueue; 250 u_int32_t reserved1[4]; 251 252 /* interrupt control */ 253 u_int8_t automask; 254 u_int8_t nintr; 255 u_int8_t evintr; 256 u_int8_t modlevel[VMXNET3_MAX_INTRS]; 257 u_int32_t ictrl; 258 u_int32_t reserved2[2]; 259 260 /* receive filter parameters */ 261 u_int32_t rxmode; 262 u_int16_t mcast_tablelen; 263 u_int16_t pad2; 264 u_int64_t mcast_table; 265 u_int32_t vlan_filter[4096 / 32]; 266 267 struct { 268 u_int32_t version; 269 u_int32_t len; 270 u_int64_t paddr; 271 } rss, pm, plugin; 272 273 u_int32_t event; 274 u_int32_t reserved3[5]; 275 } __packed; 276 277 struct vmxnet3_txq_shared { 278 u_int32_t npending; 279 u_int32_t intr_threshold; 280 u_int64_t reserved1; 281 282 u_int64_t cmd_ring; 283 u_int64_t data_ring; 284 u_int64_t comp_ring; 285 u_int64_t driver_data; 286 u_int64_t reserved2; 287 u_int32_t cmd_ring_len; 288 u_int32_t data_ring_len; 289 u_int32_t comp_ring_len; 290 u_int32_t driver_data_len; 291 u_int8_t intr_idx; 292 u_int8_t pad1[7]; 293 294 u_int8_t stopped; 295 u_int8_t pad2[3]; 296 u_int32_t error; 297 298 struct UPT1_TxStats stats; 299 300 u_int8_t pad3[88]; 301 } __packed; 302 303 struct vmxnet3_rxq_shared { 304 u_int8_t update_rxhead; 305 u_int8_t pad1[7]; 306 u_int64_t reserved1; 307 308 u_int64_t cmd_ring[2]; 309 u_int64_t comp_ring; 310 u_int64_t driver_data; 311 u_int64_t reserved2; 312 u_int32_t cmd_ring_len[2]; 313 u_int32_t comp_ring_len; 314 u_int32_t driver_data_len; 315 u_int8_t intr_idx; 316 u_int8_t pad2[7]; 317 318 u_int8_t stopped; 319 u_int8_t pad3[3]; 320 u_int32_t error; 321 322 struct UPT1_RxStats stats; 323 324 u_int8_t pad4[88]; 325 } __packed; 326