1 /* $OpenBSD: if_vic.c,v 1.81 2014/07/13 23:10:23 deraadt Exp $ */ 2 3 /* 4 * Copyright (c) 2006 Reyk Floeter <reyk@openbsd.org> 5 * Copyright (c) 2006 David Gwynne <dlg@openbsd.org> 6 * 7 * Permission to use, copy, modify, and distribute this software for any 8 * purpose with or without fee is hereby granted, provided that the above 9 * copyright notice and this permission notice appear in all copies. 10 * 11 * THE SOFTWARE IS PROVIDED "AS IS" AND THE AUTHOR DISCLAIMS ALL WARRANTIES 12 * WITH REGARD TO THIS SOFTWARE INCLUDING ALL IMPLIED WARRANTIES OF 13 * MERCHANTABILITY AND FITNESS. IN NO EVENT SHALL THE AUTHOR BE LIABLE FOR 14 * ANY SPECIAL, DIRECT, INDIRECT, OR CONSEQUENTIAL DAMAGES OR ANY DAMAGES 15 * WHATSOEVER RESULTING FROM LOSS OF USE, DATA OR PROFITS, WHETHER IN AN 16 * ACTION OF CONTRACT, NEGLIGENCE OR OTHER TORTIOUS ACTION, ARISING OUT OF 17 * OR IN CONNECTION WITH THE USE OR PERFORMANCE OF THIS SOFTWARE. 18 */ 19 20 /* 21 * Driver for the VMware Virtual NIC ("vmxnet") 22 */ 23 24 #include "bpfilter.h" 25 26 #include <sys/param.h> 27 #include <sys/systm.h> 28 #include <sys/sockio.h> 29 #include <sys/mbuf.h> 30 #include <sys/kernel.h> 31 #include <sys/socket.h> 32 #include <sys/malloc.h> 33 #include <sys/timeout.h> 34 #include <sys/device.h> 35 36 #include <machine/bus.h> 37 #include <machine/intr.h> 38 39 #include <net/if.h> 40 #include <net/if_dl.h> 41 #include <net/if_media.h> 42 #include <net/if_types.h> 43 44 #if NBPFILTER > 0 45 #include <net/bpf.h> 46 #endif 47 48 #ifdef INET 49 #include <netinet/in.h> 50 #include <netinet/if_ether.h> 51 #endif 52 53 #include <dev/pci/pcireg.h> 54 #include <dev/pci/pcivar.h> 55 #include <dev/pci/pcidevs.h> 56 57 #define VIC_PCI_BAR PCI_MAPREG_START /* Base Address Register */ 58 59 #define VIC_LANCE_SIZE 0x20 60 #define VIC_MORPH_SIZE 0x04 61 #define VIC_MORPH_MASK 0xffff 62 #define VIC_MORPH_LANCE 0x2934 63 #define VIC_MORPH_VMXNET 0x4392 64 #define VIC_VMXNET_SIZE 0x40 65 #define VIC_LANCE_MINLEN (VIC_LANCE_SIZE + VIC_MORPH_SIZE + \ 66 VIC_VMXNET_SIZE) 67 68 #define VIC_MAGIC 0xbabe864f 69 70 /* Register address offsets */ 71 #define VIC_DATA_ADDR 0x0000 /* Shared data address */ 72 #define VIC_DATA_LENGTH 0x0004 /* Shared data length */ 73 #define VIC_Tx_ADDR 0x0008 /* Tx pointer address */ 74 75 /* Command register */ 76 #define VIC_CMD 0x000c /* Command register */ 77 #define VIC_CMD_INTR_ACK 0x0001 /* Acknowledge interrupt */ 78 #define VIC_CMD_MCASTFIL 0x0002 /* Multicast address filter */ 79 #define VIC_CMD_MCASTFIL_LENGTH 2 80 #define VIC_CMD_IFF 0x0004 /* Interface flags */ 81 #define VIC_CMD_IFF_PROMISC 0x0001 /* Promiscous enabled */ 82 #define VIC_CMD_IFF_BROADCAST 0x0002 /* Broadcast enabled */ 83 #define VIC_CMD_IFF_MULTICAST 0x0004 /* Multicast enabled */ 84 #define VIC_CMD_INTR_DISABLE 0x0020 /* Enable interrupts */ 85 #define VIC_CMD_INTR_ENABLE 0x0040 /* Disable interrupts */ 86 #define VIC_CMD_Tx_DONE 0x0100 /* Tx done register */ 87 #define VIC_CMD_NUM_Rx_BUF 0x0200 /* Number of Rx buffers */ 88 #define VIC_CMD_NUM_Tx_BUF 0x0400 /* Number of Tx buffers */ 89 #define VIC_CMD_NUM_PINNED_BUF 0x0800 /* Number of pinned buffers */ 90 #define VIC_CMD_HWCAP 0x1000 /* Capability register */ 91 #define VIC_CMD_HWCAP_SG (1<<0) /* Scatter-gather transmits */ 92 #define VIC_CMD_HWCAP_CSUM_IPv4 (1<<1) /* TCP/UDP cksum */ 93 #define VIC_CMD_HWCAP_CSUM_ALL (1<<3) /* Hardware cksum */ 94 #define VIC_CMD_HWCAP_CSUM \ 95 (VIC_CMD_HWCAP_CSUM_IPv4 | VIC_CMD_HWCAP_CSUM_ALL) 96 #define VIC_CMD_HWCAP_DMA_HIGH (1<<4) /* High DMA mapping */ 97 #define VIC_CMD_HWCAP_TOE (1<<5) /* TCP offload engine */ 98 #define VIC_CMD_HWCAP_TSO (1<<6) /* TCP segmentation offload */ 99 #define VIC_CMD_HWCAP_TSO_SW (1<<7) /* Software TCP segmentation */ 100 #define VIC_CMD_HWCAP_VPROM (1<<8) /* Virtual PROM available */ 101 #define VIC_CMD_HWCAP_VLAN_Tx (1<<9) /* Hardware VLAN MTU Rx */ 102 #define VIC_CMD_HWCAP_VLAN_Rx (1<<10) /* Hardware VLAN MTU Tx */ 103 #define VIC_CMD_HWCAP_VLAN_SW (1<<11) /* Software VLAN MTU */ 104 #define VIC_CMD_HWCAP_VLAN \ 105 (VIC_CMD_HWCAP_VLAN_Tx | VIC_CMD_HWCAP_VLAN_Rx | \ 106 VIC_CMD_HWCAP_VLAN_SW) 107 #define VIC_CMD_HWCAP_BITS \ 108 "\20\01SG\02CSUM4\03CSUM\04HDMA\05TOE\06TSO" \ 109 "\07TSOSW\10VPROM\13VLANTx\14VLANRx\15VLANSW" 110 #define VIC_CMD_FEATURE 0x2000 /* Additional feature register */ 111 #define VIC_CMD_FEATURE_0_Tx (1<<0) 112 #define VIC_CMD_FEATURE_TSO (1<<1) 113 114 #define VIC_LLADDR 0x0010 /* MAC address register */ 115 #define VIC_VERSION_MINOR 0x0018 /* Minor version register */ 116 #define VIC_VERSION_MAJOR 0x001c /* Major version register */ 117 #define VIC_VERSION_MAJOR_M 0xffff0000 118 119 /* Status register */ 120 #define VIC_STATUS 0x0020 121 #define VIC_STATUS_CONNECTED (1<<0) 122 #define VIC_STATUS_ENABLED (1<<1) 123 124 #define VIC_TOE_ADDR 0x0024 /* TCP offload address */ 125 126 /* Virtual PROM address */ 127 #define VIC_VPROM 0x0028 128 #define VIC_VPROM_LENGTH 6 129 130 /* Shared DMA data structures */ 131 132 struct vic_sg { 133 u_int32_t sg_addr_low; 134 u_int16_t sg_addr_high; 135 u_int16_t sg_length; 136 } __packed; 137 138 #define VIC_SG_MAX 6 139 #define VIC_SG_ADDR_MACH 0 140 #define VIC_SG_ADDR_PHYS 1 141 #define VIC_SG_ADDR_VIRT 3 142 143 struct vic_sgarray { 144 u_int16_t sa_addr_type; 145 u_int16_t sa_length; 146 struct vic_sg sa_sg[VIC_SG_MAX]; 147 } __packed; 148 149 struct vic_rxdesc { 150 u_int64_t rx_physaddr; 151 u_int32_t rx_buflength; 152 u_int32_t rx_length; 153 u_int16_t rx_owner; 154 u_int16_t rx_flags; 155 u_int32_t rx_priv; 156 } __packed; 157 158 #define VIC_RX_FLAGS_CSUMHW_OK 0x0001 159 160 struct vic_txdesc { 161 u_int16_t tx_flags; 162 u_int16_t tx_owner; 163 u_int32_t tx_priv; 164 u_int32_t tx_tsomss; 165 struct vic_sgarray tx_sa; 166 } __packed; 167 168 #define VIC_TX_FLAGS_KEEP 0x0001 169 #define VIC_TX_FLAGS_TXURN 0x0002 170 #define VIC_TX_FLAGS_CSUMHW 0x0004 171 #define VIC_TX_FLAGS_TSO 0x0008 172 #define VIC_TX_FLAGS_PINNED 0x0010 173 #define VIC_TX_FLAGS_QRETRY 0x1000 174 175 struct vic_stats { 176 u_int32_t vs_tx_count; 177 u_int32_t vs_tx_packets; 178 u_int32_t vs_tx_0copy; 179 u_int32_t vs_tx_copy; 180 u_int32_t vs_tx_maxpending; 181 u_int32_t vs_tx_stopped; 182 u_int32_t vs_tx_overrun; 183 u_int32_t vs_intr; 184 u_int32_t vs_rx_packets; 185 u_int32_t vs_rx_underrun; 186 } __packed; 187 188 #define VIC_NRXRINGS 2 189 190 struct vic_data { 191 u_int32_t vd_magic; 192 193 struct { 194 u_int32_t length; 195 u_int32_t nextidx; 196 } vd_rx[VIC_NRXRINGS]; 197 198 u_int32_t vd_irq; 199 u_int32_t vd_iff; 200 201 u_int32_t vd_mcastfil[VIC_CMD_MCASTFIL_LENGTH]; 202 203 u_int32_t vd_reserved1[1]; 204 205 u_int32_t vd_tx_length; 206 u_int32_t vd_tx_curidx; 207 u_int32_t vd_tx_nextidx; 208 u_int32_t vd_tx_stopped; 209 u_int32_t vd_tx_triggerlvl; 210 u_int32_t vd_tx_queued; 211 u_int32_t vd_tx_minlength; 212 213 u_int32_t vd_reserved2[6]; 214 215 u_int32_t vd_rx_saved_nextidx[VIC_NRXRINGS]; 216 u_int32_t vd_tx_saved_nextidx; 217 218 u_int32_t vd_length; 219 u_int32_t vd_rx_offset[VIC_NRXRINGS]; 220 u_int32_t vd_tx_offset; 221 u_int32_t vd_debug; 222 u_int32_t vd_tx_physaddr; 223 u_int32_t vd_tx_physaddr_length; 224 u_int32_t vd_tx_maxlength; 225 226 struct vic_stats vd_stats; 227 } __packed; 228 229 #define VIC_OWNER_DRIVER 0 230 #define VIC_OWNER_DRIVER_PEND 1 231 #define VIC_OWNER_NIC 2 232 #define VIC_OWNER_NIC_PEND 3 233 234 #define VIC_JUMBO_FRAMELEN 9018 235 #define VIC_JUMBO_MTU (VIC_JUMBO_FRAMELEN - ETHER_HDR_LEN - ETHER_CRC_LEN) 236 237 #define VIC_NBUF 100 238 #define VIC_NBUF_MAX 128 239 #define VIC_MAX_SCATTER 1 /* 8? */ 240 #define VIC_QUEUE_SIZE VIC_NBUF_MAX 241 #define VIC_INC(_x, _y) (_x) = ((_x) + 1) % (_y) 242 #define VIC_TX_TIMEOUT 5 243 244 #define VIC_MIN_FRAMELEN (ETHER_MIN_LEN - ETHER_CRC_LEN) 245 246 #define VIC_TXURN_WARN(_sc) ((_sc)->sc_txpending >= ((_sc)->sc_ntxbuf - 5)) 247 #define VIC_TXURN(_sc) ((_sc)->sc_txpending >= (_sc)->sc_ntxbuf) 248 249 struct vic_rxbuf { 250 bus_dmamap_t rxb_dmamap; 251 struct mbuf *rxb_m; 252 }; 253 254 struct vic_txbuf { 255 bus_dmamap_t txb_dmamap; 256 struct mbuf *txb_m; 257 }; 258 259 struct vic_softc { 260 struct device sc_dev; 261 262 pci_chipset_tag_t sc_pc; 263 pcitag_t sc_tag; 264 265 bus_space_tag_t sc_iot; 266 bus_space_handle_t sc_ioh; 267 bus_size_t sc_ios; 268 bus_dma_tag_t sc_dmat; 269 270 void *sc_ih; 271 272 struct timeout sc_tick; 273 274 struct arpcom sc_ac; 275 struct ifmedia sc_media; 276 277 u_int32_t sc_nrxbuf; 278 u_int32_t sc_ntxbuf; 279 u_int32_t sc_cap; 280 u_int32_t sc_feature; 281 u_int8_t sc_lladdr[ETHER_ADDR_LEN]; 282 283 bus_dmamap_t sc_dma_map; 284 bus_dma_segment_t sc_dma_seg; 285 size_t sc_dma_size; 286 caddr_t sc_dma_kva; 287 #define VIC_DMA_DVA(_sc) ((_sc)->sc_dma_map->dm_segs[0].ds_addr) 288 #define VIC_DMA_KVA(_sc) ((void *)(_sc)->sc_dma_kva) 289 290 struct vic_data *sc_data; 291 292 struct { 293 struct if_rxring ring; 294 struct vic_rxbuf *bufs; 295 struct vic_rxdesc *slots; 296 int end; 297 u_int pktlen; 298 } sc_rxq[VIC_NRXRINGS]; 299 300 struct vic_txbuf *sc_txbuf; 301 struct vic_txdesc *sc_txq; 302 volatile u_int sc_txpending; 303 }; 304 305 struct cfdriver vic_cd = { 306 NULL, "vic", DV_IFNET 307 }; 308 309 int vic_match(struct device *, void *, void *); 310 void vic_attach(struct device *, struct device *, void *); 311 312 struct cfattach vic_ca = { 313 sizeof(struct vic_softc), vic_match, vic_attach 314 }; 315 316 int vic_intr(void *); 317 318 int vic_query(struct vic_softc *); 319 int vic_alloc_data(struct vic_softc *); 320 int vic_init_data(struct vic_softc *sc); 321 int vic_uninit_data(struct vic_softc *sc); 322 323 u_int32_t vic_read(struct vic_softc *, bus_size_t); 324 void vic_write(struct vic_softc *, bus_size_t, u_int32_t); 325 326 u_int32_t vic_read_cmd(struct vic_softc *, u_int32_t); 327 328 int vic_alloc_dmamem(struct vic_softc *); 329 void vic_free_dmamem(struct vic_softc *); 330 331 void vic_link_state(struct vic_softc *); 332 void vic_rx_fill(struct vic_softc *, int); 333 void vic_rx_proc(struct vic_softc *, int); 334 void vic_tx_proc(struct vic_softc *); 335 void vic_iff(struct vic_softc *); 336 void vic_getlladdr(struct vic_softc *); 337 void vic_setlladdr(struct vic_softc *); 338 int vic_media_change(struct ifnet *); 339 void vic_media_status(struct ifnet *, struct ifmediareq *); 340 void vic_start(struct ifnet *); 341 int vic_load_txb(struct vic_softc *, struct vic_txbuf *, 342 struct mbuf *); 343 void vic_watchdog(struct ifnet *); 344 int vic_ioctl(struct ifnet *, u_long, caddr_t); 345 void vic_init(struct ifnet *); 346 void vic_stop(struct ifnet *); 347 void vic_tick(void *); 348 349 #define DEVNAME(_s) ((_s)->sc_dev.dv_xname) 350 351 struct mbuf *vic_alloc_mbuf(struct vic_softc *, bus_dmamap_t, u_int); 352 353 const struct pci_matchid vic_devices[] = { 354 { PCI_VENDOR_VMWARE, PCI_PRODUCT_VMWARE_NET } 355 }; 356 357 int 358 vic_match(struct device *parent, void *match, void *aux) 359 { 360 struct pci_attach_args *pa = aux; 361 pcireg_t memtype; 362 bus_size_t pcisize; 363 bus_addr_t pciaddr; 364 365 switch (pa->pa_id) { 366 case PCI_ID_CODE(PCI_VENDOR_VMWARE, PCI_PRODUCT_VMWARE_NET): 367 return (1); 368 369 case PCI_ID_CODE(PCI_VENDOR_AMD, PCI_PRODUCT_AMD_PCNET_PCI): 370 memtype = pci_mapreg_type(pa->pa_pc, pa->pa_tag, VIC_PCI_BAR); 371 if (pci_mapreg_info(pa->pa_pc, pa->pa_tag, VIC_PCI_BAR, 372 memtype, &pciaddr, &pcisize, NULL) != 0) 373 break; 374 375 if (pcisize > VIC_LANCE_MINLEN) 376 return (2); 377 378 break; 379 } 380 381 return (0); 382 } 383 384 void 385 vic_attach(struct device *parent, struct device *self, void *aux) 386 { 387 struct vic_softc *sc = (struct vic_softc *)self; 388 struct pci_attach_args *pa = aux; 389 bus_space_handle_t ioh; 390 pcireg_t r; 391 pci_intr_handle_t ih; 392 struct ifnet *ifp; 393 394 sc->sc_pc = pa->pa_pc; 395 sc->sc_tag = pa->pa_tag; 396 sc->sc_dmat = pa->pa_dmat; 397 398 r = pci_mapreg_type(sc->sc_pc, sc->sc_tag, VIC_PCI_BAR); 399 if (pci_mapreg_map(pa, VIC_PCI_BAR, r, 0, &sc->sc_iot, 400 &ioh, NULL, &sc->sc_ios, 0) != 0) { 401 printf(": unable to map system interface register\n"); 402 return; 403 } 404 405 switch (pa->pa_id) { 406 case PCI_ID_CODE(PCI_VENDOR_VMWARE, PCI_PRODUCT_VMWARE_NET): 407 if (bus_space_subregion(sc->sc_iot, ioh, 0, sc->sc_ios, 408 &sc->sc_ioh) != 0) { 409 printf(": unable to map register window\n"); 410 goto unmap; 411 } 412 break; 413 414 case PCI_ID_CODE(PCI_VENDOR_AMD, PCI_PRODUCT_AMD_PCNET_PCI): 415 if (bus_space_subregion(sc->sc_iot, ioh, 416 VIC_LANCE_SIZE + VIC_MORPH_SIZE, VIC_VMXNET_SIZE, 417 &sc->sc_ioh) != 0) { 418 printf(": unable to map register window\n"); 419 goto unmap; 420 } 421 422 bus_space_barrier(sc->sc_iot, ioh, VIC_LANCE_SIZE, 4, 423 BUS_SPACE_BARRIER_READ); 424 r = bus_space_read_4(sc->sc_iot, ioh, VIC_LANCE_SIZE); 425 426 if ((r & VIC_MORPH_MASK) == VIC_MORPH_VMXNET) 427 break; 428 if ((r & VIC_MORPH_MASK) != VIC_MORPH_LANCE) { 429 printf(": unexpect morph value (0x%08x)\n", r); 430 goto unmap; 431 } 432 433 r &= ~VIC_MORPH_MASK; 434 r |= VIC_MORPH_VMXNET; 435 436 bus_space_write_4(sc->sc_iot, ioh, VIC_LANCE_SIZE, r); 437 bus_space_barrier(sc->sc_iot, ioh, VIC_LANCE_SIZE, 4, 438 BUS_SPACE_BARRIER_WRITE); 439 440 bus_space_barrier(sc->sc_iot, ioh, VIC_LANCE_SIZE, 4, 441 BUS_SPACE_BARRIER_READ); 442 r = bus_space_read_4(sc->sc_iot, ioh, VIC_LANCE_SIZE); 443 444 if ((r & VIC_MORPH_MASK) != VIC_MORPH_VMXNET) { 445 printf(": unable to morph vlance chip\n"); 446 goto unmap; 447 } 448 449 break; 450 } 451 452 if (pci_intr_map(pa, &ih) != 0) { 453 printf(": unable to map interrupt\n"); 454 goto unmap; 455 } 456 457 sc->sc_ih = pci_intr_establish(pa->pa_pc, ih, IPL_NET, 458 vic_intr, sc, DEVNAME(sc)); 459 if (sc->sc_ih == NULL) { 460 printf(": unable to establish interrupt\n"); 461 goto unmap; 462 } 463 464 if (vic_query(sc) != 0) { 465 /* error printed by vic_query */ 466 goto unmap; 467 } 468 469 if (vic_alloc_data(sc) != 0) { 470 /* error printed by vic_alloc */ 471 goto unmap; 472 } 473 474 timeout_set(&sc->sc_tick, vic_tick, sc); 475 476 bcopy(sc->sc_lladdr, sc->sc_ac.ac_enaddr, ETHER_ADDR_LEN); 477 478 ifp = &sc->sc_ac.ac_if; 479 ifp->if_softc = sc; 480 ifp->if_flags = IFF_BROADCAST | IFF_SIMPLEX | IFF_MULTICAST; 481 ifp->if_ioctl = vic_ioctl; 482 ifp->if_start = vic_start; 483 ifp->if_watchdog = vic_watchdog; 484 ifp->if_hardmtu = VIC_JUMBO_MTU; 485 strlcpy(ifp->if_xname, DEVNAME(sc), IFNAMSIZ); 486 IFQ_SET_MAXLEN(&ifp->if_snd, sc->sc_ntxbuf - 1); 487 IFQ_SET_READY(&ifp->if_snd); 488 489 ifp->if_capabilities = IFCAP_VLAN_MTU; 490 491 #if 0 492 /* XXX interface capabilities */ 493 if (sc->sc_cap & VIC_CMD_HWCAP_VLAN) 494 ifp->if_capabilities |= IFCAP_VLAN_HWTAGGING; 495 if (sc->sc_cap & VIC_CMD_HWCAP_CSUM) 496 ifp->if_capabilities |= IFCAP_CSUM_IPv4 | IFCAP_CSUM_TCPv4 | 497 IFCAP_CSUM_UDPv4; 498 #endif 499 500 ifmedia_init(&sc->sc_media, 0, vic_media_change, vic_media_status); 501 ifmedia_add(&sc->sc_media, IFM_ETHER | IFM_AUTO, 0, NULL); 502 ifmedia_set(&sc->sc_media, IFM_ETHER | IFM_AUTO); 503 504 if_attach(ifp); 505 ether_ifattach(ifp); 506 507 printf(": %s, address %s\n", pci_intr_string(pa->pa_pc, ih), 508 ether_sprintf(sc->sc_lladdr)); 509 510 #ifdef VIC_DEBUG 511 printf("%s: feature 0x%8x, cap 0x%8x, rx/txbuf %d/%d\n", DEVNAME(sc), 512 sc->sc_feature, sc->sc_cap, sc->sc_nrxbuf, sc->sc_ntxbuf); 513 #endif 514 515 return; 516 517 unmap: 518 bus_space_unmap(sc->sc_iot, ioh, sc->sc_ios); 519 sc->sc_ios = 0; 520 } 521 522 int 523 vic_query(struct vic_softc *sc) 524 { 525 u_int32_t major, minor; 526 527 major = vic_read(sc, VIC_VERSION_MAJOR); 528 minor = vic_read(sc, VIC_VERSION_MINOR); 529 530 /* Check for a supported version */ 531 if ((major & VIC_VERSION_MAJOR_M) != 532 (VIC_MAGIC & VIC_VERSION_MAJOR_M)) { 533 printf(": magic mismatch\n"); 534 return (1); 535 } 536 537 if (VIC_MAGIC > major || VIC_MAGIC < minor) { 538 printf(": unsupported version (%X)\n", 539 major & ~VIC_VERSION_MAJOR_M); 540 return (1); 541 } 542 543 sc->sc_nrxbuf = vic_read_cmd(sc, VIC_CMD_NUM_Rx_BUF); 544 sc->sc_ntxbuf = vic_read_cmd(sc, VIC_CMD_NUM_Tx_BUF); 545 sc->sc_feature = vic_read_cmd(sc, VIC_CMD_FEATURE); 546 sc->sc_cap = vic_read_cmd(sc, VIC_CMD_HWCAP); 547 548 vic_getlladdr(sc); 549 550 if (sc->sc_nrxbuf > VIC_NBUF_MAX || sc->sc_nrxbuf == 0) 551 sc->sc_nrxbuf = VIC_NBUF; 552 if (sc->sc_ntxbuf > VIC_NBUF_MAX || sc->sc_ntxbuf == 0) 553 sc->sc_ntxbuf = VIC_NBUF; 554 555 return (0); 556 } 557 558 int 559 vic_alloc_data(struct vic_softc *sc) 560 { 561 u_int8_t *kva; 562 u_int offset; 563 struct vic_rxdesc *rxd; 564 int i, q; 565 566 sc->sc_rxq[0].pktlen = MCLBYTES; 567 sc->sc_rxq[1].pktlen = 4096; 568 569 for (q = 0; q < VIC_NRXRINGS; q++) { 570 sc->sc_rxq[q].bufs = mallocarray(sc->sc_nrxbuf, 571 sizeof(struct vic_rxbuf), M_DEVBUF, M_NOWAIT | M_ZERO); 572 if (sc->sc_rxq[q].bufs == NULL) { 573 printf(": unable to allocate rxbuf for ring %d\n", q); 574 goto freerx; 575 } 576 } 577 578 sc->sc_txbuf = mallocarray(sc->sc_ntxbuf, sizeof(struct vic_txbuf), 579 M_DEVBUF, M_NOWAIT); 580 if (sc->sc_txbuf == NULL) { 581 printf(": unable to allocate txbuf\n"); 582 goto freerx; 583 } 584 585 sc->sc_dma_size = sizeof(struct vic_data) + 586 (sc->sc_nrxbuf * VIC_NRXRINGS) * sizeof(struct vic_rxdesc) + 587 sc->sc_ntxbuf * sizeof(struct vic_txdesc); 588 589 if (vic_alloc_dmamem(sc) != 0) { 590 printf(": unable to allocate dma region\n"); 591 goto freetx; 592 } 593 kva = VIC_DMA_KVA(sc); 594 595 /* set up basic vic data */ 596 sc->sc_data = VIC_DMA_KVA(sc); 597 598 sc->sc_data->vd_magic = VIC_MAGIC; 599 sc->sc_data->vd_length = sc->sc_dma_size; 600 601 offset = sizeof(struct vic_data); 602 603 /* set up the rx rings */ 604 605 for (q = 0; q < VIC_NRXRINGS; q++) { 606 sc->sc_rxq[q].slots = (struct vic_rxdesc *)&kva[offset]; 607 sc->sc_data->vd_rx_offset[q] = offset; 608 sc->sc_data->vd_rx[q].length = sc->sc_nrxbuf; 609 610 for (i = 0; i < sc->sc_nrxbuf; i++) { 611 rxd = &sc->sc_rxq[q].slots[i]; 612 613 rxd->rx_physaddr = 0; 614 rxd->rx_buflength = 0; 615 rxd->rx_length = 0; 616 rxd->rx_owner = VIC_OWNER_DRIVER; 617 618 offset += sizeof(struct vic_rxdesc); 619 } 620 } 621 622 /* set up the tx ring */ 623 sc->sc_txq = (struct vic_txdesc *)&kva[offset]; 624 625 sc->sc_data->vd_tx_offset = offset; 626 sc->sc_data->vd_tx_length = sc->sc_ntxbuf; 627 628 return (0); 629 freetx: 630 free(sc->sc_txbuf, M_DEVBUF, 0); 631 q = VIC_NRXRINGS; 632 freerx: 633 while (q--) 634 free(sc->sc_rxq[q].bufs, M_DEVBUF, 0); 635 636 return (1); 637 } 638 639 void 640 vic_rx_fill(struct vic_softc *sc, int q) 641 { 642 struct vic_rxbuf *rxb; 643 struct vic_rxdesc *rxd; 644 u_int slots; 645 646 for (slots = if_rxr_get(&sc->sc_rxq[q].ring, sc->sc_nrxbuf); 647 slots > 0; slots--) { 648 rxb = &sc->sc_rxq[q].bufs[sc->sc_rxq[q].end]; 649 rxd = &sc->sc_rxq[q].slots[sc->sc_rxq[q].end]; 650 651 rxb->rxb_m = vic_alloc_mbuf(sc, rxb->rxb_dmamap, 652 sc->sc_rxq[q].pktlen); 653 if (rxb->rxb_m == NULL) 654 break; 655 656 bus_dmamap_sync(sc->sc_dmat, rxb->rxb_dmamap, 0, 657 rxb->rxb_m->m_pkthdr.len, BUS_DMASYNC_PREREAD); 658 659 rxd->rx_physaddr = rxb->rxb_dmamap->dm_segs[0].ds_addr; 660 rxd->rx_buflength = rxb->rxb_m->m_pkthdr.len; 661 rxd->rx_length = 0; 662 rxd->rx_owner = VIC_OWNER_NIC; 663 664 VIC_INC(sc->sc_rxq[q].end, sc->sc_data->vd_rx[q].length); 665 } 666 if_rxr_put(&sc->sc_rxq[q].ring, slots); 667 } 668 669 int 670 vic_init_data(struct vic_softc *sc) 671 { 672 struct vic_rxbuf *rxb; 673 struct vic_rxdesc *rxd; 674 struct vic_txbuf *txb; 675 676 int q, i; 677 678 for (q = 0; q < VIC_NRXRINGS; q++) { 679 for (i = 0; i < sc->sc_nrxbuf; i++) { 680 rxb = &sc->sc_rxq[q].bufs[i]; 681 rxd = &sc->sc_rxq[q].slots[i]; 682 683 if (bus_dmamap_create(sc->sc_dmat, 684 sc->sc_rxq[q].pktlen, 1, sc->sc_rxq[q].pktlen, 0, 685 BUS_DMA_NOWAIT, &rxb->rxb_dmamap) != 0) { 686 printf("%s: unable to create dmamap for " 687 "ring %d slot %d\n", DEVNAME(sc), q, i); 688 goto freerxbs; 689 } 690 691 /* scrub the ring */ 692 rxd->rx_physaddr = 0; 693 rxd->rx_buflength = 0; 694 rxd->rx_length = 0; 695 rxd->rx_owner = VIC_OWNER_DRIVER; 696 } 697 sc->sc_rxq[q].end = 0; 698 699 if_rxr_init(&sc->sc_rxq[q].ring, 2, sc->sc_nrxbuf - 1); 700 vic_rx_fill(sc, q); 701 } 702 703 for (i = 0; i < sc->sc_ntxbuf; i++) { 704 txb = &sc->sc_txbuf[i]; 705 if (bus_dmamap_create(sc->sc_dmat, VIC_JUMBO_FRAMELEN, 706 (sc->sc_cap & VIC_CMD_HWCAP_SG) ? VIC_SG_MAX : 1, 707 VIC_JUMBO_FRAMELEN, 0, BUS_DMA_NOWAIT, 708 &txb->txb_dmamap) != 0) { 709 printf("%s: unable to create dmamap for tx %d\n", 710 DEVNAME(sc), i); 711 goto freetxbs; 712 } 713 txb->txb_m = NULL; 714 } 715 716 return (0); 717 718 freetxbs: 719 while (i--) { 720 txb = &sc->sc_txbuf[i]; 721 bus_dmamap_destroy(sc->sc_dmat, txb->txb_dmamap); 722 } 723 724 i = sc->sc_nrxbuf; 725 q = VIC_NRXRINGS - 1; 726 freerxbs: 727 while (q >= 0) { 728 while (i--) { 729 rxb = &sc->sc_rxq[q].bufs[i]; 730 731 if (rxb->rxb_m != NULL) { 732 bus_dmamap_sync(sc->sc_dmat, rxb->rxb_dmamap, 733 0, rxb->rxb_m->m_pkthdr.len, 734 BUS_DMASYNC_POSTREAD); 735 bus_dmamap_unload(sc->sc_dmat, rxb->rxb_dmamap); 736 m_freem(rxb->rxb_m); 737 rxb->rxb_m = NULL; 738 } 739 bus_dmamap_destroy(sc->sc_dmat, rxb->rxb_dmamap); 740 } 741 q--; 742 } 743 744 return (1); 745 } 746 747 int 748 vic_uninit_data(struct vic_softc *sc) 749 { 750 struct vic_rxbuf *rxb; 751 struct vic_rxdesc *rxd; 752 struct vic_txbuf *txb; 753 754 int i, q; 755 756 for (q = 0; q < VIC_NRXRINGS; q++) { 757 for (i = 0; i < sc->sc_nrxbuf; i++) { 758 rxb = &sc->sc_rxq[q].bufs[i]; 759 rxd = &sc->sc_rxq[q].slots[i]; 760 761 if (rxb->rxb_m != NULL) { 762 bus_dmamap_sync(sc->sc_dmat, rxb->rxb_dmamap, 763 0, rxb->rxb_m->m_pkthdr.len, 764 BUS_DMASYNC_POSTREAD); 765 bus_dmamap_unload(sc->sc_dmat, rxb->rxb_dmamap); 766 m_freem(rxb->rxb_m); 767 rxb->rxb_m = NULL; 768 } 769 bus_dmamap_destroy(sc->sc_dmat, rxb->rxb_dmamap); 770 } 771 } 772 773 for (i = 0; i < sc->sc_ntxbuf; i++) { 774 txb = &sc->sc_txbuf[i]; 775 bus_dmamap_destroy(sc->sc_dmat, txb->txb_dmamap); 776 } 777 778 return (0); 779 } 780 781 void 782 vic_link_state(struct vic_softc *sc) 783 { 784 struct ifnet *ifp = &sc->sc_ac.ac_if; 785 u_int32_t status; 786 int link_state = LINK_STATE_DOWN; 787 788 status = vic_read(sc, VIC_STATUS); 789 if (status & VIC_STATUS_CONNECTED) 790 link_state = LINK_STATE_FULL_DUPLEX; 791 if (ifp->if_link_state != link_state) { 792 ifp->if_link_state = link_state; 793 if_link_state_change(ifp); 794 } 795 } 796 797 int 798 vic_intr(void *arg) 799 { 800 struct vic_softc *sc = (struct vic_softc *)arg; 801 int q; 802 803 for (q = 0; q < VIC_NRXRINGS; q++) 804 vic_rx_proc(sc, q); 805 vic_tx_proc(sc); 806 807 vic_write(sc, VIC_CMD, VIC_CMD_INTR_ACK); 808 809 return (-1); 810 } 811 812 void 813 vic_rx_proc(struct vic_softc *sc, int q) 814 { 815 struct ifnet *ifp = &sc->sc_ac.ac_if; 816 struct vic_rxdesc *rxd; 817 struct vic_rxbuf *rxb; 818 struct mbuf *m; 819 int len, idx; 820 821 if ((ifp->if_flags & IFF_RUNNING) == 0) 822 return; 823 824 bus_dmamap_sync(sc->sc_dmat, sc->sc_dma_map, 0, sc->sc_dma_size, 825 BUS_DMASYNC_POSTREAD | BUS_DMASYNC_POSTWRITE); 826 827 while (if_rxr_inuse(&sc->sc_rxq[q].ring) > 0) { 828 idx = sc->sc_data->vd_rx[q].nextidx; 829 if (idx >= sc->sc_data->vd_rx[q].length) { 830 ifp->if_ierrors++; 831 if (ifp->if_flags & IFF_DEBUG) 832 printf("%s: receive index error\n", 833 sc->sc_dev.dv_xname); 834 break; 835 } 836 837 rxd = &sc->sc_rxq[q].slots[idx]; 838 if (rxd->rx_owner != VIC_OWNER_DRIVER) 839 break; 840 841 rxb = &sc->sc_rxq[q].bufs[idx]; 842 843 if (rxb->rxb_m == NULL) { 844 ifp->if_ierrors++; 845 printf("%s: rxb %d has no mbuf\n", DEVNAME(sc), idx); 846 break; 847 } 848 849 bus_dmamap_sync(sc->sc_dmat, rxb->rxb_dmamap, 0, 850 rxb->rxb_m->m_pkthdr.len, BUS_DMASYNC_POSTREAD); 851 bus_dmamap_unload(sc->sc_dmat, rxb->rxb_dmamap); 852 853 m = rxb->rxb_m; 854 rxb->rxb_m = NULL; 855 len = rxd->rx_length; 856 857 if (len < VIC_MIN_FRAMELEN) { 858 m_freem(m); 859 860 ifp->if_iqdrops++; 861 goto nextp; 862 } 863 864 m->m_pkthdr.rcvif = ifp; 865 m->m_pkthdr.len = m->m_len = len; 866 867 ifp->if_ipackets++; 868 869 #if NBPFILTER > 0 870 if (ifp->if_bpf) 871 bpf_mtap(ifp->if_bpf, m, BPF_DIRECTION_IN); 872 #endif 873 874 ether_input_mbuf(ifp, m); 875 876 nextp: 877 if_rxr_put(&sc->sc_rxq[q].ring, 1); 878 VIC_INC(sc->sc_data->vd_rx[q].nextidx, sc->sc_nrxbuf); 879 } 880 881 vic_rx_fill(sc, q); 882 883 bus_dmamap_sync(sc->sc_dmat, sc->sc_dma_map, 0, sc->sc_dma_size, 884 BUS_DMASYNC_PREREAD | BUS_DMASYNC_PREWRITE); 885 } 886 887 void 888 vic_tx_proc(struct vic_softc *sc) 889 { 890 struct ifnet *ifp = &sc->sc_ac.ac_if; 891 struct vic_txdesc *txd; 892 struct vic_txbuf *txb; 893 int idx; 894 895 bus_dmamap_sync(sc->sc_dmat, sc->sc_dma_map, 0, sc->sc_dma_size, 896 BUS_DMASYNC_POSTREAD | BUS_DMASYNC_POSTWRITE); 897 898 while (sc->sc_txpending > 0) { 899 idx = sc->sc_data->vd_tx_curidx; 900 if (idx >= sc->sc_data->vd_tx_length) { 901 ifp->if_oerrors++; 902 break; 903 } 904 905 txd = &sc->sc_txq[idx]; 906 if (txd->tx_owner != VIC_OWNER_DRIVER) 907 break; 908 909 txb = &sc->sc_txbuf[idx]; 910 if (txb->txb_m == NULL) { 911 printf("%s: tx ring is corrupt\n", DEVNAME(sc)); 912 ifp->if_oerrors++; 913 break; 914 } 915 916 bus_dmamap_sync(sc->sc_dmat, txb->txb_dmamap, 0, 917 txb->txb_dmamap->dm_mapsize, BUS_DMASYNC_POSTWRITE); 918 bus_dmamap_unload(sc->sc_dmat, txb->txb_dmamap); 919 920 m_freem(txb->txb_m); 921 txb->txb_m = NULL; 922 ifp->if_flags &= ~IFF_OACTIVE; 923 924 sc->sc_txpending--; 925 sc->sc_data->vd_tx_stopped = 0; 926 927 VIC_INC(sc->sc_data->vd_tx_curidx, sc->sc_data->vd_tx_length); 928 } 929 930 bus_dmamap_sync(sc->sc_dmat, sc->sc_dma_map, 0, sc->sc_dma_size, 931 BUS_DMASYNC_PREREAD | BUS_DMASYNC_PREWRITE); 932 933 vic_start(ifp); 934 } 935 936 void 937 vic_iff(struct vic_softc *sc) 938 { 939 struct arpcom *ac = &sc->sc_ac; 940 struct ifnet *ifp = &sc->sc_ac.ac_if; 941 struct ether_multi *enm; 942 struct ether_multistep step; 943 u_int32_t crc; 944 u_int16_t *mcastfil = (u_int16_t *)sc->sc_data->vd_mcastfil; 945 u_int flags; 946 947 ifp->if_flags &= ~IFF_ALLMULTI; 948 949 /* Always accept broadcast frames. */ 950 flags = VIC_CMD_IFF_BROADCAST; 951 952 if (ifp->if_flags & IFF_PROMISC || ac->ac_multirangecnt > 0) { 953 ifp->if_flags |= IFF_ALLMULTI; 954 if (ifp->if_flags & IFF_PROMISC) 955 flags |= VIC_CMD_IFF_PROMISC; 956 else 957 flags |= VIC_CMD_IFF_MULTICAST; 958 memset(&sc->sc_data->vd_mcastfil, 0xff, 959 sizeof(sc->sc_data->vd_mcastfil)); 960 } else { 961 flags |= VIC_CMD_IFF_MULTICAST; 962 963 bzero(&sc->sc_data->vd_mcastfil, 964 sizeof(sc->sc_data->vd_mcastfil)); 965 966 ETHER_FIRST_MULTI(step, ac, enm); 967 while (enm != NULL) { 968 crc = ether_crc32_le(enm->enm_addrlo, ETHER_ADDR_LEN); 969 970 crc >>= 26; 971 972 mcastfil[crc >> 4] |= htole16(1 << (crc & 0xf)); 973 974 ETHER_NEXT_MULTI(step, enm); 975 } 976 } 977 978 vic_write(sc, VIC_CMD, VIC_CMD_MCASTFIL); 979 sc->sc_data->vd_iff = flags; 980 vic_write(sc, VIC_CMD, VIC_CMD_IFF); 981 } 982 983 void 984 vic_getlladdr(struct vic_softc *sc) 985 { 986 u_int32_t reg; 987 988 /* Get MAC address */ 989 reg = (sc->sc_cap & VIC_CMD_HWCAP_VPROM) ? VIC_VPROM : VIC_LLADDR; 990 991 bus_space_barrier(sc->sc_iot, sc->sc_ioh, reg, ETHER_ADDR_LEN, 992 BUS_SPACE_BARRIER_READ); 993 bus_space_read_region_1(sc->sc_iot, sc->sc_ioh, reg, sc->sc_lladdr, 994 ETHER_ADDR_LEN); 995 996 /* Update the MAC address register */ 997 if (reg == VIC_VPROM) 998 vic_setlladdr(sc); 999 } 1000 1001 void 1002 vic_setlladdr(struct vic_softc *sc) 1003 { 1004 bus_space_write_region_1(sc->sc_iot, sc->sc_ioh, VIC_LLADDR, 1005 sc->sc_lladdr, ETHER_ADDR_LEN); 1006 bus_space_barrier(sc->sc_iot, sc->sc_ioh, VIC_LLADDR, ETHER_ADDR_LEN, 1007 BUS_SPACE_BARRIER_WRITE); 1008 } 1009 1010 int 1011 vic_media_change(struct ifnet *ifp) 1012 { 1013 /* Ignore */ 1014 return (0); 1015 } 1016 1017 void 1018 vic_media_status(struct ifnet *ifp, struct ifmediareq *imr) 1019 { 1020 struct vic_softc *sc = (struct vic_softc *)ifp->if_softc; 1021 1022 imr->ifm_active = IFM_ETHER | IFM_AUTO; 1023 imr->ifm_status = IFM_AVALID; 1024 1025 vic_link_state(sc); 1026 1027 if (LINK_STATE_IS_UP(ifp->if_link_state) && 1028 ifp->if_flags & IFF_UP) 1029 imr->ifm_status |= IFM_ACTIVE; 1030 } 1031 1032 void 1033 vic_start(struct ifnet *ifp) 1034 { 1035 struct vic_softc *sc; 1036 struct mbuf *m; 1037 struct vic_txbuf *txb; 1038 struct vic_txdesc *txd; 1039 struct vic_sg *sge; 1040 bus_dmamap_t dmap; 1041 int i, idx; 1042 int tx = 0; 1043 1044 if (!(ifp->if_flags & IFF_RUNNING)) 1045 return; 1046 1047 if (ifp->if_flags & IFF_OACTIVE) 1048 return; 1049 1050 if (IFQ_IS_EMPTY(&ifp->if_snd)) 1051 return; 1052 1053 sc = (struct vic_softc *)ifp->if_softc; 1054 1055 bus_dmamap_sync(sc->sc_dmat, sc->sc_dma_map, 0, sc->sc_dma_size, 1056 BUS_DMASYNC_POSTREAD | BUS_DMASYNC_POSTWRITE); 1057 1058 for (;;) { 1059 if (VIC_TXURN(sc)) { 1060 ifp->if_flags |= IFF_OACTIVE; 1061 break; 1062 } 1063 1064 IFQ_POLL(&ifp->if_snd, m); 1065 if (m == NULL) 1066 break; 1067 1068 idx = sc->sc_data->vd_tx_nextidx; 1069 if (idx >= sc->sc_data->vd_tx_length) { 1070 printf("%s: tx idx is corrupt\n", DEVNAME(sc)); 1071 ifp->if_oerrors++; 1072 break; 1073 } 1074 1075 txd = &sc->sc_txq[idx]; 1076 txb = &sc->sc_txbuf[idx]; 1077 1078 if (txb->txb_m != NULL) { 1079 printf("%s: tx ring is corrupt\n", DEVNAME(sc)); 1080 sc->sc_data->vd_tx_stopped = 1; 1081 ifp->if_oerrors++; 1082 break; 1083 } 1084 1085 /* 1086 * we're committed to sending it now. if we cant map it into 1087 * dma memory then we drop it. 1088 */ 1089 IFQ_DEQUEUE(&ifp->if_snd, m); 1090 if (vic_load_txb(sc, txb, m) != 0) { 1091 m_freem(m); 1092 ifp->if_oerrors++; 1093 /* continue? */ 1094 break; 1095 } 1096 1097 #if NBPFILTER > 0 1098 if (ifp->if_bpf) 1099 bpf_mtap(ifp->if_bpf, txb->txb_m, BPF_DIRECTION_OUT); 1100 #endif 1101 1102 dmap = txb->txb_dmamap; 1103 txd->tx_flags = VIC_TX_FLAGS_KEEP; 1104 txd->tx_owner = VIC_OWNER_NIC; 1105 txd->tx_sa.sa_addr_type = VIC_SG_ADDR_PHYS; 1106 txd->tx_sa.sa_length = dmap->dm_nsegs; 1107 for (i = 0; i < dmap->dm_nsegs; i++) { 1108 sge = &txd->tx_sa.sa_sg[i]; 1109 sge->sg_length = dmap->dm_segs[i].ds_len; 1110 sge->sg_addr_low = dmap->dm_segs[i].ds_addr; 1111 } 1112 1113 if (VIC_TXURN_WARN(sc)) { 1114 txd->tx_flags |= VIC_TX_FLAGS_TXURN; 1115 } 1116 1117 bus_dmamap_sync(sc->sc_dmat, dmap, 0, dmap->dm_mapsize, 1118 BUS_DMASYNC_PREWRITE); 1119 1120 ifp->if_opackets++; 1121 sc->sc_txpending++; 1122 1123 VIC_INC(sc->sc_data->vd_tx_nextidx, sc->sc_data->vd_tx_length); 1124 1125 tx = 1; 1126 } 1127 1128 bus_dmamap_sync(sc->sc_dmat, sc->sc_dma_map, 0, sc->sc_dma_size, 1129 BUS_DMASYNC_PREREAD | BUS_DMASYNC_PREWRITE); 1130 1131 if (tx) 1132 vic_read(sc, VIC_Tx_ADDR); 1133 } 1134 1135 int 1136 vic_load_txb(struct vic_softc *sc, struct vic_txbuf *txb, struct mbuf *m) 1137 { 1138 bus_dmamap_t dmap = txb->txb_dmamap; 1139 struct mbuf *m0 = NULL; 1140 int error; 1141 1142 error = bus_dmamap_load_mbuf(sc->sc_dmat, dmap, m, BUS_DMA_NOWAIT); 1143 switch (error) { 1144 case 0: 1145 txb->txb_m = m; 1146 break; 1147 1148 case EFBIG: /* mbuf chain is too fragmented */ 1149 MGETHDR(m0, M_DONTWAIT, MT_DATA); 1150 if (m0 == NULL) 1151 return (ENOBUFS); 1152 if (m->m_pkthdr.len > MHLEN) { 1153 MCLGETI(m0, M_DONTWAIT, NULL, m->m_pkthdr.len); 1154 if (!(m0->m_flags & M_EXT)) { 1155 m_freem(m0); 1156 return (ENOBUFS); 1157 } 1158 } 1159 m_copydata(m, 0, m->m_pkthdr.len, mtod(m0, caddr_t)); 1160 m0->m_pkthdr.len = m0->m_len = m->m_pkthdr.len; 1161 error = bus_dmamap_load_mbuf(sc->sc_dmat, dmap, m0, 1162 BUS_DMA_NOWAIT); 1163 if (error != 0) { 1164 m_freem(m0); 1165 printf("%s: tx dmamap load error %d\n", DEVNAME(sc), 1166 error); 1167 return (ENOBUFS); 1168 } 1169 m_freem(m); 1170 txb->txb_m = m0; 1171 break; 1172 1173 default: 1174 printf("%s: tx dmamap load error %d\n", DEVNAME(sc), error); 1175 return (ENOBUFS); 1176 } 1177 1178 return (0); 1179 } 1180 1181 void 1182 vic_watchdog(struct ifnet *ifp) 1183 { 1184 #if 0 1185 struct vic_softc *sc = (struct vic_softc *)ifp->if_softc; 1186 1187 if (sc->sc_txpending && sc->sc_txtimeout > 0) { 1188 if (--sc->sc_txtimeout == 0) { 1189 printf("%s: device timeout\n", sc->sc_dev.dv_xname); 1190 ifp->if_flags &= ~IFF_RUNNING; 1191 vic_init(ifp); 1192 ifp->if_oerrors++; 1193 return; 1194 } 1195 } 1196 1197 if (!IFQ_IS_EMPTY(&ifp->if_snd)) 1198 vic_start(ifp); 1199 #endif 1200 } 1201 1202 int 1203 vic_ioctl(struct ifnet *ifp, u_long cmd, caddr_t data) 1204 { 1205 struct vic_softc *sc = (struct vic_softc *)ifp->if_softc; 1206 struct ifaddr *ifa = (struct ifaddr *)data; 1207 struct ifreq *ifr = (struct ifreq *)data; 1208 int s, error = 0; 1209 1210 s = splnet(); 1211 1212 switch (cmd) { 1213 case SIOCSIFADDR: 1214 ifp->if_flags |= IFF_UP; 1215 #ifdef INET 1216 if (ifa->ifa_addr->sa_family == AF_INET) 1217 arp_ifinit(&sc->sc_ac, ifa); 1218 #endif 1219 /* FALLTHROUGH */ 1220 case SIOCSIFFLAGS: 1221 if (ifp->if_flags & IFF_UP) { 1222 if (ifp->if_flags & IFF_RUNNING) 1223 error = ENETRESET; 1224 else 1225 vic_init(ifp); 1226 } else { 1227 if (ifp->if_flags & IFF_RUNNING) 1228 vic_stop(ifp); 1229 } 1230 break; 1231 1232 case SIOCGIFMEDIA: 1233 case SIOCSIFMEDIA: 1234 error = ifmedia_ioctl(ifp, ifr, &sc->sc_media, cmd); 1235 break; 1236 1237 default: 1238 error = ether_ioctl(ifp, &sc->sc_ac, cmd, data); 1239 } 1240 1241 if (error == ENETRESET) { 1242 if (ifp->if_flags & IFF_RUNNING) 1243 vic_iff(sc); 1244 error = 0; 1245 } 1246 1247 splx(s); 1248 return (error); 1249 } 1250 1251 void 1252 vic_init(struct ifnet *ifp) 1253 { 1254 struct vic_softc *sc = (struct vic_softc *)ifp->if_softc; 1255 int q; 1256 int s; 1257 1258 sc->sc_data->vd_tx_curidx = 0; 1259 sc->sc_data->vd_tx_nextidx = 0; 1260 sc->sc_data->vd_tx_stopped = sc->sc_data->vd_tx_queued = 0; 1261 sc->sc_data->vd_tx_saved_nextidx = 0; 1262 1263 for (q = 0; q < VIC_NRXRINGS; q++) { 1264 sc->sc_data->vd_rx[q].nextidx = 0; 1265 sc->sc_data->vd_rx_saved_nextidx[q] = 0; 1266 } 1267 1268 if (vic_init_data(sc) != 0) 1269 return; 1270 1271 bus_dmamap_sync(sc->sc_dmat, sc->sc_dma_map, 0, sc->sc_dma_size, 1272 BUS_DMASYNC_PREREAD | BUS_DMASYNC_PREWRITE); 1273 1274 s = splnet(); 1275 1276 vic_write(sc, VIC_DATA_ADDR, VIC_DMA_DVA(sc)); 1277 vic_write(sc, VIC_DATA_LENGTH, sc->sc_dma_size); 1278 1279 ifp->if_flags |= IFF_RUNNING; 1280 ifp->if_flags &= ~IFF_OACTIVE; 1281 1282 vic_iff(sc); 1283 vic_write(sc, VIC_CMD, VIC_CMD_INTR_ENABLE); 1284 1285 splx(s); 1286 1287 timeout_add_sec(&sc->sc_tick, 1); 1288 } 1289 1290 void 1291 vic_stop(struct ifnet *ifp) 1292 { 1293 struct vic_softc *sc = (struct vic_softc *)ifp->if_softc; 1294 int s; 1295 1296 s = splnet(); 1297 1298 timeout_del(&sc->sc_tick); 1299 1300 ifp->if_flags &= ~(IFF_RUNNING | IFF_OACTIVE); 1301 1302 bus_dmamap_sync(sc->sc_dmat, sc->sc_dma_map, 0, sc->sc_dma_size, 1303 BUS_DMASYNC_POSTREAD | BUS_DMASYNC_POSTWRITE); 1304 1305 /* XXX wait for tx to complete */ 1306 while (sc->sc_txpending > 0) { 1307 splx(s); 1308 delay(1000); 1309 s = splnet(); 1310 } 1311 1312 sc->sc_data->vd_tx_stopped = 1; 1313 1314 vic_write(sc, VIC_CMD, VIC_CMD_INTR_DISABLE); 1315 1316 sc->sc_data->vd_iff = 0; 1317 vic_write(sc, VIC_CMD, VIC_CMD_IFF); 1318 1319 vic_write(sc, VIC_DATA_ADDR, 0); 1320 1321 vic_uninit_data(sc); 1322 1323 splx(s); 1324 } 1325 1326 struct mbuf * 1327 vic_alloc_mbuf(struct vic_softc *sc, bus_dmamap_t map, u_int pktlen) 1328 { 1329 struct mbuf *m = NULL; 1330 1331 m = MCLGETI(NULL, M_DONTWAIT, NULL, pktlen); 1332 if (!m) 1333 return (NULL); 1334 m->m_data += ETHER_ALIGN; 1335 m->m_len = m->m_pkthdr.len = pktlen - ETHER_ALIGN; 1336 1337 if (bus_dmamap_load_mbuf(sc->sc_dmat, map, m, BUS_DMA_NOWAIT) != 0) { 1338 printf("%s: could not load mbuf DMA map\n", DEVNAME(sc)); 1339 m_freem(m); 1340 return (NULL); 1341 } 1342 1343 return (m); 1344 } 1345 1346 void 1347 vic_tick(void *arg) 1348 { 1349 struct vic_softc *sc = (struct vic_softc *)arg; 1350 1351 vic_link_state(sc); 1352 1353 timeout_add_sec(&sc->sc_tick, 1); 1354 } 1355 1356 u_int32_t 1357 vic_read(struct vic_softc *sc, bus_size_t r) 1358 { 1359 bus_space_barrier(sc->sc_iot, sc->sc_ioh, r, 4, 1360 BUS_SPACE_BARRIER_READ); 1361 return (bus_space_read_4(sc->sc_iot, sc->sc_ioh, r)); 1362 } 1363 1364 void 1365 vic_write(struct vic_softc *sc, bus_size_t r, u_int32_t v) 1366 { 1367 bus_space_write_4(sc->sc_iot, sc->sc_ioh, r, v); 1368 bus_space_barrier(sc->sc_iot, sc->sc_ioh, r, 4, 1369 BUS_SPACE_BARRIER_WRITE); 1370 } 1371 1372 u_int32_t 1373 vic_read_cmd(struct vic_softc *sc, u_int32_t cmd) 1374 { 1375 vic_write(sc, VIC_CMD, cmd); 1376 return (vic_read(sc, VIC_CMD)); 1377 } 1378 1379 int 1380 vic_alloc_dmamem(struct vic_softc *sc) 1381 { 1382 int nsegs; 1383 1384 if (bus_dmamap_create(sc->sc_dmat, sc->sc_dma_size, 1, 1385 sc->sc_dma_size, 0, BUS_DMA_NOWAIT | BUS_DMA_ALLOCNOW, 1386 &sc->sc_dma_map) != 0) 1387 goto err; 1388 1389 if (bus_dmamem_alloc(sc->sc_dmat, sc->sc_dma_size, 16, 0, 1390 &sc->sc_dma_seg, 1, &nsegs, BUS_DMA_NOWAIT | BUS_DMA_ZERO) != 0) 1391 goto destroy; 1392 1393 if (bus_dmamem_map(sc->sc_dmat, &sc->sc_dma_seg, nsegs, 1394 sc->sc_dma_size, &sc->sc_dma_kva, BUS_DMA_NOWAIT) != 0) 1395 goto free; 1396 1397 if (bus_dmamap_load(sc->sc_dmat, sc->sc_dma_map, sc->sc_dma_kva, 1398 sc->sc_dma_size, NULL, BUS_DMA_NOWAIT) != 0) 1399 goto unmap; 1400 1401 return (0); 1402 1403 unmap: 1404 bus_dmamem_unmap(sc->sc_dmat, sc->sc_dma_kva, sc->sc_dma_size); 1405 free: 1406 bus_dmamem_free(sc->sc_dmat, &sc->sc_dma_seg, 1); 1407 destroy: 1408 bus_dmamap_destroy(sc->sc_dmat, sc->sc_dma_map); 1409 err: 1410 return (1); 1411 } 1412 1413 void 1414 vic_free_dmamem(struct vic_softc *sc) 1415 { 1416 bus_dmamap_unload(sc->sc_dmat, sc->sc_dma_map); 1417 bus_dmamem_unmap(sc->sc_dmat, sc->sc_dma_kva, sc->sc_dma_size); 1418 bus_dmamem_free(sc->sc_dmat, &sc->sc_dma_seg, 1); 1419 bus_dmamap_destroy(sc->sc_dmat, sc->sc_dma_map); 1420 } 1421