1 /* $OpenBSD: if_vic.c,v 1.74 2009/08/13 14:24:47 jasper Exp $ */ 2 3 /* 4 * Copyright (c) 2006 Reyk Floeter <reyk@openbsd.org> 5 * Copyright (c) 2006 David Gwynne <dlg@openbsd.org> 6 * 7 * Permission to use, copy, modify, and distribute this software for any 8 * purpose with or without fee is hereby granted, provided that the above 9 * copyright notice and this permission notice appear in all copies. 10 * 11 * THE SOFTWARE IS PROVIDED "AS IS" AND THE AUTHOR DISCLAIMS ALL WARRANTIES 12 * WITH REGARD TO THIS SOFTWARE INCLUDING ALL IMPLIED WARRANTIES OF 13 * MERCHANTABILITY AND FITNESS. IN NO EVENT SHALL THE AUTHOR BE LIABLE FOR 14 * ANY SPECIAL, DIRECT, INDIRECT, OR CONSEQUENTIAL DAMAGES OR ANY DAMAGES 15 * WHATSOEVER RESULTING FROM LOSS OF USE, DATA OR PROFITS, WHETHER IN AN 16 * ACTION OF CONTRACT, NEGLIGENCE OR OTHER TORTIOUS ACTION, ARISING OUT OF 17 * OR IN CONNECTION WITH THE USE OR PERFORMANCE OF THIS SOFTWARE. 18 */ 19 20 /* 21 * Driver for the VMware Virtual NIC ("vmxnet") 22 */ 23 24 #include "bpfilter.h" 25 26 #include <sys/param.h> 27 #include <sys/systm.h> 28 #include <sys/sockio.h> 29 #include <sys/mbuf.h> 30 #include <sys/kernel.h> 31 #include <sys/socket.h> 32 #include <sys/malloc.h> 33 #include <sys/timeout.h> 34 #include <sys/device.h> 35 36 #include <machine/bus.h> 37 #include <machine/intr.h> 38 39 #include <net/if.h> 40 #include <net/if_dl.h> 41 #include <net/if_media.h> 42 #include <net/if_types.h> 43 44 #if NBPFILTER > 0 45 #include <net/bpf.h> 46 #endif 47 48 #ifdef INET 49 #include <netinet/in.h> 50 #include <netinet/if_ether.h> 51 #endif 52 53 #include <dev/pci/pcireg.h> 54 #include <dev/pci/pcivar.h> 55 #include <dev/pci/pcidevs.h> 56 57 #define VIC_PCI_BAR PCI_MAPREG_START /* Base Address Register */ 58 59 #define VIC_LANCE_SIZE 0x20 60 #define VIC_MORPH_SIZE 0x04 61 #define VIC_MORPH_MASK 0xffff 62 #define VIC_MORPH_LANCE 0x2934 63 #define VIC_MORPH_VMXNET 0x4392 64 #define VIC_VMXNET_SIZE 0x40 65 #define VIC_LANCE_MINLEN (VIC_LANCE_SIZE + VIC_MORPH_SIZE + \ 66 VIC_VMXNET_SIZE) 67 68 #define VIC_MAGIC 0xbabe864f 69 70 /* Register address offsets */ 71 #define VIC_DATA_ADDR 0x0000 /* Shared data address */ 72 #define VIC_DATA_LENGTH 0x0004 /* Shared data length */ 73 #define VIC_Tx_ADDR 0x0008 /* Tx pointer address */ 74 75 /* Command register */ 76 #define VIC_CMD 0x000c /* Command register */ 77 #define VIC_CMD_INTR_ACK 0x0001 /* Acknowledge interrupt */ 78 #define VIC_CMD_MCASTFIL 0x0002 /* Multicast address filter */ 79 #define VIC_CMD_MCASTFIL_LENGTH 2 80 #define VIC_CMD_IFF 0x0004 /* Interface flags */ 81 #define VIC_CMD_IFF_PROMISC 0x0001 /* Promiscous enabled */ 82 #define VIC_CMD_IFF_BROADCAST 0x0002 /* Broadcast enabled */ 83 #define VIC_CMD_IFF_MULTICAST 0x0004 /* Multicast enabled */ 84 #define VIC_CMD_INTR_DISABLE 0x0020 /* Enable interrupts */ 85 #define VIC_CMD_INTR_ENABLE 0x0040 /* Disable interrupts */ 86 #define VIC_CMD_Tx_DONE 0x0100 /* Tx done register */ 87 #define VIC_CMD_NUM_Rx_BUF 0x0200 /* Number of Rx buffers */ 88 #define VIC_CMD_NUM_Tx_BUF 0x0400 /* Number of Tx buffers */ 89 #define VIC_CMD_NUM_PINNED_BUF 0x0800 /* Number of pinned buffers */ 90 #define VIC_CMD_HWCAP 0x1000 /* Capability register */ 91 #define VIC_CMD_HWCAP_SG (1<<0) /* Scatter-gather transmits */ 92 #define VIC_CMD_HWCAP_CSUM_IPv4 (1<<1) /* TCP/UDP cksum */ 93 #define VIC_CMD_HWCAP_CSUM_ALL (1<<3) /* Hardware cksum */ 94 #define VIC_CMD_HWCAP_CSUM \ 95 (VIC_CMD_HWCAP_CSUM_IPv4 | VIC_CMD_HWCAP_CSUM_ALL) 96 #define VIC_CMD_HWCAP_DMA_HIGH (1<<4) /* High DMA mapping */ 97 #define VIC_CMD_HWCAP_TOE (1<<5) /* TCP offload engine */ 98 #define VIC_CMD_HWCAP_TSO (1<<6) /* TCP segmentation offload */ 99 #define VIC_CMD_HWCAP_TSO_SW (1<<7) /* Software TCP segmentation */ 100 #define VIC_CMD_HWCAP_VPROM (1<<8) /* Virtual PROM available */ 101 #define VIC_CMD_HWCAP_VLAN_Tx (1<<9) /* Hardware VLAN MTU Rx */ 102 #define VIC_CMD_HWCAP_VLAN_Rx (1<<10) /* Hardware VLAN MTU Tx */ 103 #define VIC_CMD_HWCAP_VLAN_SW (1<<11) /* Software VLAN MTU */ 104 #define VIC_CMD_HWCAP_VLAN \ 105 (VIC_CMD_HWCAP_VLAN_Tx | VIC_CMD_HWCAP_VLAN_Rx | \ 106 VIC_CMD_HWCAP_VLAN_SW) 107 #define VIC_CMD_HWCAP_BITS \ 108 "\20\01SG\02CSUM4\03CSUM\04HDMA\05TOE\06TSO" \ 109 "\07TSOSW\10VPROM\13VLANTx\14VLANRx\15VLANSW" 110 #define VIC_CMD_FEATURE 0x2000 /* Additional feature register */ 111 #define VIC_CMD_FEATURE_0_Tx (1<<0) 112 #define VIC_CMD_FEATURE_TSO (1<<1) 113 114 #define VIC_LLADDR 0x0010 /* MAC address register */ 115 #define VIC_VERSION_MINOR 0x0018 /* Minor version register */ 116 #define VIC_VERSION_MAJOR 0x001c /* Major version register */ 117 #define VIC_VERSION_MAJOR_M 0xffff0000 118 119 /* Status register */ 120 #define VIC_STATUS 0x0020 121 #define VIC_STATUS_CONNECTED (1<<0) 122 #define VIC_STATUS_ENABLED (1<<1) 123 124 #define VIC_TOE_ADDR 0x0024 /* TCP offload address */ 125 126 /* Virtual PROM address */ 127 #define VIC_VPROM 0x0028 128 #define VIC_VPROM_LENGTH 6 129 130 /* Shared DMA data structures */ 131 132 struct vic_sg { 133 u_int32_t sg_addr_low; 134 u_int16_t sg_addr_high; 135 u_int16_t sg_length; 136 } __packed; 137 138 #define VIC_SG_MAX 6 139 #define VIC_SG_ADDR_MACH 0 140 #define VIC_SG_ADDR_PHYS 1 141 #define VIC_SG_ADDR_VIRT 3 142 143 struct vic_sgarray { 144 u_int16_t sa_addr_type; 145 u_int16_t sa_length; 146 struct vic_sg sa_sg[VIC_SG_MAX]; 147 } __packed; 148 149 struct vic_rxdesc { 150 u_int64_t rx_physaddr; 151 u_int32_t rx_buflength; 152 u_int32_t rx_length; 153 u_int16_t rx_owner; 154 u_int16_t rx_flags; 155 u_int32_t rx_priv; 156 } __packed; 157 158 #define VIC_RX_FLAGS_CSUMHW_OK 0x0001 159 160 struct vic_txdesc { 161 u_int16_t tx_flags; 162 u_int16_t tx_owner; 163 u_int32_t tx_priv; 164 u_int32_t tx_tsomss; 165 struct vic_sgarray tx_sa; 166 } __packed; 167 168 #define VIC_TX_FLAGS_KEEP 0x0001 169 #define VIC_TX_FLAGS_TXURN 0x0002 170 #define VIC_TX_FLAGS_CSUMHW 0x0004 171 #define VIC_TX_FLAGS_TSO 0x0008 172 #define VIC_TX_FLAGS_PINNED 0x0010 173 #define VIC_TX_FLAGS_QRETRY 0x1000 174 175 struct vic_stats { 176 u_int32_t vs_tx_count; 177 u_int32_t vs_tx_packets; 178 u_int32_t vs_tx_0copy; 179 u_int32_t vs_tx_copy; 180 u_int32_t vs_tx_maxpending; 181 u_int32_t vs_tx_stopped; 182 u_int32_t vs_tx_overrun; 183 u_int32_t vs_intr; 184 u_int32_t vs_rx_packets; 185 u_int32_t vs_rx_underrun; 186 } __packed; 187 188 #define VIC_NRXRINGS 2 189 190 struct vic_data { 191 u_int32_t vd_magic; 192 193 struct { 194 u_int32_t length; 195 u_int32_t nextidx; 196 } vd_rx[VIC_NRXRINGS]; 197 198 u_int32_t vd_irq; 199 u_int32_t vd_iff; 200 201 u_int32_t vd_mcastfil[VIC_CMD_MCASTFIL_LENGTH]; 202 203 u_int32_t vd_reserved1[1]; 204 205 u_int32_t vd_tx_length; 206 u_int32_t vd_tx_curidx; 207 u_int32_t vd_tx_nextidx; 208 u_int32_t vd_tx_stopped; 209 u_int32_t vd_tx_triggerlvl; 210 u_int32_t vd_tx_queued; 211 u_int32_t vd_tx_minlength; 212 213 u_int32_t vd_reserved2[6]; 214 215 u_int32_t vd_rx_saved_nextidx[VIC_NRXRINGS]; 216 u_int32_t vd_tx_saved_nextidx; 217 218 u_int32_t vd_length; 219 u_int32_t vd_rx_offset[VIC_NRXRINGS]; 220 u_int32_t vd_tx_offset; 221 u_int32_t vd_debug; 222 u_int32_t vd_tx_physaddr; 223 u_int32_t vd_tx_physaddr_length; 224 u_int32_t vd_tx_maxlength; 225 226 struct vic_stats vd_stats; 227 } __packed; 228 229 #define VIC_OWNER_DRIVER 0 230 #define VIC_OWNER_DRIVER_PEND 1 231 #define VIC_OWNER_NIC 2 232 #define VIC_OWNER_NIC_PEND 3 233 234 #define VIC_JUMBO_FRAMELEN 9018 235 #define VIC_JUMBO_MTU (VIC_JUMBO_FRAMELEN - ETHER_HDR_LEN - ETHER_CRC_LEN) 236 237 #define VIC_NBUF 100 238 #define VIC_NBUF_MAX 128 239 #define VIC_MAX_SCATTER 1 /* 8? */ 240 #define VIC_QUEUE_SIZE VIC_NBUF_MAX 241 #define VIC_INC(_x, _y) (_x) = ((_x) + 1) % (_y) 242 #define VIC_TX_TIMEOUT 5 243 244 #define VIC_MIN_FRAMELEN (ETHER_MIN_LEN - ETHER_CRC_LEN) 245 246 #define VIC_TXURN_WARN(_sc) ((_sc)->sc_txpending >= ((_sc)->sc_ntxbuf - 5)) 247 #define VIC_TXURN(_sc) ((_sc)->sc_txpending >= (_sc)->sc_ntxbuf) 248 249 struct vic_rxbuf { 250 bus_dmamap_t rxb_dmamap; 251 struct mbuf *rxb_m; 252 }; 253 254 struct vic_txbuf { 255 bus_dmamap_t txb_dmamap; 256 struct mbuf *txb_m; 257 }; 258 259 struct vic_softc { 260 struct device sc_dev; 261 262 pci_chipset_tag_t sc_pc; 263 pcitag_t sc_tag; 264 265 bus_space_tag_t sc_iot; 266 bus_space_handle_t sc_ioh; 267 bus_size_t sc_ios; 268 bus_dma_tag_t sc_dmat; 269 270 void *sc_ih; 271 272 struct timeout sc_tick; 273 274 struct arpcom sc_ac; 275 struct ifmedia sc_media; 276 277 u_int32_t sc_nrxbuf; 278 u_int32_t sc_ntxbuf; 279 u_int32_t sc_cap; 280 u_int32_t sc_feature; 281 u_int8_t sc_lladdr[ETHER_ADDR_LEN]; 282 283 bus_dmamap_t sc_dma_map; 284 bus_dma_segment_t sc_dma_seg; 285 size_t sc_dma_size; 286 caddr_t sc_dma_kva; 287 #define VIC_DMA_DVA(_sc) ((_sc)->sc_dma_map->dm_segs[0].ds_addr) 288 #define VIC_DMA_KVA(_sc) ((void *)(_sc)->sc_dma_kva) 289 290 struct vic_data *sc_data; 291 292 struct { 293 struct vic_rxbuf *bufs; 294 struct vic_rxdesc *slots; 295 int end; 296 int len; 297 u_int pktlen; 298 } sc_rxq[VIC_NRXRINGS]; 299 300 struct vic_txbuf *sc_txbuf; 301 struct vic_txdesc *sc_txq; 302 volatile u_int sc_txpending; 303 }; 304 305 struct cfdriver vic_cd = { 306 NULL, "vic", DV_IFNET 307 }; 308 309 int vic_match(struct device *, void *, void *); 310 void vic_attach(struct device *, struct device *, void *); 311 312 struct cfattach vic_ca = { 313 sizeof(struct vic_softc), vic_match, vic_attach 314 }; 315 316 int vic_intr(void *); 317 318 int vic_query(struct vic_softc *); 319 int vic_alloc_data(struct vic_softc *); 320 int vic_init_data(struct vic_softc *sc); 321 int vic_uninit_data(struct vic_softc *sc); 322 323 u_int32_t vic_read(struct vic_softc *, bus_size_t); 324 void vic_write(struct vic_softc *, bus_size_t, u_int32_t); 325 326 u_int32_t vic_read_cmd(struct vic_softc *, u_int32_t); 327 328 int vic_alloc_dmamem(struct vic_softc *); 329 void vic_free_dmamem(struct vic_softc *); 330 331 void vic_link_state(struct vic_softc *); 332 void vic_rx_fill(struct vic_softc *, int); 333 void vic_rx_proc(struct vic_softc *, int); 334 void vic_tx_proc(struct vic_softc *); 335 void vic_iff(struct vic_softc *); 336 void vic_getlladdr(struct vic_softc *); 337 void vic_setlladdr(struct vic_softc *); 338 int vic_media_change(struct ifnet *); 339 void vic_media_status(struct ifnet *, struct ifmediareq *); 340 void vic_start(struct ifnet *); 341 int vic_load_txb(struct vic_softc *, struct vic_txbuf *, 342 struct mbuf *); 343 void vic_watchdog(struct ifnet *); 344 int vic_ioctl(struct ifnet *, u_long, caddr_t); 345 void vic_init(struct ifnet *); 346 void vic_stop(struct ifnet *); 347 void vic_tick(void *); 348 349 #define DEVNAME(_s) ((_s)->sc_dev.dv_xname) 350 351 struct mbuf *vic_alloc_mbuf(struct vic_softc *, bus_dmamap_t, u_int); 352 353 const struct pci_matchid vic_devices[] = { 354 { PCI_VENDOR_VMWARE, PCI_PRODUCT_VMWARE_NET } 355 }; 356 357 int 358 vic_match(struct device *parent, void *match, void *aux) 359 { 360 struct pci_attach_args *pa = aux; 361 pcireg_t memtype; 362 bus_size_t pcisize; 363 bus_addr_t pciaddr; 364 365 switch (pa->pa_id) { 366 case PCI_ID_CODE(PCI_VENDOR_VMWARE, PCI_PRODUCT_VMWARE_NET): 367 return (1); 368 369 case PCI_ID_CODE(PCI_VENDOR_AMD, PCI_PRODUCT_AMD_PCNET_PCI): 370 memtype = pci_mapreg_type(pa->pa_pc, pa->pa_tag, VIC_PCI_BAR); 371 if (pci_mapreg_info(pa->pa_pc, pa->pa_tag, VIC_PCI_BAR, 372 memtype, &pciaddr, &pcisize, NULL) != 0) 373 break; 374 375 if (pcisize > VIC_LANCE_MINLEN) 376 return (2); 377 378 break; 379 } 380 381 return (0); 382 } 383 384 void 385 vic_attach(struct device *parent, struct device *self, void *aux) 386 { 387 struct vic_softc *sc = (struct vic_softc *)self; 388 struct pci_attach_args *pa = aux; 389 bus_space_handle_t ioh; 390 pcireg_t r; 391 pci_intr_handle_t ih; 392 struct ifnet *ifp; 393 394 sc->sc_pc = pa->pa_pc; 395 sc->sc_tag = pa->pa_tag; 396 sc->sc_dmat = pa->pa_dmat; 397 398 r = pci_mapreg_type(sc->sc_pc, sc->sc_tag, VIC_PCI_BAR); 399 if (pci_mapreg_map(pa, VIC_PCI_BAR, r, 0, &sc->sc_iot, 400 &ioh, NULL, &sc->sc_ios, 0) != 0) { 401 printf(": unable to map system interface register\n"); 402 return; 403 } 404 405 switch (pa->pa_id) { 406 case PCI_ID_CODE(PCI_VENDOR_VMWARE, PCI_PRODUCT_VMWARE_NET): 407 if (bus_space_subregion(sc->sc_iot, ioh, 0, sc->sc_ios, 408 &sc->sc_ioh) != 0) { 409 printf(": unable to map register window\n"); 410 goto unmap; 411 } 412 break; 413 414 case PCI_ID_CODE(PCI_VENDOR_AMD, PCI_PRODUCT_AMD_PCNET_PCI): 415 if (bus_space_subregion(sc->sc_iot, ioh, 416 VIC_LANCE_SIZE + VIC_MORPH_SIZE, VIC_VMXNET_SIZE, 417 &sc->sc_ioh) != 0) { 418 printf(": unable to map register window\n"); 419 goto unmap; 420 } 421 422 bus_space_barrier(sc->sc_iot, ioh, VIC_LANCE_SIZE, 4, 423 BUS_SPACE_BARRIER_READ); 424 r = bus_space_read_4(sc->sc_iot, ioh, VIC_LANCE_SIZE); 425 426 if ((r & VIC_MORPH_MASK) == VIC_MORPH_VMXNET) 427 break; 428 if ((r & VIC_MORPH_MASK) != VIC_MORPH_LANCE) { 429 printf(": unexpect morph value (0x%08x)\n", r); 430 goto unmap; 431 } 432 433 r &= ~VIC_MORPH_MASK; 434 r |= VIC_MORPH_VMXNET; 435 436 bus_space_write_4(sc->sc_iot, ioh, VIC_LANCE_SIZE, r); 437 bus_space_barrier(sc->sc_iot, ioh, VIC_LANCE_SIZE, 4, 438 BUS_SPACE_BARRIER_WRITE); 439 440 bus_space_barrier(sc->sc_iot, ioh, VIC_LANCE_SIZE, 4, 441 BUS_SPACE_BARRIER_READ); 442 r = bus_space_read_4(sc->sc_iot, ioh, VIC_LANCE_SIZE); 443 444 if ((r & VIC_MORPH_MASK) != VIC_MORPH_VMXNET) { 445 printf(": unable to morph vlance chip\n"); 446 goto unmap; 447 } 448 449 break; 450 } 451 452 if (pci_intr_map(pa, &ih) != 0) { 453 printf(": unable to map interrupt\n"); 454 goto unmap; 455 } 456 457 sc->sc_ih = pci_intr_establish(pa->pa_pc, ih, IPL_NET, 458 vic_intr, sc, DEVNAME(sc)); 459 if (sc->sc_ih == NULL) { 460 printf(": unable to establish interrupt\n"); 461 goto unmap; 462 } 463 464 if (vic_query(sc) != 0) { 465 /* error printed by vic_query */ 466 goto unmap; 467 } 468 469 if (vic_alloc_data(sc) != 0) { 470 /* error printed by vic_alloc */ 471 goto unmap; 472 } 473 474 timeout_set(&sc->sc_tick, vic_tick, sc); 475 476 bcopy(sc->sc_lladdr, sc->sc_ac.ac_enaddr, ETHER_ADDR_LEN); 477 478 ifp = &sc->sc_ac.ac_if; 479 ifp->if_softc = sc; 480 ifp->if_flags = IFF_BROADCAST | IFF_SIMPLEX | IFF_MULTICAST; 481 ifp->if_ioctl = vic_ioctl; 482 ifp->if_start = vic_start; 483 ifp->if_watchdog = vic_watchdog; 484 ifp->if_hardmtu = VIC_JUMBO_MTU; 485 strlcpy(ifp->if_xname, DEVNAME(sc), IFNAMSIZ); 486 IFQ_SET_MAXLEN(&ifp->if_snd, sc->sc_ntxbuf - 1); 487 IFQ_SET_READY(&ifp->if_snd); 488 489 m_clsetwms(ifp, MCLBYTES, 2, sc->sc_nrxbuf - 1); 490 m_clsetwms(ifp, 4096, 2, sc->sc_nrxbuf - 1); 491 492 ifp->if_capabilities = IFCAP_VLAN_MTU; 493 494 #if 0 495 /* XXX interface capabilities */ 496 if (sc->sc_cap & VIC_CMD_HWCAP_VLAN) 497 ifp->if_capabilities |= IFCAP_VLAN_HWTAGGING; 498 if (sc->sc_cap & VIC_CMD_HWCAP_CSUM) 499 ifp->if_capabilities |= IFCAP_CSUM_IPv4 | IFCAP_CSUM_TCPv4 | 500 IFCAP_CSUM_UDPv4; 501 #endif 502 503 ifmedia_init(&sc->sc_media, 0, vic_media_change, vic_media_status); 504 ifmedia_add(&sc->sc_media, IFM_ETHER | IFM_AUTO, 0, NULL); 505 ifmedia_set(&sc->sc_media, IFM_ETHER | IFM_AUTO); 506 507 if_attach(ifp); 508 ether_ifattach(ifp); 509 510 printf(": %s, address %s\n", pci_intr_string(pa->pa_pc, ih), 511 ether_sprintf(sc->sc_lladdr)); 512 513 #ifdef VIC_DEBUG 514 printf("%s: feature 0x%8x, cap 0x%8x, rx/txbuf %d/%d\n", DEVNAME(sc), 515 sc->sc_feature, sc->sc_cap, sc->sc_nrxbuf, sc->sc_ntxbuf); 516 #endif 517 518 return; 519 520 unmap: 521 bus_space_unmap(sc->sc_iot, ioh, sc->sc_ios); 522 sc->sc_ios = 0; 523 } 524 525 int 526 vic_query(struct vic_softc *sc) 527 { 528 u_int32_t major, minor; 529 530 major = vic_read(sc, VIC_VERSION_MAJOR); 531 minor = vic_read(sc, VIC_VERSION_MINOR); 532 533 /* Check for a supported version */ 534 if ((major & VIC_VERSION_MAJOR_M) != 535 (VIC_MAGIC & VIC_VERSION_MAJOR_M)) { 536 printf(": magic mismatch\n"); 537 return (1); 538 } 539 540 if (VIC_MAGIC > major || VIC_MAGIC < minor) { 541 printf(": unsupported version (%X)\n", 542 major & ~VIC_VERSION_MAJOR_M); 543 return (1); 544 } 545 546 sc->sc_nrxbuf = vic_read_cmd(sc, VIC_CMD_NUM_Rx_BUF); 547 sc->sc_ntxbuf = vic_read_cmd(sc, VIC_CMD_NUM_Tx_BUF); 548 sc->sc_feature = vic_read_cmd(sc, VIC_CMD_FEATURE); 549 sc->sc_cap = vic_read_cmd(sc, VIC_CMD_HWCAP); 550 551 vic_getlladdr(sc); 552 553 if (sc->sc_nrxbuf > VIC_NBUF_MAX || sc->sc_nrxbuf == 0) 554 sc->sc_nrxbuf = VIC_NBUF; 555 if (sc->sc_ntxbuf > VIC_NBUF_MAX || sc->sc_ntxbuf == 0) 556 sc->sc_ntxbuf = VIC_NBUF; 557 558 return (0); 559 } 560 561 int 562 vic_alloc_data(struct vic_softc *sc) 563 { 564 u_int8_t *kva; 565 u_int offset; 566 struct vic_rxdesc *rxd; 567 int i, q; 568 569 sc->sc_rxq[0].pktlen = MCLBYTES; 570 sc->sc_rxq[1].pktlen = 4096; 571 572 for (q = 0; q < VIC_NRXRINGS; q++) { 573 sc->sc_rxq[q].bufs = malloc(sizeof(struct vic_rxbuf) * 574 sc->sc_nrxbuf, M_DEVBUF, M_NOWAIT | M_ZERO); 575 if (sc->sc_rxq[q].bufs == NULL) { 576 printf(": unable to allocate rxbuf for ring %d\n", q); 577 goto freerx; 578 } 579 } 580 581 sc->sc_txbuf = malloc(sizeof(struct vic_txbuf) * sc->sc_ntxbuf, 582 M_DEVBUF, M_NOWAIT); 583 if (sc->sc_txbuf == NULL) { 584 printf(": unable to allocate txbuf\n"); 585 goto freerx; 586 } 587 588 sc->sc_dma_size = sizeof(struct vic_data) + 589 (sc->sc_nrxbuf * VIC_NRXRINGS) * sizeof(struct vic_rxdesc) + 590 sc->sc_ntxbuf * sizeof(struct vic_txdesc); 591 592 if (vic_alloc_dmamem(sc) != 0) { 593 printf(": unable to allocate dma region\n"); 594 goto freetx; 595 } 596 kva = VIC_DMA_KVA(sc); 597 598 /* set up basic vic data */ 599 sc->sc_data = VIC_DMA_KVA(sc); 600 601 sc->sc_data->vd_magic = VIC_MAGIC; 602 sc->sc_data->vd_length = sc->sc_dma_size; 603 604 offset = sizeof(struct vic_data); 605 606 /* set up the rx rings */ 607 608 for (q = 0; q < VIC_NRXRINGS; q++) { 609 sc->sc_rxq[q].slots = (struct vic_rxdesc *)&kva[offset]; 610 sc->sc_data->vd_rx_offset[q] = offset; 611 sc->sc_data->vd_rx[q].length = sc->sc_nrxbuf; 612 613 for (i = 0; i < sc->sc_nrxbuf; i++) { 614 rxd = &sc->sc_rxq[q].slots[i]; 615 616 rxd->rx_physaddr = 0; 617 rxd->rx_buflength = 0; 618 rxd->rx_length = 0; 619 rxd->rx_owner = VIC_OWNER_DRIVER; 620 621 offset += sizeof(struct vic_rxdesc); 622 } 623 } 624 625 /* set up the tx ring */ 626 sc->sc_txq = (struct vic_txdesc *)&kva[offset]; 627 628 sc->sc_data->vd_tx_offset = offset; 629 sc->sc_data->vd_tx_length = sc->sc_ntxbuf; 630 631 return (0); 632 freetx: 633 free(sc->sc_txbuf, M_DEVBUF); 634 q = VIC_NRXRINGS; 635 freerx: 636 while (q--) 637 free(sc->sc_rxq[q].bufs, M_DEVBUF); 638 639 return (1); 640 } 641 642 void 643 vic_rx_fill(struct vic_softc *sc, int q) 644 { 645 struct vic_rxbuf *rxb; 646 struct vic_rxdesc *rxd; 647 648 while (sc->sc_rxq[q].len < sc->sc_data->vd_rx[q].length) { 649 rxb = &sc->sc_rxq[q].bufs[sc->sc_rxq[q].end]; 650 rxd = &sc->sc_rxq[q].slots[sc->sc_rxq[q].end]; 651 652 rxb->rxb_m = vic_alloc_mbuf(sc, rxb->rxb_dmamap, 653 sc->sc_rxq[q].pktlen); 654 if (rxb->rxb_m == NULL) 655 break; 656 657 bus_dmamap_sync(sc->sc_dmat, rxb->rxb_dmamap, 0, 658 rxb->rxb_m->m_pkthdr.len, BUS_DMASYNC_PREREAD); 659 660 rxd->rx_physaddr = rxb->rxb_dmamap->dm_segs[0].ds_addr; 661 rxd->rx_buflength = rxb->rxb_m->m_pkthdr.len; 662 rxd->rx_length = 0; 663 rxd->rx_owner = VIC_OWNER_NIC; 664 665 VIC_INC(sc->sc_rxq[q].end, sc->sc_data->vd_rx[q].length); 666 sc->sc_rxq[q].len++; 667 } 668 } 669 670 int 671 vic_init_data(struct vic_softc *sc) 672 { 673 struct vic_rxbuf *rxb; 674 struct vic_rxdesc *rxd; 675 struct vic_txbuf *txb; 676 677 int q, i; 678 679 for (q = 0; q < VIC_NRXRINGS; q++) { 680 for (i = 0; i < sc->sc_nrxbuf; i++) { 681 rxb = &sc->sc_rxq[q].bufs[i]; 682 rxd = &sc->sc_rxq[q].slots[i]; 683 684 if (bus_dmamap_create(sc->sc_dmat, 685 sc->sc_rxq[q].pktlen, 1, sc->sc_rxq[q].pktlen, 0, 686 BUS_DMA_NOWAIT, &rxb->rxb_dmamap) != 0) { 687 printf("%s: unable to create dmamap for " 688 "ring %d slot %d\n", DEVNAME(sc), q, i); 689 goto freerxbs; 690 } 691 692 /* scrub the ring */ 693 rxd->rx_physaddr = 0; 694 rxd->rx_buflength = 0; 695 rxd->rx_length = 0; 696 rxd->rx_owner = VIC_OWNER_DRIVER; 697 } 698 699 sc->sc_rxq[q].len = 0; 700 sc->sc_rxq[q].end = 0; 701 vic_rx_fill(sc, q); 702 } 703 704 for (i = 0; i < sc->sc_ntxbuf; i++) { 705 txb = &sc->sc_txbuf[i]; 706 if (bus_dmamap_create(sc->sc_dmat, VIC_JUMBO_FRAMELEN, 707 (sc->sc_cap & VIC_CMD_HWCAP_SG) ? VIC_SG_MAX : 1, 708 VIC_JUMBO_FRAMELEN, 0, BUS_DMA_NOWAIT, 709 &txb->txb_dmamap) != 0) { 710 printf("%s: unable to create dmamap for tx %d\n", 711 DEVNAME(sc), i); 712 goto freetxbs; 713 } 714 txb->txb_m = NULL; 715 } 716 717 return (0); 718 719 freetxbs: 720 while (i--) { 721 txb = &sc->sc_txbuf[i]; 722 bus_dmamap_destroy(sc->sc_dmat, txb->txb_dmamap); 723 } 724 725 i = sc->sc_nrxbuf; 726 q = VIC_NRXRINGS - 1; 727 freerxbs: 728 while (q >= 0) { 729 while (i--) { 730 rxb = &sc->sc_rxq[q].bufs[i]; 731 732 if (rxb->rxb_m != NULL) { 733 bus_dmamap_sync(sc->sc_dmat, rxb->rxb_dmamap, 734 0, rxb->rxb_m->m_pkthdr.len, 735 BUS_DMASYNC_POSTREAD); 736 bus_dmamap_unload(sc->sc_dmat, rxb->rxb_dmamap); 737 m_freem(rxb->rxb_m); 738 rxb->rxb_m = NULL; 739 } 740 bus_dmamap_destroy(sc->sc_dmat, rxb->rxb_dmamap); 741 } 742 q--; 743 } 744 745 return (1); 746 } 747 748 int 749 vic_uninit_data(struct vic_softc *sc) 750 { 751 struct vic_rxbuf *rxb; 752 struct vic_rxdesc *rxd; 753 struct vic_txbuf *txb; 754 755 int i, q; 756 757 for (q = 0; q < VIC_NRXRINGS; q++) { 758 for (i = 0; i < sc->sc_nrxbuf; i++) { 759 rxb = &sc->sc_rxq[q].bufs[i]; 760 rxd = &sc->sc_rxq[q].slots[i]; 761 762 if (rxb->rxb_m != NULL) { 763 bus_dmamap_sync(sc->sc_dmat, rxb->rxb_dmamap, 764 0, rxb->rxb_m->m_pkthdr.len, 765 BUS_DMASYNC_POSTREAD); 766 bus_dmamap_unload(sc->sc_dmat, rxb->rxb_dmamap); 767 m_freem(rxb->rxb_m); 768 rxb->rxb_m = NULL; 769 } 770 bus_dmamap_destroy(sc->sc_dmat, rxb->rxb_dmamap); 771 } 772 } 773 774 for (i = 0; i < sc->sc_ntxbuf; i++) { 775 txb = &sc->sc_txbuf[i]; 776 bus_dmamap_destroy(sc->sc_dmat, txb->txb_dmamap); 777 } 778 779 return (0); 780 } 781 782 void 783 vic_link_state(struct vic_softc *sc) 784 { 785 struct ifnet *ifp = &sc->sc_ac.ac_if; 786 u_int32_t status; 787 int link_state = LINK_STATE_DOWN; 788 789 status = vic_read(sc, VIC_STATUS); 790 if (status & VIC_STATUS_CONNECTED) 791 link_state = LINK_STATE_FULL_DUPLEX; 792 if (ifp->if_link_state != link_state) { 793 ifp->if_link_state = link_state; 794 if_link_state_change(ifp); 795 } 796 } 797 798 int 799 vic_intr(void *arg) 800 { 801 struct vic_softc *sc = (struct vic_softc *)arg; 802 int q; 803 804 for (q = 0; q < VIC_NRXRINGS; q++) 805 vic_rx_proc(sc, q); 806 vic_tx_proc(sc); 807 808 vic_write(sc, VIC_CMD, VIC_CMD_INTR_ACK); 809 810 return (1); 811 } 812 813 void 814 vic_rx_proc(struct vic_softc *sc, int q) 815 { 816 struct ifnet *ifp = &sc->sc_ac.ac_if; 817 struct vic_rxdesc *rxd; 818 struct vic_rxbuf *rxb; 819 struct mbuf *m; 820 int len, idx; 821 822 if ((ifp->if_flags & IFF_RUNNING) == 0) 823 return; 824 825 bus_dmamap_sync(sc->sc_dmat, sc->sc_dma_map, 0, sc->sc_dma_size, 826 BUS_DMASYNC_POSTREAD | BUS_DMASYNC_POSTWRITE); 827 828 while (sc->sc_rxq[q].len > 0) { 829 idx = sc->sc_data->vd_rx[q].nextidx; 830 if (idx >= sc->sc_data->vd_rx[q].length) { 831 ifp->if_ierrors++; 832 if (ifp->if_flags & IFF_DEBUG) 833 printf("%s: receive index error\n", 834 sc->sc_dev.dv_xname); 835 break; 836 } 837 838 rxd = &sc->sc_rxq[q].slots[idx]; 839 if (rxd->rx_owner != VIC_OWNER_DRIVER) 840 break; 841 842 rxb = &sc->sc_rxq[q].bufs[idx]; 843 844 if (rxb->rxb_m == NULL) { 845 ifp->if_ierrors++; 846 printf("%s: rxb %d has no mbuf\n", DEVNAME(sc), idx); 847 break; 848 } 849 850 bus_dmamap_sync(sc->sc_dmat, rxb->rxb_dmamap, 0, 851 rxb->rxb_m->m_pkthdr.len, BUS_DMASYNC_POSTREAD); 852 bus_dmamap_unload(sc->sc_dmat, rxb->rxb_dmamap); 853 854 m = rxb->rxb_m; 855 rxb->rxb_m = NULL; 856 len = rxd->rx_length; 857 858 if (len < VIC_MIN_FRAMELEN) { 859 m_freem(m); 860 861 ifp->if_iqdrops++; 862 goto nextp; 863 } 864 865 m->m_pkthdr.rcvif = ifp; 866 m->m_pkthdr.len = m->m_len = len; 867 868 ifp->if_ipackets++; 869 870 #if NBPFILTER > 0 871 if (ifp->if_bpf) 872 bpf_mtap(ifp->if_bpf, m, BPF_DIRECTION_IN); 873 #endif 874 875 ether_input_mbuf(ifp, m); 876 877 nextp: 878 sc->sc_rxq[q].len--; 879 VIC_INC(sc->sc_data->vd_rx[q].nextidx, 880 sc->sc_data->vd_rx[q].length); 881 } 882 883 vic_rx_fill(sc, q); 884 885 bus_dmamap_sync(sc->sc_dmat, sc->sc_dma_map, 0, sc->sc_dma_size, 886 BUS_DMASYNC_PREREAD | BUS_DMASYNC_PREWRITE); 887 } 888 889 void 890 vic_tx_proc(struct vic_softc *sc) 891 { 892 struct ifnet *ifp = &sc->sc_ac.ac_if; 893 struct vic_txdesc *txd; 894 struct vic_txbuf *txb; 895 int idx; 896 897 bus_dmamap_sync(sc->sc_dmat, sc->sc_dma_map, 0, sc->sc_dma_size, 898 BUS_DMASYNC_POSTREAD | BUS_DMASYNC_POSTWRITE); 899 900 while (sc->sc_txpending > 0) { 901 idx = sc->sc_data->vd_tx_curidx; 902 if (idx >= sc->sc_data->vd_tx_length) { 903 ifp->if_oerrors++; 904 break; 905 } 906 907 txd = &sc->sc_txq[idx]; 908 if (txd->tx_owner != VIC_OWNER_DRIVER) 909 break; 910 911 txb = &sc->sc_txbuf[idx]; 912 if (txb->txb_m == NULL) { 913 printf("%s: tx ring is corrupt\n", DEVNAME(sc)); 914 ifp->if_oerrors++; 915 break; 916 } 917 918 bus_dmamap_sync(sc->sc_dmat, txb->txb_dmamap, 0, 919 txb->txb_dmamap->dm_mapsize, BUS_DMASYNC_POSTWRITE); 920 bus_dmamap_unload(sc->sc_dmat, txb->txb_dmamap); 921 922 m_freem(txb->txb_m); 923 txb->txb_m = NULL; 924 ifp->if_flags &= ~IFF_OACTIVE; 925 926 sc->sc_txpending--; 927 sc->sc_data->vd_tx_stopped = 0; 928 929 VIC_INC(sc->sc_data->vd_tx_curidx, sc->sc_data->vd_tx_length); 930 } 931 932 bus_dmamap_sync(sc->sc_dmat, sc->sc_dma_map, 0, sc->sc_dma_size, 933 BUS_DMASYNC_PREREAD | BUS_DMASYNC_PREWRITE); 934 935 vic_start(ifp); 936 } 937 938 void 939 vic_iff(struct vic_softc *sc) 940 { 941 struct arpcom *ac = &sc->sc_ac; 942 struct ifnet *ifp = &sc->sc_ac.ac_if; 943 struct ether_multi *enm; 944 struct ether_multistep step; 945 u_int32_t crc; 946 u_int16_t *mcastfil = (u_int16_t *)sc->sc_data->vd_mcastfil; 947 u_int flags = 0; 948 949 bzero(&sc->sc_data->vd_mcastfil, sizeof(sc->sc_data->vd_mcastfil)); 950 ifp->if_flags &= ~IFF_ALLMULTI; 951 952 if ((ifp->if_flags & IFF_RUNNING) == 0) 953 goto domulti; 954 if (ifp->if_flags & IFF_PROMISC) 955 goto allmulti; 956 957 ETHER_FIRST_MULTI(step, ac, enm); 958 while (enm != NULL) { 959 if (bcmp(enm->enm_addrlo, enm->enm_addrhi, ETHER_ADDR_LEN)) 960 goto allmulti; 961 962 crc = ether_crc32_le(enm->enm_addrlo, ETHER_ADDR_LEN); 963 crc >>= 26; 964 mcastfil[crc >> 4] |= htole16(1 << (crc & 0xf)); 965 966 ETHER_NEXT_MULTI(step, enm); 967 } 968 969 goto domulti; 970 971 allmulti: 972 ifp->if_flags |= IFF_ALLMULTI; 973 memset(&sc->sc_data->vd_mcastfil, 0xff, 974 sizeof(sc->sc_data->vd_mcastfil)); 975 976 domulti: 977 vic_write(sc, VIC_CMD, VIC_CMD_MCASTFIL); 978 979 if (ifp->if_flags & IFF_RUNNING) { 980 flags = (ifp->if_flags & IFF_PROMISC) ? 981 VIC_CMD_IFF_PROMISC : 982 (VIC_CMD_IFF_BROADCAST | VIC_CMD_IFF_MULTICAST); 983 } 984 sc->sc_data->vd_iff = flags; 985 vic_write(sc, VIC_CMD, VIC_CMD_IFF); 986 } 987 988 void 989 vic_getlladdr(struct vic_softc *sc) 990 { 991 u_int32_t reg; 992 993 /* Get MAC address */ 994 reg = (sc->sc_cap & VIC_CMD_HWCAP_VPROM) ? VIC_VPROM : VIC_LLADDR; 995 996 bus_space_barrier(sc->sc_iot, sc->sc_ioh, reg, ETHER_ADDR_LEN, 997 BUS_SPACE_BARRIER_READ); 998 bus_space_read_region_1(sc->sc_iot, sc->sc_ioh, reg, sc->sc_lladdr, 999 ETHER_ADDR_LEN); 1000 1001 /* Update the MAC address register */ 1002 if (reg == VIC_VPROM) 1003 vic_setlladdr(sc); 1004 } 1005 1006 void 1007 vic_setlladdr(struct vic_softc *sc) 1008 { 1009 bus_space_write_region_1(sc->sc_iot, sc->sc_ioh, VIC_LLADDR, 1010 sc->sc_lladdr, ETHER_ADDR_LEN); 1011 bus_space_barrier(sc->sc_iot, sc->sc_ioh, VIC_LLADDR, ETHER_ADDR_LEN, 1012 BUS_SPACE_BARRIER_WRITE); 1013 } 1014 1015 int 1016 vic_media_change(struct ifnet *ifp) 1017 { 1018 /* Ignore */ 1019 return (0); 1020 } 1021 1022 void 1023 vic_media_status(struct ifnet *ifp, struct ifmediareq *imr) 1024 { 1025 struct vic_softc *sc = (struct vic_softc *)ifp->if_softc; 1026 1027 imr->ifm_active = IFM_ETHER | IFM_AUTO; 1028 imr->ifm_status = IFM_AVALID; 1029 1030 vic_link_state(sc); 1031 1032 if (LINK_STATE_IS_UP(ifp->if_link_state) && 1033 ifp->if_flags & IFF_UP) 1034 imr->ifm_status |= IFM_ACTIVE; 1035 } 1036 1037 void 1038 vic_start(struct ifnet *ifp) 1039 { 1040 struct vic_softc *sc; 1041 struct mbuf *m; 1042 struct vic_txbuf *txb; 1043 struct vic_txdesc *txd; 1044 struct vic_sg *sge; 1045 bus_dmamap_t dmap; 1046 int i, idx; 1047 int tx = 0; 1048 1049 if (!(ifp->if_flags & IFF_RUNNING)) 1050 return; 1051 1052 if (ifp->if_flags & IFF_OACTIVE) 1053 return; 1054 1055 if (IFQ_IS_EMPTY(&ifp->if_snd)) 1056 return; 1057 1058 sc = (struct vic_softc *)ifp->if_softc; 1059 1060 bus_dmamap_sync(sc->sc_dmat, sc->sc_dma_map, 0, sc->sc_dma_size, 1061 BUS_DMASYNC_POSTREAD | BUS_DMASYNC_POSTWRITE); 1062 1063 for (;;) { 1064 if (VIC_TXURN(sc)) { 1065 ifp->if_flags |= IFF_OACTIVE; 1066 break; 1067 } 1068 1069 IFQ_POLL(&ifp->if_snd, m); 1070 if (m == NULL) 1071 break; 1072 1073 idx = sc->sc_data->vd_tx_nextidx; 1074 if (idx >= sc->sc_data->vd_tx_length) { 1075 printf("%s: tx idx is corrupt\n", DEVNAME(sc)); 1076 ifp->if_oerrors++; 1077 break; 1078 } 1079 1080 txd = &sc->sc_txq[idx]; 1081 txb = &sc->sc_txbuf[idx]; 1082 1083 if (txb->txb_m != NULL) { 1084 printf("%s: tx ring is corrupt\n", DEVNAME(sc)); 1085 sc->sc_data->vd_tx_stopped = 1; 1086 ifp->if_oerrors++; 1087 break; 1088 } 1089 1090 /* 1091 * we're committed to sending it now. if we cant map it into 1092 * dma memory then we drop it. 1093 */ 1094 IFQ_DEQUEUE(&ifp->if_snd, m); 1095 if (vic_load_txb(sc, txb, m) != 0) { 1096 m_freem(m); 1097 ifp->if_oerrors++; 1098 /* continue? */ 1099 break; 1100 } 1101 1102 #if NBPFILTER > 0 1103 if (ifp->if_bpf) 1104 bpf_mtap(ifp->if_bpf, txb->txb_m, BPF_DIRECTION_OUT); 1105 #endif 1106 1107 dmap = txb->txb_dmamap; 1108 txd->tx_flags = VIC_TX_FLAGS_KEEP; 1109 txd->tx_owner = VIC_OWNER_NIC; 1110 txd->tx_sa.sa_addr_type = VIC_SG_ADDR_PHYS; 1111 txd->tx_sa.sa_length = dmap->dm_nsegs; 1112 for (i = 0; i < dmap->dm_nsegs; i++) { 1113 sge = &txd->tx_sa.sa_sg[i]; 1114 sge->sg_length = dmap->dm_segs[i].ds_len; 1115 sge->sg_addr_low = dmap->dm_segs[i].ds_addr; 1116 } 1117 1118 if (VIC_TXURN_WARN(sc)) { 1119 txd->tx_flags |= VIC_TX_FLAGS_TXURN; 1120 } 1121 1122 bus_dmamap_sync(sc->sc_dmat, dmap, 0, dmap->dm_mapsize, 1123 BUS_DMASYNC_PREWRITE); 1124 1125 ifp->if_opackets++; 1126 sc->sc_txpending++; 1127 1128 VIC_INC(sc->sc_data->vd_tx_nextidx, sc->sc_data->vd_tx_length); 1129 1130 tx = 1; 1131 } 1132 1133 bus_dmamap_sync(sc->sc_dmat, sc->sc_dma_map, 0, sc->sc_dma_size, 1134 BUS_DMASYNC_PREREAD | BUS_DMASYNC_PREWRITE); 1135 1136 if (tx) 1137 vic_read(sc, VIC_Tx_ADDR); 1138 } 1139 1140 int 1141 vic_load_txb(struct vic_softc *sc, struct vic_txbuf *txb, struct mbuf *m) 1142 { 1143 bus_dmamap_t dmap = txb->txb_dmamap; 1144 struct mbuf *m0 = NULL; 1145 int error; 1146 1147 error = bus_dmamap_load_mbuf(sc->sc_dmat, dmap, m, BUS_DMA_NOWAIT); 1148 switch (error) { 1149 case 0: 1150 txb->txb_m = m; 1151 break; 1152 1153 case EFBIG: /* mbuf chain is too fragmented */ 1154 MGETHDR(m0, M_DONTWAIT, MT_DATA); 1155 if (m0 == NULL) 1156 return (ENOBUFS); 1157 if (m->m_pkthdr.len > MHLEN) { 1158 MCLGETI(m0, M_DONTWAIT, NULL, m->m_pkthdr.len); 1159 if (!(m0->m_flags & M_EXT)) { 1160 m_freem(m0); 1161 return (ENOBUFS); 1162 } 1163 } 1164 m_copydata(m, 0, m->m_pkthdr.len, mtod(m0, caddr_t)); 1165 m0->m_pkthdr.len = m0->m_len = m->m_pkthdr.len; 1166 error = bus_dmamap_load_mbuf(sc->sc_dmat, dmap, m0, 1167 BUS_DMA_NOWAIT); 1168 if (error != 0) { 1169 m_freem(m0); 1170 printf("%s: tx dmamap load error %d\n", DEVNAME(sc), 1171 error); 1172 return (ENOBUFS); 1173 } 1174 m_freem(m); 1175 txb->txb_m = m0; 1176 break; 1177 1178 default: 1179 printf("%s: tx dmamap load error %d\n", DEVNAME(sc), error); 1180 return (ENOBUFS); 1181 } 1182 1183 return (0); 1184 } 1185 1186 void 1187 vic_watchdog(struct ifnet *ifp) 1188 { 1189 #if 0 1190 struct vic_softc *sc = (struct vic_softc *)ifp->if_softc; 1191 1192 if (sc->sc_txpending && sc->sc_txtimeout > 0) { 1193 if (--sc->sc_txtimeout == 0) { 1194 printf("%s: device timeout\n", sc->sc_dev.dv_xname); 1195 ifp->if_flags &= ~IFF_RUNNING; 1196 vic_init(ifp); 1197 ifp->if_oerrors++; 1198 return; 1199 } 1200 } 1201 1202 if (!IFQ_IS_EMPTY(&ifp->if_snd)) 1203 vic_start(ifp); 1204 #endif 1205 } 1206 1207 int 1208 vic_ioctl(struct ifnet *ifp, u_long cmd, caddr_t data) 1209 { 1210 struct vic_softc *sc = (struct vic_softc *)ifp->if_softc; 1211 struct ifaddr *ifa = (struct ifaddr *)data; 1212 struct ifreq *ifr = (struct ifreq *)data; 1213 int s, error = 0; 1214 1215 s = splnet(); 1216 1217 switch (cmd) { 1218 case SIOCSIFADDR: 1219 ifp->if_flags |= IFF_UP; 1220 #ifdef INET 1221 if (ifa->ifa_addr->sa_family == AF_INET) 1222 arp_ifinit(&sc->sc_ac, ifa); 1223 #endif 1224 /* FALLTHROUGH */ 1225 case SIOCSIFFLAGS: 1226 if (ifp->if_flags & IFF_UP) { 1227 if (ifp->if_flags & IFF_RUNNING) 1228 vic_iff(sc); 1229 else 1230 vic_init(ifp); 1231 } else { 1232 if (ifp->if_flags & IFF_RUNNING) 1233 vic_stop(ifp); 1234 } 1235 break; 1236 1237 case SIOCGIFMEDIA: 1238 case SIOCSIFMEDIA: 1239 error = ifmedia_ioctl(ifp, ifr, &sc->sc_media, cmd); 1240 break; 1241 1242 default: 1243 error = ether_ioctl(ifp, &sc->sc_ac, cmd, data); 1244 } 1245 1246 if (error == ENETRESET) { 1247 if (ifp->if_flags & IFF_RUNNING) 1248 vic_iff(sc); 1249 error = 0; 1250 } 1251 1252 splx(s); 1253 return (error); 1254 } 1255 1256 void 1257 vic_init(struct ifnet *ifp) 1258 { 1259 struct vic_softc *sc = (struct vic_softc *)ifp->if_softc; 1260 int q; 1261 int s; 1262 1263 sc->sc_data->vd_tx_curidx = 0; 1264 sc->sc_data->vd_tx_nextidx = 0; 1265 sc->sc_data->vd_tx_stopped = sc->sc_data->vd_tx_queued = 0; 1266 sc->sc_data->vd_tx_saved_nextidx = 0; 1267 1268 for (q = 0; q < VIC_NRXRINGS; q++) { 1269 sc->sc_data->vd_rx[q].nextidx = 0; 1270 sc->sc_data->vd_rx_saved_nextidx[q] = 0; 1271 } 1272 1273 if (vic_init_data(sc) != 0) 1274 return; 1275 1276 bus_dmamap_sync(sc->sc_dmat, sc->sc_dma_map, 0, sc->sc_dma_size, 1277 BUS_DMASYNC_PREREAD | BUS_DMASYNC_PREWRITE); 1278 1279 s = splnet(); 1280 1281 vic_write(sc, VIC_DATA_ADDR, VIC_DMA_DVA(sc)); 1282 vic_write(sc, VIC_DATA_LENGTH, sc->sc_dma_size); 1283 1284 ifp->if_flags |= IFF_RUNNING; 1285 ifp->if_flags &= ~IFF_OACTIVE; 1286 1287 vic_iff(sc); 1288 vic_write(sc, VIC_CMD, VIC_CMD_INTR_ENABLE); 1289 1290 splx(s); 1291 1292 timeout_add_sec(&sc->sc_tick, 1); 1293 } 1294 1295 void 1296 vic_stop(struct ifnet *ifp) 1297 { 1298 struct vic_softc *sc = (struct vic_softc *)ifp->if_softc; 1299 int s; 1300 1301 s = splnet(); 1302 1303 timeout_del(&sc->sc_tick); 1304 1305 ifp->if_flags &= ~(IFF_RUNNING | IFF_OACTIVE); 1306 1307 bus_dmamap_sync(sc->sc_dmat, sc->sc_dma_map, 0, sc->sc_dma_size, 1308 BUS_DMASYNC_POSTREAD | BUS_DMASYNC_POSTWRITE); 1309 1310 /* XXX wait for tx to complete */ 1311 while (sc->sc_txpending > 0) { 1312 splx(s); 1313 delay(1000); 1314 s = splnet(); 1315 } 1316 1317 sc->sc_data->vd_tx_stopped = 1; 1318 1319 vic_write(sc, VIC_CMD, VIC_CMD_INTR_DISABLE); 1320 1321 vic_iff(sc); 1322 vic_write(sc, VIC_DATA_ADDR, 0); 1323 1324 vic_uninit_data(sc); 1325 1326 splx(s); 1327 } 1328 1329 struct mbuf * 1330 vic_alloc_mbuf(struct vic_softc *sc, bus_dmamap_t map, u_int pktlen) 1331 { 1332 struct mbuf *m = NULL; 1333 1334 m = MCLGETI(NULL, M_DONTWAIT, &sc->sc_ac.ac_if, pktlen); 1335 if (!m) 1336 return (NULL); 1337 m->m_data += ETHER_ALIGN; 1338 m->m_len = m->m_pkthdr.len = pktlen - ETHER_ALIGN; 1339 1340 if (bus_dmamap_load_mbuf(sc->sc_dmat, map, m, BUS_DMA_NOWAIT) != 0) { 1341 printf("%s: could not load mbuf DMA map\n", DEVNAME(sc)); 1342 m_freem(m); 1343 return (NULL); 1344 } 1345 1346 return (m); 1347 } 1348 1349 void 1350 vic_tick(void *arg) 1351 { 1352 struct vic_softc *sc = (struct vic_softc *)arg; 1353 1354 vic_link_state(sc); 1355 1356 timeout_add_sec(&sc->sc_tick, 1); 1357 } 1358 1359 u_int32_t 1360 vic_read(struct vic_softc *sc, bus_size_t r) 1361 { 1362 bus_space_barrier(sc->sc_iot, sc->sc_ioh, r, 4, 1363 BUS_SPACE_BARRIER_READ); 1364 return (bus_space_read_4(sc->sc_iot, sc->sc_ioh, r)); 1365 } 1366 1367 void 1368 vic_write(struct vic_softc *sc, bus_size_t r, u_int32_t v) 1369 { 1370 bus_space_write_4(sc->sc_iot, sc->sc_ioh, r, v); 1371 bus_space_barrier(sc->sc_iot, sc->sc_ioh, r, 4, 1372 BUS_SPACE_BARRIER_WRITE); 1373 } 1374 1375 u_int32_t 1376 vic_read_cmd(struct vic_softc *sc, u_int32_t cmd) 1377 { 1378 vic_write(sc, VIC_CMD, cmd); 1379 return (vic_read(sc, VIC_CMD)); 1380 } 1381 1382 int 1383 vic_alloc_dmamem(struct vic_softc *sc) 1384 { 1385 int nsegs; 1386 1387 if (bus_dmamap_create(sc->sc_dmat, sc->sc_dma_size, 1, 1388 sc->sc_dma_size, 0, BUS_DMA_NOWAIT | BUS_DMA_ALLOCNOW, 1389 &sc->sc_dma_map) != 0) 1390 goto err; 1391 1392 if (bus_dmamem_alloc(sc->sc_dmat, sc->sc_dma_size, 16, 0, 1393 &sc->sc_dma_seg, 1, &nsegs, BUS_DMA_NOWAIT) != 0) 1394 goto destroy; 1395 1396 if (bus_dmamem_map(sc->sc_dmat, &sc->sc_dma_seg, nsegs, 1397 sc->sc_dma_size, &sc->sc_dma_kva, BUS_DMA_NOWAIT) != 0) 1398 goto free; 1399 1400 if (bus_dmamap_load(sc->sc_dmat, sc->sc_dma_map, sc->sc_dma_kva, 1401 sc->sc_dma_size, NULL, BUS_DMA_NOWAIT) != 0) 1402 goto unmap; 1403 1404 bzero(sc->sc_dma_kva, sc->sc_dma_size); 1405 1406 return (0); 1407 1408 unmap: 1409 bus_dmamem_unmap(sc->sc_dmat, sc->sc_dma_kva, sc->sc_dma_size); 1410 free: 1411 bus_dmamem_free(sc->sc_dmat, &sc->sc_dma_seg, 1); 1412 destroy: 1413 bus_dmamap_destroy(sc->sc_dmat, sc->sc_dma_map); 1414 err: 1415 return (1); 1416 } 1417 1418 void 1419 vic_free_dmamem(struct vic_softc *sc) 1420 { 1421 bus_dmamap_unload(sc->sc_dmat, sc->sc_dma_map); 1422 bus_dmamem_unmap(sc->sc_dmat, sc->sc_dma_kva, sc->sc_dma_size); 1423 bus_dmamem_free(sc->sc_dmat, &sc->sc_dma_seg, 1); 1424 bus_dmamap_destroy(sc->sc_dmat, sc->sc_dma_map); 1425 } 1426