1 /* $OpenBSD: if_vge.c,v 1.51 2011/06/22 16:44:27 tedu Exp $ */ 2 /* $FreeBSD: if_vge.c,v 1.3 2004/09/11 22:13:25 wpaul Exp $ */ 3 /* 4 * Copyright (c) 2004 5 * Bill Paul <wpaul@windriver.com>. All rights reserved. 6 * 7 * Redistribution and use in source and binary forms, with or without 8 * modification, are permitted provided that the following conditions 9 * are met: 10 * 1. Redistributions of source code must retain the above copyright 11 * notice, this list of conditions and the following disclaimer. 12 * 2. Redistributions in binary form must reproduce the above copyright 13 * notice, this list of conditions and the following disclaimer in the 14 * documentation and/or other materials provided with the distribution. 15 * 3. All advertising materials mentioning features or use of this software 16 * must display the following acknowledgement: 17 * This product includes software developed by Bill Paul. 18 * 4. Neither the name of the author nor the names of any co-contributors 19 * may be used to endorse or promote products derived from this software 20 * without specific prior written permission. 21 * 22 * THIS SOFTWARE IS PROVIDED BY Bill Paul AND CONTRIBUTORS ``AS IS'' AND 23 * ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE 24 * IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE 25 * ARE DISCLAIMED. IN NO EVENT SHALL Bill Paul OR THE VOICES IN HIS HEAD 26 * BE LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR 27 * CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF 28 * SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS 29 * INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN 30 * CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) 31 * ARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF 32 * THE POSSIBILITY OF SUCH DAMAGE. 33 */ 34 35 /* 36 * VIA Networking Technologies VT612x PCI gigabit ethernet NIC driver. 37 * 38 * Written by Bill Paul <wpaul@windriver.com> 39 * Senior Networking Software Engineer 40 * Wind River Systems 41 * 42 * Ported to OpenBSD by Peter Valchev <pvalchev@openbsd.org> 43 */ 44 45 /* 46 * The VIA Networking VT6122 is a 32bit, 33/66MHz PCI device that 47 * combines a tri-speed ethernet MAC and PHY, with the following 48 * features: 49 * 50 * o Jumbo frame support up to 16K 51 * o Transmit and receive flow control 52 * o IPv4 checksum offload 53 * o VLAN tag insertion and stripping 54 * o TCP large send 55 * o 64-bit multicast hash table filter 56 * o 64 entry CAM filter 57 * o 16K RX FIFO and 48K TX FIFO memory 58 * o Interrupt moderation 59 * 60 * The VT6122 supports up to four transmit DMA queues. The descriptors 61 * in the transmit ring can address up to 7 data fragments; frames which 62 * span more than 7 data buffers must be coalesced, but in general the 63 * BSD TCP/IP stack rarely generates frames more than 2 or 3 fragments 64 * long. The receive descriptors address only a single buffer. 65 * 66 * There are two peculiar design issues with the VT6122. One is that 67 * receive data buffers must be aligned on a 32-bit boundary. This is 68 * not a problem where the VT6122 is used as a LOM device in x86-based 69 * systems, but on architectures that generate unaligned access traps, we 70 * have to do some copying. 71 * 72 * The other issue has to do with the way 64-bit addresses are handled. 73 * The DMA descriptors only allow you to specify 48 bits of addressing 74 * information. The remaining 16 bits are specified using one of the 75 * I/O registers. If you only have a 32-bit system, then this isn't 76 * an issue, but if you have a 64-bit system and more than 4GB of 77 * memory, you must have to make sure your network data buffers reside 78 * in the same 48-bit 'segment.' 79 * 80 * Special thanks to Ryan Fu at VIA Networking for providing documentation 81 * and sample NICs for testing. 82 */ 83 84 #include "bpfilter.h" 85 #include "vlan.h" 86 87 #include <sys/param.h> 88 #include <sys/endian.h> 89 #include <sys/systm.h> 90 #include <sys/sockio.h> 91 #include <sys/mbuf.h> 92 #include <sys/malloc.h> 93 #include <sys/kernel.h> 94 #include <sys/device.h> 95 #include <sys/timeout.h> 96 #include <sys/socket.h> 97 98 #include <net/if.h> 99 #include <net/if_dl.h> 100 #include <net/if_media.h> 101 102 #ifdef INET 103 #include <netinet/in.h> 104 #include <netinet/in_systm.h> 105 #include <netinet/in_var.h> 106 #include <netinet/ip.h> 107 #include <netinet/if_ether.h> 108 #endif 109 110 #if NVLAN > 0 111 #include <net/if_types.h> 112 #include <net/if_vlan_var.h> 113 #endif 114 115 #if NBPFILTER > 0 116 #include <net/bpf.h> 117 #endif 118 119 #include <dev/mii/mii.h> 120 #include <dev/mii/miivar.h> 121 122 #include <dev/pci/pcireg.h> 123 #include <dev/pci/pcivar.h> 124 #include <dev/pci/pcidevs.h> 125 126 #include <dev/pci/if_vgereg.h> 127 #include <dev/pci/if_vgevar.h> 128 129 int vge_probe (struct device *, void *, void *); 130 void vge_attach (struct device *, struct device *, void *); 131 int vge_detach (struct device *, int); 132 133 int vge_encap (struct vge_softc *, struct mbuf *, int); 134 135 int vge_allocmem (struct vge_softc *); 136 void vge_freemem (struct vge_softc *); 137 int vge_newbuf (struct vge_softc *, int, struct mbuf *); 138 int vge_rx_list_init (struct vge_softc *); 139 int vge_tx_list_init (struct vge_softc *); 140 void vge_rxeof (struct vge_softc *); 141 void vge_txeof (struct vge_softc *); 142 int vge_intr (void *); 143 void vge_tick (void *); 144 void vge_start (struct ifnet *); 145 int vge_ioctl (struct ifnet *, u_long, caddr_t); 146 int vge_init (struct ifnet *); 147 void vge_stop (struct vge_softc *); 148 void vge_watchdog (struct ifnet *); 149 int vge_ifmedia_upd (struct ifnet *); 150 void vge_ifmedia_sts (struct ifnet *, struct ifmediareq *); 151 152 #ifdef VGE_EEPROM 153 void vge_eeprom_getword (struct vge_softc *, int, u_int16_t *); 154 #endif 155 void vge_read_eeprom (struct vge_softc *, caddr_t, int, int, int); 156 157 void vge_miipoll_start (struct vge_softc *); 158 void vge_miipoll_stop (struct vge_softc *); 159 int vge_miibus_readreg (struct device *, int, int); 160 void vge_miibus_writereg (struct device *, int, int, int); 161 void vge_miibus_statchg (struct device *); 162 163 void vge_cam_clear (struct vge_softc *); 164 int vge_cam_set (struct vge_softc *, uint8_t *); 165 void vge_setmulti (struct vge_softc *); 166 void vge_reset (struct vge_softc *); 167 168 struct cfattach vge_ca = { 169 sizeof(struct vge_softc), vge_probe, vge_attach, vge_detach 170 }; 171 172 struct cfdriver vge_cd = { 173 NULL, "vge", DV_IFNET 174 }; 175 176 #define VGE_PCI_LOIO 0x10 177 #define VGE_PCI_LOMEM 0x14 178 179 int vge_debug = 0; 180 #define DPRINTF(x) if (vge_debug) printf x 181 #define DPRINTFN(n, x) if (vge_debug >= (n)) printf x 182 183 const struct pci_matchid vge_devices[] = { 184 { PCI_VENDOR_VIATECH, PCI_PRODUCT_VIATECH_VT612x }, 185 }; 186 187 #ifdef VGE_EEPROM 188 /* 189 * Read a word of data stored in the EEPROM at address 'addr.' 190 */ 191 void 192 vge_eeprom_getword(struct vge_softc *sc, int addr, u_int16_t *dest) 193 { 194 int i; 195 u_int16_t word = 0; 196 197 /* 198 * Enter EEPROM embedded programming mode. In order to 199 * access the EEPROM at all, we first have to set the 200 * EELOAD bit in the CHIPCFG2 register. 201 */ 202 CSR_SETBIT_1(sc, VGE_CHIPCFG2, VGE_CHIPCFG2_EELOAD); 203 CSR_SETBIT_1(sc, VGE_EECSR, VGE_EECSR_EMBP/*|VGE_EECSR_ECS*/); 204 205 /* Select the address of the word we want to read */ 206 CSR_WRITE_1(sc, VGE_EEADDR, addr); 207 208 /* Issue read command */ 209 CSR_SETBIT_1(sc, VGE_EECMD, VGE_EECMD_ERD); 210 211 /* Wait for the done bit to be set. */ 212 for (i = 0; i < VGE_TIMEOUT; i++) { 213 if (CSR_READ_1(sc, VGE_EECMD) & VGE_EECMD_EDONE) 214 break; 215 } 216 217 if (i == VGE_TIMEOUT) { 218 printf("%s: EEPROM read timed out\n", sc->vge_dev.dv_xname); 219 *dest = 0; 220 return; 221 } 222 223 /* Read the result */ 224 word = CSR_READ_2(sc, VGE_EERDDAT); 225 226 /* Turn off EEPROM access mode. */ 227 CSR_CLRBIT_1(sc, VGE_EECSR, VGE_EECSR_EMBP/*|VGE_EECSR_ECS*/); 228 CSR_CLRBIT_1(sc, VGE_CHIPCFG2, VGE_CHIPCFG2_EELOAD); 229 230 *dest = word; 231 } 232 #endif 233 234 /* 235 * Read a sequence of words from the EEPROM. 236 */ 237 void 238 vge_read_eeprom(struct vge_softc *sc, caddr_t dest, int off, int cnt, 239 int swap) 240 { 241 int i; 242 #ifdef VGE_EEPROM 243 u_int16_t word = 0, *ptr; 244 245 for (i = 0; i < cnt; i++) { 246 vge_eeprom_getword(sc, off + i, &word); 247 ptr = (u_int16_t *)(dest + (i * 2)); 248 if (swap) 249 *ptr = ntohs(word); 250 else 251 *ptr = word; 252 } 253 #else 254 for (i = 0; i < ETHER_ADDR_LEN; i++) 255 dest[i] = CSR_READ_1(sc, VGE_PAR0 + i); 256 #endif 257 } 258 259 void 260 vge_miipoll_stop(struct vge_softc *sc) 261 { 262 int i; 263 264 CSR_WRITE_1(sc, VGE_MIICMD, 0); 265 266 for (i = 0; i < VGE_TIMEOUT; i++) { 267 DELAY(1); 268 if (CSR_READ_1(sc, VGE_MIISTS) & VGE_MIISTS_IIDL) 269 break; 270 } 271 272 if (i == VGE_TIMEOUT) 273 printf("%s: failed to idle MII autopoll\n", sc->vge_dev.dv_xname); 274 } 275 276 void 277 vge_miipoll_start(struct vge_softc *sc) 278 { 279 int i; 280 281 /* First, make sure we're idle. */ 282 283 CSR_WRITE_1(sc, VGE_MIICMD, 0); 284 CSR_WRITE_1(sc, VGE_MIIADDR, VGE_MIIADDR_SWMPL); 285 286 for (i = 0; i < VGE_TIMEOUT; i++) { 287 DELAY(1); 288 if (CSR_READ_1(sc, VGE_MIISTS) & VGE_MIISTS_IIDL) 289 break; 290 } 291 292 if (i == VGE_TIMEOUT) { 293 printf("%s: failed to idle MII autopoll\n", sc->vge_dev.dv_xname); 294 return; 295 } 296 297 /* Now enable auto poll mode. */ 298 299 CSR_WRITE_1(sc, VGE_MIICMD, VGE_MIICMD_MAUTO); 300 301 /* And make sure it started. */ 302 303 for (i = 0; i < VGE_TIMEOUT; i++) { 304 DELAY(1); 305 if ((CSR_READ_1(sc, VGE_MIISTS) & VGE_MIISTS_IIDL) == 0) 306 break; 307 } 308 309 if (i == VGE_TIMEOUT) 310 printf("%s: failed to start MII autopoll\n", sc->vge_dev.dv_xname); 311 } 312 313 int 314 vge_miibus_readreg(struct device *dev, int phy, int reg) 315 { 316 struct vge_softc *sc = (struct vge_softc *)dev; 317 int i, s; 318 u_int16_t rval = 0; 319 320 if (phy != (CSR_READ_1(sc, VGE_MIICFG) & 0x1F)) 321 return(0); 322 323 s = splnet(); 324 325 vge_miipoll_stop(sc); 326 327 /* Specify the register we want to read. */ 328 CSR_WRITE_1(sc, VGE_MIIADDR, reg); 329 330 /* Issue read command. */ 331 CSR_SETBIT_1(sc, VGE_MIICMD, VGE_MIICMD_RCMD); 332 333 /* Wait for the read command bit to self-clear. */ 334 for (i = 0; i < VGE_TIMEOUT; i++) { 335 DELAY(1); 336 if ((CSR_READ_1(sc, VGE_MIICMD) & VGE_MIICMD_RCMD) == 0) 337 break; 338 } 339 340 if (i == VGE_TIMEOUT) 341 printf("%s: MII read timed out\n", sc->vge_dev.dv_xname); 342 else 343 rval = CSR_READ_2(sc, VGE_MIIDATA); 344 345 vge_miipoll_start(sc); 346 splx(s); 347 348 return (rval); 349 } 350 351 void 352 vge_miibus_writereg(struct device *dev, int phy, int reg, int data) 353 { 354 struct vge_softc *sc = (struct vge_softc *)dev; 355 int i, s; 356 357 if (phy != (CSR_READ_1(sc, VGE_MIICFG) & 0x1F)) 358 return; 359 360 s = splnet(); 361 vge_miipoll_stop(sc); 362 363 /* Specify the register we want to write. */ 364 CSR_WRITE_1(sc, VGE_MIIADDR, reg); 365 366 /* Specify the data we want to write. */ 367 CSR_WRITE_2(sc, VGE_MIIDATA, data); 368 369 /* Issue write command. */ 370 CSR_SETBIT_1(sc, VGE_MIICMD, VGE_MIICMD_WCMD); 371 372 /* Wait for the write command bit to self-clear. */ 373 for (i = 0; i < VGE_TIMEOUT; i++) { 374 DELAY(1); 375 if ((CSR_READ_1(sc, VGE_MIICMD) & VGE_MIICMD_WCMD) == 0) 376 break; 377 } 378 379 if (i == VGE_TIMEOUT) { 380 printf("%s: MII write timed out\n", sc->vge_dev.dv_xname); 381 } 382 383 vge_miipoll_start(sc); 384 splx(s); 385 } 386 387 void 388 vge_cam_clear(struct vge_softc *sc) 389 { 390 int i; 391 392 /* 393 * Turn off all the mask bits. This tells the chip 394 * that none of the entries in the CAM filter are valid. 395 * desired entries will be enabled as we fill the filter in. 396 */ 397 398 CSR_CLRBIT_1(sc, VGE_CAMCTL, VGE_CAMCTL_PAGESEL); 399 CSR_SETBIT_1(sc, VGE_CAMCTL, VGE_PAGESEL_CAMMASK); 400 CSR_WRITE_1(sc, VGE_CAMADDR, VGE_CAMADDR_ENABLE); 401 for (i = 0; i < 8; i++) 402 CSR_WRITE_1(sc, VGE_CAM0 + i, 0); 403 404 /* Clear the VLAN filter too. */ 405 406 CSR_WRITE_1(sc, VGE_CAMADDR, VGE_CAMADDR_ENABLE|VGE_CAMADDR_AVSEL|0); 407 for (i = 0; i < 8; i++) 408 CSR_WRITE_1(sc, VGE_CAM0 + i, 0); 409 410 CSR_WRITE_1(sc, VGE_CAMADDR, 0); 411 CSR_CLRBIT_1(sc, VGE_CAMCTL, VGE_CAMCTL_PAGESEL); 412 CSR_SETBIT_1(sc, VGE_CAMCTL, VGE_PAGESEL_MAR); 413 414 sc->vge_camidx = 0; 415 } 416 417 int 418 vge_cam_set(struct vge_softc *sc, uint8_t *addr) 419 { 420 int i, error = 0; 421 422 if (sc->vge_camidx == VGE_CAM_MAXADDRS) 423 return(ENOSPC); 424 425 /* Select the CAM data page. */ 426 CSR_CLRBIT_1(sc, VGE_CAMCTL, VGE_CAMCTL_PAGESEL); 427 CSR_SETBIT_1(sc, VGE_CAMCTL, VGE_PAGESEL_CAMDATA); 428 429 /* Set the filter entry we want to update and enable writing. */ 430 CSR_WRITE_1(sc, VGE_CAMADDR, VGE_CAMADDR_ENABLE|sc->vge_camidx); 431 432 /* Write the address to the CAM registers */ 433 for (i = 0; i < ETHER_ADDR_LEN; i++) 434 CSR_WRITE_1(sc, VGE_CAM0 + i, addr[i]); 435 436 /* Issue a write command. */ 437 CSR_SETBIT_1(sc, VGE_CAMCTL, VGE_CAMCTL_WRITE); 438 439 /* Wake for it to clear. */ 440 for (i = 0; i < VGE_TIMEOUT; i++) { 441 DELAY(1); 442 if ((CSR_READ_1(sc, VGE_CAMCTL) & VGE_CAMCTL_WRITE) == 0) 443 break; 444 } 445 446 if (i == VGE_TIMEOUT) { 447 printf("%s: setting CAM filter failed\n", sc->vge_dev.dv_xname); 448 error = EIO; 449 goto fail; 450 } 451 452 /* Select the CAM mask page. */ 453 CSR_CLRBIT_1(sc, VGE_CAMCTL, VGE_CAMCTL_PAGESEL); 454 CSR_SETBIT_1(sc, VGE_CAMCTL, VGE_PAGESEL_CAMMASK); 455 456 /* Set the mask bit that enables this filter. */ 457 CSR_SETBIT_1(sc, VGE_CAM0 + (sc->vge_camidx/8), 458 1<<(sc->vge_camidx & 7)); 459 460 sc->vge_camidx++; 461 462 fail: 463 /* Turn off access to CAM. */ 464 CSR_WRITE_1(sc, VGE_CAMADDR, 0); 465 CSR_CLRBIT_1(sc, VGE_CAMCTL, VGE_CAMCTL_PAGESEL); 466 CSR_SETBIT_1(sc, VGE_CAMCTL, VGE_PAGESEL_MAR); 467 468 return (error); 469 } 470 471 /* 472 * Program the multicast filter. We use the 64-entry CAM filter 473 * for perfect filtering. If there's more than 64 multicast addresses, 474 * we use the hash filter instead. 475 */ 476 void 477 vge_setmulti(struct vge_softc *sc) 478 { 479 struct arpcom *ac = &sc->arpcom; 480 struct ifnet *ifp = &ac->ac_if; 481 struct ether_multi *enm; 482 struct ether_multistep step; 483 int error; 484 u_int32_t h = 0, hashes[2] = { 0, 0 }; 485 486 /* First, zot all the multicast entries. */ 487 vge_cam_clear(sc); 488 CSR_WRITE_4(sc, VGE_MAR0, 0); 489 CSR_WRITE_4(sc, VGE_MAR1, 0); 490 ifp->if_flags &= ~IFF_ALLMULTI; 491 492 /* 493 * If the user wants allmulti or promisc mode, enable reception 494 * of all multicast frames. 495 */ 496 if (ifp->if_flags & IFF_PROMISC) { 497 allmulti: 498 CSR_WRITE_4(sc, VGE_MAR0, 0xFFFFFFFF); 499 CSR_WRITE_4(sc, VGE_MAR1, 0xFFFFFFFF); 500 ifp->if_flags |= IFF_ALLMULTI; 501 return; 502 } 503 504 /* Now program new ones */ 505 ETHER_FIRST_MULTI(step, ac, enm); 506 while (enm != NULL) { 507 if (bcmp(enm->enm_addrlo, enm->enm_addrhi, ETHER_ADDR_LEN)) 508 goto allmulti; 509 510 error = vge_cam_set(sc, enm->enm_addrlo); 511 if (error) 512 break; 513 514 ETHER_NEXT_MULTI(step, enm); 515 } 516 517 /* If there were too many addresses, use the hash filter. */ 518 if (error) { 519 vge_cam_clear(sc); 520 521 ETHER_FIRST_MULTI(step, ac, enm); 522 while (enm != NULL) { 523 h = ether_crc32_be(enm->enm_addrlo, 524 ETHER_ADDR_LEN) >> 26; 525 hashes[h >> 5] |= 1 << (h & 0x1f); 526 527 ETHER_NEXT_MULTI(step, enm); 528 } 529 530 CSR_WRITE_4(sc, VGE_MAR0, hashes[0]); 531 CSR_WRITE_4(sc, VGE_MAR1, hashes[1]); 532 } 533 } 534 535 void 536 vge_reset(struct vge_softc *sc) 537 { 538 int i; 539 540 CSR_WRITE_1(sc, VGE_CRS1, VGE_CR1_SOFTRESET); 541 542 for (i = 0; i < VGE_TIMEOUT; i++) { 543 DELAY(5); 544 if ((CSR_READ_1(sc, VGE_CRS1) & VGE_CR1_SOFTRESET) == 0) 545 break; 546 } 547 548 if (i == VGE_TIMEOUT) { 549 printf("%s: soft reset timed out", sc->vge_dev.dv_xname); 550 CSR_WRITE_1(sc, VGE_CRS3, VGE_CR3_STOP_FORCE); 551 DELAY(2000); 552 } 553 554 DELAY(5000); 555 556 CSR_SETBIT_1(sc, VGE_EECSR, VGE_EECSR_RELOAD); 557 558 for (i = 0; i < VGE_TIMEOUT; i++) { 559 DELAY(5); 560 if ((CSR_READ_1(sc, VGE_EECSR) & VGE_EECSR_RELOAD) == 0) 561 break; 562 } 563 564 CSR_CLRBIT_1(sc, VGE_CHIPCFG0, VGE_CHIPCFG0_PACPI); 565 } 566 567 /* 568 * Probe for a VIA gigabit chip. Check the PCI vendor and device 569 * IDs against our list and return a device name if we find a match. 570 */ 571 int 572 vge_probe(struct device *dev, void *match, void *aux) 573 { 574 return (pci_matchbyid((struct pci_attach_args *)aux, vge_devices, 575 nitems(vge_devices))); 576 } 577 578 /* 579 * Allocate memory for RX/TX rings 580 */ 581 int 582 vge_allocmem(struct vge_softc *sc) 583 { 584 int nseg, rseg; 585 int i, error; 586 587 nseg = 32; 588 589 /* Allocate DMA'able memory for the TX ring */ 590 591 error = bus_dmamap_create(sc->sc_dmat, VGE_TX_LIST_SZ, 1, 592 VGE_TX_LIST_SZ, 0, BUS_DMA_ALLOCNOW, 593 &sc->vge_ldata.vge_tx_list_map); 594 if (error) 595 return (ENOMEM); 596 error = bus_dmamem_alloc(sc->sc_dmat, VGE_TX_LIST_SZ, 597 ETHER_ALIGN, 0, 598 &sc->vge_ldata.vge_tx_listseg, 1, &rseg, BUS_DMA_NOWAIT); 599 if (error) { 600 printf("%s: can't alloc TX list\n", sc->vge_dev.dv_xname); 601 return (ENOMEM); 602 } 603 604 /* Load the map for the TX ring. */ 605 error = bus_dmamem_map(sc->sc_dmat, &sc->vge_ldata.vge_tx_listseg, 606 1, VGE_TX_LIST_SZ, 607 (caddr_t *)&sc->vge_ldata.vge_tx_list, BUS_DMA_NOWAIT); 608 memset(sc->vge_ldata.vge_tx_list, 0, VGE_TX_LIST_SZ); 609 if (error) { 610 printf("%s: can't map TX dma buffers\n", 611 sc->vge_dev.dv_xname); 612 bus_dmamem_free(sc->sc_dmat, &sc->vge_ldata.vge_tx_listseg, rseg); 613 return (ENOMEM); 614 } 615 616 error = bus_dmamap_load(sc->sc_dmat, sc->vge_ldata.vge_tx_list_map, 617 sc->vge_ldata.vge_tx_list, VGE_TX_LIST_SZ, NULL, BUS_DMA_NOWAIT); 618 if (error) { 619 printf("%s: can't load TX dma map\n", sc->vge_dev.dv_xname); 620 bus_dmamap_destroy(sc->sc_dmat, sc->vge_ldata.vge_tx_list_map); 621 bus_dmamem_unmap(sc->sc_dmat, (caddr_t)sc->vge_ldata.vge_tx_list, 622 VGE_TX_LIST_SZ); 623 bus_dmamem_free(sc->sc_dmat, &sc->vge_ldata.vge_tx_listseg, rseg); 624 return (ENOMEM); 625 } 626 627 /* Create DMA maps for TX buffers */ 628 629 for (i = 0; i < VGE_TX_DESC_CNT; i++) { 630 error = bus_dmamap_create(sc->sc_dmat, MCLBYTES * nseg, nseg, 631 MCLBYTES, 0, BUS_DMA_ALLOCNOW, 632 &sc->vge_ldata.vge_tx_dmamap[i]); 633 if (error) { 634 printf("%s: can't create DMA map for TX\n", 635 sc->vge_dev.dv_xname); 636 return (ENOMEM); 637 } 638 } 639 640 /* Allocate DMA'able memory for the RX ring */ 641 642 error = bus_dmamap_create(sc->sc_dmat, VGE_RX_LIST_SZ, 1, 643 VGE_RX_LIST_SZ, 0, BUS_DMA_ALLOCNOW, 644 &sc->vge_ldata.vge_rx_list_map); 645 if (error) 646 return (ENOMEM); 647 error = bus_dmamem_alloc(sc->sc_dmat, VGE_RX_LIST_SZ, VGE_RING_ALIGN, 648 0, &sc->vge_ldata.vge_rx_listseg, 1, &rseg, BUS_DMA_NOWAIT); 649 if (error) { 650 printf("%s: can't alloc RX list\n", sc->vge_dev.dv_xname); 651 return (ENOMEM); 652 } 653 654 /* Load the map for the RX ring. */ 655 656 error = bus_dmamem_map(sc->sc_dmat, &sc->vge_ldata.vge_rx_listseg, 657 1, VGE_RX_LIST_SZ, 658 (caddr_t *)&sc->vge_ldata.vge_rx_list, BUS_DMA_NOWAIT); 659 memset(sc->vge_ldata.vge_rx_list, 0, VGE_RX_LIST_SZ); 660 if (error) { 661 printf("%s: can't map RX dma buffers\n", 662 sc->vge_dev.dv_xname); 663 bus_dmamem_free(sc->sc_dmat, &sc->vge_ldata.vge_rx_listseg, rseg); 664 return (ENOMEM); 665 } 666 error = bus_dmamap_load(sc->sc_dmat, sc->vge_ldata.vge_rx_list_map, 667 sc->vge_ldata.vge_rx_list, VGE_RX_LIST_SZ, NULL, BUS_DMA_NOWAIT); 668 if (error) { 669 printf("%s: can't load RX dma map\n", sc->vge_dev.dv_xname); 670 bus_dmamap_destroy(sc->sc_dmat, sc->vge_ldata.vge_rx_list_map); 671 bus_dmamem_unmap(sc->sc_dmat, (caddr_t)sc->vge_ldata.vge_rx_list, 672 VGE_RX_LIST_SZ); 673 bus_dmamem_free(sc->sc_dmat, &sc->vge_ldata.vge_rx_listseg, rseg); 674 return (ENOMEM); 675 } 676 677 /* Create DMA maps for RX buffers */ 678 679 for (i = 0; i < VGE_RX_DESC_CNT; i++) { 680 error = bus_dmamap_create(sc->sc_dmat, MCLBYTES * nseg, nseg, 681 MCLBYTES, 0, BUS_DMA_ALLOCNOW, 682 &sc->vge_ldata.vge_rx_dmamap[i]); 683 if (error) { 684 printf("%s: can't create DMA map for RX\n", 685 sc->vge_dev.dv_xname); 686 return (ENOMEM); 687 } 688 } 689 690 return (0); 691 } 692 693 void 694 vge_freemem(struct vge_softc *sc) 695 { 696 int i; 697 698 for (i = 0; i < VGE_RX_DESC_CNT; i++) 699 bus_dmamap_destroy(sc->sc_dmat, 700 sc->vge_ldata.vge_rx_dmamap[i]); 701 702 bus_dmamap_unload(sc->sc_dmat, sc->vge_ldata.vge_rx_list_map); 703 bus_dmamap_destroy(sc->sc_dmat, sc->vge_ldata.vge_rx_list_map); 704 bus_dmamem_unmap(sc->sc_dmat, (caddr_t)sc->vge_ldata.vge_rx_list, 705 VGE_RX_LIST_SZ); 706 bus_dmamem_free(sc->sc_dmat, &sc->vge_ldata.vge_rx_listseg, 1); 707 708 for (i = 0; i < VGE_TX_DESC_CNT; i++) 709 bus_dmamap_destroy(sc->sc_dmat, 710 sc->vge_ldata.vge_tx_dmamap[i]); 711 712 bus_dmamap_unload(sc->sc_dmat, sc->vge_ldata.vge_tx_list_map); 713 bus_dmamap_destroy(sc->sc_dmat, sc->vge_ldata.vge_tx_list_map); 714 bus_dmamem_unmap(sc->sc_dmat, (caddr_t)sc->vge_ldata.vge_tx_list, 715 VGE_TX_LIST_SZ); 716 bus_dmamem_free(sc->sc_dmat, &sc->vge_ldata.vge_tx_listseg, 1); 717 } 718 719 /* 720 * Attach the interface. Allocate softc structures, do ifmedia 721 * setup and ethernet/BPF attach. 722 */ 723 void 724 vge_attach(struct device *parent, struct device *self, void *aux) 725 { 726 u_char eaddr[ETHER_ADDR_LEN]; 727 struct vge_softc *sc = (struct vge_softc *)self; 728 struct pci_attach_args *pa = aux; 729 pci_chipset_tag_t pc = pa->pa_pc; 730 pci_intr_handle_t ih; 731 const char *intrstr = NULL; 732 struct ifnet *ifp; 733 int error = 0; 734 735 /* 736 * Map control/status registers. 737 */ 738 if (pci_mapreg_map(pa, VGE_PCI_LOMEM, PCI_MAPREG_TYPE_MEM, 0, 739 &sc->vge_btag, &sc->vge_bhandle, NULL, &sc->vge_bsize, 0)) { 740 if (pci_mapreg_map(pa, VGE_PCI_LOIO, PCI_MAPREG_TYPE_IO, 0, 741 &sc->vge_btag, &sc->vge_bhandle, NULL, &sc->vge_bsize, 0)) { 742 printf(": can't map mem or i/o space\n"); 743 return; 744 } 745 } 746 747 /* Allocate interrupt */ 748 if (pci_intr_map(pa, &ih)) { 749 printf(": couldn't map interrupt\n"); 750 return; 751 } 752 intrstr = pci_intr_string(pc, ih); 753 sc->vge_intrhand = pci_intr_establish(pc, ih, IPL_NET, vge_intr, sc, 754 sc->vge_dev.dv_xname); 755 if (sc->vge_intrhand == NULL) { 756 printf(": couldn't establish interrupt"); 757 if (intrstr != NULL) 758 printf(" at %s", intrstr); 759 return; 760 } 761 printf(": %s", intrstr); 762 763 sc->sc_dmat = pa->pa_dmat; 764 sc->sc_pc = pa->pa_pc; 765 766 /* Reset the adapter. */ 767 vge_reset(sc); 768 769 /* 770 * Get station address from the EEPROM. 771 */ 772 vge_read_eeprom(sc, eaddr, VGE_EE_EADDR, 3, 1); 773 774 bcopy(eaddr, &sc->arpcom.ac_enaddr, ETHER_ADDR_LEN); 775 776 printf(", address %s\n", 777 ether_sprintf(sc->arpcom.ac_enaddr)); 778 779 error = vge_allocmem(sc); 780 781 if (error) 782 return; 783 784 ifp = &sc->arpcom.ac_if; 785 ifp->if_softc = sc; 786 ifp->if_flags = IFF_BROADCAST | IFF_SIMPLEX | IFF_MULTICAST; 787 ifp->if_ioctl = vge_ioctl; 788 ifp->if_start = vge_start; 789 ifp->if_watchdog = vge_watchdog; 790 ifp->if_baudrate = 1000000000; 791 #ifdef VGE_JUMBO 792 ifp->if_hardmtu = VGE_JUMBO_MTU; 793 #endif 794 IFQ_SET_MAXLEN(&ifp->if_snd, VGE_IFQ_MAXLEN); 795 IFQ_SET_READY(&ifp->if_snd); 796 797 ifp->if_capabilities = IFCAP_VLAN_MTU | IFCAP_CSUM_IPv4 | 798 IFCAP_CSUM_TCPv4 | IFCAP_CSUM_UDPv4; 799 800 #if NVLAN > 0 801 ifp->if_capabilities |= IFCAP_VLAN_HWTAGGING; 802 #endif 803 804 /* Set interface name */ 805 strlcpy(ifp->if_xname, sc->vge_dev.dv_xname, IFNAMSIZ); 806 807 /* Do MII setup */ 808 sc->sc_mii.mii_ifp = ifp; 809 sc->sc_mii.mii_readreg = vge_miibus_readreg; 810 sc->sc_mii.mii_writereg = vge_miibus_writereg; 811 sc->sc_mii.mii_statchg = vge_miibus_statchg; 812 ifmedia_init(&sc->sc_mii.mii_media, 0, 813 vge_ifmedia_upd, vge_ifmedia_sts); 814 mii_attach(self, &sc->sc_mii, 0xffffffff, MII_PHY_ANY, 815 MII_OFFSET_ANY, 0); 816 if (LIST_FIRST(&sc->sc_mii.mii_phys) == NULL) { 817 printf("%s: no PHY found!\n", sc->vge_dev.dv_xname); 818 ifmedia_add(&sc->sc_mii.mii_media, IFM_ETHER|IFM_MANUAL, 819 0, NULL); 820 ifmedia_set(&sc->sc_mii.mii_media, IFM_ETHER|IFM_MANUAL); 821 } else 822 ifmedia_set(&sc->sc_mii.mii_media, IFM_ETHER|IFM_AUTO); 823 824 timeout_set(&sc->timer_handle, vge_tick, sc); 825 826 /* 827 * Call MI attach routine. 828 */ 829 if_attach(ifp); 830 ether_ifattach(ifp); 831 } 832 833 int 834 vge_detach(struct device *self, int flags) 835 { 836 struct vge_softc *sc = (void *)self; 837 struct ifnet *ifp = &sc->arpcom.ac_if; 838 839 pci_intr_disestablish(sc->sc_pc, sc->vge_intrhand); 840 841 vge_stop(sc); 842 843 /* Detach all PHYs */ 844 mii_detach(&sc->sc_mii, MII_PHY_ANY, MII_OFFSET_ANY); 845 846 /* Delete any remaining media. */ 847 ifmedia_delete_instance(&sc->sc_mii.mii_media, IFM_INST_ANY); 848 849 ether_ifdetach(ifp); 850 if_detach(ifp); 851 852 vge_freemem(sc); 853 854 bus_space_unmap(sc->vge_btag, sc->vge_bhandle, sc->vge_bsize); 855 return (0); 856 } 857 858 int 859 vge_newbuf(struct vge_softc *sc, int idx, struct mbuf *m) 860 { 861 struct mbuf *m_new = NULL; 862 struct vge_rx_desc *r; 863 bus_dmamap_t rxmap = sc->vge_ldata.vge_rx_dmamap[idx]; 864 int i; 865 866 if (m == NULL) { 867 /* Allocate a new mbuf */ 868 MGETHDR(m_new, M_DONTWAIT, MT_DATA); 869 if (m_new == NULL) 870 return (ENOBUFS); 871 872 /* Allocate a cluster */ 873 MCLGET(m_new, M_DONTWAIT); 874 if (!(m_new->m_flags & M_EXT)) { 875 m_freem(m_new); 876 return (ENOBUFS); 877 } 878 879 m = m_new; 880 } else 881 m->m_data = m->m_ext.ext_buf; 882 883 m->m_len = m->m_pkthdr.len = MCLBYTES; 884 /* Fix-up alignment so payload is doubleword-aligned */ 885 /* XXX m_adj(m, ETHER_ALIGN); */ 886 887 if (bus_dmamap_load_mbuf(sc->sc_dmat, rxmap, m, BUS_DMA_NOWAIT)) 888 return (ENOBUFS); 889 890 if (rxmap->dm_nsegs > 1) 891 goto out; 892 893 /* Map the segments into RX descriptors */ 894 r = &sc->vge_ldata.vge_rx_list[idx]; 895 896 if (letoh32(r->vge_sts) & VGE_RDSTS_OWN) { 897 printf("%s: tried to map a busy RX descriptor\n", 898 sc->vge_dev.dv_xname); 899 goto out; 900 } 901 r->vge_buflen = htole16(VGE_BUFLEN(rxmap->dm_segs[0].ds_len) | VGE_RXDESC_I); 902 r->vge_addrlo = htole32(VGE_ADDR_LO(rxmap->dm_segs[0].ds_addr)); 903 r->vge_addrhi = htole16(VGE_ADDR_HI(rxmap->dm_segs[0].ds_addr) & 0xFFFF); 904 r->vge_sts = htole32(0); 905 r->vge_ctl = htole32(0); 906 907 /* 908 * Note: the manual fails to document the fact that for 909 * proper operation, the driver needs to replenish the RX 910 * DMA ring 4 descriptors at a time (rather than one at a 911 * time, like most chips). We can allocate the new buffers 912 * but we should not set the OWN bits until we're ready 913 * to hand back 4 of them in one shot. 914 */ 915 #define VGE_RXCHUNK 4 916 sc->vge_rx_consumed++; 917 if (sc->vge_rx_consumed == VGE_RXCHUNK) { 918 for (i = idx; i != idx - sc->vge_rx_consumed; i--) 919 sc->vge_ldata.vge_rx_list[i].vge_sts |= 920 htole32(VGE_RDSTS_OWN); 921 sc->vge_rx_consumed = 0; 922 } 923 924 sc->vge_ldata.vge_rx_mbuf[idx] = m; 925 926 bus_dmamap_sync(sc->sc_dmat, rxmap, 0, 927 rxmap->dm_mapsize, BUS_DMASYNC_PREREAD); 928 929 return (0); 930 out: 931 DPRINTF(("vge_newbuf: out of memory\n")); 932 if (m_new != NULL) 933 m_freem(m_new); 934 return (ENOMEM); 935 } 936 937 int 938 vge_tx_list_init(struct vge_softc *sc) 939 { 940 bzero(sc->vge_ldata.vge_tx_list, VGE_TX_LIST_SZ); 941 bzero(&sc->vge_ldata.vge_tx_mbuf, 942 (VGE_TX_DESC_CNT * sizeof(struct mbuf *))); 943 944 bus_dmamap_sync(sc->sc_dmat, 945 sc->vge_ldata.vge_tx_list_map, 0, 946 sc->vge_ldata.vge_tx_list_map->dm_mapsize, 947 BUS_DMASYNC_PREWRITE); 948 sc->vge_ldata.vge_tx_prodidx = 0; 949 sc->vge_ldata.vge_tx_considx = 0; 950 sc->vge_ldata.vge_tx_free = VGE_TX_DESC_CNT; 951 952 return (0); 953 } 954 955 /* Init RX descriptors and allocate mbufs with vge_newbuf() 956 * A ring is used, and last descriptor points to first. */ 957 int 958 vge_rx_list_init(struct vge_softc *sc) 959 { 960 int i; 961 962 bzero(sc->vge_ldata.vge_rx_list, VGE_RX_LIST_SZ); 963 bzero(&sc->vge_ldata.vge_rx_mbuf, 964 (VGE_RX_DESC_CNT * sizeof(struct mbuf *))); 965 966 sc->vge_rx_consumed = 0; 967 968 for (i = 0; i < VGE_RX_DESC_CNT; i++) { 969 if (vge_newbuf(sc, i, NULL) == ENOBUFS) 970 return (ENOBUFS); 971 } 972 973 /* Flush the RX descriptors */ 974 975 bus_dmamap_sync(sc->sc_dmat, 976 sc->vge_ldata.vge_rx_list_map, 977 0, sc->vge_ldata.vge_rx_list_map->dm_mapsize, 978 BUS_DMASYNC_PREWRITE|BUS_DMASYNC_PREREAD); 979 980 sc->vge_ldata.vge_rx_prodidx = 0; 981 sc->vge_rx_consumed = 0; 982 sc->vge_head = sc->vge_tail = NULL; 983 984 return (0); 985 } 986 987 /* 988 * RX handler. We support the reception of jumbo frames that have 989 * been fragmented across multiple 2K mbuf cluster buffers. 990 */ 991 void 992 vge_rxeof(struct vge_softc *sc) 993 { 994 struct mbuf *m; 995 struct ifnet *ifp; 996 int i, total_len; 997 int lim = 0; 998 struct vge_rx_desc *cur_rx; 999 u_int32_t rxstat, rxctl; 1000 1001 ifp = &sc->arpcom.ac_if; 1002 i = sc->vge_ldata.vge_rx_prodidx; 1003 1004 /* Invalidate the descriptor memory */ 1005 1006 bus_dmamap_sync(sc->sc_dmat, 1007 sc->vge_ldata.vge_rx_list_map, 1008 0, sc->vge_ldata.vge_rx_list_map->dm_mapsize, 1009 BUS_DMASYNC_POSTREAD); 1010 1011 while (!VGE_OWN(&sc->vge_ldata.vge_rx_list[i])) { 1012 struct mbuf *m0 = NULL; 1013 1014 cur_rx = &sc->vge_ldata.vge_rx_list[i]; 1015 m = sc->vge_ldata.vge_rx_mbuf[i]; 1016 total_len = VGE_RXBYTES(cur_rx); 1017 rxstat = letoh32(cur_rx->vge_sts); 1018 rxctl = letoh32(cur_rx->vge_ctl); 1019 1020 /* Invalidate the RX mbuf and unload its map */ 1021 1022 bus_dmamap_sync(sc->sc_dmat, 1023 sc->vge_ldata.vge_rx_dmamap[i], 1024 0, sc->vge_ldata.vge_rx_dmamap[i]->dm_mapsize, 1025 BUS_DMASYNC_POSTWRITE); 1026 bus_dmamap_unload(sc->sc_dmat, 1027 sc->vge_ldata.vge_rx_dmamap[i]); 1028 1029 /* 1030 * If the 'start of frame' bit is set, this indicates 1031 * either the first fragment in a multi-fragment receive, 1032 * or an intermediate fragment. Either way, we want to 1033 * accumulate the buffers. 1034 */ 1035 if (rxstat & VGE_RXPKT_SOF) { 1036 DPRINTF(("vge_rxeof: SOF\n")); 1037 m->m_len = MCLBYTES; 1038 if (sc->vge_head == NULL) 1039 sc->vge_head = sc->vge_tail = m; 1040 else { 1041 m->m_flags &= ~M_PKTHDR; 1042 sc->vge_tail->m_next = m; 1043 sc->vge_tail = m; 1044 } 1045 vge_newbuf(sc, i, NULL); 1046 VGE_RX_DESC_INC(i); 1047 continue; 1048 } 1049 1050 /* 1051 * Bad/error frames will have the RXOK bit cleared. 1052 * However, there's one error case we want to allow: 1053 * if a VLAN tagged frame arrives and the chip can't 1054 * match it against the CAM filter, it considers this 1055 * a 'VLAN CAM filter miss' and clears the 'RXOK' bit. 1056 * We don't want to drop the frame though: our VLAN 1057 * filtering is done in software. 1058 */ 1059 if (!(rxstat & VGE_RDSTS_RXOK) && !(rxstat & VGE_RDSTS_VIDM) 1060 && !(rxstat & VGE_RDSTS_CSUMERR)) { 1061 ifp->if_ierrors++; 1062 /* 1063 * If this is part of a multi-fragment packet, 1064 * discard all the pieces. 1065 */ 1066 if (sc->vge_head != NULL) { 1067 m_freem(sc->vge_head); 1068 sc->vge_head = sc->vge_tail = NULL; 1069 } 1070 vge_newbuf(sc, i, m); 1071 VGE_RX_DESC_INC(i); 1072 continue; 1073 } 1074 1075 /* 1076 * If allocating a replacement mbuf fails, 1077 * reload the current one. 1078 */ 1079 1080 if (vge_newbuf(sc, i, NULL) == ENOBUFS) { 1081 if (sc->vge_head != NULL) { 1082 m_freem(sc->vge_head); 1083 sc->vge_head = sc->vge_tail = NULL; 1084 } 1085 1086 m0 = m_devget(mtod(m, char *), 1087 total_len - ETHER_CRC_LEN, ETHER_ALIGN, ifp, NULL); 1088 vge_newbuf(sc, i, m); 1089 if (m0 == NULL) { 1090 ifp->if_ierrors++; 1091 continue; 1092 } 1093 m = m0; 1094 1095 VGE_RX_DESC_INC(i); 1096 continue; 1097 } 1098 1099 VGE_RX_DESC_INC(i); 1100 1101 if (sc->vge_head != NULL) { 1102 m->m_len = total_len % MCLBYTES; 1103 /* 1104 * Special case: if there's 4 bytes or less 1105 * in this buffer, the mbuf can be discarded: 1106 * the last 4 bytes is the CRC, which we don't 1107 * care about anyway. 1108 */ 1109 if (m->m_len <= ETHER_CRC_LEN) { 1110 sc->vge_tail->m_len -= 1111 (ETHER_CRC_LEN - m->m_len); 1112 m_freem(m); 1113 } else { 1114 m->m_len -= ETHER_CRC_LEN; 1115 m->m_flags &= ~M_PKTHDR; 1116 sc->vge_tail->m_next = m; 1117 } 1118 m = sc->vge_head; 1119 sc->vge_head = sc->vge_tail = NULL; 1120 m->m_pkthdr.len = total_len - ETHER_CRC_LEN; 1121 } else 1122 m->m_pkthdr.len = m->m_len = 1123 (total_len - ETHER_CRC_LEN); 1124 1125 #ifdef __STRICT_ALIGNMENT 1126 bcopy(m->m_data, m->m_data + ETHER_ALIGN, total_len); 1127 m->m_data += ETHER_ALIGN; 1128 #endif 1129 ifp->if_ipackets++; 1130 m->m_pkthdr.rcvif = ifp; 1131 1132 /* Do RX checksumming */ 1133 1134 /* Check IP header checksum */ 1135 if ((rxctl & VGE_RDCTL_IPPKT) && 1136 (rxctl & VGE_RDCTL_IPCSUMOK)) 1137 m->m_pkthdr.csum_flags |= M_IPV4_CSUM_IN_OK; 1138 1139 /* Check TCP/UDP checksum */ 1140 if ((rxctl & (VGE_RDCTL_TCPPKT|VGE_RDCTL_UDPPKT)) && 1141 (rxctl & VGE_RDCTL_PROTOCSUMOK)) 1142 m->m_pkthdr.csum_flags |= M_TCP_CSUM_IN_OK | M_UDP_CSUM_IN_OK; 1143 1144 #if NVLAN > 0 1145 if (rxstat & VGE_RDSTS_VTAG) { 1146 m->m_pkthdr.ether_vtag = swap16(rxctl & VGE_RDCTL_VLANID); 1147 m->m_flags |= M_VLANTAG; 1148 } 1149 #endif 1150 1151 #if NBPFILTER > 0 1152 if (ifp->if_bpf) 1153 bpf_mtap_ether(ifp->if_bpf, m, BPF_DIRECTION_IN); 1154 #endif 1155 ether_input_mbuf(ifp, m); 1156 1157 lim++; 1158 if (lim == VGE_RX_DESC_CNT) 1159 break; 1160 } 1161 1162 /* Flush the RX DMA ring */ 1163 bus_dmamap_sync(sc->sc_dmat, 1164 sc->vge_ldata.vge_rx_list_map, 1165 0, sc->vge_ldata.vge_rx_list_map->dm_mapsize, 1166 BUS_DMASYNC_PREWRITE|BUS_DMASYNC_PREREAD); 1167 1168 sc->vge_ldata.vge_rx_prodidx = i; 1169 CSR_WRITE_2(sc, VGE_RXDESC_RESIDUECNT, lim); 1170 } 1171 1172 void 1173 vge_txeof(struct vge_softc *sc) 1174 { 1175 struct ifnet *ifp; 1176 u_int32_t txstat; 1177 int idx; 1178 1179 ifp = &sc->arpcom.ac_if; 1180 idx = sc->vge_ldata.vge_tx_considx; 1181 1182 /* Invalidate the TX descriptor list */ 1183 1184 bus_dmamap_sync(sc->sc_dmat, 1185 sc->vge_ldata.vge_tx_list_map, 1186 0, sc->vge_ldata.vge_tx_list_map->dm_mapsize, 1187 BUS_DMASYNC_POSTREAD); 1188 1189 /* Transmitted frames can be now free'd from the TX list */ 1190 while (idx != sc->vge_ldata.vge_tx_prodidx) { 1191 txstat = letoh32(sc->vge_ldata.vge_tx_list[idx].vge_sts); 1192 if (txstat & VGE_TDSTS_OWN) 1193 break; 1194 1195 m_freem(sc->vge_ldata.vge_tx_mbuf[idx]); 1196 sc->vge_ldata.vge_tx_mbuf[idx] = NULL; 1197 bus_dmamap_unload(sc->sc_dmat, 1198 sc->vge_ldata.vge_tx_dmamap[idx]); 1199 if (txstat & (VGE_TDSTS_EXCESSCOLL|VGE_TDSTS_COLL)) 1200 ifp->if_collisions++; 1201 if (txstat & VGE_TDSTS_TXERR) 1202 ifp->if_oerrors++; 1203 else 1204 ifp->if_opackets++; 1205 1206 sc->vge_ldata.vge_tx_free++; 1207 VGE_TX_DESC_INC(idx); 1208 } 1209 1210 /* No changes made to the TX ring, so no flush needed */ 1211 1212 if (idx != sc->vge_ldata.vge_tx_considx) { 1213 sc->vge_ldata.vge_tx_considx = idx; 1214 ifp->if_flags &= ~IFF_OACTIVE; 1215 ifp->if_timer = 0; 1216 } 1217 1218 /* 1219 * If not all descriptors have been released reaped yet, 1220 * reload the timer so that we will eventually get another 1221 * interrupt that will cause us to re-enter this routine. 1222 * This is done in case the transmitter has gone idle. 1223 */ 1224 if (sc->vge_ldata.vge_tx_free != VGE_TX_DESC_CNT) 1225 CSR_WRITE_1(sc, VGE_CRS1, VGE_CR1_TIMER0_ENABLE); 1226 } 1227 1228 void 1229 vge_tick(void *xsc) 1230 { 1231 struct vge_softc *sc = xsc; 1232 struct ifnet *ifp = &sc->arpcom.ac_if; 1233 struct mii_data *mii = &sc->sc_mii; 1234 int s; 1235 1236 s = splnet(); 1237 1238 mii_tick(mii); 1239 1240 if (sc->vge_link) { 1241 if (!(mii->mii_media_status & IFM_ACTIVE)) { 1242 sc->vge_link = 0; 1243 ifp->if_link_state = LINK_STATE_DOWN; 1244 if_link_state_change(ifp); 1245 } 1246 } else { 1247 if (mii->mii_media_status & IFM_ACTIVE && 1248 IFM_SUBTYPE(mii->mii_media_active) != IFM_NONE) { 1249 sc->vge_link = 1; 1250 if (mii->mii_media_status & IFM_FDX) 1251 ifp->if_link_state = LINK_STATE_FULL_DUPLEX; 1252 else 1253 ifp->if_link_state = LINK_STATE_HALF_DUPLEX; 1254 if_link_state_change(ifp); 1255 if (!IFQ_IS_EMPTY(&ifp->if_snd)) 1256 vge_start(ifp); 1257 } 1258 } 1259 timeout_add_sec(&sc->timer_handle, 1); 1260 splx(s); 1261 } 1262 1263 int 1264 vge_intr(void *arg) 1265 { 1266 struct vge_softc *sc = arg; 1267 struct ifnet *ifp; 1268 u_int32_t status; 1269 int claimed = 0; 1270 1271 ifp = &sc->arpcom.ac_if; 1272 1273 if (!(ifp->if_flags & IFF_UP)) 1274 return 0; 1275 1276 /* Disable interrupts */ 1277 CSR_WRITE_1(sc, VGE_CRC3, VGE_CR3_INT_GMSK); 1278 1279 for (;;) { 1280 status = CSR_READ_4(sc, VGE_ISR); 1281 DPRINTFN(3, ("vge_intr: status=%#x\n", status)); 1282 1283 /* If the card has gone away the read returns 0xffffffff. */ 1284 if (status == 0xFFFFFFFF) 1285 break; 1286 1287 if (status) { 1288 CSR_WRITE_4(sc, VGE_ISR, status); 1289 } 1290 1291 if ((status & VGE_INTRS) == 0) 1292 break; 1293 1294 claimed = 1; 1295 1296 if (status & (VGE_ISR_RXOK|VGE_ISR_RXOK_HIPRIO)) 1297 vge_rxeof(sc); 1298 1299 if (status & (VGE_ISR_RXOFLOW|VGE_ISR_RXNODESC)) { 1300 DPRINTFN(2, ("vge_intr: RX error, recovering\n")); 1301 vge_rxeof(sc); 1302 CSR_WRITE_1(sc, VGE_RXQCSRS, VGE_RXQCSR_RUN); 1303 CSR_WRITE_1(sc, VGE_RXQCSRS, VGE_RXQCSR_WAK); 1304 } 1305 1306 if (status & (VGE_ISR_TXOK0|VGE_ISR_TIMER0)) 1307 vge_txeof(sc); 1308 1309 if (status & (VGE_ISR_TXDMA_STALL|VGE_ISR_RXDMA_STALL)) { 1310 DPRINTFN(2, ("DMA_STALL\n")); 1311 vge_init(ifp); 1312 } 1313 1314 if (status & VGE_ISR_LINKSTS) { 1315 timeout_del(&sc->timer_handle); 1316 vge_tick(sc); 1317 } 1318 } 1319 1320 /* Re-enable interrupts */ 1321 CSR_WRITE_1(sc, VGE_CRS3, VGE_CR3_INT_GMSK); 1322 1323 if (!IFQ_IS_EMPTY(&ifp->if_snd)) 1324 vge_start(ifp); 1325 1326 return (claimed); 1327 } 1328 1329 /* 1330 * Encapsulate an mbuf chain into the TX ring by combining it w/ 1331 * the descriptors. 1332 */ 1333 int 1334 vge_encap(struct vge_softc *sc, struct mbuf *m_head, int idx) 1335 { 1336 struct ifnet *ifp = &sc->arpcom.ac_if; 1337 bus_dmamap_t txmap; 1338 struct vge_tx_desc *d = NULL; 1339 struct vge_tx_frag *f; 1340 struct mbuf *mnew = NULL; 1341 int error, frag; 1342 u_int32_t vge_flags; 1343 1344 vge_flags = 0; 1345 1346 if (m_head->m_pkthdr.csum_flags & M_IPV4_CSUM_OUT) 1347 vge_flags |= VGE_TDCTL_IPCSUM; 1348 if (m_head->m_pkthdr.csum_flags & M_TCP_CSUM_OUT) 1349 vge_flags |= VGE_TDCTL_TCPCSUM; 1350 if (m_head->m_pkthdr.csum_flags & M_UDP_CSUM_OUT) 1351 vge_flags |= VGE_TDCTL_UDPCSUM; 1352 1353 txmap = sc->vge_ldata.vge_tx_dmamap[idx]; 1354 repack: 1355 error = bus_dmamap_load_mbuf(sc->sc_dmat, txmap, 1356 m_head, BUS_DMA_NOWAIT); 1357 if (error) { 1358 printf("%s: can't map mbuf (error %d)\n", 1359 sc->vge_dev.dv_xname, error); 1360 return (ENOBUFS); 1361 } 1362 1363 d = &sc->vge_ldata.vge_tx_list[idx]; 1364 /* If owned by chip, fail */ 1365 if (letoh32(d->vge_sts) & VGE_TDSTS_OWN) 1366 return (ENOBUFS); 1367 1368 for (frag = 0; frag < txmap->dm_nsegs; frag++) { 1369 /* Check if we have used all 7 fragments. */ 1370 if (frag == VGE_TX_FRAGS) 1371 break; 1372 f = &d->vge_frag[frag]; 1373 f->vge_buflen = htole16(VGE_BUFLEN(txmap->dm_segs[frag].ds_len)); 1374 f->vge_addrlo = htole32(VGE_ADDR_LO(txmap->dm_segs[frag].ds_addr)); 1375 f->vge_addrhi = htole16(VGE_ADDR_HI(txmap->dm_segs[frag].ds_addr) & 0xFFFF); 1376 } 1377 1378 /* 1379 * We used up all 7 fragments! Now what we have to do is 1380 * copy the data into a mbuf cluster and map that. 1381 */ 1382 if (frag == VGE_TX_FRAGS) { 1383 MGETHDR(mnew, M_DONTWAIT, MT_DATA); 1384 if (mnew == NULL) 1385 return (ENOBUFS); 1386 1387 if (m_head->m_pkthdr.len > MHLEN) { 1388 MCLGET(mnew, M_DONTWAIT); 1389 if (!(mnew->m_flags & M_EXT)) { 1390 m_freem(mnew); 1391 return (ENOBUFS); 1392 } 1393 } 1394 m_copydata(m_head, 0, m_head->m_pkthdr.len, 1395 mtod(mnew, caddr_t)); 1396 mnew->m_pkthdr.len = mnew->m_len = m_head->m_pkthdr.len; 1397 IFQ_DEQUEUE(&ifp->if_snd, m_head); 1398 m_freem(m_head); 1399 m_head = mnew; 1400 goto repack; 1401 } 1402 1403 /* This chip does not do auto-padding */ 1404 if (m_head->m_pkthdr.len < VGE_MIN_FRAMELEN) { 1405 f = &d->vge_frag[frag]; 1406 1407 f->vge_buflen = htole16(VGE_BUFLEN(VGE_MIN_FRAMELEN - 1408 m_head->m_pkthdr.len)); 1409 f->vge_addrlo = htole32(VGE_ADDR_LO(txmap->dm_segs[0].ds_addr)); 1410 f->vge_addrhi = htole16(VGE_ADDR_HI(txmap->dm_segs[0].ds_addr) & 0xFFFF); 1411 m_head->m_pkthdr.len = VGE_MIN_FRAMELEN; 1412 frag++; 1413 } 1414 /* For some reason, we need to tell the card fragment + 1 */ 1415 frag++; 1416 1417 bus_dmamap_sync(sc->sc_dmat, txmap, 0, txmap->dm_mapsize, 1418 BUS_DMASYNC_PREWRITE); 1419 1420 d->vge_sts = htole32(m_head->m_pkthdr.len << 16); 1421 d->vge_ctl = htole32(vge_flags|(frag << 28) | VGE_TD_LS_NORM); 1422 1423 if (m_head->m_pkthdr.len > ETHERMTU + ETHER_HDR_LEN) 1424 d->vge_ctl |= htole32(VGE_TDCTL_JUMBO); 1425 1426 #if NVLAN > 0 1427 /* Set up hardware VLAN tagging. */ 1428 if (m_head->m_flags & M_VLANTAG) { 1429 d->vge_ctl |= htole32(m_head->m_pkthdr.ether_vtag | 1430 VGE_TDCTL_VTAG); 1431 } 1432 #endif 1433 1434 sc->vge_ldata.vge_tx_dmamap[idx] = txmap; 1435 sc->vge_ldata.vge_tx_mbuf[idx] = m_head; 1436 sc->vge_ldata.vge_tx_free--; 1437 sc->vge_ldata.vge_tx_list[idx].vge_sts |= htole32(VGE_TDSTS_OWN); 1438 1439 idx++; 1440 if (mnew == NULL) { 1441 /* if mbuf is coalesced, it is already dequeued */ 1442 IFQ_DEQUEUE(&ifp->if_snd, m_head); 1443 } 1444 return (0); 1445 } 1446 1447 /* 1448 * Main transmit routine. 1449 */ 1450 void 1451 vge_start(struct ifnet *ifp) 1452 { 1453 struct vge_softc *sc; 1454 struct mbuf *m_head = NULL; 1455 int idx, pidx = 0; 1456 1457 sc = ifp->if_softc; 1458 1459 if (!sc->vge_link || ifp->if_flags & IFF_OACTIVE) 1460 return; 1461 1462 if (IFQ_IS_EMPTY(&ifp->if_snd)) 1463 return; 1464 1465 idx = sc->vge_ldata.vge_tx_prodidx; 1466 1467 pidx = idx - 1; 1468 if (pidx < 0) 1469 pidx = VGE_TX_DESC_CNT - 1; 1470 1471 while (sc->vge_ldata.vge_tx_mbuf[idx] == NULL) { 1472 IFQ_POLL(&ifp->if_snd, m_head); 1473 if (m_head == NULL) 1474 break; 1475 1476 /* 1477 * If there's a BPF listener, bounce a copy of this frame 1478 * to him. 1479 */ 1480 #if NBPFILTER > 0 1481 if (ifp->if_bpf) 1482 bpf_mtap_ether(ifp->if_bpf, m_head, BPF_DIRECTION_OUT); 1483 #endif 1484 1485 if (vge_encap(sc, m_head, idx)) { 1486 ifp->if_flags |= IFF_OACTIVE; 1487 break; 1488 } 1489 1490 sc->vge_ldata.vge_tx_list[pidx].vge_frag[0].vge_buflen |= 1491 htole16(VGE_TXDESC_Q); 1492 1493 pidx = idx; 1494 VGE_TX_DESC_INC(idx); 1495 } 1496 1497 if (idx == sc->vge_ldata.vge_tx_prodidx) { 1498 return; 1499 } 1500 1501 /* Flush the TX descriptors */ 1502 1503 bus_dmamap_sync(sc->sc_dmat, 1504 sc->vge_ldata.vge_tx_list_map, 1505 0, sc->vge_ldata.vge_tx_list_map->dm_mapsize, 1506 BUS_DMASYNC_PREWRITE|BUS_DMASYNC_PREREAD); 1507 1508 /* Issue a transmit command. */ 1509 CSR_WRITE_2(sc, VGE_TXQCSRS, VGE_TXQCSR_WAK0); 1510 1511 sc->vge_ldata.vge_tx_prodidx = idx; 1512 1513 /* 1514 * Use the countdown timer for interrupt moderation. 1515 * 'TX done' interrupts are disabled. Instead, we reset the 1516 * countdown timer, which will begin counting until it hits 1517 * the value in the SSTIMER register, and then trigger an 1518 * interrupt. Each time we set the TIMER0_ENABLE bit, the 1519 * the timer count is reloaded. Only when the transmitter 1520 * is idle will the timer hit 0 and an interrupt fire. 1521 */ 1522 CSR_WRITE_1(sc, VGE_CRS1, VGE_CR1_TIMER0_ENABLE); 1523 1524 /* 1525 * Set a timeout in case the chip goes out to lunch. 1526 */ 1527 ifp->if_timer = 5; 1528 } 1529 1530 int 1531 vge_init(struct ifnet *ifp) 1532 { 1533 struct vge_softc *sc = ifp->if_softc; 1534 int i; 1535 1536 /* 1537 * Cancel pending I/O and free all RX/TX buffers. 1538 */ 1539 vge_stop(sc); 1540 vge_reset(sc); 1541 1542 /* Initialize RX descriptors list */ 1543 if (vge_rx_list_init(sc) == ENOBUFS) { 1544 printf("%s: init failed: no memory for RX buffers\n", 1545 sc->vge_dev.dv_xname); 1546 vge_stop(sc); 1547 return (ENOBUFS); 1548 } 1549 /* Initialize TX descriptors */ 1550 if (vge_tx_list_init(sc) == ENOBUFS) { 1551 printf("%s: init failed: no memory for TX buffers\n", 1552 sc->vge_dev.dv_xname); 1553 vge_stop(sc); 1554 return (ENOBUFS); 1555 } 1556 1557 /* Set our station address */ 1558 for (i = 0; i < ETHER_ADDR_LEN; i++) 1559 CSR_WRITE_1(sc, VGE_PAR0 + i, sc->arpcom.ac_enaddr[i]); 1560 1561 /* Set receive FIFO threshold */ 1562 CSR_CLRBIT_1(sc, VGE_RXCFG, VGE_RXCFG_FIFO_THR); 1563 CSR_SETBIT_1(sc, VGE_RXCFG, VGE_RXFIFOTHR_128BYTES); 1564 1565 if (ifp->if_capabilities & IFCAP_VLAN_HWTAGGING) { 1566 /* 1567 * Allow transmission and reception of VLAN tagged 1568 * frames. 1569 */ 1570 CSR_CLRBIT_1(sc, VGE_RXCFG, VGE_RXCFG_VTAGOPT); 1571 CSR_SETBIT_1(sc, VGE_RXCFG, VGE_VTAG_OPT2); 1572 } 1573 1574 /* Set DMA burst length */ 1575 CSR_CLRBIT_1(sc, VGE_DMACFG0, VGE_DMACFG0_BURSTLEN); 1576 CSR_SETBIT_1(sc, VGE_DMACFG0, VGE_DMABURST_128); 1577 1578 CSR_SETBIT_1(sc, VGE_TXCFG, VGE_TXCFG_ARB_PRIO|VGE_TXCFG_NONBLK); 1579 1580 /* Set collision backoff algorithm */ 1581 CSR_CLRBIT_1(sc, VGE_CHIPCFG1, VGE_CHIPCFG1_CRANDOM| 1582 VGE_CHIPCFG1_CAP|VGE_CHIPCFG1_MBA|VGE_CHIPCFG1_BAKOPT); 1583 CSR_SETBIT_1(sc, VGE_CHIPCFG1, VGE_CHIPCFG1_OFSET); 1584 1585 /* Disable LPSEL field in priority resolution */ 1586 CSR_SETBIT_1(sc, VGE_DIAGCTL, VGE_DIAGCTL_LPSEL_DIS); 1587 1588 /* 1589 * Load the addresses of the DMA queues into the chip. 1590 * Note that we only use one transmit queue. 1591 */ 1592 1593 CSR_WRITE_4(sc, VGE_TXDESC_ADDR_LO0, 1594 VGE_ADDR_LO(sc->vge_ldata.vge_tx_listseg.ds_addr)); 1595 CSR_WRITE_2(sc, VGE_TXDESCNUM, VGE_TX_DESC_CNT - 1); 1596 1597 CSR_WRITE_4(sc, VGE_RXDESC_ADDR_LO, 1598 VGE_ADDR_LO(sc->vge_ldata.vge_rx_listseg.ds_addr)); 1599 CSR_WRITE_2(sc, VGE_RXDESCNUM, VGE_RX_DESC_CNT - 1); 1600 CSR_WRITE_2(sc, VGE_RXDESC_RESIDUECNT, VGE_RX_DESC_CNT); 1601 1602 /* Enable and wake up the RX descriptor queue */ 1603 CSR_WRITE_1(sc, VGE_RXQCSRS, VGE_RXQCSR_RUN); 1604 CSR_WRITE_1(sc, VGE_RXQCSRS, VGE_RXQCSR_WAK); 1605 1606 /* Enable the TX descriptor queue */ 1607 CSR_WRITE_2(sc, VGE_TXQCSRS, VGE_TXQCSR_RUN0); 1608 1609 /* Set up the receive filter -- allow large frames for VLANs. */ 1610 CSR_WRITE_1(sc, VGE_RXCTL, VGE_RXCTL_RX_UCAST|VGE_RXCTL_RX_GIANT); 1611 1612 /* If we want promiscuous mode, set the allframes bit. */ 1613 if (ifp->if_flags & IFF_PROMISC) { 1614 CSR_SETBIT_1(sc, VGE_RXCTL, VGE_RXCTL_RX_PROMISC); 1615 } 1616 1617 /* Set capture broadcast bit to capture broadcast frames. */ 1618 if (ifp->if_flags & IFF_BROADCAST) { 1619 CSR_SETBIT_1(sc, VGE_RXCTL, VGE_RXCTL_RX_BCAST); 1620 } 1621 1622 /* Set multicast bit to capture multicast frames. */ 1623 if (ifp->if_flags & IFF_MULTICAST) { 1624 CSR_SETBIT_1(sc, VGE_RXCTL, VGE_RXCTL_RX_MCAST); 1625 } 1626 1627 /* Init the cam filter. */ 1628 vge_cam_clear(sc); 1629 1630 /* Init the multicast filter. */ 1631 vge_setmulti(sc); 1632 1633 /* Enable flow control */ 1634 1635 CSR_WRITE_1(sc, VGE_CRS2, 0x8B); 1636 1637 /* Enable jumbo frame reception (if desired) */ 1638 1639 /* Start the MAC. */ 1640 CSR_WRITE_1(sc, VGE_CRC0, VGE_CR0_STOP); 1641 CSR_WRITE_1(sc, VGE_CRS1, VGE_CR1_NOPOLL); 1642 CSR_WRITE_1(sc, VGE_CRS0, 1643 VGE_CR0_TX_ENABLE|VGE_CR0_RX_ENABLE|VGE_CR0_START); 1644 1645 /* 1646 * Configure one-shot timer for microsecond 1647 * resulution and load it for 500 usecs. 1648 */ 1649 CSR_SETBIT_1(sc, VGE_DIAGCTL, VGE_DIAGCTL_TIMER0_RES); 1650 CSR_WRITE_2(sc, VGE_SSTIMER, 400); 1651 1652 /* 1653 * Configure interrupt moderation for receive. Enable 1654 * the holdoff counter and load it, and set the RX 1655 * suppression count to the number of descriptors we 1656 * want to allow before triggering an interrupt. 1657 * The holdoff timer is in units of 20 usecs. 1658 */ 1659 1660 #ifdef notyet 1661 CSR_WRITE_1(sc, VGE_INTCTL1, VGE_INTCTL_TXINTSUP_DISABLE); 1662 /* Select the interrupt holdoff timer page. */ 1663 CSR_CLRBIT_1(sc, VGE_CAMCTL, VGE_CAMCTL_PAGESEL); 1664 CSR_SETBIT_1(sc, VGE_CAMCTL, VGE_PAGESEL_INTHLDOFF); 1665 CSR_WRITE_1(sc, VGE_INTHOLDOFF, 10); /* ~200 usecs */ 1666 1667 /* Enable use of the holdoff timer. */ 1668 CSR_WRITE_1(sc, VGE_CRS3, VGE_CR3_INT_HOLDOFF); 1669 CSR_WRITE_1(sc, VGE_INTCTL1, VGE_INTCTL_SC_RELOAD); 1670 1671 /* Select the RX suppression threshold page. */ 1672 CSR_CLRBIT_1(sc, VGE_CAMCTL, VGE_CAMCTL_PAGESEL); 1673 CSR_SETBIT_1(sc, VGE_CAMCTL, VGE_PAGESEL_RXSUPPTHR); 1674 CSR_WRITE_1(sc, VGE_RXSUPPTHR, 64); /* interrupt after 64 packets */ 1675 1676 /* Restore the page select bits. */ 1677 CSR_CLRBIT_1(sc, VGE_CAMCTL, VGE_CAMCTL_PAGESEL); 1678 CSR_SETBIT_1(sc, VGE_CAMCTL, VGE_PAGESEL_MAR); 1679 #endif 1680 1681 /* 1682 * Enable interrupts. 1683 */ 1684 CSR_WRITE_4(sc, VGE_IMR, VGE_INTRS); 1685 CSR_WRITE_4(sc, VGE_ISR, 0); 1686 CSR_WRITE_1(sc, VGE_CRS3, VGE_CR3_INT_GMSK); 1687 1688 /* Restore BMCR state */ 1689 mii_mediachg(&sc->sc_mii); 1690 1691 ifp->if_flags |= IFF_RUNNING; 1692 ifp->if_flags &= ~IFF_OACTIVE; 1693 1694 sc->vge_if_flags = 0; 1695 sc->vge_link = 0; 1696 1697 if (!timeout_pending(&sc->timer_handle)) 1698 timeout_add_sec(&sc->timer_handle, 1); 1699 1700 return (0); 1701 } 1702 1703 /* 1704 * Set media options. 1705 */ 1706 int 1707 vge_ifmedia_upd(struct ifnet *ifp) 1708 { 1709 struct vge_softc *sc = ifp->if_softc; 1710 1711 return (mii_mediachg(&sc->sc_mii)); 1712 } 1713 1714 /* 1715 * Report current media status. 1716 */ 1717 void 1718 vge_ifmedia_sts(struct ifnet *ifp, struct ifmediareq *ifmr) 1719 { 1720 struct vge_softc *sc = ifp->if_softc; 1721 1722 mii_pollstat(&sc->sc_mii); 1723 ifmr->ifm_active = sc->sc_mii.mii_media_active; 1724 ifmr->ifm_status = sc->sc_mii.mii_media_status; 1725 } 1726 1727 void 1728 vge_miibus_statchg(struct device *dev) 1729 { 1730 struct vge_softc *sc = (struct vge_softc *)dev; 1731 struct mii_data *mii; 1732 struct ifmedia_entry *ife; 1733 1734 mii = &sc->sc_mii; 1735 ife = mii->mii_media.ifm_cur; 1736 1737 /* 1738 * If the user manually selects a media mode, we need to turn 1739 * on the forced MAC mode bit in the DIAGCTL register. If the 1740 * user happens to choose a full duplex mode, we also need to 1741 * set the 'force full duplex' bit. This applies only to 1742 * 10Mbps and 100Mbps speeds. In autoselect mode, forced MAC 1743 * mode is disabled, and in 1000baseT mode, full duplex is 1744 * always implied, so we turn on the forced mode bit but leave 1745 * the FDX bit cleared. 1746 */ 1747 1748 switch (IFM_SUBTYPE(ife->ifm_media)) { 1749 case IFM_AUTO: 1750 CSR_CLRBIT_1(sc, VGE_DIAGCTL, VGE_DIAGCTL_MACFORCE); 1751 CSR_CLRBIT_1(sc, VGE_DIAGCTL, VGE_DIAGCTL_FDXFORCE); 1752 break; 1753 case IFM_1000_T: 1754 CSR_SETBIT_1(sc, VGE_DIAGCTL, VGE_DIAGCTL_MACFORCE); 1755 CSR_CLRBIT_1(sc, VGE_DIAGCTL, VGE_DIAGCTL_FDXFORCE); 1756 break; 1757 case IFM_100_TX: 1758 case IFM_10_T: 1759 CSR_SETBIT_1(sc, VGE_DIAGCTL, VGE_DIAGCTL_MACFORCE); 1760 if ((ife->ifm_media & IFM_GMASK) == IFM_FDX) { 1761 CSR_SETBIT_1(sc, VGE_DIAGCTL, VGE_DIAGCTL_FDXFORCE); 1762 } else { 1763 CSR_CLRBIT_1(sc, VGE_DIAGCTL, VGE_DIAGCTL_FDXFORCE); 1764 } 1765 break; 1766 default: 1767 printf("%s: unknown media type: %x\n", 1768 sc->vge_dev.dv_xname, IFM_SUBTYPE(ife->ifm_media)); 1769 break; 1770 } 1771 } 1772 1773 int 1774 vge_ioctl(struct ifnet *ifp, u_long command, caddr_t data) 1775 { 1776 struct vge_softc *sc = ifp->if_softc; 1777 struct ifaddr *ifa = (struct ifaddr *) data; 1778 struct ifreq *ifr = (struct ifreq *) data; 1779 int s, error = 0; 1780 1781 s = splnet(); 1782 1783 switch (command) { 1784 case SIOCSIFADDR: 1785 ifp->if_flags |= IFF_UP; 1786 switch (ifa->ifa_addr->sa_family) { 1787 #ifdef INET 1788 case AF_INET: 1789 vge_init(ifp); 1790 arp_ifinit(&sc->arpcom, ifa); 1791 break; 1792 #endif 1793 default: 1794 vge_init(ifp); 1795 break; 1796 } 1797 break; 1798 1799 case SIOCSIFFLAGS: 1800 if (ifp->if_flags & IFF_UP) { 1801 if (ifp->if_flags & IFF_RUNNING && 1802 ifp->if_flags & IFF_PROMISC && 1803 !(sc->vge_if_flags & IFF_PROMISC)) { 1804 CSR_SETBIT_1(sc, VGE_RXCTL, 1805 VGE_RXCTL_RX_PROMISC); 1806 vge_setmulti(sc); 1807 } else if (ifp->if_flags & IFF_RUNNING && 1808 !(ifp->if_flags & IFF_PROMISC) && 1809 sc->vge_if_flags & IFF_PROMISC) { 1810 CSR_CLRBIT_1(sc, VGE_RXCTL, 1811 VGE_RXCTL_RX_PROMISC); 1812 vge_setmulti(sc); 1813 } else 1814 vge_init(ifp); 1815 } else { 1816 if (ifp->if_flags & IFF_RUNNING) 1817 vge_stop(sc); 1818 } 1819 sc->vge_if_flags = ifp->if_flags; 1820 break; 1821 1822 case SIOCGIFMEDIA: 1823 case SIOCSIFMEDIA: 1824 error = ifmedia_ioctl(ifp, ifr, &sc->sc_mii.mii_media, command); 1825 break; 1826 1827 default: 1828 error = ether_ioctl(ifp, &sc->arpcom, command, data); 1829 } 1830 1831 if (error == ENETRESET) { 1832 if (ifp->if_flags & IFF_RUNNING) 1833 vge_setmulti(sc); 1834 error = 0; 1835 } 1836 1837 splx(s); 1838 return (error); 1839 } 1840 1841 void 1842 vge_watchdog(struct ifnet *ifp) 1843 { 1844 struct vge_softc *sc = ifp->if_softc; 1845 int s; 1846 1847 s = splnet(); 1848 printf("%s: watchdog timeout\n", sc->vge_dev.dv_xname); 1849 ifp->if_oerrors++; 1850 1851 vge_txeof(sc); 1852 vge_rxeof(sc); 1853 1854 vge_init(ifp); 1855 1856 splx(s); 1857 } 1858 1859 /* 1860 * Stop the adapter and free any mbufs allocated to the 1861 * RX and TX lists. 1862 */ 1863 void 1864 vge_stop(struct vge_softc *sc) 1865 { 1866 int i; 1867 struct ifnet *ifp; 1868 1869 ifp = &sc->arpcom.ac_if; 1870 ifp->if_timer = 0; 1871 1872 timeout_del(&sc->timer_handle); 1873 1874 ifp->if_flags &= ~(IFF_RUNNING | IFF_OACTIVE); 1875 1876 CSR_WRITE_1(sc, VGE_CRC3, VGE_CR3_INT_GMSK); 1877 CSR_WRITE_1(sc, VGE_CRS0, VGE_CR0_STOP); 1878 CSR_WRITE_4(sc, VGE_ISR, 0xFFFFFFFF); 1879 CSR_WRITE_2(sc, VGE_TXQCSRC, 0xFFFF); 1880 CSR_WRITE_1(sc, VGE_RXQCSRC, 0xFF); 1881 CSR_WRITE_4(sc, VGE_RXDESC_ADDR_LO, 0); 1882 1883 if (sc->vge_head != NULL) { 1884 m_freem(sc->vge_head); 1885 sc->vge_head = sc->vge_tail = NULL; 1886 } 1887 1888 /* Free the TX list buffers. */ 1889 for (i = 0; i < VGE_TX_DESC_CNT; i++) { 1890 if (sc->vge_ldata.vge_tx_mbuf[i] != NULL) { 1891 bus_dmamap_unload(sc->sc_dmat, 1892 sc->vge_ldata.vge_tx_dmamap[i]); 1893 m_freem(sc->vge_ldata.vge_tx_mbuf[i]); 1894 sc->vge_ldata.vge_tx_mbuf[i] = NULL; 1895 } 1896 } 1897 1898 /* Free the RX list buffers. */ 1899 for (i = 0; i < VGE_RX_DESC_CNT; i++) { 1900 if (sc->vge_ldata.vge_rx_mbuf[i] != NULL) { 1901 bus_dmamap_unload(sc->sc_dmat, 1902 sc->vge_ldata.vge_rx_dmamap[i]); 1903 m_freem(sc->vge_ldata.vge_rx_mbuf[i]); 1904 sc->vge_ldata.vge_rx_mbuf[i] = NULL; 1905 } 1906 } 1907 } 1908