1 /* $OpenBSD: if_vge.c,v 1.43 2008/11/28 02:44:18 brad Exp $ */ 2 /* $FreeBSD: if_vge.c,v 1.3 2004/09/11 22:13:25 wpaul Exp $ */ 3 /* 4 * Copyright (c) 2004 5 * Bill Paul <wpaul@windriver.com>. All rights reserved. 6 * 7 * Redistribution and use in source and binary forms, with or without 8 * modification, are permitted provided that the following conditions 9 * are met: 10 * 1. Redistributions of source code must retain the above copyright 11 * notice, this list of conditions and the following disclaimer. 12 * 2. Redistributions in binary form must reproduce the above copyright 13 * notice, this list of conditions and the following disclaimer in the 14 * documentation and/or other materials provided with the distribution. 15 * 3. All advertising materials mentioning features or use of this software 16 * must display the following acknowledgement: 17 * This product includes software developed by Bill Paul. 18 * 4. Neither the name of the author nor the names of any co-contributors 19 * may be used to endorse or promote products derived from this software 20 * without specific prior written permission. 21 * 22 * THIS SOFTWARE IS PROVIDED BY Bill Paul AND CONTRIBUTORS ``AS IS'' AND 23 * ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE 24 * IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE 25 * ARE DISCLAIMED. IN NO EVENT SHALL Bill Paul OR THE VOICES IN HIS HEAD 26 * BE LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR 27 * CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF 28 * SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS 29 * INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN 30 * CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) 31 * ARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF 32 * THE POSSIBILITY OF SUCH DAMAGE. 33 */ 34 35 /* 36 * VIA Networking Technologies VT612x PCI gigabit ethernet NIC driver. 37 * 38 * Written by Bill Paul <wpaul@windriver.com> 39 * Senior Networking Software Engineer 40 * Wind River Systems 41 * 42 * Ported to OpenBSD by Peter Valchev <pvalchev@openbsd.org> 43 */ 44 45 /* 46 * The VIA Networking VT6122 is a 32bit, 33/66MHz PCI device that 47 * combines a tri-speed ethernet MAC and PHY, with the following 48 * features: 49 * 50 * o Jumbo frame support up to 16K 51 * o Transmit and receive flow control 52 * o IPv4 checksum offload 53 * o VLAN tag insertion and stripping 54 * o TCP large send 55 * o 64-bit multicast hash table filter 56 * o 64 entry CAM filter 57 * o 16K RX FIFO and 48K TX FIFO memory 58 * o Interrupt moderation 59 * 60 * The VT6122 supports up to four transmit DMA queues. The descriptors 61 * in the transmit ring can address up to 7 data fragments; frames which 62 * span more than 7 data buffers must be coalesced, but in general the 63 * BSD TCP/IP stack rarely generates frames more than 2 or 3 fragments 64 * long. The receive descriptors address only a single buffer. 65 * 66 * There are two peculiar design issues with the VT6122. One is that 67 * receive data buffers must be aligned on a 32-bit boundary. This is 68 * not a problem where the VT6122 is used as a LOM device in x86-based 69 * systems, but on architectures that generate unaligned access traps, we 70 * have to do some copying. 71 * 72 * The other issue has to do with the way 64-bit addresses are handled. 73 * The DMA descriptors only allow you to specify 48 bits of addressing 74 * information. The remaining 16 bits are specified using one of the 75 * I/O registers. If you only have a 32-bit system, then this isn't 76 * an issue, but if you have a 64-bit system and more than 4GB of 77 * memory, you must have to make sure your network data buffers reside 78 * in the same 48-bit 'segment.' 79 * 80 * Special thanks to Ryan Fu at VIA Networking for providing documentation 81 * and sample NICs for testing. 82 */ 83 84 #include "bpfilter.h" 85 #include "vlan.h" 86 87 #include <sys/param.h> 88 #include <sys/endian.h> 89 #include <sys/systm.h> 90 #include <sys/sockio.h> 91 #include <sys/mbuf.h> 92 #include <sys/malloc.h> 93 #include <sys/kernel.h> 94 #include <sys/device.h> 95 #include <sys/timeout.h> 96 #include <sys/socket.h> 97 98 #include <net/if.h> 99 #include <net/if_dl.h> 100 #include <net/if_media.h> 101 102 #ifdef INET 103 #include <netinet/in.h> 104 #include <netinet/in_systm.h> 105 #include <netinet/in_var.h> 106 #include <netinet/ip.h> 107 #include <netinet/if_ether.h> 108 #endif 109 110 #if NVLAN > 0 111 #include <net/if_types.h> 112 #include <net/if_vlan_var.h> 113 #endif 114 115 #if NBPFILTER > 0 116 #include <net/bpf.h> 117 #endif 118 119 #include <dev/mii/mii.h> 120 #include <dev/mii/miivar.h> 121 122 #include <dev/pci/pcireg.h> 123 #include <dev/pci/pcivar.h> 124 #include <dev/pci/pcidevs.h> 125 126 #include <dev/pci/if_vgereg.h> 127 #include <dev/pci/if_vgevar.h> 128 129 int vge_probe (struct device *, void *, void *); 130 void vge_attach (struct device *, struct device *, void *); 131 132 int vge_encap (struct vge_softc *, struct mbuf *, int); 133 134 int vge_allocmem (struct vge_softc *); 135 int vge_newbuf (struct vge_softc *, int, struct mbuf *); 136 int vge_rx_list_init (struct vge_softc *); 137 int vge_tx_list_init (struct vge_softc *); 138 void vge_rxeof (struct vge_softc *); 139 void vge_txeof (struct vge_softc *); 140 int vge_intr (void *); 141 void vge_tick (void *); 142 void vge_start (struct ifnet *); 143 int vge_ioctl (struct ifnet *, u_long, caddr_t); 144 int vge_init (struct ifnet *); 145 void vge_stop (struct vge_softc *); 146 void vge_watchdog (struct ifnet *); 147 int vge_ifmedia_upd (struct ifnet *); 148 void vge_ifmedia_sts (struct ifnet *, struct ifmediareq *); 149 150 #ifdef VGE_EEPROM 151 void vge_eeprom_getword (struct vge_softc *, int, u_int16_t *); 152 #endif 153 void vge_read_eeprom (struct vge_softc *, caddr_t, int, int, int); 154 155 void vge_miipoll_start (struct vge_softc *); 156 void vge_miipoll_stop (struct vge_softc *); 157 int vge_miibus_readreg (struct device *, int, int); 158 void vge_miibus_writereg (struct device *, int, int, int); 159 void vge_miibus_statchg (struct device *); 160 161 void vge_cam_clear (struct vge_softc *); 162 int vge_cam_set (struct vge_softc *, uint8_t *); 163 void vge_setmulti (struct vge_softc *); 164 void vge_reset (struct vge_softc *); 165 166 struct cfattach vge_ca = { 167 sizeof(struct vge_softc), vge_probe, vge_attach 168 }; 169 170 struct cfdriver vge_cd = { 171 0, "vge", DV_IFNET 172 }; 173 174 #define VGE_PCI_LOIO 0x10 175 #define VGE_PCI_LOMEM 0x14 176 177 int vge_debug = 0; 178 #define DPRINTF(x) if (vge_debug) printf x 179 #define DPRINTFN(n, x) if (vge_debug >= (n)) printf x 180 181 const struct pci_matchid vge_devices[] = { 182 { PCI_VENDOR_VIATECH, PCI_PRODUCT_VIATECH_VT612x }, 183 }; 184 185 #ifdef VGE_EEPROM 186 /* 187 * Read a word of data stored in the EEPROM at address 'addr.' 188 */ 189 void 190 vge_eeprom_getword(struct vge_softc *sc, int addr, u_int16_t *dest) 191 { 192 int i; 193 u_int16_t word = 0; 194 195 /* 196 * Enter EEPROM embedded programming mode. In order to 197 * access the EEPROM at all, we first have to set the 198 * EELOAD bit in the CHIPCFG2 register. 199 */ 200 CSR_SETBIT_1(sc, VGE_CHIPCFG2, VGE_CHIPCFG2_EELOAD); 201 CSR_SETBIT_1(sc, VGE_EECSR, VGE_EECSR_EMBP/*|VGE_EECSR_ECS*/); 202 203 /* Select the address of the word we want to read */ 204 CSR_WRITE_1(sc, VGE_EEADDR, addr); 205 206 /* Issue read command */ 207 CSR_SETBIT_1(sc, VGE_EECMD, VGE_EECMD_ERD); 208 209 /* Wait for the done bit to be set. */ 210 for (i = 0; i < VGE_TIMEOUT; i++) { 211 if (CSR_READ_1(sc, VGE_EECMD) & VGE_EECMD_EDONE) 212 break; 213 } 214 215 if (i == VGE_TIMEOUT) { 216 printf("%s: EEPROM read timed out\n", sc->vge_dev.dv_xname); 217 *dest = 0; 218 return; 219 } 220 221 /* Read the result */ 222 word = CSR_READ_2(sc, VGE_EERDDAT); 223 224 /* Turn off EEPROM access mode. */ 225 CSR_CLRBIT_1(sc, VGE_EECSR, VGE_EECSR_EMBP/*|VGE_EECSR_ECS*/); 226 CSR_CLRBIT_1(sc, VGE_CHIPCFG2, VGE_CHIPCFG2_EELOAD); 227 228 *dest = word; 229 } 230 #endif 231 232 /* 233 * Read a sequence of words from the EEPROM. 234 */ 235 void 236 vge_read_eeprom(struct vge_softc *sc, caddr_t dest, int off, int cnt, 237 int swap) 238 { 239 int i; 240 #ifdef VGE_EEPROM 241 u_int16_t word = 0, *ptr; 242 243 for (i = 0; i < cnt; i++) { 244 vge_eeprom_getword(sc, off + i, &word); 245 ptr = (u_int16_t *)(dest + (i * 2)); 246 if (swap) 247 *ptr = ntohs(word); 248 else 249 *ptr = word; 250 } 251 #else 252 for (i = 0; i < ETHER_ADDR_LEN; i++) 253 dest[i] = CSR_READ_1(sc, VGE_PAR0 + i); 254 #endif 255 } 256 257 void 258 vge_miipoll_stop(struct vge_softc *sc) 259 { 260 int i; 261 262 CSR_WRITE_1(sc, VGE_MIICMD, 0); 263 264 for (i = 0; i < VGE_TIMEOUT; i++) { 265 DELAY(1); 266 if (CSR_READ_1(sc, VGE_MIISTS) & VGE_MIISTS_IIDL) 267 break; 268 } 269 270 if (i == VGE_TIMEOUT) 271 printf("%s: failed to idle MII autopoll\n", sc->vge_dev.dv_xname); 272 } 273 274 void 275 vge_miipoll_start(struct vge_softc *sc) 276 { 277 int i; 278 279 /* First, make sure we're idle. */ 280 281 CSR_WRITE_1(sc, VGE_MIICMD, 0); 282 CSR_WRITE_1(sc, VGE_MIIADDR, VGE_MIIADDR_SWMPL); 283 284 for (i = 0; i < VGE_TIMEOUT; i++) { 285 DELAY(1); 286 if (CSR_READ_1(sc, VGE_MIISTS) & VGE_MIISTS_IIDL) 287 break; 288 } 289 290 if (i == VGE_TIMEOUT) { 291 printf("%s: failed to idle MII autopoll\n", sc->vge_dev.dv_xname); 292 return; 293 } 294 295 /* Now enable auto poll mode. */ 296 297 CSR_WRITE_1(sc, VGE_MIICMD, VGE_MIICMD_MAUTO); 298 299 /* And make sure it started. */ 300 301 for (i = 0; i < VGE_TIMEOUT; i++) { 302 DELAY(1); 303 if ((CSR_READ_1(sc, VGE_MIISTS) & VGE_MIISTS_IIDL) == 0) 304 break; 305 } 306 307 if (i == VGE_TIMEOUT) 308 printf("%s: failed to start MII autopoll\n", sc->vge_dev.dv_xname); 309 } 310 311 int 312 vge_miibus_readreg(struct device *dev, int phy, int reg) 313 { 314 struct vge_softc *sc = (struct vge_softc *)dev; 315 int i, s; 316 u_int16_t rval = 0; 317 318 if (phy != (CSR_READ_1(sc, VGE_MIICFG) & 0x1F)) 319 return(0); 320 321 s = splnet(); 322 323 vge_miipoll_stop(sc); 324 325 /* Specify the register we want to read. */ 326 CSR_WRITE_1(sc, VGE_MIIADDR, reg); 327 328 /* Issue read command. */ 329 CSR_SETBIT_1(sc, VGE_MIICMD, VGE_MIICMD_RCMD); 330 331 /* Wait for the read command bit to self-clear. */ 332 for (i = 0; i < VGE_TIMEOUT; i++) { 333 DELAY(1); 334 if ((CSR_READ_1(sc, VGE_MIICMD) & VGE_MIICMD_RCMD) == 0) 335 break; 336 } 337 338 if (i == VGE_TIMEOUT) 339 printf("%s: MII read timed out\n", sc->vge_dev.dv_xname); 340 else 341 rval = CSR_READ_2(sc, VGE_MIIDATA); 342 343 vge_miipoll_start(sc); 344 splx(s); 345 346 return (rval); 347 } 348 349 void 350 vge_miibus_writereg(struct device *dev, int phy, int reg, int data) 351 { 352 struct vge_softc *sc = (struct vge_softc *)dev; 353 int i, s; 354 355 if (phy != (CSR_READ_1(sc, VGE_MIICFG) & 0x1F)) 356 return; 357 358 s = splnet(); 359 vge_miipoll_stop(sc); 360 361 /* Specify the register we want to write. */ 362 CSR_WRITE_1(sc, VGE_MIIADDR, reg); 363 364 /* Specify the data we want to write. */ 365 CSR_WRITE_2(sc, VGE_MIIDATA, data); 366 367 /* Issue write command. */ 368 CSR_SETBIT_1(sc, VGE_MIICMD, VGE_MIICMD_WCMD); 369 370 /* Wait for the write command bit to self-clear. */ 371 for (i = 0; i < VGE_TIMEOUT; i++) { 372 DELAY(1); 373 if ((CSR_READ_1(sc, VGE_MIICMD) & VGE_MIICMD_WCMD) == 0) 374 break; 375 } 376 377 if (i == VGE_TIMEOUT) { 378 printf("%s: MII write timed out\n", sc->vge_dev.dv_xname); 379 } 380 381 vge_miipoll_start(sc); 382 splx(s); 383 } 384 385 void 386 vge_cam_clear(struct vge_softc *sc) 387 { 388 int i; 389 390 /* 391 * Turn off all the mask bits. This tells the chip 392 * that none of the entries in the CAM filter are valid. 393 * desired entries will be enabled as we fill the filter in. 394 */ 395 396 CSR_CLRBIT_1(sc, VGE_CAMCTL, VGE_CAMCTL_PAGESEL); 397 CSR_SETBIT_1(sc, VGE_CAMCTL, VGE_PAGESEL_CAMMASK); 398 CSR_WRITE_1(sc, VGE_CAMADDR, VGE_CAMADDR_ENABLE); 399 for (i = 0; i < 8; i++) 400 CSR_WRITE_1(sc, VGE_CAM0 + i, 0); 401 402 /* Clear the VLAN filter too. */ 403 404 CSR_WRITE_1(sc, VGE_CAMADDR, VGE_CAMADDR_ENABLE|VGE_CAMADDR_AVSEL|0); 405 for (i = 0; i < 8; i++) 406 CSR_WRITE_1(sc, VGE_CAM0 + i, 0); 407 408 CSR_WRITE_1(sc, VGE_CAMADDR, 0); 409 CSR_CLRBIT_1(sc, VGE_CAMCTL, VGE_CAMCTL_PAGESEL); 410 CSR_SETBIT_1(sc, VGE_CAMCTL, VGE_PAGESEL_MAR); 411 412 sc->vge_camidx = 0; 413 } 414 415 int 416 vge_cam_set(struct vge_softc *sc, uint8_t *addr) 417 { 418 int i, error = 0; 419 420 if (sc->vge_camidx == VGE_CAM_MAXADDRS) 421 return(ENOSPC); 422 423 /* Select the CAM data page. */ 424 CSR_CLRBIT_1(sc, VGE_CAMCTL, VGE_CAMCTL_PAGESEL); 425 CSR_SETBIT_1(sc, VGE_CAMCTL, VGE_PAGESEL_CAMDATA); 426 427 /* Set the filter entry we want to update and enable writing. */ 428 CSR_WRITE_1(sc, VGE_CAMADDR, VGE_CAMADDR_ENABLE|sc->vge_camidx); 429 430 /* Write the address to the CAM registers */ 431 for (i = 0; i < ETHER_ADDR_LEN; i++) 432 CSR_WRITE_1(sc, VGE_CAM0 + i, addr[i]); 433 434 /* Issue a write command. */ 435 CSR_SETBIT_1(sc, VGE_CAMCTL, VGE_CAMCTL_WRITE); 436 437 /* Wake for it to clear. */ 438 for (i = 0; i < VGE_TIMEOUT; i++) { 439 DELAY(1); 440 if ((CSR_READ_1(sc, VGE_CAMCTL) & VGE_CAMCTL_WRITE) == 0) 441 break; 442 } 443 444 if (i == VGE_TIMEOUT) { 445 printf("%s: setting CAM filter failed\n", sc->vge_dev.dv_xname); 446 error = EIO; 447 goto fail; 448 } 449 450 /* Select the CAM mask page. */ 451 CSR_CLRBIT_1(sc, VGE_CAMCTL, VGE_CAMCTL_PAGESEL); 452 CSR_SETBIT_1(sc, VGE_CAMCTL, VGE_PAGESEL_CAMMASK); 453 454 /* Set the mask bit that enables this filter. */ 455 CSR_SETBIT_1(sc, VGE_CAM0 + (sc->vge_camidx/8), 456 1<<(sc->vge_camidx & 7)); 457 458 sc->vge_camidx++; 459 460 fail: 461 /* Turn off access to CAM. */ 462 CSR_WRITE_1(sc, VGE_CAMADDR, 0); 463 CSR_CLRBIT_1(sc, VGE_CAMCTL, VGE_CAMCTL_PAGESEL); 464 CSR_SETBIT_1(sc, VGE_CAMCTL, VGE_PAGESEL_MAR); 465 466 return (error); 467 } 468 469 /* 470 * Program the multicast filter. We use the 64-entry CAM filter 471 * for perfect filtering. If there's more than 64 multicast addresses, 472 * we use the hash filter instead. 473 */ 474 void 475 vge_setmulti(struct vge_softc *sc) 476 { 477 struct arpcom *ac = &sc->arpcom; 478 struct ifnet *ifp = &ac->ac_if; 479 struct ether_multi *enm; 480 struct ether_multistep step; 481 int error; 482 u_int32_t h = 0, hashes[2] = { 0, 0 }; 483 484 /* First, zot all the multicast entries. */ 485 vge_cam_clear(sc); 486 CSR_WRITE_4(sc, VGE_MAR0, 0); 487 CSR_WRITE_4(sc, VGE_MAR1, 0); 488 ifp->if_flags &= ~IFF_ALLMULTI; 489 490 /* 491 * If the user wants allmulti or promisc mode, enable reception 492 * of all multicast frames. 493 */ 494 if (ifp->if_flags & IFF_PROMISC) { 495 allmulti: 496 CSR_WRITE_4(sc, VGE_MAR0, 0xFFFFFFFF); 497 CSR_WRITE_4(sc, VGE_MAR1, 0xFFFFFFFF); 498 ifp->if_flags |= IFF_ALLMULTI; 499 return; 500 } 501 502 /* Now program new ones */ 503 ETHER_FIRST_MULTI(step, ac, enm); 504 while (enm != NULL) { 505 if (bcmp(enm->enm_addrlo, enm->enm_addrhi, ETHER_ADDR_LEN)) 506 goto allmulti; 507 508 error = vge_cam_set(sc, enm->enm_addrlo); 509 if (error) 510 break; 511 512 ETHER_NEXT_MULTI(step, enm); 513 } 514 515 /* If there were too many addresses, use the hash filter. */ 516 if (error) { 517 vge_cam_clear(sc); 518 519 ETHER_FIRST_MULTI(step, ac, enm); 520 while (enm != NULL) { 521 h = ether_crc32_be(enm->enm_addrlo, 522 ETHER_ADDR_LEN) >> 26; 523 hashes[h >> 5] |= 1 << (h & 0x1f); 524 525 ETHER_NEXT_MULTI(step, enm); 526 } 527 528 CSR_WRITE_4(sc, VGE_MAR0, hashes[0]); 529 CSR_WRITE_4(sc, VGE_MAR1, hashes[1]); 530 } 531 } 532 533 void 534 vge_reset(struct vge_softc *sc) 535 { 536 int i; 537 538 CSR_WRITE_1(sc, VGE_CRS1, VGE_CR1_SOFTRESET); 539 540 for (i = 0; i < VGE_TIMEOUT; i++) { 541 DELAY(5); 542 if ((CSR_READ_1(sc, VGE_CRS1) & VGE_CR1_SOFTRESET) == 0) 543 break; 544 } 545 546 if (i == VGE_TIMEOUT) { 547 printf("%s: soft reset timed out", sc->vge_dev.dv_xname); 548 CSR_WRITE_1(sc, VGE_CRS3, VGE_CR3_STOP_FORCE); 549 DELAY(2000); 550 } 551 552 DELAY(5000); 553 554 CSR_SETBIT_1(sc, VGE_EECSR, VGE_EECSR_RELOAD); 555 556 for (i = 0; i < VGE_TIMEOUT; i++) { 557 DELAY(5); 558 if ((CSR_READ_1(sc, VGE_EECSR) & VGE_EECSR_RELOAD) == 0) 559 break; 560 } 561 562 if (i == VGE_TIMEOUT) { 563 printf("%s: EEPROM reload timed out\n", sc->vge_dev.dv_xname); 564 return; 565 } 566 567 CSR_CLRBIT_1(sc, VGE_CHIPCFG0, VGE_CHIPCFG0_PACPI); 568 } 569 570 /* 571 * Probe for a VIA gigabit chip. Check the PCI vendor and device 572 * IDs against our list and return a device name if we find a match. 573 */ 574 int 575 vge_probe(struct device *dev, void *match, void *aux) 576 { 577 return (pci_matchbyid((struct pci_attach_args *)aux, vge_devices, 578 sizeof(vge_devices)/sizeof(vge_devices[0]))); 579 } 580 581 /* 582 * Allocate memory for RX/TX rings 583 */ 584 int 585 vge_allocmem(struct vge_softc *sc) 586 { 587 int nseg, rseg; 588 int i, error; 589 590 nseg = 32; 591 592 /* Allocate DMA'able memory for the TX ring */ 593 594 error = bus_dmamap_create(sc->sc_dmat, VGE_TX_LIST_SZ, 1, 595 VGE_TX_LIST_SZ, 0, BUS_DMA_ALLOCNOW, 596 &sc->vge_ldata.vge_tx_list_map); 597 if (error) 598 return (ENOMEM); 599 error = bus_dmamem_alloc(sc->sc_dmat, VGE_TX_LIST_SZ, 600 ETHER_ALIGN, 0, 601 &sc->vge_ldata.vge_tx_listseg, 1, &rseg, BUS_DMA_NOWAIT); 602 if (error) { 603 printf("%s: can't alloc TX list\n", sc->vge_dev.dv_xname); 604 return (ENOMEM); 605 } 606 607 /* Load the map for the TX ring. */ 608 error = bus_dmamem_map(sc->sc_dmat, &sc->vge_ldata.vge_tx_listseg, 609 1, VGE_TX_LIST_SZ, 610 (caddr_t *)&sc->vge_ldata.vge_tx_list, BUS_DMA_NOWAIT); 611 memset(sc->vge_ldata.vge_tx_list, 0, VGE_TX_LIST_SZ); 612 if (error) { 613 printf("%s: can't map TX dma buffers\n", 614 sc->vge_dev.dv_xname); 615 bus_dmamem_free(sc->sc_dmat, &sc->vge_ldata.vge_tx_listseg, rseg); 616 return (ENOMEM); 617 } 618 619 error = bus_dmamap_load(sc->sc_dmat, sc->vge_ldata.vge_tx_list_map, 620 sc->vge_ldata.vge_tx_list, VGE_TX_LIST_SZ, NULL, BUS_DMA_NOWAIT); 621 if (error) { 622 printf("%s: can't load TX dma map\n", sc->vge_dev.dv_xname); 623 bus_dmamap_destroy(sc->sc_dmat, sc->vge_ldata.vge_tx_list_map); 624 bus_dmamem_unmap(sc->sc_dmat, (caddr_t)sc->vge_ldata.vge_tx_list, 625 VGE_TX_LIST_SZ); 626 bus_dmamem_free(sc->sc_dmat, &sc->vge_ldata.vge_tx_listseg, rseg); 627 return (ENOMEM); 628 } 629 630 /* Create DMA maps for TX buffers */ 631 632 for (i = 0; i < VGE_TX_DESC_CNT; i++) { 633 error = bus_dmamap_create(sc->sc_dmat, MCLBYTES * nseg, nseg, 634 MCLBYTES, 0, BUS_DMA_ALLOCNOW, 635 &sc->vge_ldata.vge_tx_dmamap[i]); 636 if (error) { 637 printf("%s: can't create DMA map for TX\n", 638 sc->vge_dev.dv_xname); 639 return (ENOMEM); 640 } 641 } 642 643 /* Allocate DMA'able memory for the RX ring */ 644 645 error = bus_dmamap_create(sc->sc_dmat, VGE_RX_LIST_SZ, 1, 646 VGE_RX_LIST_SZ, 0, BUS_DMA_ALLOCNOW, 647 &sc->vge_ldata.vge_rx_list_map); 648 if (error) 649 return (ENOMEM); 650 error = bus_dmamem_alloc(sc->sc_dmat, VGE_RX_LIST_SZ, VGE_RING_ALIGN, 651 0, &sc->vge_ldata.vge_rx_listseg, 1, &rseg, BUS_DMA_NOWAIT); 652 if (error) { 653 printf("%s: can't alloc RX list\n", sc->vge_dev.dv_xname); 654 return (ENOMEM); 655 } 656 657 /* Load the map for the RX ring. */ 658 659 error = bus_dmamem_map(sc->sc_dmat, &sc->vge_ldata.vge_rx_listseg, 660 1, VGE_RX_LIST_SZ, 661 (caddr_t *)&sc->vge_ldata.vge_rx_list, BUS_DMA_NOWAIT); 662 memset(sc->vge_ldata.vge_rx_list, 0, VGE_RX_LIST_SZ); 663 if (error) { 664 printf("%s: can't map RX dma buffers\n", 665 sc->vge_dev.dv_xname); 666 bus_dmamem_free(sc->sc_dmat, &sc->vge_ldata.vge_rx_listseg, rseg); 667 return (ENOMEM); 668 } 669 error = bus_dmamap_load(sc->sc_dmat, sc->vge_ldata.vge_rx_list_map, 670 sc->vge_ldata.vge_rx_list, VGE_RX_LIST_SZ, NULL, BUS_DMA_NOWAIT); 671 if (error) { 672 printf("%s: can't load RX dma map\n", sc->vge_dev.dv_xname); 673 bus_dmamap_destroy(sc->sc_dmat, sc->vge_ldata.vge_rx_list_map); 674 bus_dmamem_unmap(sc->sc_dmat, (caddr_t)sc->vge_ldata.vge_rx_list, 675 VGE_RX_LIST_SZ); 676 bus_dmamem_free(sc->sc_dmat, &sc->vge_ldata.vge_rx_listseg, rseg); 677 return (ENOMEM); 678 } 679 680 /* Create DMA maps for RX buffers */ 681 682 for (i = 0; i < VGE_RX_DESC_CNT; i++) { 683 error = bus_dmamap_create(sc->sc_dmat, MCLBYTES * nseg, nseg, 684 MCLBYTES, 0, BUS_DMA_ALLOCNOW, 685 &sc->vge_ldata.vge_rx_dmamap[i]); 686 if (error) { 687 printf("%s: can't create DMA map for RX\n", 688 sc->vge_dev.dv_xname); 689 return (ENOMEM); 690 } 691 } 692 693 return (0); 694 } 695 696 /* 697 * Attach the interface. Allocate softc structures, do ifmedia 698 * setup and ethernet/BPF attach. 699 */ 700 void 701 vge_attach(struct device *parent, struct device *self, void *aux) 702 { 703 u_char eaddr[ETHER_ADDR_LEN]; 704 u_int16_t as[3]; 705 struct vge_softc *sc = (struct vge_softc *)self; 706 struct pci_attach_args *pa = aux; 707 pci_chipset_tag_t pc = pa->pa_pc; 708 pci_intr_handle_t ih; 709 const char *intrstr = NULL; 710 struct ifnet *ifp; 711 int error = 0, i; 712 bus_size_t iosize; 713 714 /* 715 * Map control/status registers. 716 */ 717 if (pci_mapreg_map(pa, VGE_PCI_LOMEM, PCI_MAPREG_TYPE_MEM, 0, 718 &sc->vge_btag, &sc->vge_bhandle, NULL, &iosize, 0)) { 719 if (pci_mapreg_map(pa, VGE_PCI_LOIO, PCI_MAPREG_TYPE_IO, 0, 720 &sc->vge_btag, &sc->vge_bhandle, NULL, &iosize, 0)) { 721 printf(": can't map mem or i/o space\n"); 722 return; 723 } 724 } 725 726 /* Allocate interrupt */ 727 if (pci_intr_map(pa, &ih)) { 728 printf(": couldn't map interrupt\n"); 729 return; 730 } 731 intrstr = pci_intr_string(pc, ih); 732 sc->vge_intrhand = pci_intr_establish(pc, ih, IPL_NET, vge_intr, sc, 733 sc->vge_dev.dv_xname); 734 if (sc->vge_intrhand == NULL) { 735 printf(": couldn't establish interrupt"); 736 if (intrstr != NULL) 737 printf(" at %s", intrstr); 738 return; 739 } 740 printf(": %s", intrstr); 741 742 sc->sc_dmat = pa->pa_dmat; 743 744 /* Reset the adapter. */ 745 vge_reset(sc); 746 747 /* 748 * Get station address from the EEPROM. 749 */ 750 vge_read_eeprom(sc, (caddr_t)as, VGE_EE_EADDR, 3, 0); 751 for (i = 0; i < 3; i++) { 752 eaddr[(i * 2) + 0] = as[i] & 0xff; 753 eaddr[(i * 2) + 1] = as[i] >> 8; 754 } 755 756 bcopy(eaddr, (char *)&sc->arpcom.ac_enaddr, ETHER_ADDR_LEN); 757 758 printf(", address %s\n", 759 ether_sprintf(sc->arpcom.ac_enaddr)); 760 761 error = vge_allocmem(sc); 762 763 if (error) 764 return; 765 766 ifp = &sc->arpcom.ac_if; 767 ifp->if_softc = sc; 768 ifp->if_flags = IFF_BROADCAST | IFF_SIMPLEX | IFF_MULTICAST; 769 ifp->if_ioctl = vge_ioctl; 770 ifp->if_start = vge_start; 771 ifp->if_watchdog = vge_watchdog; 772 ifp->if_init = vge_init; 773 ifp->if_baudrate = 1000000000; 774 #ifdef VGE_JUMBO 775 ifp->if_hardmtu = VGE_JUMBO_MTU; 776 #endif 777 IFQ_SET_MAXLEN(&ifp->if_snd, VGE_IFQ_MAXLEN); 778 IFQ_SET_READY(&ifp->if_snd); 779 780 ifp->if_capabilities = IFCAP_VLAN_MTU | IFCAP_CSUM_IPv4 | 781 IFCAP_CSUM_TCPv4 | IFCAP_CSUM_UDPv4; 782 783 #if NVLAN > 0 784 ifp->if_capabilities |= IFCAP_VLAN_HWTAGGING; 785 #endif 786 787 /* Set interface name */ 788 strlcpy(ifp->if_xname, sc->vge_dev.dv_xname, IFNAMSIZ); 789 790 /* Do MII setup */ 791 sc->sc_mii.mii_ifp = ifp; 792 sc->sc_mii.mii_readreg = vge_miibus_readreg; 793 sc->sc_mii.mii_writereg = vge_miibus_writereg; 794 sc->sc_mii.mii_statchg = vge_miibus_statchg; 795 ifmedia_init(&sc->sc_mii.mii_media, 0, 796 vge_ifmedia_upd, vge_ifmedia_sts); 797 mii_attach(self, &sc->sc_mii, 0xffffffff, MII_PHY_ANY, 798 MII_OFFSET_ANY, 0); 799 if (LIST_FIRST(&sc->sc_mii.mii_phys) == NULL) { 800 printf("%s: no PHY found!\n", sc->vge_dev.dv_xname); 801 ifmedia_add(&sc->sc_mii.mii_media, IFM_ETHER|IFM_MANUAL, 802 0, NULL); 803 ifmedia_set(&sc->sc_mii.mii_media, IFM_ETHER|IFM_MANUAL); 804 } else 805 ifmedia_set(&sc->sc_mii.mii_media, IFM_ETHER|IFM_AUTO); 806 807 timeout_set(&sc->timer_handle, vge_tick, sc); 808 809 /* 810 * Call MI attach routine. 811 */ 812 if_attach(ifp); 813 ether_ifattach(ifp); 814 } 815 816 int 817 vge_newbuf(struct vge_softc *sc, int idx, struct mbuf *m) 818 { 819 struct mbuf *m_new = NULL; 820 struct vge_rx_desc *r; 821 bus_dmamap_t rxmap = sc->vge_ldata.vge_rx_dmamap[idx]; 822 int i; 823 824 if (m == NULL) { 825 /* Allocate a new mbuf */ 826 MGETHDR(m_new, M_DONTWAIT, MT_DATA); 827 if (m_new == NULL) 828 return (ENOBUFS); 829 830 /* Allocate a cluster */ 831 MCLGET(m_new, M_DONTWAIT); 832 if (!(m_new->m_flags & M_EXT)) { 833 m_freem(m_new); 834 return (ENOBUFS); 835 } 836 837 m = m_new; 838 } else 839 m->m_data = m->m_ext.ext_buf; 840 841 m->m_len = m->m_pkthdr.len = MCLBYTES; 842 /* Fix-up alignment so payload is doubleword-aligned */ 843 /* XXX m_adj(m, ETHER_ALIGN); */ 844 845 if (bus_dmamap_load_mbuf(sc->sc_dmat, rxmap, m, BUS_DMA_NOWAIT)) 846 return (ENOBUFS); 847 848 if (rxmap->dm_nsegs > 1) 849 goto out; 850 851 /* Map the segments into RX descriptors */ 852 r = &sc->vge_ldata.vge_rx_list[idx]; 853 854 if (letoh32(r->vge_sts) & VGE_RDSTS_OWN) { 855 printf("%s: tried to map a busy RX descriptor\n", 856 sc->vge_dev.dv_xname); 857 goto out; 858 } 859 r->vge_buflen = htole16(VGE_BUFLEN(rxmap->dm_segs[0].ds_len) | VGE_RXDESC_I); 860 r->vge_addrlo = htole32(VGE_ADDR_LO(rxmap->dm_segs[0].ds_addr)); 861 r->vge_addrhi = htole16(VGE_ADDR_HI(rxmap->dm_segs[0].ds_addr) & 0xFFFF); 862 r->vge_sts = htole32(0); 863 r->vge_ctl = htole32(0); 864 865 /* 866 * Note: the manual fails to document the fact that for 867 * proper operation, the driver needs to replenish the RX 868 * DMA ring 4 descriptors at a time (rather than one at a 869 * time, like most chips). We can allocate the new buffers 870 * but we should not set the OWN bits until we're ready 871 * to hand back 4 of them in one shot. 872 */ 873 #define VGE_RXCHUNK 4 874 sc->vge_rx_consumed++; 875 if (sc->vge_rx_consumed == VGE_RXCHUNK) { 876 for (i = idx; i != idx - sc->vge_rx_consumed; i--) 877 sc->vge_ldata.vge_rx_list[i].vge_sts |= 878 htole32(VGE_RDSTS_OWN); 879 sc->vge_rx_consumed = 0; 880 } 881 882 sc->vge_ldata.vge_rx_mbuf[idx] = m; 883 884 bus_dmamap_sync(sc->sc_dmat, rxmap, 0, 885 rxmap->dm_mapsize, BUS_DMASYNC_PREREAD); 886 887 return (0); 888 out: 889 DPRINTF(("vge_newbuf: out of memory\n")); 890 if (m_new != NULL) 891 m_freem(m_new); 892 return (ENOMEM); 893 } 894 895 int 896 vge_tx_list_init(struct vge_softc *sc) 897 { 898 bzero ((char *)sc->vge_ldata.vge_tx_list, VGE_TX_LIST_SZ); 899 bzero ((char *)&sc->vge_ldata.vge_tx_mbuf, 900 (VGE_TX_DESC_CNT * sizeof(struct mbuf *))); 901 902 bus_dmamap_sync(sc->sc_dmat, 903 sc->vge_ldata.vge_tx_list_map, 0, 904 sc->vge_ldata.vge_tx_list_map->dm_mapsize, 905 BUS_DMASYNC_PREWRITE); 906 sc->vge_ldata.vge_tx_prodidx = 0; 907 sc->vge_ldata.vge_tx_considx = 0; 908 sc->vge_ldata.vge_tx_free = VGE_TX_DESC_CNT; 909 910 return (0); 911 } 912 913 /* Init RX descriptors and allocate mbufs with vge_newbuf() 914 * A ring is used, and last descriptor points to first. */ 915 int 916 vge_rx_list_init(struct vge_softc *sc) 917 { 918 int i; 919 920 bzero ((char *)sc->vge_ldata.vge_rx_list, VGE_RX_LIST_SZ); 921 bzero ((char *)&sc->vge_ldata.vge_rx_mbuf, 922 (VGE_RX_DESC_CNT * sizeof(struct mbuf *))); 923 924 sc->vge_rx_consumed = 0; 925 926 for (i = 0; i < VGE_RX_DESC_CNT; i++) { 927 if (vge_newbuf(sc, i, NULL) == ENOBUFS) 928 return (ENOBUFS); 929 } 930 931 /* Flush the RX descriptors */ 932 933 bus_dmamap_sync(sc->sc_dmat, 934 sc->vge_ldata.vge_rx_list_map, 935 0, sc->vge_ldata.vge_rx_list_map->dm_mapsize, 936 BUS_DMASYNC_PREWRITE|BUS_DMASYNC_PREREAD); 937 938 sc->vge_ldata.vge_rx_prodidx = 0; 939 sc->vge_rx_consumed = 0; 940 sc->vge_head = sc->vge_tail = NULL; 941 942 return (0); 943 } 944 945 /* 946 * RX handler. We support the reception of jumbo frames that have 947 * been fragmented across multiple 2K mbuf cluster buffers. 948 */ 949 void 950 vge_rxeof(struct vge_softc *sc) 951 { 952 struct mbuf *m; 953 struct ifnet *ifp; 954 int i, total_len; 955 int lim = 0; 956 struct vge_rx_desc *cur_rx; 957 u_int32_t rxstat, rxctl; 958 959 ifp = &sc->arpcom.ac_if; 960 i = sc->vge_ldata.vge_rx_prodidx; 961 962 /* Invalidate the descriptor memory */ 963 964 bus_dmamap_sync(sc->sc_dmat, 965 sc->vge_ldata.vge_rx_list_map, 966 0, sc->vge_ldata.vge_rx_list_map->dm_mapsize, 967 BUS_DMASYNC_POSTREAD); 968 969 while (!VGE_OWN(&sc->vge_ldata.vge_rx_list[i])) { 970 struct mbuf *m0 = NULL; 971 972 cur_rx = &sc->vge_ldata.vge_rx_list[i]; 973 m = sc->vge_ldata.vge_rx_mbuf[i]; 974 total_len = VGE_RXBYTES(cur_rx); 975 rxstat = letoh32(cur_rx->vge_sts); 976 rxctl = letoh32(cur_rx->vge_ctl); 977 978 /* Invalidate the RX mbuf and unload its map */ 979 980 bus_dmamap_sync(sc->sc_dmat, 981 sc->vge_ldata.vge_rx_dmamap[i], 982 0, sc->vge_ldata.vge_rx_dmamap[i]->dm_mapsize, 983 BUS_DMASYNC_POSTWRITE); 984 bus_dmamap_unload(sc->sc_dmat, 985 sc->vge_ldata.vge_rx_dmamap[i]); 986 987 /* 988 * If the 'start of frame' bit is set, this indicates 989 * either the first fragment in a multi-fragment receive, 990 * or an intermediate fragment. Either way, we want to 991 * accumulate the buffers. 992 */ 993 if (rxstat & VGE_RXPKT_SOF) { 994 DPRINTF(("vge_rxeof: SOF\n")); 995 m->m_len = MCLBYTES; 996 if (sc->vge_head == NULL) 997 sc->vge_head = sc->vge_tail = m; 998 else { 999 m->m_flags &= ~M_PKTHDR; 1000 sc->vge_tail->m_next = m; 1001 sc->vge_tail = m; 1002 } 1003 vge_newbuf(sc, i, NULL); 1004 VGE_RX_DESC_INC(i); 1005 continue; 1006 } 1007 1008 /* 1009 * Bad/error frames will have the RXOK bit cleared. 1010 * However, there's one error case we want to allow: 1011 * if a VLAN tagged frame arrives and the chip can't 1012 * match it against the CAM filter, it considers this 1013 * a 'VLAN CAM filter miss' and clears the 'RXOK' bit. 1014 * We don't want to drop the frame though: our VLAN 1015 * filtering is done in software. 1016 */ 1017 if (!(rxstat & VGE_RDSTS_RXOK) && !(rxstat & VGE_RDSTS_VIDM) 1018 && !(rxstat & VGE_RDSTS_CSUMERR)) { 1019 ifp->if_ierrors++; 1020 /* 1021 * If this is part of a multi-fragment packet, 1022 * discard all the pieces. 1023 */ 1024 if (sc->vge_head != NULL) { 1025 m_freem(sc->vge_head); 1026 sc->vge_head = sc->vge_tail = NULL; 1027 } 1028 vge_newbuf(sc, i, m); 1029 VGE_RX_DESC_INC(i); 1030 continue; 1031 } 1032 1033 /* 1034 * If allocating a replacement mbuf fails, 1035 * reload the current one. 1036 */ 1037 1038 if (vge_newbuf(sc, i, NULL) == ENOBUFS) { 1039 if (sc->vge_head != NULL) { 1040 m_freem(sc->vge_head); 1041 sc->vge_head = sc->vge_tail = NULL; 1042 } 1043 1044 m0 = m_devget(mtod(m, char *), 1045 total_len - ETHER_CRC_LEN, ETHER_ALIGN, ifp, NULL); 1046 vge_newbuf(sc, i, m); 1047 if (m0 == NULL) { 1048 ifp->if_ierrors++; 1049 continue; 1050 } 1051 m = m0; 1052 1053 VGE_RX_DESC_INC(i); 1054 continue; 1055 } 1056 1057 VGE_RX_DESC_INC(i); 1058 1059 if (sc->vge_head != NULL) { 1060 m->m_len = total_len % MCLBYTES; 1061 /* 1062 * Special case: if there's 4 bytes or less 1063 * in this buffer, the mbuf can be discarded: 1064 * the last 4 bytes is the CRC, which we don't 1065 * care about anyway. 1066 */ 1067 if (m->m_len <= ETHER_CRC_LEN) { 1068 sc->vge_tail->m_len -= 1069 (ETHER_CRC_LEN - m->m_len); 1070 m_freem(m); 1071 } else { 1072 m->m_len -= ETHER_CRC_LEN; 1073 m->m_flags &= ~M_PKTHDR; 1074 sc->vge_tail->m_next = m; 1075 } 1076 m = sc->vge_head; 1077 sc->vge_head = sc->vge_tail = NULL; 1078 m->m_pkthdr.len = total_len - ETHER_CRC_LEN; 1079 } else 1080 m->m_pkthdr.len = m->m_len = 1081 (total_len - ETHER_CRC_LEN); 1082 1083 #ifdef __STRICT_ALIGNMENT 1084 bcopy(m->m_data, m->m_data + ETHER_ALIGN, 1085 total_len); 1086 m->m_data += ETHER_ALIGN; 1087 #endif 1088 ifp->if_ipackets++; 1089 m->m_pkthdr.rcvif = ifp; 1090 1091 /* Do RX checksumming */ 1092 1093 /* Check IP header checksum */ 1094 if ((rxctl & VGE_RDCTL_IPPKT) && 1095 (rxctl & VGE_RDCTL_IPCSUMOK)) 1096 m->m_pkthdr.csum_flags |= M_IPV4_CSUM_IN_OK; 1097 1098 /* Check TCP/UDP checksum */ 1099 if ((rxctl & (VGE_RDCTL_TCPPKT|VGE_RDCTL_UDPPKT)) && 1100 (rxctl & VGE_RDCTL_PROTOCSUMOK)) 1101 m->m_pkthdr.csum_flags |= M_TCP_CSUM_IN_OK | M_UDP_CSUM_IN_OK; 1102 1103 #if NVLAN > 0 1104 if (rxstat & VGE_RDSTS_VTAG) { 1105 m->m_pkthdr.ether_vtag = swap16(rxctl & VGE_RDCTL_VLANID); 1106 m->m_flags |= M_VLANTAG; 1107 } 1108 #endif 1109 1110 #if NBPFILTER > 0 1111 if (ifp->if_bpf) 1112 bpf_mtap_ether(ifp->if_bpf, m, BPF_DIRECTION_IN); 1113 #endif 1114 ether_input_mbuf(ifp, m); 1115 1116 lim++; 1117 if (lim == VGE_RX_DESC_CNT) 1118 break; 1119 } 1120 1121 /* Flush the RX DMA ring */ 1122 bus_dmamap_sync(sc->sc_dmat, 1123 sc->vge_ldata.vge_rx_list_map, 1124 0, sc->vge_ldata.vge_rx_list_map->dm_mapsize, 1125 BUS_DMASYNC_PREWRITE|BUS_DMASYNC_PREREAD); 1126 1127 sc->vge_ldata.vge_rx_prodidx = i; 1128 CSR_WRITE_2(sc, VGE_RXDESC_RESIDUECNT, lim); 1129 } 1130 1131 void 1132 vge_txeof(struct vge_softc *sc) 1133 { 1134 struct ifnet *ifp; 1135 u_int32_t txstat; 1136 int idx; 1137 1138 ifp = &sc->arpcom.ac_if; 1139 idx = sc->vge_ldata.vge_tx_considx; 1140 1141 /* Invalidate the TX descriptor list */ 1142 1143 bus_dmamap_sync(sc->sc_dmat, 1144 sc->vge_ldata.vge_tx_list_map, 1145 0, sc->vge_ldata.vge_tx_list_map->dm_mapsize, 1146 BUS_DMASYNC_POSTREAD); 1147 1148 /* Transmitted frames can be now free'd from the TX list */ 1149 while (idx != sc->vge_ldata.vge_tx_prodidx) { 1150 txstat = letoh32(sc->vge_ldata.vge_tx_list[idx].vge_sts); 1151 if (txstat & VGE_TDSTS_OWN) 1152 break; 1153 1154 m_freem(sc->vge_ldata.vge_tx_mbuf[idx]); 1155 sc->vge_ldata.vge_tx_mbuf[idx] = NULL; 1156 bus_dmamap_unload(sc->sc_dmat, 1157 sc->vge_ldata.vge_tx_dmamap[idx]); 1158 if (txstat & (VGE_TDSTS_EXCESSCOLL|VGE_TDSTS_COLL)) 1159 ifp->if_collisions++; 1160 if (txstat & VGE_TDSTS_TXERR) 1161 ifp->if_oerrors++; 1162 else 1163 ifp->if_opackets++; 1164 1165 sc->vge_ldata.vge_tx_free++; 1166 VGE_TX_DESC_INC(idx); 1167 } 1168 1169 /* No changes made to the TX ring, so no flush needed */ 1170 1171 if (idx != sc->vge_ldata.vge_tx_considx) { 1172 sc->vge_ldata.vge_tx_considx = idx; 1173 ifp->if_flags &= ~IFF_OACTIVE; 1174 ifp->if_timer = 0; 1175 } 1176 1177 /* 1178 * If not all descriptors have been released reaped yet, 1179 * reload the timer so that we will eventually get another 1180 * interrupt that will cause us to re-enter this routine. 1181 * This is done in case the transmitter has gone idle. 1182 */ 1183 if (sc->vge_ldata.vge_tx_free != VGE_TX_DESC_CNT) 1184 CSR_WRITE_1(sc, VGE_CRS1, VGE_CR1_TIMER0_ENABLE); 1185 } 1186 1187 void 1188 vge_tick(void *xsc) 1189 { 1190 struct vge_softc *sc = xsc; 1191 struct ifnet *ifp = &sc->arpcom.ac_if; 1192 struct mii_data *mii = &sc->sc_mii; 1193 int s; 1194 1195 s = splnet(); 1196 1197 mii_tick(mii); 1198 1199 if (sc->vge_link) { 1200 if (!(mii->mii_media_status & IFM_ACTIVE)) { 1201 sc->vge_link = 0; 1202 ifp->if_link_state = LINK_STATE_DOWN; 1203 if_link_state_change(ifp); 1204 } 1205 } else { 1206 if (mii->mii_media_status & IFM_ACTIVE && 1207 IFM_SUBTYPE(mii->mii_media_active) != IFM_NONE) { 1208 sc->vge_link = 1; 1209 if (mii->mii_media_status & IFM_FDX) 1210 ifp->if_link_state = LINK_STATE_FULL_DUPLEX; 1211 else 1212 ifp->if_link_state = LINK_STATE_HALF_DUPLEX; 1213 if_link_state_change(ifp); 1214 if (!IFQ_IS_EMPTY(&ifp->if_snd)) 1215 vge_start(ifp); 1216 } 1217 } 1218 timeout_add_sec(&sc->timer_handle, 1); 1219 splx(s); 1220 } 1221 1222 int 1223 vge_intr(void *arg) 1224 { 1225 struct vge_softc *sc = arg; 1226 struct ifnet *ifp; 1227 u_int32_t status; 1228 int claimed = 0; 1229 1230 ifp = &sc->arpcom.ac_if; 1231 1232 if (!(ifp->if_flags & IFF_UP)) 1233 return 0; 1234 1235 /* Disable interrupts */ 1236 CSR_WRITE_1(sc, VGE_CRC3, VGE_CR3_INT_GMSK); 1237 1238 for (;;) { 1239 status = CSR_READ_4(sc, VGE_ISR); 1240 DPRINTFN(3, ("vge_intr: status=%#x\n", status)); 1241 1242 /* If the card has gone away the read returns 0xffffffff. */ 1243 if (status == 0xFFFFFFFF) 1244 break; 1245 1246 if (status) { 1247 CSR_WRITE_4(sc, VGE_ISR, status); 1248 } 1249 1250 if ((status & VGE_INTRS) == 0) 1251 break; 1252 1253 claimed = 1; 1254 1255 if (status & (VGE_ISR_RXOK|VGE_ISR_RXOK_HIPRIO)) 1256 vge_rxeof(sc); 1257 1258 if (status & (VGE_ISR_RXOFLOW|VGE_ISR_RXNODESC)) { 1259 DPRINTFN(2, ("vge_intr: RX error, recovering\n")); 1260 vge_rxeof(sc); 1261 CSR_WRITE_1(sc, VGE_RXQCSRS, VGE_RXQCSR_RUN); 1262 CSR_WRITE_1(sc, VGE_RXQCSRS, VGE_RXQCSR_WAK); 1263 } 1264 1265 if (status & (VGE_ISR_TXOK0|VGE_ISR_TIMER0)) 1266 vge_txeof(sc); 1267 1268 if (status & (VGE_ISR_TXDMA_STALL|VGE_ISR_RXDMA_STALL)) { 1269 DPRINTFN(2, ("DMA_STALL\n")); 1270 vge_init(ifp); 1271 } 1272 1273 if (status & VGE_ISR_LINKSTS) { 1274 timeout_del(&sc->timer_handle); 1275 vge_tick(sc); 1276 } 1277 } 1278 1279 /* Re-enable interrupts */ 1280 CSR_WRITE_1(sc, VGE_CRS3, VGE_CR3_INT_GMSK); 1281 1282 if (!IFQ_IS_EMPTY(&ifp->if_snd)) 1283 vge_start(ifp); 1284 1285 return (claimed); 1286 } 1287 1288 /* 1289 * Encapsulate an mbuf chain into the TX ring by combining it w/ 1290 * the descriptors. 1291 */ 1292 int 1293 vge_encap(struct vge_softc *sc, struct mbuf *m_head, int idx) 1294 { 1295 struct ifnet *ifp = &sc->arpcom.ac_if; 1296 bus_dmamap_t txmap; 1297 struct vge_tx_desc *d = NULL; 1298 struct vge_tx_frag *f; 1299 struct mbuf *mnew = NULL; 1300 int error, frag; 1301 u_int32_t vge_flags; 1302 1303 vge_flags = 0; 1304 1305 if (m_head->m_pkthdr.csum_flags & M_IPV4_CSUM_OUT) 1306 vge_flags |= VGE_TDCTL_IPCSUM; 1307 if (m_head->m_pkthdr.csum_flags & M_TCPV4_CSUM_OUT) 1308 vge_flags |= VGE_TDCTL_TCPCSUM; 1309 if (m_head->m_pkthdr.csum_flags & M_UDPV4_CSUM_OUT) 1310 vge_flags |= VGE_TDCTL_UDPCSUM; 1311 1312 txmap = sc->vge_ldata.vge_tx_dmamap[idx]; 1313 repack: 1314 error = bus_dmamap_load_mbuf(sc->sc_dmat, txmap, 1315 m_head, BUS_DMA_NOWAIT); 1316 if (error) { 1317 printf("%s: can't map mbuf (error %d)\n", 1318 sc->vge_dev.dv_xname, error); 1319 return (ENOBUFS); 1320 } 1321 1322 d = &sc->vge_ldata.vge_tx_list[idx]; 1323 /* If owned by chip, fail */ 1324 if (letoh32(d->vge_sts) & VGE_TDSTS_OWN) 1325 return (ENOBUFS); 1326 1327 for (frag = 0; frag < txmap->dm_nsegs; frag++) { 1328 /* Check if we have used all 7 fragments. */ 1329 if (frag == VGE_TX_FRAGS) 1330 break; 1331 f = &d->vge_frag[frag]; 1332 f->vge_buflen = htole16(VGE_BUFLEN(txmap->dm_segs[frag].ds_len)); 1333 f->vge_addrlo = htole32(VGE_ADDR_LO(txmap->dm_segs[frag].ds_addr)); 1334 f->vge_addrhi = htole16(VGE_ADDR_HI(txmap->dm_segs[frag].ds_addr) & 0xFFFF); 1335 } 1336 1337 /* 1338 * We used up all 7 fragments! Now what we have to do is 1339 * copy the data into a mbuf cluster and map that. 1340 */ 1341 if (frag == VGE_TX_FRAGS) { 1342 MGETHDR(mnew, M_DONTWAIT, MT_DATA); 1343 if (mnew == NULL) 1344 return (ENOBUFS); 1345 1346 if (m_head->m_pkthdr.len > MHLEN) { 1347 MCLGET(mnew, M_DONTWAIT); 1348 if (!(mnew->m_flags & M_EXT)) { 1349 m_freem(mnew); 1350 return (ENOBUFS); 1351 } 1352 } 1353 m_copydata(m_head, 0, m_head->m_pkthdr.len, 1354 mtod(mnew, caddr_t)); 1355 mnew->m_pkthdr.len = mnew->m_len = m_head->m_pkthdr.len; 1356 IFQ_DEQUEUE(&ifp->if_snd, m_head); 1357 m_freem(m_head); 1358 m_head = mnew; 1359 goto repack; 1360 } 1361 1362 /* This chip does not do auto-padding */ 1363 if (m_head->m_pkthdr.len < VGE_MIN_FRAMELEN) { 1364 f = &d->vge_frag[frag]; 1365 1366 f->vge_buflen = htole16(VGE_BUFLEN(VGE_MIN_FRAMELEN - 1367 m_head->m_pkthdr.len)); 1368 f->vge_addrlo = htole32(VGE_ADDR_LO(txmap->dm_segs[0].ds_addr)); 1369 f->vge_addrhi = htole16(VGE_ADDR_HI(txmap->dm_segs[0].ds_addr) & 0xFFFF); 1370 m_head->m_pkthdr.len = VGE_MIN_FRAMELEN; 1371 frag++; 1372 } 1373 /* For some reason, we need to tell the card fragment + 1 */ 1374 frag++; 1375 1376 bus_dmamap_sync(sc->sc_dmat, txmap, 0, txmap->dm_mapsize, 1377 BUS_DMASYNC_PREWRITE); 1378 1379 d->vge_sts = htole32(m_head->m_pkthdr.len << 16); 1380 d->vge_ctl = htole32(vge_flags|(frag << 28) | VGE_TD_LS_NORM); 1381 1382 if (m_head->m_pkthdr.len > ETHERMTU + ETHER_HDR_LEN) 1383 d->vge_ctl |= htole32(VGE_TDCTL_JUMBO); 1384 1385 #if NVLAN > 0 1386 /* Set up hardware VLAN tagging. */ 1387 if (m_head->m_flags & M_VLANTAG) { 1388 d->vge_ctl |= htole32(m_head->m_pkthdr.ether_vtag | 1389 VGE_TDCTL_VTAG); 1390 } 1391 #endif 1392 1393 sc->vge_ldata.vge_tx_dmamap[idx] = txmap; 1394 sc->vge_ldata.vge_tx_mbuf[idx] = m_head; 1395 sc->vge_ldata.vge_tx_free--; 1396 sc->vge_ldata.vge_tx_list[idx].vge_sts |= htole32(VGE_TDSTS_OWN); 1397 1398 idx++; 1399 if (mnew == NULL) { 1400 /* if mbuf is coalesced, it is already dequeued */ 1401 IFQ_DEQUEUE(&ifp->if_snd, m_head); 1402 } 1403 return (0); 1404 } 1405 1406 /* 1407 * Main transmit routine. 1408 */ 1409 void 1410 vge_start(struct ifnet *ifp) 1411 { 1412 struct vge_softc *sc; 1413 struct mbuf *m_head = NULL; 1414 int idx, pidx = 0; 1415 1416 sc = ifp->if_softc; 1417 1418 if (!sc->vge_link || ifp->if_flags & IFF_OACTIVE) 1419 return; 1420 1421 if (IFQ_IS_EMPTY(&ifp->if_snd)) 1422 return; 1423 1424 idx = sc->vge_ldata.vge_tx_prodidx; 1425 1426 pidx = idx - 1; 1427 if (pidx < 0) 1428 pidx = VGE_TX_DESC_CNT - 1; 1429 1430 while (sc->vge_ldata.vge_tx_mbuf[idx] == NULL) { 1431 IFQ_POLL(&ifp->if_snd, m_head); 1432 if (m_head == NULL) 1433 break; 1434 1435 /* 1436 * If there's a BPF listener, bounce a copy of this frame 1437 * to him. 1438 */ 1439 #if NBPFILTER > 0 1440 if (ifp->if_bpf) 1441 bpf_mtap_ether(ifp->if_bpf, m_head, BPF_DIRECTION_OUT); 1442 #endif 1443 1444 if (vge_encap(sc, m_head, idx)) { 1445 ifp->if_flags |= IFF_OACTIVE; 1446 break; 1447 } 1448 1449 sc->vge_ldata.vge_tx_list[pidx].vge_frag[0].vge_buflen |= 1450 htole16(VGE_TXDESC_Q); 1451 1452 pidx = idx; 1453 VGE_TX_DESC_INC(idx); 1454 } 1455 1456 if (idx == sc->vge_ldata.vge_tx_prodidx) { 1457 return; 1458 } 1459 1460 /* Flush the TX descriptors */ 1461 1462 bus_dmamap_sync(sc->sc_dmat, 1463 sc->vge_ldata.vge_tx_list_map, 1464 0, sc->vge_ldata.vge_tx_list_map->dm_mapsize, 1465 BUS_DMASYNC_PREWRITE|BUS_DMASYNC_PREREAD); 1466 1467 /* Issue a transmit command. */ 1468 CSR_WRITE_2(sc, VGE_TXQCSRS, VGE_TXQCSR_WAK0); 1469 1470 sc->vge_ldata.vge_tx_prodidx = idx; 1471 1472 /* 1473 * Use the countdown timer for interrupt moderation. 1474 * 'TX done' interrupts are disabled. Instead, we reset the 1475 * countdown timer, which will begin counting until it hits 1476 * the value in the SSTIMER register, and then trigger an 1477 * interrupt. Each time we set the TIMER0_ENABLE bit, the 1478 * the timer count is reloaded. Only when the transmitter 1479 * is idle will the timer hit 0 and an interrupt fire. 1480 */ 1481 CSR_WRITE_1(sc, VGE_CRS1, VGE_CR1_TIMER0_ENABLE); 1482 1483 /* 1484 * Set a timeout in case the chip goes out to lunch. 1485 */ 1486 ifp->if_timer = 5; 1487 } 1488 1489 int 1490 vge_init(struct ifnet *ifp) 1491 { 1492 struct vge_softc *sc = ifp->if_softc; 1493 int i; 1494 1495 /* 1496 * Cancel pending I/O and free all RX/TX buffers. 1497 */ 1498 vge_stop(sc); 1499 vge_reset(sc); 1500 1501 /* Initialize RX descriptors list */ 1502 if (vge_rx_list_init(sc) == ENOBUFS) { 1503 printf("%s: init failed: no memory for RX buffers\n", 1504 sc->vge_dev.dv_xname); 1505 vge_stop(sc); 1506 return (ENOBUFS); 1507 } 1508 /* Initialize TX descriptors */ 1509 if (vge_tx_list_init(sc) == ENOBUFS) { 1510 printf("%s: init failed: no memory for TX buffers\n", 1511 sc->vge_dev.dv_xname); 1512 vge_stop(sc); 1513 return (ENOBUFS); 1514 } 1515 1516 /* Set our station address */ 1517 for (i = 0; i < ETHER_ADDR_LEN; i++) 1518 CSR_WRITE_1(sc, VGE_PAR0 + i, sc->arpcom.ac_enaddr[i]); 1519 1520 /* Set receive FIFO threshold */ 1521 CSR_CLRBIT_1(sc, VGE_RXCFG, VGE_RXCFG_FIFO_THR); 1522 CSR_SETBIT_1(sc, VGE_RXCFG, VGE_RXFIFOTHR_128BYTES); 1523 1524 if (ifp->if_capabilities & IFCAP_VLAN_HWTAGGING) { 1525 /* 1526 * Allow transmission and reception of VLAN tagged 1527 * frames. 1528 */ 1529 CSR_CLRBIT_1(sc, VGE_RXCFG, VGE_RXCFG_VTAGOPT); 1530 CSR_SETBIT_1(sc, VGE_RXCFG, VGE_VTAG_OPT2); 1531 } 1532 1533 /* Set DMA burst length */ 1534 CSR_CLRBIT_1(sc, VGE_DMACFG0, VGE_DMACFG0_BURSTLEN); 1535 CSR_SETBIT_1(sc, VGE_DMACFG0, VGE_DMABURST_128); 1536 1537 CSR_SETBIT_1(sc, VGE_TXCFG, VGE_TXCFG_ARB_PRIO|VGE_TXCFG_NONBLK); 1538 1539 /* Set collision backoff algorithm */ 1540 CSR_CLRBIT_1(sc, VGE_CHIPCFG1, VGE_CHIPCFG1_CRANDOM| 1541 VGE_CHIPCFG1_CAP|VGE_CHIPCFG1_MBA|VGE_CHIPCFG1_BAKOPT); 1542 CSR_SETBIT_1(sc, VGE_CHIPCFG1, VGE_CHIPCFG1_OFSET); 1543 1544 /* Disable LPSEL field in priority resolution */ 1545 CSR_SETBIT_1(sc, VGE_DIAGCTL, VGE_DIAGCTL_LPSEL_DIS); 1546 1547 /* 1548 * Load the addresses of the DMA queues into the chip. 1549 * Note that we only use one transmit queue. 1550 */ 1551 1552 CSR_WRITE_4(sc, VGE_TXDESC_ADDR_LO0, 1553 VGE_ADDR_LO(sc->vge_ldata.vge_tx_listseg.ds_addr)); 1554 CSR_WRITE_2(sc, VGE_TXDESCNUM, VGE_TX_DESC_CNT - 1); 1555 1556 CSR_WRITE_4(sc, VGE_RXDESC_ADDR_LO, 1557 VGE_ADDR_LO(sc->vge_ldata.vge_rx_listseg.ds_addr)); 1558 CSR_WRITE_2(sc, VGE_RXDESCNUM, VGE_RX_DESC_CNT - 1); 1559 CSR_WRITE_2(sc, VGE_RXDESC_RESIDUECNT, VGE_RX_DESC_CNT); 1560 1561 /* Enable and wake up the RX descriptor queue */ 1562 CSR_WRITE_1(sc, VGE_RXQCSRS, VGE_RXQCSR_RUN); 1563 CSR_WRITE_1(sc, VGE_RXQCSRS, VGE_RXQCSR_WAK); 1564 1565 /* Enable the TX descriptor queue */ 1566 CSR_WRITE_2(sc, VGE_TXQCSRS, VGE_TXQCSR_RUN0); 1567 1568 /* Set up the receive filter -- allow large frames for VLANs. */ 1569 CSR_WRITE_1(sc, VGE_RXCTL, VGE_RXCTL_RX_UCAST|VGE_RXCTL_RX_GIANT); 1570 1571 /* If we want promiscuous mode, set the allframes bit. */ 1572 if (ifp->if_flags & IFF_PROMISC) { 1573 CSR_SETBIT_1(sc, VGE_RXCTL, VGE_RXCTL_RX_PROMISC); 1574 } 1575 1576 /* Set capture broadcast bit to capture broadcast frames. */ 1577 if (ifp->if_flags & IFF_BROADCAST) { 1578 CSR_SETBIT_1(sc, VGE_RXCTL, VGE_RXCTL_RX_BCAST); 1579 } 1580 1581 /* Set multicast bit to capture multicast frames. */ 1582 if (ifp->if_flags & IFF_MULTICAST) { 1583 CSR_SETBIT_1(sc, VGE_RXCTL, VGE_RXCTL_RX_MCAST); 1584 } 1585 1586 /* Init the cam filter. */ 1587 vge_cam_clear(sc); 1588 1589 /* Init the multicast filter. */ 1590 vge_setmulti(sc); 1591 1592 /* Enable flow control */ 1593 1594 CSR_WRITE_1(sc, VGE_CRS2, 0x8B); 1595 1596 /* Enable jumbo frame reception (if desired) */ 1597 1598 /* Start the MAC. */ 1599 CSR_WRITE_1(sc, VGE_CRC0, VGE_CR0_STOP); 1600 CSR_WRITE_1(sc, VGE_CRS1, VGE_CR1_NOPOLL); 1601 CSR_WRITE_1(sc, VGE_CRS0, 1602 VGE_CR0_TX_ENABLE|VGE_CR0_RX_ENABLE|VGE_CR0_START); 1603 1604 /* 1605 * Configure one-shot timer for microsecond 1606 * resulution and load it for 500 usecs. 1607 */ 1608 CSR_SETBIT_1(sc, VGE_DIAGCTL, VGE_DIAGCTL_TIMER0_RES); 1609 CSR_WRITE_2(sc, VGE_SSTIMER, 400); 1610 1611 /* 1612 * Configure interrupt moderation for receive. Enable 1613 * the holdoff counter and load it, and set the RX 1614 * suppression count to the number of descriptors we 1615 * want to allow before triggering an interrupt. 1616 * The holdoff timer is in units of 20 usecs. 1617 */ 1618 1619 #ifdef notyet 1620 CSR_WRITE_1(sc, VGE_INTCTL1, VGE_INTCTL_TXINTSUP_DISABLE); 1621 /* Select the interrupt holdoff timer page. */ 1622 CSR_CLRBIT_1(sc, VGE_CAMCTL, VGE_CAMCTL_PAGESEL); 1623 CSR_SETBIT_1(sc, VGE_CAMCTL, VGE_PAGESEL_INTHLDOFF); 1624 CSR_WRITE_1(sc, VGE_INTHOLDOFF, 10); /* ~200 usecs */ 1625 1626 /* Enable use of the holdoff timer. */ 1627 CSR_WRITE_1(sc, VGE_CRS3, VGE_CR3_INT_HOLDOFF); 1628 CSR_WRITE_1(sc, VGE_INTCTL1, VGE_INTCTL_SC_RELOAD); 1629 1630 /* Select the RX suppression threshold page. */ 1631 CSR_CLRBIT_1(sc, VGE_CAMCTL, VGE_CAMCTL_PAGESEL); 1632 CSR_SETBIT_1(sc, VGE_CAMCTL, VGE_PAGESEL_RXSUPPTHR); 1633 CSR_WRITE_1(sc, VGE_RXSUPPTHR, 64); /* interrupt after 64 packets */ 1634 1635 /* Restore the page select bits. */ 1636 CSR_CLRBIT_1(sc, VGE_CAMCTL, VGE_CAMCTL_PAGESEL); 1637 CSR_SETBIT_1(sc, VGE_CAMCTL, VGE_PAGESEL_MAR); 1638 #endif 1639 1640 /* 1641 * Enable interrupts. 1642 */ 1643 CSR_WRITE_4(sc, VGE_IMR, VGE_INTRS); 1644 CSR_WRITE_4(sc, VGE_ISR, 0); 1645 CSR_WRITE_1(sc, VGE_CRS3, VGE_CR3_INT_GMSK); 1646 1647 /* Restore BMCR state */ 1648 mii_mediachg(&sc->sc_mii); 1649 1650 ifp->if_flags |= IFF_RUNNING; 1651 ifp->if_flags &= ~IFF_OACTIVE; 1652 1653 sc->vge_if_flags = 0; 1654 sc->vge_link = 0; 1655 1656 if (!timeout_pending(&sc->timer_handle)) 1657 timeout_add_sec(&sc->timer_handle, 1); 1658 1659 return (0); 1660 } 1661 1662 /* 1663 * Set media options. 1664 */ 1665 int 1666 vge_ifmedia_upd(struct ifnet *ifp) 1667 { 1668 struct vge_softc *sc = ifp->if_softc; 1669 1670 return (mii_mediachg(&sc->sc_mii)); 1671 } 1672 1673 /* 1674 * Report current media status. 1675 */ 1676 void 1677 vge_ifmedia_sts(struct ifnet *ifp, struct ifmediareq *ifmr) 1678 { 1679 struct vge_softc *sc = ifp->if_softc; 1680 1681 mii_pollstat(&sc->sc_mii); 1682 ifmr->ifm_active = sc->sc_mii.mii_media_active; 1683 ifmr->ifm_status = sc->sc_mii.mii_media_status; 1684 } 1685 1686 void 1687 vge_miibus_statchg(struct device *dev) 1688 { 1689 struct vge_softc *sc = (struct vge_softc *)dev; 1690 struct mii_data *mii; 1691 struct ifmedia_entry *ife; 1692 1693 mii = &sc->sc_mii; 1694 ife = mii->mii_media.ifm_cur; 1695 1696 /* 1697 * If the user manually selects a media mode, we need to turn 1698 * on the forced MAC mode bit in the DIAGCTL register. If the 1699 * user happens to choose a full duplex mode, we also need to 1700 * set the 'force full duplex' bit. This applies only to 1701 * 10Mbps and 100Mbps speeds. In autoselect mode, forced MAC 1702 * mode is disabled, and in 1000baseT mode, full duplex is 1703 * always implied, so we turn on the forced mode bit but leave 1704 * the FDX bit cleared. 1705 */ 1706 1707 switch (IFM_SUBTYPE(ife->ifm_media)) { 1708 case IFM_AUTO: 1709 CSR_CLRBIT_1(sc, VGE_DIAGCTL, VGE_DIAGCTL_MACFORCE); 1710 CSR_CLRBIT_1(sc, VGE_DIAGCTL, VGE_DIAGCTL_FDXFORCE); 1711 break; 1712 case IFM_1000_T: 1713 CSR_SETBIT_1(sc, VGE_DIAGCTL, VGE_DIAGCTL_MACFORCE); 1714 CSR_CLRBIT_1(sc, VGE_DIAGCTL, VGE_DIAGCTL_FDXFORCE); 1715 break; 1716 case IFM_100_TX: 1717 case IFM_10_T: 1718 CSR_SETBIT_1(sc, VGE_DIAGCTL, VGE_DIAGCTL_MACFORCE); 1719 if ((ife->ifm_media & IFM_GMASK) == IFM_FDX) { 1720 CSR_SETBIT_1(sc, VGE_DIAGCTL, VGE_DIAGCTL_FDXFORCE); 1721 } else { 1722 CSR_CLRBIT_1(sc, VGE_DIAGCTL, VGE_DIAGCTL_FDXFORCE); 1723 } 1724 break; 1725 default: 1726 printf("%s: unknown media type: %x\n", 1727 sc->vge_dev.dv_xname, IFM_SUBTYPE(ife->ifm_media)); 1728 break; 1729 } 1730 } 1731 1732 int 1733 vge_ioctl(struct ifnet *ifp, u_long command, caddr_t data) 1734 { 1735 struct vge_softc *sc = ifp->if_softc; 1736 struct ifaddr *ifa = (struct ifaddr *) data; 1737 struct ifreq *ifr = (struct ifreq *) data; 1738 int s, error = 0; 1739 1740 s = splnet(); 1741 1742 switch (command) { 1743 case SIOCSIFADDR: 1744 ifp->if_flags |= IFF_UP; 1745 switch (ifa->ifa_addr->sa_family) { 1746 #ifdef INET 1747 case AF_INET: 1748 vge_init(ifp); 1749 arp_ifinit(&sc->arpcom, ifa); 1750 break; 1751 #endif 1752 default: 1753 vge_init(ifp); 1754 break; 1755 } 1756 break; 1757 1758 case SIOCSIFFLAGS: 1759 if (ifp->if_flags & IFF_UP) { 1760 if (ifp->if_flags & IFF_RUNNING && 1761 ifp->if_flags & IFF_PROMISC && 1762 !(sc->vge_if_flags & IFF_PROMISC)) { 1763 CSR_SETBIT_1(sc, VGE_RXCTL, 1764 VGE_RXCTL_RX_PROMISC); 1765 vge_setmulti(sc); 1766 } else if (ifp->if_flags & IFF_RUNNING && 1767 !(ifp->if_flags & IFF_PROMISC) && 1768 sc->vge_if_flags & IFF_PROMISC) { 1769 CSR_CLRBIT_1(sc, VGE_RXCTL, 1770 VGE_RXCTL_RX_PROMISC); 1771 vge_setmulti(sc); 1772 } else 1773 vge_init(ifp); 1774 } else { 1775 if (ifp->if_flags & IFF_RUNNING) 1776 vge_stop(sc); 1777 } 1778 sc->vge_if_flags = ifp->if_flags; 1779 break; 1780 1781 case SIOCGIFMEDIA: 1782 case SIOCSIFMEDIA: 1783 error = ifmedia_ioctl(ifp, ifr, &sc->sc_mii.mii_media, command); 1784 break; 1785 1786 default: 1787 error = ether_ioctl(ifp, &sc->arpcom, command, data); 1788 } 1789 1790 if (error == ENETRESET) { 1791 if (ifp->if_flags & IFF_RUNNING) 1792 vge_setmulti(sc); 1793 error = 0; 1794 } 1795 1796 splx(s); 1797 return (error); 1798 } 1799 1800 void 1801 vge_watchdog(struct ifnet *ifp) 1802 { 1803 struct vge_softc *sc = ifp->if_softc; 1804 int s; 1805 1806 s = splnet(); 1807 printf("%s: watchdog timeout\n", sc->vge_dev.dv_xname); 1808 ifp->if_oerrors++; 1809 1810 vge_txeof(sc); 1811 vge_rxeof(sc); 1812 1813 vge_init(ifp); 1814 1815 splx(s); 1816 } 1817 1818 /* 1819 * Stop the adapter and free any mbufs allocated to the 1820 * RX and TX lists. 1821 */ 1822 void 1823 vge_stop(struct vge_softc *sc) 1824 { 1825 int i; 1826 struct ifnet *ifp; 1827 1828 ifp = &sc->arpcom.ac_if; 1829 ifp->if_timer = 0; 1830 1831 timeout_del(&sc->timer_handle); 1832 1833 ifp->if_flags &= ~(IFF_RUNNING | IFF_OACTIVE); 1834 1835 CSR_WRITE_1(sc, VGE_CRC3, VGE_CR3_INT_GMSK); 1836 CSR_WRITE_1(sc, VGE_CRS0, VGE_CR0_STOP); 1837 CSR_WRITE_4(sc, VGE_ISR, 0xFFFFFFFF); 1838 CSR_WRITE_2(sc, VGE_TXQCSRC, 0xFFFF); 1839 CSR_WRITE_1(sc, VGE_RXQCSRC, 0xFF); 1840 CSR_WRITE_4(sc, VGE_RXDESC_ADDR_LO, 0); 1841 1842 if (sc->vge_head != NULL) { 1843 m_freem(sc->vge_head); 1844 sc->vge_head = sc->vge_tail = NULL; 1845 } 1846 1847 /* Free the TX list buffers. */ 1848 for (i = 0; i < VGE_TX_DESC_CNT; i++) { 1849 if (sc->vge_ldata.vge_tx_mbuf[i] != NULL) { 1850 bus_dmamap_unload(sc->sc_dmat, 1851 sc->vge_ldata.vge_tx_dmamap[i]); 1852 m_freem(sc->vge_ldata.vge_tx_mbuf[i]); 1853 sc->vge_ldata.vge_tx_mbuf[i] = NULL; 1854 } 1855 } 1856 1857 /* Free the RX list buffers. */ 1858 for (i = 0; i < VGE_RX_DESC_CNT; i++) { 1859 if (sc->vge_ldata.vge_rx_mbuf[i] != NULL) { 1860 bus_dmamap_unload(sc->sc_dmat, 1861 sc->vge_ldata.vge_rx_dmamap[i]); 1862 m_freem(sc->vge_ldata.vge_rx_mbuf[i]); 1863 sc->vge_ldata.vge_rx_mbuf[i] = NULL; 1864 } 1865 } 1866 } 1867