1 /* $OpenBSD: if_vge.c,v 1.38 2008/09/10 14:01:23 blambert Exp $ */ 2 /* $FreeBSD: if_vge.c,v 1.3 2004/09/11 22:13:25 wpaul Exp $ */ 3 /* 4 * Copyright (c) 2004 5 * Bill Paul <wpaul@windriver.com>. All rights reserved. 6 * 7 * Redistribution and use in source and binary forms, with or without 8 * modification, are permitted provided that the following conditions 9 * are met: 10 * 1. Redistributions of source code must retain the above copyright 11 * notice, this list of conditions and the following disclaimer. 12 * 2. Redistributions in binary form must reproduce the above copyright 13 * notice, this list of conditions and the following disclaimer in the 14 * documentation and/or other materials provided with the distribution. 15 * 3. All advertising materials mentioning features or use of this software 16 * must display the following acknowledgement: 17 * This product includes software developed by Bill Paul. 18 * 4. Neither the name of the author nor the names of any co-contributors 19 * may be used to endorse or promote products derived from this software 20 * without specific prior written permission. 21 * 22 * THIS SOFTWARE IS PROVIDED BY Bill Paul AND CONTRIBUTORS ``AS IS'' AND 23 * ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE 24 * IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE 25 * ARE DISCLAIMED. IN NO EVENT SHALL Bill Paul OR THE VOICES IN HIS HEAD 26 * BE LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR 27 * CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF 28 * SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS 29 * INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN 30 * CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) 31 * ARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF 32 * THE POSSIBILITY OF SUCH DAMAGE. 33 */ 34 35 /* 36 * VIA Networking Technologies VT612x PCI gigabit ethernet NIC driver. 37 * 38 * Written by Bill Paul <wpaul@windriver.com> 39 * Senior Networking Software Engineer 40 * Wind River Systems 41 * 42 * Ported to OpenBSD by Peter Valchev <pvalchev@openbsd.org> 43 */ 44 45 /* 46 * The VIA Networking VT6122 is a 32bit, 33/66MHz PCI device that 47 * combines a tri-speed ethernet MAC and PHY, with the following 48 * features: 49 * 50 * o Jumbo frame support up to 16K 51 * o Transmit and receive flow control 52 * o IPv4 checksum offload 53 * o VLAN tag insertion and stripping 54 * o TCP large send 55 * o 64-bit multicast hash table filter 56 * o 64 entry CAM filter 57 * o 16K RX FIFO and 48K TX FIFO memory 58 * o Interrupt moderation 59 * 60 * The VT6122 supports up to four transmit DMA queues. The descriptors 61 * in the transmit ring can address up to 7 data fragments; frames which 62 * span more than 7 data buffers must be coalesced, but in general the 63 * BSD TCP/IP stack rarely generates frames more than 2 or 3 fragments 64 * long. The receive descriptors address only a single buffer. 65 * 66 * There are two peculiar design issues with the VT6122. One is that 67 * receive data buffers must be aligned on a 32-bit boundary. This is 68 * not a problem where the VT6122 is used as a LOM device in x86-based 69 * systems, but on architectures that generate unaligned access traps, we 70 * have to do some copying. 71 * 72 * The other issue has to do with the way 64-bit addresses are handled. 73 * The DMA descriptors only allow you to specify 48 bits of addressing 74 * information. The remaining 16 bits are specified using one of the 75 * I/O registers. If you only have a 32-bit system, then this isn't 76 * an issue, but if you have a 64-bit system and more than 4GB of 77 * memory, you must have to make sure your network data buffers reside 78 * in the same 48-bit 'segment.' 79 * 80 * Special thanks to Ryan Fu at VIA Networking for providing documentation 81 * and sample NICs for testing. 82 */ 83 84 #include "bpfilter.h" 85 86 #include <sys/param.h> 87 #include <sys/endian.h> 88 #include <sys/systm.h> 89 #include <sys/sockio.h> 90 #include <sys/mbuf.h> 91 #include <sys/malloc.h> 92 #include <sys/kernel.h> 93 #include <sys/device.h> 94 #include <sys/timeout.h> 95 #include <sys/socket.h> 96 97 #include <net/if.h> 98 #include <net/if_dl.h> 99 #include <net/if_media.h> 100 101 #ifdef INET 102 #include <netinet/in.h> 103 #include <netinet/in_systm.h> 104 #include <netinet/in_var.h> 105 #include <netinet/ip.h> 106 #include <netinet/if_ether.h> 107 #endif 108 109 #if NBPFILTER > 0 110 #include <net/bpf.h> 111 #endif 112 113 #include <dev/mii/mii.h> 114 #include <dev/mii/miivar.h> 115 116 #include <dev/pci/pcireg.h> 117 #include <dev/pci/pcivar.h> 118 #include <dev/pci/pcidevs.h> 119 120 #include <dev/pci/if_vgereg.h> 121 #include <dev/pci/if_vgevar.h> 122 123 int vge_probe (struct device *, void *, void *); 124 void vge_attach (struct device *, struct device *, void *); 125 126 int vge_encap (struct vge_softc *, struct mbuf *, int); 127 128 int vge_allocmem (struct vge_softc *); 129 int vge_newbuf (struct vge_softc *, int, struct mbuf *); 130 int vge_rx_list_init (struct vge_softc *); 131 int vge_tx_list_init (struct vge_softc *); 132 void vge_rxeof (struct vge_softc *); 133 void vge_txeof (struct vge_softc *); 134 int vge_intr (void *); 135 void vge_tick (void *); 136 void vge_start (struct ifnet *); 137 int vge_ioctl (struct ifnet *, u_long, caddr_t); 138 int vge_init (struct ifnet *); 139 void vge_stop (struct vge_softc *); 140 void vge_watchdog (struct ifnet *); 141 int vge_ifmedia_upd (struct ifnet *); 142 void vge_ifmedia_sts (struct ifnet *, struct ifmediareq *); 143 144 #ifdef VGE_EEPROM 145 void vge_eeprom_getword (struct vge_softc *, int, u_int16_t *); 146 #endif 147 void vge_read_eeprom (struct vge_softc *, caddr_t, int, int, int); 148 149 void vge_miipoll_start (struct vge_softc *); 150 void vge_miipoll_stop (struct vge_softc *); 151 int vge_miibus_readreg (struct device *, int, int); 152 void vge_miibus_writereg (struct device *, int, int, int); 153 void vge_miibus_statchg (struct device *); 154 155 void vge_cam_clear (struct vge_softc *); 156 int vge_cam_set (struct vge_softc *, uint8_t *); 157 void vge_setmulti (struct vge_softc *); 158 void vge_reset (struct vge_softc *); 159 160 struct cfattach vge_ca = { 161 sizeof(struct vge_softc), vge_probe, vge_attach 162 }; 163 164 struct cfdriver vge_cd = { 165 0, "vge", DV_IFNET 166 }; 167 168 #define VGE_PCI_LOIO 0x10 169 #define VGE_PCI_LOMEM 0x14 170 171 int vge_debug = 0; 172 #define DPRINTF(x) if (vge_debug) printf x 173 #define DPRINTFN(n, x) if (vge_debug >= (n)) printf x 174 175 const struct pci_matchid vge_devices[] = { 176 { PCI_VENDOR_VIATECH, PCI_PRODUCT_VIATECH_VT612x }, 177 }; 178 179 #ifdef VGE_EEPROM 180 /* 181 * Read a word of data stored in the EEPROM at address 'addr.' 182 */ 183 void 184 vge_eeprom_getword(struct vge_softc *sc, int addr, u_int16_t *dest) 185 { 186 int i; 187 u_int16_t word = 0; 188 189 /* 190 * Enter EEPROM embedded programming mode. In order to 191 * access the EEPROM at all, we first have to set the 192 * EELOAD bit in the CHIPCFG2 register. 193 */ 194 CSR_SETBIT_1(sc, VGE_CHIPCFG2, VGE_CHIPCFG2_EELOAD); 195 CSR_SETBIT_1(sc, VGE_EECSR, VGE_EECSR_EMBP/*|VGE_EECSR_ECS*/); 196 197 /* Select the address of the word we want to read */ 198 CSR_WRITE_1(sc, VGE_EEADDR, addr); 199 200 /* Issue read command */ 201 CSR_SETBIT_1(sc, VGE_EECMD, VGE_EECMD_ERD); 202 203 /* Wait for the done bit to be set. */ 204 for (i = 0; i < VGE_TIMEOUT; i++) { 205 if (CSR_READ_1(sc, VGE_EECMD) & VGE_EECMD_EDONE) 206 break; 207 } 208 209 if (i == VGE_TIMEOUT) { 210 printf("%s: EEPROM read timed out\n", sc->vge_dev.dv_xname); 211 *dest = 0; 212 return; 213 } 214 215 /* Read the result */ 216 word = CSR_READ_2(sc, VGE_EERDDAT); 217 218 /* Turn off EEPROM access mode. */ 219 CSR_CLRBIT_1(sc, VGE_EECSR, VGE_EECSR_EMBP/*|VGE_EECSR_ECS*/); 220 CSR_CLRBIT_1(sc, VGE_CHIPCFG2, VGE_CHIPCFG2_EELOAD); 221 222 *dest = word; 223 } 224 #endif 225 226 /* 227 * Read a sequence of words from the EEPROM. 228 */ 229 void 230 vge_read_eeprom(struct vge_softc *sc, caddr_t dest, int off, int cnt, 231 int swap) 232 { 233 int i; 234 #ifdef VGE_EEPROM 235 u_int16_t word = 0, *ptr; 236 237 for (i = 0; i < cnt; i++) { 238 vge_eeprom_getword(sc, off + i, &word); 239 ptr = (u_int16_t *)(dest + (i * 2)); 240 if (swap) 241 *ptr = ntohs(word); 242 else 243 *ptr = word; 244 } 245 #else 246 for (i = 0; i < ETHER_ADDR_LEN; i++) 247 dest[i] = CSR_READ_1(sc, VGE_PAR0 + i); 248 #endif 249 } 250 251 void 252 vge_miipoll_stop(struct vge_softc *sc) 253 { 254 int i; 255 256 CSR_WRITE_1(sc, VGE_MIICMD, 0); 257 258 for (i = 0; i < VGE_TIMEOUT; i++) { 259 DELAY(1); 260 if (CSR_READ_1(sc, VGE_MIISTS) & VGE_MIISTS_IIDL) 261 break; 262 } 263 264 if (i == VGE_TIMEOUT) 265 printf("%s: failed to idle MII autopoll\n", sc->vge_dev.dv_xname); 266 } 267 268 void 269 vge_miipoll_start(struct vge_softc *sc) 270 { 271 int i; 272 273 /* First, make sure we're idle. */ 274 275 CSR_WRITE_1(sc, VGE_MIICMD, 0); 276 CSR_WRITE_1(sc, VGE_MIIADDR, VGE_MIIADDR_SWMPL); 277 278 for (i = 0; i < VGE_TIMEOUT; i++) { 279 DELAY(1); 280 if (CSR_READ_1(sc, VGE_MIISTS) & VGE_MIISTS_IIDL) 281 break; 282 } 283 284 if (i == VGE_TIMEOUT) { 285 printf("%s: failed to idle MII autopoll\n", sc->vge_dev.dv_xname); 286 return; 287 } 288 289 /* Now enable auto poll mode. */ 290 291 CSR_WRITE_1(sc, VGE_MIICMD, VGE_MIICMD_MAUTO); 292 293 /* And make sure it started. */ 294 295 for (i = 0; i < VGE_TIMEOUT; i++) { 296 DELAY(1); 297 if ((CSR_READ_1(sc, VGE_MIISTS) & VGE_MIISTS_IIDL) == 0) 298 break; 299 } 300 301 if (i == VGE_TIMEOUT) 302 printf("%s: failed to start MII autopoll\n", sc->vge_dev.dv_xname); 303 } 304 305 int 306 vge_miibus_readreg(struct device *dev, int phy, int reg) 307 { 308 struct vge_softc *sc = (struct vge_softc *)dev; 309 int i, s; 310 u_int16_t rval = 0; 311 312 if (phy != (CSR_READ_1(sc, VGE_MIICFG) & 0x1F)) 313 return(0); 314 315 s = splnet(); 316 317 vge_miipoll_stop(sc); 318 319 /* Specify the register we want to read. */ 320 CSR_WRITE_1(sc, VGE_MIIADDR, reg); 321 322 /* Issue read command. */ 323 CSR_SETBIT_1(sc, VGE_MIICMD, VGE_MIICMD_RCMD); 324 325 /* Wait for the read command bit to self-clear. */ 326 for (i = 0; i < VGE_TIMEOUT; i++) { 327 DELAY(1); 328 if ((CSR_READ_1(sc, VGE_MIICMD) & VGE_MIICMD_RCMD) == 0) 329 break; 330 } 331 332 if (i == VGE_TIMEOUT) 333 printf("%s: MII read timed out\n", sc->vge_dev.dv_xname); 334 else 335 rval = CSR_READ_2(sc, VGE_MIIDATA); 336 337 vge_miipoll_start(sc); 338 splx(s); 339 340 return (rval); 341 } 342 343 void 344 vge_miibus_writereg(struct device *dev, int phy, int reg, int data) 345 { 346 struct vge_softc *sc = (struct vge_softc *)dev; 347 int i, s; 348 349 if (phy != (CSR_READ_1(sc, VGE_MIICFG) & 0x1F)) 350 return; 351 352 s = splnet(); 353 vge_miipoll_stop(sc); 354 355 /* Specify the register we want to write. */ 356 CSR_WRITE_1(sc, VGE_MIIADDR, reg); 357 358 /* Specify the data we want to write. */ 359 CSR_WRITE_2(sc, VGE_MIIDATA, data); 360 361 /* Issue write command. */ 362 CSR_SETBIT_1(sc, VGE_MIICMD, VGE_MIICMD_WCMD); 363 364 /* Wait for the write command bit to self-clear. */ 365 for (i = 0; i < VGE_TIMEOUT; i++) { 366 DELAY(1); 367 if ((CSR_READ_1(sc, VGE_MIICMD) & VGE_MIICMD_WCMD) == 0) 368 break; 369 } 370 371 if (i == VGE_TIMEOUT) { 372 printf("%s: MII write timed out\n", sc->vge_dev.dv_xname); 373 } 374 375 vge_miipoll_start(sc); 376 splx(s); 377 } 378 379 void 380 vge_cam_clear(struct vge_softc *sc) 381 { 382 int i; 383 384 /* 385 * Turn off all the mask bits. This tells the chip 386 * that none of the entries in the CAM filter are valid. 387 * desired entries will be enabled as we fill the filter in. 388 */ 389 390 CSR_CLRBIT_1(sc, VGE_CAMCTL, VGE_CAMCTL_PAGESEL); 391 CSR_SETBIT_1(sc, VGE_CAMCTL, VGE_PAGESEL_CAMMASK); 392 CSR_WRITE_1(sc, VGE_CAMADDR, VGE_CAMADDR_ENABLE); 393 for (i = 0; i < 8; i++) 394 CSR_WRITE_1(sc, VGE_CAM0 + i, 0); 395 396 /* Clear the VLAN filter too. */ 397 398 CSR_WRITE_1(sc, VGE_CAMADDR, VGE_CAMADDR_ENABLE|VGE_CAMADDR_AVSEL|0); 399 for (i = 0; i < 8; i++) 400 CSR_WRITE_1(sc, VGE_CAM0 + i, 0); 401 402 CSR_WRITE_1(sc, VGE_CAMADDR, 0); 403 CSR_CLRBIT_1(sc, VGE_CAMCTL, VGE_CAMCTL_PAGESEL); 404 CSR_SETBIT_1(sc, VGE_CAMCTL, VGE_PAGESEL_MAR); 405 406 sc->vge_camidx = 0; 407 } 408 409 int 410 vge_cam_set(struct vge_softc *sc, uint8_t *addr) 411 { 412 int i, error = 0; 413 414 if (sc->vge_camidx == VGE_CAM_MAXADDRS) 415 return(ENOSPC); 416 417 /* Select the CAM data page. */ 418 CSR_CLRBIT_1(sc, VGE_CAMCTL, VGE_CAMCTL_PAGESEL); 419 CSR_SETBIT_1(sc, VGE_CAMCTL, VGE_PAGESEL_CAMDATA); 420 421 /* Set the filter entry we want to update and enable writing. */ 422 CSR_WRITE_1(sc, VGE_CAMADDR, VGE_CAMADDR_ENABLE|sc->vge_camidx); 423 424 /* Write the address to the CAM registers */ 425 for (i = 0; i < ETHER_ADDR_LEN; i++) 426 CSR_WRITE_1(sc, VGE_CAM0 + i, addr[i]); 427 428 /* Issue a write command. */ 429 CSR_SETBIT_1(sc, VGE_CAMCTL, VGE_CAMCTL_WRITE); 430 431 /* Wake for it to clear. */ 432 for (i = 0; i < VGE_TIMEOUT; i++) { 433 DELAY(1); 434 if ((CSR_READ_1(sc, VGE_CAMCTL) & VGE_CAMCTL_WRITE) == 0) 435 break; 436 } 437 438 if (i == VGE_TIMEOUT) { 439 printf("%s: setting CAM filter failed\n", sc->vge_dev.dv_xname); 440 error = EIO; 441 goto fail; 442 } 443 444 /* Select the CAM mask page. */ 445 CSR_CLRBIT_1(sc, VGE_CAMCTL, VGE_CAMCTL_PAGESEL); 446 CSR_SETBIT_1(sc, VGE_CAMCTL, VGE_PAGESEL_CAMMASK); 447 448 /* Set the mask bit that enables this filter. */ 449 CSR_SETBIT_1(sc, VGE_CAM0 + (sc->vge_camidx/8), 450 1<<(sc->vge_camidx & 7)); 451 452 sc->vge_camidx++; 453 454 fail: 455 /* Turn off access to CAM. */ 456 CSR_WRITE_1(sc, VGE_CAMADDR, 0); 457 CSR_CLRBIT_1(sc, VGE_CAMCTL, VGE_CAMCTL_PAGESEL); 458 CSR_SETBIT_1(sc, VGE_CAMCTL, VGE_PAGESEL_MAR); 459 460 return (error); 461 } 462 463 /* 464 * Program the multicast filter. We use the 64-entry CAM filter 465 * for perfect filtering. If there's more than 64 multicast addresses, 466 * we use the hash filter instead. 467 */ 468 void 469 vge_setmulti(struct vge_softc *sc) 470 { 471 struct arpcom *ac = &sc->arpcom; 472 struct ifnet *ifp = &ac->ac_if; 473 struct ether_multi *enm; 474 struct ether_multistep step; 475 int error; 476 u_int32_t h = 0, hashes[2] = { 0, 0 }; 477 478 /* First, zot all the multicast entries. */ 479 vge_cam_clear(sc); 480 CSR_WRITE_4(sc, VGE_MAR0, 0); 481 CSR_WRITE_4(sc, VGE_MAR1, 0); 482 ifp->if_flags &= ~IFF_ALLMULTI; 483 484 /* 485 * If the user wants allmulti or promisc mode, enable reception 486 * of all multicast frames. 487 */ 488 if (ifp->if_flags & IFF_PROMISC) { 489 allmulti: 490 CSR_WRITE_4(sc, VGE_MAR0, 0xFFFFFFFF); 491 CSR_WRITE_4(sc, VGE_MAR1, 0xFFFFFFFF); 492 ifp->if_flags |= IFF_ALLMULTI; 493 return; 494 } 495 496 /* Now program new ones */ 497 ETHER_FIRST_MULTI(step, ac, enm); 498 while (enm != NULL) { 499 if (bcmp(enm->enm_addrlo, enm->enm_addrhi, ETHER_ADDR_LEN)) 500 goto allmulti; 501 502 error = vge_cam_set(sc, enm->enm_addrlo); 503 if (error) 504 break; 505 506 ETHER_NEXT_MULTI(step, enm); 507 } 508 509 /* If there were too many addresses, use the hash filter. */ 510 if (error) { 511 vge_cam_clear(sc); 512 513 ETHER_FIRST_MULTI(step, ac, enm); 514 while (enm != NULL) { 515 h = ether_crc32_be(enm->enm_addrlo, 516 ETHER_ADDR_LEN) >> 26; 517 hashes[h >> 5] |= 1 << (h & 0x1f); 518 519 ETHER_NEXT_MULTI(step, enm); 520 } 521 522 CSR_WRITE_4(sc, VGE_MAR0, hashes[0]); 523 CSR_WRITE_4(sc, VGE_MAR1, hashes[1]); 524 } 525 } 526 527 void 528 vge_reset(struct vge_softc *sc) 529 { 530 int i; 531 532 CSR_WRITE_1(sc, VGE_CRS1, VGE_CR1_SOFTRESET); 533 534 for (i = 0; i < VGE_TIMEOUT; i++) { 535 DELAY(5); 536 if ((CSR_READ_1(sc, VGE_CRS1) & VGE_CR1_SOFTRESET) == 0) 537 break; 538 } 539 540 if (i == VGE_TIMEOUT) { 541 printf("%s: soft reset timed out", sc->vge_dev.dv_xname); 542 CSR_WRITE_1(sc, VGE_CRS3, VGE_CR3_STOP_FORCE); 543 DELAY(2000); 544 } 545 546 DELAY(5000); 547 548 CSR_SETBIT_1(sc, VGE_EECSR, VGE_EECSR_RELOAD); 549 550 for (i = 0; i < VGE_TIMEOUT; i++) { 551 DELAY(5); 552 if ((CSR_READ_1(sc, VGE_EECSR) & VGE_EECSR_RELOAD) == 0) 553 break; 554 } 555 556 if (i == VGE_TIMEOUT) { 557 printf("%s: EEPROM reload timed out\n", sc->vge_dev.dv_xname); 558 return; 559 } 560 561 CSR_CLRBIT_1(sc, VGE_CHIPCFG0, VGE_CHIPCFG0_PACPI); 562 } 563 564 /* 565 * Probe for a VIA gigabit chip. Check the PCI vendor and device 566 * IDs against our list and return a device name if we find a match. 567 */ 568 int 569 vge_probe(struct device *dev, void *match, void *aux) 570 { 571 return (pci_matchbyid((struct pci_attach_args *)aux, vge_devices, 572 sizeof(vge_devices)/sizeof(vge_devices[0]))); 573 } 574 575 /* 576 * Allocate memory for RX/TX rings 577 */ 578 int 579 vge_allocmem(struct vge_softc *sc) 580 { 581 int nseg, rseg; 582 int i, error; 583 584 nseg = 32; 585 586 /* Allocate DMA'able memory for the TX ring */ 587 588 error = bus_dmamap_create(sc->sc_dmat, VGE_TX_LIST_SZ, 1, 589 VGE_TX_LIST_SZ, 0, BUS_DMA_ALLOCNOW, 590 &sc->vge_ldata.vge_tx_list_map); 591 if (error) 592 return (ENOMEM); 593 error = bus_dmamem_alloc(sc->sc_dmat, VGE_TX_LIST_SZ, 594 ETHER_ALIGN, 0, 595 &sc->vge_ldata.vge_tx_listseg, 1, &rseg, BUS_DMA_NOWAIT); 596 if (error) { 597 printf("%s: can't alloc TX list\n", sc->vge_dev.dv_xname); 598 return (ENOMEM); 599 } 600 601 /* Load the map for the TX ring. */ 602 error = bus_dmamem_map(sc->sc_dmat, &sc->vge_ldata.vge_tx_listseg, 603 1, VGE_TX_LIST_SZ, 604 (caddr_t *)&sc->vge_ldata.vge_tx_list, BUS_DMA_NOWAIT); 605 memset(sc->vge_ldata.vge_tx_list, 0, VGE_TX_LIST_SZ); 606 if (error) { 607 printf("%s: can't map TX dma buffers\n", 608 sc->vge_dev.dv_xname); 609 bus_dmamem_free(sc->sc_dmat, &sc->vge_ldata.vge_tx_listseg, rseg); 610 return (ENOMEM); 611 } 612 613 error = bus_dmamap_load(sc->sc_dmat, sc->vge_ldata.vge_tx_list_map, 614 sc->vge_ldata.vge_tx_list, VGE_TX_LIST_SZ, NULL, BUS_DMA_NOWAIT); 615 if (error) { 616 printf("%s: can't load TX dma map\n", sc->vge_dev.dv_xname); 617 bus_dmamap_destroy(sc->sc_dmat, sc->vge_ldata.vge_tx_list_map); 618 bus_dmamem_unmap(sc->sc_dmat, (caddr_t)sc->vge_ldata.vge_tx_list, 619 VGE_TX_LIST_SZ); 620 bus_dmamem_free(sc->sc_dmat, &sc->vge_ldata.vge_tx_listseg, rseg); 621 return (ENOMEM); 622 } 623 624 /* Create DMA maps for TX buffers */ 625 626 for (i = 0; i < VGE_TX_DESC_CNT; i++) { 627 error = bus_dmamap_create(sc->sc_dmat, MCLBYTES * nseg, nseg, 628 MCLBYTES, 0, BUS_DMA_ALLOCNOW, 629 &sc->vge_ldata.vge_tx_dmamap[i]); 630 if (error) { 631 printf("%s: can't create DMA map for TX\n", 632 sc->vge_dev.dv_xname); 633 return (ENOMEM); 634 } 635 } 636 637 /* Allocate DMA'able memory for the RX ring */ 638 639 error = bus_dmamap_create(sc->sc_dmat, VGE_RX_LIST_SZ, 1, 640 VGE_RX_LIST_SZ, 0, BUS_DMA_ALLOCNOW, 641 &sc->vge_ldata.vge_rx_list_map); 642 if (error) 643 return (ENOMEM); 644 error = bus_dmamem_alloc(sc->sc_dmat, VGE_RX_LIST_SZ, VGE_RING_ALIGN, 645 0, &sc->vge_ldata.vge_rx_listseg, 1, &rseg, BUS_DMA_NOWAIT); 646 if (error) { 647 printf("%s: can't alloc RX list\n", sc->vge_dev.dv_xname); 648 return (ENOMEM); 649 } 650 651 /* Load the map for the RX ring. */ 652 653 error = bus_dmamem_map(sc->sc_dmat, &sc->vge_ldata.vge_rx_listseg, 654 1, VGE_RX_LIST_SZ, 655 (caddr_t *)&sc->vge_ldata.vge_rx_list, BUS_DMA_NOWAIT); 656 memset(sc->vge_ldata.vge_rx_list, 0, VGE_RX_LIST_SZ); 657 if (error) { 658 printf("%s: can't map RX dma buffers\n", 659 sc->vge_dev.dv_xname); 660 bus_dmamem_free(sc->sc_dmat, &sc->vge_ldata.vge_rx_listseg, rseg); 661 return (ENOMEM); 662 } 663 error = bus_dmamap_load(sc->sc_dmat, sc->vge_ldata.vge_rx_list_map, 664 sc->vge_ldata.vge_rx_list, VGE_RX_LIST_SZ, NULL, BUS_DMA_NOWAIT); 665 if (error) { 666 printf("%s: can't load RX dma map\n", sc->vge_dev.dv_xname); 667 bus_dmamap_destroy(sc->sc_dmat, sc->vge_ldata.vge_rx_list_map); 668 bus_dmamem_unmap(sc->sc_dmat, (caddr_t)sc->vge_ldata.vge_rx_list, 669 VGE_RX_LIST_SZ); 670 bus_dmamem_free(sc->sc_dmat, &sc->vge_ldata.vge_rx_listseg, rseg); 671 return (ENOMEM); 672 } 673 674 /* Create DMA maps for RX buffers */ 675 676 for (i = 0; i < VGE_RX_DESC_CNT; i++) { 677 error = bus_dmamap_create(sc->sc_dmat, MCLBYTES * nseg, nseg, 678 MCLBYTES, 0, BUS_DMA_ALLOCNOW, 679 &sc->vge_ldata.vge_rx_dmamap[i]); 680 if (error) { 681 printf("%s: can't create DMA map for RX\n", 682 sc->vge_dev.dv_xname); 683 return (ENOMEM); 684 } 685 } 686 687 return (0); 688 } 689 690 /* 691 * Attach the interface. Allocate softc structures, do ifmedia 692 * setup and ethernet/BPF attach. 693 */ 694 void 695 vge_attach(struct device *parent, struct device *self, void *aux) 696 { 697 u_char eaddr[ETHER_ADDR_LEN]; 698 u_int16_t as[3]; 699 struct vge_softc *sc = (struct vge_softc *)self; 700 struct pci_attach_args *pa = aux; 701 pci_chipset_tag_t pc = pa->pa_pc; 702 pci_intr_handle_t ih; 703 const char *intrstr = NULL; 704 struct ifnet *ifp; 705 int error = 0, i; 706 bus_size_t iosize; 707 708 /* 709 * Map control/status registers. 710 */ 711 if (pci_mapreg_map(pa, VGE_PCI_LOMEM, PCI_MAPREG_TYPE_MEM, 0, 712 &sc->vge_btag, &sc->vge_bhandle, NULL, &iosize, 0)) { 713 if (pci_mapreg_map(pa, VGE_PCI_LOIO, PCI_MAPREG_TYPE_IO, 0, 714 &sc->vge_btag, &sc->vge_bhandle, NULL, &iosize, 0)) { 715 printf(": can't map mem or i/o space\n"); 716 return; 717 } 718 } 719 720 /* Allocate interrupt */ 721 if (pci_intr_map(pa, &ih)) { 722 printf(": couldn't map interrupt\n"); 723 return; 724 } 725 intrstr = pci_intr_string(pc, ih); 726 sc->vge_intrhand = pci_intr_establish(pc, ih, IPL_NET, vge_intr, sc, 727 sc->vge_dev.dv_xname); 728 if (sc->vge_intrhand == NULL) { 729 printf(": couldn't establish interrupt"); 730 if (intrstr != NULL) 731 printf(" at %s", intrstr); 732 return; 733 } 734 printf(": %s", intrstr); 735 736 sc->sc_dmat = pa->pa_dmat; 737 738 /* Reset the adapter. */ 739 vge_reset(sc); 740 741 /* 742 * Get station address from the EEPROM. 743 */ 744 vge_read_eeprom(sc, (caddr_t)as, VGE_EE_EADDR, 3, 0); 745 for (i = 0; i < 3; i++) { 746 eaddr[(i * 2) + 0] = as[i] & 0xff; 747 eaddr[(i * 2) + 1] = as[i] >> 8; 748 } 749 750 bcopy(eaddr, (char *)&sc->arpcom.ac_enaddr, ETHER_ADDR_LEN); 751 752 printf(", address %s\n", 753 ether_sprintf(sc->arpcom.ac_enaddr)); 754 755 error = vge_allocmem(sc); 756 757 if (error) 758 return; 759 760 ifp = &sc->arpcom.ac_if; 761 ifp->if_softc = sc; 762 ifp->if_flags = IFF_BROADCAST | IFF_SIMPLEX | IFF_MULTICAST; 763 ifp->if_ioctl = vge_ioctl; 764 ifp->if_start = vge_start; 765 ifp->if_watchdog = vge_watchdog; 766 ifp->if_init = vge_init; 767 ifp->if_baudrate = 1000000000; 768 #ifdef VGE_JUMBO 769 ifp->if_hardmtu = VGE_JUMBO_MTU; 770 #endif 771 IFQ_SET_MAXLEN(&ifp->if_snd, VGE_IFQ_MAXLEN); 772 IFQ_SET_READY(&ifp->if_snd); 773 774 ifp->if_capabilities = IFCAP_VLAN_MTU | IFCAP_CSUM_IPv4 | 775 IFCAP_CSUM_TCPv4 | IFCAP_CSUM_UDPv4; 776 777 /* Set interface name */ 778 strlcpy(ifp->if_xname, sc->vge_dev.dv_xname, IFNAMSIZ); 779 780 /* Do MII setup */ 781 sc->sc_mii.mii_ifp = ifp; 782 sc->sc_mii.mii_readreg = vge_miibus_readreg; 783 sc->sc_mii.mii_writereg = vge_miibus_writereg; 784 sc->sc_mii.mii_statchg = vge_miibus_statchg; 785 ifmedia_init(&sc->sc_mii.mii_media, 0, 786 vge_ifmedia_upd, vge_ifmedia_sts); 787 mii_attach(self, &sc->sc_mii, 0xffffffff, MII_PHY_ANY, 788 MII_OFFSET_ANY, 0); 789 if (LIST_FIRST(&sc->sc_mii.mii_phys) == NULL) { 790 printf("%s: no PHY found!\n", sc->vge_dev.dv_xname); 791 ifmedia_add(&sc->sc_mii.mii_media, IFM_ETHER|IFM_MANUAL, 792 0, NULL); 793 ifmedia_set(&sc->sc_mii.mii_media, IFM_ETHER|IFM_MANUAL); 794 } else 795 ifmedia_set(&sc->sc_mii.mii_media, IFM_ETHER|IFM_AUTO); 796 797 timeout_set(&sc->timer_handle, vge_tick, sc); 798 799 /* 800 * Call MI attach routine. 801 */ 802 if_attach(ifp); 803 ether_ifattach(ifp); 804 } 805 806 int 807 vge_newbuf(struct vge_softc *sc, int idx, struct mbuf *m) 808 { 809 struct mbuf *m_new = NULL; 810 struct vge_rx_desc *r; 811 bus_dmamap_t rxmap = sc->vge_ldata.vge_rx_dmamap[idx]; 812 int i; 813 814 if (m == NULL) { 815 /* Allocate a new mbuf */ 816 MGETHDR(m_new, M_DONTWAIT, MT_DATA); 817 if (m_new == NULL) 818 return (ENOBUFS); 819 820 /* Allocate a cluster */ 821 MCLGET(m_new, M_DONTWAIT); 822 if (!(m_new->m_flags & M_EXT)) { 823 m_freem(m_new); 824 return (ENOBUFS); 825 } 826 827 m = m_new; 828 } else 829 m->m_data = m->m_ext.ext_buf; 830 831 m->m_len = m->m_pkthdr.len = MCLBYTES; 832 /* Fix-up alignment so payload is doubleword-aligned */ 833 /* XXX m_adj(m, ETHER_ALIGN); */ 834 835 if (bus_dmamap_load_mbuf(sc->sc_dmat, rxmap, m, BUS_DMA_NOWAIT)) 836 return (ENOBUFS); 837 838 if (rxmap->dm_nsegs > 1) 839 goto out; 840 841 /* Map the segments into RX descriptors */ 842 r = &sc->vge_ldata.vge_rx_list[idx]; 843 844 if (letoh32(r->vge_sts) & VGE_RDSTS_OWN) { 845 printf("%s: tried to map a busy RX descriptor\n", 846 sc->vge_dev.dv_xname); 847 goto out; 848 } 849 r->vge_buflen = htole16(VGE_BUFLEN(rxmap->dm_segs[0].ds_len) | VGE_RXDESC_I); 850 r->vge_addrlo = htole32(VGE_ADDR_LO(rxmap->dm_segs[0].ds_addr)); 851 r->vge_addrhi = htole16(VGE_ADDR_HI(rxmap->dm_segs[0].ds_addr) & 0xFFFF); 852 r->vge_sts = htole32(0); 853 r->vge_ctl = htole32(0); 854 855 /* 856 * Note: the manual fails to document the fact that for 857 * proper operation, the driver needs to replenish the RX 858 * DMA ring 4 descriptors at a time (rather than one at a 859 * time, like most chips). We can allocate the new buffers 860 * but we should not set the OWN bits until we're ready 861 * to hand back 4 of them in one shot. 862 */ 863 #define VGE_RXCHUNK 4 864 sc->vge_rx_consumed++; 865 if (sc->vge_rx_consumed == VGE_RXCHUNK) { 866 for (i = idx; i != idx - sc->vge_rx_consumed; i--) 867 sc->vge_ldata.vge_rx_list[i].vge_sts |= 868 htole32(VGE_RDSTS_OWN); 869 sc->vge_rx_consumed = 0; 870 } 871 872 sc->vge_ldata.vge_rx_mbuf[idx] = m; 873 874 bus_dmamap_sync(sc->sc_dmat, rxmap, 0, 875 rxmap->dm_mapsize, BUS_DMASYNC_PREREAD); 876 877 return (0); 878 out: 879 DPRINTF(("vge_newbuf: out of memory\n")); 880 if (m_new != NULL) 881 m_freem(m_new); 882 return (ENOMEM); 883 } 884 885 int 886 vge_tx_list_init(struct vge_softc *sc) 887 { 888 bzero ((char *)sc->vge_ldata.vge_tx_list, VGE_TX_LIST_SZ); 889 bzero ((char *)&sc->vge_ldata.vge_tx_mbuf, 890 (VGE_TX_DESC_CNT * sizeof(struct mbuf *))); 891 892 bus_dmamap_sync(sc->sc_dmat, 893 sc->vge_ldata.vge_tx_list_map, 0, 894 sc->vge_ldata.vge_tx_list_map->dm_mapsize, 895 BUS_DMASYNC_PREWRITE); 896 sc->vge_ldata.vge_tx_prodidx = 0; 897 sc->vge_ldata.vge_tx_considx = 0; 898 sc->vge_ldata.vge_tx_free = VGE_TX_DESC_CNT; 899 900 return (0); 901 } 902 903 /* Init RX descriptors and allocate mbufs with vge_newbuf() 904 * A ring is used, and last descriptor points to first. */ 905 int 906 vge_rx_list_init(struct vge_softc *sc) 907 { 908 int i; 909 910 bzero ((char *)sc->vge_ldata.vge_rx_list, VGE_RX_LIST_SZ); 911 bzero ((char *)&sc->vge_ldata.vge_rx_mbuf, 912 (VGE_RX_DESC_CNT * sizeof(struct mbuf *))); 913 914 sc->vge_rx_consumed = 0; 915 916 for (i = 0; i < VGE_RX_DESC_CNT; i++) { 917 if (vge_newbuf(sc, i, NULL) == ENOBUFS) 918 return (ENOBUFS); 919 } 920 921 /* Flush the RX descriptors */ 922 923 bus_dmamap_sync(sc->sc_dmat, 924 sc->vge_ldata.vge_rx_list_map, 925 0, sc->vge_ldata.vge_rx_list_map->dm_mapsize, 926 BUS_DMASYNC_PREWRITE|BUS_DMASYNC_PREREAD); 927 928 sc->vge_ldata.vge_rx_prodidx = 0; 929 sc->vge_rx_consumed = 0; 930 sc->vge_head = sc->vge_tail = NULL; 931 932 return (0); 933 } 934 935 /* 936 * RX handler. We support the reception of jumbo frames that have 937 * been fragmented across multiple 2K mbuf cluster buffers. 938 */ 939 void 940 vge_rxeof(struct vge_softc *sc) 941 { 942 struct mbuf *m; 943 struct ifnet *ifp; 944 int i, total_len; 945 int lim = 0; 946 struct vge_rx_desc *cur_rx; 947 u_int32_t rxstat, rxctl; 948 949 ifp = &sc->arpcom.ac_if; 950 i = sc->vge_ldata.vge_rx_prodidx; 951 952 /* Invalidate the descriptor memory */ 953 954 bus_dmamap_sync(sc->sc_dmat, 955 sc->vge_ldata.vge_rx_list_map, 956 0, sc->vge_ldata.vge_rx_list_map->dm_mapsize, 957 BUS_DMASYNC_POSTREAD); 958 959 while (!VGE_OWN(&sc->vge_ldata.vge_rx_list[i])) { 960 struct mbuf *m0 = NULL; 961 962 cur_rx = &sc->vge_ldata.vge_rx_list[i]; 963 m = sc->vge_ldata.vge_rx_mbuf[i]; 964 total_len = VGE_RXBYTES(cur_rx); 965 rxstat = letoh32(cur_rx->vge_sts); 966 rxctl = letoh32(cur_rx->vge_ctl); 967 968 /* Invalidate the RX mbuf and unload its map */ 969 970 bus_dmamap_sync(sc->sc_dmat, 971 sc->vge_ldata.vge_rx_dmamap[i], 972 0, sc->vge_ldata.vge_rx_dmamap[i]->dm_mapsize, 973 BUS_DMASYNC_POSTWRITE); 974 bus_dmamap_unload(sc->sc_dmat, 975 sc->vge_ldata.vge_rx_dmamap[i]); 976 977 /* 978 * If the 'start of frame' bit is set, this indicates 979 * either the first fragment in a multi-fragment receive, 980 * or an intermediate fragment. Either way, we want to 981 * accumulate the buffers. 982 */ 983 if (rxstat & VGE_RXPKT_SOF) { 984 DPRINTF(("vge_rxeof: SOF\n")); 985 m->m_len = MCLBYTES; 986 if (sc->vge_head == NULL) 987 sc->vge_head = sc->vge_tail = m; 988 else { 989 m->m_flags &= ~M_PKTHDR; 990 sc->vge_tail->m_next = m; 991 sc->vge_tail = m; 992 } 993 vge_newbuf(sc, i, NULL); 994 VGE_RX_DESC_INC(i); 995 continue; 996 } 997 998 /* 999 * Bad/error frames will have the RXOK bit cleared. 1000 * However, there's one error case we want to allow: 1001 * if a VLAN tagged frame arrives and the chip can't 1002 * match it against the CAM filter, it considers this 1003 * a 'VLAN CAM filter miss' and clears the 'RXOK' bit. 1004 * We don't want to drop the frame though: our VLAN 1005 * filtering is done in software. 1006 */ 1007 if (!(rxstat & VGE_RDSTS_RXOK) && !(rxstat & VGE_RDSTS_VIDM) 1008 && !(rxstat & VGE_RDSTS_CSUMERR)) { 1009 ifp->if_ierrors++; 1010 /* 1011 * If this is part of a multi-fragment packet, 1012 * discard all the pieces. 1013 */ 1014 if (sc->vge_head != NULL) { 1015 m_freem(sc->vge_head); 1016 sc->vge_head = sc->vge_tail = NULL; 1017 } 1018 vge_newbuf(sc, i, m); 1019 VGE_RX_DESC_INC(i); 1020 continue; 1021 } 1022 1023 /* 1024 * If allocating a replacement mbuf fails, 1025 * reload the current one. 1026 */ 1027 1028 if (vge_newbuf(sc, i, NULL) == ENOBUFS) { 1029 if (sc->vge_head != NULL) { 1030 m_freem(sc->vge_head); 1031 sc->vge_head = sc->vge_tail = NULL; 1032 } 1033 1034 m0 = m_devget(mtod(m, char *) - ETHER_ALIGN, 1035 total_len - ETHER_CRC_LEN + ETHER_ALIGN, 1036 0, ifp, NULL); 1037 vge_newbuf(sc, i, m); 1038 if (m0 == NULL) { 1039 ifp->if_ierrors++; 1040 continue; 1041 } 1042 m_adj(m0, ETHER_ALIGN); 1043 m = m0; 1044 1045 VGE_RX_DESC_INC(i); 1046 continue; 1047 } 1048 1049 VGE_RX_DESC_INC(i); 1050 1051 if (sc->vge_head != NULL) { 1052 m->m_len = total_len % MCLBYTES; 1053 /* 1054 * Special case: if there's 4 bytes or less 1055 * in this buffer, the mbuf can be discarded: 1056 * the last 4 bytes is the CRC, which we don't 1057 * care about anyway. 1058 */ 1059 if (m->m_len <= ETHER_CRC_LEN) { 1060 sc->vge_tail->m_len -= 1061 (ETHER_CRC_LEN - m->m_len); 1062 m_freem(m); 1063 } else { 1064 m->m_len -= ETHER_CRC_LEN; 1065 m->m_flags &= ~M_PKTHDR; 1066 sc->vge_tail->m_next = m; 1067 } 1068 m = sc->vge_head; 1069 sc->vge_head = sc->vge_tail = NULL; 1070 m->m_pkthdr.len = total_len - ETHER_CRC_LEN; 1071 } else 1072 m->m_pkthdr.len = m->m_len = 1073 (total_len - ETHER_CRC_LEN); 1074 1075 #ifdef __STRICT_ALIGNMENT 1076 bcopy(m->m_data, m->m_data + ETHER_ALIGN, 1077 total_len); 1078 m->m_data += ETHER_ALIGN; 1079 #endif 1080 ifp->if_ipackets++; 1081 m->m_pkthdr.rcvif = ifp; 1082 1083 /* Do RX checksumming */ 1084 1085 /* Check IP header checksum */ 1086 if ((rxctl & VGE_RDCTL_IPPKT) && 1087 (rxctl & VGE_RDCTL_IPCSUMOK)) 1088 m->m_pkthdr.csum_flags |= M_IPV4_CSUM_IN_OK; 1089 1090 /* Check TCP/UDP checksum */ 1091 if ((rxctl & (VGE_RDCTL_TCPPKT|VGE_RDCTL_UDPPKT)) && 1092 (rxctl & VGE_RDCTL_PROTOCSUMOK)) 1093 m->m_pkthdr.csum_flags |= M_TCP_CSUM_IN_OK | M_UDP_CSUM_IN_OK; 1094 1095 #if NBPFILTER > 0 1096 if (ifp->if_bpf) 1097 bpf_mtap(ifp->if_bpf, m, BPF_DIRECTION_IN); 1098 #endif 1099 ether_input_mbuf(ifp, m); 1100 1101 lim++; 1102 if (lim == VGE_RX_DESC_CNT) 1103 break; 1104 } 1105 1106 /* Flush the RX DMA ring */ 1107 bus_dmamap_sync(sc->sc_dmat, 1108 sc->vge_ldata.vge_rx_list_map, 1109 0, sc->vge_ldata.vge_rx_list_map->dm_mapsize, 1110 BUS_DMASYNC_PREWRITE|BUS_DMASYNC_PREREAD); 1111 1112 sc->vge_ldata.vge_rx_prodidx = i; 1113 CSR_WRITE_2(sc, VGE_RXDESC_RESIDUECNT, lim); 1114 } 1115 1116 void 1117 vge_txeof(struct vge_softc *sc) 1118 { 1119 struct ifnet *ifp; 1120 u_int32_t txstat; 1121 int idx; 1122 1123 ifp = &sc->arpcom.ac_if; 1124 idx = sc->vge_ldata.vge_tx_considx; 1125 1126 /* Invalidate the TX descriptor list */ 1127 1128 bus_dmamap_sync(sc->sc_dmat, 1129 sc->vge_ldata.vge_tx_list_map, 1130 0, sc->vge_ldata.vge_tx_list_map->dm_mapsize, 1131 BUS_DMASYNC_POSTREAD); 1132 1133 /* Transmitted frames can be now free'd from the TX list */ 1134 while (idx != sc->vge_ldata.vge_tx_prodidx) { 1135 txstat = letoh32(sc->vge_ldata.vge_tx_list[idx].vge_sts); 1136 if (txstat & VGE_TDSTS_OWN) 1137 break; 1138 1139 m_freem(sc->vge_ldata.vge_tx_mbuf[idx]); 1140 sc->vge_ldata.vge_tx_mbuf[idx] = NULL; 1141 bus_dmamap_unload(sc->sc_dmat, 1142 sc->vge_ldata.vge_tx_dmamap[idx]); 1143 if (txstat & (VGE_TDSTS_EXCESSCOLL|VGE_TDSTS_COLL)) 1144 ifp->if_collisions++; 1145 if (txstat & VGE_TDSTS_TXERR) 1146 ifp->if_oerrors++; 1147 else 1148 ifp->if_opackets++; 1149 1150 sc->vge_ldata.vge_tx_free++; 1151 VGE_TX_DESC_INC(idx); 1152 } 1153 1154 /* No changes made to the TX ring, so no flush needed */ 1155 1156 if (idx != sc->vge_ldata.vge_tx_considx) { 1157 sc->vge_ldata.vge_tx_considx = idx; 1158 ifp->if_flags &= ~IFF_OACTIVE; 1159 ifp->if_timer = 0; 1160 } 1161 1162 /* 1163 * If not all descriptors have been released reaped yet, 1164 * reload the timer so that we will eventually get another 1165 * interrupt that will cause us to re-enter this routine. 1166 * This is done in case the transmitter has gone idle. 1167 */ 1168 if (sc->vge_ldata.vge_tx_free != VGE_TX_DESC_CNT) 1169 CSR_WRITE_1(sc, VGE_CRS1, VGE_CR1_TIMER0_ENABLE); 1170 } 1171 1172 void 1173 vge_tick(void *xsc) 1174 { 1175 struct vge_softc *sc = xsc; 1176 struct ifnet *ifp = &sc->arpcom.ac_if; 1177 struct mii_data *mii = &sc->sc_mii; 1178 int s; 1179 1180 s = splnet(); 1181 1182 mii_tick(mii); 1183 1184 if (sc->vge_link) { 1185 if (!(mii->mii_media_status & IFM_ACTIVE)) { 1186 sc->vge_link = 0; 1187 ifp->if_link_state = LINK_STATE_DOWN; 1188 if_link_state_change(ifp); 1189 } 1190 } else { 1191 if (mii->mii_media_status & IFM_ACTIVE && 1192 IFM_SUBTYPE(mii->mii_media_active) != IFM_NONE) { 1193 sc->vge_link = 1; 1194 if (mii->mii_media_status & IFM_FDX) 1195 ifp->if_link_state = LINK_STATE_FULL_DUPLEX; 1196 else 1197 ifp->if_link_state = LINK_STATE_HALF_DUPLEX; 1198 if_link_state_change(ifp); 1199 if (!IFQ_IS_EMPTY(&ifp->if_snd)) 1200 vge_start(ifp); 1201 } 1202 } 1203 timeout_add_sec(&sc->timer_handle, 1); 1204 splx(s); 1205 } 1206 1207 int 1208 vge_intr(void *arg) 1209 { 1210 struct vge_softc *sc = arg; 1211 struct ifnet *ifp; 1212 u_int32_t status; 1213 int claimed = 0; 1214 1215 ifp = &sc->arpcom.ac_if; 1216 1217 if (!(ifp->if_flags & IFF_UP)) 1218 return 0; 1219 1220 /* Disable interrupts */ 1221 CSR_WRITE_1(sc, VGE_CRC3, VGE_CR3_INT_GMSK); 1222 1223 for (;;) { 1224 status = CSR_READ_4(sc, VGE_ISR); 1225 DPRINTFN(3, ("vge_intr: status=%#x\n", status)); 1226 1227 /* If the card has gone away the read returns 0xffffffff. */ 1228 if (status == 0xFFFFFFFF) 1229 break; 1230 1231 if (status) { 1232 CSR_WRITE_4(sc, VGE_ISR, status); 1233 } 1234 1235 if ((status & VGE_INTRS) == 0) 1236 break; 1237 1238 claimed = 1; 1239 1240 if (status & (VGE_ISR_RXOK|VGE_ISR_RXOK_HIPRIO)) 1241 vge_rxeof(sc); 1242 1243 if (status & (VGE_ISR_RXOFLOW|VGE_ISR_RXNODESC)) { 1244 DPRINTFN(2, ("vge_intr: RX error, recovering\n")); 1245 vge_rxeof(sc); 1246 CSR_WRITE_1(sc, VGE_RXQCSRS, VGE_RXQCSR_RUN); 1247 CSR_WRITE_1(sc, VGE_RXQCSRS, VGE_RXQCSR_WAK); 1248 } 1249 1250 if (status & (VGE_ISR_TXOK0|VGE_ISR_TIMER0)) 1251 vge_txeof(sc); 1252 1253 if (status & (VGE_ISR_TXDMA_STALL|VGE_ISR_RXDMA_STALL)) { 1254 DPRINTFN(2, ("DMA_STALL\n")); 1255 vge_init(ifp); 1256 } 1257 1258 if (status & VGE_ISR_LINKSTS) { 1259 timeout_del(&sc->timer_handle); 1260 vge_tick(sc); 1261 } 1262 } 1263 1264 /* Re-enable interrupts */ 1265 CSR_WRITE_1(sc, VGE_CRS3, VGE_CR3_INT_GMSK); 1266 1267 if (!IFQ_IS_EMPTY(&ifp->if_snd)) 1268 vge_start(ifp); 1269 1270 return (claimed); 1271 } 1272 1273 /* 1274 * Encapsulate an mbuf chain into the TX ring by combining it w/ 1275 * the descriptors. 1276 */ 1277 int 1278 vge_encap(struct vge_softc *sc, struct mbuf *m_head, int idx) 1279 { 1280 struct ifnet *ifp = &sc->arpcom.ac_if; 1281 bus_dmamap_t txmap; 1282 struct vge_tx_desc *d = NULL; 1283 struct vge_tx_frag *f; 1284 struct mbuf *mnew = NULL; 1285 int error, frag; 1286 u_int32_t vge_flags; 1287 1288 vge_flags = 0; 1289 1290 if (m_head->m_pkthdr.csum_flags & M_IPV4_CSUM_OUT) 1291 vge_flags |= VGE_TDCTL_IPCSUM; 1292 if (m_head->m_pkthdr.csum_flags & M_TCPV4_CSUM_OUT) 1293 vge_flags |= VGE_TDCTL_TCPCSUM; 1294 if (m_head->m_pkthdr.csum_flags & M_UDPV4_CSUM_OUT) 1295 vge_flags |= VGE_TDCTL_UDPCSUM; 1296 1297 txmap = sc->vge_ldata.vge_tx_dmamap[idx]; 1298 repack: 1299 error = bus_dmamap_load_mbuf(sc->sc_dmat, txmap, 1300 m_head, BUS_DMA_NOWAIT); 1301 if (error) { 1302 printf("%s: can't map mbuf (error %d)\n", 1303 sc->vge_dev.dv_xname, error); 1304 return (ENOBUFS); 1305 } 1306 1307 d = &sc->vge_ldata.vge_tx_list[idx]; 1308 /* If owned by chip, fail */ 1309 if (letoh32(d->vge_sts) & VGE_TDSTS_OWN) 1310 return (ENOBUFS); 1311 1312 for (frag = 0; frag < txmap->dm_nsegs; frag++) { 1313 /* Check if we have used all 7 fragments. */ 1314 if (frag == VGE_TX_FRAGS) 1315 break; 1316 f = &d->vge_frag[frag]; 1317 f->vge_buflen = htole16(VGE_BUFLEN(txmap->dm_segs[frag].ds_len)); 1318 f->vge_addrlo = htole32(VGE_ADDR_LO(txmap->dm_segs[frag].ds_addr)); 1319 f->vge_addrhi = htole16(VGE_ADDR_HI(txmap->dm_segs[frag].ds_addr) & 0xFFFF); 1320 } 1321 1322 /* 1323 * We used up all 7 fragments! Now what we have to do is 1324 * copy the data into a mbuf cluster and map that. 1325 */ 1326 if (frag == VGE_TX_FRAGS) { 1327 MGETHDR(mnew, M_DONTWAIT, MT_DATA); 1328 if (mnew == NULL) 1329 return (ENOBUFS); 1330 1331 if (m_head->m_pkthdr.len > MHLEN) { 1332 MCLGET(mnew, M_DONTWAIT); 1333 if (!(mnew->m_flags & M_EXT)) { 1334 m_freem(mnew); 1335 return (ENOBUFS); 1336 } 1337 } 1338 m_copydata(m_head, 0, m_head->m_pkthdr.len, 1339 mtod(mnew, caddr_t)); 1340 mnew->m_pkthdr.len = mnew->m_len = m_head->m_pkthdr.len; 1341 IFQ_DEQUEUE(&ifp->if_snd, m_head); 1342 m_freem(m_head); 1343 m_head = mnew; 1344 goto repack; 1345 } 1346 1347 /* This chip does not do auto-padding */ 1348 if (m_head->m_pkthdr.len < VGE_MIN_FRAMELEN) { 1349 f = &d->vge_frag[frag]; 1350 1351 f->vge_buflen = htole16(VGE_BUFLEN(VGE_MIN_FRAMELEN - 1352 m_head->m_pkthdr.len)); 1353 f->vge_addrlo = htole32(VGE_ADDR_LO(txmap->dm_segs[0].ds_addr)); 1354 f->vge_addrhi = htole16(VGE_ADDR_HI(txmap->dm_segs[0].ds_addr) & 0xFFFF); 1355 m_head->m_pkthdr.len = VGE_MIN_FRAMELEN; 1356 frag++; 1357 } 1358 /* For some reason, we need to tell the card fragment + 1 */ 1359 frag++; 1360 1361 bus_dmamap_sync(sc->sc_dmat, txmap, 0, txmap->dm_mapsize, 1362 BUS_DMASYNC_PREWRITE); 1363 1364 d->vge_sts = htole32(m_head->m_pkthdr.len << 16); 1365 d->vge_ctl = htole32(vge_flags|(frag << 28) | VGE_TD_LS_NORM); 1366 1367 if (m_head->m_pkthdr.len > ETHERMTU + ETHER_HDR_LEN) 1368 d->vge_ctl |= htole32(VGE_TDCTL_JUMBO); 1369 1370 sc->vge_ldata.vge_tx_dmamap[idx] = txmap; 1371 sc->vge_ldata.vge_tx_mbuf[idx] = m_head; 1372 sc->vge_ldata.vge_tx_free--; 1373 sc->vge_ldata.vge_tx_list[idx].vge_sts |= htole32(VGE_TDSTS_OWN); 1374 1375 idx++; 1376 if (mnew == NULL) { 1377 /* if mbuf is coalesced, it is already dequeued */ 1378 IFQ_DEQUEUE(&ifp->if_snd, m_head); 1379 } 1380 return (0); 1381 } 1382 1383 /* 1384 * Main transmit routine. 1385 */ 1386 void 1387 vge_start(struct ifnet *ifp) 1388 { 1389 struct vge_softc *sc; 1390 struct mbuf *m_head = NULL; 1391 int idx, pidx = 0; 1392 1393 sc = ifp->if_softc; 1394 1395 if (!sc->vge_link || ifp->if_flags & IFF_OACTIVE) 1396 return; 1397 1398 if (IFQ_IS_EMPTY(&ifp->if_snd)) 1399 return; 1400 1401 idx = sc->vge_ldata.vge_tx_prodidx; 1402 1403 pidx = idx - 1; 1404 if (pidx < 0) 1405 pidx = VGE_TX_DESC_CNT - 1; 1406 1407 while (sc->vge_ldata.vge_tx_mbuf[idx] == NULL) { 1408 IFQ_POLL(&ifp->if_snd, m_head); 1409 if (m_head == NULL) 1410 break; 1411 1412 /* 1413 * If there's a BPF listener, bounce a copy of this frame 1414 * to him. 1415 */ 1416 #if NBPFILTER > 0 1417 if (ifp->if_bpf) 1418 bpf_mtap(ifp->if_bpf, m_head, BPF_DIRECTION_OUT); 1419 #endif 1420 1421 if (vge_encap(sc, m_head, idx)) { 1422 ifp->if_flags |= IFF_OACTIVE; 1423 break; 1424 } 1425 1426 sc->vge_ldata.vge_tx_list[pidx].vge_frag[0].vge_buflen |= 1427 htole16(VGE_TXDESC_Q); 1428 1429 pidx = idx; 1430 VGE_TX_DESC_INC(idx); 1431 } 1432 1433 if (idx == sc->vge_ldata.vge_tx_prodidx) { 1434 return; 1435 } 1436 1437 /* Flush the TX descriptors */ 1438 1439 bus_dmamap_sync(sc->sc_dmat, 1440 sc->vge_ldata.vge_tx_list_map, 1441 0, sc->vge_ldata.vge_tx_list_map->dm_mapsize, 1442 BUS_DMASYNC_PREWRITE|BUS_DMASYNC_PREREAD); 1443 1444 /* Issue a transmit command. */ 1445 CSR_WRITE_2(sc, VGE_TXQCSRS, VGE_TXQCSR_WAK0); 1446 1447 sc->vge_ldata.vge_tx_prodidx = idx; 1448 1449 /* 1450 * Use the countdown timer for interrupt moderation. 1451 * 'TX done' interrupts are disabled. Instead, we reset the 1452 * countdown timer, which will begin counting until it hits 1453 * the value in the SSTIMER register, and then trigger an 1454 * interrupt. Each time we set the TIMER0_ENABLE bit, the 1455 * the timer count is reloaded. Only when the transmitter 1456 * is idle will the timer hit 0 and an interrupt fire. 1457 */ 1458 CSR_WRITE_1(sc, VGE_CRS1, VGE_CR1_TIMER0_ENABLE); 1459 1460 /* 1461 * Set a timeout in case the chip goes out to lunch. 1462 */ 1463 ifp->if_timer = 5; 1464 } 1465 1466 int 1467 vge_init(struct ifnet *ifp) 1468 { 1469 struct vge_softc *sc = ifp->if_softc; 1470 int i; 1471 1472 /* 1473 * Cancel pending I/O and free all RX/TX buffers. 1474 */ 1475 vge_stop(sc); 1476 vge_reset(sc); 1477 1478 /* Initialize RX descriptors list */ 1479 if (vge_rx_list_init(sc) == ENOBUFS) { 1480 printf("%s: init failed: no memory for RX buffers\n", 1481 sc->vge_dev.dv_xname); 1482 vge_stop(sc); 1483 return (ENOBUFS); 1484 } 1485 /* Initialize TX descriptors */ 1486 if (vge_tx_list_init(sc) == ENOBUFS) { 1487 printf("%s: init failed: no memory for TX buffers\n", 1488 sc->vge_dev.dv_xname); 1489 vge_stop(sc); 1490 return (ENOBUFS); 1491 } 1492 1493 /* Set our station address */ 1494 for (i = 0; i < ETHER_ADDR_LEN; i++) 1495 CSR_WRITE_1(sc, VGE_PAR0 + i, sc->arpcom.ac_enaddr[i]); 1496 1497 /* Set receive FIFO threshold */ 1498 CSR_CLRBIT_1(sc, VGE_RXCFG, VGE_RXCFG_FIFO_THR); 1499 CSR_SETBIT_1(sc, VGE_RXCFG, VGE_RXFIFOTHR_128BYTES); 1500 1501 /* Set DMA burst length */ 1502 CSR_CLRBIT_1(sc, VGE_DMACFG0, VGE_DMACFG0_BURSTLEN); 1503 CSR_SETBIT_1(sc, VGE_DMACFG0, VGE_DMABURST_128); 1504 1505 CSR_SETBIT_1(sc, VGE_TXCFG, VGE_TXCFG_ARB_PRIO|VGE_TXCFG_NONBLK); 1506 1507 /* Set collision backoff algorithm */ 1508 CSR_CLRBIT_1(sc, VGE_CHIPCFG1, VGE_CHIPCFG1_CRANDOM| 1509 VGE_CHIPCFG1_CAP|VGE_CHIPCFG1_MBA|VGE_CHIPCFG1_BAKOPT); 1510 CSR_SETBIT_1(sc, VGE_CHIPCFG1, VGE_CHIPCFG1_OFSET); 1511 1512 /* Disable LPSEL field in priority resolution */ 1513 CSR_SETBIT_1(sc, VGE_DIAGCTL, VGE_DIAGCTL_LPSEL_DIS); 1514 1515 /* 1516 * Load the addresses of the DMA queues into the chip. 1517 * Note that we only use one transmit queue. 1518 */ 1519 1520 CSR_WRITE_4(sc, VGE_TXDESC_ADDR_LO0, 1521 VGE_ADDR_LO(sc->vge_ldata.vge_tx_listseg.ds_addr)); 1522 CSR_WRITE_2(sc, VGE_TXDESCNUM, VGE_TX_DESC_CNT - 1); 1523 1524 CSR_WRITE_4(sc, VGE_RXDESC_ADDR_LO, 1525 VGE_ADDR_LO(sc->vge_ldata.vge_rx_listseg.ds_addr)); 1526 CSR_WRITE_2(sc, VGE_RXDESCNUM, VGE_RX_DESC_CNT - 1); 1527 CSR_WRITE_2(sc, VGE_RXDESC_RESIDUECNT, VGE_RX_DESC_CNT); 1528 1529 /* Enable and wake up the RX descriptor queue */ 1530 CSR_WRITE_1(sc, VGE_RXQCSRS, VGE_RXQCSR_RUN); 1531 CSR_WRITE_1(sc, VGE_RXQCSRS, VGE_RXQCSR_WAK); 1532 1533 /* Enable the TX descriptor queue */ 1534 CSR_WRITE_2(sc, VGE_TXQCSRS, VGE_TXQCSR_RUN0); 1535 1536 /* Set up the receive filter -- allow large frames for VLANs. */ 1537 CSR_WRITE_1(sc, VGE_RXCTL, VGE_RXCTL_RX_UCAST|VGE_RXCTL_RX_GIANT); 1538 1539 /* If we want promiscuous mode, set the allframes bit. */ 1540 if (ifp->if_flags & IFF_PROMISC) { 1541 CSR_SETBIT_1(sc, VGE_RXCTL, VGE_RXCTL_RX_PROMISC); 1542 } 1543 1544 /* Set capture broadcast bit to capture broadcast frames. */ 1545 if (ifp->if_flags & IFF_BROADCAST) { 1546 CSR_SETBIT_1(sc, VGE_RXCTL, VGE_RXCTL_RX_BCAST); 1547 } 1548 1549 /* Set multicast bit to capture multicast frames. */ 1550 if (ifp->if_flags & IFF_MULTICAST) { 1551 CSR_SETBIT_1(sc, VGE_RXCTL, VGE_RXCTL_RX_MCAST); 1552 } 1553 1554 /* Init the cam filter. */ 1555 vge_cam_clear(sc); 1556 1557 /* Init the multicast filter. */ 1558 vge_setmulti(sc); 1559 1560 /* Enable flow control */ 1561 1562 CSR_WRITE_1(sc, VGE_CRS2, 0x8B); 1563 1564 /* Enable jumbo frame reception (if desired) */ 1565 1566 /* Start the MAC. */ 1567 CSR_WRITE_1(sc, VGE_CRC0, VGE_CR0_STOP); 1568 CSR_WRITE_1(sc, VGE_CRS1, VGE_CR1_NOPOLL); 1569 CSR_WRITE_1(sc, VGE_CRS0, 1570 VGE_CR0_TX_ENABLE|VGE_CR0_RX_ENABLE|VGE_CR0_START); 1571 1572 /* 1573 * Configure one-shot timer for microsecond 1574 * resulution and load it for 500 usecs. 1575 */ 1576 CSR_SETBIT_1(sc, VGE_DIAGCTL, VGE_DIAGCTL_TIMER0_RES); 1577 CSR_WRITE_2(sc, VGE_SSTIMER, 400); 1578 1579 /* 1580 * Configure interrupt moderation for receive. Enable 1581 * the holdoff counter and load it, and set the RX 1582 * suppression count to the number of descriptors we 1583 * want to allow before triggering an interrupt. 1584 * The holdoff timer is in units of 20 usecs. 1585 */ 1586 1587 #ifdef notyet 1588 CSR_WRITE_1(sc, VGE_INTCTL1, VGE_INTCTL_TXINTSUP_DISABLE); 1589 /* Select the interrupt holdoff timer page. */ 1590 CSR_CLRBIT_1(sc, VGE_CAMCTL, VGE_CAMCTL_PAGESEL); 1591 CSR_SETBIT_1(sc, VGE_CAMCTL, VGE_PAGESEL_INTHLDOFF); 1592 CSR_WRITE_1(sc, VGE_INTHOLDOFF, 10); /* ~200 usecs */ 1593 1594 /* Enable use of the holdoff timer. */ 1595 CSR_WRITE_1(sc, VGE_CRS3, VGE_CR3_INT_HOLDOFF); 1596 CSR_WRITE_1(sc, VGE_INTCTL1, VGE_INTCTL_SC_RELOAD); 1597 1598 /* Select the RX suppression threshold page. */ 1599 CSR_CLRBIT_1(sc, VGE_CAMCTL, VGE_CAMCTL_PAGESEL); 1600 CSR_SETBIT_1(sc, VGE_CAMCTL, VGE_PAGESEL_RXSUPPTHR); 1601 CSR_WRITE_1(sc, VGE_RXSUPPTHR, 64); /* interrupt after 64 packets */ 1602 1603 /* Restore the page select bits. */ 1604 CSR_CLRBIT_1(sc, VGE_CAMCTL, VGE_CAMCTL_PAGESEL); 1605 CSR_SETBIT_1(sc, VGE_CAMCTL, VGE_PAGESEL_MAR); 1606 #endif 1607 1608 /* 1609 * Enable interrupts. 1610 */ 1611 CSR_WRITE_4(sc, VGE_IMR, VGE_INTRS); 1612 CSR_WRITE_4(sc, VGE_ISR, 0); 1613 CSR_WRITE_1(sc, VGE_CRS3, VGE_CR3_INT_GMSK); 1614 1615 /* Restore BMCR state */ 1616 mii_mediachg(&sc->sc_mii); 1617 1618 ifp->if_flags |= IFF_RUNNING; 1619 ifp->if_flags &= ~IFF_OACTIVE; 1620 1621 sc->vge_if_flags = 0; 1622 sc->vge_link = 0; 1623 1624 if (!timeout_pending(&sc->timer_handle)) 1625 timeout_add_sec(&sc->timer_handle, 1); 1626 1627 return (0); 1628 } 1629 1630 /* 1631 * Set media options. 1632 */ 1633 int 1634 vge_ifmedia_upd(struct ifnet *ifp) 1635 { 1636 struct vge_softc *sc = ifp->if_softc; 1637 1638 return (mii_mediachg(&sc->sc_mii)); 1639 } 1640 1641 /* 1642 * Report current media status. 1643 */ 1644 void 1645 vge_ifmedia_sts(struct ifnet *ifp, struct ifmediareq *ifmr) 1646 { 1647 struct vge_softc *sc = ifp->if_softc; 1648 1649 mii_pollstat(&sc->sc_mii); 1650 ifmr->ifm_active = sc->sc_mii.mii_media_active; 1651 ifmr->ifm_status = sc->sc_mii.mii_media_status; 1652 } 1653 1654 void 1655 vge_miibus_statchg(struct device *dev) 1656 { 1657 struct vge_softc *sc = (struct vge_softc *)dev; 1658 struct mii_data *mii; 1659 struct ifmedia_entry *ife; 1660 1661 mii = &sc->sc_mii; 1662 ife = mii->mii_media.ifm_cur; 1663 1664 /* 1665 * If the user manually selects a media mode, we need to turn 1666 * on the forced MAC mode bit in the DIAGCTL register. If the 1667 * user happens to choose a full duplex mode, we also need to 1668 * set the 'force full duplex' bit. This applies only to 1669 * 10Mbps and 100Mbps speeds. In autoselect mode, forced MAC 1670 * mode is disabled, and in 1000baseT mode, full duplex is 1671 * always implied, so we turn on the forced mode bit but leave 1672 * the FDX bit cleared. 1673 */ 1674 1675 switch (IFM_SUBTYPE(ife->ifm_media)) { 1676 case IFM_AUTO: 1677 CSR_CLRBIT_1(sc, VGE_DIAGCTL, VGE_DIAGCTL_MACFORCE); 1678 CSR_CLRBIT_1(sc, VGE_DIAGCTL, VGE_DIAGCTL_FDXFORCE); 1679 break; 1680 case IFM_1000_T: 1681 CSR_SETBIT_1(sc, VGE_DIAGCTL, VGE_DIAGCTL_MACFORCE); 1682 CSR_CLRBIT_1(sc, VGE_DIAGCTL, VGE_DIAGCTL_FDXFORCE); 1683 break; 1684 case IFM_100_TX: 1685 case IFM_10_T: 1686 CSR_SETBIT_1(sc, VGE_DIAGCTL, VGE_DIAGCTL_MACFORCE); 1687 if ((ife->ifm_media & IFM_GMASK) == IFM_FDX) { 1688 CSR_SETBIT_1(sc, VGE_DIAGCTL, VGE_DIAGCTL_FDXFORCE); 1689 } else { 1690 CSR_CLRBIT_1(sc, VGE_DIAGCTL, VGE_DIAGCTL_FDXFORCE); 1691 } 1692 break; 1693 default: 1694 printf("%s: unknown media type: %x\n", 1695 sc->vge_dev.dv_xname, IFM_SUBTYPE(ife->ifm_media)); 1696 break; 1697 } 1698 } 1699 1700 int 1701 vge_ioctl(struct ifnet *ifp, u_long command, caddr_t data) 1702 { 1703 struct vge_softc *sc = ifp->if_softc; 1704 struct ifreq *ifr = (struct ifreq *) data; 1705 struct ifaddr *ifa = (struct ifaddr *) data; 1706 int s, error = 0; 1707 1708 s = splnet(); 1709 1710 if ((error = ether_ioctl(ifp, &sc->arpcom, command, data)) > 0) { 1711 splx(s); 1712 return (error); 1713 } 1714 1715 switch (command) { 1716 case SIOCSIFADDR: 1717 ifp->if_flags |= IFF_UP; 1718 switch (ifa->ifa_addr->sa_family) { 1719 #ifdef INET 1720 case AF_INET: 1721 vge_init(ifp); 1722 arp_ifinit(&sc->arpcom, ifa); 1723 break; 1724 #endif 1725 default: 1726 vge_init(ifp); 1727 break; 1728 } 1729 break; 1730 case SIOCSIFMTU: 1731 if (ifr->ifr_mtu < ETHERMIN || ifr->ifr_mtu > ifp->if_hardmtu) 1732 error = EINVAL; 1733 else if (ifp->if_mtu != ifr->ifr_mtu) 1734 ifp->if_mtu = ifr->ifr_mtu; 1735 break; 1736 case SIOCSIFFLAGS: 1737 if (ifp->if_flags & IFF_UP) { 1738 if (ifp->if_flags & IFF_RUNNING && 1739 ifp->if_flags & IFF_PROMISC && 1740 !(sc->vge_if_flags & IFF_PROMISC)) { 1741 CSR_SETBIT_1(sc, VGE_RXCTL, 1742 VGE_RXCTL_RX_PROMISC); 1743 vge_setmulti(sc); 1744 } else if (ifp->if_flags & IFF_RUNNING && 1745 !(ifp->if_flags & IFF_PROMISC) && 1746 sc->vge_if_flags & IFF_PROMISC) { 1747 CSR_CLRBIT_1(sc, VGE_RXCTL, 1748 VGE_RXCTL_RX_PROMISC); 1749 vge_setmulti(sc); 1750 } else 1751 vge_init(ifp); 1752 } else { 1753 if (ifp->if_flags & IFF_RUNNING) 1754 vge_stop(sc); 1755 } 1756 sc->vge_if_flags = ifp->if_flags; 1757 break; 1758 case SIOCADDMULTI: 1759 case SIOCDELMULTI: 1760 error = (command == SIOCADDMULTI) ? 1761 ether_addmulti(ifr, &sc->arpcom) : 1762 ether_delmulti(ifr, &sc->arpcom); 1763 1764 if (error == ENETRESET) { 1765 if (ifp->if_flags & IFF_RUNNING) 1766 vge_setmulti(sc); 1767 error = 0; 1768 } 1769 break; 1770 case SIOCGIFMEDIA: 1771 case SIOCSIFMEDIA: 1772 error = ifmedia_ioctl(ifp, ifr, &sc->sc_mii.mii_media, command); 1773 break; 1774 default: 1775 error = ENOTTY; 1776 break; 1777 } 1778 1779 splx(s); 1780 return (error); 1781 } 1782 1783 void 1784 vge_watchdog(struct ifnet *ifp) 1785 { 1786 struct vge_softc *sc = ifp->if_softc; 1787 int s; 1788 1789 s = splnet(); 1790 printf("%s: watchdog timeout\n", sc->vge_dev.dv_xname); 1791 ifp->if_oerrors++; 1792 1793 vge_txeof(sc); 1794 vge_rxeof(sc); 1795 1796 vge_init(ifp); 1797 1798 splx(s); 1799 } 1800 1801 /* 1802 * Stop the adapter and free any mbufs allocated to the 1803 * RX and TX lists. 1804 */ 1805 void 1806 vge_stop(struct vge_softc *sc) 1807 { 1808 int i; 1809 struct ifnet *ifp; 1810 1811 ifp = &sc->arpcom.ac_if; 1812 ifp->if_timer = 0; 1813 1814 timeout_del(&sc->timer_handle); 1815 1816 ifp->if_flags &= ~(IFF_RUNNING | IFF_OACTIVE); 1817 1818 CSR_WRITE_1(sc, VGE_CRC3, VGE_CR3_INT_GMSK); 1819 CSR_WRITE_1(sc, VGE_CRS0, VGE_CR0_STOP); 1820 CSR_WRITE_4(sc, VGE_ISR, 0xFFFFFFFF); 1821 CSR_WRITE_2(sc, VGE_TXQCSRC, 0xFFFF); 1822 CSR_WRITE_1(sc, VGE_RXQCSRC, 0xFF); 1823 CSR_WRITE_4(sc, VGE_RXDESC_ADDR_LO, 0); 1824 1825 if (sc->vge_head != NULL) { 1826 m_freem(sc->vge_head); 1827 sc->vge_head = sc->vge_tail = NULL; 1828 } 1829 1830 /* Free the TX list buffers. */ 1831 for (i = 0; i < VGE_TX_DESC_CNT; i++) { 1832 if (sc->vge_ldata.vge_tx_mbuf[i] != NULL) { 1833 bus_dmamap_unload(sc->sc_dmat, 1834 sc->vge_ldata.vge_tx_dmamap[i]); 1835 m_freem(sc->vge_ldata.vge_tx_mbuf[i]); 1836 sc->vge_ldata.vge_tx_mbuf[i] = NULL; 1837 } 1838 } 1839 1840 /* Free the RX list buffers. */ 1841 for (i = 0; i < VGE_RX_DESC_CNT; i++) { 1842 if (sc->vge_ldata.vge_rx_mbuf[i] != NULL) { 1843 bus_dmamap_unload(sc->sc_dmat, 1844 sc->vge_ldata.vge_rx_dmamap[i]); 1845 m_freem(sc->vge_ldata.vge_rx_mbuf[i]); 1846 sc->vge_ldata.vge_rx_mbuf[i] = NULL; 1847 } 1848 } 1849 } 1850