1 /* $OpenBSD: if_vge.c,v 1.70 2016/04/13 10:34:32 mpi Exp $ */ 2 /* $FreeBSD: if_vge.c,v 1.3 2004/09/11 22:13:25 wpaul Exp $ */ 3 /* 4 * Copyright (c) 2004 5 * Bill Paul <wpaul@windriver.com>. All rights reserved. 6 * 7 * Redistribution and use in source and binary forms, with or without 8 * modification, are permitted provided that the following conditions 9 * are met: 10 * 1. Redistributions of source code must retain the above copyright 11 * notice, this list of conditions and the following disclaimer. 12 * 2. Redistributions in binary form must reproduce the above copyright 13 * notice, this list of conditions and the following disclaimer in the 14 * documentation and/or other materials provided with the distribution. 15 * 3. All advertising materials mentioning features or use of this software 16 * must display the following acknowledgement: 17 * This product includes software developed by Bill Paul. 18 * 4. Neither the name of the author nor the names of any co-contributors 19 * may be used to endorse or promote products derived from this software 20 * without specific prior written permission. 21 * 22 * THIS SOFTWARE IS PROVIDED BY Bill Paul AND CONTRIBUTORS ``AS IS'' AND 23 * ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE 24 * IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE 25 * ARE DISCLAIMED. IN NO EVENT SHALL Bill Paul OR THE VOICES IN HIS HEAD 26 * BE LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR 27 * CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF 28 * SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS 29 * INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN 30 * CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) 31 * ARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF 32 * THE POSSIBILITY OF SUCH DAMAGE. 33 */ 34 35 /* 36 * VIA Networking Technologies VT612x PCI gigabit ethernet NIC driver. 37 * 38 * Written by Bill Paul <wpaul@windriver.com> 39 * Senior Networking Software Engineer 40 * Wind River Systems 41 * 42 * Ported to OpenBSD by Peter Valchev <pvalchev@openbsd.org> 43 */ 44 45 /* 46 * The VIA Networking VT6122 is a 32bit, 33/66MHz PCI device that 47 * combines a tri-speed ethernet MAC and PHY, with the following 48 * features: 49 * 50 * o Jumbo frame support up to 16K 51 * o Transmit and receive flow control 52 * o IPv4 checksum offload 53 * o VLAN tag insertion and stripping 54 * o TCP large send 55 * o 64-bit multicast hash table filter 56 * o 64 entry CAM filter 57 * o 16K RX FIFO and 48K TX FIFO memory 58 * o Interrupt moderation 59 * 60 * The VT6122 supports up to four transmit DMA queues. The descriptors 61 * in the transmit ring can address up to 7 data fragments; frames which 62 * span more than 7 data buffers must be coalesced, but in general the 63 * BSD TCP/IP stack rarely generates frames more than 2 or 3 fragments 64 * long. The receive descriptors address only a single buffer. 65 * 66 * There are two peculiar design issues with the VT6122. One is that 67 * receive data buffers must be aligned on a 32-bit boundary. This is 68 * not a problem where the VT6122 is used as a LOM device in x86-based 69 * systems, but on architectures that generate unaligned access traps, we 70 * have to do some copying. 71 * 72 * The other issue has to do with the way 64-bit addresses are handled. 73 * The DMA descriptors only allow you to specify 48 bits of addressing 74 * information. The remaining 16 bits are specified using one of the 75 * I/O registers. If you only have a 32-bit system, then this isn't 76 * an issue, but if you have a 64-bit system and more than 4GB of 77 * memory, you must have to make sure your network data buffers reside 78 * in the same 48-bit 'segment.' 79 * 80 * Special thanks to Ryan Fu at VIA Networking for providing documentation 81 * and sample NICs for testing. 82 */ 83 84 #include "bpfilter.h" 85 #include "vlan.h" 86 87 #include <sys/param.h> 88 #include <sys/endian.h> 89 #include <sys/systm.h> 90 #include <sys/sockio.h> 91 #include <sys/mbuf.h> 92 #include <sys/malloc.h> 93 #include <sys/kernel.h> 94 #include <sys/device.h> 95 #include <sys/timeout.h> 96 #include <sys/socket.h> 97 98 #include <net/if.h> 99 #include <net/if_media.h> 100 101 #include <netinet/in.h> 102 #include <netinet/if_ether.h> 103 104 #if NBPFILTER > 0 105 #include <net/bpf.h> 106 #endif 107 108 #include <dev/mii/miivar.h> 109 110 #include <dev/pci/pcireg.h> 111 #include <dev/pci/pcivar.h> 112 #include <dev/pci/pcidevs.h> 113 114 #include <dev/pci/if_vgereg.h> 115 #include <dev/pci/if_vgevar.h> 116 117 int vge_probe (struct device *, void *, void *); 118 void vge_attach (struct device *, struct device *, void *); 119 int vge_detach (struct device *, int); 120 121 int vge_encap (struct vge_softc *, struct mbuf *, int); 122 123 int vge_allocmem (struct vge_softc *); 124 void vge_freemem (struct vge_softc *); 125 int vge_newbuf (struct vge_softc *, int, struct mbuf *); 126 int vge_rx_list_init (struct vge_softc *); 127 int vge_tx_list_init (struct vge_softc *); 128 void vge_rxeof (struct vge_softc *); 129 void vge_txeof (struct vge_softc *); 130 int vge_intr (void *); 131 void vge_tick (void *); 132 void vge_start (struct ifnet *); 133 int vge_ioctl (struct ifnet *, u_long, caddr_t); 134 int vge_init (struct ifnet *); 135 void vge_stop (struct vge_softc *); 136 void vge_watchdog (struct ifnet *); 137 int vge_ifmedia_upd (struct ifnet *); 138 void vge_ifmedia_sts (struct ifnet *, struct ifmediareq *); 139 140 #ifdef VGE_EEPROM 141 void vge_eeprom_getword (struct vge_softc *, int, u_int16_t *); 142 #endif 143 void vge_read_eeprom (struct vge_softc *, caddr_t, int, int, int); 144 145 void vge_miipoll_start (struct vge_softc *); 146 void vge_miipoll_stop (struct vge_softc *); 147 int vge_miibus_readreg (struct device *, int, int); 148 void vge_miibus_writereg (struct device *, int, int, int); 149 void vge_miibus_statchg (struct device *); 150 151 void vge_cam_clear (struct vge_softc *); 152 int vge_cam_set (struct vge_softc *, uint8_t *); 153 void vge_iff (struct vge_softc *); 154 void vge_reset (struct vge_softc *); 155 156 struct cfattach vge_ca = { 157 sizeof(struct vge_softc), vge_probe, vge_attach, vge_detach 158 }; 159 160 struct cfdriver vge_cd = { 161 NULL, "vge", DV_IFNET 162 }; 163 164 #define VGE_PCI_LOIO 0x10 165 #define VGE_PCI_LOMEM 0x14 166 167 int vge_debug = 0; 168 #define DPRINTF(x) if (vge_debug) printf x 169 #define DPRINTFN(n, x) if (vge_debug >= (n)) printf x 170 171 const struct pci_matchid vge_devices[] = { 172 { PCI_VENDOR_VIATECH, PCI_PRODUCT_VIATECH_VT612x }, 173 }; 174 175 #ifdef VGE_EEPROM 176 /* 177 * Read a word of data stored in the EEPROM at address 'addr.' 178 */ 179 void 180 vge_eeprom_getword(struct vge_softc *sc, int addr, u_int16_t *dest) 181 { 182 int i; 183 u_int16_t word = 0; 184 185 /* 186 * Enter EEPROM embedded programming mode. In order to 187 * access the EEPROM at all, we first have to set the 188 * EELOAD bit in the CHIPCFG2 register. 189 */ 190 CSR_SETBIT_1(sc, VGE_CHIPCFG2, VGE_CHIPCFG2_EELOAD); 191 CSR_SETBIT_1(sc, VGE_EECSR, VGE_EECSR_EMBP/*|VGE_EECSR_ECS*/); 192 193 /* Select the address of the word we want to read */ 194 CSR_WRITE_1(sc, VGE_EEADDR, addr); 195 196 /* Issue read command */ 197 CSR_SETBIT_1(sc, VGE_EECMD, VGE_EECMD_ERD); 198 199 /* Wait for the done bit to be set. */ 200 for (i = 0; i < VGE_TIMEOUT; i++) { 201 if (CSR_READ_1(sc, VGE_EECMD) & VGE_EECMD_EDONE) 202 break; 203 } 204 205 if (i == VGE_TIMEOUT) { 206 printf("%s: EEPROM read timed out\n", sc->vge_dev.dv_xname); 207 *dest = 0; 208 return; 209 } 210 211 /* Read the result */ 212 word = CSR_READ_2(sc, VGE_EERDDAT); 213 214 /* Turn off EEPROM access mode. */ 215 CSR_CLRBIT_1(sc, VGE_EECSR, VGE_EECSR_EMBP/*|VGE_EECSR_ECS*/); 216 CSR_CLRBIT_1(sc, VGE_CHIPCFG2, VGE_CHIPCFG2_EELOAD); 217 218 *dest = word; 219 } 220 #endif 221 222 /* 223 * Read a sequence of words from the EEPROM. 224 */ 225 void 226 vge_read_eeprom(struct vge_softc *sc, caddr_t dest, int off, int cnt, 227 int swap) 228 { 229 int i; 230 #ifdef VGE_EEPROM 231 u_int16_t word = 0, *ptr; 232 233 for (i = 0; i < cnt; i++) { 234 vge_eeprom_getword(sc, off + i, &word); 235 ptr = (u_int16_t *)(dest + (i * 2)); 236 if (swap) 237 *ptr = ntohs(word); 238 else 239 *ptr = word; 240 } 241 #else 242 for (i = 0; i < ETHER_ADDR_LEN; i++) 243 dest[i] = CSR_READ_1(sc, VGE_PAR0 + i); 244 #endif 245 } 246 247 void 248 vge_miipoll_stop(struct vge_softc *sc) 249 { 250 int i; 251 252 CSR_WRITE_1(sc, VGE_MIICMD, 0); 253 254 for (i = 0; i < VGE_TIMEOUT; i++) { 255 DELAY(1); 256 if (CSR_READ_1(sc, VGE_MIISTS) & VGE_MIISTS_IIDL) 257 break; 258 } 259 260 if (i == VGE_TIMEOUT) 261 printf("%s: failed to idle MII autopoll\n", sc->vge_dev.dv_xname); 262 } 263 264 void 265 vge_miipoll_start(struct vge_softc *sc) 266 { 267 int i; 268 269 /* First, make sure we're idle. */ 270 271 CSR_WRITE_1(sc, VGE_MIICMD, 0); 272 CSR_WRITE_1(sc, VGE_MIIADDR, VGE_MIIADDR_SWMPL); 273 274 for (i = 0; i < VGE_TIMEOUT; i++) { 275 DELAY(1); 276 if (CSR_READ_1(sc, VGE_MIISTS) & VGE_MIISTS_IIDL) 277 break; 278 } 279 280 if (i == VGE_TIMEOUT) { 281 printf("%s: failed to idle MII autopoll\n", sc->vge_dev.dv_xname); 282 return; 283 } 284 285 /* Now enable auto poll mode. */ 286 287 CSR_WRITE_1(sc, VGE_MIICMD, VGE_MIICMD_MAUTO); 288 289 /* And make sure it started. */ 290 291 for (i = 0; i < VGE_TIMEOUT; i++) { 292 DELAY(1); 293 if ((CSR_READ_1(sc, VGE_MIISTS) & VGE_MIISTS_IIDL) == 0) 294 break; 295 } 296 297 if (i == VGE_TIMEOUT) 298 printf("%s: failed to start MII autopoll\n", sc->vge_dev.dv_xname); 299 } 300 301 int 302 vge_miibus_readreg(struct device *dev, int phy, int reg) 303 { 304 struct vge_softc *sc = (struct vge_softc *)dev; 305 int i, s; 306 u_int16_t rval = 0; 307 308 if (phy != (CSR_READ_1(sc, VGE_MIICFG) & 0x1F)) 309 return(0); 310 311 s = splnet(); 312 313 vge_miipoll_stop(sc); 314 315 /* Specify the register we want to read. */ 316 CSR_WRITE_1(sc, VGE_MIIADDR, reg); 317 318 /* Issue read command. */ 319 CSR_SETBIT_1(sc, VGE_MIICMD, VGE_MIICMD_RCMD); 320 321 /* Wait for the read command bit to self-clear. */ 322 for (i = 0; i < VGE_TIMEOUT; i++) { 323 DELAY(1); 324 if ((CSR_READ_1(sc, VGE_MIICMD) & VGE_MIICMD_RCMD) == 0) 325 break; 326 } 327 328 if (i == VGE_TIMEOUT) 329 printf("%s: MII read timed out\n", sc->vge_dev.dv_xname); 330 else 331 rval = CSR_READ_2(sc, VGE_MIIDATA); 332 333 vge_miipoll_start(sc); 334 splx(s); 335 336 return (rval); 337 } 338 339 void 340 vge_miibus_writereg(struct device *dev, int phy, int reg, int data) 341 { 342 struct vge_softc *sc = (struct vge_softc *)dev; 343 int i, s; 344 345 if (phy != (CSR_READ_1(sc, VGE_MIICFG) & 0x1F)) 346 return; 347 348 s = splnet(); 349 vge_miipoll_stop(sc); 350 351 /* Specify the register we want to write. */ 352 CSR_WRITE_1(sc, VGE_MIIADDR, reg); 353 354 /* Specify the data we want to write. */ 355 CSR_WRITE_2(sc, VGE_MIIDATA, data); 356 357 /* Issue write command. */ 358 CSR_SETBIT_1(sc, VGE_MIICMD, VGE_MIICMD_WCMD); 359 360 /* Wait for the write command bit to self-clear. */ 361 for (i = 0; i < VGE_TIMEOUT; i++) { 362 DELAY(1); 363 if ((CSR_READ_1(sc, VGE_MIICMD) & VGE_MIICMD_WCMD) == 0) 364 break; 365 } 366 367 if (i == VGE_TIMEOUT) { 368 printf("%s: MII write timed out\n", sc->vge_dev.dv_xname); 369 } 370 371 vge_miipoll_start(sc); 372 splx(s); 373 } 374 375 void 376 vge_cam_clear(struct vge_softc *sc) 377 { 378 int i; 379 380 /* 381 * Turn off all the mask bits. This tells the chip 382 * that none of the entries in the CAM filter are valid. 383 * desired entries will be enabled as we fill the filter in. 384 */ 385 386 CSR_CLRBIT_1(sc, VGE_CAMCTL, VGE_CAMCTL_PAGESEL); 387 CSR_SETBIT_1(sc, VGE_CAMCTL, VGE_PAGESEL_CAMMASK); 388 CSR_WRITE_1(sc, VGE_CAMADDR, VGE_CAMADDR_ENABLE); 389 for (i = 0; i < 8; i++) 390 CSR_WRITE_1(sc, VGE_CAM0 + i, 0); 391 392 /* Clear the VLAN filter too. */ 393 394 CSR_WRITE_1(sc, VGE_CAMADDR, VGE_CAMADDR_ENABLE|VGE_CAMADDR_AVSEL|0); 395 for (i = 0; i < 8; i++) 396 CSR_WRITE_1(sc, VGE_CAM0 + i, 0); 397 398 CSR_WRITE_1(sc, VGE_CAMADDR, 0); 399 CSR_CLRBIT_1(sc, VGE_CAMCTL, VGE_CAMCTL_PAGESEL); 400 CSR_SETBIT_1(sc, VGE_CAMCTL, VGE_PAGESEL_MAR); 401 402 sc->vge_camidx = 0; 403 } 404 405 int 406 vge_cam_set(struct vge_softc *sc, uint8_t *addr) 407 { 408 int i, error = 0; 409 410 if (sc->vge_camidx == VGE_CAM_MAXADDRS) 411 return(ENOSPC); 412 413 /* Select the CAM data page. */ 414 CSR_CLRBIT_1(sc, VGE_CAMCTL, VGE_CAMCTL_PAGESEL); 415 CSR_SETBIT_1(sc, VGE_CAMCTL, VGE_PAGESEL_CAMDATA); 416 417 /* Set the filter entry we want to update and enable writing. */ 418 CSR_WRITE_1(sc, VGE_CAMADDR, VGE_CAMADDR_ENABLE|sc->vge_camidx); 419 420 /* Write the address to the CAM registers */ 421 for (i = 0; i < ETHER_ADDR_LEN; i++) 422 CSR_WRITE_1(sc, VGE_CAM0 + i, addr[i]); 423 424 /* Issue a write command. */ 425 CSR_SETBIT_1(sc, VGE_CAMCTL, VGE_CAMCTL_WRITE); 426 427 /* Wake for it to clear. */ 428 for (i = 0; i < VGE_TIMEOUT; i++) { 429 DELAY(1); 430 if ((CSR_READ_1(sc, VGE_CAMCTL) & VGE_CAMCTL_WRITE) == 0) 431 break; 432 } 433 434 if (i == VGE_TIMEOUT) { 435 printf("%s: setting CAM filter failed\n", sc->vge_dev.dv_xname); 436 error = EIO; 437 goto fail; 438 } 439 440 /* Select the CAM mask page. */ 441 CSR_CLRBIT_1(sc, VGE_CAMCTL, VGE_CAMCTL_PAGESEL); 442 CSR_SETBIT_1(sc, VGE_CAMCTL, VGE_PAGESEL_CAMMASK); 443 444 /* Set the mask bit that enables this filter. */ 445 CSR_SETBIT_1(sc, VGE_CAM0 + (sc->vge_camidx/8), 446 1<<(sc->vge_camidx & 7)); 447 448 sc->vge_camidx++; 449 450 fail: 451 /* Turn off access to CAM. */ 452 CSR_WRITE_1(sc, VGE_CAMADDR, 0); 453 CSR_CLRBIT_1(sc, VGE_CAMCTL, VGE_CAMCTL_PAGESEL); 454 CSR_SETBIT_1(sc, VGE_CAMCTL, VGE_PAGESEL_MAR); 455 456 return (error); 457 } 458 459 /* 460 * We use the 64-entry CAM filter for perfect filtering. 461 * If there's more than 64 multicast addresses, we use the 462 * hash filter instead. 463 */ 464 void 465 vge_iff(struct vge_softc *sc) 466 { 467 struct arpcom *ac = &sc->arpcom; 468 struct ifnet *ifp = &ac->ac_if; 469 struct ether_multi *enm; 470 struct ether_multistep step; 471 u_int32_t h = 0, hashes[2]; 472 u_int8_t rxctl; 473 int error; 474 475 vge_cam_clear(sc); 476 rxctl = CSR_READ_1(sc, VGE_RXCTL); 477 rxctl &= ~(VGE_RXCTL_RX_BCAST | VGE_RXCTL_RX_MCAST | 478 VGE_RXCTL_RX_PROMISC | VGE_RXCTL_RX_UCAST); 479 bzero(hashes, sizeof(hashes)); 480 ifp->if_flags &= ~IFF_ALLMULTI; 481 482 /* 483 * Always accept broadcast frames. 484 * Always accept frames destined to our station address. 485 */ 486 rxctl |= VGE_RXCTL_RX_BCAST | VGE_RXCTL_RX_UCAST; 487 488 if ((ifp->if_flags & IFF_PROMISC) == 0) 489 rxctl |= VGE_RXCTL_RX_MCAST; 490 491 if (ifp->if_flags & IFF_PROMISC || ac->ac_multirangecnt > 0) { 492 ifp->if_flags |= IFF_ALLMULTI; 493 if (ifp->if_flags & IFF_PROMISC) 494 rxctl |= VGE_RXCTL_RX_PROMISC; 495 hashes[0] = hashes[1] = 0xFFFFFFFF; 496 } else if (ac->ac_multicnt > VGE_CAM_MAXADDRS) { 497 ETHER_FIRST_MULTI(step, ac, enm); 498 while (enm != NULL) { 499 h = ether_crc32_be(enm->enm_addrlo, 500 ETHER_ADDR_LEN) >> 26; 501 502 hashes[h >> 5] |= 1 << (h & 0x1f); 503 504 ETHER_NEXT_MULTI(step, enm); 505 } 506 } else { 507 ETHER_FIRST_MULTI(step, ac, enm); 508 while (enm != NULL) { 509 error = vge_cam_set(sc, enm->enm_addrlo); 510 if (error) 511 break; 512 513 ETHER_NEXT_MULTI(step, enm); 514 } 515 } 516 517 CSR_WRITE_4(sc, VGE_MAR0, hashes[0]); 518 CSR_WRITE_4(sc, VGE_MAR1, hashes[1]); 519 CSR_WRITE_1(sc, VGE_RXCTL, rxctl); 520 } 521 522 void 523 vge_reset(struct vge_softc *sc) 524 { 525 int i; 526 527 CSR_WRITE_1(sc, VGE_CRS1, VGE_CR1_SOFTRESET); 528 529 for (i = 0; i < VGE_TIMEOUT; i++) { 530 DELAY(5); 531 if ((CSR_READ_1(sc, VGE_CRS1) & VGE_CR1_SOFTRESET) == 0) 532 break; 533 } 534 535 if (i == VGE_TIMEOUT) { 536 printf("%s: soft reset timed out", sc->vge_dev.dv_xname); 537 CSR_WRITE_1(sc, VGE_CRS3, VGE_CR3_STOP_FORCE); 538 DELAY(2000); 539 } 540 541 DELAY(5000); 542 543 CSR_SETBIT_1(sc, VGE_EECSR, VGE_EECSR_RELOAD); 544 545 for (i = 0; i < VGE_TIMEOUT; i++) { 546 DELAY(5); 547 if ((CSR_READ_1(sc, VGE_EECSR) & VGE_EECSR_RELOAD) == 0) 548 break; 549 } 550 551 CSR_CLRBIT_1(sc, VGE_CHIPCFG0, VGE_CHIPCFG0_PACPI); 552 } 553 554 /* 555 * Probe for a VIA gigabit chip. Check the PCI vendor and device 556 * IDs against our list and return a device name if we find a match. 557 */ 558 int 559 vge_probe(struct device *dev, void *match, void *aux) 560 { 561 return (pci_matchbyid((struct pci_attach_args *)aux, vge_devices, 562 nitems(vge_devices))); 563 } 564 565 /* 566 * Allocate memory for RX/TX rings 567 */ 568 int 569 vge_allocmem(struct vge_softc *sc) 570 { 571 int nseg, rseg; 572 int i, error; 573 574 nseg = 32; 575 576 /* Allocate DMA'able memory for the TX ring */ 577 578 error = bus_dmamap_create(sc->sc_dmat, VGE_TX_LIST_SZ, 1, 579 VGE_TX_LIST_SZ, 0, BUS_DMA_ALLOCNOW, 580 &sc->vge_ldata.vge_tx_list_map); 581 if (error) 582 return (ENOMEM); 583 error = bus_dmamem_alloc(sc->sc_dmat, VGE_TX_LIST_SZ, 584 ETHER_ALIGN, 0, 585 &sc->vge_ldata.vge_tx_listseg, 1, &rseg, BUS_DMA_NOWAIT); 586 if (error) { 587 printf("%s: can't alloc TX list\n", sc->vge_dev.dv_xname); 588 return (ENOMEM); 589 } 590 591 /* Load the map for the TX ring. */ 592 error = bus_dmamem_map(sc->sc_dmat, &sc->vge_ldata.vge_tx_listseg, 593 1, VGE_TX_LIST_SZ, 594 (caddr_t *)&sc->vge_ldata.vge_tx_list, BUS_DMA_NOWAIT); 595 memset(sc->vge_ldata.vge_tx_list, 0, VGE_TX_LIST_SZ); 596 if (error) { 597 printf("%s: can't map TX dma buffers\n", 598 sc->vge_dev.dv_xname); 599 bus_dmamem_free(sc->sc_dmat, &sc->vge_ldata.vge_tx_listseg, rseg); 600 return (ENOMEM); 601 } 602 603 error = bus_dmamap_load(sc->sc_dmat, sc->vge_ldata.vge_tx_list_map, 604 sc->vge_ldata.vge_tx_list, VGE_TX_LIST_SZ, NULL, BUS_DMA_NOWAIT); 605 if (error) { 606 printf("%s: can't load TX dma map\n", sc->vge_dev.dv_xname); 607 bus_dmamap_destroy(sc->sc_dmat, sc->vge_ldata.vge_tx_list_map); 608 bus_dmamem_unmap(sc->sc_dmat, (caddr_t)sc->vge_ldata.vge_tx_list, 609 VGE_TX_LIST_SZ); 610 bus_dmamem_free(sc->sc_dmat, &sc->vge_ldata.vge_tx_listseg, rseg); 611 return (ENOMEM); 612 } 613 614 /* Create DMA maps for TX buffers */ 615 616 for (i = 0; i < VGE_TX_DESC_CNT; i++) { 617 error = bus_dmamap_create(sc->sc_dmat, MCLBYTES * nseg, 618 VGE_TX_FRAGS, MCLBYTES, 0, BUS_DMA_ALLOCNOW, 619 &sc->vge_ldata.vge_tx_dmamap[i]); 620 if (error) { 621 printf("%s: can't create DMA map for TX\n", 622 sc->vge_dev.dv_xname); 623 return (ENOMEM); 624 } 625 } 626 627 /* Allocate DMA'able memory for the RX ring */ 628 629 error = bus_dmamap_create(sc->sc_dmat, VGE_RX_LIST_SZ, 1, 630 VGE_RX_LIST_SZ, 0, BUS_DMA_ALLOCNOW, 631 &sc->vge_ldata.vge_rx_list_map); 632 if (error) 633 return (ENOMEM); 634 error = bus_dmamem_alloc(sc->sc_dmat, VGE_RX_LIST_SZ, VGE_RING_ALIGN, 635 0, &sc->vge_ldata.vge_rx_listseg, 1, &rseg, BUS_DMA_NOWAIT); 636 if (error) { 637 printf("%s: can't alloc RX list\n", sc->vge_dev.dv_xname); 638 return (ENOMEM); 639 } 640 641 /* Load the map for the RX ring. */ 642 643 error = bus_dmamem_map(sc->sc_dmat, &sc->vge_ldata.vge_rx_listseg, 644 1, VGE_RX_LIST_SZ, 645 (caddr_t *)&sc->vge_ldata.vge_rx_list, BUS_DMA_NOWAIT); 646 memset(sc->vge_ldata.vge_rx_list, 0, VGE_RX_LIST_SZ); 647 if (error) { 648 printf("%s: can't map RX dma buffers\n", 649 sc->vge_dev.dv_xname); 650 bus_dmamem_free(sc->sc_dmat, &sc->vge_ldata.vge_rx_listseg, rseg); 651 return (ENOMEM); 652 } 653 error = bus_dmamap_load(sc->sc_dmat, sc->vge_ldata.vge_rx_list_map, 654 sc->vge_ldata.vge_rx_list, VGE_RX_LIST_SZ, NULL, BUS_DMA_NOWAIT); 655 if (error) { 656 printf("%s: can't load RX dma map\n", sc->vge_dev.dv_xname); 657 bus_dmamap_destroy(sc->sc_dmat, sc->vge_ldata.vge_rx_list_map); 658 bus_dmamem_unmap(sc->sc_dmat, (caddr_t)sc->vge_ldata.vge_rx_list, 659 VGE_RX_LIST_SZ); 660 bus_dmamem_free(sc->sc_dmat, &sc->vge_ldata.vge_rx_listseg, rseg); 661 return (ENOMEM); 662 } 663 664 /* Create DMA maps for RX buffers */ 665 666 for (i = 0; i < VGE_RX_DESC_CNT; i++) { 667 error = bus_dmamap_create(sc->sc_dmat, MCLBYTES * nseg, nseg, 668 MCLBYTES, 0, BUS_DMA_ALLOCNOW, 669 &sc->vge_ldata.vge_rx_dmamap[i]); 670 if (error) { 671 printf("%s: can't create DMA map for RX\n", 672 sc->vge_dev.dv_xname); 673 return (ENOMEM); 674 } 675 } 676 677 return (0); 678 } 679 680 void 681 vge_freemem(struct vge_softc *sc) 682 { 683 int i; 684 685 for (i = 0; i < VGE_RX_DESC_CNT; i++) 686 bus_dmamap_destroy(sc->sc_dmat, 687 sc->vge_ldata.vge_rx_dmamap[i]); 688 689 bus_dmamap_unload(sc->sc_dmat, sc->vge_ldata.vge_rx_list_map); 690 bus_dmamap_destroy(sc->sc_dmat, sc->vge_ldata.vge_rx_list_map); 691 bus_dmamem_unmap(sc->sc_dmat, (caddr_t)sc->vge_ldata.vge_rx_list, 692 VGE_RX_LIST_SZ); 693 bus_dmamem_free(sc->sc_dmat, &sc->vge_ldata.vge_rx_listseg, 1); 694 695 for (i = 0; i < VGE_TX_DESC_CNT; i++) 696 bus_dmamap_destroy(sc->sc_dmat, 697 sc->vge_ldata.vge_tx_dmamap[i]); 698 699 bus_dmamap_unload(sc->sc_dmat, sc->vge_ldata.vge_tx_list_map); 700 bus_dmamap_destroy(sc->sc_dmat, sc->vge_ldata.vge_tx_list_map); 701 bus_dmamem_unmap(sc->sc_dmat, (caddr_t)sc->vge_ldata.vge_tx_list, 702 VGE_TX_LIST_SZ); 703 bus_dmamem_free(sc->sc_dmat, &sc->vge_ldata.vge_tx_listseg, 1); 704 } 705 706 /* 707 * Attach the interface. Allocate softc structures, do ifmedia 708 * setup and ethernet/BPF attach. 709 */ 710 void 711 vge_attach(struct device *parent, struct device *self, void *aux) 712 { 713 u_char eaddr[ETHER_ADDR_LEN]; 714 struct vge_softc *sc = (struct vge_softc *)self; 715 struct pci_attach_args *pa = aux; 716 pci_chipset_tag_t pc = pa->pa_pc; 717 pci_intr_handle_t ih; 718 const char *intrstr = NULL; 719 struct ifnet *ifp; 720 int error = 0; 721 722 /* 723 * Map control/status registers. 724 */ 725 if (pci_mapreg_map(pa, VGE_PCI_LOMEM, PCI_MAPREG_TYPE_MEM, 0, 726 &sc->vge_btag, &sc->vge_bhandle, NULL, &sc->vge_bsize, 0)) { 727 if (pci_mapreg_map(pa, VGE_PCI_LOIO, PCI_MAPREG_TYPE_IO, 0, 728 &sc->vge_btag, &sc->vge_bhandle, NULL, &sc->vge_bsize, 0)) { 729 printf(": can't map mem or i/o space\n"); 730 return; 731 } 732 } 733 734 /* Allocate interrupt */ 735 if (pci_intr_map(pa, &ih)) { 736 printf(": couldn't map interrupt\n"); 737 return; 738 } 739 intrstr = pci_intr_string(pc, ih); 740 sc->vge_intrhand = pci_intr_establish(pc, ih, IPL_NET, vge_intr, sc, 741 sc->vge_dev.dv_xname); 742 if (sc->vge_intrhand == NULL) { 743 printf(": couldn't establish interrupt"); 744 if (intrstr != NULL) 745 printf(" at %s", intrstr); 746 return; 747 } 748 printf(": %s", intrstr); 749 750 sc->sc_dmat = pa->pa_dmat; 751 sc->sc_pc = pa->pa_pc; 752 753 /* Reset the adapter. */ 754 vge_reset(sc); 755 756 /* 757 * Get station address from the EEPROM. 758 */ 759 vge_read_eeprom(sc, eaddr, VGE_EE_EADDR, 3, 1); 760 761 bcopy(eaddr, &sc->arpcom.ac_enaddr, ETHER_ADDR_LEN); 762 763 printf(", address %s\n", 764 ether_sprintf(sc->arpcom.ac_enaddr)); 765 766 error = vge_allocmem(sc); 767 768 if (error) 769 return; 770 771 ifp = &sc->arpcom.ac_if; 772 ifp->if_softc = sc; 773 ifp->if_flags = IFF_BROADCAST | IFF_SIMPLEX | IFF_MULTICAST; 774 ifp->if_ioctl = vge_ioctl; 775 ifp->if_start = vge_start; 776 ifp->if_watchdog = vge_watchdog; 777 #ifdef VGE_JUMBO 778 ifp->if_hardmtu = VGE_JUMBO_MTU; 779 #endif 780 IFQ_SET_MAXLEN(&ifp->if_snd, VGE_IFQ_MAXLEN); 781 782 ifp->if_capabilities = IFCAP_VLAN_MTU | IFCAP_CSUM_IPv4 | 783 IFCAP_CSUM_TCPv4 | IFCAP_CSUM_UDPv4; 784 785 #if NVLAN > 0 786 ifp->if_capabilities |= IFCAP_VLAN_HWTAGGING; 787 #endif 788 789 /* Set interface name */ 790 strlcpy(ifp->if_xname, sc->vge_dev.dv_xname, IFNAMSIZ); 791 792 /* Do MII setup */ 793 sc->sc_mii.mii_ifp = ifp; 794 sc->sc_mii.mii_readreg = vge_miibus_readreg; 795 sc->sc_mii.mii_writereg = vge_miibus_writereg; 796 sc->sc_mii.mii_statchg = vge_miibus_statchg; 797 ifmedia_init(&sc->sc_mii.mii_media, 0, 798 vge_ifmedia_upd, vge_ifmedia_sts); 799 mii_attach(self, &sc->sc_mii, 0xffffffff, MII_PHY_ANY, 800 MII_OFFSET_ANY, MIIF_DOPAUSE); 801 if (LIST_FIRST(&sc->sc_mii.mii_phys) == NULL) { 802 printf("%s: no PHY found!\n", sc->vge_dev.dv_xname); 803 ifmedia_add(&sc->sc_mii.mii_media, IFM_ETHER|IFM_MANUAL, 804 0, NULL); 805 ifmedia_set(&sc->sc_mii.mii_media, IFM_ETHER|IFM_MANUAL); 806 } else 807 ifmedia_set(&sc->sc_mii.mii_media, IFM_ETHER|IFM_AUTO); 808 809 timeout_set(&sc->timer_handle, vge_tick, sc); 810 811 /* 812 * Call MI attach routine. 813 */ 814 if_attach(ifp); 815 ether_ifattach(ifp); 816 } 817 818 int 819 vge_detach(struct device *self, int flags) 820 { 821 struct vge_softc *sc = (void *)self; 822 struct ifnet *ifp = &sc->arpcom.ac_if; 823 824 pci_intr_disestablish(sc->sc_pc, sc->vge_intrhand); 825 826 vge_stop(sc); 827 828 /* Detach all PHYs */ 829 mii_detach(&sc->sc_mii, MII_PHY_ANY, MII_OFFSET_ANY); 830 831 /* Delete any remaining media. */ 832 ifmedia_delete_instance(&sc->sc_mii.mii_media, IFM_INST_ANY); 833 834 ether_ifdetach(ifp); 835 if_detach(ifp); 836 837 vge_freemem(sc); 838 839 bus_space_unmap(sc->vge_btag, sc->vge_bhandle, sc->vge_bsize); 840 return (0); 841 } 842 843 int 844 vge_newbuf(struct vge_softc *sc, int idx, struct mbuf *m) 845 { 846 struct mbuf *m_new = NULL; 847 struct vge_rx_desc *r; 848 bus_dmamap_t rxmap = sc->vge_ldata.vge_rx_dmamap[idx]; 849 int i; 850 851 if (m == NULL) { 852 /* Allocate a new mbuf */ 853 MGETHDR(m_new, M_DONTWAIT, MT_DATA); 854 if (m_new == NULL) 855 return (ENOBUFS); 856 857 /* Allocate a cluster */ 858 MCLGET(m_new, M_DONTWAIT); 859 if (!(m_new->m_flags & M_EXT)) { 860 m_freem(m_new); 861 return (ENOBUFS); 862 } 863 864 m = m_new; 865 } else 866 m->m_data = m->m_ext.ext_buf; 867 868 m->m_len = m->m_pkthdr.len = MCLBYTES; 869 /* Fix-up alignment so payload is doubleword-aligned */ 870 /* XXX m_adj(m, ETHER_ALIGN); */ 871 872 if (bus_dmamap_load_mbuf(sc->sc_dmat, rxmap, m, BUS_DMA_NOWAIT)) 873 return (ENOBUFS); 874 875 if (rxmap->dm_nsegs > 1) 876 goto out; 877 878 /* Map the segments into RX descriptors */ 879 r = &sc->vge_ldata.vge_rx_list[idx]; 880 881 if (letoh32(r->vge_sts) & VGE_RDSTS_OWN) { 882 printf("%s: tried to map a busy RX descriptor\n", 883 sc->vge_dev.dv_xname); 884 goto out; 885 } 886 r->vge_buflen = htole16(VGE_BUFLEN(rxmap->dm_segs[0].ds_len) | VGE_RXDESC_I); 887 r->vge_addrlo = htole32(VGE_ADDR_LO(rxmap->dm_segs[0].ds_addr)); 888 r->vge_addrhi = htole16(VGE_ADDR_HI(rxmap->dm_segs[0].ds_addr) & 0xFFFF); 889 r->vge_sts = htole32(0); 890 r->vge_ctl = htole32(0); 891 892 /* 893 * Note: the manual fails to document the fact that for 894 * proper operation, the driver needs to replenish the RX 895 * DMA ring 4 descriptors at a time (rather than one at a 896 * time, like most chips). We can allocate the new buffers 897 * but we should not set the OWN bits until we're ready 898 * to hand back 4 of them in one shot. 899 */ 900 #define VGE_RXCHUNK 4 901 sc->vge_rx_consumed++; 902 if (sc->vge_rx_consumed == VGE_RXCHUNK) { 903 for (i = idx; i != idx - sc->vge_rx_consumed; i--) 904 sc->vge_ldata.vge_rx_list[i].vge_sts |= 905 htole32(VGE_RDSTS_OWN); 906 sc->vge_rx_consumed = 0; 907 } 908 909 sc->vge_ldata.vge_rx_mbuf[idx] = m; 910 911 bus_dmamap_sync(sc->sc_dmat, rxmap, 0, 912 rxmap->dm_mapsize, BUS_DMASYNC_PREREAD); 913 914 return (0); 915 out: 916 DPRINTF(("vge_newbuf: out of memory\n")); 917 if (m_new != NULL) 918 m_freem(m_new); 919 return (ENOMEM); 920 } 921 922 int 923 vge_tx_list_init(struct vge_softc *sc) 924 { 925 bzero(sc->vge_ldata.vge_tx_list, VGE_TX_LIST_SZ); 926 bzero(&sc->vge_ldata.vge_tx_mbuf, 927 (VGE_TX_DESC_CNT * sizeof(struct mbuf *))); 928 929 bus_dmamap_sync(sc->sc_dmat, 930 sc->vge_ldata.vge_tx_list_map, 0, 931 sc->vge_ldata.vge_tx_list_map->dm_mapsize, 932 BUS_DMASYNC_PREWRITE); 933 sc->vge_ldata.vge_tx_prodidx = 0; 934 sc->vge_ldata.vge_tx_considx = 0; 935 sc->vge_ldata.vge_tx_free = VGE_TX_DESC_CNT; 936 937 return (0); 938 } 939 940 /* Init RX descriptors and allocate mbufs with vge_newbuf() 941 * A ring is used, and last descriptor points to first. */ 942 int 943 vge_rx_list_init(struct vge_softc *sc) 944 { 945 int i; 946 947 bzero(sc->vge_ldata.vge_rx_list, VGE_RX_LIST_SZ); 948 bzero(&sc->vge_ldata.vge_rx_mbuf, 949 (VGE_RX_DESC_CNT * sizeof(struct mbuf *))); 950 951 sc->vge_rx_consumed = 0; 952 953 for (i = 0; i < VGE_RX_DESC_CNT; i++) { 954 if (vge_newbuf(sc, i, NULL) == ENOBUFS) 955 return (ENOBUFS); 956 } 957 958 /* Flush the RX descriptors */ 959 960 bus_dmamap_sync(sc->sc_dmat, 961 sc->vge_ldata.vge_rx_list_map, 962 0, sc->vge_ldata.vge_rx_list_map->dm_mapsize, 963 BUS_DMASYNC_PREWRITE|BUS_DMASYNC_PREREAD); 964 965 sc->vge_ldata.vge_rx_prodidx = 0; 966 sc->vge_rx_consumed = 0; 967 sc->vge_head = sc->vge_tail = NULL; 968 969 return (0); 970 } 971 972 /* 973 * RX handler. We support the reception of jumbo frames that have 974 * been fragmented across multiple 2K mbuf cluster buffers. 975 */ 976 void 977 vge_rxeof(struct vge_softc *sc) 978 { 979 struct mbuf_list ml = MBUF_LIST_INITIALIZER(); 980 struct mbuf *m; 981 struct ifnet *ifp; 982 int i, total_len; 983 int lim = 0; 984 struct vge_rx_desc *cur_rx; 985 u_int32_t rxstat, rxctl; 986 987 ifp = &sc->arpcom.ac_if; 988 i = sc->vge_ldata.vge_rx_prodidx; 989 990 /* Invalidate the descriptor memory */ 991 992 bus_dmamap_sync(sc->sc_dmat, 993 sc->vge_ldata.vge_rx_list_map, 994 0, sc->vge_ldata.vge_rx_list_map->dm_mapsize, 995 BUS_DMASYNC_POSTREAD); 996 997 while (!VGE_OWN(&sc->vge_ldata.vge_rx_list[i])) { 998 struct mbuf *m0 = NULL; 999 1000 cur_rx = &sc->vge_ldata.vge_rx_list[i]; 1001 m = sc->vge_ldata.vge_rx_mbuf[i]; 1002 total_len = VGE_RXBYTES(cur_rx); 1003 rxstat = letoh32(cur_rx->vge_sts); 1004 rxctl = letoh32(cur_rx->vge_ctl); 1005 1006 /* Invalidate the RX mbuf and unload its map */ 1007 1008 bus_dmamap_sync(sc->sc_dmat, 1009 sc->vge_ldata.vge_rx_dmamap[i], 1010 0, sc->vge_ldata.vge_rx_dmamap[i]->dm_mapsize, 1011 BUS_DMASYNC_POSTWRITE); 1012 bus_dmamap_unload(sc->sc_dmat, 1013 sc->vge_ldata.vge_rx_dmamap[i]); 1014 1015 /* 1016 * If the 'start of frame' bit is set, this indicates 1017 * either the first fragment in a multi-fragment receive, 1018 * or an intermediate fragment. Either way, we want to 1019 * accumulate the buffers. 1020 */ 1021 if (rxstat & VGE_RXPKT_SOF) { 1022 DPRINTF(("vge_rxeof: SOF\n")); 1023 m->m_len = MCLBYTES; 1024 if (sc->vge_head == NULL) 1025 sc->vge_head = sc->vge_tail = m; 1026 else { 1027 m->m_flags &= ~M_PKTHDR; 1028 sc->vge_tail->m_next = m; 1029 sc->vge_tail = m; 1030 } 1031 vge_newbuf(sc, i, NULL); 1032 VGE_RX_DESC_INC(i); 1033 continue; 1034 } 1035 1036 /* 1037 * Bad/error frames will have the RXOK bit cleared. 1038 * However, there's one error case we want to allow: 1039 * if a VLAN tagged frame arrives and the chip can't 1040 * match it against the CAM filter, it considers this 1041 * a 'VLAN CAM filter miss' and clears the 'RXOK' bit. 1042 * We don't want to drop the frame though: our VLAN 1043 * filtering is done in software. 1044 */ 1045 if (!(rxstat & VGE_RDSTS_RXOK) && !(rxstat & VGE_RDSTS_VIDM) 1046 && !(rxstat & VGE_RDSTS_CSUMERR)) { 1047 ifp->if_ierrors++; 1048 /* 1049 * If this is part of a multi-fragment packet, 1050 * discard all the pieces. 1051 */ 1052 if (sc->vge_head != NULL) { 1053 m_freem(sc->vge_head); 1054 sc->vge_head = sc->vge_tail = NULL; 1055 } 1056 vge_newbuf(sc, i, m); 1057 VGE_RX_DESC_INC(i); 1058 continue; 1059 } 1060 1061 /* 1062 * If allocating a replacement mbuf fails, 1063 * reload the current one. 1064 */ 1065 1066 if (vge_newbuf(sc, i, NULL) == ENOBUFS) { 1067 if (sc->vge_head != NULL) { 1068 m_freem(sc->vge_head); 1069 sc->vge_head = sc->vge_tail = NULL; 1070 } 1071 1072 m0 = m_devget(mtod(m, char *), 1073 total_len - ETHER_CRC_LEN, ETHER_ALIGN); 1074 vge_newbuf(sc, i, m); 1075 if (m0 == NULL) { 1076 ifp->if_ierrors++; 1077 continue; 1078 } 1079 m = m0; 1080 1081 VGE_RX_DESC_INC(i); 1082 continue; 1083 } 1084 1085 VGE_RX_DESC_INC(i); 1086 1087 if (sc->vge_head != NULL) { 1088 m->m_len = total_len % MCLBYTES; 1089 /* 1090 * Special case: if there's 4 bytes or less 1091 * in this buffer, the mbuf can be discarded: 1092 * the last 4 bytes is the CRC, which we don't 1093 * care about anyway. 1094 */ 1095 if (m->m_len <= ETHER_CRC_LEN) { 1096 sc->vge_tail->m_len -= 1097 (ETHER_CRC_LEN - m->m_len); 1098 m_freem(m); 1099 } else { 1100 m->m_len -= ETHER_CRC_LEN; 1101 m->m_flags &= ~M_PKTHDR; 1102 sc->vge_tail->m_next = m; 1103 } 1104 m = sc->vge_head; 1105 sc->vge_head = sc->vge_tail = NULL; 1106 m->m_pkthdr.len = total_len - ETHER_CRC_LEN; 1107 } else 1108 m->m_pkthdr.len = m->m_len = 1109 (total_len - ETHER_CRC_LEN); 1110 1111 #ifdef __STRICT_ALIGNMENT 1112 bcopy(m->m_data, m->m_data + ETHER_ALIGN, total_len); 1113 m->m_data += ETHER_ALIGN; 1114 #endif 1115 /* Do RX checksumming */ 1116 1117 /* Check IP header checksum */ 1118 if ((rxctl & VGE_RDCTL_IPPKT) && 1119 (rxctl & VGE_RDCTL_IPCSUMOK)) 1120 m->m_pkthdr.csum_flags |= M_IPV4_CSUM_IN_OK; 1121 1122 /* Check TCP/UDP checksum */ 1123 if ((rxctl & (VGE_RDCTL_TCPPKT|VGE_RDCTL_UDPPKT)) && 1124 (rxctl & VGE_RDCTL_PROTOCSUMOK)) 1125 m->m_pkthdr.csum_flags |= M_TCP_CSUM_IN_OK | M_UDP_CSUM_IN_OK; 1126 1127 #if NVLAN > 0 1128 if (rxstat & VGE_RDSTS_VTAG) { 1129 m->m_pkthdr.ether_vtag = swap16(rxctl & VGE_RDCTL_VLANID); 1130 m->m_flags |= M_VLANTAG; 1131 } 1132 #endif 1133 1134 ml_enqueue(&ml, m); 1135 1136 lim++; 1137 if (lim == VGE_RX_DESC_CNT) 1138 break; 1139 } 1140 1141 if_input(ifp, &ml); 1142 1143 /* Flush the RX DMA ring */ 1144 bus_dmamap_sync(sc->sc_dmat, 1145 sc->vge_ldata.vge_rx_list_map, 1146 0, sc->vge_ldata.vge_rx_list_map->dm_mapsize, 1147 BUS_DMASYNC_PREWRITE|BUS_DMASYNC_PREREAD); 1148 1149 sc->vge_ldata.vge_rx_prodidx = i; 1150 CSR_WRITE_2(sc, VGE_RXDESC_RESIDUECNT, lim); 1151 } 1152 1153 void 1154 vge_txeof(struct vge_softc *sc) 1155 { 1156 struct ifnet *ifp; 1157 u_int32_t txstat; 1158 int idx; 1159 1160 ifp = &sc->arpcom.ac_if; 1161 idx = sc->vge_ldata.vge_tx_considx; 1162 1163 /* Invalidate the TX descriptor list */ 1164 1165 bus_dmamap_sync(sc->sc_dmat, 1166 sc->vge_ldata.vge_tx_list_map, 1167 0, sc->vge_ldata.vge_tx_list_map->dm_mapsize, 1168 BUS_DMASYNC_POSTREAD); 1169 1170 /* Transmitted frames can be now free'd from the TX list */ 1171 while (idx != sc->vge_ldata.vge_tx_prodidx) { 1172 txstat = letoh32(sc->vge_ldata.vge_tx_list[idx].vge_sts); 1173 if (txstat & VGE_TDSTS_OWN) 1174 break; 1175 1176 m_freem(sc->vge_ldata.vge_tx_mbuf[idx]); 1177 sc->vge_ldata.vge_tx_mbuf[idx] = NULL; 1178 bus_dmamap_unload(sc->sc_dmat, 1179 sc->vge_ldata.vge_tx_dmamap[idx]); 1180 if (txstat & (VGE_TDSTS_EXCESSCOLL|VGE_TDSTS_COLL)) 1181 ifp->if_collisions++; 1182 if (txstat & VGE_TDSTS_TXERR) 1183 ifp->if_oerrors++; 1184 else 1185 ifp->if_opackets++; 1186 1187 sc->vge_ldata.vge_tx_free++; 1188 VGE_TX_DESC_INC(idx); 1189 } 1190 1191 /* No changes made to the TX ring, so no flush needed */ 1192 1193 if (idx != sc->vge_ldata.vge_tx_considx) { 1194 sc->vge_ldata.vge_tx_considx = idx; 1195 ifq_clr_oactive(&ifp->if_snd); 1196 ifp->if_timer = 0; 1197 } 1198 1199 /* 1200 * If not all descriptors have been released reaped yet, 1201 * reload the timer so that we will eventually get another 1202 * interrupt that will cause us to re-enter this routine. 1203 * This is done in case the transmitter has gone idle. 1204 */ 1205 if (sc->vge_ldata.vge_tx_free != VGE_TX_DESC_CNT) 1206 CSR_WRITE_1(sc, VGE_CRS1, VGE_CR1_TIMER0_ENABLE); 1207 } 1208 1209 void 1210 vge_tick(void *xsc) 1211 { 1212 struct vge_softc *sc = xsc; 1213 struct ifnet *ifp = &sc->arpcom.ac_if; 1214 struct mii_data *mii = &sc->sc_mii; 1215 int s; 1216 1217 s = splnet(); 1218 1219 mii_tick(mii); 1220 1221 if (sc->vge_link) { 1222 if (!(mii->mii_media_status & IFM_ACTIVE)) { 1223 sc->vge_link = 0; 1224 ifp->if_link_state = LINK_STATE_DOWN; 1225 if_link_state_change(ifp); 1226 } 1227 } else { 1228 if (mii->mii_media_status & IFM_ACTIVE && 1229 IFM_SUBTYPE(mii->mii_media_active) != IFM_NONE) { 1230 sc->vge_link = 1; 1231 if (mii->mii_media_status & IFM_FDX) 1232 ifp->if_link_state = LINK_STATE_FULL_DUPLEX; 1233 else 1234 ifp->if_link_state = LINK_STATE_HALF_DUPLEX; 1235 if_link_state_change(ifp); 1236 if (!IFQ_IS_EMPTY(&ifp->if_snd)) 1237 vge_start(ifp); 1238 } 1239 } 1240 timeout_add_sec(&sc->timer_handle, 1); 1241 splx(s); 1242 } 1243 1244 int 1245 vge_intr(void *arg) 1246 { 1247 struct vge_softc *sc = arg; 1248 struct ifnet *ifp; 1249 u_int32_t status; 1250 int claimed = 0; 1251 1252 ifp = &sc->arpcom.ac_if; 1253 1254 if (!(ifp->if_flags & IFF_UP)) 1255 return 0; 1256 1257 /* Disable interrupts */ 1258 CSR_WRITE_1(sc, VGE_CRC3, VGE_CR3_INT_GMSK); 1259 1260 for (;;) { 1261 status = CSR_READ_4(sc, VGE_ISR); 1262 DPRINTFN(3, ("vge_intr: status=%#x\n", status)); 1263 1264 /* If the card has gone away the read returns 0xffffffff. */ 1265 if (status == 0xFFFFFFFF) 1266 break; 1267 1268 if (status) { 1269 CSR_WRITE_4(sc, VGE_ISR, status); 1270 } 1271 1272 if ((status & VGE_INTRS) == 0) 1273 break; 1274 1275 claimed = 1; 1276 1277 if (status & (VGE_ISR_RXOK|VGE_ISR_RXOK_HIPRIO)) 1278 vge_rxeof(sc); 1279 1280 if (status & (VGE_ISR_RXOFLOW|VGE_ISR_RXNODESC)) { 1281 DPRINTFN(2, ("vge_intr: RX error, recovering\n")); 1282 vge_rxeof(sc); 1283 CSR_WRITE_1(sc, VGE_RXQCSRS, VGE_RXQCSR_RUN); 1284 CSR_WRITE_1(sc, VGE_RXQCSRS, VGE_RXQCSR_WAK); 1285 } 1286 1287 if (status & (VGE_ISR_TXOK0|VGE_ISR_TIMER0)) 1288 vge_txeof(sc); 1289 1290 if (status & (VGE_ISR_TXDMA_STALL|VGE_ISR_RXDMA_STALL)) { 1291 DPRINTFN(2, ("DMA_STALL\n")); 1292 vge_init(ifp); 1293 } 1294 1295 if (status & VGE_ISR_LINKSTS) { 1296 timeout_del(&sc->timer_handle); 1297 vge_tick(sc); 1298 } 1299 } 1300 1301 /* Re-enable interrupts */ 1302 CSR_WRITE_1(sc, VGE_CRS3, VGE_CR3_INT_GMSK); 1303 1304 if (!IFQ_IS_EMPTY(&ifp->if_snd)) 1305 vge_start(ifp); 1306 1307 return (claimed); 1308 } 1309 1310 /* 1311 * Encapsulate an mbuf chain into the TX ring by combining it w/ 1312 * the descriptors. 1313 */ 1314 int 1315 vge_encap(struct vge_softc *sc, struct mbuf *m_head, int idx) 1316 { 1317 bus_dmamap_t txmap; 1318 struct vge_tx_desc *d = NULL; 1319 struct vge_tx_frag *f; 1320 int error, frag; 1321 u_int32_t vge_flags; 1322 unsigned int len; 1323 1324 vge_flags = 0; 1325 1326 if (m_head->m_pkthdr.csum_flags & M_IPV4_CSUM_OUT) 1327 vge_flags |= VGE_TDCTL_IPCSUM; 1328 if (m_head->m_pkthdr.csum_flags & M_TCP_CSUM_OUT) 1329 vge_flags |= VGE_TDCTL_TCPCSUM; 1330 if (m_head->m_pkthdr.csum_flags & M_UDP_CSUM_OUT) 1331 vge_flags |= VGE_TDCTL_UDPCSUM; 1332 1333 txmap = sc->vge_ldata.vge_tx_dmamap[idx]; 1334 error = bus_dmamap_load_mbuf(sc->sc_dmat, txmap, 1335 m_head, BUS_DMA_NOWAIT); 1336 switch (error) { 1337 case 0: 1338 break; 1339 case EFBIG: /* mbuf chain is too fragmented */ 1340 if ((error = m_defrag(m_head, M_DONTWAIT)) == 0 && 1341 (error = bus_dmamap_load_mbuf(sc->sc_dmat, txmap, m_head, 1342 BUS_DMA_NOWAIT)) == 0) 1343 break; 1344 default: 1345 return (error); 1346 } 1347 1348 d = &sc->vge_ldata.vge_tx_list[idx]; 1349 /* If owned by chip, fail */ 1350 if (letoh32(d->vge_sts) & VGE_TDSTS_OWN) 1351 return (ENOBUFS); 1352 1353 for (frag = 0; frag < txmap->dm_nsegs; frag++) { 1354 f = &d->vge_frag[frag]; 1355 f->vge_buflen = htole16(VGE_BUFLEN(txmap->dm_segs[frag].ds_len)); 1356 f->vge_addrlo = htole32(VGE_ADDR_LO(txmap->dm_segs[frag].ds_addr)); 1357 f->vge_addrhi = htole16(VGE_ADDR_HI(txmap->dm_segs[frag].ds_addr) & 0xFFFF); 1358 } 1359 1360 /* This chip does not do auto-padding */ 1361 if (m_head->m_pkthdr.len < VGE_MIN_FRAMELEN) { 1362 f = &d->vge_frag[frag]; 1363 1364 f->vge_buflen = htole16(VGE_BUFLEN(VGE_MIN_FRAMELEN - 1365 m_head->m_pkthdr.len)); 1366 f->vge_addrlo = htole32(VGE_ADDR_LO(txmap->dm_segs[0].ds_addr)); 1367 f->vge_addrhi = htole16(VGE_ADDR_HI(txmap->dm_segs[0].ds_addr) & 0xFFFF); 1368 len = VGE_MIN_FRAMELEN; 1369 frag++; 1370 } else 1371 len = m_head->m_pkthdr.len; 1372 1373 /* For some reason, we need to tell the card fragment + 1 */ 1374 frag++; 1375 1376 bus_dmamap_sync(sc->sc_dmat, txmap, 0, txmap->dm_mapsize, 1377 BUS_DMASYNC_PREWRITE); 1378 1379 d->vge_sts = htole32(len << 16); 1380 d->vge_ctl = htole32(vge_flags|(frag << 28) | VGE_TD_LS_NORM); 1381 1382 if (len > ETHERMTU + ETHER_HDR_LEN) 1383 d->vge_ctl |= htole32(VGE_TDCTL_JUMBO); 1384 1385 #if NVLAN > 0 1386 /* Set up hardware VLAN tagging. */ 1387 if (m_head->m_flags & M_VLANTAG) { 1388 d->vge_ctl |= htole32(m_head->m_pkthdr.ether_vtag | 1389 VGE_TDCTL_VTAG); 1390 } 1391 #endif 1392 1393 sc->vge_ldata.vge_tx_dmamap[idx] = txmap; 1394 sc->vge_ldata.vge_tx_mbuf[idx] = m_head; 1395 sc->vge_ldata.vge_tx_free--; 1396 sc->vge_ldata.vge_tx_list[idx].vge_sts |= htole32(VGE_TDSTS_OWN); 1397 1398 idx++; 1399 return (0); 1400 } 1401 1402 /* 1403 * Main transmit routine. 1404 */ 1405 void 1406 vge_start(struct ifnet *ifp) 1407 { 1408 struct vge_softc *sc; 1409 struct mbuf *m_head = NULL; 1410 int idx, pidx = 0; 1411 1412 sc = ifp->if_softc; 1413 1414 if (!sc->vge_link || ifq_is_oactive(&ifp->if_snd)) 1415 return; 1416 1417 if (IFQ_IS_EMPTY(&ifp->if_snd)) 1418 return; 1419 1420 idx = sc->vge_ldata.vge_tx_prodidx; 1421 1422 pidx = idx - 1; 1423 if (pidx < 0) 1424 pidx = VGE_TX_DESC_CNT - 1; 1425 1426 for (;;) { 1427 if (sc->vge_ldata.vge_tx_mbuf[idx] != NULL) { 1428 ifq_set_oactive(&ifp->if_snd); 1429 break; 1430 } 1431 1432 IFQ_DEQUEUE(&ifp->if_snd, m_head); 1433 if (m_head == NULL) 1434 break; 1435 1436 if (vge_encap(sc, m_head, idx)) { 1437 m_freem(m_head); 1438 ifp->if_oerrors++; 1439 continue; 1440 } 1441 1442 /* 1443 * If there's a BPF listener, bounce a copy of this frame 1444 * to him. 1445 */ 1446 #if NBPFILTER > 0 1447 if (ifp->if_bpf) 1448 bpf_mtap_ether(ifp->if_bpf, m_head, BPF_DIRECTION_OUT); 1449 #endif 1450 1451 sc->vge_ldata.vge_tx_list[pidx].vge_frag[0].vge_buflen |= 1452 htole16(VGE_TXDESC_Q); 1453 1454 pidx = idx; 1455 VGE_TX_DESC_INC(idx); 1456 } 1457 1458 if (idx == sc->vge_ldata.vge_tx_prodidx) { 1459 return; 1460 } 1461 1462 /* Flush the TX descriptors */ 1463 1464 bus_dmamap_sync(sc->sc_dmat, 1465 sc->vge_ldata.vge_tx_list_map, 1466 0, sc->vge_ldata.vge_tx_list_map->dm_mapsize, 1467 BUS_DMASYNC_PREWRITE|BUS_DMASYNC_PREREAD); 1468 1469 /* Issue a transmit command. */ 1470 CSR_WRITE_2(sc, VGE_TXQCSRS, VGE_TXQCSR_WAK0); 1471 1472 sc->vge_ldata.vge_tx_prodidx = idx; 1473 1474 /* 1475 * Use the countdown timer for interrupt moderation. 1476 * 'TX done' interrupts are disabled. Instead, we reset the 1477 * countdown timer, which will begin counting until it hits 1478 * the value in the SSTIMER register, and then trigger an 1479 * interrupt. Each time we set the TIMER0_ENABLE bit, the 1480 * the timer count is reloaded. Only when the transmitter 1481 * is idle will the timer hit 0 and an interrupt fire. 1482 */ 1483 CSR_WRITE_1(sc, VGE_CRS1, VGE_CR1_TIMER0_ENABLE); 1484 1485 /* 1486 * Set a timeout in case the chip goes out to lunch. 1487 */ 1488 ifp->if_timer = 5; 1489 } 1490 1491 int 1492 vge_init(struct ifnet *ifp) 1493 { 1494 struct vge_softc *sc = ifp->if_softc; 1495 int i; 1496 1497 /* 1498 * Cancel pending I/O and free all RX/TX buffers. 1499 */ 1500 vge_stop(sc); 1501 vge_reset(sc); 1502 1503 /* Initialize RX descriptors list */ 1504 if (vge_rx_list_init(sc) == ENOBUFS) { 1505 printf("%s: init failed: no memory for RX buffers\n", 1506 sc->vge_dev.dv_xname); 1507 vge_stop(sc); 1508 return (ENOBUFS); 1509 } 1510 /* Initialize TX descriptors */ 1511 if (vge_tx_list_init(sc) == ENOBUFS) { 1512 printf("%s: init failed: no memory for TX buffers\n", 1513 sc->vge_dev.dv_xname); 1514 vge_stop(sc); 1515 return (ENOBUFS); 1516 } 1517 1518 /* Set our station address */ 1519 for (i = 0; i < ETHER_ADDR_LEN; i++) 1520 CSR_WRITE_1(sc, VGE_PAR0 + i, sc->arpcom.ac_enaddr[i]); 1521 1522 /* Set receive FIFO threshold */ 1523 CSR_CLRBIT_1(sc, VGE_RXCFG, VGE_RXCFG_FIFO_THR); 1524 CSR_SETBIT_1(sc, VGE_RXCFG, VGE_RXFIFOTHR_128BYTES); 1525 1526 if (ifp->if_capabilities & IFCAP_VLAN_HWTAGGING) { 1527 /* 1528 * Allow transmission and reception of VLAN tagged 1529 * frames. 1530 */ 1531 CSR_CLRBIT_1(sc, VGE_RXCFG, VGE_RXCFG_VTAGOPT); 1532 CSR_SETBIT_1(sc, VGE_RXCFG, VGE_VTAG_OPT2); 1533 } 1534 1535 /* Set DMA burst length */ 1536 CSR_CLRBIT_1(sc, VGE_DMACFG0, VGE_DMACFG0_BURSTLEN); 1537 CSR_SETBIT_1(sc, VGE_DMACFG0, VGE_DMABURST_128); 1538 1539 CSR_SETBIT_1(sc, VGE_TXCFG, VGE_TXCFG_ARB_PRIO|VGE_TXCFG_NONBLK); 1540 1541 /* Set collision backoff algorithm */ 1542 CSR_CLRBIT_1(sc, VGE_CHIPCFG1, VGE_CHIPCFG1_CRANDOM| 1543 VGE_CHIPCFG1_CAP|VGE_CHIPCFG1_MBA|VGE_CHIPCFG1_BAKOPT); 1544 CSR_SETBIT_1(sc, VGE_CHIPCFG1, VGE_CHIPCFG1_OFSET); 1545 1546 /* Disable LPSEL field in priority resolution */ 1547 CSR_SETBIT_1(sc, VGE_DIAGCTL, VGE_DIAGCTL_LPSEL_DIS); 1548 1549 /* 1550 * Load the addresses of the DMA queues into the chip. 1551 * Note that we only use one transmit queue. 1552 */ 1553 CSR_WRITE_4(sc, VGE_TXDESC_ADDR_LO0, 1554 VGE_ADDR_LO(sc->vge_ldata.vge_tx_listseg.ds_addr)); 1555 CSR_WRITE_2(sc, VGE_TXDESCNUM, VGE_TX_DESC_CNT - 1); 1556 1557 CSR_WRITE_4(sc, VGE_RXDESC_ADDR_LO, 1558 VGE_ADDR_LO(sc->vge_ldata.vge_rx_listseg.ds_addr)); 1559 CSR_WRITE_2(sc, VGE_RXDESCNUM, VGE_RX_DESC_CNT - 1); 1560 CSR_WRITE_2(sc, VGE_RXDESC_RESIDUECNT, VGE_RX_DESC_CNT); 1561 1562 /* Enable and wake up the RX descriptor queue */ 1563 CSR_WRITE_1(sc, VGE_RXQCSRS, VGE_RXQCSR_RUN); 1564 CSR_WRITE_1(sc, VGE_RXQCSRS, VGE_RXQCSR_WAK); 1565 1566 /* Enable the TX descriptor queue */ 1567 CSR_WRITE_2(sc, VGE_TXQCSRS, VGE_TXQCSR_RUN0); 1568 1569 /* Set up the receive filter -- allow large frames for VLANs. */ 1570 CSR_WRITE_1(sc, VGE_RXCTL, VGE_RXCTL_RX_GIANT); 1571 1572 /* Program promiscuous mode and multicast filters. */ 1573 vge_iff(sc); 1574 1575 /* Initialize pause timer. */ 1576 CSR_WRITE_2(sc, VGE_TX_PAUSE_TIMER, 0xFFFF); 1577 /* 1578 * Initialize flow control parameters. 1579 * TX XON high threshold : 48 1580 * TX pause low threshold : 24 1581 * Disable half-duplex flow control 1582 */ 1583 CSR_WRITE_1(sc, VGE_CRC2, 0xFF); 1584 CSR_WRITE_1(sc, VGE_CRS2, VGE_CR2_XON_ENABLE | 0x0B); 1585 1586 /* Enable jumbo frame reception (if desired) */ 1587 1588 /* Start the MAC. */ 1589 CSR_WRITE_1(sc, VGE_CRC0, VGE_CR0_STOP); 1590 CSR_WRITE_1(sc, VGE_CRS1, VGE_CR1_NOPOLL); 1591 CSR_WRITE_1(sc, VGE_CRS0, 1592 VGE_CR0_TX_ENABLE|VGE_CR0_RX_ENABLE|VGE_CR0_START); 1593 1594 /* 1595 * Configure one-shot timer for microsecond 1596 * resulution and load it for 500 usecs. 1597 */ 1598 CSR_SETBIT_1(sc, VGE_DIAGCTL, VGE_DIAGCTL_TIMER0_RES); 1599 CSR_WRITE_2(sc, VGE_SSTIMER, 400); 1600 1601 /* 1602 * Configure interrupt moderation for receive. Enable 1603 * the holdoff counter and load it, and set the RX 1604 * suppression count to the number of descriptors we 1605 * want to allow before triggering an interrupt. 1606 * The holdoff timer is in units of 20 usecs. 1607 */ 1608 1609 #ifdef notyet 1610 CSR_WRITE_1(sc, VGE_INTCTL1, VGE_INTCTL_TXINTSUP_DISABLE); 1611 /* Select the interrupt holdoff timer page. */ 1612 CSR_CLRBIT_1(sc, VGE_CAMCTL, VGE_CAMCTL_PAGESEL); 1613 CSR_SETBIT_1(sc, VGE_CAMCTL, VGE_PAGESEL_INTHLDOFF); 1614 CSR_WRITE_1(sc, VGE_INTHOLDOFF, 10); /* ~200 usecs */ 1615 1616 /* Enable use of the holdoff timer. */ 1617 CSR_WRITE_1(sc, VGE_CRS3, VGE_CR3_INT_HOLDOFF); 1618 CSR_WRITE_1(sc, VGE_INTCTL1, VGE_INTCTL_SC_RELOAD); 1619 1620 /* Select the RX suppression threshold page. */ 1621 CSR_CLRBIT_1(sc, VGE_CAMCTL, VGE_CAMCTL_PAGESEL); 1622 CSR_SETBIT_1(sc, VGE_CAMCTL, VGE_PAGESEL_RXSUPPTHR); 1623 CSR_WRITE_1(sc, VGE_RXSUPPTHR, 64); /* interrupt after 64 packets */ 1624 1625 /* Restore the page select bits. */ 1626 CSR_CLRBIT_1(sc, VGE_CAMCTL, VGE_CAMCTL_PAGESEL); 1627 CSR_SETBIT_1(sc, VGE_CAMCTL, VGE_PAGESEL_MAR); 1628 #endif 1629 1630 /* 1631 * Enable interrupts. 1632 */ 1633 CSR_WRITE_4(sc, VGE_IMR, VGE_INTRS); 1634 CSR_WRITE_4(sc, VGE_ISR, 0); 1635 CSR_WRITE_1(sc, VGE_CRS3, VGE_CR3_INT_GMSK); 1636 1637 /* Restore BMCR state */ 1638 mii_mediachg(&sc->sc_mii); 1639 1640 ifp->if_flags |= IFF_RUNNING; 1641 ifq_clr_oactive(&ifp->if_snd); 1642 1643 sc->vge_link = 0; 1644 1645 if (!timeout_pending(&sc->timer_handle)) 1646 timeout_add_sec(&sc->timer_handle, 1); 1647 1648 return (0); 1649 } 1650 1651 /* 1652 * Set media options. 1653 */ 1654 int 1655 vge_ifmedia_upd(struct ifnet *ifp) 1656 { 1657 struct vge_softc *sc = ifp->if_softc; 1658 1659 return (mii_mediachg(&sc->sc_mii)); 1660 } 1661 1662 /* 1663 * Report current media status. 1664 */ 1665 void 1666 vge_ifmedia_sts(struct ifnet *ifp, struct ifmediareq *ifmr) 1667 { 1668 struct vge_softc *sc = ifp->if_softc; 1669 1670 mii_pollstat(&sc->sc_mii); 1671 ifmr->ifm_active = sc->sc_mii.mii_media_active; 1672 ifmr->ifm_status = sc->sc_mii.mii_media_status; 1673 } 1674 1675 void 1676 vge_miibus_statchg(struct device *dev) 1677 { 1678 struct vge_softc *sc = (struct vge_softc *)dev; 1679 struct mii_data *mii; 1680 struct ifmedia_entry *ife; 1681 1682 mii = &sc->sc_mii; 1683 ife = mii->mii_media.ifm_cur; 1684 1685 /* 1686 * If the user manually selects a media mode, we need to turn 1687 * on the forced MAC mode bit in the DIAGCTL register. If the 1688 * user happens to choose a full duplex mode, we also need to 1689 * set the 'force full duplex' bit. This applies only to 1690 * 10Mbps and 100Mbps speeds. In autoselect mode, forced MAC 1691 * mode is disabled, and in 1000baseT mode, full duplex is 1692 * always implied, so we turn on the forced mode bit but leave 1693 * the FDX bit cleared. 1694 */ 1695 1696 switch (IFM_SUBTYPE(ife->ifm_media)) { 1697 case IFM_AUTO: 1698 CSR_CLRBIT_1(sc, VGE_DIAGCTL, VGE_DIAGCTL_MACFORCE); 1699 CSR_CLRBIT_1(sc, VGE_DIAGCTL, VGE_DIAGCTL_FDXFORCE); 1700 break; 1701 case IFM_1000_T: 1702 CSR_SETBIT_1(sc, VGE_DIAGCTL, VGE_DIAGCTL_MACFORCE); 1703 CSR_CLRBIT_1(sc, VGE_DIAGCTL, VGE_DIAGCTL_FDXFORCE); 1704 break; 1705 case IFM_100_TX: 1706 case IFM_10_T: 1707 CSR_SETBIT_1(sc, VGE_DIAGCTL, VGE_DIAGCTL_MACFORCE); 1708 if ((ife->ifm_media & IFM_GMASK) == IFM_FDX) { 1709 CSR_SETBIT_1(sc, VGE_DIAGCTL, VGE_DIAGCTL_FDXFORCE); 1710 } else { 1711 CSR_CLRBIT_1(sc, VGE_DIAGCTL, VGE_DIAGCTL_FDXFORCE); 1712 } 1713 break; 1714 default: 1715 printf("%s: unknown media type: %llx\n", 1716 sc->vge_dev.dv_xname, IFM_SUBTYPE(ife->ifm_media)); 1717 break; 1718 } 1719 1720 /* 1721 * 802.3x flow control 1722 */ 1723 CSR_WRITE_1(sc, VGE_CRC2, VGE_CR2_FDX_TXFLOWCTL_ENABLE | 1724 VGE_CR2_FDX_RXFLOWCTL_ENABLE); 1725 if ((IFM_OPTIONS(mii->mii_media_active) & IFM_ETH_TXPAUSE) != 0) 1726 CSR_WRITE_1(sc, VGE_CRS2, VGE_CR2_FDX_TXFLOWCTL_ENABLE); 1727 if ((IFM_OPTIONS(mii->mii_media_active) & IFM_ETH_RXPAUSE) != 0) 1728 CSR_WRITE_1(sc, VGE_CRS2, VGE_CR2_FDX_RXFLOWCTL_ENABLE); 1729 } 1730 1731 int 1732 vge_ioctl(struct ifnet *ifp, u_long command, caddr_t data) 1733 { 1734 struct vge_softc *sc = ifp->if_softc; 1735 struct ifreq *ifr = (struct ifreq *) data; 1736 int s, error = 0; 1737 1738 s = splnet(); 1739 1740 switch (command) { 1741 case SIOCSIFADDR: 1742 ifp->if_flags |= IFF_UP; 1743 if (!(ifp->if_flags & IFF_RUNNING)) 1744 vge_init(ifp); 1745 break; 1746 1747 case SIOCSIFFLAGS: 1748 if (ifp->if_flags & IFF_UP) { 1749 if (ifp->if_flags & IFF_RUNNING) 1750 error = ENETRESET; 1751 else 1752 vge_init(ifp); 1753 } else { 1754 if (ifp->if_flags & IFF_RUNNING) 1755 vge_stop(sc); 1756 } 1757 break; 1758 1759 case SIOCGIFMEDIA: 1760 case SIOCSIFMEDIA: 1761 error = ifmedia_ioctl(ifp, ifr, &sc->sc_mii.mii_media, command); 1762 break; 1763 1764 default: 1765 error = ether_ioctl(ifp, &sc->arpcom, command, data); 1766 } 1767 1768 if (error == ENETRESET) { 1769 if (ifp->if_flags & IFF_RUNNING) 1770 vge_iff(sc); 1771 error = 0; 1772 } 1773 1774 splx(s); 1775 return (error); 1776 } 1777 1778 void 1779 vge_watchdog(struct ifnet *ifp) 1780 { 1781 struct vge_softc *sc = ifp->if_softc; 1782 int s; 1783 1784 s = splnet(); 1785 printf("%s: watchdog timeout\n", sc->vge_dev.dv_xname); 1786 ifp->if_oerrors++; 1787 1788 vge_txeof(sc); 1789 vge_rxeof(sc); 1790 1791 vge_init(ifp); 1792 1793 splx(s); 1794 } 1795 1796 /* 1797 * Stop the adapter and free any mbufs allocated to the 1798 * RX and TX lists. 1799 */ 1800 void 1801 vge_stop(struct vge_softc *sc) 1802 { 1803 int i; 1804 struct ifnet *ifp; 1805 1806 ifp = &sc->arpcom.ac_if; 1807 ifp->if_timer = 0; 1808 1809 timeout_del(&sc->timer_handle); 1810 1811 ifp->if_flags &= ~IFF_RUNNING; 1812 ifq_clr_oactive(&ifp->if_snd); 1813 1814 CSR_WRITE_1(sc, VGE_CRC3, VGE_CR3_INT_GMSK); 1815 CSR_WRITE_1(sc, VGE_CRS0, VGE_CR0_STOP); 1816 CSR_WRITE_4(sc, VGE_ISR, 0xFFFFFFFF); 1817 CSR_WRITE_2(sc, VGE_TXQCSRC, 0xFFFF); 1818 CSR_WRITE_1(sc, VGE_RXQCSRC, 0xFF); 1819 CSR_WRITE_4(sc, VGE_RXDESC_ADDR_LO, 0); 1820 1821 if (sc->vge_head != NULL) { 1822 m_freem(sc->vge_head); 1823 sc->vge_head = sc->vge_tail = NULL; 1824 } 1825 1826 /* Free the TX list buffers. */ 1827 for (i = 0; i < VGE_TX_DESC_CNT; i++) { 1828 if (sc->vge_ldata.vge_tx_mbuf[i] != NULL) { 1829 bus_dmamap_unload(sc->sc_dmat, 1830 sc->vge_ldata.vge_tx_dmamap[i]); 1831 m_freem(sc->vge_ldata.vge_tx_mbuf[i]); 1832 sc->vge_ldata.vge_tx_mbuf[i] = NULL; 1833 } 1834 } 1835 1836 /* Free the RX list buffers. */ 1837 for (i = 0; i < VGE_RX_DESC_CNT; i++) { 1838 if (sc->vge_ldata.vge_rx_mbuf[i] != NULL) { 1839 bus_dmamap_unload(sc->sc_dmat, 1840 sc->vge_ldata.vge_rx_dmamap[i]); 1841 m_freem(sc->vge_ldata.vge_rx_mbuf[i]); 1842 sc->vge_ldata.vge_rx_mbuf[i] = NULL; 1843 } 1844 } 1845 } 1846