1 /* $OpenBSD: if_txp.c,v 1.125 2017/01/22 10:17:38 dlg Exp $ */ 2 3 /* 4 * Copyright (c) 2001 5 * Jason L. Wright <jason@thought.net>, Theo de Raadt, and 6 * Aaron Campbell <aaron@monkey.org>. All rights reserved. 7 * 8 * Redistribution and use in source and binary forms, with or without 9 * modification, are permitted provided that the following conditions 10 * are met: 11 * 1. Redistributions of source code must retain the above copyright 12 * notice, this list of conditions and the following disclaimer. 13 * 2. Redistributions in binary form must reproduce the above copyright 14 * notice, this list of conditions and the following disclaimer in the 15 * documentation and/or other materials provided with the distribution. 16 * 17 * THIS SOFTWARE IS PROVIDED BY THE AUTHORS ``AS IS'' AND ANY EXPRESS OR 18 * IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED 19 * WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE 20 * ARE DISCLAIMED. IN NO EVENT SHALL THE AUTHORS OR THE VOICES IN THEIR HEADS 21 * BE LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR 22 * CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF 23 * SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS 24 * INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN 25 * CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) 26 * ARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF 27 * THE POSSIBILITY OF SUCH DAMAGE. 28 */ 29 30 /* 31 * Driver for 3c990 (Typhoon) Ethernet ASIC 32 */ 33 34 #include "bpfilter.h" 35 #include "vlan.h" 36 37 #include <sys/param.h> 38 #include <sys/systm.h> 39 #include <sys/sockio.h> 40 #include <sys/mbuf.h> 41 #include <sys/malloc.h> 42 #include <sys/kernel.h> 43 #include <sys/socket.h> 44 #include <sys/device.h> 45 #include <sys/timeout.h> 46 47 #include <net/if.h> 48 49 #include <netinet/in.h> 50 #include <netinet/if_ether.h> 51 52 #include <net/if_media.h> 53 54 #if NBPFILTER > 0 55 #include <net/bpf.h> 56 #endif 57 58 #include <machine/bus.h> 59 60 #include <dev/mii/mii.h> 61 #include <dev/pci/pcireg.h> 62 #include <dev/pci/pcivar.h> 63 #include <dev/pci/pcidevs.h> 64 65 #include <dev/pci/if_txpreg.h> 66 67 /* 68 * These currently break the 3c990 firmware, hopefully will be resolved 69 * at some point. 70 */ 71 #undef TRY_TX_UDP_CSUM 72 #undef TRY_TX_TCP_CSUM 73 74 int txp_probe(struct device *, void *, void *); 75 void txp_attach(struct device *, struct device *, void *); 76 void txp_attachhook(struct device *); 77 int txp_intr(void *); 78 void txp_tick(void *); 79 int txp_ioctl(struct ifnet *, u_long, caddr_t); 80 void txp_start(struct ifnet *); 81 void txp_stop(struct txp_softc *); 82 void txp_init(struct txp_softc *); 83 void txp_watchdog(struct ifnet *); 84 85 int txp_chip_init(struct txp_softc *); 86 int txp_reset_adapter(struct txp_softc *); 87 int txp_download_fw(struct txp_softc *); 88 int txp_download_fw_wait(struct txp_softc *); 89 int txp_download_fw_section(struct txp_softc *, 90 struct txp_fw_section_header *, int, u_char *, size_t); 91 int txp_alloc_rings(struct txp_softc *); 92 void txp_dma_free(struct txp_softc *, struct txp_dma_alloc *); 93 int txp_dma_malloc(struct txp_softc *, bus_size_t, struct txp_dma_alloc *, int); 94 void txp_set_filter(struct txp_softc *); 95 96 int txp_cmd_desc_numfree(struct txp_softc *); 97 int txp_command(struct txp_softc *, u_int16_t, u_int16_t, u_int32_t, 98 u_int32_t, u_int16_t *, u_int32_t *, u_int32_t *, int); 99 int txp_command2(struct txp_softc *, u_int16_t, u_int16_t, 100 u_int32_t, u_int32_t, struct txp_ext_desc *, u_int8_t, 101 struct txp_rsp_desc **, int); 102 int txp_response(struct txp_softc *, u_int32_t, u_int16_t, u_int16_t, 103 struct txp_rsp_desc **); 104 void txp_rsp_fixup(struct txp_softc *, struct txp_rsp_desc *, 105 struct txp_rsp_desc *); 106 void txp_capabilities(struct txp_softc *); 107 108 void txp_ifmedia_sts(struct ifnet *, struct ifmediareq *); 109 int txp_ifmedia_upd(struct ifnet *); 110 void txp_show_descriptor(void *); 111 void txp_tx_reclaim(struct txp_softc *, struct txp_tx_ring *, 112 struct txp_dma_alloc *); 113 void txp_rxbuf_reclaim(struct txp_softc *); 114 void txp_rx_reclaim(struct txp_softc *, struct txp_rx_ring *, 115 struct txp_dma_alloc *); 116 117 struct cfattach txp_ca = { 118 sizeof(struct txp_softc), txp_probe, txp_attach, 119 }; 120 121 struct cfdriver txp_cd = { 122 NULL, "txp", DV_IFNET 123 }; 124 125 const struct pci_matchid txp_devices[] = { 126 { PCI_VENDOR_3COM, PCI_PRODUCT_3COM_3CR990 }, 127 { PCI_VENDOR_3COM, PCI_PRODUCT_3COM_3CR990TX }, 128 { PCI_VENDOR_3COM, PCI_PRODUCT_3COM_3CR990TX95 }, 129 { PCI_VENDOR_3COM, PCI_PRODUCT_3COM_3CR990TX97 }, 130 { PCI_VENDOR_3COM, PCI_PRODUCT_3COM_3CR990SVR95 }, 131 { PCI_VENDOR_3COM, PCI_PRODUCT_3COM_3CR990SVR97 }, 132 { PCI_VENDOR_3COM, PCI_PRODUCT_3COM_3C990BTXM }, 133 { PCI_VENDOR_3COM, PCI_PRODUCT_3COM_3C990BSVR }, 134 { PCI_VENDOR_3COM, PCI_PRODUCT_3COM_3CR990FX }, 135 }; 136 137 int 138 txp_probe(struct device *parent, void *match, void *aux) 139 { 140 return (pci_matchbyid((struct pci_attach_args *)aux, txp_devices, 141 nitems(txp_devices))); 142 } 143 144 void 145 txp_attachhook(struct device *self) 146 { 147 struct txp_softc *sc = (struct txp_softc *)self; 148 struct ifnet *ifp = &sc->sc_arpcom.ac_if; 149 u_int16_t p1; 150 u_int32_t p2; 151 int s; 152 153 s = splnet(); 154 printf("%s: ", sc->sc_dev.dv_xname); 155 156 if (txp_chip_init(sc)) { 157 printf("failed chip init\n"); 158 splx(s); 159 return; 160 } 161 162 if (txp_download_fw(sc)) { 163 splx(s); 164 return; 165 } 166 167 if (txp_alloc_rings(sc)) { 168 splx(s); 169 return; 170 } 171 172 if (txp_command(sc, TXP_CMD_MAX_PKT_SIZE_WRITE, TXP_MAX_PKTLEN, 0, 0, 173 NULL, NULL, NULL, 1)) { 174 splx(s); 175 return; 176 } 177 178 if (txp_command(sc, TXP_CMD_STATION_ADDRESS_READ, 0, 0, 0, 179 &p1, &p2, NULL, 1)) { 180 splx(s); 181 return; 182 } 183 184 p1 = htole16(p1); 185 sc->sc_arpcom.ac_enaddr[0] = ((u_int8_t *)&p1)[1]; 186 sc->sc_arpcom.ac_enaddr[1] = ((u_int8_t *)&p1)[0]; 187 p2 = htole32(p2); 188 sc->sc_arpcom.ac_enaddr[2] = ((u_int8_t *)&p2)[3]; 189 sc->sc_arpcom.ac_enaddr[3] = ((u_int8_t *)&p2)[2]; 190 sc->sc_arpcom.ac_enaddr[4] = ((u_int8_t *)&p2)[1]; 191 sc->sc_arpcom.ac_enaddr[5] = ((u_int8_t *)&p2)[0]; 192 193 printf("address %s\n", ether_sprintf(sc->sc_arpcom.ac_enaddr)); 194 sc->sc_cold = 0; 195 196 ifmedia_init(&sc->sc_ifmedia, 0, txp_ifmedia_upd, txp_ifmedia_sts); 197 ifmedia_add(&sc->sc_ifmedia, IFM_ETHER|IFM_10_T, 0, NULL); 198 ifmedia_add(&sc->sc_ifmedia, IFM_ETHER|IFM_10_T|IFM_HDX, 0, NULL); 199 ifmedia_add(&sc->sc_ifmedia, IFM_ETHER|IFM_10_T|IFM_FDX, 0, NULL); 200 ifmedia_add(&sc->sc_ifmedia, IFM_ETHER|IFM_100_TX, 0, NULL); 201 ifmedia_add(&sc->sc_ifmedia, IFM_ETHER|IFM_100_TX|IFM_HDX, 0, NULL); 202 ifmedia_add(&sc->sc_ifmedia, IFM_ETHER|IFM_100_TX|IFM_FDX, 0, NULL); 203 ifmedia_add(&sc->sc_ifmedia, IFM_ETHER|IFM_AUTO, 0, NULL); 204 205 sc->sc_xcvr = TXP_XCVR_AUTO; 206 txp_command(sc, TXP_CMD_XCVR_SELECT, TXP_XCVR_AUTO, 0, 0, 207 NULL, NULL, NULL, 0); 208 ifmedia_set(&sc->sc_ifmedia, IFM_ETHER|IFM_AUTO); 209 210 ifp->if_softc = sc; 211 ifp->if_flags = IFF_BROADCAST | IFF_SIMPLEX | IFF_MULTICAST; 212 ifp->if_ioctl = txp_ioctl; 213 ifp->if_start = txp_start; 214 ifp->if_watchdog = txp_watchdog; 215 ifp->if_baudrate = IF_Mbps(10); 216 IFQ_SET_MAXLEN(&ifp->if_snd, TX_ENTRIES); 217 bcopy(sc->sc_dev.dv_xname, ifp->if_xname, IFNAMSIZ); 218 219 txp_capabilities(sc); 220 221 timeout_set(&sc->sc_tick, txp_tick, sc); 222 223 /* 224 * Attach us everywhere 225 */ 226 if_attach(ifp); 227 ether_ifattach(ifp); 228 229 splx(s); 230 } 231 232 void 233 txp_attach(struct device *parent, struct device *self, void *aux) 234 { 235 struct txp_softc *sc = (struct txp_softc *)self; 236 struct pci_attach_args *pa = aux; 237 pci_chipset_tag_t pc = pa->pa_pc; 238 pci_intr_handle_t ih; 239 const char *intrstr = NULL; 240 bus_size_t iosize; 241 242 sc->sc_cold = 1; 243 244 if (pci_mapreg_map(pa, TXP_PCI_LOMEM, PCI_MAPREG_TYPE_MEM, 0, 245 &sc->sc_bt, &sc->sc_bh, NULL, &iosize, 0)) { 246 printf(": can't map mem space %d\n", 0); 247 return; 248 } 249 250 sc->sc_dmat = pa->pa_dmat; 251 252 /* 253 * Allocate our interrupt. 254 */ 255 if (pci_intr_map(pa, &ih)) { 256 printf(": couldn't map interrupt\n"); 257 return; 258 } 259 260 intrstr = pci_intr_string(pc, ih); 261 sc->sc_ih = pci_intr_establish(pc, ih, IPL_NET, txp_intr, sc, 262 self->dv_xname); 263 if (sc->sc_ih == NULL) { 264 printf(": couldn't establish interrupt"); 265 if (intrstr != NULL) 266 printf(" at %s", intrstr); 267 printf("\n"); 268 return; 269 } 270 printf(": %s\n", intrstr); 271 272 config_mountroot(self, txp_attachhook); 273 274 } 275 276 int 277 txp_chip_init(struct txp_softc *sc) 278 { 279 /* disable interrupts */ 280 WRITE_REG(sc, TXP_IER, 0); 281 WRITE_REG(sc, TXP_IMR, 282 TXP_INT_SELF | TXP_INT_PCI_TABORT | TXP_INT_PCI_MABORT | 283 TXP_INT_DMA3 | TXP_INT_DMA2 | TXP_INT_DMA1 | TXP_INT_DMA0 | 284 TXP_INT_LATCH); 285 286 /* ack all interrupts */ 287 WRITE_REG(sc, TXP_ISR, TXP_INT_RESERVED | TXP_INT_LATCH | 288 TXP_INT_A2H_7 | TXP_INT_A2H_6 | TXP_INT_A2H_5 | TXP_INT_A2H_4 | 289 TXP_INT_SELF | TXP_INT_PCI_TABORT | TXP_INT_PCI_MABORT | 290 TXP_INT_DMA3 | TXP_INT_DMA2 | TXP_INT_DMA1 | TXP_INT_DMA0 | 291 TXP_INT_A2H_3 | TXP_INT_A2H_2 | TXP_INT_A2H_1 | TXP_INT_A2H_0); 292 293 if (txp_reset_adapter(sc)) 294 return (-1); 295 296 /* disable interrupts */ 297 WRITE_REG(sc, TXP_IER, 0); 298 WRITE_REG(sc, TXP_IMR, 299 TXP_INT_SELF | TXP_INT_PCI_TABORT | TXP_INT_PCI_MABORT | 300 TXP_INT_DMA3 | TXP_INT_DMA2 | TXP_INT_DMA1 | TXP_INT_DMA0 | 301 TXP_INT_LATCH); 302 303 /* ack all interrupts */ 304 WRITE_REG(sc, TXP_ISR, TXP_INT_RESERVED | TXP_INT_LATCH | 305 TXP_INT_A2H_7 | TXP_INT_A2H_6 | TXP_INT_A2H_5 | TXP_INT_A2H_4 | 306 TXP_INT_SELF | TXP_INT_PCI_TABORT | TXP_INT_PCI_MABORT | 307 TXP_INT_DMA3 | TXP_INT_DMA2 | TXP_INT_DMA1 | TXP_INT_DMA0 | 308 TXP_INT_A2H_3 | TXP_INT_A2H_2 | TXP_INT_A2H_1 | TXP_INT_A2H_0); 309 310 return (0); 311 } 312 313 int 314 txp_reset_adapter(struct txp_softc *sc) 315 { 316 u_int32_t r; 317 int i; 318 319 WRITE_REG(sc, TXP_SRR, TXP_SRR_ALL); 320 DELAY(1000); 321 WRITE_REG(sc, TXP_SRR, 0); 322 323 /* Should wait max 6 seconds */ 324 for (i = 0; i < 6000; i++) { 325 r = READ_REG(sc, TXP_A2H_0); 326 if (r == STAT_WAITING_FOR_HOST_REQUEST) 327 break; 328 DELAY(1000); 329 } 330 331 if (r != STAT_WAITING_FOR_HOST_REQUEST) { 332 printf("%s: reset hung\n", TXP_DEVNAME(sc)); 333 return (-1); 334 } 335 336 return (0); 337 } 338 339 int 340 txp_download_fw(struct txp_softc *sc) 341 { 342 struct txp_fw_file_header *fileheader; 343 struct txp_fw_section_header *secthead; 344 u_int32_t r, i, ier, imr; 345 size_t buflen; 346 int sect, err; 347 u_char *buf; 348 349 ier = READ_REG(sc, TXP_IER); 350 WRITE_REG(sc, TXP_IER, ier | TXP_INT_A2H_0); 351 352 imr = READ_REG(sc, TXP_IMR); 353 WRITE_REG(sc, TXP_IMR, imr | TXP_INT_A2H_0); 354 355 for (i = 0; i < 10000; i++) { 356 r = READ_REG(sc, TXP_A2H_0); 357 if (r == STAT_WAITING_FOR_HOST_REQUEST) 358 break; 359 DELAY(50); 360 } 361 if (r != STAT_WAITING_FOR_HOST_REQUEST) { 362 printf("not waiting for host request\n"); 363 return (-1); 364 } 365 366 /* Ack the status */ 367 WRITE_REG(sc, TXP_ISR, TXP_INT_A2H_0); 368 369 err = loadfirmware("3c990", &buf, &buflen); 370 if (err) { 371 printf("failed loadfirmware of file 3c990: errno %d\n", 372 err); 373 return (err); 374 } 375 376 fileheader = (struct txp_fw_file_header *)buf; 377 if (bcmp("TYPHOON", fileheader->magicid, sizeof(fileheader->magicid))) { 378 printf("firmware invalid magic\n"); 379 goto fail; 380 } 381 382 /* Tell boot firmware to get ready for image */ 383 WRITE_REG(sc, TXP_H2A_1, letoh32(fileheader->addr)); 384 WRITE_REG(sc, TXP_H2A_2, letoh32(fileheader->hmac[0])); 385 WRITE_REG(sc, TXP_H2A_3, letoh32(fileheader->hmac[1])); 386 WRITE_REG(sc, TXP_H2A_4, letoh32(fileheader->hmac[2])); 387 WRITE_REG(sc, TXP_H2A_5, letoh32(fileheader->hmac[3])); 388 WRITE_REG(sc, TXP_H2A_6, letoh32(fileheader->hmac[4])); 389 WRITE_REG(sc, TXP_H2A_0, TXP_BOOTCMD_RUNTIME_IMAGE); 390 391 if (txp_download_fw_wait(sc)) { 392 printf("fw wait failed, initial\n"); 393 goto fail; 394 } 395 396 secthead = (struct txp_fw_section_header *)(buf + 397 sizeof(struct txp_fw_file_header)); 398 399 for (sect = 0; sect < letoh32(fileheader->nsections); sect++) { 400 if (txp_download_fw_section(sc, secthead, sect, buf, buflen)) 401 goto fail; 402 secthead = (struct txp_fw_section_header *) 403 (((u_int8_t *)secthead) + letoh32(secthead->nbytes) + 404 sizeof(*secthead)); 405 } 406 407 WRITE_REG(sc, TXP_H2A_0, TXP_BOOTCMD_DOWNLOAD_COMPLETE); 408 409 for (i = 0; i < 10000; i++) { 410 r = READ_REG(sc, TXP_A2H_0); 411 if (r == STAT_WAITING_FOR_BOOT) 412 break; 413 DELAY(50); 414 } 415 if (r != STAT_WAITING_FOR_BOOT) { 416 printf("not waiting for boot\n"); 417 goto fail; 418 } 419 420 WRITE_REG(sc, TXP_IER, ier); 421 WRITE_REG(sc, TXP_IMR, imr); 422 423 free(buf, M_DEVBUF, 0); 424 return (0); 425 fail: 426 free(buf, M_DEVBUF, 0); 427 return (-1); 428 } 429 430 int 431 txp_download_fw_wait(struct txp_softc *sc) 432 { 433 u_int32_t i, r; 434 435 for (i = 0; i < 10000; i++) { 436 r = READ_REG(sc, TXP_ISR); 437 if (r & TXP_INT_A2H_0) 438 break; 439 DELAY(50); 440 } 441 442 if (!(r & TXP_INT_A2H_0)) { 443 printf("fw wait failed comm0\n"); 444 return (-1); 445 } 446 447 WRITE_REG(sc, TXP_ISR, TXP_INT_A2H_0); 448 449 r = READ_REG(sc, TXP_A2H_0); 450 if (r != STAT_WAITING_FOR_SEGMENT) { 451 printf("fw not waiting for segment\n"); 452 return (-1); 453 } 454 return (0); 455 } 456 457 int 458 txp_download_fw_section(struct txp_softc *sc, 459 struct txp_fw_section_header *sect, int sectnum, u_char *buf, 460 size_t buflen) 461 { 462 struct txp_dma_alloc dma; 463 int rseg, err = 0; 464 struct mbuf m; 465 u_int16_t csum; 466 467 /* Skip zero length sections */ 468 if (sect->nbytes == 0) 469 return (0); 470 471 /* Make sure we aren't past the end of the image */ 472 rseg = ((u_int8_t *)sect) - ((u_int8_t *)buf); 473 if (rseg >= buflen) { 474 printf("fw invalid section address, section %d\n", sectnum); 475 return (-1); 476 } 477 478 /* Make sure this section doesn't go past the end */ 479 rseg += letoh32(sect->nbytes); 480 if (rseg >= buflen) { 481 printf("fw truncated section %d\n", sectnum); 482 return (-1); 483 } 484 485 /* map a buffer, copy segment to it, get physaddr */ 486 if (txp_dma_malloc(sc, letoh32(sect->nbytes), &dma, 0)) { 487 printf("fw dma malloc failed, section %d\n", sectnum); 488 return (-1); 489 } 490 491 bcopy(((u_int8_t *)sect) + sizeof(*sect), dma.dma_vaddr, 492 letoh32(sect->nbytes)); 493 494 /* 495 * dummy up mbuf and verify section checksum 496 */ 497 m.m_type = MT_DATA; 498 m.m_next = m.m_nextpkt = NULL; 499 m.m_len = letoh32(sect->nbytes); 500 m.m_data = dma.dma_vaddr; 501 m.m_flags = 0; 502 csum = in_cksum(&m, letoh32(sect->nbytes)); 503 if (csum != sect->cksum) { 504 printf("fw section %d, bad cksum (expected 0x%x got 0x%x)\n", 505 sectnum, sect->cksum, csum); 506 err = -1; 507 goto bail; 508 } 509 510 bus_dmamap_sync(sc->sc_dmat, dma.dma_map, 0, 511 dma.dma_map->dm_mapsize, BUS_DMASYNC_PREWRITE); 512 513 WRITE_REG(sc, TXP_H2A_1, letoh32(sect->nbytes)); 514 WRITE_REG(sc, TXP_H2A_2, letoh16(sect->cksum)); 515 WRITE_REG(sc, TXP_H2A_3, letoh32(sect->addr)); 516 WRITE_REG(sc, TXP_H2A_4, dma.dma_paddr >> 32); 517 WRITE_REG(sc, TXP_H2A_5, dma.dma_paddr & 0xffffffff); 518 WRITE_REG(sc, TXP_H2A_0, TXP_BOOTCMD_SEGMENT_AVAILABLE); 519 520 if (txp_download_fw_wait(sc)) { 521 printf("%s: fw wait failed, section %d\n", 522 sc->sc_dev.dv_xname, sectnum); 523 err = -1; 524 } 525 526 bus_dmamap_sync(sc->sc_dmat, dma.dma_map, 0, 527 dma.dma_map->dm_mapsize, BUS_DMASYNC_POSTWRITE); 528 529 bail: 530 txp_dma_free(sc, &dma); 531 532 return (err); 533 } 534 535 int 536 txp_intr(void *vsc) 537 { 538 struct txp_softc *sc = vsc; 539 struct txp_hostvar *hv = sc->sc_hostvar; 540 u_int32_t isr; 541 int claimed = 0; 542 543 /* mask all interrupts */ 544 WRITE_REG(sc, TXP_IMR, TXP_INT_RESERVED | TXP_INT_SELF | 545 TXP_INT_A2H_7 | TXP_INT_A2H_6 | TXP_INT_A2H_5 | TXP_INT_A2H_4 | 546 TXP_INT_A2H_2 | TXP_INT_A2H_1 | TXP_INT_A2H_0 | 547 TXP_INT_DMA3 | TXP_INT_DMA2 | TXP_INT_DMA1 | TXP_INT_DMA0 | 548 TXP_INT_PCI_TABORT | TXP_INT_PCI_MABORT | TXP_INT_LATCH); 549 550 bus_dmamap_sync(sc->sc_dmat, sc->sc_host_dma.dma_map, 0, 551 sizeof(struct txp_hostvar), BUS_DMASYNC_POSTWRITE|BUS_DMASYNC_POSTREAD); 552 553 isr = READ_REG(sc, TXP_ISR); 554 while (isr) { 555 claimed = 1; 556 WRITE_REG(sc, TXP_ISR, isr); 557 558 if ((*sc->sc_rxhir.r_roff) != (*sc->sc_rxhir.r_woff)) 559 txp_rx_reclaim(sc, &sc->sc_rxhir, &sc->sc_rxhiring_dma); 560 if ((*sc->sc_rxlor.r_roff) != (*sc->sc_rxlor.r_woff)) 561 txp_rx_reclaim(sc, &sc->sc_rxlor, &sc->sc_rxloring_dma); 562 563 if (hv->hv_rx_buf_write_idx == hv->hv_rx_buf_read_idx) 564 txp_rxbuf_reclaim(sc); 565 566 if (sc->sc_txhir.r_cnt && (sc->sc_txhir.r_cons != 567 TXP_OFFSET2IDX(letoh32(*(sc->sc_txhir.r_off))))) 568 txp_tx_reclaim(sc, &sc->sc_txhir, &sc->sc_txhiring_dma); 569 570 if (sc->sc_txlor.r_cnt && (sc->sc_txlor.r_cons != 571 TXP_OFFSET2IDX(letoh32(*(sc->sc_txlor.r_off))))) 572 txp_tx_reclaim(sc, &sc->sc_txlor, &sc->sc_txloring_dma); 573 574 isr = READ_REG(sc, TXP_ISR); 575 } 576 577 bus_dmamap_sync(sc->sc_dmat, sc->sc_host_dma.dma_map, 0, 578 sizeof(struct txp_hostvar), BUS_DMASYNC_POSTWRITE|BUS_DMASYNC_POSTREAD); 579 580 /* unmask all interrupts */ 581 WRITE_REG(sc, TXP_IMR, TXP_INT_A2H_3); 582 583 txp_start(&sc->sc_arpcom.ac_if); 584 585 return (claimed); 586 } 587 588 void 589 txp_rx_reclaim(struct txp_softc *sc, struct txp_rx_ring *r, 590 struct txp_dma_alloc *dma) 591 { 592 struct ifnet *ifp = &sc->sc_arpcom.ac_if; 593 struct txp_rx_desc *rxd; 594 struct mbuf *m; 595 struct mbuf_list ml = MBUF_LIST_INITIALIZER(); 596 struct txp_swdesc *sd; 597 u_int32_t roff, woff; 598 int idx; 599 u_int16_t sumflags = 0; 600 601 roff = letoh32(*r->r_roff); 602 woff = letoh32(*r->r_woff); 603 idx = roff / sizeof(struct txp_rx_desc); 604 rxd = r->r_desc + idx; 605 606 while (roff != woff) { 607 608 bus_dmamap_sync(sc->sc_dmat, dma->dma_map, 609 idx * sizeof(struct txp_rx_desc), sizeof(struct txp_rx_desc), 610 BUS_DMASYNC_POSTREAD); 611 612 if (rxd->rx_flags & RX_FLAGS_ERROR) { 613 printf("%s: error 0x%x\n", sc->sc_dev.dv_xname, 614 letoh32(rxd->rx_stat)); 615 ifp->if_ierrors++; 616 goto next; 617 } 618 619 /* retrieve stashed pointer */ 620 bcopy((u_long *)&rxd->rx_vaddrlo, &sd, sizeof(sd)); 621 622 bus_dmamap_sync(sc->sc_dmat, sd->sd_map, 0, 623 sd->sd_map->dm_mapsize, BUS_DMASYNC_POSTREAD); 624 bus_dmamap_unload(sc->sc_dmat, sd->sd_map); 625 bus_dmamap_destroy(sc->sc_dmat, sd->sd_map); 626 m = sd->sd_mbuf; 627 free(sd, M_DEVBUF, 0); 628 m->m_pkthdr.len = m->m_len = letoh16(rxd->rx_len); 629 630 #ifdef __STRICT_ALIGNMENT 631 { 632 /* 633 * XXX Nice chip, except it won't accept "off by 2" 634 * buffers, so we're force to copy. Supposedly 635 * this will be fixed in a newer firmware rev 636 * and this will be temporary. 637 */ 638 struct mbuf *mnew; 639 640 MGETHDR(mnew, M_DONTWAIT, MT_DATA); 641 if (mnew == NULL) { 642 m_freem(m); 643 goto next; 644 } 645 if (m->m_len > (MHLEN - 2)) { 646 MCLGET(mnew, M_DONTWAIT); 647 if (!(mnew->m_flags & M_EXT)) { 648 m_freem(mnew); 649 m_freem(m); 650 goto next; 651 } 652 } 653 mnew->m_pkthdr.len = mnew->m_len = m->m_len; 654 mnew->m_data += 2; 655 bcopy(m->m_data, mnew->m_data, m->m_len); 656 m_freem(m); 657 m = mnew; 658 } 659 #endif 660 661 #if NVLAN > 0 662 /* 663 * XXX Another firmware bug: the vlan encapsulation 664 * is always removed, even when we tell the card not 665 * to do that. Restore the vlan encapsulation below. 666 */ 667 if (rxd->rx_stat & htole32(RX_STAT_VLAN)) { 668 m->m_pkthdr.ether_vtag = ntohs(rxd->rx_vlan >> 16); 669 m->m_flags |= M_VLANTAG; 670 } 671 #endif 672 673 if (rxd->rx_stat & htole32(RX_STAT_IPCKSUMBAD)) 674 sumflags |= M_IPV4_CSUM_IN_BAD; 675 else if (rxd->rx_stat & htole32(RX_STAT_IPCKSUMGOOD)) 676 sumflags |= M_IPV4_CSUM_IN_OK; 677 678 if (rxd->rx_stat & htole32(RX_STAT_TCPCKSUMBAD)) 679 sumflags |= M_TCP_CSUM_IN_BAD; 680 else if (rxd->rx_stat & htole32(RX_STAT_TCPCKSUMGOOD)) 681 sumflags |= M_TCP_CSUM_IN_OK; 682 683 if (rxd->rx_stat & htole32(RX_STAT_UDPCKSUMBAD)) 684 sumflags |= M_UDP_CSUM_IN_BAD; 685 else if (rxd->rx_stat & htole32(RX_STAT_UDPCKSUMGOOD)) 686 sumflags |= M_UDP_CSUM_IN_OK; 687 688 m->m_pkthdr.csum_flags = sumflags; 689 690 ml_enqueue(&ml, m); 691 692 next: 693 bus_dmamap_sync(sc->sc_dmat, dma->dma_map, 694 idx * sizeof(struct txp_rx_desc), sizeof(struct txp_rx_desc), 695 BUS_DMASYNC_PREREAD); 696 697 roff += sizeof(struct txp_rx_desc); 698 if (roff == (RX_ENTRIES * sizeof(struct txp_rx_desc))) { 699 idx = 0; 700 roff = 0; 701 rxd = r->r_desc; 702 } else { 703 idx++; 704 rxd++; 705 } 706 woff = letoh32(*r->r_woff); 707 } 708 709 if_input(ifp, &ml); 710 711 *r->r_roff = htole32(woff); 712 } 713 714 void 715 txp_rxbuf_reclaim(struct txp_softc *sc) 716 { 717 struct txp_hostvar *hv = sc->sc_hostvar; 718 struct txp_rxbuf_desc *rbd; 719 struct txp_swdesc *sd; 720 u_int32_t i, end; 721 722 end = TXP_OFFSET2IDX(letoh32(hv->hv_rx_buf_read_idx)); 723 i = TXP_OFFSET2IDX(letoh32(hv->hv_rx_buf_write_idx)); 724 725 if (++i == RXBUF_ENTRIES) 726 i = 0; 727 728 rbd = sc->sc_rxbufs + i; 729 730 while (i != end) { 731 sd = (struct txp_swdesc *)malloc(sizeof(struct txp_swdesc), 732 M_DEVBUF, M_NOWAIT); 733 if (sd == NULL) 734 break; 735 736 MGETHDR(sd->sd_mbuf, M_DONTWAIT, MT_DATA); 737 if (sd->sd_mbuf == NULL) 738 goto err_sd; 739 740 MCLGET(sd->sd_mbuf, M_DONTWAIT); 741 if ((sd->sd_mbuf->m_flags & M_EXT) == 0) 742 goto err_mbuf; 743 sd->sd_mbuf->m_pkthdr.len = sd->sd_mbuf->m_len = MCLBYTES; 744 if (bus_dmamap_create(sc->sc_dmat, TXP_MAX_PKTLEN, 1, 745 TXP_MAX_PKTLEN, 0, BUS_DMA_NOWAIT, &sd->sd_map)) 746 goto err_mbuf; 747 if (bus_dmamap_load_mbuf(sc->sc_dmat, sd->sd_map, sd->sd_mbuf, 748 BUS_DMA_NOWAIT)) { 749 bus_dmamap_destroy(sc->sc_dmat, sd->sd_map); 750 goto err_mbuf; 751 } 752 753 bus_dmamap_sync(sc->sc_dmat, sc->sc_rxbufring_dma.dma_map, 754 i * sizeof(struct txp_rxbuf_desc), 755 sizeof(struct txp_rxbuf_desc), BUS_DMASYNC_POSTWRITE); 756 757 /* stash away pointer */ 758 bcopy(&sd, (u_long *)&rbd->rb_vaddrlo, sizeof(sd)); 759 760 rbd->rb_paddrlo = ((u_int64_t)sd->sd_map->dm_segs[0].ds_addr) 761 & 0xffffffff; 762 rbd->rb_paddrhi = ((u_int64_t)sd->sd_map->dm_segs[0].ds_addr) 763 >> 32; 764 765 bus_dmamap_sync(sc->sc_dmat, sd->sd_map, 0, 766 sd->sd_map->dm_mapsize, BUS_DMASYNC_PREREAD); 767 768 bus_dmamap_sync(sc->sc_dmat, sc->sc_rxbufring_dma.dma_map, 769 i * sizeof(struct txp_rxbuf_desc), 770 sizeof(struct txp_rxbuf_desc), BUS_DMASYNC_PREWRITE); 771 772 hv->hv_rx_buf_write_idx = htole32(TXP_IDX2OFFSET(i)); 773 774 if (++i == RXBUF_ENTRIES) { 775 i = 0; 776 rbd = sc->sc_rxbufs; 777 } else 778 rbd++; 779 } 780 return; 781 782 err_mbuf: 783 m_freem(sd->sd_mbuf); 784 err_sd: 785 free(sd, M_DEVBUF, 0); 786 } 787 788 /* 789 * Reclaim mbufs and entries from a transmit ring. 790 */ 791 void 792 txp_tx_reclaim(struct txp_softc *sc, struct txp_tx_ring *r, 793 struct txp_dma_alloc *dma) 794 { 795 struct ifnet *ifp = &sc->sc_arpcom.ac_if; 796 u_int32_t idx = TXP_OFFSET2IDX(letoh32(*(r->r_off))); 797 u_int32_t cons = r->r_cons, cnt = r->r_cnt; 798 struct txp_tx_desc *txd = r->r_desc + cons; 799 struct txp_swdesc *sd = sc->sc_txd + cons; 800 struct mbuf *m; 801 802 while (cons != idx) { 803 if (cnt == 0) 804 break; 805 806 bus_dmamap_sync(sc->sc_dmat, dma->dma_map, 807 cons * sizeof(struct txp_tx_desc), 808 sizeof(struct txp_tx_desc), 809 BUS_DMASYNC_POSTWRITE); 810 811 if ((txd->tx_flags & TX_FLAGS_TYPE_M) == 812 TX_FLAGS_TYPE_DATA) { 813 bus_dmamap_sync(sc->sc_dmat, sd->sd_map, 0, 814 sd->sd_map->dm_mapsize, BUS_DMASYNC_POSTWRITE); 815 bus_dmamap_unload(sc->sc_dmat, sd->sd_map); 816 m = sd->sd_mbuf; 817 if (m != NULL) { 818 m_freem(m); 819 txd->tx_addrlo = 0; 820 txd->tx_addrhi = 0; 821 } 822 } 823 ifq_clr_oactive(&ifp->if_snd); 824 825 if (++cons == TX_ENTRIES) { 826 txd = r->r_desc; 827 cons = 0; 828 sd = sc->sc_txd; 829 } else { 830 txd++; 831 sd++; 832 } 833 834 cnt--; 835 } 836 837 r->r_cons = cons; 838 r->r_cnt = cnt; 839 if (cnt == 0) 840 ifp->if_timer = 0; 841 } 842 843 int 844 txp_alloc_rings(struct txp_softc *sc) 845 { 846 struct txp_boot_record *boot; 847 struct txp_swdesc *sd; 848 u_int32_t r; 849 int i, j; 850 851 /* boot record */ 852 if (txp_dma_malloc(sc, sizeof(struct txp_boot_record), &sc->sc_boot_dma, 853 BUS_DMA_COHERENT)) { 854 printf("can't allocate boot record\n"); 855 return (-1); 856 } 857 boot = (struct txp_boot_record *)sc->sc_boot_dma.dma_vaddr; 858 bzero(boot, sizeof(*boot)); 859 sc->sc_boot = boot; 860 861 /* host variables */ 862 if (txp_dma_malloc(sc, sizeof(struct txp_hostvar), &sc->sc_host_dma, 863 BUS_DMA_COHERENT)) { 864 printf("can't allocate host ring\n"); 865 goto bail_boot; 866 } 867 bzero(sc->sc_host_dma.dma_vaddr, sizeof(struct txp_hostvar)); 868 boot->br_hostvar_lo = htole32(sc->sc_host_dma.dma_paddr & 0xffffffff); 869 boot->br_hostvar_hi = htole32(sc->sc_host_dma.dma_paddr >> 32); 870 sc->sc_hostvar = (struct txp_hostvar *)sc->sc_host_dma.dma_vaddr; 871 872 /* high priority tx ring */ 873 if (txp_dma_malloc(sc, sizeof(struct txp_tx_desc) * TX_ENTRIES, 874 &sc->sc_txhiring_dma, BUS_DMA_COHERENT)) { 875 printf("can't allocate high tx ring\n"); 876 goto bail_host; 877 } 878 bzero(sc->sc_txhiring_dma.dma_vaddr, sizeof(struct txp_tx_desc) * TX_ENTRIES); 879 boot->br_txhipri_lo = htole32(sc->sc_txhiring_dma.dma_paddr & 0xffffffff); 880 boot->br_txhipri_hi = htole32(sc->sc_txhiring_dma.dma_paddr >> 32); 881 boot->br_txhipri_siz = htole32(TX_ENTRIES * sizeof(struct txp_tx_desc)); 882 sc->sc_txhir.r_reg = TXP_H2A_1; 883 sc->sc_txhir.r_desc = (struct txp_tx_desc *)sc->sc_txhiring_dma.dma_vaddr; 884 sc->sc_txhir.r_cons = sc->sc_txhir.r_prod = sc->sc_txhir.r_cnt = 0; 885 sc->sc_txhir.r_off = &sc->sc_hostvar->hv_tx_hi_desc_read_idx; 886 for (i = 0; i < TX_ENTRIES; i++) { 887 if (bus_dmamap_create(sc->sc_dmat, TXP_MAX_PKTLEN, 888 TX_ENTRIES - 4, TXP_MAX_SEGLEN, 0, 889 BUS_DMA_NOWAIT, &sc->sc_txd[i].sd_map) != 0) { 890 for (j = 0; j < i; j++) { 891 bus_dmamap_destroy(sc->sc_dmat, 892 sc->sc_txd[j].sd_map); 893 sc->sc_txd[j].sd_map = NULL; 894 } 895 goto bail_txhiring; 896 } 897 } 898 899 /* low priority tx ring */ 900 if (txp_dma_malloc(sc, sizeof(struct txp_tx_desc) * TX_ENTRIES, 901 &sc->sc_txloring_dma, BUS_DMA_COHERENT)) { 902 printf("can't allocate low tx ring\n"); 903 goto bail_txhiring; 904 } 905 bzero(sc->sc_txloring_dma.dma_vaddr, sizeof(struct txp_tx_desc) * TX_ENTRIES); 906 boot->br_txlopri_lo = htole32(sc->sc_txloring_dma.dma_paddr & 0xffffffff); 907 boot->br_txlopri_hi = htole32(sc->sc_txloring_dma.dma_paddr >> 32); 908 boot->br_txlopri_siz = htole32(TX_ENTRIES * sizeof(struct txp_tx_desc)); 909 sc->sc_txlor.r_reg = TXP_H2A_3; 910 sc->sc_txlor.r_desc = (struct txp_tx_desc *)sc->sc_txloring_dma.dma_vaddr; 911 sc->sc_txlor.r_cons = sc->sc_txlor.r_prod = sc->sc_txlor.r_cnt = 0; 912 sc->sc_txlor.r_off = &sc->sc_hostvar->hv_tx_lo_desc_read_idx; 913 914 /* high priority rx ring */ 915 if (txp_dma_malloc(sc, sizeof(struct txp_rx_desc) * RX_ENTRIES, 916 &sc->sc_rxhiring_dma, BUS_DMA_COHERENT)) { 917 printf("can't allocate high rx ring\n"); 918 goto bail_txloring; 919 } 920 bzero(sc->sc_rxhiring_dma.dma_vaddr, sizeof(struct txp_rx_desc) * RX_ENTRIES); 921 boot->br_rxhipri_lo = htole32(sc->sc_rxhiring_dma.dma_paddr & 0xffffffff); 922 boot->br_rxhipri_hi = htole32(sc->sc_rxhiring_dma.dma_paddr >> 32); 923 boot->br_rxhipri_siz = htole32(RX_ENTRIES * sizeof(struct txp_rx_desc)); 924 sc->sc_rxhir.r_desc = 925 (struct txp_rx_desc *)sc->sc_rxhiring_dma.dma_vaddr; 926 sc->sc_rxhir.r_roff = &sc->sc_hostvar->hv_rx_hi_read_idx; 927 sc->sc_rxhir.r_woff = &sc->sc_hostvar->hv_rx_hi_write_idx; 928 bus_dmamap_sync(sc->sc_dmat, sc->sc_rxhiring_dma.dma_map, 929 0, sc->sc_rxhiring_dma.dma_map->dm_mapsize, BUS_DMASYNC_PREREAD); 930 931 /* low priority ring */ 932 if (txp_dma_malloc(sc, sizeof(struct txp_rx_desc) * RX_ENTRIES, 933 &sc->sc_rxloring_dma, BUS_DMA_COHERENT)) { 934 printf("can't allocate low rx ring\n"); 935 goto bail_rxhiring; 936 } 937 bzero(sc->sc_rxloring_dma.dma_vaddr, sizeof(struct txp_rx_desc) * RX_ENTRIES); 938 boot->br_rxlopri_lo = htole32(sc->sc_rxloring_dma.dma_paddr & 0xffffffff); 939 boot->br_rxlopri_hi = htole32(sc->sc_rxloring_dma.dma_paddr >> 32); 940 boot->br_rxlopri_siz = htole32(RX_ENTRIES * sizeof(struct txp_rx_desc)); 941 sc->sc_rxlor.r_desc = 942 (struct txp_rx_desc *)sc->sc_rxloring_dma.dma_vaddr; 943 sc->sc_rxlor.r_roff = &sc->sc_hostvar->hv_rx_lo_read_idx; 944 sc->sc_rxlor.r_woff = &sc->sc_hostvar->hv_rx_lo_write_idx; 945 bus_dmamap_sync(sc->sc_dmat, sc->sc_rxloring_dma.dma_map, 946 0, sc->sc_rxloring_dma.dma_map->dm_mapsize, BUS_DMASYNC_PREREAD); 947 948 /* command ring */ 949 if (txp_dma_malloc(sc, sizeof(struct txp_cmd_desc) * CMD_ENTRIES, 950 &sc->sc_cmdring_dma, BUS_DMA_COHERENT)) { 951 printf("can't allocate command ring\n"); 952 goto bail_rxloring; 953 } 954 bzero(sc->sc_cmdring_dma.dma_vaddr, sizeof(struct txp_cmd_desc) * CMD_ENTRIES); 955 boot->br_cmd_lo = htole32(sc->sc_cmdring_dma.dma_paddr & 0xffffffff); 956 boot->br_cmd_hi = htole32(sc->sc_cmdring_dma.dma_paddr >> 32); 957 boot->br_cmd_siz = htole32(CMD_ENTRIES * sizeof(struct txp_cmd_desc)); 958 sc->sc_cmdring.base = (struct txp_cmd_desc *)sc->sc_cmdring_dma.dma_vaddr; 959 sc->sc_cmdring.size = CMD_ENTRIES * sizeof(struct txp_cmd_desc); 960 sc->sc_cmdring.lastwrite = 0; 961 962 /* response ring */ 963 if (txp_dma_malloc(sc, sizeof(struct txp_rsp_desc) * RSP_ENTRIES, 964 &sc->sc_rspring_dma, BUS_DMA_COHERENT)) { 965 printf("can't allocate response ring\n"); 966 goto bail_cmdring; 967 } 968 bzero(sc->sc_rspring_dma.dma_vaddr, sizeof(struct txp_rsp_desc) * RSP_ENTRIES); 969 boot->br_resp_lo = htole32(sc->sc_rspring_dma.dma_paddr & 0xffffffff); 970 boot->br_resp_hi = htole32(sc->sc_rspring_dma.dma_paddr >> 32); 971 boot->br_resp_siz = htole32(CMD_ENTRIES * sizeof(struct txp_rsp_desc)); 972 sc->sc_rspring.base = (struct txp_rsp_desc *)sc->sc_rspring_dma.dma_vaddr; 973 sc->sc_rspring.size = RSP_ENTRIES * sizeof(struct txp_rsp_desc); 974 sc->sc_rspring.lastwrite = 0; 975 976 /* receive buffer ring */ 977 if (txp_dma_malloc(sc, sizeof(struct txp_rxbuf_desc) * RXBUF_ENTRIES, 978 &sc->sc_rxbufring_dma, BUS_DMA_COHERENT)) { 979 printf("can't allocate rx buffer ring\n"); 980 goto bail_rspring; 981 } 982 bzero(sc->sc_rxbufring_dma.dma_vaddr, sizeof(struct txp_rxbuf_desc) * RXBUF_ENTRIES); 983 boot->br_rxbuf_lo = htole32(sc->sc_rxbufring_dma.dma_paddr & 0xffffffff); 984 boot->br_rxbuf_hi = htole32(sc->sc_rxbufring_dma.dma_paddr >> 32); 985 boot->br_rxbuf_siz = htole32(RXBUF_ENTRIES * sizeof(struct txp_rxbuf_desc)); 986 sc->sc_rxbufs = (struct txp_rxbuf_desc *)sc->sc_rxbufring_dma.dma_vaddr; 987 for (i = 0; i < RXBUF_ENTRIES; i++) { 988 sd = (struct txp_swdesc *)malloc(sizeof(struct txp_swdesc), 989 M_DEVBUF, M_NOWAIT); 990 991 /* stash away pointer */ 992 bcopy(&sd, (u_long *)&sc->sc_rxbufs[i].rb_vaddrlo, sizeof(sd)); 993 994 if (sd == NULL) 995 break; 996 997 MGETHDR(sd->sd_mbuf, M_DONTWAIT, MT_DATA); 998 if (sd->sd_mbuf == NULL) { 999 goto bail_rxbufring; 1000 } 1001 1002 MCLGET(sd->sd_mbuf, M_DONTWAIT); 1003 if ((sd->sd_mbuf->m_flags & M_EXT) == 0) { 1004 goto bail_rxbufring; 1005 } 1006 sd->sd_mbuf->m_pkthdr.len = sd->sd_mbuf->m_len = MCLBYTES; 1007 if (bus_dmamap_create(sc->sc_dmat, TXP_MAX_PKTLEN, 1, 1008 TXP_MAX_PKTLEN, 0, BUS_DMA_NOWAIT, &sd->sd_map)) { 1009 goto bail_rxbufring; 1010 } 1011 if (bus_dmamap_load_mbuf(sc->sc_dmat, sd->sd_map, sd->sd_mbuf, 1012 BUS_DMA_NOWAIT)) { 1013 bus_dmamap_destroy(sc->sc_dmat, sd->sd_map); 1014 goto bail_rxbufring; 1015 } 1016 bus_dmamap_sync(sc->sc_dmat, sd->sd_map, 0, 1017 sd->sd_map->dm_mapsize, BUS_DMASYNC_PREREAD); 1018 1019 sc->sc_rxbufs[i].rb_paddrlo = 1020 ((u_int64_t)sd->sd_map->dm_segs[0].ds_addr) & 0xffffffff; 1021 sc->sc_rxbufs[i].rb_paddrhi = 1022 ((u_int64_t)sd->sd_map->dm_segs[0].ds_addr) >> 32; 1023 } 1024 bus_dmamap_sync(sc->sc_dmat, sc->sc_rxbufring_dma.dma_map, 1025 0, sc->sc_rxbufring_dma.dma_map->dm_mapsize, 1026 BUS_DMASYNC_PREWRITE); 1027 sc->sc_hostvar->hv_rx_buf_write_idx = htole32((RXBUF_ENTRIES - 1) * 1028 sizeof(struct txp_rxbuf_desc)); 1029 1030 /* zero dma */ 1031 if (txp_dma_malloc(sc, sizeof(u_int32_t), &sc->sc_zero_dma, 1032 BUS_DMA_COHERENT)) { 1033 printf("can't allocate response ring\n"); 1034 goto bail_rxbufring; 1035 } 1036 bzero(sc->sc_zero_dma.dma_vaddr, sizeof(u_int32_t)); 1037 boot->br_zero_lo = htole32(sc->sc_zero_dma.dma_paddr & 0xffffffff); 1038 boot->br_zero_hi = htole32(sc->sc_zero_dma.dma_paddr >> 32); 1039 1040 /* See if it's waiting for boot, and try to boot it */ 1041 for (i = 0; i < 10000; i++) { 1042 r = READ_REG(sc, TXP_A2H_0); 1043 if (r == STAT_WAITING_FOR_BOOT) 1044 break; 1045 DELAY(50); 1046 } 1047 if (r != STAT_WAITING_FOR_BOOT) { 1048 printf("not waiting for boot\n"); 1049 goto bail; 1050 } 1051 WRITE_REG(sc, TXP_H2A_2, sc->sc_boot_dma.dma_paddr >> 32); 1052 WRITE_REG(sc, TXP_H2A_1, sc->sc_boot_dma.dma_paddr & 0xffffffff); 1053 WRITE_REG(sc, TXP_H2A_0, TXP_BOOTCMD_REGISTER_BOOT_RECORD); 1054 1055 /* See if it booted */ 1056 for (i = 0; i < 10000; i++) { 1057 r = READ_REG(sc, TXP_A2H_0); 1058 if (r == STAT_RUNNING) 1059 break; 1060 DELAY(50); 1061 } 1062 if (r != STAT_RUNNING) { 1063 printf("fw not running\n"); 1064 goto bail; 1065 } 1066 1067 /* Clear TX and CMD ring write registers */ 1068 WRITE_REG(sc, TXP_H2A_1, TXP_BOOTCMD_NULL); 1069 WRITE_REG(sc, TXP_H2A_2, TXP_BOOTCMD_NULL); 1070 WRITE_REG(sc, TXP_H2A_3, TXP_BOOTCMD_NULL); 1071 WRITE_REG(sc, TXP_H2A_0, TXP_BOOTCMD_NULL); 1072 1073 return (0); 1074 1075 bail: 1076 txp_dma_free(sc, &sc->sc_zero_dma); 1077 bail_rxbufring: 1078 for (i = 0; i < RXBUF_ENTRIES; i++) { 1079 bcopy((u_long *)&sc->sc_rxbufs[i].rb_vaddrlo, &sd, sizeof(sd)); 1080 if (sd) 1081 free(sd, M_DEVBUF, 0); 1082 } 1083 txp_dma_free(sc, &sc->sc_rxbufring_dma); 1084 bail_rspring: 1085 txp_dma_free(sc, &sc->sc_rspring_dma); 1086 bail_cmdring: 1087 txp_dma_free(sc, &sc->sc_cmdring_dma); 1088 bail_rxloring: 1089 txp_dma_free(sc, &sc->sc_rxloring_dma); 1090 bail_rxhiring: 1091 txp_dma_free(sc, &sc->sc_rxhiring_dma); 1092 bail_txloring: 1093 txp_dma_free(sc, &sc->sc_txloring_dma); 1094 bail_txhiring: 1095 txp_dma_free(sc, &sc->sc_txhiring_dma); 1096 bail_host: 1097 txp_dma_free(sc, &sc->sc_host_dma); 1098 bail_boot: 1099 txp_dma_free(sc, &sc->sc_boot_dma); 1100 return (-1); 1101 } 1102 1103 int 1104 txp_dma_malloc(struct txp_softc *sc, bus_size_t size, 1105 struct txp_dma_alloc *dma, int mapflags) 1106 { 1107 int r; 1108 1109 if ((r = bus_dmamem_alloc(sc->sc_dmat, size, PAGE_SIZE, 0, 1110 &dma->dma_seg, 1, &dma->dma_nseg, 0)) != 0) 1111 goto fail_0; 1112 1113 if ((r = bus_dmamem_map(sc->sc_dmat, &dma->dma_seg, dma->dma_nseg, 1114 size, &dma->dma_vaddr, mapflags | BUS_DMA_NOWAIT)) != 0) 1115 goto fail_1; 1116 1117 if ((r = bus_dmamap_create(sc->sc_dmat, size, 1, size, 0, 1118 BUS_DMA_NOWAIT, &dma->dma_map)) != 0) 1119 goto fail_2; 1120 1121 if ((r = bus_dmamap_load(sc->sc_dmat, dma->dma_map, dma->dma_vaddr, 1122 size, NULL, BUS_DMA_NOWAIT)) != 0) 1123 goto fail_3; 1124 1125 dma->dma_paddr = dma->dma_map->dm_segs[0].ds_addr; 1126 return (0); 1127 1128 fail_3: 1129 bus_dmamap_destroy(sc->sc_dmat, dma->dma_map); 1130 fail_2: 1131 bus_dmamem_unmap(sc->sc_dmat, dma->dma_vaddr, size); 1132 fail_1: 1133 bus_dmamem_free(sc->sc_dmat, &dma->dma_seg, dma->dma_nseg); 1134 fail_0: 1135 return (r); 1136 } 1137 1138 void 1139 txp_dma_free(struct txp_softc *sc, struct txp_dma_alloc *dma) 1140 { 1141 bus_dmamap_unload(sc->sc_dmat, dma->dma_map); 1142 bus_dmamem_unmap(sc->sc_dmat, dma->dma_vaddr, dma->dma_map->dm_mapsize); 1143 bus_dmamem_free(sc->sc_dmat, &dma->dma_seg, dma->dma_nseg); 1144 bus_dmamap_destroy(sc->sc_dmat, dma->dma_map); 1145 } 1146 1147 int 1148 txp_ioctl(struct ifnet *ifp, u_long command, caddr_t data) 1149 { 1150 struct txp_softc *sc = ifp->if_softc; 1151 struct ifreq *ifr = (struct ifreq *) data; 1152 int s, error = 0; 1153 1154 s = splnet(); 1155 1156 switch(command) { 1157 case SIOCSIFADDR: 1158 ifp->if_flags |= IFF_UP; 1159 txp_init(sc); 1160 break; 1161 1162 case SIOCSIFFLAGS: 1163 if (ifp->if_flags & IFF_UP) { 1164 txp_init(sc); 1165 } else { 1166 if (ifp->if_flags & IFF_RUNNING) 1167 txp_stop(sc); 1168 } 1169 break; 1170 1171 case SIOCGIFMEDIA: 1172 case SIOCSIFMEDIA: 1173 error = ifmedia_ioctl(ifp, ifr, &sc->sc_ifmedia, command); 1174 break; 1175 1176 default: 1177 error = ether_ioctl(ifp, &sc->sc_arpcom, command, data); 1178 } 1179 1180 if (error == ENETRESET) { 1181 if (ifp->if_flags & IFF_RUNNING) 1182 txp_set_filter(sc); 1183 error = 0; 1184 } 1185 1186 splx(s); 1187 return(error); 1188 } 1189 1190 void 1191 txp_init(struct txp_softc *sc) 1192 { 1193 struct ifnet *ifp = &sc->sc_arpcom.ac_if; 1194 int s; 1195 1196 txp_stop(sc); 1197 1198 s = splnet(); 1199 1200 txp_set_filter(sc); 1201 1202 txp_command(sc, TXP_CMD_TX_ENABLE, 0, 0, 0, NULL, NULL, NULL, 1); 1203 txp_command(sc, TXP_CMD_RX_ENABLE, 0, 0, 0, NULL, NULL, NULL, 1); 1204 1205 WRITE_REG(sc, TXP_IER, TXP_INT_RESERVED | TXP_INT_SELF | 1206 TXP_INT_A2H_7 | TXP_INT_A2H_6 | TXP_INT_A2H_5 | TXP_INT_A2H_4 | 1207 TXP_INT_A2H_2 | TXP_INT_A2H_1 | TXP_INT_A2H_0 | 1208 TXP_INT_DMA3 | TXP_INT_DMA2 | TXP_INT_DMA1 | TXP_INT_DMA0 | 1209 TXP_INT_PCI_TABORT | TXP_INT_PCI_MABORT | TXP_INT_LATCH); 1210 WRITE_REG(sc, TXP_IMR, TXP_INT_A2H_3); 1211 1212 ifp->if_flags |= IFF_RUNNING; 1213 ifq_clr_oactive(&ifp->if_snd); 1214 1215 if (!timeout_pending(&sc->sc_tick)) 1216 timeout_add_sec(&sc->sc_tick, 1); 1217 1218 splx(s); 1219 } 1220 1221 void 1222 txp_tick(void *vsc) 1223 { 1224 struct txp_softc *sc = vsc; 1225 struct ifnet *ifp = &sc->sc_arpcom.ac_if; 1226 struct txp_rsp_desc *rsp = NULL; 1227 struct txp_ext_desc *ext; 1228 int s; 1229 1230 s = splnet(); 1231 txp_rxbuf_reclaim(sc); 1232 1233 if (txp_command2(sc, TXP_CMD_READ_STATISTICS, 0, 0, 0, NULL, 0, 1234 &rsp, 1)) 1235 goto out; 1236 if (rsp->rsp_numdesc != 6) 1237 goto out; 1238 if (txp_command(sc, TXP_CMD_CLEAR_STATISTICS, 0, 0, 0, 1239 NULL, NULL, NULL, 1)) 1240 goto out; 1241 ext = (struct txp_ext_desc *)(rsp + 1); 1242 1243 ifp->if_ierrors += ext[3].ext_2 + ext[3].ext_3 + ext[3].ext_4 + 1244 ext[4].ext_1 + ext[4].ext_4; 1245 ifp->if_oerrors += ext[0].ext_1 + ext[1].ext_1 + ext[1].ext_4 + 1246 ext[2].ext_1; 1247 ifp->if_collisions += ext[0].ext_2 + ext[0].ext_3 + ext[1].ext_2 + 1248 ext[1].ext_3; 1249 1250 out: 1251 if (rsp != NULL) 1252 free(rsp, M_DEVBUF, 0); 1253 1254 splx(s); 1255 timeout_add_sec(&sc->sc_tick, 1); 1256 } 1257 1258 void 1259 txp_start(struct ifnet *ifp) 1260 { 1261 struct txp_softc *sc = ifp->if_softc; 1262 struct txp_tx_ring *r = &sc->sc_txhir; 1263 struct txp_tx_desc *txd; 1264 int txdidx; 1265 struct txp_frag_desc *fxd; 1266 struct mbuf *m, *mnew; 1267 struct txp_swdesc *sd; 1268 u_int32_t firstprod, firstcnt, prod, cnt, i; 1269 1270 if (!(ifp->if_flags & IFF_RUNNING) || ifq_is_oactive(&ifp->if_snd)) 1271 return; 1272 1273 prod = r->r_prod; 1274 cnt = r->r_cnt; 1275 1276 while (1) { 1277 m = ifq_deq_begin(&ifp->if_snd); 1278 if (m == NULL) 1279 break; 1280 mnew = NULL; 1281 1282 firstprod = prod; 1283 firstcnt = cnt; 1284 1285 sd = sc->sc_txd + prod; 1286 sd->sd_mbuf = m; 1287 1288 if (bus_dmamap_load_mbuf(sc->sc_dmat, sd->sd_map, m, 1289 BUS_DMA_NOWAIT)) { 1290 MGETHDR(mnew, M_DONTWAIT, MT_DATA); 1291 if (mnew == NULL) 1292 goto oactive1; 1293 if (m->m_pkthdr.len > MHLEN) { 1294 MCLGET(mnew, M_DONTWAIT); 1295 if ((mnew->m_flags & M_EXT) == 0) { 1296 m_freem(mnew); 1297 goto oactive1; 1298 } 1299 } 1300 m_copydata(m, 0, m->m_pkthdr.len, mtod(mnew, caddr_t)); 1301 mnew->m_pkthdr.len = mnew->m_len = m->m_pkthdr.len; 1302 ifq_deq_commit(&ifp->if_snd, m); 1303 m_freem(m); 1304 m = mnew; 1305 if (bus_dmamap_load_mbuf(sc->sc_dmat, sd->sd_map, m, 1306 BUS_DMA_NOWAIT)) 1307 goto oactive1; 1308 } 1309 1310 if ((TX_ENTRIES - cnt) < 4) 1311 goto oactive; 1312 1313 txd = r->r_desc + prod; 1314 txdidx = prod; 1315 txd->tx_flags = TX_FLAGS_TYPE_DATA; 1316 txd->tx_numdesc = 0; 1317 txd->tx_addrlo = 0; 1318 txd->tx_addrhi = 0; 1319 txd->tx_totlen = m->m_pkthdr.len; 1320 txd->tx_pflags = 0; 1321 txd->tx_numdesc = sd->sd_map->dm_nsegs; 1322 1323 if (++prod == TX_ENTRIES) 1324 prod = 0; 1325 1326 if (++cnt >= (TX_ENTRIES - 4)) 1327 goto oactive; 1328 1329 #if NVLAN > 0 1330 if (m->m_flags & M_VLANTAG) { 1331 txd->tx_pflags = TX_PFLAGS_VLAN | 1332 (htons(m->m_pkthdr.ether_vtag) << TX_PFLAGS_VLANTAG_S); 1333 } 1334 #endif 1335 1336 if (m->m_pkthdr.csum_flags & M_IPV4_CSUM_OUT) 1337 txd->tx_pflags |= TX_PFLAGS_IPCKSUM; 1338 #ifdef TRY_TX_TCP_CSUM 1339 if (m->m_pkthdr.csum_flags & M_TCP_CSUM_OUT) 1340 txd->tx_pflags |= TX_PFLAGS_TCPCKSUM; 1341 #endif 1342 #ifdef TRY_TX_UDP_CSUM 1343 if (m->m_pkthdr.csum_flags & M_UDP_CSUM_OUT) 1344 txd->tx_pflags |= TX_PFLAGS_UDPCKSUM; 1345 #endif 1346 1347 bus_dmamap_sync(sc->sc_dmat, sd->sd_map, 0, 1348 sd->sd_map->dm_mapsize, BUS_DMASYNC_PREWRITE); 1349 1350 fxd = (struct txp_frag_desc *)(r->r_desc + prod); 1351 for (i = 0; i < sd->sd_map->dm_nsegs; i++) { 1352 if (++cnt >= (TX_ENTRIES - 4)) { 1353 bus_dmamap_sync(sc->sc_dmat, sd->sd_map, 1354 0, sd->sd_map->dm_mapsize, 1355 BUS_DMASYNC_POSTWRITE); 1356 goto oactive; 1357 } 1358 1359 fxd->frag_flags = FRAG_FLAGS_TYPE_FRAG | 1360 FRAG_FLAGS_VALID; 1361 fxd->frag_rsvd1 = 0; 1362 fxd->frag_len = sd->sd_map->dm_segs[i].ds_len; 1363 fxd->frag_addrlo = 1364 ((u_int64_t)sd->sd_map->dm_segs[i].ds_addr) & 1365 0xffffffff; 1366 fxd->frag_addrhi = 1367 ((u_int64_t)sd->sd_map->dm_segs[i].ds_addr) >> 1368 32; 1369 fxd->frag_rsvd2 = 0; 1370 1371 bus_dmamap_sync(sc->sc_dmat, 1372 sc->sc_txhiring_dma.dma_map, 1373 prod * sizeof(struct txp_frag_desc), 1374 sizeof(struct txp_frag_desc), BUS_DMASYNC_PREWRITE); 1375 1376 if (++prod == TX_ENTRIES) { 1377 fxd = (struct txp_frag_desc *)r->r_desc; 1378 prod = 0; 1379 } else 1380 fxd++; 1381 1382 } 1383 1384 /* 1385 * if mnew isn't NULL, we already dequeued and copied 1386 * the packet. 1387 */ 1388 if (mnew == NULL) 1389 ifq_deq_commit(&ifp->if_snd, m); 1390 1391 ifp->if_timer = 5; 1392 1393 #if NBPFILTER > 0 1394 if (ifp->if_bpf) 1395 bpf_mtap_ether(ifp->if_bpf, m, BPF_DIRECTION_OUT); 1396 #endif 1397 1398 txd->tx_flags |= TX_FLAGS_VALID; 1399 bus_dmamap_sync(sc->sc_dmat, sc->sc_txhiring_dma.dma_map, 1400 txdidx * sizeof(struct txp_tx_desc), 1401 sizeof(struct txp_tx_desc), BUS_DMASYNC_PREWRITE); 1402 1403 #if 0 1404 { 1405 struct mbuf *mx; 1406 int i; 1407 1408 printf("txd: flags 0x%x ndesc %d totlen %d pflags 0x%x\n", 1409 txd->tx_flags, txd->tx_numdesc, txd->tx_totlen, 1410 txd->tx_pflags); 1411 for (mx = m; mx != NULL; mx = mx->m_next) { 1412 for (i = 0; i < mx->m_len; i++) { 1413 printf(":%02x", 1414 (u_int8_t)m->m_data[i]); 1415 } 1416 } 1417 printf("\n"); 1418 } 1419 #endif 1420 1421 WRITE_REG(sc, r->r_reg, TXP_IDX2OFFSET(prod)); 1422 } 1423 1424 r->r_prod = prod; 1425 r->r_cnt = cnt; 1426 return; 1427 1428 oactive: 1429 bus_dmamap_unload(sc->sc_dmat, sd->sd_map); 1430 oactive1: 1431 ifq_deq_rollback(&ifp->if_snd, m); 1432 ifq_set_oactive(&ifp->if_snd); 1433 r->r_prod = firstprod; 1434 r->r_cnt = firstcnt; 1435 } 1436 1437 /* 1438 * Handle simple commands sent to the typhoon 1439 */ 1440 int 1441 txp_command(struct txp_softc *sc, u_int16_t id, u_int16_t in1, 1442 u_int32_t in2, u_int32_t in3, u_int16_t *out1, u_int32_t *out2, 1443 u_int32_t *out3, int wait) 1444 { 1445 struct txp_rsp_desc *rsp = NULL; 1446 1447 if (txp_command2(sc, id, in1, in2, in3, NULL, 0, &rsp, wait)) 1448 return (-1); 1449 1450 if (!wait) 1451 return (0); 1452 1453 if (out1 != NULL) 1454 *out1 = letoh16(rsp->rsp_par1); 1455 if (out2 != NULL) 1456 *out2 = letoh32(rsp->rsp_par2); 1457 if (out3 != NULL) 1458 *out3 = letoh32(rsp->rsp_par3); 1459 free(rsp, M_DEVBUF, 0); 1460 return (0); 1461 } 1462 1463 int 1464 txp_command2(struct txp_softc *sc, u_int16_t id, u_int16_t in1, 1465 u_int32_t in2, u_int32_t in3, struct txp_ext_desc *in_extp, 1466 u_int8_t in_extn,struct txp_rsp_desc **rspp, int wait) 1467 { 1468 struct txp_hostvar *hv = sc->sc_hostvar; 1469 struct txp_cmd_desc *cmd; 1470 struct txp_ext_desc *ext; 1471 u_int32_t idx, i; 1472 u_int16_t seq; 1473 1474 if (txp_cmd_desc_numfree(sc) < (in_extn + 1)) { 1475 printf("%s: no free cmd descriptors\n", TXP_DEVNAME(sc)); 1476 return (-1); 1477 } 1478 1479 idx = sc->sc_cmdring.lastwrite; 1480 cmd = (struct txp_cmd_desc *)(((u_int8_t *)sc->sc_cmdring.base) + idx); 1481 bzero(cmd, sizeof(*cmd)); 1482 1483 cmd->cmd_numdesc = in_extn; 1484 seq = sc->sc_seq++; 1485 cmd->cmd_seq = htole16(seq); 1486 cmd->cmd_id = htole16(id); 1487 cmd->cmd_par1 = htole16(in1); 1488 cmd->cmd_par2 = htole32(in2); 1489 cmd->cmd_par3 = htole32(in3); 1490 cmd->cmd_flags = CMD_FLAGS_TYPE_CMD | 1491 (wait ? CMD_FLAGS_RESP : 0) | CMD_FLAGS_VALID; 1492 1493 idx += sizeof(struct txp_cmd_desc); 1494 if (idx == sc->sc_cmdring.size) 1495 idx = 0; 1496 1497 for (i = 0; i < in_extn; i++) { 1498 ext = (struct txp_ext_desc *)(((u_int8_t *)sc->sc_cmdring.base) + idx); 1499 bcopy(in_extp, ext, sizeof(struct txp_ext_desc)); 1500 in_extp++; 1501 idx += sizeof(struct txp_cmd_desc); 1502 if (idx == sc->sc_cmdring.size) 1503 idx = 0; 1504 } 1505 1506 sc->sc_cmdring.lastwrite = idx; 1507 1508 WRITE_REG(sc, TXP_H2A_2, sc->sc_cmdring.lastwrite); 1509 bus_dmamap_sync(sc->sc_dmat, sc->sc_host_dma.dma_map, 0, 1510 sizeof(struct txp_hostvar), BUS_DMASYNC_PREREAD); 1511 1512 if (!wait) 1513 return (0); 1514 1515 for (i = 0; i < 10000; i++) { 1516 bus_dmamap_sync(sc->sc_dmat, sc->sc_host_dma.dma_map, 0, 1517 sizeof(struct txp_hostvar), BUS_DMASYNC_POSTREAD); 1518 idx = letoh32(hv->hv_resp_read_idx); 1519 if (idx != letoh32(hv->hv_resp_write_idx)) { 1520 *rspp = NULL; 1521 if (txp_response(sc, idx, id, seq, rspp)) 1522 return (-1); 1523 if (*rspp != NULL) 1524 break; 1525 } 1526 bus_dmamap_sync(sc->sc_dmat, sc->sc_host_dma.dma_map, 0, 1527 sizeof(struct txp_hostvar), BUS_DMASYNC_PREREAD); 1528 DELAY(50); 1529 } 1530 if (i == 1000 || (*rspp) == NULL) { 1531 printf("%s: 0x%x command failed\n", TXP_DEVNAME(sc), id); 1532 return (-1); 1533 } 1534 1535 return (0); 1536 } 1537 1538 int 1539 txp_response(struct txp_softc *sc, u_int32_t ridx, u_int16_t id, 1540 u_int16_t seq, struct txp_rsp_desc **rspp) 1541 { 1542 struct txp_hostvar *hv = sc->sc_hostvar; 1543 struct txp_rsp_desc *rsp; 1544 1545 while (ridx != letoh32(hv->hv_resp_write_idx)) { 1546 rsp = (struct txp_rsp_desc *)(((u_int8_t *)sc->sc_rspring.base) + ridx); 1547 1548 if (id == letoh16(rsp->rsp_id) && letoh16(rsp->rsp_seq) == seq) { 1549 *rspp = mallocarray(rsp->rsp_numdesc + 1, 1550 sizeof(struct txp_rsp_desc), M_DEVBUF, M_NOWAIT); 1551 if ((*rspp) == NULL) 1552 return (-1); 1553 txp_rsp_fixup(sc, rsp, *rspp); 1554 return (0); 1555 } 1556 1557 if (rsp->rsp_flags & RSP_FLAGS_ERROR) { 1558 printf("%s: response error: id 0x%x\n", 1559 TXP_DEVNAME(sc), letoh16(rsp->rsp_id)); 1560 txp_rsp_fixup(sc, rsp, NULL); 1561 ridx = letoh32(hv->hv_resp_read_idx); 1562 continue; 1563 } 1564 1565 switch (letoh16(rsp->rsp_id)) { 1566 case TXP_CMD_CYCLE_STATISTICS: 1567 case TXP_CMD_MEDIA_STATUS_READ: 1568 break; 1569 case TXP_CMD_HELLO_RESPONSE: 1570 printf("%s: hello\n", TXP_DEVNAME(sc)); 1571 break; 1572 default: 1573 printf("%s: unknown id(0x%x)\n", TXP_DEVNAME(sc), 1574 letoh16(rsp->rsp_id)); 1575 } 1576 1577 txp_rsp_fixup(sc, rsp, NULL); 1578 ridx = letoh32(hv->hv_resp_read_idx); 1579 hv->hv_resp_read_idx = letoh32(ridx); 1580 } 1581 1582 return (0); 1583 } 1584 1585 void 1586 txp_rsp_fixup(struct txp_softc *sc, struct txp_rsp_desc *rsp, 1587 struct txp_rsp_desc *dst) 1588 { 1589 struct txp_rsp_desc *src = rsp; 1590 struct txp_hostvar *hv = sc->sc_hostvar; 1591 u_int32_t i, ridx; 1592 1593 ridx = letoh32(hv->hv_resp_read_idx); 1594 1595 for (i = 0; i < rsp->rsp_numdesc + 1; i++) { 1596 if (dst != NULL) 1597 bcopy(src, dst++, sizeof(struct txp_rsp_desc)); 1598 ridx += sizeof(struct txp_rsp_desc); 1599 if (ridx == sc->sc_rspring.size) { 1600 src = sc->sc_rspring.base; 1601 ridx = 0; 1602 } else 1603 src++; 1604 sc->sc_rspring.lastwrite = ridx; 1605 hv->hv_resp_read_idx = htole32(ridx); 1606 } 1607 1608 hv->hv_resp_read_idx = htole32(ridx); 1609 } 1610 1611 int 1612 txp_cmd_desc_numfree(struct txp_softc *sc) 1613 { 1614 struct txp_hostvar *hv = sc->sc_hostvar; 1615 struct txp_boot_record *br = sc->sc_boot; 1616 u_int32_t widx, ridx, nfree; 1617 1618 widx = sc->sc_cmdring.lastwrite; 1619 ridx = letoh32(hv->hv_cmd_read_idx); 1620 1621 if (widx == ridx) { 1622 /* Ring is completely free */ 1623 nfree = letoh32(br->br_cmd_siz) - sizeof(struct txp_cmd_desc); 1624 } else { 1625 if (widx > ridx) 1626 nfree = letoh32(br->br_cmd_siz) - 1627 (widx - ridx + sizeof(struct txp_cmd_desc)); 1628 else 1629 nfree = ridx - widx - sizeof(struct txp_cmd_desc); 1630 } 1631 1632 return (nfree / sizeof(struct txp_cmd_desc)); 1633 } 1634 1635 void 1636 txp_stop(struct txp_softc *sc) 1637 { 1638 struct ifnet *ifp = &sc->sc_arpcom.ac_if; 1639 1640 timeout_del(&sc->sc_tick); 1641 1642 /* Mark the interface as down and cancel the watchdog timer. */ 1643 ifp->if_flags &= ~IFF_RUNNING; 1644 ifq_clr_oactive(&ifp->if_snd); 1645 ifp->if_timer = 0; 1646 1647 txp_command(sc, TXP_CMD_TX_DISABLE, 0, 0, 0, NULL, NULL, NULL, 1); 1648 txp_command(sc, TXP_CMD_RX_DISABLE, 0, 0, 0, NULL, NULL, NULL, 1); 1649 } 1650 1651 void 1652 txp_watchdog(struct ifnet *ifp) 1653 { 1654 } 1655 1656 int 1657 txp_ifmedia_upd(struct ifnet *ifp) 1658 { 1659 struct txp_softc *sc = ifp->if_softc; 1660 struct ifmedia *ifm = &sc->sc_ifmedia; 1661 u_int16_t new_xcvr; 1662 1663 if (IFM_TYPE(ifm->ifm_media) != IFM_ETHER) 1664 return (EINVAL); 1665 1666 if (IFM_SUBTYPE(ifm->ifm_media) == IFM_10_T) { 1667 if ((ifm->ifm_media & IFM_GMASK) == IFM_FDX) 1668 new_xcvr = TXP_XCVR_10_FDX; 1669 else 1670 new_xcvr = TXP_XCVR_10_HDX; 1671 } else if (IFM_SUBTYPE(ifm->ifm_media) == IFM_100_TX) { 1672 if ((ifm->ifm_media & IFM_GMASK) == IFM_FDX) 1673 new_xcvr = TXP_XCVR_100_FDX; 1674 else 1675 new_xcvr = TXP_XCVR_100_HDX; 1676 } else if (IFM_SUBTYPE(ifm->ifm_media) == IFM_AUTO) { 1677 new_xcvr = TXP_XCVR_AUTO; 1678 } else 1679 return (EINVAL); 1680 1681 /* nothing to do */ 1682 if (sc->sc_xcvr == new_xcvr) 1683 return (0); 1684 1685 txp_command(sc, TXP_CMD_XCVR_SELECT, new_xcvr, 0, 0, 1686 NULL, NULL, NULL, 0); 1687 sc->sc_xcvr = new_xcvr; 1688 1689 return (0); 1690 } 1691 1692 void 1693 txp_ifmedia_sts(struct ifnet *ifp, struct ifmediareq *ifmr) 1694 { 1695 struct txp_softc *sc = ifp->if_softc; 1696 struct ifmedia *ifm = &sc->sc_ifmedia; 1697 u_int16_t bmsr, bmcr, anar, anlpar; 1698 1699 ifmr->ifm_status = IFM_AVALID; 1700 ifmr->ifm_active = IFM_ETHER; 1701 1702 if (txp_command(sc, TXP_CMD_PHY_MGMT_READ, 0, MII_BMSR, 0, 1703 &bmsr, NULL, NULL, 1)) 1704 goto bail; 1705 if (txp_command(sc, TXP_CMD_PHY_MGMT_READ, 0, MII_BMSR, 0, 1706 &bmsr, NULL, NULL, 1)) 1707 goto bail; 1708 1709 if (txp_command(sc, TXP_CMD_PHY_MGMT_READ, 0, MII_BMCR, 0, 1710 &bmcr, NULL, NULL, 1)) 1711 goto bail; 1712 1713 if (txp_command(sc, TXP_CMD_PHY_MGMT_READ, 0, MII_ANAR, 0, 1714 &anar, NULL, NULL, 1)) 1715 goto bail; 1716 1717 if (txp_command(sc, TXP_CMD_PHY_MGMT_READ, 0, MII_ANLPAR, 0, 1718 &anlpar, NULL, NULL, 1)) 1719 goto bail; 1720 1721 if (bmsr & BMSR_LINK) 1722 ifmr->ifm_status |= IFM_ACTIVE; 1723 1724 if (bmcr & BMCR_ISO) { 1725 ifmr->ifm_active |= IFM_NONE; 1726 ifmr->ifm_status = 0; 1727 return; 1728 } 1729 1730 if (bmcr & BMCR_LOOP) 1731 ifmr->ifm_active |= IFM_LOOP; 1732 1733 if (bmcr & BMCR_AUTOEN) { 1734 if ((bmsr & BMSR_ACOMP) == 0) { 1735 ifmr->ifm_active |= IFM_NONE; 1736 return; 1737 } 1738 1739 anlpar &= anar; 1740 if (anlpar & ANLPAR_TX_FD) 1741 ifmr->ifm_active |= IFM_100_TX|IFM_FDX; 1742 else if (anlpar & ANLPAR_T4) 1743 ifmr->ifm_active |= IFM_100_T4|IFM_HDX; 1744 else if (anlpar & ANLPAR_TX) 1745 ifmr->ifm_active |= IFM_100_TX|IFM_HDX; 1746 else if (anlpar & ANLPAR_10_FD) 1747 ifmr->ifm_active |= IFM_10_T|IFM_FDX; 1748 else if (anlpar & ANLPAR_10) 1749 ifmr->ifm_active |= IFM_10_T|IFM_HDX; 1750 else 1751 ifmr->ifm_active |= IFM_NONE; 1752 } else 1753 ifmr->ifm_active = ifm->ifm_cur->ifm_media; 1754 return; 1755 1756 bail: 1757 ifmr->ifm_active |= IFM_NONE; 1758 ifmr->ifm_status &= ~IFM_AVALID; 1759 } 1760 1761 void 1762 txp_show_descriptor(void *d) 1763 { 1764 struct txp_cmd_desc *cmd = d; 1765 struct txp_rsp_desc *rsp = d; 1766 struct txp_tx_desc *txd = d; 1767 struct txp_frag_desc *frgd = d; 1768 1769 switch (cmd->cmd_flags & CMD_FLAGS_TYPE_M) { 1770 case CMD_FLAGS_TYPE_CMD: 1771 /* command descriptor */ 1772 printf("[cmd flags 0x%x num %d id %d seq %d par1 0x%x par2 0x%x par3 0x%x]\n", 1773 cmd->cmd_flags, cmd->cmd_numdesc, letoh16(cmd->cmd_id), 1774 letoh16(cmd->cmd_seq), letoh16(cmd->cmd_par1), 1775 letoh32(cmd->cmd_par2), letoh32(cmd->cmd_par3)); 1776 break; 1777 case CMD_FLAGS_TYPE_RESP: 1778 /* response descriptor */ 1779 printf("[rsp flags 0x%x num %d id %d seq %d par1 0x%x par2 0x%x par3 0x%x]\n", 1780 rsp->rsp_flags, rsp->rsp_numdesc, letoh16(rsp->rsp_id), 1781 letoh16(rsp->rsp_seq), letoh16(rsp->rsp_par1), 1782 letoh32(rsp->rsp_par2), letoh32(rsp->rsp_par3)); 1783 break; 1784 case CMD_FLAGS_TYPE_DATA: 1785 /* data header (assuming tx for now) */ 1786 printf("[data flags 0x%x num %d totlen %d addr 0x%x/0x%x pflags 0x%x]", 1787 txd->tx_flags, txd->tx_numdesc, txd->tx_totlen, 1788 txd->tx_addrlo, txd->tx_addrhi, txd->tx_pflags); 1789 break; 1790 case CMD_FLAGS_TYPE_FRAG: 1791 /* fragment descriptor */ 1792 printf("[frag flags 0x%x rsvd1 0x%x len %d addr 0x%x/0x%x rsvd2 0x%x]", 1793 frgd->frag_flags, frgd->frag_rsvd1, frgd->frag_len, 1794 frgd->frag_addrlo, frgd->frag_addrhi, frgd->frag_rsvd2); 1795 break; 1796 default: 1797 printf("[unknown(%x) flags 0x%x num %d id %d seq %d par1 0x%x par2 0x%x par3 0x%x]\n", 1798 cmd->cmd_flags & CMD_FLAGS_TYPE_M, 1799 cmd->cmd_flags, cmd->cmd_numdesc, letoh16(cmd->cmd_id), 1800 letoh16(cmd->cmd_seq), letoh16(cmd->cmd_par1), 1801 letoh32(cmd->cmd_par2), letoh32(cmd->cmd_par3)); 1802 break; 1803 } 1804 } 1805 1806 void 1807 txp_set_filter(struct txp_softc *sc) 1808 { 1809 struct arpcom *ac = &sc->sc_arpcom; 1810 struct ifnet *ifp = &sc->sc_arpcom.ac_if; 1811 u_int32_t hashbit, hash[2]; 1812 u_int16_t filter; 1813 int mcnt = 0; 1814 struct ether_multi *enm; 1815 struct ether_multistep step; 1816 1817 if (ifp->if_flags & IFF_PROMISC) { 1818 filter = TXP_RXFILT_PROMISC; 1819 goto setit; 1820 } 1821 1822 if (ac->ac_multirangecnt > 0) 1823 ifp->if_flags |= IFF_ALLMULTI; 1824 1825 filter = TXP_RXFILT_DIRECT; 1826 1827 if (ifp->if_flags & IFF_BROADCAST) 1828 filter |= TXP_RXFILT_BROADCAST; 1829 1830 if (ifp->if_flags & IFF_ALLMULTI) 1831 filter |= TXP_RXFILT_ALLMULTI; 1832 else { 1833 hash[0] = hash[1] = 0; 1834 1835 ETHER_FIRST_MULTI(step, ac, enm); 1836 while (enm != NULL) { 1837 mcnt++; 1838 hashbit = (u_int16_t)(ether_crc32_be(enm->enm_addrlo, 1839 ETHER_ADDR_LEN) & (64 - 1)); 1840 hash[hashbit / 32] |= (1 << hashbit % 32); 1841 ETHER_NEXT_MULTI(step, enm); 1842 } 1843 1844 if (mcnt > 0) { 1845 filter |= TXP_RXFILT_HASHMULTI; 1846 txp_command(sc, TXP_CMD_MCAST_HASH_MASK_WRITE, 1847 2, hash[0], hash[1], NULL, NULL, NULL, 0); 1848 } 1849 } 1850 1851 setit: 1852 txp_command(sc, TXP_CMD_RX_FILTER_WRITE, filter, 0, 0, 1853 NULL, NULL, NULL, 1); 1854 } 1855 1856 void 1857 txp_capabilities(struct txp_softc *sc) 1858 { 1859 struct ifnet *ifp = &sc->sc_arpcom.ac_if; 1860 struct txp_rsp_desc *rsp = NULL; 1861 struct txp_ext_desc *ext; 1862 1863 if (txp_command2(sc, TXP_CMD_OFFLOAD_READ, 0, 0, 0, NULL, 0, &rsp, 1)) 1864 goto out; 1865 1866 if (rsp->rsp_numdesc != 1) 1867 goto out; 1868 ext = (struct txp_ext_desc *)(rsp + 1); 1869 1870 sc->sc_tx_capability = ext->ext_1 & OFFLOAD_MASK; 1871 sc->sc_rx_capability = ext->ext_2 & OFFLOAD_MASK; 1872 1873 ifp->if_capabilities = IFCAP_VLAN_MTU; 1874 1875 #if NVLAN > 0 1876 if (rsp->rsp_par2 & rsp->rsp_par3 & OFFLOAD_VLAN) { 1877 sc->sc_tx_capability |= OFFLOAD_VLAN; 1878 sc->sc_rx_capability |= OFFLOAD_VLAN; 1879 ifp->if_capabilities |= IFCAP_VLAN_HWTAGGING; 1880 } 1881 #endif 1882 1883 #if 0 1884 /* not ready yet */ 1885 if (rsp->rsp_par2 & rsp->rsp_par3 & OFFLOAD_IPSEC) { 1886 sc->sc_tx_capability |= OFFLOAD_IPSEC; 1887 sc->sc_rx_capability |= OFFLOAD_IPSEC; 1888 ifp->if_capabilities |= IFCAP_IPSEC; 1889 } 1890 #endif 1891 1892 if (rsp->rsp_par2 & rsp->rsp_par3 & OFFLOAD_IPCKSUM) { 1893 sc->sc_tx_capability |= OFFLOAD_IPCKSUM; 1894 sc->sc_rx_capability |= OFFLOAD_IPCKSUM; 1895 ifp->if_capabilities |= IFCAP_CSUM_IPv4; 1896 } 1897 1898 if (rsp->rsp_par2 & rsp->rsp_par3 & OFFLOAD_TCPCKSUM) { 1899 sc->sc_rx_capability |= OFFLOAD_TCPCKSUM; 1900 #ifdef TRY_TX_TCP_CSUM 1901 sc->sc_tx_capability |= OFFLOAD_TCPCKSUM; 1902 ifp->if_capabilities |= IFCAP_CSUM_TCPv4; 1903 #endif 1904 } 1905 1906 if (rsp->rsp_par2 & rsp->rsp_par3 & OFFLOAD_UDPCKSUM) { 1907 sc->sc_rx_capability |= OFFLOAD_UDPCKSUM; 1908 #ifdef TRY_TX_UDP_CSUM 1909 sc->sc_tx_capability |= OFFLOAD_UDPCKSUM; 1910 ifp->if_capabilities |= IFCAP_CSUM_UDPv4; 1911 #endif 1912 } 1913 1914 if (txp_command(sc, TXP_CMD_OFFLOAD_WRITE, 0, 1915 sc->sc_tx_capability, sc->sc_rx_capability, NULL, NULL, NULL, 1)) 1916 goto out; 1917 1918 out: 1919 if (rsp != NULL) 1920 free(rsp, M_DEVBUF, 0); 1921 } 1922