1 /* $OpenBSD: if_txp.c,v 1.100 2009/03/24 11:12:10 kettenis Exp $ */ 2 3 /* 4 * Copyright (c) 2001 5 * Jason L. Wright <jason@thought.net>, Theo de Raadt, and 6 * Aaron Campbell <aaron@monkey.org>. All rights reserved. 7 * 8 * Redistribution and use in source and binary forms, with or without 9 * modification, are permitted provided that the following conditions 10 * are met: 11 * 1. Redistributions of source code must retain the above copyright 12 * notice, this list of conditions and the following disclaimer. 13 * 2. Redistributions in binary form must reproduce the above copyright 14 * notice, this list of conditions and the following disclaimer in the 15 * documentation and/or other materials provided with the distribution. 16 * 17 * THIS SOFTWARE IS PROVIDED BY THE AUTHORS ``AS IS'' AND ANY EXPRESS OR 18 * IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED 19 * WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE 20 * ARE DISCLAIMED. IN NO EVENT SHALL THE AUTHORS OR THE VOICES IN THEIR HEADS 21 * BE LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR 22 * CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF 23 * SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS 24 * INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN 25 * CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) 26 * ARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF 27 * THE POSSIBILITY OF SUCH DAMAGE. 28 */ 29 30 /* 31 * Driver for 3c990 (Typhoon) Ethernet ASIC 32 */ 33 34 #include "bpfilter.h" 35 #include "vlan.h" 36 37 #include <sys/param.h> 38 #include <sys/systm.h> 39 #include <sys/sockio.h> 40 #include <sys/mbuf.h> 41 #include <sys/malloc.h> 42 #include <sys/kernel.h> 43 #include <sys/socket.h> 44 #include <sys/device.h> 45 #include <sys/timeout.h> 46 47 #include <net/if.h> 48 #include <net/if_dl.h> 49 #include <net/if_types.h> 50 51 #ifdef INET 52 #include <netinet/in.h> 53 #include <netinet/in_systm.h> 54 #include <netinet/in_var.h> 55 #include <netinet/ip.h> 56 #include <netinet/if_ether.h> 57 #endif 58 59 #include <net/if_media.h> 60 61 #if NBPFILTER > 0 62 #include <net/bpf.h> 63 #endif 64 65 #if NVLAN > 0 66 #include <net/if_types.h> 67 #include <net/if_vlan_var.h> 68 #endif 69 70 #include <machine/bus.h> 71 72 #include <dev/mii/mii.h> 73 #include <dev/mii/miivar.h> 74 #include <dev/pci/pcireg.h> 75 #include <dev/pci/pcivar.h> 76 #include <dev/pci/pcidevs.h> 77 78 #include <dev/pci/if_txpreg.h> 79 80 /* 81 * These currently break the 3c990 firmware, hopefully will be resolved 82 * at some point. 83 */ 84 #undef TRY_TX_UDP_CSUM 85 #undef TRY_TX_TCP_CSUM 86 87 int txp_probe(struct device *, void *, void *); 88 void txp_attach(struct device *, struct device *, void *); 89 void txp_attachhook(void *vsc); 90 int txp_intr(void *); 91 void txp_tick(void *); 92 void txp_shutdown(void *); 93 int txp_ioctl(struct ifnet *, u_long, caddr_t); 94 void txp_start(struct ifnet *); 95 void txp_stop(struct txp_softc *); 96 void txp_init(struct txp_softc *); 97 void txp_watchdog(struct ifnet *); 98 99 int txp_chip_init(struct txp_softc *); 100 int txp_reset_adapter(struct txp_softc *); 101 int txp_download_fw(struct txp_softc *); 102 int txp_download_fw_wait(struct txp_softc *); 103 int txp_download_fw_section(struct txp_softc *, 104 struct txp_fw_section_header *, int, u_char *, size_t); 105 int txp_alloc_rings(struct txp_softc *); 106 void txp_dma_free(struct txp_softc *, struct txp_dma_alloc *); 107 int txp_dma_malloc(struct txp_softc *, bus_size_t, struct txp_dma_alloc *, int); 108 void txp_set_filter(struct txp_softc *); 109 110 int txp_cmd_desc_numfree(struct txp_softc *); 111 int txp_command(struct txp_softc *, u_int16_t, u_int16_t, u_int32_t, 112 u_int32_t, u_int16_t *, u_int32_t *, u_int32_t *, int); 113 int txp_command2(struct txp_softc *, u_int16_t, u_int16_t, 114 u_int32_t, u_int32_t, struct txp_ext_desc *, u_int8_t, 115 struct txp_rsp_desc **, int); 116 int txp_response(struct txp_softc *, u_int32_t, u_int16_t, u_int16_t, 117 struct txp_rsp_desc **); 118 void txp_rsp_fixup(struct txp_softc *, struct txp_rsp_desc *, 119 struct txp_rsp_desc *); 120 void txp_capabilities(struct txp_softc *); 121 122 void txp_ifmedia_sts(struct ifnet *, struct ifmediareq *); 123 int txp_ifmedia_upd(struct ifnet *); 124 void txp_show_descriptor(void *); 125 void txp_tx_reclaim(struct txp_softc *, struct txp_tx_ring *, 126 struct txp_dma_alloc *); 127 void txp_rxbuf_reclaim(struct txp_softc *); 128 void txp_rx_reclaim(struct txp_softc *, struct txp_rx_ring *, 129 struct txp_dma_alloc *); 130 131 struct cfattach txp_ca = { 132 sizeof(struct txp_softc), txp_probe, txp_attach, 133 }; 134 135 struct cfdriver txp_cd = { 136 0, "txp", DV_IFNET 137 }; 138 139 const struct pci_matchid txp_devices[] = { 140 { PCI_VENDOR_3COM, PCI_PRODUCT_3COM_3CR990 }, 141 { PCI_VENDOR_3COM, PCI_PRODUCT_3COM_3CR990TX }, 142 { PCI_VENDOR_3COM, PCI_PRODUCT_3COM_3CR990TX95 }, 143 { PCI_VENDOR_3COM, PCI_PRODUCT_3COM_3CR990TX97 }, 144 { PCI_VENDOR_3COM, PCI_PRODUCT_3COM_3CR990SVR95 }, 145 { PCI_VENDOR_3COM, PCI_PRODUCT_3COM_3CR990SVR97 }, 146 { PCI_VENDOR_3COM, PCI_PRODUCT_3COM_3C990BTXM }, 147 { PCI_VENDOR_3COM, PCI_PRODUCT_3COM_3C990BSVR }, 148 { PCI_VENDOR_3COM, PCI_PRODUCT_3COM_3CR990FX }, 149 }; 150 151 int 152 txp_probe(struct device *parent, void *match, void *aux) 153 { 154 return (pci_matchbyid((struct pci_attach_args *)aux, txp_devices, 155 sizeof(txp_devices)/sizeof(txp_devices[0]))); 156 } 157 158 void 159 txp_attachhook(void *vsc) 160 { 161 struct txp_softc *sc = vsc; 162 struct ifnet *ifp = &sc->sc_arpcom.ac_if; 163 u_int16_t p1; 164 u_int32_t p2; 165 int s; 166 167 s = splnet(); 168 printf("%s: ", sc->sc_dev.dv_xname); 169 170 if (txp_chip_init(sc)) { 171 printf("failed chip init\n"); 172 splx(s); 173 return; 174 } 175 176 if (txp_download_fw(sc)) { 177 splx(s); 178 return; 179 } 180 181 if (txp_alloc_rings(sc)) { 182 splx(s); 183 return; 184 } 185 186 if (txp_command(sc, TXP_CMD_MAX_PKT_SIZE_WRITE, TXP_MAX_PKTLEN, 0, 0, 187 NULL, NULL, NULL, 1)) { 188 splx(s); 189 return; 190 } 191 192 if (txp_command(sc, TXP_CMD_STATION_ADDRESS_READ, 0, 0, 0, 193 &p1, &p2, NULL, 1)) { 194 splx(s); 195 return; 196 } 197 198 p1 = htole16(p1); 199 sc->sc_arpcom.ac_enaddr[0] = ((u_int8_t *)&p1)[1]; 200 sc->sc_arpcom.ac_enaddr[1] = ((u_int8_t *)&p1)[0]; 201 p2 = htole32(p2); 202 sc->sc_arpcom.ac_enaddr[2] = ((u_int8_t *)&p2)[3]; 203 sc->sc_arpcom.ac_enaddr[3] = ((u_int8_t *)&p2)[2]; 204 sc->sc_arpcom.ac_enaddr[4] = ((u_int8_t *)&p2)[1]; 205 sc->sc_arpcom.ac_enaddr[5] = ((u_int8_t *)&p2)[0]; 206 207 printf("address %s\n", ether_sprintf(sc->sc_arpcom.ac_enaddr)); 208 sc->sc_cold = 0; 209 210 ifmedia_init(&sc->sc_ifmedia, 0, txp_ifmedia_upd, txp_ifmedia_sts); 211 ifmedia_add(&sc->sc_ifmedia, IFM_ETHER|IFM_10_T, 0, NULL); 212 ifmedia_add(&sc->sc_ifmedia, IFM_ETHER|IFM_10_T|IFM_HDX, 0, NULL); 213 ifmedia_add(&sc->sc_ifmedia, IFM_ETHER|IFM_10_T|IFM_FDX, 0, NULL); 214 ifmedia_add(&sc->sc_ifmedia, IFM_ETHER|IFM_100_TX, 0, NULL); 215 ifmedia_add(&sc->sc_ifmedia, IFM_ETHER|IFM_100_TX|IFM_HDX, 0, NULL); 216 ifmedia_add(&sc->sc_ifmedia, IFM_ETHER|IFM_100_TX|IFM_FDX, 0, NULL); 217 ifmedia_add(&sc->sc_ifmedia, IFM_ETHER|IFM_AUTO, 0, NULL); 218 219 sc->sc_xcvr = TXP_XCVR_AUTO; 220 txp_command(sc, TXP_CMD_XCVR_SELECT, TXP_XCVR_AUTO, 0, 0, 221 NULL, NULL, NULL, 0); 222 ifmedia_set(&sc->sc_ifmedia, IFM_ETHER|IFM_AUTO); 223 224 ifp->if_softc = sc; 225 ifp->if_flags = IFF_BROADCAST | IFF_SIMPLEX | IFF_MULTICAST; 226 ifp->if_ioctl = txp_ioctl; 227 ifp->if_start = txp_start; 228 ifp->if_watchdog = txp_watchdog; 229 ifp->if_baudrate = 10000000; 230 IFQ_SET_MAXLEN(&ifp->if_snd, TX_ENTRIES); 231 IFQ_SET_READY(&ifp->if_snd); 232 ifp->if_capabilities = 0; 233 bcopy(sc->sc_dev.dv_xname, ifp->if_xname, IFNAMSIZ); 234 235 txp_capabilities(sc); 236 237 timeout_set(&sc->sc_tick, txp_tick, sc); 238 239 /* 240 * Attach us everywhere 241 */ 242 if_attach(ifp); 243 ether_ifattach(ifp); 244 245 shutdownhook_establish(txp_shutdown, sc); 246 splx(s); 247 } 248 249 void 250 txp_attach(struct device *parent, struct device *self, void *aux) 251 { 252 struct txp_softc *sc = (struct txp_softc *)self; 253 struct pci_attach_args *pa = aux; 254 pci_chipset_tag_t pc = pa->pa_pc; 255 pci_intr_handle_t ih; 256 const char *intrstr = NULL; 257 bus_size_t iosize; 258 259 sc->sc_cold = 1; 260 261 if (pci_mapreg_map(pa, TXP_PCI_LOMEM, PCI_MAPREG_TYPE_MEM, 0, 262 &sc->sc_bt, &sc->sc_bh, NULL, &iosize, 0)) { 263 printf(": can't map mem space %d\n", 0); 264 return; 265 } 266 267 sc->sc_dmat = pa->pa_dmat; 268 269 /* 270 * Allocate our interrupt. 271 */ 272 if (pci_intr_map(pa, &ih)) { 273 printf(": couldn't map interrupt\n"); 274 return; 275 } 276 277 intrstr = pci_intr_string(pc, ih); 278 sc->sc_ih = pci_intr_establish(pc, ih, IPL_NET, txp_intr, sc, 279 self->dv_xname); 280 if (sc->sc_ih == NULL) { 281 printf(": couldn't establish interrupt"); 282 if (intrstr != NULL) 283 printf(" at %s", intrstr); 284 printf("\n"); 285 return; 286 } 287 printf(": %s\n", intrstr); 288 289 if (rootvp == NULL) 290 mountroothook_establish(txp_attachhook, sc); 291 else 292 txp_attachhook(sc); 293 294 } 295 296 int 297 txp_chip_init(struct txp_softc *sc) 298 { 299 /* disable interrupts */ 300 WRITE_REG(sc, TXP_IER, 0); 301 WRITE_REG(sc, TXP_IMR, 302 TXP_INT_SELF | TXP_INT_PCI_TABORT | TXP_INT_PCI_MABORT | 303 TXP_INT_DMA3 | TXP_INT_DMA2 | TXP_INT_DMA1 | TXP_INT_DMA0 | 304 TXP_INT_LATCH); 305 306 /* ack all interrupts */ 307 WRITE_REG(sc, TXP_ISR, TXP_INT_RESERVED | TXP_INT_LATCH | 308 TXP_INT_A2H_7 | TXP_INT_A2H_6 | TXP_INT_A2H_5 | TXP_INT_A2H_4 | 309 TXP_INT_SELF | TXP_INT_PCI_TABORT | TXP_INT_PCI_MABORT | 310 TXP_INT_DMA3 | TXP_INT_DMA2 | TXP_INT_DMA1 | TXP_INT_DMA0 | 311 TXP_INT_A2H_3 | TXP_INT_A2H_2 | TXP_INT_A2H_1 | TXP_INT_A2H_0); 312 313 if (txp_reset_adapter(sc)) 314 return (-1); 315 316 /* disable interrupts */ 317 WRITE_REG(sc, TXP_IER, 0); 318 WRITE_REG(sc, TXP_IMR, 319 TXP_INT_SELF | TXP_INT_PCI_TABORT | TXP_INT_PCI_MABORT | 320 TXP_INT_DMA3 | TXP_INT_DMA2 | TXP_INT_DMA1 | TXP_INT_DMA0 | 321 TXP_INT_LATCH); 322 323 /* ack all interrupts */ 324 WRITE_REG(sc, TXP_ISR, TXP_INT_RESERVED | TXP_INT_LATCH | 325 TXP_INT_A2H_7 | TXP_INT_A2H_6 | TXP_INT_A2H_5 | TXP_INT_A2H_4 | 326 TXP_INT_SELF | TXP_INT_PCI_TABORT | TXP_INT_PCI_MABORT | 327 TXP_INT_DMA3 | TXP_INT_DMA2 | TXP_INT_DMA1 | TXP_INT_DMA0 | 328 TXP_INT_A2H_3 | TXP_INT_A2H_2 | TXP_INT_A2H_1 | TXP_INT_A2H_0); 329 330 return (0); 331 } 332 333 int 334 txp_reset_adapter(struct txp_softc *sc) 335 { 336 u_int32_t r; 337 int i; 338 339 WRITE_REG(sc, TXP_SRR, TXP_SRR_ALL); 340 DELAY(1000); 341 WRITE_REG(sc, TXP_SRR, 0); 342 343 /* Should wait max 6 seconds */ 344 for (i = 0; i < 6000; i++) { 345 r = READ_REG(sc, TXP_A2H_0); 346 if (r == STAT_WAITING_FOR_HOST_REQUEST) 347 break; 348 DELAY(1000); 349 } 350 351 if (r != STAT_WAITING_FOR_HOST_REQUEST) { 352 printf("%s: reset hung\n", TXP_DEVNAME(sc)); 353 return (-1); 354 } 355 356 return (0); 357 } 358 359 int 360 txp_download_fw(struct txp_softc *sc) 361 { 362 struct txp_fw_file_header *fileheader; 363 struct txp_fw_section_header *secthead; 364 u_int32_t r, i, ier, imr; 365 size_t buflen; 366 int sect, err; 367 u_char *buf; 368 369 ier = READ_REG(sc, TXP_IER); 370 WRITE_REG(sc, TXP_IER, ier | TXP_INT_A2H_0); 371 372 imr = READ_REG(sc, TXP_IMR); 373 WRITE_REG(sc, TXP_IMR, imr | TXP_INT_A2H_0); 374 375 for (i = 0; i < 10000; i++) { 376 r = READ_REG(sc, TXP_A2H_0); 377 if (r == STAT_WAITING_FOR_HOST_REQUEST) 378 break; 379 DELAY(50); 380 } 381 if (r != STAT_WAITING_FOR_HOST_REQUEST) { 382 printf("not waiting for host request\n"); 383 return (-1); 384 } 385 386 /* Ack the status */ 387 WRITE_REG(sc, TXP_ISR, TXP_INT_A2H_0); 388 389 err = loadfirmware("3c990", &buf, &buflen); 390 if (err) { 391 printf("failed loadfirmware of file 3c990: errno %d\n", 392 err); 393 return (err); 394 } 395 396 fileheader = (struct txp_fw_file_header *)buf; 397 if (bcmp("TYPHOON", fileheader->magicid, sizeof(fileheader->magicid))) { 398 printf("firmware invalid magic\n"); 399 goto fail; 400 } 401 402 /* Tell boot firmware to get ready for image */ 403 WRITE_REG(sc, TXP_H2A_1, letoh32(fileheader->addr)); 404 WRITE_REG(sc, TXP_H2A_2, letoh32(fileheader->hmac[0])); 405 WRITE_REG(sc, TXP_H2A_3, letoh32(fileheader->hmac[1])); 406 WRITE_REG(sc, TXP_H2A_4, letoh32(fileheader->hmac[2])); 407 WRITE_REG(sc, TXP_H2A_5, letoh32(fileheader->hmac[3])); 408 WRITE_REG(sc, TXP_H2A_6, letoh32(fileheader->hmac[4])); 409 WRITE_REG(sc, TXP_H2A_0, TXP_BOOTCMD_RUNTIME_IMAGE); 410 411 if (txp_download_fw_wait(sc)) { 412 printf("fw wait failed, initial\n"); 413 goto fail; 414 } 415 416 secthead = (struct txp_fw_section_header *)(buf + 417 sizeof(struct txp_fw_file_header)); 418 419 for (sect = 0; sect < letoh32(fileheader->nsections); sect++) { 420 if (txp_download_fw_section(sc, secthead, sect, buf, buflen)) 421 goto fail; 422 secthead = (struct txp_fw_section_header *) 423 (((u_int8_t *)secthead) + letoh32(secthead->nbytes) + 424 sizeof(*secthead)); 425 } 426 427 WRITE_REG(sc, TXP_H2A_0, TXP_BOOTCMD_DOWNLOAD_COMPLETE); 428 429 for (i = 0; i < 10000; i++) { 430 r = READ_REG(sc, TXP_A2H_0); 431 if (r == STAT_WAITING_FOR_BOOT) 432 break; 433 DELAY(50); 434 } 435 if (r != STAT_WAITING_FOR_BOOT) { 436 printf("not waiting for boot\n"); 437 goto fail; 438 } 439 440 WRITE_REG(sc, TXP_IER, ier); 441 WRITE_REG(sc, TXP_IMR, imr); 442 443 free(buf, M_DEVBUF); 444 return (0); 445 fail: 446 free(buf, M_DEVBUF); 447 return (-1); 448 } 449 450 int 451 txp_download_fw_wait(struct txp_softc *sc) 452 { 453 u_int32_t i, r; 454 455 for (i = 0; i < 10000; i++) { 456 r = READ_REG(sc, TXP_ISR); 457 if (r & TXP_INT_A2H_0) 458 break; 459 DELAY(50); 460 } 461 462 if (!(r & TXP_INT_A2H_0)) { 463 printf("fw wait failed comm0\n"); 464 return (-1); 465 } 466 467 WRITE_REG(sc, TXP_ISR, TXP_INT_A2H_0); 468 469 r = READ_REG(sc, TXP_A2H_0); 470 if (r != STAT_WAITING_FOR_SEGMENT) { 471 printf("fw not waiting for segment\n"); 472 return (-1); 473 } 474 return (0); 475 } 476 477 int 478 txp_download_fw_section(struct txp_softc *sc, 479 struct txp_fw_section_header *sect, int sectnum, u_char *buf, 480 size_t buflen) 481 { 482 struct txp_dma_alloc dma; 483 int rseg, err = 0; 484 struct mbuf m; 485 u_int16_t csum; 486 487 /* Skip zero length sections */ 488 if (sect->nbytes == 0) 489 return (0); 490 491 /* Make sure we aren't past the end of the image */ 492 rseg = ((u_int8_t *)sect) - ((u_int8_t *)buf); 493 if (rseg >= buflen) { 494 printf("fw invalid section address, section %d\n", sectnum); 495 return (-1); 496 } 497 498 /* Make sure this section doesn't go past the end */ 499 rseg += letoh32(sect->nbytes); 500 if (rseg >= buflen) { 501 printf("fw truncated section %d\n", sectnum); 502 return (-1); 503 } 504 505 /* map a buffer, copy segment to it, get physaddr */ 506 if (txp_dma_malloc(sc, letoh32(sect->nbytes), &dma, 0)) { 507 printf("fw dma malloc failed, section %d\n", sectnum); 508 return (-1); 509 } 510 511 bcopy(((u_int8_t *)sect) + sizeof(*sect), dma.dma_vaddr, 512 letoh32(sect->nbytes)); 513 514 /* 515 * dummy up mbuf and verify section checksum 516 */ 517 m.m_type = MT_DATA; 518 m.m_next = m.m_nextpkt = NULL; 519 m.m_len = letoh32(sect->nbytes); 520 m.m_data = dma.dma_vaddr; 521 m.m_flags = 0; 522 csum = in_cksum(&m, letoh32(sect->nbytes)); 523 if (csum != sect->cksum) { 524 printf("fw section %d, bad cksum (expected 0x%x got 0x%x)\n", 525 sectnum, sect->cksum, csum); 526 err = -1; 527 goto bail; 528 } 529 530 bus_dmamap_sync(sc->sc_dmat, dma.dma_map, 0, 531 dma.dma_map->dm_mapsize, BUS_DMASYNC_PREWRITE); 532 533 WRITE_REG(sc, TXP_H2A_1, letoh32(sect->nbytes)); 534 WRITE_REG(sc, TXP_H2A_2, letoh16(sect->cksum)); 535 WRITE_REG(sc, TXP_H2A_3, letoh32(sect->addr)); 536 WRITE_REG(sc, TXP_H2A_4, dma.dma_paddr >> 32); 537 WRITE_REG(sc, TXP_H2A_5, dma.dma_paddr & 0xffffffff); 538 WRITE_REG(sc, TXP_H2A_0, TXP_BOOTCMD_SEGMENT_AVAILABLE); 539 540 if (txp_download_fw_wait(sc)) { 541 printf("%s: fw wait failed, section %d\n", 542 sc->sc_dev.dv_xname, sectnum); 543 err = -1; 544 } 545 546 bus_dmamap_sync(sc->sc_dmat, dma.dma_map, 0, 547 dma.dma_map->dm_mapsize, BUS_DMASYNC_POSTWRITE); 548 549 bail: 550 txp_dma_free(sc, &dma); 551 552 return (err); 553 } 554 555 int 556 txp_intr(void *vsc) 557 { 558 struct txp_softc *sc = vsc; 559 struct txp_hostvar *hv = sc->sc_hostvar; 560 u_int32_t isr; 561 int claimed = 0; 562 563 /* mask all interrupts */ 564 WRITE_REG(sc, TXP_IMR, TXP_INT_RESERVED | TXP_INT_SELF | 565 TXP_INT_A2H_7 | TXP_INT_A2H_6 | TXP_INT_A2H_5 | TXP_INT_A2H_4 | 566 TXP_INT_A2H_2 | TXP_INT_A2H_1 | TXP_INT_A2H_0 | 567 TXP_INT_DMA3 | TXP_INT_DMA2 | TXP_INT_DMA1 | TXP_INT_DMA0 | 568 TXP_INT_PCI_TABORT | TXP_INT_PCI_MABORT | TXP_INT_LATCH); 569 570 bus_dmamap_sync(sc->sc_dmat, sc->sc_host_dma.dma_map, 0, 571 sizeof(struct txp_hostvar), BUS_DMASYNC_POSTWRITE|BUS_DMASYNC_POSTREAD); 572 573 isr = READ_REG(sc, TXP_ISR); 574 while (isr) { 575 claimed = 1; 576 WRITE_REG(sc, TXP_ISR, isr); 577 578 if ((*sc->sc_rxhir.r_roff) != (*sc->sc_rxhir.r_woff)) 579 txp_rx_reclaim(sc, &sc->sc_rxhir, &sc->sc_rxhiring_dma); 580 if ((*sc->sc_rxlor.r_roff) != (*sc->sc_rxlor.r_woff)) 581 txp_rx_reclaim(sc, &sc->sc_rxlor, &sc->sc_rxloring_dma); 582 583 if (hv->hv_rx_buf_write_idx == hv->hv_rx_buf_read_idx) 584 txp_rxbuf_reclaim(sc); 585 586 if (sc->sc_txhir.r_cnt && (sc->sc_txhir.r_cons != 587 TXP_OFFSET2IDX(letoh32(*(sc->sc_txhir.r_off))))) 588 txp_tx_reclaim(sc, &sc->sc_txhir, &sc->sc_txhiring_dma); 589 590 if (sc->sc_txlor.r_cnt && (sc->sc_txlor.r_cons != 591 TXP_OFFSET2IDX(letoh32(*(sc->sc_txlor.r_off))))) 592 txp_tx_reclaim(sc, &sc->sc_txlor, &sc->sc_txloring_dma); 593 594 isr = READ_REG(sc, TXP_ISR); 595 } 596 597 bus_dmamap_sync(sc->sc_dmat, sc->sc_host_dma.dma_map, 0, 598 sizeof(struct txp_hostvar), BUS_DMASYNC_POSTWRITE|BUS_DMASYNC_POSTREAD); 599 600 /* unmask all interrupts */ 601 WRITE_REG(sc, TXP_IMR, TXP_INT_A2H_3); 602 603 txp_start(&sc->sc_arpcom.ac_if); 604 605 return (claimed); 606 } 607 608 void 609 txp_rx_reclaim(struct txp_softc *sc, struct txp_rx_ring *r, 610 struct txp_dma_alloc *dma) 611 { 612 struct ifnet *ifp = &sc->sc_arpcom.ac_if; 613 struct txp_rx_desc *rxd; 614 struct mbuf *m; 615 struct txp_swdesc *sd; 616 u_int32_t roff, woff; 617 int idx; 618 u_int16_t sumflags = 0; 619 620 roff = letoh32(*r->r_roff); 621 woff = letoh32(*r->r_woff); 622 idx = roff / sizeof(struct txp_rx_desc); 623 rxd = r->r_desc + idx; 624 625 while (roff != woff) { 626 627 bus_dmamap_sync(sc->sc_dmat, dma->dma_map, 628 idx * sizeof(struct txp_rx_desc), sizeof(struct txp_rx_desc), 629 BUS_DMASYNC_POSTREAD); 630 631 if (rxd->rx_flags & RX_FLAGS_ERROR) { 632 printf("%s: error 0x%x\n", sc->sc_dev.dv_xname, 633 letoh32(rxd->rx_stat)); 634 ifp->if_ierrors++; 635 goto next; 636 } 637 638 /* retrieve stashed pointer */ 639 bcopy((u_long *)&rxd->rx_vaddrlo, &sd, sizeof(sd)); 640 641 bus_dmamap_sync(sc->sc_dmat, sd->sd_map, 0, 642 sd->sd_map->dm_mapsize, BUS_DMASYNC_POSTREAD); 643 bus_dmamap_unload(sc->sc_dmat, sd->sd_map); 644 bus_dmamap_destroy(sc->sc_dmat, sd->sd_map); 645 m = sd->sd_mbuf; 646 free(sd, M_DEVBUF); 647 m->m_pkthdr.len = m->m_len = letoh16(rxd->rx_len); 648 649 #ifdef __STRICT_ALIGNMENT 650 { 651 /* 652 * XXX Nice chip, except it won't accept "off by 2" 653 * buffers, so we're force to copy. Supposedly 654 * this will be fixed in a newer firmware rev 655 * and this will be temporary. 656 */ 657 struct mbuf *mnew; 658 659 MGETHDR(mnew, M_DONTWAIT, MT_DATA); 660 if (mnew == NULL) { 661 m_freem(m); 662 goto next; 663 } 664 if (m->m_len > (MHLEN - 2)) { 665 MCLGET(mnew, M_DONTWAIT); 666 if (!(mnew->m_flags & M_EXT)) { 667 m_freem(mnew); 668 m_freem(m); 669 goto next; 670 } 671 } 672 mnew->m_pkthdr.rcvif = ifp; 673 mnew->m_pkthdr.len = mnew->m_len = m->m_len; 674 mnew->m_data += 2; 675 bcopy(m->m_data, mnew->m_data, m->m_len); 676 m_freem(m); 677 m = mnew; 678 } 679 #endif 680 681 #if NVLAN > 0 682 /* 683 * XXX Another firmware bug: the vlan encapsulation 684 * is always removed, even when we tell the card not 685 * to do that. Restore the vlan encapsulation below. 686 */ 687 if (rxd->rx_stat & htole32(RX_STAT_VLAN)) { 688 m->m_pkthdr.ether_vtag = ntohs(rxd->rx_vlan >> 16); 689 m->m_flags |= M_VLANTAG; 690 } 691 #endif 692 693 #if NBPFILTER > 0 694 /* 695 * Handle BPF listeners. Let the BPF user see the packet. 696 */ 697 if (ifp->if_bpf) 698 bpf_mtap_ether(ifp->if_bpf, m, BPF_DIRECTION_IN); 699 #endif 700 701 if (rxd->rx_stat & htole32(RX_STAT_IPCKSUMBAD)) 702 sumflags |= M_IPV4_CSUM_IN_BAD; 703 else if (rxd->rx_stat & htole32(RX_STAT_IPCKSUMGOOD)) 704 sumflags |= M_IPV4_CSUM_IN_OK; 705 706 if (rxd->rx_stat & htole32(RX_STAT_TCPCKSUMBAD)) 707 sumflags |= M_TCP_CSUM_IN_BAD; 708 else if (rxd->rx_stat & htole32(RX_STAT_TCPCKSUMGOOD)) 709 sumflags |= M_TCP_CSUM_IN_OK; 710 711 if (rxd->rx_stat & htole32(RX_STAT_UDPCKSUMBAD)) 712 sumflags |= M_UDP_CSUM_IN_BAD; 713 else if (rxd->rx_stat & htole32(RX_STAT_UDPCKSUMGOOD)) 714 sumflags |= M_UDP_CSUM_IN_OK; 715 716 m->m_pkthdr.csum_flags = sumflags; 717 718 ether_input_mbuf(ifp, m); 719 720 next: 721 bus_dmamap_sync(sc->sc_dmat, dma->dma_map, 722 idx * sizeof(struct txp_rx_desc), sizeof(struct txp_rx_desc), 723 BUS_DMASYNC_PREREAD); 724 725 roff += sizeof(struct txp_rx_desc); 726 if (roff == (RX_ENTRIES * sizeof(struct txp_rx_desc))) { 727 idx = 0; 728 roff = 0; 729 rxd = r->r_desc; 730 } else { 731 idx++; 732 rxd++; 733 } 734 woff = letoh32(*r->r_woff); 735 } 736 737 *r->r_roff = htole32(woff); 738 } 739 740 void 741 txp_rxbuf_reclaim(struct txp_softc *sc) 742 { 743 struct ifnet *ifp = &sc->sc_arpcom.ac_if; 744 struct txp_hostvar *hv = sc->sc_hostvar; 745 struct txp_rxbuf_desc *rbd; 746 struct txp_swdesc *sd; 747 u_int32_t i, end; 748 749 end = TXP_OFFSET2IDX(letoh32(hv->hv_rx_buf_read_idx)); 750 i = TXP_OFFSET2IDX(letoh32(hv->hv_rx_buf_write_idx)); 751 752 if (++i == RXBUF_ENTRIES) 753 i = 0; 754 755 rbd = sc->sc_rxbufs + i; 756 757 while (i != end) { 758 sd = (struct txp_swdesc *)malloc(sizeof(struct txp_swdesc), 759 M_DEVBUF, M_NOWAIT); 760 if (sd == NULL) 761 break; 762 763 MGETHDR(sd->sd_mbuf, M_DONTWAIT, MT_DATA); 764 if (sd->sd_mbuf == NULL) 765 goto err_sd; 766 767 MCLGET(sd->sd_mbuf, M_DONTWAIT); 768 if ((sd->sd_mbuf->m_flags & M_EXT) == 0) 769 goto err_mbuf; 770 sd->sd_mbuf->m_pkthdr.rcvif = ifp; 771 sd->sd_mbuf->m_pkthdr.len = sd->sd_mbuf->m_len = MCLBYTES; 772 if (bus_dmamap_create(sc->sc_dmat, TXP_MAX_PKTLEN, 1, 773 TXP_MAX_PKTLEN, 0, BUS_DMA_NOWAIT, &sd->sd_map)) 774 goto err_mbuf; 775 if (bus_dmamap_load_mbuf(sc->sc_dmat, sd->sd_map, sd->sd_mbuf, 776 BUS_DMA_NOWAIT)) { 777 bus_dmamap_destroy(sc->sc_dmat, sd->sd_map); 778 goto err_mbuf; 779 } 780 781 bus_dmamap_sync(sc->sc_dmat, sc->sc_rxbufring_dma.dma_map, 782 i * sizeof(struct txp_rxbuf_desc), 783 sizeof(struct txp_rxbuf_desc), BUS_DMASYNC_POSTWRITE); 784 785 /* stash away pointer */ 786 bcopy(&sd, (u_long *)&rbd->rb_vaddrlo, sizeof(sd)); 787 788 rbd->rb_paddrlo = ((u_int64_t)sd->sd_map->dm_segs[0].ds_addr) 789 & 0xffffffff; 790 rbd->rb_paddrhi = ((u_int64_t)sd->sd_map->dm_segs[0].ds_addr) 791 >> 32; 792 793 bus_dmamap_sync(sc->sc_dmat, sd->sd_map, 0, 794 sd->sd_map->dm_mapsize, BUS_DMASYNC_PREREAD); 795 796 bus_dmamap_sync(sc->sc_dmat, sc->sc_rxbufring_dma.dma_map, 797 i * sizeof(struct txp_rxbuf_desc), 798 sizeof(struct txp_rxbuf_desc), BUS_DMASYNC_PREWRITE); 799 800 hv->hv_rx_buf_write_idx = htole32(TXP_IDX2OFFSET(i)); 801 802 if (++i == RXBUF_ENTRIES) { 803 i = 0; 804 rbd = sc->sc_rxbufs; 805 } else 806 rbd++; 807 } 808 return; 809 810 err_mbuf: 811 m_freem(sd->sd_mbuf); 812 err_sd: 813 free(sd, M_DEVBUF); 814 } 815 816 /* 817 * Reclaim mbufs and entries from a transmit ring. 818 */ 819 void 820 txp_tx_reclaim(struct txp_softc *sc, struct txp_tx_ring *r, 821 struct txp_dma_alloc *dma) 822 { 823 struct ifnet *ifp = &sc->sc_arpcom.ac_if; 824 u_int32_t idx = TXP_OFFSET2IDX(letoh32(*(r->r_off))); 825 u_int32_t cons = r->r_cons, cnt = r->r_cnt; 826 struct txp_tx_desc *txd = r->r_desc + cons; 827 struct txp_swdesc *sd = sc->sc_txd + cons; 828 struct mbuf *m; 829 830 while (cons != idx) { 831 if (cnt == 0) 832 break; 833 834 bus_dmamap_sync(sc->sc_dmat, dma->dma_map, 835 cons * sizeof(struct txp_tx_desc), 836 sizeof(struct txp_tx_desc), 837 BUS_DMASYNC_POSTWRITE); 838 839 if ((txd->tx_flags & TX_FLAGS_TYPE_M) == 840 TX_FLAGS_TYPE_DATA) { 841 bus_dmamap_sync(sc->sc_dmat, sd->sd_map, 0, 842 sd->sd_map->dm_mapsize, BUS_DMASYNC_POSTWRITE); 843 bus_dmamap_unload(sc->sc_dmat, sd->sd_map); 844 m = sd->sd_mbuf; 845 if (m != NULL) { 846 m_freem(m); 847 txd->tx_addrlo = 0; 848 txd->tx_addrhi = 0; 849 ifp->if_opackets++; 850 } 851 } 852 ifp->if_flags &= ~IFF_OACTIVE; 853 854 if (++cons == TX_ENTRIES) { 855 txd = r->r_desc; 856 cons = 0; 857 sd = sc->sc_txd; 858 } else { 859 txd++; 860 sd++; 861 } 862 863 cnt--; 864 } 865 866 r->r_cons = cons; 867 r->r_cnt = cnt; 868 if (cnt == 0) 869 ifp->if_timer = 0; 870 } 871 872 void 873 txp_shutdown(void *vsc) 874 { 875 struct txp_softc *sc = (struct txp_softc *)vsc; 876 877 /* mask all interrupts */ 878 WRITE_REG(sc, TXP_IMR, 879 TXP_INT_SELF | TXP_INT_PCI_TABORT | TXP_INT_PCI_MABORT | 880 TXP_INT_DMA3 | TXP_INT_DMA2 | TXP_INT_DMA1 | TXP_INT_DMA0 | 881 TXP_INT_LATCH); 882 883 txp_command(sc, TXP_CMD_TX_DISABLE, 0, 0, 0, NULL, NULL, NULL, 0); 884 txp_command(sc, TXP_CMD_RX_DISABLE, 0, 0, 0, NULL, NULL, NULL, 0); 885 txp_command(sc, TXP_CMD_HALT, 0, 0, 0, NULL, NULL, NULL, 0); 886 } 887 888 int 889 txp_alloc_rings(struct txp_softc *sc) 890 { 891 struct ifnet *ifp = &sc->sc_arpcom.ac_if; 892 struct txp_boot_record *boot; 893 struct txp_swdesc *sd; 894 u_int32_t r; 895 int i, j; 896 897 /* boot record */ 898 if (txp_dma_malloc(sc, sizeof(struct txp_boot_record), &sc->sc_boot_dma, 899 BUS_DMA_COHERENT)) { 900 printf("can't allocate boot record\n"); 901 return (-1); 902 } 903 boot = (struct txp_boot_record *)sc->sc_boot_dma.dma_vaddr; 904 bzero(boot, sizeof(*boot)); 905 sc->sc_boot = boot; 906 907 /* host variables */ 908 if (txp_dma_malloc(sc, sizeof(struct txp_hostvar), &sc->sc_host_dma, 909 BUS_DMA_COHERENT)) { 910 printf("can't allocate host ring\n"); 911 goto bail_boot; 912 } 913 bzero(sc->sc_host_dma.dma_vaddr, sizeof(struct txp_hostvar)); 914 boot->br_hostvar_lo = htole32(sc->sc_host_dma.dma_paddr & 0xffffffff); 915 boot->br_hostvar_hi = htole32(sc->sc_host_dma.dma_paddr >> 32); 916 sc->sc_hostvar = (struct txp_hostvar *)sc->sc_host_dma.dma_vaddr; 917 918 /* high priority tx ring */ 919 if (txp_dma_malloc(sc, sizeof(struct txp_tx_desc) * TX_ENTRIES, 920 &sc->sc_txhiring_dma, BUS_DMA_COHERENT)) { 921 printf("can't allocate high tx ring\n"); 922 goto bail_host; 923 } 924 bzero(sc->sc_txhiring_dma.dma_vaddr, sizeof(struct txp_tx_desc) * TX_ENTRIES); 925 boot->br_txhipri_lo = htole32(sc->sc_txhiring_dma.dma_paddr & 0xffffffff); 926 boot->br_txhipri_hi = htole32(sc->sc_txhiring_dma.dma_paddr >> 32); 927 boot->br_txhipri_siz = htole32(TX_ENTRIES * sizeof(struct txp_tx_desc)); 928 sc->sc_txhir.r_reg = TXP_H2A_1; 929 sc->sc_txhir.r_desc = (struct txp_tx_desc *)sc->sc_txhiring_dma.dma_vaddr; 930 sc->sc_txhir.r_cons = sc->sc_txhir.r_prod = sc->sc_txhir.r_cnt = 0; 931 sc->sc_txhir.r_off = &sc->sc_hostvar->hv_tx_hi_desc_read_idx; 932 for (i = 0; i < TX_ENTRIES; i++) { 933 if (bus_dmamap_create(sc->sc_dmat, TXP_MAX_PKTLEN, 934 TX_ENTRIES - 4, TXP_MAX_SEGLEN, 0, 935 BUS_DMA_NOWAIT, &sc->sc_txd[i].sd_map) != 0) { 936 for (j = 0; j < i; j++) { 937 bus_dmamap_destroy(sc->sc_dmat, 938 sc->sc_txd[j].sd_map); 939 sc->sc_txd[j].sd_map = NULL; 940 } 941 goto bail_txhiring; 942 } 943 } 944 945 /* low priority tx ring */ 946 if (txp_dma_malloc(sc, sizeof(struct txp_tx_desc) * TX_ENTRIES, 947 &sc->sc_txloring_dma, BUS_DMA_COHERENT)) { 948 printf("can't allocate low tx ring\n"); 949 goto bail_txhiring; 950 } 951 bzero(sc->sc_txloring_dma.dma_vaddr, sizeof(struct txp_tx_desc) * TX_ENTRIES); 952 boot->br_txlopri_lo = htole32(sc->sc_txloring_dma.dma_paddr & 0xffffffff); 953 boot->br_txlopri_hi = htole32(sc->sc_txloring_dma.dma_paddr >> 32); 954 boot->br_txlopri_siz = htole32(TX_ENTRIES * sizeof(struct txp_tx_desc)); 955 sc->sc_txlor.r_reg = TXP_H2A_3; 956 sc->sc_txlor.r_desc = (struct txp_tx_desc *)sc->sc_txloring_dma.dma_vaddr; 957 sc->sc_txlor.r_cons = sc->sc_txlor.r_prod = sc->sc_txlor.r_cnt = 0; 958 sc->sc_txlor.r_off = &sc->sc_hostvar->hv_tx_lo_desc_read_idx; 959 960 /* high priority rx ring */ 961 if (txp_dma_malloc(sc, sizeof(struct txp_rx_desc) * RX_ENTRIES, 962 &sc->sc_rxhiring_dma, BUS_DMA_COHERENT)) { 963 printf("can't allocate high rx ring\n"); 964 goto bail_txloring; 965 } 966 bzero(sc->sc_rxhiring_dma.dma_vaddr, sizeof(struct txp_rx_desc) * RX_ENTRIES); 967 boot->br_rxhipri_lo = htole32(sc->sc_rxhiring_dma.dma_paddr & 0xffffffff); 968 boot->br_rxhipri_hi = htole32(sc->sc_rxhiring_dma.dma_paddr >> 32); 969 boot->br_rxhipri_siz = htole32(RX_ENTRIES * sizeof(struct txp_rx_desc)); 970 sc->sc_rxhir.r_desc = 971 (struct txp_rx_desc *)sc->sc_rxhiring_dma.dma_vaddr; 972 sc->sc_rxhir.r_roff = &sc->sc_hostvar->hv_rx_hi_read_idx; 973 sc->sc_rxhir.r_woff = &sc->sc_hostvar->hv_rx_hi_write_idx; 974 bus_dmamap_sync(sc->sc_dmat, sc->sc_rxhiring_dma.dma_map, 975 0, sc->sc_rxhiring_dma.dma_map->dm_mapsize, BUS_DMASYNC_PREREAD); 976 977 /* low priority ring */ 978 if (txp_dma_malloc(sc, sizeof(struct txp_rx_desc) * RX_ENTRIES, 979 &sc->sc_rxloring_dma, BUS_DMA_COHERENT)) { 980 printf("can't allocate low rx ring\n"); 981 goto bail_rxhiring; 982 } 983 bzero(sc->sc_rxloring_dma.dma_vaddr, sizeof(struct txp_rx_desc) * RX_ENTRIES); 984 boot->br_rxlopri_lo = htole32(sc->sc_rxloring_dma.dma_paddr & 0xffffffff); 985 boot->br_rxlopri_hi = htole32(sc->sc_rxloring_dma.dma_paddr >> 32); 986 boot->br_rxlopri_siz = htole32(RX_ENTRIES * sizeof(struct txp_rx_desc)); 987 sc->sc_rxlor.r_desc = 988 (struct txp_rx_desc *)sc->sc_rxloring_dma.dma_vaddr; 989 sc->sc_rxlor.r_roff = &sc->sc_hostvar->hv_rx_lo_read_idx; 990 sc->sc_rxlor.r_woff = &sc->sc_hostvar->hv_rx_lo_write_idx; 991 bus_dmamap_sync(sc->sc_dmat, sc->sc_rxloring_dma.dma_map, 992 0, sc->sc_rxloring_dma.dma_map->dm_mapsize, BUS_DMASYNC_PREREAD); 993 994 /* command ring */ 995 if (txp_dma_malloc(sc, sizeof(struct txp_cmd_desc) * CMD_ENTRIES, 996 &sc->sc_cmdring_dma, BUS_DMA_COHERENT)) { 997 printf("can't allocate command ring\n"); 998 goto bail_rxloring; 999 } 1000 bzero(sc->sc_cmdring_dma.dma_vaddr, sizeof(struct txp_cmd_desc) * CMD_ENTRIES); 1001 boot->br_cmd_lo = htole32(sc->sc_cmdring_dma.dma_paddr & 0xffffffff); 1002 boot->br_cmd_hi = htole32(sc->sc_cmdring_dma.dma_paddr >> 32); 1003 boot->br_cmd_siz = htole32(CMD_ENTRIES * sizeof(struct txp_cmd_desc)); 1004 sc->sc_cmdring.base = (struct txp_cmd_desc *)sc->sc_cmdring_dma.dma_vaddr; 1005 sc->sc_cmdring.size = CMD_ENTRIES * sizeof(struct txp_cmd_desc); 1006 sc->sc_cmdring.lastwrite = 0; 1007 1008 /* response ring */ 1009 if (txp_dma_malloc(sc, sizeof(struct txp_rsp_desc) * RSP_ENTRIES, 1010 &sc->sc_rspring_dma, BUS_DMA_COHERENT)) { 1011 printf("can't allocate response ring\n"); 1012 goto bail_cmdring; 1013 } 1014 bzero(sc->sc_rspring_dma.dma_vaddr, sizeof(struct txp_rsp_desc) * RSP_ENTRIES); 1015 boot->br_resp_lo = htole32(sc->sc_rspring_dma.dma_paddr & 0xffffffff); 1016 boot->br_resp_hi = htole32(sc->sc_rspring_dma.dma_paddr >> 32); 1017 boot->br_resp_siz = htole32(CMD_ENTRIES * sizeof(struct txp_rsp_desc)); 1018 sc->sc_rspring.base = (struct txp_rsp_desc *)sc->sc_rspring_dma.dma_vaddr; 1019 sc->sc_rspring.size = RSP_ENTRIES * sizeof(struct txp_rsp_desc); 1020 sc->sc_rspring.lastwrite = 0; 1021 1022 /* receive buffer ring */ 1023 if (txp_dma_malloc(sc, sizeof(struct txp_rxbuf_desc) * RXBUF_ENTRIES, 1024 &sc->sc_rxbufring_dma, BUS_DMA_COHERENT)) { 1025 printf("can't allocate rx buffer ring\n"); 1026 goto bail_rspring; 1027 } 1028 bzero(sc->sc_rxbufring_dma.dma_vaddr, sizeof(struct txp_rxbuf_desc) * RXBUF_ENTRIES); 1029 boot->br_rxbuf_lo = htole32(sc->sc_rxbufring_dma.dma_paddr & 0xffffffff); 1030 boot->br_rxbuf_hi = htole32(sc->sc_rxbufring_dma.dma_paddr >> 32); 1031 boot->br_rxbuf_siz = htole32(RXBUF_ENTRIES * sizeof(struct txp_rxbuf_desc)); 1032 sc->sc_rxbufs = (struct txp_rxbuf_desc *)sc->sc_rxbufring_dma.dma_vaddr; 1033 for (i = 0; i < RXBUF_ENTRIES; i++) { 1034 sd = (struct txp_swdesc *)malloc(sizeof(struct txp_swdesc), 1035 M_DEVBUF, M_NOWAIT); 1036 1037 /* stash away pointer */ 1038 bcopy(&sd, (u_long *)&sc->sc_rxbufs[i].rb_vaddrlo, sizeof(sd)); 1039 1040 if (sd == NULL) 1041 break; 1042 1043 MGETHDR(sd->sd_mbuf, M_DONTWAIT, MT_DATA); 1044 if (sd->sd_mbuf == NULL) { 1045 goto bail_rxbufring; 1046 } 1047 1048 MCLGET(sd->sd_mbuf, M_DONTWAIT); 1049 if ((sd->sd_mbuf->m_flags & M_EXT) == 0) { 1050 goto bail_rxbufring; 1051 } 1052 sd->sd_mbuf->m_pkthdr.len = sd->sd_mbuf->m_len = MCLBYTES; 1053 sd->sd_mbuf->m_pkthdr.rcvif = ifp; 1054 if (bus_dmamap_create(sc->sc_dmat, TXP_MAX_PKTLEN, 1, 1055 TXP_MAX_PKTLEN, 0, BUS_DMA_NOWAIT, &sd->sd_map)) { 1056 goto bail_rxbufring; 1057 } 1058 if (bus_dmamap_load_mbuf(sc->sc_dmat, sd->sd_map, sd->sd_mbuf, 1059 BUS_DMA_NOWAIT)) { 1060 bus_dmamap_destroy(sc->sc_dmat, sd->sd_map); 1061 goto bail_rxbufring; 1062 } 1063 bus_dmamap_sync(sc->sc_dmat, sd->sd_map, 0, 1064 sd->sd_map->dm_mapsize, BUS_DMASYNC_PREREAD); 1065 1066 sc->sc_rxbufs[i].rb_paddrlo = 1067 ((u_int64_t)sd->sd_map->dm_segs[0].ds_addr) & 0xffffffff; 1068 sc->sc_rxbufs[i].rb_paddrhi = 1069 ((u_int64_t)sd->sd_map->dm_segs[0].ds_addr) >> 32; 1070 } 1071 bus_dmamap_sync(sc->sc_dmat, sc->sc_rxbufring_dma.dma_map, 1072 0, sc->sc_rxbufring_dma.dma_map->dm_mapsize, 1073 BUS_DMASYNC_PREWRITE); 1074 sc->sc_hostvar->hv_rx_buf_write_idx = htole32((RXBUF_ENTRIES - 1) * 1075 sizeof(struct txp_rxbuf_desc)); 1076 1077 /* zero dma */ 1078 if (txp_dma_malloc(sc, sizeof(u_int32_t), &sc->sc_zero_dma, 1079 BUS_DMA_COHERENT)) { 1080 printf("can't allocate response ring\n"); 1081 goto bail_rxbufring; 1082 } 1083 bzero(sc->sc_zero_dma.dma_vaddr, sizeof(u_int32_t)); 1084 boot->br_zero_lo = htole32(sc->sc_zero_dma.dma_paddr & 0xffffffff); 1085 boot->br_zero_hi = htole32(sc->sc_zero_dma.dma_paddr >> 32); 1086 1087 /* See if it's waiting for boot, and try to boot it */ 1088 for (i = 0; i < 10000; i++) { 1089 r = READ_REG(sc, TXP_A2H_0); 1090 if (r == STAT_WAITING_FOR_BOOT) 1091 break; 1092 DELAY(50); 1093 } 1094 if (r != STAT_WAITING_FOR_BOOT) { 1095 printf("not waiting for boot\n"); 1096 goto bail; 1097 } 1098 WRITE_REG(sc, TXP_H2A_2, sc->sc_boot_dma.dma_paddr >> 32); 1099 WRITE_REG(sc, TXP_H2A_1, sc->sc_boot_dma.dma_paddr & 0xffffffff); 1100 WRITE_REG(sc, TXP_H2A_0, TXP_BOOTCMD_REGISTER_BOOT_RECORD); 1101 1102 /* See if it booted */ 1103 for (i = 0; i < 10000; i++) { 1104 r = READ_REG(sc, TXP_A2H_0); 1105 if (r == STAT_RUNNING) 1106 break; 1107 DELAY(50); 1108 } 1109 if (r != STAT_RUNNING) { 1110 printf("fw not running\n"); 1111 goto bail; 1112 } 1113 1114 /* Clear TX and CMD ring write registers */ 1115 WRITE_REG(sc, TXP_H2A_1, TXP_BOOTCMD_NULL); 1116 WRITE_REG(sc, TXP_H2A_2, TXP_BOOTCMD_NULL); 1117 WRITE_REG(sc, TXP_H2A_3, TXP_BOOTCMD_NULL); 1118 WRITE_REG(sc, TXP_H2A_0, TXP_BOOTCMD_NULL); 1119 1120 return (0); 1121 1122 bail: 1123 txp_dma_free(sc, &sc->sc_zero_dma); 1124 bail_rxbufring: 1125 for (i = 0; i < RXBUF_ENTRIES; i++) { 1126 bcopy((u_long *)&sc->sc_rxbufs[i].rb_vaddrlo, &sd, sizeof(sd)); 1127 if (sd) 1128 free(sd, M_DEVBUF); 1129 } 1130 txp_dma_free(sc, &sc->sc_rxbufring_dma); 1131 bail_rspring: 1132 txp_dma_free(sc, &sc->sc_rspring_dma); 1133 bail_cmdring: 1134 txp_dma_free(sc, &sc->sc_cmdring_dma); 1135 bail_rxloring: 1136 txp_dma_free(sc, &sc->sc_rxloring_dma); 1137 bail_rxhiring: 1138 txp_dma_free(sc, &sc->sc_rxhiring_dma); 1139 bail_txloring: 1140 txp_dma_free(sc, &sc->sc_txloring_dma); 1141 bail_txhiring: 1142 txp_dma_free(sc, &sc->sc_txhiring_dma); 1143 bail_host: 1144 txp_dma_free(sc, &sc->sc_host_dma); 1145 bail_boot: 1146 txp_dma_free(sc, &sc->sc_boot_dma); 1147 return (-1); 1148 } 1149 1150 int 1151 txp_dma_malloc(struct txp_softc *sc, bus_size_t size, 1152 struct txp_dma_alloc *dma, int mapflags) 1153 { 1154 int r; 1155 1156 if ((r = bus_dmamem_alloc(sc->sc_dmat, size, PAGE_SIZE, 0, 1157 &dma->dma_seg, 1, &dma->dma_nseg, 0)) != 0) 1158 goto fail_0; 1159 1160 if ((r = bus_dmamem_map(sc->sc_dmat, &dma->dma_seg, dma->dma_nseg, 1161 size, &dma->dma_vaddr, mapflags | BUS_DMA_NOWAIT)) != 0) 1162 goto fail_1; 1163 1164 if ((r = bus_dmamap_create(sc->sc_dmat, size, 1, size, 0, 1165 BUS_DMA_NOWAIT, &dma->dma_map)) != 0) 1166 goto fail_2; 1167 1168 if ((r = bus_dmamap_load(sc->sc_dmat, dma->dma_map, dma->dma_vaddr, 1169 size, NULL, BUS_DMA_NOWAIT)) != 0) 1170 goto fail_3; 1171 1172 dma->dma_paddr = dma->dma_map->dm_segs[0].ds_addr; 1173 return (0); 1174 1175 fail_3: 1176 bus_dmamap_destroy(sc->sc_dmat, dma->dma_map); 1177 fail_2: 1178 bus_dmamem_unmap(sc->sc_dmat, dma->dma_vaddr, size); 1179 fail_1: 1180 bus_dmamem_free(sc->sc_dmat, &dma->dma_seg, dma->dma_nseg); 1181 fail_0: 1182 return (r); 1183 } 1184 1185 void 1186 txp_dma_free(struct txp_softc *sc, struct txp_dma_alloc *dma) 1187 { 1188 bus_dmamap_unload(sc->sc_dmat, dma->dma_map); 1189 bus_dmamem_unmap(sc->sc_dmat, dma->dma_vaddr, dma->dma_map->dm_mapsize); 1190 bus_dmamem_free(sc->sc_dmat, &dma->dma_seg, dma->dma_nseg); 1191 bus_dmamap_destroy(sc->sc_dmat, dma->dma_map); 1192 } 1193 1194 int 1195 txp_ioctl(struct ifnet *ifp, u_long command, caddr_t data) 1196 { 1197 struct txp_softc *sc = ifp->if_softc; 1198 struct ifaddr *ifa = (struct ifaddr *) data; 1199 struct ifreq *ifr = (struct ifreq *) data; 1200 int s, error = 0; 1201 1202 s = splnet(); 1203 1204 switch(command) { 1205 case SIOCSIFADDR: 1206 ifp->if_flags |= IFF_UP; 1207 switch (ifa->ifa_addr->sa_family) { 1208 #ifdef INET 1209 case AF_INET: 1210 txp_init(sc); 1211 arp_ifinit(&sc->sc_arpcom, ifa); 1212 break; 1213 #endif /* INET */ 1214 default: 1215 txp_init(sc); 1216 break; 1217 } 1218 break; 1219 1220 case SIOCSIFFLAGS: 1221 if (ifp->if_flags & IFF_UP) { 1222 txp_init(sc); 1223 } else { 1224 if (ifp->if_flags & IFF_RUNNING) 1225 txp_stop(sc); 1226 } 1227 break; 1228 1229 case SIOCGIFMEDIA: 1230 case SIOCSIFMEDIA: 1231 error = ifmedia_ioctl(ifp, ifr, &sc->sc_ifmedia, command); 1232 break; 1233 1234 default: 1235 error = ether_ioctl(ifp, &sc->sc_arpcom, command, data); 1236 } 1237 1238 if (error == ENETRESET) { 1239 if (ifp->if_flags & IFF_RUNNING) 1240 txp_set_filter(sc); 1241 error = 0; 1242 } 1243 1244 splx(s); 1245 return(error); 1246 } 1247 1248 void 1249 txp_init(struct txp_softc *sc) 1250 { 1251 struct ifnet *ifp = &sc->sc_arpcom.ac_if; 1252 int s; 1253 1254 txp_stop(sc); 1255 1256 s = splnet(); 1257 1258 txp_set_filter(sc); 1259 1260 txp_command(sc, TXP_CMD_TX_ENABLE, 0, 0, 0, NULL, NULL, NULL, 1); 1261 txp_command(sc, TXP_CMD_RX_ENABLE, 0, 0, 0, NULL, NULL, NULL, 1); 1262 1263 WRITE_REG(sc, TXP_IER, TXP_INT_RESERVED | TXP_INT_SELF | 1264 TXP_INT_A2H_7 | TXP_INT_A2H_6 | TXP_INT_A2H_5 | TXP_INT_A2H_4 | 1265 TXP_INT_A2H_2 | TXP_INT_A2H_1 | TXP_INT_A2H_0 | 1266 TXP_INT_DMA3 | TXP_INT_DMA2 | TXP_INT_DMA1 | TXP_INT_DMA0 | 1267 TXP_INT_PCI_TABORT | TXP_INT_PCI_MABORT | TXP_INT_LATCH); 1268 WRITE_REG(sc, TXP_IMR, TXP_INT_A2H_3); 1269 1270 ifp->if_flags |= IFF_RUNNING; 1271 ifp->if_flags &= ~IFF_OACTIVE; 1272 1273 if (!timeout_pending(&sc->sc_tick)) 1274 timeout_add_sec(&sc->sc_tick, 1); 1275 1276 splx(s); 1277 } 1278 1279 void 1280 txp_tick(void *vsc) 1281 { 1282 struct txp_softc *sc = vsc; 1283 struct ifnet *ifp = &sc->sc_arpcom.ac_if; 1284 struct txp_rsp_desc *rsp = NULL; 1285 struct txp_ext_desc *ext; 1286 int s; 1287 1288 s = splnet(); 1289 txp_rxbuf_reclaim(sc); 1290 1291 if (txp_command2(sc, TXP_CMD_READ_STATISTICS, 0, 0, 0, NULL, 0, 1292 &rsp, 1)) 1293 goto out; 1294 if (rsp->rsp_numdesc != 6) 1295 goto out; 1296 if (txp_command(sc, TXP_CMD_CLEAR_STATISTICS, 0, 0, 0, 1297 NULL, NULL, NULL, 1)) 1298 goto out; 1299 ext = (struct txp_ext_desc *)(rsp + 1); 1300 1301 ifp->if_ierrors += ext[3].ext_2 + ext[3].ext_3 + ext[3].ext_4 + 1302 ext[4].ext_1 + ext[4].ext_4; 1303 ifp->if_oerrors += ext[0].ext_1 + ext[1].ext_1 + ext[1].ext_4 + 1304 ext[2].ext_1; 1305 ifp->if_collisions += ext[0].ext_2 + ext[0].ext_3 + ext[1].ext_2 + 1306 ext[1].ext_3; 1307 ifp->if_opackets += rsp->rsp_par2; 1308 ifp->if_ipackets += ext[2].ext_3; 1309 1310 out: 1311 if (rsp != NULL) 1312 free(rsp, M_DEVBUF); 1313 1314 splx(s); 1315 timeout_add_sec(&sc->sc_tick, 1); 1316 } 1317 1318 void 1319 txp_start(struct ifnet *ifp) 1320 { 1321 struct txp_softc *sc = ifp->if_softc; 1322 struct txp_tx_ring *r = &sc->sc_txhir; 1323 struct txp_tx_desc *txd; 1324 int txdidx; 1325 struct txp_frag_desc *fxd; 1326 struct mbuf *m, *mnew; 1327 struct txp_swdesc *sd; 1328 u_int32_t firstprod, firstcnt, prod, cnt, i; 1329 1330 if ((ifp->if_flags & (IFF_RUNNING | IFF_OACTIVE)) != IFF_RUNNING) 1331 return; 1332 1333 prod = r->r_prod; 1334 cnt = r->r_cnt; 1335 1336 while (1) { 1337 IFQ_POLL(&ifp->if_snd, m); 1338 if (m == NULL) 1339 break; 1340 mnew = NULL; 1341 1342 firstprod = prod; 1343 firstcnt = cnt; 1344 1345 sd = sc->sc_txd + prod; 1346 sd->sd_mbuf = m; 1347 1348 if (bus_dmamap_load_mbuf(sc->sc_dmat, sd->sd_map, m, 1349 BUS_DMA_NOWAIT)) { 1350 MGETHDR(mnew, M_DONTWAIT, MT_DATA); 1351 if (mnew == NULL) 1352 goto oactive1; 1353 if (m->m_pkthdr.len > MHLEN) { 1354 MCLGET(mnew, M_DONTWAIT); 1355 if ((mnew->m_flags & M_EXT) == 0) { 1356 m_freem(mnew); 1357 goto oactive1; 1358 } 1359 } 1360 m_copydata(m, 0, m->m_pkthdr.len, mtod(mnew, caddr_t)); 1361 mnew->m_pkthdr.len = mnew->m_len = m->m_pkthdr.len; 1362 IFQ_DEQUEUE(&ifp->if_snd, m); 1363 m_freem(m); 1364 m = mnew; 1365 if (bus_dmamap_load_mbuf(sc->sc_dmat, sd->sd_map, m, 1366 BUS_DMA_NOWAIT)) 1367 goto oactive1; 1368 } 1369 1370 if ((TX_ENTRIES - cnt) < 4) 1371 goto oactive; 1372 1373 txd = r->r_desc + prod; 1374 txdidx = prod; 1375 txd->tx_flags = TX_FLAGS_TYPE_DATA; 1376 txd->tx_numdesc = 0; 1377 txd->tx_addrlo = 0; 1378 txd->tx_addrhi = 0; 1379 txd->tx_totlen = m->m_pkthdr.len; 1380 txd->tx_pflags = 0; 1381 txd->tx_numdesc = sd->sd_map->dm_nsegs; 1382 1383 if (++prod == TX_ENTRIES) 1384 prod = 0; 1385 1386 if (++cnt >= (TX_ENTRIES - 4)) 1387 goto oactive; 1388 1389 #if NVLAN > 0 1390 if (m->m_flags & M_VLANTAG) { 1391 txd->tx_pflags = TX_PFLAGS_VLAN | 1392 (htons(m->m_pkthdr.ether_vtag) << TX_PFLAGS_VLANTAG_S); 1393 } 1394 #endif 1395 1396 if (m->m_pkthdr.csum_flags & M_IPV4_CSUM_OUT) 1397 txd->tx_pflags |= TX_PFLAGS_IPCKSUM; 1398 #ifdef TRY_TX_TCP_CSUM 1399 if (m->m_pkthdr.csum_flags & M_TCPV4_CSUM_OUT) 1400 txd->tx_pflags |= TX_PFLAGS_TCPCKSUM; 1401 #endif 1402 #ifdef TRY_TX_UDP_CSUM 1403 if (m->m_pkthdr.csum_flags & M_UDPV4_CSUM_OUT) 1404 txd->tx_pflags |= TX_PFLAGS_UDPCKSUM; 1405 #endif 1406 1407 bus_dmamap_sync(sc->sc_dmat, sd->sd_map, 0, 1408 sd->sd_map->dm_mapsize, BUS_DMASYNC_PREWRITE); 1409 1410 fxd = (struct txp_frag_desc *)(r->r_desc + prod); 1411 for (i = 0; i < sd->sd_map->dm_nsegs; i++) { 1412 if (++cnt >= (TX_ENTRIES - 4)) { 1413 bus_dmamap_sync(sc->sc_dmat, sd->sd_map, 1414 0, sd->sd_map->dm_mapsize, 1415 BUS_DMASYNC_POSTWRITE); 1416 goto oactive; 1417 } 1418 1419 fxd->frag_flags = FRAG_FLAGS_TYPE_FRAG | 1420 FRAG_FLAGS_VALID; 1421 fxd->frag_rsvd1 = 0; 1422 fxd->frag_len = sd->sd_map->dm_segs[i].ds_len; 1423 fxd->frag_addrlo = 1424 ((u_int64_t)sd->sd_map->dm_segs[i].ds_addr) & 1425 0xffffffff; 1426 fxd->frag_addrhi = 1427 ((u_int64_t)sd->sd_map->dm_segs[i].ds_addr) >> 1428 32; 1429 fxd->frag_rsvd2 = 0; 1430 1431 bus_dmamap_sync(sc->sc_dmat, 1432 sc->sc_txhiring_dma.dma_map, 1433 prod * sizeof(struct txp_frag_desc), 1434 sizeof(struct txp_frag_desc), BUS_DMASYNC_PREWRITE); 1435 1436 if (++prod == TX_ENTRIES) { 1437 fxd = (struct txp_frag_desc *)r->r_desc; 1438 prod = 0; 1439 } else 1440 fxd++; 1441 1442 } 1443 1444 /* 1445 * if mnew isn't NULL, we already dequeued and copied 1446 * the packet. 1447 */ 1448 if (mnew == NULL) 1449 IFQ_DEQUEUE(&ifp->if_snd, m); 1450 1451 ifp->if_timer = 5; 1452 1453 #if NBPFILTER > 0 1454 if (ifp->if_bpf) 1455 bpf_mtap_ether(ifp->if_bpf, m, BPF_DIRECTION_OUT); 1456 #endif 1457 1458 txd->tx_flags |= TX_FLAGS_VALID; 1459 bus_dmamap_sync(sc->sc_dmat, sc->sc_txhiring_dma.dma_map, 1460 txdidx * sizeof(struct txp_tx_desc), 1461 sizeof(struct txp_tx_desc), BUS_DMASYNC_PREWRITE); 1462 1463 #if 0 1464 { 1465 struct mbuf *mx; 1466 int i; 1467 1468 printf("txd: flags 0x%x ndesc %d totlen %d pflags 0x%x\n", 1469 txd->tx_flags, txd->tx_numdesc, txd->tx_totlen, 1470 txd->tx_pflags); 1471 for (mx = m; mx != NULL; mx = mx->m_next) { 1472 for (i = 0; i < mx->m_len; i++) { 1473 printf(":%02x", 1474 (u_int8_t)m->m_data[i]); 1475 } 1476 } 1477 printf("\n"); 1478 } 1479 #endif 1480 1481 WRITE_REG(sc, r->r_reg, TXP_IDX2OFFSET(prod)); 1482 } 1483 1484 r->r_prod = prod; 1485 r->r_cnt = cnt; 1486 return; 1487 1488 oactive: 1489 bus_dmamap_unload(sc->sc_dmat, sd->sd_map); 1490 oactive1: 1491 ifp->if_flags |= IFF_OACTIVE; 1492 r->r_prod = firstprod; 1493 r->r_cnt = firstcnt; 1494 } 1495 1496 /* 1497 * Handle simple commands sent to the typhoon 1498 */ 1499 int 1500 txp_command(struct txp_softc *sc, u_int16_t id, u_int16_t in1, 1501 u_int32_t in2, u_int32_t in3, u_int16_t *out1, u_int32_t *out2, 1502 u_int32_t *out3, int wait) 1503 { 1504 struct txp_rsp_desc *rsp = NULL; 1505 1506 if (txp_command2(sc, id, in1, in2, in3, NULL, 0, &rsp, wait)) 1507 return (-1); 1508 1509 if (!wait) 1510 return (0); 1511 1512 if (out1 != NULL) 1513 *out1 = letoh16(rsp->rsp_par1); 1514 if (out2 != NULL) 1515 *out2 = letoh32(rsp->rsp_par2); 1516 if (out3 != NULL) 1517 *out3 = letoh32(rsp->rsp_par3); 1518 free(rsp, M_DEVBUF); 1519 return (0); 1520 } 1521 1522 int 1523 txp_command2(struct txp_softc *sc, u_int16_t id, u_int16_t in1, 1524 u_int32_t in2, u_int32_t in3, struct txp_ext_desc *in_extp, 1525 u_int8_t in_extn,struct txp_rsp_desc **rspp, int wait) 1526 { 1527 struct txp_hostvar *hv = sc->sc_hostvar; 1528 struct txp_cmd_desc *cmd; 1529 struct txp_ext_desc *ext; 1530 u_int32_t idx, i; 1531 u_int16_t seq; 1532 1533 if (txp_cmd_desc_numfree(sc) < (in_extn + 1)) { 1534 printf("%s: no free cmd descriptors\n", TXP_DEVNAME(sc)); 1535 return (-1); 1536 } 1537 1538 idx = sc->sc_cmdring.lastwrite; 1539 cmd = (struct txp_cmd_desc *)(((u_int8_t *)sc->sc_cmdring.base) + idx); 1540 bzero(cmd, sizeof(*cmd)); 1541 1542 cmd->cmd_numdesc = in_extn; 1543 seq = sc->sc_seq++; 1544 cmd->cmd_seq = htole16(seq); 1545 cmd->cmd_id = htole16(id); 1546 cmd->cmd_par1 = htole16(in1); 1547 cmd->cmd_par2 = htole32(in2); 1548 cmd->cmd_par3 = htole32(in3); 1549 cmd->cmd_flags = CMD_FLAGS_TYPE_CMD | 1550 (wait ? CMD_FLAGS_RESP : 0) | CMD_FLAGS_VALID; 1551 1552 idx += sizeof(struct txp_cmd_desc); 1553 if (idx == sc->sc_cmdring.size) 1554 idx = 0; 1555 1556 for (i = 0; i < in_extn; i++) { 1557 ext = (struct txp_ext_desc *)(((u_int8_t *)sc->sc_cmdring.base) + idx); 1558 bcopy(in_extp, ext, sizeof(struct txp_ext_desc)); 1559 in_extp++; 1560 idx += sizeof(struct txp_cmd_desc); 1561 if (idx == sc->sc_cmdring.size) 1562 idx = 0; 1563 } 1564 1565 sc->sc_cmdring.lastwrite = idx; 1566 1567 WRITE_REG(sc, TXP_H2A_2, sc->sc_cmdring.lastwrite); 1568 bus_dmamap_sync(sc->sc_dmat, sc->sc_host_dma.dma_map, 0, 1569 sizeof(struct txp_hostvar), BUS_DMASYNC_PREREAD); 1570 1571 if (!wait) 1572 return (0); 1573 1574 for (i = 0; i < 10000; i++) { 1575 bus_dmamap_sync(sc->sc_dmat, sc->sc_host_dma.dma_map, 0, 1576 sizeof(struct txp_hostvar), BUS_DMASYNC_POSTREAD); 1577 idx = letoh32(hv->hv_resp_read_idx); 1578 if (idx != letoh32(hv->hv_resp_write_idx)) { 1579 *rspp = NULL; 1580 if (txp_response(sc, idx, id, seq, rspp)) 1581 return (-1); 1582 if (*rspp != NULL) 1583 break; 1584 } 1585 bus_dmamap_sync(sc->sc_dmat, sc->sc_host_dma.dma_map, 0, 1586 sizeof(struct txp_hostvar), BUS_DMASYNC_PREREAD); 1587 DELAY(50); 1588 } 1589 if (i == 1000 || (*rspp) == NULL) { 1590 printf("%s: 0x%x command failed\n", TXP_DEVNAME(sc), id); 1591 return (-1); 1592 } 1593 1594 return (0); 1595 } 1596 1597 int 1598 txp_response(struct txp_softc *sc, u_int32_t ridx, u_int16_t id, 1599 u_int16_t seq, struct txp_rsp_desc **rspp) 1600 { 1601 struct txp_hostvar *hv = sc->sc_hostvar; 1602 struct txp_rsp_desc *rsp; 1603 1604 while (ridx != letoh32(hv->hv_resp_write_idx)) { 1605 rsp = (struct txp_rsp_desc *)(((u_int8_t *)sc->sc_rspring.base) + ridx); 1606 1607 if (id == letoh16(rsp->rsp_id) && letoh16(rsp->rsp_seq) == seq) { 1608 *rspp = (struct txp_rsp_desc *)malloc( 1609 sizeof(struct txp_rsp_desc) * (rsp->rsp_numdesc + 1), 1610 M_DEVBUF, M_NOWAIT); 1611 if ((*rspp) == NULL) 1612 return (-1); 1613 txp_rsp_fixup(sc, rsp, *rspp); 1614 return (0); 1615 } 1616 1617 if (rsp->rsp_flags & RSP_FLAGS_ERROR) { 1618 printf("%s: response error: id 0x%x\n", 1619 TXP_DEVNAME(sc), letoh16(rsp->rsp_id)); 1620 txp_rsp_fixup(sc, rsp, NULL); 1621 ridx = letoh32(hv->hv_resp_read_idx); 1622 continue; 1623 } 1624 1625 switch (letoh16(rsp->rsp_id)) { 1626 case TXP_CMD_CYCLE_STATISTICS: 1627 case TXP_CMD_MEDIA_STATUS_READ: 1628 break; 1629 case TXP_CMD_HELLO_RESPONSE: 1630 printf("%s: hello\n", TXP_DEVNAME(sc)); 1631 break; 1632 default: 1633 printf("%s: unknown id(0x%x)\n", TXP_DEVNAME(sc), 1634 letoh16(rsp->rsp_id)); 1635 } 1636 1637 txp_rsp_fixup(sc, rsp, NULL); 1638 ridx = letoh32(hv->hv_resp_read_idx); 1639 hv->hv_resp_read_idx = letoh32(ridx); 1640 } 1641 1642 return (0); 1643 } 1644 1645 void 1646 txp_rsp_fixup(struct txp_softc *sc, struct txp_rsp_desc *rsp, 1647 struct txp_rsp_desc *dst) 1648 { 1649 struct txp_rsp_desc *src = rsp; 1650 struct txp_hostvar *hv = sc->sc_hostvar; 1651 u_int32_t i, ridx; 1652 1653 ridx = letoh32(hv->hv_resp_read_idx); 1654 1655 for (i = 0; i < rsp->rsp_numdesc + 1; i++) { 1656 if (dst != NULL) 1657 bcopy(src, dst++, sizeof(struct txp_rsp_desc)); 1658 ridx += sizeof(struct txp_rsp_desc); 1659 if (ridx == sc->sc_rspring.size) { 1660 src = sc->sc_rspring.base; 1661 ridx = 0; 1662 } else 1663 src++; 1664 sc->sc_rspring.lastwrite = ridx; 1665 hv->hv_resp_read_idx = htole32(ridx); 1666 } 1667 1668 hv->hv_resp_read_idx = htole32(ridx); 1669 } 1670 1671 int 1672 txp_cmd_desc_numfree(struct txp_softc *sc) 1673 { 1674 struct txp_hostvar *hv = sc->sc_hostvar; 1675 struct txp_boot_record *br = sc->sc_boot; 1676 u_int32_t widx, ridx, nfree; 1677 1678 widx = sc->sc_cmdring.lastwrite; 1679 ridx = letoh32(hv->hv_cmd_read_idx); 1680 1681 if (widx == ridx) { 1682 /* Ring is completely free */ 1683 nfree = letoh32(br->br_cmd_siz) - sizeof(struct txp_cmd_desc); 1684 } else { 1685 if (widx > ridx) 1686 nfree = letoh32(br->br_cmd_siz) - 1687 (widx - ridx + sizeof(struct txp_cmd_desc)); 1688 else 1689 nfree = ridx - widx - sizeof(struct txp_cmd_desc); 1690 } 1691 1692 return (nfree / sizeof(struct txp_cmd_desc)); 1693 } 1694 1695 void 1696 txp_stop(struct txp_softc *sc) 1697 { 1698 struct ifnet *ifp = &sc->sc_arpcom.ac_if; 1699 1700 timeout_del(&sc->sc_tick); 1701 1702 /* Mark the interface as down and cancel the watchdog timer. */ 1703 ifp->if_flags &= ~(IFF_RUNNING | IFF_OACTIVE); 1704 ifp->if_timer = 0; 1705 1706 txp_command(sc, TXP_CMD_TX_DISABLE, 0, 0, 0, NULL, NULL, NULL, 1); 1707 txp_command(sc, TXP_CMD_RX_DISABLE, 0, 0, 0, NULL, NULL, NULL, 1); 1708 } 1709 1710 void 1711 txp_watchdog(struct ifnet *ifp) 1712 { 1713 } 1714 1715 int 1716 txp_ifmedia_upd(struct ifnet *ifp) 1717 { 1718 struct txp_softc *sc = ifp->if_softc; 1719 struct ifmedia *ifm = &sc->sc_ifmedia; 1720 u_int16_t new_xcvr; 1721 1722 if (IFM_TYPE(ifm->ifm_media) != IFM_ETHER) 1723 return (EINVAL); 1724 1725 if (IFM_SUBTYPE(ifm->ifm_media) == IFM_10_T) { 1726 if ((ifm->ifm_media & IFM_GMASK) == IFM_FDX) 1727 new_xcvr = TXP_XCVR_10_FDX; 1728 else 1729 new_xcvr = TXP_XCVR_10_HDX; 1730 } else if (IFM_SUBTYPE(ifm->ifm_media) == IFM_100_TX) { 1731 if ((ifm->ifm_media & IFM_GMASK) == IFM_FDX) 1732 new_xcvr = TXP_XCVR_100_FDX; 1733 else 1734 new_xcvr = TXP_XCVR_100_HDX; 1735 } else if (IFM_SUBTYPE(ifm->ifm_media) == IFM_AUTO) { 1736 new_xcvr = TXP_XCVR_AUTO; 1737 } else 1738 return (EINVAL); 1739 1740 /* nothing to do */ 1741 if (sc->sc_xcvr == new_xcvr) 1742 return (0); 1743 1744 txp_command(sc, TXP_CMD_XCVR_SELECT, new_xcvr, 0, 0, 1745 NULL, NULL, NULL, 0); 1746 sc->sc_xcvr = new_xcvr; 1747 1748 return (0); 1749 } 1750 1751 void 1752 txp_ifmedia_sts(struct ifnet *ifp, struct ifmediareq *ifmr) 1753 { 1754 struct txp_softc *sc = ifp->if_softc; 1755 struct ifmedia *ifm = &sc->sc_ifmedia; 1756 u_int16_t bmsr, bmcr, anar, anlpar; 1757 1758 ifmr->ifm_status = IFM_AVALID; 1759 ifmr->ifm_active = IFM_ETHER; 1760 1761 if (txp_command(sc, TXP_CMD_PHY_MGMT_READ, 0, MII_BMSR, 0, 1762 &bmsr, NULL, NULL, 1)) 1763 goto bail; 1764 if (txp_command(sc, TXP_CMD_PHY_MGMT_READ, 0, MII_BMSR, 0, 1765 &bmsr, NULL, NULL, 1)) 1766 goto bail; 1767 1768 if (txp_command(sc, TXP_CMD_PHY_MGMT_READ, 0, MII_BMCR, 0, 1769 &bmcr, NULL, NULL, 1)) 1770 goto bail; 1771 1772 if (txp_command(sc, TXP_CMD_PHY_MGMT_READ, 0, MII_ANAR, 0, 1773 &anar, NULL, NULL, 1)) 1774 goto bail; 1775 1776 if (txp_command(sc, TXP_CMD_PHY_MGMT_READ, 0, MII_ANLPAR, 0, 1777 &anlpar, NULL, NULL, 1)) 1778 goto bail; 1779 1780 if (bmsr & BMSR_LINK) 1781 ifmr->ifm_status |= IFM_ACTIVE; 1782 1783 if (bmcr & BMCR_ISO) { 1784 ifmr->ifm_active |= IFM_NONE; 1785 ifmr->ifm_status = 0; 1786 return; 1787 } 1788 1789 if (bmcr & BMCR_LOOP) 1790 ifmr->ifm_active |= IFM_LOOP; 1791 1792 if (bmcr & BMCR_AUTOEN) { 1793 if ((bmsr & BMSR_ACOMP) == 0) { 1794 ifmr->ifm_active |= IFM_NONE; 1795 return; 1796 } 1797 1798 anlpar &= anar; 1799 if (anlpar & ANLPAR_TX_FD) 1800 ifmr->ifm_active |= IFM_100_TX|IFM_FDX; 1801 else if (anlpar & ANLPAR_T4) 1802 ifmr->ifm_active |= IFM_100_T4|IFM_HDX; 1803 else if (anlpar & ANLPAR_TX) 1804 ifmr->ifm_active |= IFM_100_TX|IFM_HDX; 1805 else if (anlpar & ANLPAR_10_FD) 1806 ifmr->ifm_active |= IFM_10_T|IFM_FDX; 1807 else if (anlpar & ANLPAR_10) 1808 ifmr->ifm_active |= IFM_10_T|IFM_HDX; 1809 else 1810 ifmr->ifm_active |= IFM_NONE; 1811 } else 1812 ifmr->ifm_active = ifm->ifm_cur->ifm_media; 1813 return; 1814 1815 bail: 1816 ifmr->ifm_active |= IFM_NONE; 1817 ifmr->ifm_status &= ~IFM_AVALID; 1818 } 1819 1820 void 1821 txp_show_descriptor(void *d) 1822 { 1823 struct txp_cmd_desc *cmd = d; 1824 struct txp_rsp_desc *rsp = d; 1825 struct txp_tx_desc *txd = d; 1826 struct txp_frag_desc *frgd = d; 1827 1828 switch (cmd->cmd_flags & CMD_FLAGS_TYPE_M) { 1829 case CMD_FLAGS_TYPE_CMD: 1830 /* command descriptor */ 1831 printf("[cmd flags 0x%x num %d id %d seq %d par1 0x%x par2 0x%x par3 0x%x]\n", 1832 cmd->cmd_flags, cmd->cmd_numdesc, letoh16(cmd->cmd_id), 1833 letoh16(cmd->cmd_seq), letoh16(cmd->cmd_par1), 1834 letoh32(cmd->cmd_par2), letoh32(cmd->cmd_par3)); 1835 break; 1836 case CMD_FLAGS_TYPE_RESP: 1837 /* response descriptor */ 1838 printf("[rsp flags 0x%x num %d id %d seq %d par1 0x%x par2 0x%x par3 0x%x]\n", 1839 rsp->rsp_flags, rsp->rsp_numdesc, letoh16(rsp->rsp_id), 1840 letoh16(rsp->rsp_seq), letoh16(rsp->rsp_par1), 1841 letoh32(rsp->rsp_par2), letoh32(rsp->rsp_par3)); 1842 break; 1843 case CMD_FLAGS_TYPE_DATA: 1844 /* data header (assuming tx for now) */ 1845 printf("[data flags 0x%x num %d totlen %d addr 0x%x/0x%x pflags 0x%x]", 1846 txd->tx_flags, txd->tx_numdesc, txd->tx_totlen, 1847 txd->tx_addrlo, txd->tx_addrhi, txd->tx_pflags); 1848 break; 1849 case CMD_FLAGS_TYPE_FRAG: 1850 /* fragment descriptor */ 1851 printf("[frag flags 0x%x rsvd1 0x%x len %d addr 0x%x/0x%x rsvd2 0x%x]", 1852 frgd->frag_flags, frgd->frag_rsvd1, frgd->frag_len, 1853 frgd->frag_addrlo, frgd->frag_addrhi, frgd->frag_rsvd2); 1854 break; 1855 default: 1856 printf("[unknown(%x) flags 0x%x num %d id %d seq %d par1 0x%x par2 0x%x par3 0x%x]\n", 1857 cmd->cmd_flags & CMD_FLAGS_TYPE_M, 1858 cmd->cmd_flags, cmd->cmd_numdesc, letoh16(cmd->cmd_id), 1859 letoh16(cmd->cmd_seq), letoh16(cmd->cmd_par1), 1860 letoh32(cmd->cmd_par2), letoh32(cmd->cmd_par3)); 1861 break; 1862 } 1863 } 1864 1865 void 1866 txp_set_filter(struct txp_softc *sc) 1867 { 1868 struct arpcom *ac = &sc->sc_arpcom; 1869 struct ifnet *ifp = &sc->sc_arpcom.ac_if; 1870 u_int32_t hashbit, hash[2]; 1871 u_int16_t filter; 1872 int mcnt = 0; 1873 struct ether_multi *enm; 1874 struct ether_multistep step; 1875 1876 if (ifp->if_flags & IFF_PROMISC) { 1877 filter = TXP_RXFILT_PROMISC; 1878 goto setit; 1879 } 1880 1881 again: 1882 filter = TXP_RXFILT_DIRECT; 1883 1884 if (ifp->if_flags & IFF_BROADCAST) 1885 filter |= TXP_RXFILT_BROADCAST; 1886 1887 if (ifp->if_flags & IFF_ALLMULTI) 1888 filter |= TXP_RXFILT_ALLMULTI; 1889 else { 1890 hash[0] = hash[1] = 0; 1891 1892 ETHER_FIRST_MULTI(step, ac, enm); 1893 while (enm != NULL) { 1894 if (bcmp(enm->enm_addrlo, enm->enm_addrhi, ETHER_ADDR_LEN)) { 1895 /* 1896 * We must listen to a range of multicast 1897 * addresses. For now, just accept all 1898 * multicasts, rather than trying to set only 1899 * those filter bits needed to match the range. 1900 * (At this time, the only use of address 1901 * ranges is for IP multicast routing, for 1902 * which the range is big enough to require 1903 * all bits set.) 1904 */ 1905 ifp->if_flags |= IFF_ALLMULTI; 1906 goto again; 1907 } 1908 1909 mcnt++; 1910 hashbit = (u_int16_t)(ether_crc32_be(enm->enm_addrlo, 1911 ETHER_ADDR_LEN) & (64 - 1)); 1912 hash[hashbit / 32] |= (1 << hashbit % 32); 1913 ETHER_NEXT_MULTI(step, enm); 1914 } 1915 1916 if (mcnt > 0) { 1917 filter |= TXP_RXFILT_HASHMULTI; 1918 txp_command(sc, TXP_CMD_MCAST_HASH_MASK_WRITE, 1919 2, hash[0], hash[1], NULL, NULL, NULL, 0); 1920 } 1921 } 1922 1923 setit: 1924 txp_command(sc, TXP_CMD_RX_FILTER_WRITE, filter, 0, 0, 1925 NULL, NULL, NULL, 1); 1926 } 1927 1928 void 1929 txp_capabilities(struct txp_softc *sc) 1930 { 1931 struct ifnet *ifp = &sc->sc_arpcom.ac_if; 1932 struct txp_rsp_desc *rsp = NULL; 1933 struct txp_ext_desc *ext; 1934 1935 if (txp_command2(sc, TXP_CMD_OFFLOAD_READ, 0, 0, 0, NULL, 0, &rsp, 1)) 1936 goto out; 1937 1938 if (rsp->rsp_numdesc != 1) 1939 goto out; 1940 ext = (struct txp_ext_desc *)(rsp + 1); 1941 1942 sc->sc_tx_capability = ext->ext_1 & OFFLOAD_MASK; 1943 sc->sc_rx_capability = ext->ext_2 & OFFLOAD_MASK; 1944 1945 ifp->if_capabilities |= IFCAP_VLAN_MTU; 1946 1947 #if NVLAN > 0 1948 if (rsp->rsp_par2 & rsp->rsp_par3 & OFFLOAD_VLAN) { 1949 sc->sc_tx_capability |= OFFLOAD_VLAN; 1950 sc->sc_rx_capability |= OFFLOAD_VLAN; 1951 ifp->if_capabilities |= IFCAP_VLAN_HWTAGGING; 1952 } 1953 #endif 1954 1955 #if 0 1956 /* not ready yet */ 1957 if (rsp->rsp_par2 & rsp->rsp_par3 & OFFLOAD_IPSEC) { 1958 sc->sc_tx_capability |= OFFLOAD_IPSEC; 1959 sc->sc_rx_capability |= OFFLOAD_IPSEC; 1960 ifp->if_capabilities |= IFCAP_IPSEC; 1961 } 1962 #endif 1963 1964 if (rsp->rsp_par2 & rsp->rsp_par3 & OFFLOAD_IPCKSUM) { 1965 sc->sc_tx_capability |= OFFLOAD_IPCKSUM; 1966 sc->sc_rx_capability |= OFFLOAD_IPCKSUM; 1967 ifp->if_capabilities |= IFCAP_CSUM_IPv4; 1968 } 1969 1970 if (rsp->rsp_par2 & rsp->rsp_par3 & OFFLOAD_TCPCKSUM) { 1971 sc->sc_rx_capability |= OFFLOAD_TCPCKSUM; 1972 #ifdef TRY_TX_TCP_CSUM 1973 sc->sc_tx_capability |= OFFLOAD_TCPCKSUM; 1974 ifp->if_capabilities |= IFCAP_CSUM_TCPv4; 1975 #endif 1976 } 1977 1978 if (rsp->rsp_par2 & rsp->rsp_par3 & OFFLOAD_UDPCKSUM) { 1979 sc->sc_rx_capability |= OFFLOAD_UDPCKSUM; 1980 #ifdef TRY_TX_UDP_CSUM 1981 sc->sc_tx_capability |= OFFLOAD_UDPCKSUM; 1982 ifp->if_capabilities |= IFCAP_CSUM_UDPv4; 1983 #endif 1984 } 1985 1986 if (txp_command(sc, TXP_CMD_OFFLOAD_WRITE, 0, 1987 sc->sc_tx_capability, sc->sc_rx_capability, NULL, NULL, NULL, 1)) 1988 goto out; 1989 1990 out: 1991 if (rsp != NULL) 1992 free(rsp, M_DEVBUF); 1993 } 1994