1 /* $OpenBSD: if_txp.c,v 1.94 2008/09/18 15:16:30 naddy Exp $ */ 2 3 /* 4 * Copyright (c) 2001 5 * Jason L. Wright <jason@thought.net>, Theo de Raadt, and 6 * Aaron Campbell <aaron@monkey.org>. All rights reserved. 7 * 8 * Redistribution and use in source and binary forms, with or without 9 * modification, are permitted provided that the following conditions 10 * are met: 11 * 1. Redistributions of source code must retain the above copyright 12 * notice, this list of conditions and the following disclaimer. 13 * 2. Redistributions in binary form must reproduce the above copyright 14 * notice, this list of conditions and the following disclaimer in the 15 * documentation and/or other materials provided with the distribution. 16 * 17 * THIS SOFTWARE IS PROVIDED BY THE AUTHORS ``AS IS'' AND ANY EXPRESS OR 18 * IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED 19 * WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE 20 * ARE DISCLAIMED. IN NO EVENT SHALL THE AUTHORS OR THE VOICES IN THEIR HEADS 21 * BE LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR 22 * CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF 23 * SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS 24 * INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN 25 * CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) 26 * ARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF 27 * THE POSSIBILITY OF SUCH DAMAGE. 28 */ 29 30 /* 31 * Driver for 3c990 (Typhoon) Ethernet ASIC 32 */ 33 34 #include "bpfilter.h" 35 #include "vlan.h" 36 37 #include <sys/param.h> 38 #include <sys/systm.h> 39 #include <sys/sockio.h> 40 #include <sys/mbuf.h> 41 #include <sys/malloc.h> 42 #include <sys/kernel.h> 43 #include <sys/socket.h> 44 #include <sys/device.h> 45 #include <sys/timeout.h> 46 47 #include <net/if.h> 48 #include <net/if_dl.h> 49 #include <net/if_types.h> 50 51 #ifdef INET 52 #include <netinet/in.h> 53 #include <netinet/in_systm.h> 54 #include <netinet/in_var.h> 55 #include <netinet/ip.h> 56 #include <netinet/if_ether.h> 57 #endif 58 59 #include <net/if_media.h> 60 61 #if NBPFILTER > 0 62 #include <net/bpf.h> 63 #endif 64 65 #if NVLAN > 0 66 #include <net/if_types.h> 67 #include <net/if_vlan_var.h> 68 #endif 69 70 #include <machine/bus.h> 71 72 #include <dev/mii/mii.h> 73 #include <dev/mii/miivar.h> 74 #include <dev/pci/pcireg.h> 75 #include <dev/pci/pcivar.h> 76 #include <dev/pci/pcidevs.h> 77 78 #include <dev/pci/if_txpreg.h> 79 80 /* 81 * These currently break the 3c990 firmware, hopefully will be resolved 82 * at some point. 83 */ 84 #undef TRY_TX_UDP_CSUM 85 #undef TRY_TX_TCP_CSUM 86 87 int txp_probe(struct device *, void *, void *); 88 void txp_attach(struct device *, struct device *, void *); 89 void txp_attachhook(void *vsc); 90 int txp_intr(void *); 91 void txp_tick(void *); 92 void txp_shutdown(void *); 93 int txp_ioctl(struct ifnet *, u_long, caddr_t); 94 void txp_start(struct ifnet *); 95 void txp_stop(struct txp_softc *); 96 void txp_init(struct txp_softc *); 97 void txp_watchdog(struct ifnet *); 98 99 int txp_chip_init(struct txp_softc *); 100 int txp_reset_adapter(struct txp_softc *); 101 int txp_download_fw(struct txp_softc *); 102 int txp_download_fw_wait(struct txp_softc *); 103 int txp_download_fw_section(struct txp_softc *, 104 struct txp_fw_section_header *, int, u_char *, size_t); 105 int txp_alloc_rings(struct txp_softc *); 106 void txp_dma_free(struct txp_softc *, struct txp_dma_alloc *); 107 int txp_dma_malloc(struct txp_softc *, bus_size_t, struct txp_dma_alloc *, int); 108 void txp_set_filter(struct txp_softc *); 109 110 int txp_cmd_desc_numfree(struct txp_softc *); 111 int txp_command(struct txp_softc *, u_int16_t, u_int16_t, u_int32_t, 112 u_int32_t, u_int16_t *, u_int32_t *, u_int32_t *, int); 113 int txp_command2(struct txp_softc *, u_int16_t, u_int16_t, 114 u_int32_t, u_int32_t, struct txp_ext_desc *, u_int8_t, 115 struct txp_rsp_desc **, int); 116 int txp_response(struct txp_softc *, u_int32_t, u_int16_t, u_int16_t, 117 struct txp_rsp_desc **); 118 void txp_rsp_fixup(struct txp_softc *, struct txp_rsp_desc *, 119 struct txp_rsp_desc *); 120 void txp_capabilities(struct txp_softc *); 121 122 void txp_ifmedia_sts(struct ifnet *, struct ifmediareq *); 123 int txp_ifmedia_upd(struct ifnet *); 124 void txp_show_descriptor(void *); 125 void txp_tx_reclaim(struct txp_softc *, struct txp_tx_ring *, 126 struct txp_dma_alloc *); 127 void txp_rxbuf_reclaim(struct txp_softc *); 128 void txp_rx_reclaim(struct txp_softc *, struct txp_rx_ring *, 129 struct txp_dma_alloc *); 130 131 struct cfattach txp_ca = { 132 sizeof(struct txp_softc), txp_probe, txp_attach, 133 }; 134 135 struct cfdriver txp_cd = { 136 0, "txp", DV_IFNET 137 }; 138 139 const struct pci_matchid txp_devices[] = { 140 { PCI_VENDOR_3COM, PCI_PRODUCT_3COM_3CR990 }, 141 { PCI_VENDOR_3COM, PCI_PRODUCT_3COM_3CR990TX }, 142 { PCI_VENDOR_3COM, PCI_PRODUCT_3COM_3CR990TX95 }, 143 { PCI_VENDOR_3COM, PCI_PRODUCT_3COM_3CR990TX97 }, 144 { PCI_VENDOR_3COM, PCI_PRODUCT_3COM_3CR990SVR95 }, 145 { PCI_VENDOR_3COM, PCI_PRODUCT_3COM_3CR990SVR97 }, 146 { PCI_VENDOR_3COM, PCI_PRODUCT_3COM_3C990BTXM }, 147 { PCI_VENDOR_3COM, PCI_PRODUCT_3COM_3C990BSVR }, 148 { PCI_VENDOR_3COM, PCI_PRODUCT_3COM_3CR990FX }, 149 }; 150 151 int 152 txp_probe(struct device *parent, void *match, void *aux) 153 { 154 return (pci_matchbyid((struct pci_attach_args *)aux, txp_devices, 155 sizeof(txp_devices)/sizeof(txp_devices[0]))); 156 } 157 158 void 159 txp_attachhook(void *vsc) 160 { 161 struct txp_softc *sc = vsc; 162 struct ifnet *ifp = &sc->sc_arpcom.ac_if; 163 u_int16_t p1; 164 u_int32_t p2; 165 int s; 166 167 s = splnet(); 168 printf("%s: ", sc->sc_dev.dv_xname); 169 170 if (txp_chip_init(sc)) { 171 printf("failed chip init\n"); 172 splx(s); 173 return; 174 } 175 176 if (txp_download_fw(sc)) { 177 splx(s); 178 return; 179 } 180 181 if (txp_alloc_rings(sc)) { 182 splx(s); 183 return; 184 } 185 186 if (txp_command(sc, TXP_CMD_MAX_PKT_SIZE_WRITE, TXP_MAX_PKTLEN, 0, 0, 187 NULL, NULL, NULL, 1)) { 188 splx(s); 189 return; 190 } 191 192 if (txp_command(sc, TXP_CMD_STATION_ADDRESS_READ, 0, 0, 0, 193 &p1, &p2, NULL, 1)) { 194 splx(s); 195 return; 196 } 197 198 p1 = htole16(p1); 199 sc->sc_arpcom.ac_enaddr[0] = ((u_int8_t *)&p1)[1]; 200 sc->sc_arpcom.ac_enaddr[1] = ((u_int8_t *)&p1)[0]; 201 p2 = htole32(p2); 202 sc->sc_arpcom.ac_enaddr[2] = ((u_int8_t *)&p2)[3]; 203 sc->sc_arpcom.ac_enaddr[3] = ((u_int8_t *)&p2)[2]; 204 sc->sc_arpcom.ac_enaddr[4] = ((u_int8_t *)&p2)[1]; 205 sc->sc_arpcom.ac_enaddr[5] = ((u_int8_t *)&p2)[0]; 206 207 printf("address %s\n", ether_sprintf(sc->sc_arpcom.ac_enaddr)); 208 sc->sc_cold = 0; 209 210 ifmedia_init(&sc->sc_ifmedia, 0, txp_ifmedia_upd, txp_ifmedia_sts); 211 ifmedia_add(&sc->sc_ifmedia, IFM_ETHER|IFM_10_T, 0, NULL); 212 ifmedia_add(&sc->sc_ifmedia, IFM_ETHER|IFM_10_T|IFM_HDX, 0, NULL); 213 ifmedia_add(&sc->sc_ifmedia, IFM_ETHER|IFM_10_T|IFM_FDX, 0, NULL); 214 ifmedia_add(&sc->sc_ifmedia, IFM_ETHER|IFM_100_TX, 0, NULL); 215 ifmedia_add(&sc->sc_ifmedia, IFM_ETHER|IFM_100_TX|IFM_HDX, 0, NULL); 216 ifmedia_add(&sc->sc_ifmedia, IFM_ETHER|IFM_100_TX|IFM_FDX, 0, NULL); 217 ifmedia_add(&sc->sc_ifmedia, IFM_ETHER|IFM_AUTO, 0, NULL); 218 219 sc->sc_xcvr = TXP_XCVR_AUTO; 220 txp_command(sc, TXP_CMD_XCVR_SELECT, TXP_XCVR_AUTO, 0, 0, 221 NULL, NULL, NULL, 0); 222 ifmedia_set(&sc->sc_ifmedia, IFM_ETHER|IFM_AUTO); 223 224 ifp->if_softc = sc; 225 ifp->if_flags = IFF_BROADCAST | IFF_SIMPLEX | IFF_MULTICAST; 226 ifp->if_ioctl = txp_ioctl; 227 ifp->if_start = txp_start; 228 ifp->if_watchdog = txp_watchdog; 229 ifp->if_baudrate = 10000000; 230 IFQ_SET_MAXLEN(&ifp->if_snd, TX_ENTRIES); 231 IFQ_SET_READY(&ifp->if_snd); 232 ifp->if_capabilities = 0; 233 bcopy(sc->sc_dev.dv_xname, ifp->if_xname, IFNAMSIZ); 234 235 txp_capabilities(sc); 236 237 timeout_set(&sc->sc_tick, txp_tick, sc); 238 239 /* 240 * Attach us everywhere 241 */ 242 if_attach(ifp); 243 ether_ifattach(ifp); 244 245 shutdownhook_establish(txp_shutdown, sc); 246 splx(s); 247 } 248 249 void 250 txp_attach(struct device *parent, struct device *self, void *aux) 251 { 252 struct txp_softc *sc = (struct txp_softc *)self; 253 struct pci_attach_args *pa = aux; 254 pci_chipset_tag_t pc = pa->pa_pc; 255 pci_intr_handle_t ih; 256 const char *intrstr = NULL; 257 bus_size_t iosize; 258 259 sc->sc_cold = 1; 260 261 if (pci_mapreg_map(pa, TXP_PCI_LOMEM, PCI_MAPREG_TYPE_MEM, 0, 262 &sc->sc_bt, &sc->sc_bh, NULL, &iosize, 0)) { 263 printf(": can't map mem space %d\n", 0); 264 return; 265 } 266 267 sc->sc_dmat = pa->pa_dmat; 268 269 /* 270 * Allocate our interrupt. 271 */ 272 if (pci_intr_map(pa, &ih)) { 273 printf(": couldn't map interrupt\n"); 274 return; 275 } 276 277 intrstr = pci_intr_string(pc, ih); 278 sc->sc_ih = pci_intr_establish(pc, ih, IPL_NET, txp_intr, sc, 279 self->dv_xname); 280 if (sc->sc_ih == NULL) { 281 printf(": couldn't establish interrupt"); 282 if (intrstr != NULL) 283 printf(" at %s", intrstr); 284 printf("\n"); 285 return; 286 } 287 printf(": %s\n", intrstr); 288 289 if (rootvp == NULL) 290 mountroothook_establish(txp_attachhook, sc); 291 else 292 txp_attachhook(sc); 293 294 } 295 296 int 297 txp_chip_init(struct txp_softc *sc) 298 { 299 /* disable interrupts */ 300 WRITE_REG(sc, TXP_IER, 0); 301 WRITE_REG(sc, TXP_IMR, 302 TXP_INT_SELF | TXP_INT_PCI_TABORT | TXP_INT_PCI_MABORT | 303 TXP_INT_DMA3 | TXP_INT_DMA2 | TXP_INT_DMA1 | TXP_INT_DMA0 | 304 TXP_INT_LATCH); 305 306 /* ack all interrupts */ 307 WRITE_REG(sc, TXP_ISR, TXP_INT_RESERVED | TXP_INT_LATCH | 308 TXP_INT_A2H_7 | TXP_INT_A2H_6 | TXP_INT_A2H_5 | TXP_INT_A2H_4 | 309 TXP_INT_SELF | TXP_INT_PCI_TABORT | TXP_INT_PCI_MABORT | 310 TXP_INT_DMA3 | TXP_INT_DMA2 | TXP_INT_DMA1 | TXP_INT_DMA0 | 311 TXP_INT_A2H_3 | TXP_INT_A2H_2 | TXP_INT_A2H_1 | TXP_INT_A2H_0); 312 313 if (txp_reset_adapter(sc)) 314 return (-1); 315 316 /* disable interrupts */ 317 WRITE_REG(sc, TXP_IER, 0); 318 WRITE_REG(sc, TXP_IMR, 319 TXP_INT_SELF | TXP_INT_PCI_TABORT | TXP_INT_PCI_MABORT | 320 TXP_INT_DMA3 | TXP_INT_DMA2 | TXP_INT_DMA1 | TXP_INT_DMA0 | 321 TXP_INT_LATCH); 322 323 /* ack all interrupts */ 324 WRITE_REG(sc, TXP_ISR, TXP_INT_RESERVED | TXP_INT_LATCH | 325 TXP_INT_A2H_7 | TXP_INT_A2H_6 | TXP_INT_A2H_5 | TXP_INT_A2H_4 | 326 TXP_INT_SELF | TXP_INT_PCI_TABORT | TXP_INT_PCI_MABORT | 327 TXP_INT_DMA3 | TXP_INT_DMA2 | TXP_INT_DMA1 | TXP_INT_DMA0 | 328 TXP_INT_A2H_3 | TXP_INT_A2H_2 | TXP_INT_A2H_1 | TXP_INT_A2H_0); 329 330 return (0); 331 } 332 333 int 334 txp_reset_adapter(struct txp_softc *sc) 335 { 336 u_int32_t r; 337 int i; 338 339 WRITE_REG(sc, TXP_SRR, TXP_SRR_ALL); 340 DELAY(1000); 341 WRITE_REG(sc, TXP_SRR, 0); 342 343 /* Should wait max 6 seconds */ 344 for (i = 0; i < 6000; i++) { 345 r = READ_REG(sc, TXP_A2H_0); 346 if (r == STAT_WAITING_FOR_HOST_REQUEST) 347 break; 348 DELAY(1000); 349 } 350 351 if (r != STAT_WAITING_FOR_HOST_REQUEST) { 352 printf("%s: reset hung\n", TXP_DEVNAME(sc)); 353 return (-1); 354 } 355 356 return (0); 357 } 358 359 int 360 txp_download_fw(struct txp_softc *sc) 361 { 362 struct txp_fw_file_header *fileheader; 363 struct txp_fw_section_header *secthead; 364 u_int32_t r, i, ier, imr; 365 size_t buflen; 366 int sect, err; 367 u_char *buf; 368 369 ier = READ_REG(sc, TXP_IER); 370 WRITE_REG(sc, TXP_IER, ier | TXP_INT_A2H_0); 371 372 imr = READ_REG(sc, TXP_IMR); 373 WRITE_REG(sc, TXP_IMR, imr | TXP_INT_A2H_0); 374 375 for (i = 0; i < 10000; i++) { 376 r = READ_REG(sc, TXP_A2H_0); 377 if (r == STAT_WAITING_FOR_HOST_REQUEST) 378 break; 379 DELAY(50); 380 } 381 if (r != STAT_WAITING_FOR_HOST_REQUEST) { 382 printf("not waiting for host request\n"); 383 return (-1); 384 } 385 386 /* Ack the status */ 387 WRITE_REG(sc, TXP_ISR, TXP_INT_A2H_0); 388 389 err = loadfirmware("3c990", &buf, &buflen); 390 if (err) { 391 printf("failed loadfirmware of file 3c990: errno %d\n", 392 err); 393 return (err); 394 } 395 396 fileheader = (struct txp_fw_file_header *)buf; 397 if (bcmp("TYPHOON", fileheader->magicid, sizeof(fileheader->magicid))) { 398 printf("firmware invalid magic\n"); 399 goto fail; 400 } 401 402 /* Tell boot firmware to get ready for image */ 403 WRITE_REG(sc, TXP_H2A_1, letoh32(fileheader->addr)); 404 WRITE_REG(sc, TXP_H2A_0, TXP_BOOTCMD_RUNTIME_IMAGE); 405 406 if (txp_download_fw_wait(sc)) { 407 printf("fw wait failed, initial\n"); 408 goto fail; 409 } 410 411 secthead = (struct txp_fw_section_header *)(buf + 412 sizeof(struct txp_fw_file_header)); 413 414 for (sect = 0; sect < letoh32(fileheader->nsections); sect++) { 415 if (txp_download_fw_section(sc, secthead, sect, buf, buflen)) 416 goto fail; 417 secthead = (struct txp_fw_section_header *) 418 (((u_int8_t *)secthead) + letoh32(secthead->nbytes) + 419 sizeof(*secthead)); 420 } 421 422 WRITE_REG(sc, TXP_H2A_0, TXP_BOOTCMD_DOWNLOAD_COMPLETE); 423 424 for (i = 0; i < 10000; i++) { 425 r = READ_REG(sc, TXP_A2H_0); 426 if (r == STAT_WAITING_FOR_BOOT) 427 break; 428 DELAY(50); 429 } 430 if (r != STAT_WAITING_FOR_BOOT) { 431 printf("not waiting for boot\n"); 432 goto fail; 433 } 434 435 WRITE_REG(sc, TXP_IER, ier); 436 WRITE_REG(sc, TXP_IMR, imr); 437 438 free(buf, M_DEVBUF); 439 return (0); 440 fail: 441 free(buf, M_DEVBUF); 442 return (-1); 443 } 444 445 int 446 txp_download_fw_wait(struct txp_softc *sc) 447 { 448 u_int32_t i, r; 449 450 for (i = 0; i < 10000; i++) { 451 r = READ_REG(sc, TXP_ISR); 452 if (r & TXP_INT_A2H_0) 453 break; 454 DELAY(50); 455 } 456 457 if (!(r & TXP_INT_A2H_0)) { 458 printf("fw wait failed comm0\n"); 459 return (-1); 460 } 461 462 WRITE_REG(sc, TXP_ISR, TXP_INT_A2H_0); 463 464 r = READ_REG(sc, TXP_A2H_0); 465 if (r != STAT_WAITING_FOR_SEGMENT) { 466 printf("fw not waiting for segment\n"); 467 return (-1); 468 } 469 return (0); 470 } 471 472 int 473 txp_download_fw_section(struct txp_softc *sc, 474 struct txp_fw_section_header *sect, int sectnum, u_char *buf, 475 size_t buflen) 476 { 477 struct txp_dma_alloc dma; 478 int rseg, err = 0; 479 struct mbuf m; 480 u_int16_t csum; 481 482 /* Skip zero length sections */ 483 if (sect->nbytes == 0) 484 return (0); 485 486 /* Make sure we aren't past the end of the image */ 487 rseg = ((u_int8_t *)sect) - ((u_int8_t *)buf); 488 if (rseg >= buflen) { 489 printf("fw invalid section address, section %d\n", sectnum); 490 return (-1); 491 } 492 493 /* Make sure this section doesn't go past the end */ 494 rseg += letoh32(sect->nbytes); 495 if (rseg >= buflen) { 496 printf("fw truncated section %d\n", sectnum); 497 return (-1); 498 } 499 500 /* map a buffer, copy segment to it, get physaddr */ 501 if (txp_dma_malloc(sc, letoh32(sect->nbytes), &dma, 0)) { 502 printf("fw dma malloc failed, section %d\n", sectnum); 503 return (-1); 504 } 505 506 bcopy(((u_int8_t *)sect) + sizeof(*sect), dma.dma_vaddr, 507 letoh32(sect->nbytes)); 508 509 /* 510 * dummy up mbuf and verify section checksum 511 */ 512 m.m_type = MT_DATA; 513 m.m_next = m.m_nextpkt = NULL; 514 m.m_len = letoh32(sect->nbytes); 515 m.m_data = dma.dma_vaddr; 516 m.m_flags = 0; 517 csum = in_cksum(&m, letoh32(sect->nbytes)); 518 if (csum != sect->cksum) { 519 printf("fw section %d, bad cksum (expected 0x%x got 0x%x)\n", 520 sectnum, sect->cksum, csum); 521 err = -1; 522 goto bail; 523 } 524 525 bus_dmamap_sync(sc->sc_dmat, dma.dma_map, 0, 526 dma.dma_map->dm_mapsize, BUS_DMASYNC_PREWRITE); 527 528 WRITE_REG(sc, TXP_H2A_1, letoh32(sect->nbytes)); 529 WRITE_REG(sc, TXP_H2A_2, letoh16(sect->cksum)); 530 WRITE_REG(sc, TXP_H2A_3, letoh32(sect->addr)); 531 WRITE_REG(sc, TXP_H2A_4, dma.dma_paddr >> 32); 532 WRITE_REG(sc, TXP_H2A_5, dma.dma_paddr & 0xffffffff); 533 WRITE_REG(sc, TXP_H2A_0, TXP_BOOTCMD_SEGMENT_AVAILABLE); 534 535 if (txp_download_fw_wait(sc)) { 536 printf("%s: fw wait failed, section %d\n", 537 sc->sc_dev.dv_xname, sectnum); 538 err = -1; 539 } 540 541 bus_dmamap_sync(sc->sc_dmat, dma.dma_map, 0, 542 dma.dma_map->dm_mapsize, BUS_DMASYNC_POSTWRITE); 543 544 bail: 545 txp_dma_free(sc, &dma); 546 547 return (err); 548 } 549 550 int 551 txp_intr(void *vsc) 552 { 553 struct txp_softc *sc = vsc; 554 struct txp_hostvar *hv = sc->sc_hostvar; 555 u_int32_t isr; 556 int claimed = 0; 557 558 /* mask all interrupts */ 559 WRITE_REG(sc, TXP_IMR, TXP_INT_RESERVED | TXP_INT_SELF | 560 TXP_INT_A2H_7 | TXP_INT_A2H_6 | TXP_INT_A2H_5 | TXP_INT_A2H_4 | 561 TXP_INT_A2H_2 | TXP_INT_A2H_1 | TXP_INT_A2H_0 | 562 TXP_INT_DMA3 | TXP_INT_DMA2 | TXP_INT_DMA1 | TXP_INT_DMA0 | 563 TXP_INT_PCI_TABORT | TXP_INT_PCI_MABORT | TXP_INT_LATCH); 564 565 bus_dmamap_sync(sc->sc_dmat, sc->sc_host_dma.dma_map, 0, 566 sizeof(struct txp_hostvar), BUS_DMASYNC_POSTWRITE|BUS_DMASYNC_POSTREAD); 567 568 isr = READ_REG(sc, TXP_ISR); 569 while (isr) { 570 claimed = 1; 571 WRITE_REG(sc, TXP_ISR, isr); 572 573 if ((*sc->sc_rxhir.r_roff) != (*sc->sc_rxhir.r_woff)) 574 txp_rx_reclaim(sc, &sc->sc_rxhir, &sc->sc_rxhiring_dma); 575 if ((*sc->sc_rxlor.r_roff) != (*sc->sc_rxlor.r_woff)) 576 txp_rx_reclaim(sc, &sc->sc_rxlor, &sc->sc_rxloring_dma); 577 578 if (hv->hv_rx_buf_write_idx == hv->hv_rx_buf_read_idx) 579 txp_rxbuf_reclaim(sc); 580 581 if (sc->sc_txhir.r_cnt && (sc->sc_txhir.r_cons != 582 TXP_OFFSET2IDX(letoh32(*(sc->sc_txhir.r_off))))) 583 txp_tx_reclaim(sc, &sc->sc_txhir, &sc->sc_txhiring_dma); 584 585 if (sc->sc_txlor.r_cnt && (sc->sc_txlor.r_cons != 586 TXP_OFFSET2IDX(letoh32(*(sc->sc_txlor.r_off))))) 587 txp_tx_reclaim(sc, &sc->sc_txlor, &sc->sc_txloring_dma); 588 589 isr = READ_REG(sc, TXP_ISR); 590 } 591 592 bus_dmamap_sync(sc->sc_dmat, sc->sc_host_dma.dma_map, 0, 593 sizeof(struct txp_hostvar), BUS_DMASYNC_POSTWRITE|BUS_DMASYNC_POSTREAD); 594 595 /* unmask all interrupts */ 596 WRITE_REG(sc, TXP_IMR, TXP_INT_A2H_3); 597 598 txp_start(&sc->sc_arpcom.ac_if); 599 600 return (claimed); 601 } 602 603 void 604 txp_rx_reclaim(struct txp_softc *sc, struct txp_rx_ring *r, 605 struct txp_dma_alloc *dma) 606 { 607 struct ifnet *ifp = &sc->sc_arpcom.ac_if; 608 struct txp_rx_desc *rxd; 609 struct mbuf *m; 610 struct txp_swdesc *sd; 611 u_int32_t roff, woff; 612 int idx; 613 u_int16_t sumflags = 0; 614 615 roff = letoh32(*r->r_roff); 616 woff = letoh32(*r->r_woff); 617 idx = roff / sizeof(struct txp_rx_desc); 618 rxd = r->r_desc + idx; 619 620 while (roff != woff) { 621 622 bus_dmamap_sync(sc->sc_dmat, dma->dma_map, 623 idx * sizeof(struct txp_rx_desc), sizeof(struct txp_rx_desc), 624 BUS_DMASYNC_POSTREAD); 625 626 if (rxd->rx_flags & RX_FLAGS_ERROR) { 627 printf("%s: error 0x%x\n", sc->sc_dev.dv_xname, 628 letoh32(rxd->rx_stat)); 629 ifp->if_ierrors++; 630 goto next; 631 } 632 633 /* retrieve stashed pointer */ 634 bcopy((u_long *)&rxd->rx_vaddrlo, &sd, sizeof(sd)); 635 636 bus_dmamap_sync(sc->sc_dmat, sd->sd_map, 0, 637 sd->sd_map->dm_mapsize, BUS_DMASYNC_POSTREAD); 638 bus_dmamap_unload(sc->sc_dmat, sd->sd_map); 639 bus_dmamap_destroy(sc->sc_dmat, sd->sd_map); 640 m = sd->sd_mbuf; 641 free(sd, M_DEVBUF); 642 m->m_pkthdr.len = m->m_len = letoh16(rxd->rx_len); 643 644 #if NVLAN > 0 645 /* 646 * XXX Another firmware bug: the vlan encapsulation 647 * is always removed, even when we tell the card not 648 * to do that. Restore the vlan encapsulation below. 649 */ 650 if (rxd->rx_stat & htole32(RX_STAT_VLAN)) { 651 struct ether_vlan_header vh; 652 653 if (m->m_pkthdr.len < ETHER_HDR_LEN) { 654 m_freem(m); 655 goto next; 656 } 657 m_copydata(m, 0, ETHER_HDR_LEN, (caddr_t)&vh); 658 vh.evl_proto = vh.evl_encap_proto; 659 vh.evl_tag = rxd->rx_vlan >> 16; 660 vh.evl_encap_proto = htons(ETHERTYPE_VLAN); 661 m_adj(m, ETHER_HDR_LEN); 662 M_PREPEND(m, sizeof(vh), M_DONTWAIT); 663 if (m == NULL) 664 goto next; 665 m_copyback(m, 0, sizeof(vh), &vh); 666 } 667 #endif 668 669 #ifdef __STRICT_ALIGNMENT 670 { 671 /* 672 * XXX Nice chip, except it won't accept "off by 2" 673 * buffers, so we're force to copy. Supposedly 674 * this will be fixed in a newer firmware rev 675 * and this will be temporary. 676 */ 677 struct mbuf *mnew; 678 679 MGETHDR(mnew, M_DONTWAIT, MT_DATA); 680 if (mnew == NULL) { 681 m_freem(m); 682 goto next; 683 } 684 if (m->m_len > (MHLEN - 2)) { 685 MCLGET(mnew, M_DONTWAIT); 686 if (!(mnew->m_flags & M_EXT)) { 687 m_freem(mnew); 688 m_freem(m); 689 goto next; 690 } 691 } 692 mnew->m_pkthdr.rcvif = ifp; 693 mnew->m_pkthdr.len = mnew->m_len = m->m_len; 694 mnew->m_data += 2; 695 bcopy(m->m_data, mnew->m_data, m->m_len); 696 m_freem(m); 697 m = mnew; 698 } 699 #endif 700 701 #if NBPFILTER > 0 702 /* 703 * Handle BPF listeners. Let the BPF user see the packet. 704 */ 705 if (ifp->if_bpf) 706 bpf_mtap(ifp->if_bpf, m, BPF_DIRECTION_IN); 707 #endif 708 709 if (rxd->rx_stat & htole32(RX_STAT_IPCKSUMBAD)) 710 sumflags |= M_IPV4_CSUM_IN_BAD; 711 else if (rxd->rx_stat & htole32(RX_STAT_IPCKSUMGOOD)) 712 sumflags |= M_IPV4_CSUM_IN_OK; 713 714 if (rxd->rx_stat & htole32(RX_STAT_TCPCKSUMBAD)) 715 sumflags |= M_TCP_CSUM_IN_BAD; 716 else if (rxd->rx_stat & htole32(RX_STAT_TCPCKSUMGOOD)) 717 sumflags |= M_TCP_CSUM_IN_OK; 718 719 if (rxd->rx_stat & htole32(RX_STAT_UDPCKSUMBAD)) 720 sumflags |= M_UDP_CSUM_IN_BAD; 721 else if (rxd->rx_stat & htole32(RX_STAT_UDPCKSUMGOOD)) 722 sumflags |= M_UDP_CSUM_IN_OK; 723 724 m->m_pkthdr.csum_flags = sumflags; 725 726 ether_input_mbuf(ifp, m); 727 728 next: 729 bus_dmamap_sync(sc->sc_dmat, dma->dma_map, 730 idx * sizeof(struct txp_rx_desc), sizeof(struct txp_rx_desc), 731 BUS_DMASYNC_PREREAD); 732 733 roff += sizeof(struct txp_rx_desc); 734 if (roff == (RX_ENTRIES * sizeof(struct txp_rx_desc))) { 735 idx = 0; 736 roff = 0; 737 rxd = r->r_desc; 738 } else { 739 idx++; 740 rxd++; 741 } 742 woff = letoh32(*r->r_woff); 743 } 744 745 *r->r_roff = htole32(woff); 746 } 747 748 void 749 txp_rxbuf_reclaim(struct txp_softc *sc) 750 { 751 struct ifnet *ifp = &sc->sc_arpcom.ac_if; 752 struct txp_hostvar *hv = sc->sc_hostvar; 753 struct txp_rxbuf_desc *rbd; 754 struct txp_swdesc *sd; 755 u_int32_t i, end; 756 757 end = TXP_OFFSET2IDX(letoh32(hv->hv_rx_buf_read_idx)); 758 i = TXP_OFFSET2IDX(letoh32(hv->hv_rx_buf_write_idx)); 759 760 if (++i == RXBUF_ENTRIES) 761 i = 0; 762 763 rbd = sc->sc_rxbufs + i; 764 765 while (i != end) { 766 sd = (struct txp_swdesc *)malloc(sizeof(struct txp_swdesc), 767 M_DEVBUF, M_NOWAIT); 768 if (sd == NULL) 769 break; 770 771 MGETHDR(sd->sd_mbuf, M_DONTWAIT, MT_DATA); 772 if (sd->sd_mbuf == NULL) 773 goto err_sd; 774 775 MCLGET(sd->sd_mbuf, M_DONTWAIT); 776 if ((sd->sd_mbuf->m_flags & M_EXT) == 0) 777 goto err_mbuf; 778 /* reserve some space for a possible VLAN header */ 779 sd->sd_mbuf->m_data += 8; 780 sd->sd_mbuf->m_pkthdr.len = sd->sd_mbuf->m_len = MCLBYTES - 8; 781 sd->sd_mbuf->m_pkthdr.rcvif = ifp; 782 if (bus_dmamap_create(sc->sc_dmat, TXP_MAX_PKTLEN, 1, 783 TXP_MAX_PKTLEN, 0, BUS_DMA_NOWAIT, &sd->sd_map)) 784 goto err_mbuf; 785 if (bus_dmamap_load_mbuf(sc->sc_dmat, sd->sd_map, sd->sd_mbuf, 786 BUS_DMA_NOWAIT)) { 787 bus_dmamap_destroy(sc->sc_dmat, sd->sd_map); 788 goto err_mbuf; 789 } 790 791 bus_dmamap_sync(sc->sc_dmat, sc->sc_rxbufring_dma.dma_map, 792 i * sizeof(struct txp_rxbuf_desc), 793 sizeof(struct txp_rxbuf_desc), BUS_DMASYNC_POSTWRITE); 794 795 /* stash away pointer */ 796 bcopy(&sd, (u_long *)&rbd->rb_vaddrlo, sizeof(sd)); 797 798 rbd->rb_paddrlo = ((u_int64_t)sd->sd_map->dm_segs[0].ds_addr) 799 & 0xffffffff; 800 rbd->rb_paddrhi = ((u_int64_t)sd->sd_map->dm_segs[0].ds_addr) 801 >> 32; 802 803 bus_dmamap_sync(sc->sc_dmat, sd->sd_map, 0, 804 sd->sd_map->dm_mapsize, BUS_DMASYNC_PREREAD); 805 806 bus_dmamap_sync(sc->sc_dmat, sc->sc_rxbufring_dma.dma_map, 807 i * sizeof(struct txp_rxbuf_desc), 808 sizeof(struct txp_rxbuf_desc), BUS_DMASYNC_PREWRITE); 809 810 hv->hv_rx_buf_write_idx = htole32(TXP_IDX2OFFSET(i)); 811 812 if (++i == RXBUF_ENTRIES) { 813 i = 0; 814 rbd = sc->sc_rxbufs; 815 } else 816 rbd++; 817 } 818 return; 819 820 err_mbuf: 821 m_freem(sd->sd_mbuf); 822 err_sd: 823 free(sd, M_DEVBUF); 824 } 825 826 /* 827 * Reclaim mbufs and entries from a transmit ring. 828 */ 829 void 830 txp_tx_reclaim(struct txp_softc *sc, struct txp_tx_ring *r, 831 struct txp_dma_alloc *dma) 832 { 833 struct ifnet *ifp = &sc->sc_arpcom.ac_if; 834 u_int32_t idx = TXP_OFFSET2IDX(letoh32(*(r->r_off))); 835 u_int32_t cons = r->r_cons, cnt = r->r_cnt; 836 struct txp_tx_desc *txd = r->r_desc + cons; 837 struct txp_swdesc *sd = sc->sc_txd + cons; 838 struct mbuf *m; 839 840 while (cons != idx) { 841 if (cnt == 0) 842 break; 843 844 bus_dmamap_sync(sc->sc_dmat, dma->dma_map, 845 cons * sizeof(struct txp_tx_desc), 846 sizeof(struct txp_tx_desc), 847 BUS_DMASYNC_POSTWRITE); 848 849 if ((txd->tx_flags & TX_FLAGS_TYPE_M) == 850 TX_FLAGS_TYPE_DATA) { 851 bus_dmamap_sync(sc->sc_dmat, sd->sd_map, 0, 852 sd->sd_map->dm_mapsize, BUS_DMASYNC_POSTWRITE); 853 bus_dmamap_unload(sc->sc_dmat, sd->sd_map); 854 m = sd->sd_mbuf; 855 if (m != NULL) { 856 m_freem(m); 857 txd->tx_addrlo = 0; 858 txd->tx_addrhi = 0; 859 ifp->if_opackets++; 860 } 861 } 862 ifp->if_flags &= ~IFF_OACTIVE; 863 864 if (++cons == TX_ENTRIES) { 865 txd = r->r_desc; 866 cons = 0; 867 sd = sc->sc_txd; 868 } else { 869 txd++; 870 sd++; 871 } 872 873 cnt--; 874 } 875 876 r->r_cons = cons; 877 r->r_cnt = cnt; 878 if (cnt == 0) 879 ifp->if_timer = 0; 880 } 881 882 void 883 txp_shutdown(void *vsc) 884 { 885 struct txp_softc *sc = (struct txp_softc *)vsc; 886 887 /* mask all interrupts */ 888 WRITE_REG(sc, TXP_IMR, 889 TXP_INT_SELF | TXP_INT_PCI_TABORT | TXP_INT_PCI_MABORT | 890 TXP_INT_DMA3 | TXP_INT_DMA2 | TXP_INT_DMA1 | TXP_INT_DMA0 | 891 TXP_INT_LATCH); 892 893 txp_command(sc, TXP_CMD_TX_DISABLE, 0, 0, 0, NULL, NULL, NULL, 0); 894 txp_command(sc, TXP_CMD_RX_DISABLE, 0, 0, 0, NULL, NULL, NULL, 0); 895 txp_command(sc, TXP_CMD_HALT, 0, 0, 0, NULL, NULL, NULL, 0); 896 } 897 898 int 899 txp_alloc_rings(struct txp_softc *sc) 900 { 901 struct ifnet *ifp = &sc->sc_arpcom.ac_if; 902 struct txp_boot_record *boot; 903 struct txp_swdesc *sd; 904 u_int32_t r; 905 int i, j; 906 907 /* boot record */ 908 if (txp_dma_malloc(sc, sizeof(struct txp_boot_record), &sc->sc_boot_dma, 909 BUS_DMA_COHERENT)) { 910 printf("can't allocate boot record\n"); 911 return (-1); 912 } 913 boot = (struct txp_boot_record *)sc->sc_boot_dma.dma_vaddr; 914 bzero(boot, sizeof(*boot)); 915 sc->sc_boot = boot; 916 917 /* host variables */ 918 if (txp_dma_malloc(sc, sizeof(struct txp_hostvar), &sc->sc_host_dma, 919 BUS_DMA_COHERENT)) { 920 printf("can't allocate host ring\n"); 921 goto bail_boot; 922 } 923 bzero(sc->sc_host_dma.dma_vaddr, sizeof(struct txp_hostvar)); 924 boot->br_hostvar_lo = htole32(sc->sc_host_dma.dma_paddr & 0xffffffff); 925 boot->br_hostvar_hi = htole32(sc->sc_host_dma.dma_paddr >> 32); 926 sc->sc_hostvar = (struct txp_hostvar *)sc->sc_host_dma.dma_vaddr; 927 928 /* high priority tx ring */ 929 if (txp_dma_malloc(sc, sizeof(struct txp_tx_desc) * TX_ENTRIES, 930 &sc->sc_txhiring_dma, BUS_DMA_COHERENT)) { 931 printf("can't allocate high tx ring\n"); 932 goto bail_host; 933 } 934 bzero(sc->sc_txhiring_dma.dma_vaddr, sizeof(struct txp_tx_desc) * TX_ENTRIES); 935 boot->br_txhipri_lo = htole32(sc->sc_txhiring_dma.dma_paddr & 0xffffffff); 936 boot->br_txhipri_hi = htole32(sc->sc_txhiring_dma.dma_paddr >> 32); 937 boot->br_txhipri_siz = htole32(TX_ENTRIES * sizeof(struct txp_tx_desc)); 938 sc->sc_txhir.r_reg = TXP_H2A_1; 939 sc->sc_txhir.r_desc = (struct txp_tx_desc *)sc->sc_txhiring_dma.dma_vaddr; 940 sc->sc_txhir.r_cons = sc->sc_txhir.r_prod = sc->sc_txhir.r_cnt = 0; 941 sc->sc_txhir.r_off = &sc->sc_hostvar->hv_tx_hi_desc_read_idx; 942 for (i = 0; i < TX_ENTRIES; i++) { 943 if (bus_dmamap_create(sc->sc_dmat, TXP_MAX_PKTLEN, 944 TX_ENTRIES - 4, TXP_MAX_SEGLEN, 0, 945 BUS_DMA_NOWAIT, &sc->sc_txd[i].sd_map) != 0) { 946 for (j = 0; j < i; j++) { 947 bus_dmamap_destroy(sc->sc_dmat, 948 sc->sc_txd[j].sd_map); 949 sc->sc_txd[j].sd_map = NULL; 950 } 951 goto bail_txhiring; 952 } 953 } 954 955 /* low priority tx ring */ 956 if (txp_dma_malloc(sc, sizeof(struct txp_tx_desc) * TX_ENTRIES, 957 &sc->sc_txloring_dma, BUS_DMA_COHERENT)) { 958 printf("can't allocate low tx ring\n"); 959 goto bail_txhiring; 960 } 961 bzero(sc->sc_txloring_dma.dma_vaddr, sizeof(struct txp_tx_desc) * TX_ENTRIES); 962 boot->br_txlopri_lo = htole32(sc->sc_txloring_dma.dma_paddr & 0xffffffff); 963 boot->br_txlopri_hi = htole32(sc->sc_txloring_dma.dma_paddr >> 32); 964 boot->br_txlopri_siz = htole32(TX_ENTRIES * sizeof(struct txp_tx_desc)); 965 sc->sc_txlor.r_reg = TXP_H2A_3; 966 sc->sc_txlor.r_desc = (struct txp_tx_desc *)sc->sc_txloring_dma.dma_vaddr; 967 sc->sc_txlor.r_cons = sc->sc_txlor.r_prod = sc->sc_txlor.r_cnt = 0; 968 sc->sc_txlor.r_off = &sc->sc_hostvar->hv_tx_lo_desc_read_idx; 969 970 /* high priority rx ring */ 971 if (txp_dma_malloc(sc, sizeof(struct txp_rx_desc) * RX_ENTRIES, 972 &sc->sc_rxhiring_dma, BUS_DMA_COHERENT)) { 973 printf("can't allocate high rx ring\n"); 974 goto bail_txloring; 975 } 976 bzero(sc->sc_rxhiring_dma.dma_vaddr, sizeof(struct txp_rx_desc) * RX_ENTRIES); 977 boot->br_rxhipri_lo = htole32(sc->sc_rxhiring_dma.dma_paddr & 0xffffffff); 978 boot->br_rxhipri_hi = htole32(sc->sc_rxhiring_dma.dma_paddr >> 32); 979 boot->br_rxhipri_siz = htole32(RX_ENTRIES * sizeof(struct txp_rx_desc)); 980 sc->sc_rxhir.r_desc = 981 (struct txp_rx_desc *)sc->sc_rxhiring_dma.dma_vaddr; 982 sc->sc_rxhir.r_roff = &sc->sc_hostvar->hv_rx_hi_read_idx; 983 sc->sc_rxhir.r_woff = &sc->sc_hostvar->hv_rx_hi_write_idx; 984 bus_dmamap_sync(sc->sc_dmat, sc->sc_rxhiring_dma.dma_map, 985 0, sc->sc_rxhiring_dma.dma_map->dm_mapsize, BUS_DMASYNC_PREREAD); 986 987 /* low priority ring */ 988 if (txp_dma_malloc(sc, sizeof(struct txp_rx_desc) * RX_ENTRIES, 989 &sc->sc_rxloring_dma, BUS_DMA_COHERENT)) { 990 printf("can't allocate low rx ring\n"); 991 goto bail_rxhiring; 992 } 993 bzero(sc->sc_rxloring_dma.dma_vaddr, sizeof(struct txp_rx_desc) * RX_ENTRIES); 994 boot->br_rxlopri_lo = htole32(sc->sc_rxloring_dma.dma_paddr & 0xffffffff); 995 boot->br_rxlopri_hi = htole32(sc->sc_rxloring_dma.dma_paddr >> 32); 996 boot->br_rxlopri_siz = htole32(RX_ENTRIES * sizeof(struct txp_rx_desc)); 997 sc->sc_rxlor.r_desc = 998 (struct txp_rx_desc *)sc->sc_rxloring_dma.dma_vaddr; 999 sc->sc_rxlor.r_roff = &sc->sc_hostvar->hv_rx_lo_read_idx; 1000 sc->sc_rxlor.r_woff = &sc->sc_hostvar->hv_rx_lo_write_idx; 1001 bus_dmamap_sync(sc->sc_dmat, sc->sc_rxloring_dma.dma_map, 1002 0, sc->sc_rxloring_dma.dma_map->dm_mapsize, BUS_DMASYNC_PREREAD); 1003 1004 /* command ring */ 1005 if (txp_dma_malloc(sc, sizeof(struct txp_cmd_desc) * CMD_ENTRIES, 1006 &sc->sc_cmdring_dma, BUS_DMA_COHERENT)) { 1007 printf("can't allocate command ring\n"); 1008 goto bail_rxloring; 1009 } 1010 bzero(sc->sc_cmdring_dma.dma_vaddr, sizeof(struct txp_cmd_desc) * CMD_ENTRIES); 1011 boot->br_cmd_lo = htole32(sc->sc_cmdring_dma.dma_paddr & 0xffffffff); 1012 boot->br_cmd_hi = htole32(sc->sc_cmdring_dma.dma_paddr >> 32); 1013 boot->br_cmd_siz = htole32(CMD_ENTRIES * sizeof(struct txp_cmd_desc)); 1014 sc->sc_cmdring.base = (struct txp_cmd_desc *)sc->sc_cmdring_dma.dma_vaddr; 1015 sc->sc_cmdring.size = CMD_ENTRIES * sizeof(struct txp_cmd_desc); 1016 sc->sc_cmdring.lastwrite = 0; 1017 1018 /* response ring */ 1019 if (txp_dma_malloc(sc, sizeof(struct txp_rsp_desc) * RSP_ENTRIES, 1020 &sc->sc_rspring_dma, BUS_DMA_COHERENT)) { 1021 printf("can't allocate response ring\n"); 1022 goto bail_cmdring; 1023 } 1024 bzero(sc->sc_rspring_dma.dma_vaddr, sizeof(struct txp_rsp_desc) * RSP_ENTRIES); 1025 boot->br_resp_lo = htole32(sc->sc_rspring_dma.dma_paddr & 0xffffffff); 1026 boot->br_resp_hi = htole32(sc->sc_rspring_dma.dma_paddr >> 32); 1027 boot->br_resp_siz = htole32(CMD_ENTRIES * sizeof(struct txp_rsp_desc)); 1028 sc->sc_rspring.base = (struct txp_rsp_desc *)sc->sc_rspring_dma.dma_vaddr; 1029 sc->sc_rspring.size = RSP_ENTRIES * sizeof(struct txp_rsp_desc); 1030 sc->sc_rspring.lastwrite = 0; 1031 1032 /* receive buffer ring */ 1033 if (txp_dma_malloc(sc, sizeof(struct txp_rxbuf_desc) * RXBUF_ENTRIES, 1034 &sc->sc_rxbufring_dma, BUS_DMA_COHERENT)) { 1035 printf("can't allocate rx buffer ring\n"); 1036 goto bail_rspring; 1037 } 1038 bzero(sc->sc_rxbufring_dma.dma_vaddr, sizeof(struct txp_rxbuf_desc) * RXBUF_ENTRIES); 1039 boot->br_rxbuf_lo = htole32(sc->sc_rxbufring_dma.dma_paddr & 0xffffffff); 1040 boot->br_rxbuf_hi = htole32(sc->sc_rxbufring_dma.dma_paddr >> 32); 1041 boot->br_rxbuf_siz = htole32(RXBUF_ENTRIES * sizeof(struct txp_rxbuf_desc)); 1042 sc->sc_rxbufs = (struct txp_rxbuf_desc *)sc->sc_rxbufring_dma.dma_vaddr; 1043 for (i = 0; i < RXBUF_ENTRIES; i++) { 1044 sd = (struct txp_swdesc *)malloc(sizeof(struct txp_swdesc), 1045 M_DEVBUF, M_NOWAIT); 1046 1047 /* stash away pointer */ 1048 bcopy(&sd, (u_long *)&sc->sc_rxbufs[i].rb_vaddrlo, sizeof(sd)); 1049 1050 if (sd == NULL) 1051 break; 1052 1053 MGETHDR(sd->sd_mbuf, M_DONTWAIT, MT_DATA); 1054 if (sd->sd_mbuf == NULL) { 1055 goto bail_rxbufring; 1056 } 1057 1058 MCLGET(sd->sd_mbuf, M_DONTWAIT); 1059 if ((sd->sd_mbuf->m_flags & M_EXT) == 0) { 1060 goto bail_rxbufring; 1061 } 1062 /* reserve some space for a possible VLAN header */ 1063 sd->sd_mbuf->m_data += 8; 1064 sd->sd_mbuf->m_pkthdr.len = sd->sd_mbuf->m_len = MCLBYTES - 8; 1065 sd->sd_mbuf->m_pkthdr.rcvif = ifp; 1066 if (bus_dmamap_create(sc->sc_dmat, TXP_MAX_PKTLEN, 1, 1067 TXP_MAX_PKTLEN, 0, BUS_DMA_NOWAIT, &sd->sd_map)) { 1068 goto bail_rxbufring; 1069 } 1070 if (bus_dmamap_load_mbuf(sc->sc_dmat, sd->sd_map, sd->sd_mbuf, 1071 BUS_DMA_NOWAIT)) { 1072 bus_dmamap_destroy(sc->sc_dmat, sd->sd_map); 1073 goto bail_rxbufring; 1074 } 1075 bus_dmamap_sync(sc->sc_dmat, sd->sd_map, 0, 1076 sd->sd_map->dm_mapsize, BUS_DMASYNC_PREREAD); 1077 1078 sc->sc_rxbufs[i].rb_paddrlo = 1079 ((u_int64_t)sd->sd_map->dm_segs[0].ds_addr) & 0xffffffff; 1080 sc->sc_rxbufs[i].rb_paddrhi = 1081 ((u_int64_t)sd->sd_map->dm_segs[0].ds_addr) >> 32; 1082 } 1083 bus_dmamap_sync(sc->sc_dmat, sc->sc_rxbufring_dma.dma_map, 1084 0, sc->sc_rxbufring_dma.dma_map->dm_mapsize, 1085 BUS_DMASYNC_PREWRITE); 1086 sc->sc_hostvar->hv_rx_buf_write_idx = htole32((RXBUF_ENTRIES - 1) * 1087 sizeof(struct txp_rxbuf_desc)); 1088 1089 /* zero dma */ 1090 if (txp_dma_malloc(sc, sizeof(u_int32_t), &sc->sc_zero_dma, 1091 BUS_DMA_COHERENT)) { 1092 printf("can't allocate response ring\n"); 1093 goto bail_rxbufring; 1094 } 1095 bzero(sc->sc_zero_dma.dma_vaddr, sizeof(u_int32_t)); 1096 boot->br_zero_lo = htole32(sc->sc_zero_dma.dma_paddr & 0xffffffff); 1097 boot->br_zero_hi = htole32(sc->sc_zero_dma.dma_paddr >> 32); 1098 1099 /* See if it's waiting for boot, and try to boot it */ 1100 for (i = 0; i < 10000; i++) { 1101 r = READ_REG(sc, TXP_A2H_0); 1102 if (r == STAT_WAITING_FOR_BOOT) 1103 break; 1104 DELAY(50); 1105 } 1106 if (r != STAT_WAITING_FOR_BOOT) { 1107 printf("not waiting for boot\n"); 1108 goto bail; 1109 } 1110 WRITE_REG(sc, TXP_H2A_2, sc->sc_boot_dma.dma_paddr >> 32); 1111 WRITE_REG(sc, TXP_H2A_1, sc->sc_boot_dma.dma_paddr & 0xffffffff); 1112 WRITE_REG(sc, TXP_H2A_0, TXP_BOOTCMD_REGISTER_BOOT_RECORD); 1113 1114 /* See if it booted */ 1115 for (i = 0; i < 10000; i++) { 1116 r = READ_REG(sc, TXP_A2H_0); 1117 if (r == STAT_RUNNING) 1118 break; 1119 DELAY(50); 1120 } 1121 if (r != STAT_RUNNING) { 1122 printf("fw not running\n"); 1123 goto bail; 1124 } 1125 1126 /* Clear TX and CMD ring write registers */ 1127 WRITE_REG(sc, TXP_H2A_1, TXP_BOOTCMD_NULL); 1128 WRITE_REG(sc, TXP_H2A_2, TXP_BOOTCMD_NULL); 1129 WRITE_REG(sc, TXP_H2A_3, TXP_BOOTCMD_NULL); 1130 WRITE_REG(sc, TXP_H2A_0, TXP_BOOTCMD_NULL); 1131 1132 return (0); 1133 1134 bail: 1135 txp_dma_free(sc, &sc->sc_zero_dma); 1136 bail_rxbufring: 1137 for (i = 0; i < RXBUF_ENTRIES; i++) { 1138 bcopy((u_long *)&sc->sc_rxbufs[i].rb_vaddrlo, &sd, sizeof(sd)); 1139 if (sd) 1140 free(sd, M_DEVBUF); 1141 } 1142 txp_dma_free(sc, &sc->sc_rxbufring_dma); 1143 bail_rspring: 1144 txp_dma_free(sc, &sc->sc_rspring_dma); 1145 bail_cmdring: 1146 txp_dma_free(sc, &sc->sc_cmdring_dma); 1147 bail_rxloring: 1148 txp_dma_free(sc, &sc->sc_rxloring_dma); 1149 bail_rxhiring: 1150 txp_dma_free(sc, &sc->sc_rxhiring_dma); 1151 bail_txloring: 1152 txp_dma_free(sc, &sc->sc_txloring_dma); 1153 bail_txhiring: 1154 txp_dma_free(sc, &sc->sc_txhiring_dma); 1155 bail_host: 1156 txp_dma_free(sc, &sc->sc_host_dma); 1157 bail_boot: 1158 txp_dma_free(sc, &sc->sc_boot_dma); 1159 return (-1); 1160 } 1161 1162 int 1163 txp_dma_malloc(struct txp_softc *sc, bus_size_t size, 1164 struct txp_dma_alloc *dma, int mapflags) 1165 { 1166 int r; 1167 1168 if ((r = bus_dmamem_alloc(sc->sc_dmat, size, PAGE_SIZE, 0, 1169 &dma->dma_seg, 1, &dma->dma_nseg, 0)) != 0) 1170 goto fail_0; 1171 1172 if ((r = bus_dmamem_map(sc->sc_dmat, &dma->dma_seg, dma->dma_nseg, 1173 size, &dma->dma_vaddr, mapflags | BUS_DMA_NOWAIT)) != 0) 1174 goto fail_1; 1175 1176 if ((r = bus_dmamap_create(sc->sc_dmat, size, 1, size, 0, 1177 BUS_DMA_NOWAIT, &dma->dma_map)) != 0) 1178 goto fail_2; 1179 1180 if ((r = bus_dmamap_load(sc->sc_dmat, dma->dma_map, dma->dma_vaddr, 1181 size, NULL, BUS_DMA_NOWAIT)) != 0) 1182 goto fail_3; 1183 1184 dma->dma_paddr = dma->dma_map->dm_segs[0].ds_addr; 1185 return (0); 1186 1187 fail_3: 1188 bus_dmamap_destroy(sc->sc_dmat, dma->dma_map); 1189 fail_2: 1190 bus_dmamem_unmap(sc->sc_dmat, dma->dma_vaddr, size); 1191 fail_1: 1192 bus_dmamem_free(sc->sc_dmat, &dma->dma_seg, dma->dma_nseg); 1193 fail_0: 1194 return (r); 1195 } 1196 1197 void 1198 txp_dma_free(struct txp_softc *sc, struct txp_dma_alloc *dma) 1199 { 1200 bus_dmamap_unload(sc->sc_dmat, dma->dma_map); 1201 bus_dmamem_unmap(sc->sc_dmat, dma->dma_vaddr, dma->dma_map->dm_mapsize); 1202 bus_dmamem_free(sc->sc_dmat, &dma->dma_seg, dma->dma_nseg); 1203 bus_dmamap_destroy(sc->sc_dmat, dma->dma_map); 1204 } 1205 1206 int 1207 txp_ioctl(struct ifnet *ifp, u_long command, caddr_t data) 1208 { 1209 struct txp_softc *sc = ifp->if_softc; 1210 struct ifreq *ifr = (struct ifreq *)data; 1211 struct ifaddr *ifa = (struct ifaddr *)data; 1212 int s, error = 0; 1213 1214 s = splnet(); 1215 1216 if ((error = ether_ioctl(ifp, &sc->sc_arpcom, command, data)) > 0) { 1217 splx(s); 1218 return error; 1219 } 1220 1221 switch(command) { 1222 case SIOCSIFADDR: 1223 ifp->if_flags |= IFF_UP; 1224 switch (ifa->ifa_addr->sa_family) { 1225 #ifdef INET 1226 case AF_INET: 1227 txp_init(sc); 1228 arp_ifinit(&sc->sc_arpcom, ifa); 1229 break; 1230 #endif /* INET */ 1231 default: 1232 txp_init(sc); 1233 break; 1234 } 1235 break; 1236 case SIOCSIFFLAGS: 1237 if (ifp->if_flags & IFF_UP) { 1238 txp_init(sc); 1239 } else { 1240 if (ifp->if_flags & IFF_RUNNING) 1241 txp_stop(sc); 1242 } 1243 break; 1244 case SIOCADDMULTI: 1245 case SIOCDELMULTI: 1246 error = (command == SIOCADDMULTI) ? 1247 ether_addmulti(ifr, &sc->sc_arpcom) : 1248 ether_delmulti(ifr, &sc->sc_arpcom); 1249 1250 if (error == ENETRESET) { 1251 /* 1252 * Multicast list has changed; set the hardware 1253 * filter accordingly. 1254 */ 1255 if (ifp->if_flags & IFF_RUNNING) 1256 txp_set_filter(sc); 1257 error = 0; 1258 } 1259 break; 1260 case SIOCGIFMEDIA: 1261 case SIOCSIFMEDIA: 1262 error = ifmedia_ioctl(ifp, ifr, &sc->sc_ifmedia, command); 1263 break; 1264 default: 1265 error = ENOTTY; 1266 break; 1267 } 1268 1269 splx(s); 1270 1271 return(error); 1272 } 1273 1274 void 1275 txp_init(struct txp_softc *sc) 1276 { 1277 struct ifnet *ifp = &sc->sc_arpcom.ac_if; 1278 int s; 1279 1280 txp_stop(sc); 1281 1282 s = splnet(); 1283 1284 txp_set_filter(sc); 1285 1286 txp_command(sc, TXP_CMD_TX_ENABLE, 0, 0, 0, NULL, NULL, NULL, 1); 1287 txp_command(sc, TXP_CMD_RX_ENABLE, 0, 0, 0, NULL, NULL, NULL, 1); 1288 1289 WRITE_REG(sc, TXP_IER, TXP_INT_RESERVED | TXP_INT_SELF | 1290 TXP_INT_A2H_7 | TXP_INT_A2H_6 | TXP_INT_A2H_5 | TXP_INT_A2H_4 | 1291 TXP_INT_A2H_2 | TXP_INT_A2H_1 | TXP_INT_A2H_0 | 1292 TXP_INT_DMA3 | TXP_INT_DMA2 | TXP_INT_DMA1 | TXP_INT_DMA0 | 1293 TXP_INT_PCI_TABORT | TXP_INT_PCI_MABORT | TXP_INT_LATCH); 1294 WRITE_REG(sc, TXP_IMR, TXP_INT_A2H_3); 1295 1296 ifp->if_flags |= IFF_RUNNING; 1297 ifp->if_flags &= ~IFF_OACTIVE; 1298 1299 if (!timeout_pending(&sc->sc_tick)) 1300 timeout_add_sec(&sc->sc_tick, 1); 1301 1302 splx(s); 1303 } 1304 1305 void 1306 txp_tick(void *vsc) 1307 { 1308 struct txp_softc *sc = vsc; 1309 struct ifnet *ifp = &sc->sc_arpcom.ac_if; 1310 struct txp_rsp_desc *rsp = NULL; 1311 struct txp_ext_desc *ext; 1312 int s; 1313 1314 s = splnet(); 1315 txp_rxbuf_reclaim(sc); 1316 1317 if (txp_command2(sc, TXP_CMD_READ_STATISTICS, 0, 0, 0, NULL, 0, 1318 &rsp, 1)) 1319 goto out; 1320 if (rsp->rsp_numdesc != 6) 1321 goto out; 1322 if (txp_command(sc, TXP_CMD_CLEAR_STATISTICS, 0, 0, 0, 1323 NULL, NULL, NULL, 1)) 1324 goto out; 1325 ext = (struct txp_ext_desc *)(rsp + 1); 1326 1327 ifp->if_ierrors += ext[3].ext_2 + ext[3].ext_3 + ext[3].ext_4 + 1328 ext[4].ext_1 + ext[4].ext_4; 1329 ifp->if_oerrors += ext[0].ext_1 + ext[1].ext_1 + ext[1].ext_4 + 1330 ext[2].ext_1; 1331 ifp->if_collisions += ext[0].ext_2 + ext[0].ext_3 + ext[1].ext_2 + 1332 ext[1].ext_3; 1333 ifp->if_opackets += rsp->rsp_par2; 1334 ifp->if_ipackets += ext[2].ext_3; 1335 1336 out: 1337 if (rsp != NULL) 1338 free(rsp, M_DEVBUF); 1339 1340 splx(s); 1341 timeout_add_sec(&sc->sc_tick, 1); 1342 } 1343 1344 void 1345 txp_start(struct ifnet *ifp) 1346 { 1347 struct txp_softc *sc = ifp->if_softc; 1348 struct txp_tx_ring *r = &sc->sc_txhir; 1349 struct txp_tx_desc *txd; 1350 int txdidx; 1351 struct txp_frag_desc *fxd; 1352 struct mbuf *m, *mnew; 1353 struct txp_swdesc *sd; 1354 u_int32_t firstprod, firstcnt, prod, cnt, i; 1355 #if NVLAN > 0 1356 struct ifvlan *ifv; 1357 #endif 1358 1359 if ((ifp->if_flags & (IFF_RUNNING | IFF_OACTIVE)) != IFF_RUNNING) 1360 return; 1361 1362 prod = r->r_prod; 1363 cnt = r->r_cnt; 1364 1365 while (1) { 1366 IFQ_POLL(&ifp->if_snd, m); 1367 if (m == NULL) 1368 break; 1369 mnew = NULL; 1370 1371 firstprod = prod; 1372 firstcnt = cnt; 1373 1374 sd = sc->sc_txd + prod; 1375 sd->sd_mbuf = m; 1376 1377 if (bus_dmamap_load_mbuf(sc->sc_dmat, sd->sd_map, m, 1378 BUS_DMA_NOWAIT)) { 1379 MGETHDR(mnew, M_DONTWAIT, MT_DATA); 1380 if (mnew == NULL) 1381 goto oactive1; 1382 if (m->m_pkthdr.len > MHLEN) { 1383 MCLGET(mnew, M_DONTWAIT); 1384 if ((mnew->m_flags & M_EXT) == 0) { 1385 m_freem(mnew); 1386 goto oactive1; 1387 } 1388 } 1389 m_copydata(m, 0, m->m_pkthdr.len, mtod(mnew, caddr_t)); 1390 mnew->m_pkthdr.len = mnew->m_len = m->m_pkthdr.len; 1391 IFQ_DEQUEUE(&ifp->if_snd, m); 1392 m_freem(m); 1393 m = mnew; 1394 if (bus_dmamap_load_mbuf(sc->sc_dmat, sd->sd_map, m, 1395 BUS_DMA_NOWAIT)) 1396 goto oactive1; 1397 } 1398 1399 if ((TX_ENTRIES - cnt) < 4) 1400 goto oactive; 1401 1402 txd = r->r_desc + prod; 1403 txdidx = prod; 1404 txd->tx_flags = TX_FLAGS_TYPE_DATA; 1405 txd->tx_numdesc = 0; 1406 txd->tx_addrlo = 0; 1407 txd->tx_addrhi = 0; 1408 txd->tx_totlen = m->m_pkthdr.len; 1409 txd->tx_pflags = 0; 1410 txd->tx_numdesc = sd->sd_map->dm_nsegs; 1411 1412 if (++prod == TX_ENTRIES) 1413 prod = 0; 1414 1415 if (++cnt >= (TX_ENTRIES - 4)) 1416 goto oactive; 1417 1418 #if NVLAN > 0 1419 if ((m->m_flags & (M_PROTO1|M_PKTHDR)) == (M_PROTO1|M_PKTHDR) && 1420 m->m_pkthdr.rcvif != NULL) { 1421 ifv = m->m_pkthdr.rcvif->if_softc; 1422 txd->tx_pflags = TX_PFLAGS_VLAN | 1423 (htons(ifv->ifv_tag) << TX_PFLAGS_VLANTAG_S); 1424 } 1425 #endif 1426 1427 if (m->m_pkthdr.csum_flags & M_IPV4_CSUM_OUT) 1428 txd->tx_pflags |= TX_PFLAGS_IPCKSUM; 1429 #ifdef TRY_TX_TCP_CSUM 1430 if (m->m_pkthdr.csum_flags & M_TCPV4_CSUM_OUT) 1431 txd->tx_pflags |= TX_PFLAGS_TCPCKSUM; 1432 #endif 1433 #ifdef TRY_TX_UDP_CSUM 1434 if (m->m_pkthdr.csum_flags & M_UDPV4_CSUM_OUT) 1435 txd->tx_pflags |= TX_PFLAGS_UDPCKSUM; 1436 #endif 1437 1438 bus_dmamap_sync(sc->sc_dmat, sd->sd_map, 0, 1439 sd->sd_map->dm_mapsize, BUS_DMASYNC_PREWRITE); 1440 1441 fxd = (struct txp_frag_desc *)(r->r_desc + prod); 1442 for (i = 0; i < sd->sd_map->dm_nsegs; i++) { 1443 if (++cnt >= (TX_ENTRIES - 4)) { 1444 bus_dmamap_sync(sc->sc_dmat, sd->sd_map, 1445 0, sd->sd_map->dm_mapsize, 1446 BUS_DMASYNC_POSTWRITE); 1447 goto oactive; 1448 } 1449 1450 fxd->frag_flags = FRAG_FLAGS_TYPE_FRAG | 1451 FRAG_FLAGS_VALID; 1452 fxd->frag_rsvd1 = 0; 1453 fxd->frag_len = sd->sd_map->dm_segs[i].ds_len; 1454 fxd->frag_addrlo = 1455 ((u_int64_t)sd->sd_map->dm_segs[i].ds_addr) & 1456 0xffffffff; 1457 fxd->frag_addrhi = 1458 ((u_int64_t)sd->sd_map->dm_segs[i].ds_addr) >> 1459 32; 1460 fxd->frag_rsvd2 = 0; 1461 1462 bus_dmamap_sync(sc->sc_dmat, 1463 sc->sc_txhiring_dma.dma_map, 1464 prod * sizeof(struct txp_frag_desc), 1465 sizeof(struct txp_frag_desc), BUS_DMASYNC_PREWRITE); 1466 1467 if (++prod == TX_ENTRIES) { 1468 fxd = (struct txp_frag_desc *)r->r_desc; 1469 prod = 0; 1470 } else 1471 fxd++; 1472 1473 } 1474 1475 /* 1476 * if mnew isn't NULL, we already dequeued and copied 1477 * the packet. 1478 */ 1479 if (mnew == NULL) 1480 IFQ_DEQUEUE(&ifp->if_snd, m); 1481 1482 ifp->if_timer = 5; 1483 1484 #if NBPFILTER > 0 1485 if (ifp->if_bpf) 1486 bpf_mtap(ifp->if_bpf, m, BPF_DIRECTION_OUT); 1487 #endif 1488 1489 txd->tx_flags |= TX_FLAGS_VALID; 1490 bus_dmamap_sync(sc->sc_dmat, sc->sc_txhiring_dma.dma_map, 1491 txdidx * sizeof(struct txp_tx_desc), 1492 sizeof(struct txp_tx_desc), BUS_DMASYNC_PREWRITE); 1493 1494 #if 0 1495 { 1496 struct mbuf *mx; 1497 int i; 1498 1499 printf("txd: flags 0x%x ndesc %d totlen %d pflags 0x%x\n", 1500 txd->tx_flags, txd->tx_numdesc, txd->tx_totlen, 1501 txd->tx_pflags); 1502 for (mx = m; mx != NULL; mx = mx->m_next) { 1503 for (i = 0; i < mx->m_len; i++) { 1504 printf(":%02x", 1505 (u_int8_t)m->m_data[i]); 1506 } 1507 } 1508 printf("\n"); 1509 } 1510 #endif 1511 1512 WRITE_REG(sc, r->r_reg, TXP_IDX2OFFSET(prod)); 1513 } 1514 1515 r->r_prod = prod; 1516 r->r_cnt = cnt; 1517 return; 1518 1519 oactive: 1520 bus_dmamap_unload(sc->sc_dmat, sd->sd_map); 1521 oactive1: 1522 ifp->if_flags |= IFF_OACTIVE; 1523 r->r_prod = firstprod; 1524 r->r_cnt = firstcnt; 1525 } 1526 1527 /* 1528 * Handle simple commands sent to the typhoon 1529 */ 1530 int 1531 txp_command(struct txp_softc *sc, u_int16_t id, u_int16_t in1, 1532 u_int32_t in2, u_int32_t in3, u_int16_t *out1, u_int32_t *out2, 1533 u_int32_t *out3, int wait) 1534 { 1535 struct txp_rsp_desc *rsp = NULL; 1536 1537 if (txp_command2(sc, id, in1, in2, in3, NULL, 0, &rsp, wait)) 1538 return (-1); 1539 1540 if (!wait) 1541 return (0); 1542 1543 if (out1 != NULL) 1544 *out1 = letoh16(rsp->rsp_par1); 1545 if (out2 != NULL) 1546 *out2 = letoh32(rsp->rsp_par2); 1547 if (out3 != NULL) 1548 *out3 = letoh32(rsp->rsp_par3); 1549 free(rsp, M_DEVBUF); 1550 return (0); 1551 } 1552 1553 int 1554 txp_command2(struct txp_softc *sc, u_int16_t id, u_int16_t in1, 1555 u_int32_t in2, u_int32_t in3, struct txp_ext_desc *in_extp, 1556 u_int8_t in_extn,struct txp_rsp_desc **rspp, int wait) 1557 { 1558 struct txp_hostvar *hv = sc->sc_hostvar; 1559 struct txp_cmd_desc *cmd; 1560 struct txp_ext_desc *ext; 1561 u_int32_t idx, i; 1562 u_int16_t seq; 1563 1564 if (txp_cmd_desc_numfree(sc) < (in_extn + 1)) { 1565 printf("%s: no free cmd descriptors\n", TXP_DEVNAME(sc)); 1566 return (-1); 1567 } 1568 1569 idx = sc->sc_cmdring.lastwrite; 1570 cmd = (struct txp_cmd_desc *)(((u_int8_t *)sc->sc_cmdring.base) + idx); 1571 bzero(cmd, sizeof(*cmd)); 1572 1573 cmd->cmd_numdesc = in_extn; 1574 seq = sc->sc_seq++; 1575 cmd->cmd_seq = htole16(seq); 1576 cmd->cmd_id = htole16(id); 1577 cmd->cmd_par1 = htole16(in1); 1578 cmd->cmd_par2 = htole32(in2); 1579 cmd->cmd_par3 = htole32(in3); 1580 cmd->cmd_flags = CMD_FLAGS_TYPE_CMD | 1581 (wait ? CMD_FLAGS_RESP : 0) | CMD_FLAGS_VALID; 1582 1583 idx += sizeof(struct txp_cmd_desc); 1584 if (idx == sc->sc_cmdring.size) 1585 idx = 0; 1586 1587 for (i = 0; i < in_extn; i++) { 1588 ext = (struct txp_ext_desc *)(((u_int8_t *)sc->sc_cmdring.base) + idx); 1589 bcopy(in_extp, ext, sizeof(struct txp_ext_desc)); 1590 in_extp++; 1591 idx += sizeof(struct txp_cmd_desc); 1592 if (idx == sc->sc_cmdring.size) 1593 idx = 0; 1594 } 1595 1596 sc->sc_cmdring.lastwrite = idx; 1597 1598 WRITE_REG(sc, TXP_H2A_2, sc->sc_cmdring.lastwrite); 1599 bus_dmamap_sync(sc->sc_dmat, sc->sc_host_dma.dma_map, 0, 1600 sizeof(struct txp_hostvar), BUS_DMASYNC_PREREAD); 1601 1602 if (!wait) 1603 return (0); 1604 1605 for (i = 0; i < 10000; i++) { 1606 bus_dmamap_sync(sc->sc_dmat, sc->sc_host_dma.dma_map, 0, 1607 sizeof(struct txp_hostvar), BUS_DMASYNC_POSTREAD); 1608 idx = letoh32(hv->hv_resp_read_idx); 1609 if (idx != letoh32(hv->hv_resp_write_idx)) { 1610 *rspp = NULL; 1611 if (txp_response(sc, idx, id, seq, rspp)) 1612 return (-1); 1613 if (*rspp != NULL) 1614 break; 1615 } 1616 bus_dmamap_sync(sc->sc_dmat, sc->sc_host_dma.dma_map, 0, 1617 sizeof(struct txp_hostvar), BUS_DMASYNC_PREREAD); 1618 DELAY(50); 1619 } 1620 if (i == 1000 || (*rspp) == NULL) { 1621 printf("%s: 0x%x command failed\n", TXP_DEVNAME(sc), id); 1622 return (-1); 1623 } 1624 1625 return (0); 1626 } 1627 1628 int 1629 txp_response(struct txp_softc *sc, u_int32_t ridx, u_int16_t id, 1630 u_int16_t seq, struct txp_rsp_desc **rspp) 1631 { 1632 struct txp_hostvar *hv = sc->sc_hostvar; 1633 struct txp_rsp_desc *rsp; 1634 1635 while (ridx != letoh32(hv->hv_resp_write_idx)) { 1636 rsp = (struct txp_rsp_desc *)(((u_int8_t *)sc->sc_rspring.base) + ridx); 1637 1638 if (id == letoh16(rsp->rsp_id) && letoh16(rsp->rsp_seq) == seq) { 1639 *rspp = (struct txp_rsp_desc *)malloc( 1640 sizeof(struct txp_rsp_desc) * (rsp->rsp_numdesc + 1), 1641 M_DEVBUF, M_NOWAIT); 1642 if ((*rspp) == NULL) 1643 return (-1); 1644 txp_rsp_fixup(sc, rsp, *rspp); 1645 return (0); 1646 } 1647 1648 if (rsp->rsp_flags & RSP_FLAGS_ERROR) { 1649 printf("%s: response error: id 0x%x\n", 1650 TXP_DEVNAME(sc), letoh16(rsp->rsp_id)); 1651 txp_rsp_fixup(sc, rsp, NULL); 1652 ridx = letoh32(hv->hv_resp_read_idx); 1653 continue; 1654 } 1655 1656 switch (letoh16(rsp->rsp_id)) { 1657 case TXP_CMD_CYCLE_STATISTICS: 1658 case TXP_CMD_MEDIA_STATUS_READ: 1659 break; 1660 case TXP_CMD_HELLO_RESPONSE: 1661 printf("%s: hello\n", TXP_DEVNAME(sc)); 1662 break; 1663 default: 1664 printf("%s: unknown id(0x%x)\n", TXP_DEVNAME(sc), 1665 letoh16(rsp->rsp_id)); 1666 } 1667 1668 txp_rsp_fixup(sc, rsp, NULL); 1669 ridx = letoh32(hv->hv_resp_read_idx); 1670 hv->hv_resp_read_idx = letoh32(ridx); 1671 } 1672 1673 return (0); 1674 } 1675 1676 void 1677 txp_rsp_fixup(struct txp_softc *sc, struct txp_rsp_desc *rsp, 1678 struct txp_rsp_desc *dst) 1679 { 1680 struct txp_rsp_desc *src = rsp; 1681 struct txp_hostvar *hv = sc->sc_hostvar; 1682 u_int32_t i, ridx; 1683 1684 ridx = letoh32(hv->hv_resp_read_idx); 1685 1686 for (i = 0; i < rsp->rsp_numdesc + 1; i++) { 1687 if (dst != NULL) 1688 bcopy(src, dst++, sizeof(struct txp_rsp_desc)); 1689 ridx += sizeof(struct txp_rsp_desc); 1690 if (ridx == sc->sc_rspring.size) { 1691 src = sc->sc_rspring.base; 1692 ridx = 0; 1693 } else 1694 src++; 1695 sc->sc_rspring.lastwrite = ridx; 1696 hv->hv_resp_read_idx = htole32(ridx); 1697 } 1698 1699 hv->hv_resp_read_idx = htole32(ridx); 1700 } 1701 1702 int 1703 txp_cmd_desc_numfree(struct txp_softc *sc) 1704 { 1705 struct txp_hostvar *hv = sc->sc_hostvar; 1706 struct txp_boot_record *br = sc->sc_boot; 1707 u_int32_t widx, ridx, nfree; 1708 1709 widx = sc->sc_cmdring.lastwrite; 1710 ridx = letoh32(hv->hv_cmd_read_idx); 1711 1712 if (widx == ridx) { 1713 /* Ring is completely free */ 1714 nfree = letoh32(br->br_cmd_siz) - sizeof(struct txp_cmd_desc); 1715 } else { 1716 if (widx > ridx) 1717 nfree = letoh32(br->br_cmd_siz) - 1718 (widx - ridx + sizeof(struct txp_cmd_desc)); 1719 else 1720 nfree = ridx - widx - sizeof(struct txp_cmd_desc); 1721 } 1722 1723 return (nfree / sizeof(struct txp_cmd_desc)); 1724 } 1725 1726 void 1727 txp_stop(struct txp_softc *sc) 1728 { 1729 struct ifnet *ifp = &sc->sc_arpcom.ac_if; 1730 1731 timeout_del(&sc->sc_tick); 1732 1733 /* Mark the interface as down and cancel the watchdog timer. */ 1734 ifp->if_flags &= ~(IFF_RUNNING | IFF_OACTIVE); 1735 ifp->if_timer = 0; 1736 1737 txp_command(sc, TXP_CMD_TX_DISABLE, 0, 0, 0, NULL, NULL, NULL, 1); 1738 txp_command(sc, TXP_CMD_RX_DISABLE, 0, 0, 0, NULL, NULL, NULL, 1); 1739 } 1740 1741 void 1742 txp_watchdog(struct ifnet *ifp) 1743 { 1744 } 1745 1746 int 1747 txp_ifmedia_upd(struct ifnet *ifp) 1748 { 1749 struct txp_softc *sc = ifp->if_softc; 1750 struct ifmedia *ifm = &sc->sc_ifmedia; 1751 u_int16_t new_xcvr; 1752 1753 if (IFM_TYPE(ifm->ifm_media) != IFM_ETHER) 1754 return (EINVAL); 1755 1756 if (IFM_SUBTYPE(ifm->ifm_media) == IFM_10_T) { 1757 if ((ifm->ifm_media & IFM_GMASK) == IFM_FDX) 1758 new_xcvr = TXP_XCVR_10_FDX; 1759 else 1760 new_xcvr = TXP_XCVR_10_HDX; 1761 } else if (IFM_SUBTYPE(ifm->ifm_media) == IFM_100_TX) { 1762 if ((ifm->ifm_media & IFM_GMASK) == IFM_FDX) 1763 new_xcvr = TXP_XCVR_100_FDX; 1764 else 1765 new_xcvr = TXP_XCVR_100_HDX; 1766 } else if (IFM_SUBTYPE(ifm->ifm_media) == IFM_AUTO) { 1767 new_xcvr = TXP_XCVR_AUTO; 1768 } else 1769 return (EINVAL); 1770 1771 /* nothing to do */ 1772 if (sc->sc_xcvr == new_xcvr) 1773 return (0); 1774 1775 txp_command(sc, TXP_CMD_XCVR_SELECT, new_xcvr, 0, 0, 1776 NULL, NULL, NULL, 0); 1777 sc->sc_xcvr = new_xcvr; 1778 1779 return (0); 1780 } 1781 1782 void 1783 txp_ifmedia_sts(struct ifnet *ifp, struct ifmediareq *ifmr) 1784 { 1785 struct txp_softc *sc = ifp->if_softc; 1786 struct ifmedia *ifm = &sc->sc_ifmedia; 1787 u_int16_t bmsr, bmcr, anar, anlpar; 1788 1789 ifmr->ifm_status = IFM_AVALID; 1790 ifmr->ifm_active = IFM_ETHER; 1791 1792 if (txp_command(sc, TXP_CMD_PHY_MGMT_READ, 0, MII_BMSR, 0, 1793 &bmsr, NULL, NULL, 1)) 1794 goto bail; 1795 if (txp_command(sc, TXP_CMD_PHY_MGMT_READ, 0, MII_BMSR, 0, 1796 &bmsr, NULL, NULL, 1)) 1797 goto bail; 1798 1799 if (txp_command(sc, TXP_CMD_PHY_MGMT_READ, 0, MII_BMCR, 0, 1800 &bmcr, NULL, NULL, 1)) 1801 goto bail; 1802 1803 if (txp_command(sc, TXP_CMD_PHY_MGMT_READ, 0, MII_ANAR, 0, 1804 &anar, NULL, NULL, 1)) 1805 goto bail; 1806 1807 if (txp_command(sc, TXP_CMD_PHY_MGMT_READ, 0, MII_ANLPAR, 0, 1808 &anlpar, NULL, NULL, 1)) 1809 goto bail; 1810 1811 if (bmsr & BMSR_LINK) 1812 ifmr->ifm_status |= IFM_ACTIVE; 1813 1814 if (bmcr & BMCR_ISO) { 1815 ifmr->ifm_active |= IFM_NONE; 1816 ifmr->ifm_status = 0; 1817 return; 1818 } 1819 1820 if (bmcr & BMCR_LOOP) 1821 ifmr->ifm_active |= IFM_LOOP; 1822 1823 if (bmcr & BMCR_AUTOEN) { 1824 if ((bmsr & BMSR_ACOMP) == 0) { 1825 ifmr->ifm_active |= IFM_NONE; 1826 return; 1827 } 1828 1829 anlpar &= anar; 1830 if (anlpar & ANLPAR_TX_FD) 1831 ifmr->ifm_active |= IFM_100_TX|IFM_FDX; 1832 else if (anlpar & ANLPAR_T4) 1833 ifmr->ifm_active |= IFM_100_T4|IFM_HDX; 1834 else if (anlpar & ANLPAR_TX) 1835 ifmr->ifm_active |= IFM_100_TX|IFM_HDX; 1836 else if (anlpar & ANLPAR_10_FD) 1837 ifmr->ifm_active |= IFM_10_T|IFM_FDX; 1838 else if (anlpar & ANLPAR_10) 1839 ifmr->ifm_active |= IFM_10_T|IFM_HDX; 1840 else 1841 ifmr->ifm_active |= IFM_NONE; 1842 } else 1843 ifmr->ifm_active = ifm->ifm_cur->ifm_media; 1844 return; 1845 1846 bail: 1847 ifmr->ifm_active |= IFM_NONE; 1848 ifmr->ifm_status &= ~IFM_AVALID; 1849 } 1850 1851 void 1852 txp_show_descriptor(void *d) 1853 { 1854 struct txp_cmd_desc *cmd = d; 1855 struct txp_rsp_desc *rsp = d; 1856 struct txp_tx_desc *txd = d; 1857 struct txp_frag_desc *frgd = d; 1858 1859 switch (cmd->cmd_flags & CMD_FLAGS_TYPE_M) { 1860 case CMD_FLAGS_TYPE_CMD: 1861 /* command descriptor */ 1862 printf("[cmd flags 0x%x num %d id %d seq %d par1 0x%x par2 0x%x par3 0x%x]\n", 1863 cmd->cmd_flags, cmd->cmd_numdesc, letoh16(cmd->cmd_id), 1864 letoh16(cmd->cmd_seq), letoh16(cmd->cmd_par1), 1865 letoh32(cmd->cmd_par2), letoh32(cmd->cmd_par3)); 1866 break; 1867 case CMD_FLAGS_TYPE_RESP: 1868 /* response descriptor */ 1869 printf("[rsp flags 0x%x num %d id %d seq %d par1 0x%x par2 0x%x par3 0x%x]\n", 1870 rsp->rsp_flags, rsp->rsp_numdesc, letoh16(rsp->rsp_id), 1871 letoh16(rsp->rsp_seq), letoh16(rsp->rsp_par1), 1872 letoh32(rsp->rsp_par2), letoh32(rsp->rsp_par3)); 1873 break; 1874 case CMD_FLAGS_TYPE_DATA: 1875 /* data header (assuming tx for now) */ 1876 printf("[data flags 0x%x num %d totlen %d addr 0x%x/0x%x pflags 0x%x]", 1877 txd->tx_flags, txd->tx_numdesc, txd->tx_totlen, 1878 txd->tx_addrlo, txd->tx_addrhi, txd->tx_pflags); 1879 break; 1880 case CMD_FLAGS_TYPE_FRAG: 1881 /* fragment descriptor */ 1882 printf("[frag flags 0x%x rsvd1 0x%x len %d addr 0x%x/0x%x rsvd2 0x%x]", 1883 frgd->frag_flags, frgd->frag_rsvd1, frgd->frag_len, 1884 frgd->frag_addrlo, frgd->frag_addrhi, frgd->frag_rsvd2); 1885 break; 1886 default: 1887 printf("[unknown(%x) flags 0x%x num %d id %d seq %d par1 0x%x par2 0x%x par3 0x%x]\n", 1888 cmd->cmd_flags & CMD_FLAGS_TYPE_M, 1889 cmd->cmd_flags, cmd->cmd_numdesc, letoh16(cmd->cmd_id), 1890 letoh16(cmd->cmd_seq), letoh16(cmd->cmd_par1), 1891 letoh32(cmd->cmd_par2), letoh32(cmd->cmd_par3)); 1892 break; 1893 } 1894 } 1895 1896 void 1897 txp_set_filter(struct txp_softc *sc) 1898 { 1899 struct arpcom *ac = &sc->sc_arpcom; 1900 struct ifnet *ifp = &sc->sc_arpcom.ac_if; 1901 u_int32_t hashbit, hash[2]; 1902 u_int16_t filter; 1903 int mcnt = 0; 1904 struct ether_multi *enm; 1905 struct ether_multistep step; 1906 1907 if (ifp->if_flags & IFF_PROMISC) { 1908 filter = TXP_RXFILT_PROMISC; 1909 goto setit; 1910 } 1911 1912 again: 1913 filter = TXP_RXFILT_DIRECT; 1914 1915 if (ifp->if_flags & IFF_BROADCAST) 1916 filter |= TXP_RXFILT_BROADCAST; 1917 1918 if (ifp->if_flags & IFF_ALLMULTI) 1919 filter |= TXP_RXFILT_ALLMULTI; 1920 else { 1921 hash[0] = hash[1] = 0; 1922 1923 ETHER_FIRST_MULTI(step, ac, enm); 1924 while (enm != NULL) { 1925 if (bcmp(enm->enm_addrlo, enm->enm_addrhi, ETHER_ADDR_LEN)) { 1926 /* 1927 * We must listen to a range of multicast 1928 * addresses. For now, just accept all 1929 * multicasts, rather than trying to set only 1930 * those filter bits needed to match the range. 1931 * (At this time, the only use of address 1932 * ranges is for IP multicast routing, for 1933 * which the range is big enough to require 1934 * all bits set.) 1935 */ 1936 ifp->if_flags |= IFF_ALLMULTI; 1937 goto again; 1938 } 1939 1940 mcnt++; 1941 hashbit = (u_int16_t)(ether_crc32_be(enm->enm_addrlo, 1942 ETHER_ADDR_LEN) & (64 - 1)); 1943 hash[hashbit / 32] |= (1 << hashbit % 32); 1944 ETHER_NEXT_MULTI(step, enm); 1945 } 1946 1947 if (mcnt > 0) { 1948 filter |= TXP_RXFILT_HASHMULTI; 1949 txp_command(sc, TXP_CMD_MCAST_HASH_MASK_WRITE, 1950 2, hash[0], hash[1], NULL, NULL, NULL, 0); 1951 } 1952 } 1953 1954 setit: 1955 txp_command(sc, TXP_CMD_RX_FILTER_WRITE, filter, 0, 0, 1956 NULL, NULL, NULL, 1); 1957 } 1958 1959 void 1960 txp_capabilities(struct txp_softc *sc) 1961 { 1962 struct ifnet *ifp = &sc->sc_arpcom.ac_if; 1963 struct txp_rsp_desc *rsp = NULL; 1964 struct txp_ext_desc *ext; 1965 1966 if (txp_command2(sc, TXP_CMD_OFFLOAD_READ, 0, 0, 0, NULL, 0, &rsp, 1)) 1967 goto out; 1968 1969 if (rsp->rsp_numdesc != 1) 1970 goto out; 1971 ext = (struct txp_ext_desc *)(rsp + 1); 1972 1973 sc->sc_tx_capability = ext->ext_1 & OFFLOAD_MASK; 1974 sc->sc_rx_capability = ext->ext_2 & OFFLOAD_MASK; 1975 1976 ifp->if_capabilities |= IFCAP_VLAN_MTU; 1977 1978 #if NVLAN > 0 1979 if (rsp->rsp_par2 & rsp->rsp_par3 & OFFLOAD_VLAN) { 1980 sc->sc_tx_capability |= OFFLOAD_VLAN; 1981 ifp->if_capabilities |= IFCAP_VLAN_HWTAGGING; 1982 } 1983 #endif 1984 1985 #if 0 1986 /* not ready yet */ 1987 if (rsp->rsp_par2 & rsp->rsp_par3 & OFFLOAD_IPSEC) { 1988 sc->sc_tx_capability |= OFFLOAD_IPSEC; 1989 sc->sc_rx_capability |= OFFLOAD_IPSEC; 1990 ifp->if_capabilities |= IFCAP_IPSEC; 1991 } 1992 #endif 1993 1994 if (rsp->rsp_par2 & rsp->rsp_par3 & OFFLOAD_IPCKSUM) { 1995 sc->sc_tx_capability |= OFFLOAD_IPCKSUM; 1996 sc->sc_rx_capability |= OFFLOAD_IPCKSUM; 1997 ifp->if_capabilities |= IFCAP_CSUM_IPv4; 1998 } 1999 2000 if (rsp->rsp_par2 & rsp->rsp_par3 & OFFLOAD_TCPCKSUM) { 2001 sc->sc_rx_capability |= OFFLOAD_TCPCKSUM; 2002 #ifdef TRY_TX_TCP_CSUM 2003 sc->sc_tx_capability |= OFFLOAD_TCPCKSUM; 2004 ifp->if_capabilities |= IFCAP_CSUM_TCPv4; 2005 #endif 2006 } 2007 2008 if (rsp->rsp_par2 & rsp->rsp_par3 & OFFLOAD_UDPCKSUM) { 2009 sc->sc_rx_capability |= OFFLOAD_UDPCKSUM; 2010 #ifdef TRY_TX_UDP_CSUM 2011 sc->sc_tx_capability |= OFFLOAD_UDPCKSUM; 2012 ifp->if_capabilities |= IFCAP_CSUM_UDPv4; 2013 #endif 2014 } 2015 2016 if (txp_command(sc, TXP_CMD_OFFLOAD_WRITE, 0, 2017 sc->sc_tx_capability, sc->sc_rx_capability, NULL, NULL, NULL, 1)) 2018 goto out; 2019 2020 out: 2021 if (rsp != NULL) 2022 free(rsp, M_DEVBUF); 2023 } 2024