1 /* $OpenBSD: if_txp.c,v 1.131 2024/05/24 06:02:57 jsg Exp $ */ 2 3 /* 4 * Copyright (c) 2001 5 * Jason L. Wright <jason@thought.net>, Theo de Raadt, and 6 * Aaron Campbell <aaron@monkey.org>. All rights reserved. 7 * 8 * Redistribution and use in source and binary forms, with or without 9 * modification, are permitted provided that the following conditions 10 * are met: 11 * 1. Redistributions of source code must retain the above copyright 12 * notice, this list of conditions and the following disclaimer. 13 * 2. Redistributions in binary form must reproduce the above copyright 14 * notice, this list of conditions and the following disclaimer in the 15 * documentation and/or other materials provided with the distribution. 16 * 17 * THIS SOFTWARE IS PROVIDED BY THE AUTHORS ``AS IS'' AND ANY EXPRESS OR 18 * IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED 19 * WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE 20 * ARE DISCLAIMED. IN NO EVENT SHALL THE AUTHORS OR THE VOICES IN THEIR HEADS 21 * BE LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR 22 * CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF 23 * SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS 24 * INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN 25 * CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) 26 * ARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF 27 * THE POSSIBILITY OF SUCH DAMAGE. 28 */ 29 30 /* 31 * Driver for 3c990 (Typhoon) Ethernet ASIC 32 */ 33 34 #include "bpfilter.h" 35 #include "vlan.h" 36 37 #include <sys/param.h> 38 #include <sys/systm.h> 39 #include <sys/sockio.h> 40 #include <sys/mbuf.h> 41 #include <sys/malloc.h> 42 #include <sys/socket.h> 43 #include <sys/device.h> 44 #include <sys/timeout.h> 45 46 #include <net/if.h> 47 48 #include <netinet/in.h> 49 #include <netinet/if_ether.h> 50 51 #include <net/if_media.h> 52 53 #if NBPFILTER > 0 54 #include <net/bpf.h> 55 #endif 56 57 #include <machine/bus.h> 58 59 #include <dev/mii/mii.h> 60 #include <dev/pci/pcireg.h> 61 #include <dev/pci/pcivar.h> 62 #include <dev/pci/pcidevs.h> 63 64 #include <dev/pci/if_txpreg.h> 65 66 /* 67 * These currently break the 3c990 firmware, hopefully will be resolved 68 * at some point. 69 */ 70 #undef TRY_TX_UDP_CSUM 71 #undef TRY_TX_TCP_CSUM 72 73 int txp_probe(struct device *, void *, void *); 74 void txp_attach(struct device *, struct device *, void *); 75 void txp_attachhook(struct device *); 76 int txp_intr(void *); 77 void txp_tick(void *); 78 int txp_ioctl(struct ifnet *, u_long, caddr_t); 79 void txp_start(struct ifnet *); 80 void txp_stop(struct txp_softc *); 81 void txp_init(struct txp_softc *); 82 void txp_watchdog(struct ifnet *); 83 84 int txp_chip_init(struct txp_softc *); 85 int txp_reset_adapter(struct txp_softc *); 86 int txp_download_fw(struct txp_softc *); 87 int txp_download_fw_wait(struct txp_softc *); 88 int txp_download_fw_section(struct txp_softc *, 89 struct txp_fw_section_header *, int, u_char *, size_t); 90 int txp_alloc_rings(struct txp_softc *); 91 void txp_dma_free(struct txp_softc *, struct txp_dma_alloc *); 92 int txp_dma_malloc(struct txp_softc *, bus_size_t, struct txp_dma_alloc *, int); 93 void txp_set_filter(struct txp_softc *); 94 95 int txp_cmd_desc_numfree(struct txp_softc *); 96 int txp_command(struct txp_softc *, u_int16_t, u_int16_t, u_int32_t, 97 u_int32_t, u_int16_t *, u_int32_t *, u_int32_t *, int); 98 int txp_command2(struct txp_softc *, u_int16_t, u_int16_t, 99 u_int32_t, u_int32_t, struct txp_ext_desc *, u_int8_t, 100 struct txp_rsp_desc **, int); 101 int txp_response(struct txp_softc *, u_int32_t, u_int16_t, u_int16_t, 102 struct txp_rsp_desc **); 103 void txp_rsp_fixup(struct txp_softc *, struct txp_rsp_desc *, 104 struct txp_rsp_desc *); 105 void txp_capabilities(struct txp_softc *); 106 107 void txp_ifmedia_sts(struct ifnet *, struct ifmediareq *); 108 int txp_ifmedia_upd(struct ifnet *); 109 void txp_show_descriptor(void *); 110 void txp_tx_reclaim(struct txp_softc *, struct txp_tx_ring *, 111 struct txp_dma_alloc *); 112 void txp_rxbuf_reclaim(struct txp_softc *); 113 void txp_rx_reclaim(struct txp_softc *, struct txp_rx_ring *, 114 struct txp_dma_alloc *); 115 116 const struct cfattach txp_ca = { 117 sizeof(struct txp_softc), txp_probe, txp_attach, 118 }; 119 120 struct cfdriver txp_cd = { 121 NULL, "txp", DV_IFNET 122 }; 123 124 const struct pci_matchid txp_devices[] = { 125 { PCI_VENDOR_3COM, PCI_PRODUCT_3COM_3CR990 }, 126 { PCI_VENDOR_3COM, PCI_PRODUCT_3COM_3CR990TX }, 127 { PCI_VENDOR_3COM, PCI_PRODUCT_3COM_3CR990TX95 }, 128 { PCI_VENDOR_3COM, PCI_PRODUCT_3COM_3CR990TX97 }, 129 { PCI_VENDOR_3COM, PCI_PRODUCT_3COM_3CR990SVR95 }, 130 { PCI_VENDOR_3COM, PCI_PRODUCT_3COM_3CR990SVR97 }, 131 { PCI_VENDOR_3COM, PCI_PRODUCT_3COM_3C990BTXM }, 132 { PCI_VENDOR_3COM, PCI_PRODUCT_3COM_3C990BSVR }, 133 { PCI_VENDOR_3COM, PCI_PRODUCT_3COM_3CR990FX }, 134 }; 135 136 int 137 txp_probe(struct device *parent, void *match, void *aux) 138 { 139 return (pci_matchbyid((struct pci_attach_args *)aux, txp_devices, 140 nitems(txp_devices))); 141 } 142 143 void 144 txp_attachhook(struct device *self) 145 { 146 struct txp_softc *sc = (struct txp_softc *)self; 147 struct ifnet *ifp = &sc->sc_arpcom.ac_if; 148 u_int16_t p1; 149 u_int32_t p2; 150 int s; 151 152 s = splnet(); 153 printf("%s: ", sc->sc_dev.dv_xname); 154 155 if (txp_chip_init(sc)) { 156 printf("failed chip init\n"); 157 splx(s); 158 return; 159 } 160 161 if (txp_download_fw(sc)) { 162 splx(s); 163 return; 164 } 165 166 if (txp_alloc_rings(sc)) { 167 splx(s); 168 return; 169 } 170 171 if (txp_command(sc, TXP_CMD_MAX_PKT_SIZE_WRITE, TXP_MAX_PKTLEN, 0, 0, 172 NULL, NULL, NULL, 1)) { 173 splx(s); 174 return; 175 } 176 177 if (txp_command(sc, TXP_CMD_STATION_ADDRESS_READ, 0, 0, 0, 178 &p1, &p2, NULL, 1)) { 179 splx(s); 180 return; 181 } 182 183 p1 = htole16(p1); 184 sc->sc_arpcom.ac_enaddr[0] = ((u_int8_t *)&p1)[1]; 185 sc->sc_arpcom.ac_enaddr[1] = ((u_int8_t *)&p1)[0]; 186 p2 = htole32(p2); 187 sc->sc_arpcom.ac_enaddr[2] = ((u_int8_t *)&p2)[3]; 188 sc->sc_arpcom.ac_enaddr[3] = ((u_int8_t *)&p2)[2]; 189 sc->sc_arpcom.ac_enaddr[4] = ((u_int8_t *)&p2)[1]; 190 sc->sc_arpcom.ac_enaddr[5] = ((u_int8_t *)&p2)[0]; 191 192 printf("address %s\n", ether_sprintf(sc->sc_arpcom.ac_enaddr)); 193 sc->sc_cold = 0; 194 195 ifmedia_init(&sc->sc_ifmedia, 0, txp_ifmedia_upd, txp_ifmedia_sts); 196 ifmedia_add(&sc->sc_ifmedia, IFM_ETHER|IFM_10_T, 0, NULL); 197 ifmedia_add(&sc->sc_ifmedia, IFM_ETHER|IFM_10_T|IFM_HDX, 0, NULL); 198 ifmedia_add(&sc->sc_ifmedia, IFM_ETHER|IFM_10_T|IFM_FDX, 0, NULL); 199 ifmedia_add(&sc->sc_ifmedia, IFM_ETHER|IFM_100_TX, 0, NULL); 200 ifmedia_add(&sc->sc_ifmedia, IFM_ETHER|IFM_100_TX|IFM_HDX, 0, NULL); 201 ifmedia_add(&sc->sc_ifmedia, IFM_ETHER|IFM_100_TX|IFM_FDX, 0, NULL); 202 ifmedia_add(&sc->sc_ifmedia, IFM_ETHER|IFM_AUTO, 0, NULL); 203 204 sc->sc_xcvr = TXP_XCVR_AUTO; 205 txp_command(sc, TXP_CMD_XCVR_SELECT, TXP_XCVR_AUTO, 0, 0, 206 NULL, NULL, NULL, 0); 207 ifmedia_set(&sc->sc_ifmedia, IFM_ETHER|IFM_AUTO); 208 209 ifp->if_softc = sc; 210 ifp->if_flags = IFF_BROADCAST | IFF_SIMPLEX | IFF_MULTICAST; 211 ifp->if_ioctl = txp_ioctl; 212 ifp->if_start = txp_start; 213 ifp->if_watchdog = txp_watchdog; 214 ifp->if_baudrate = IF_Mbps(10); 215 ifq_init_maxlen(&ifp->if_snd, TX_ENTRIES); 216 bcopy(sc->sc_dev.dv_xname, ifp->if_xname, IFNAMSIZ); 217 218 txp_capabilities(sc); 219 220 timeout_set(&sc->sc_tick, txp_tick, sc); 221 222 /* 223 * Attach us everywhere 224 */ 225 if_attach(ifp); 226 ether_ifattach(ifp); 227 228 splx(s); 229 } 230 231 void 232 txp_attach(struct device *parent, struct device *self, void *aux) 233 { 234 struct txp_softc *sc = (struct txp_softc *)self; 235 struct pci_attach_args *pa = aux; 236 pci_chipset_tag_t pc = pa->pa_pc; 237 pci_intr_handle_t ih; 238 const char *intrstr = NULL; 239 bus_size_t iosize; 240 241 sc->sc_cold = 1; 242 243 if (pci_mapreg_map(pa, TXP_PCI_LOMEM, PCI_MAPREG_TYPE_MEM, 0, 244 &sc->sc_bt, &sc->sc_bh, NULL, &iosize, 0)) { 245 printf(": can't map mem space %d\n", 0); 246 return; 247 } 248 249 sc->sc_dmat = pa->pa_dmat; 250 251 /* 252 * Allocate our interrupt. 253 */ 254 if (pci_intr_map(pa, &ih)) { 255 printf(": couldn't map interrupt\n"); 256 return; 257 } 258 259 intrstr = pci_intr_string(pc, ih); 260 sc->sc_ih = pci_intr_establish(pc, ih, IPL_NET, txp_intr, sc, 261 self->dv_xname); 262 if (sc->sc_ih == NULL) { 263 printf(": couldn't establish interrupt"); 264 if (intrstr != NULL) 265 printf(" at %s", intrstr); 266 printf("\n"); 267 return; 268 } 269 printf(": %s\n", intrstr); 270 271 config_mountroot(self, txp_attachhook); 272 273 } 274 275 int 276 txp_chip_init(struct txp_softc *sc) 277 { 278 /* disable interrupts */ 279 WRITE_REG(sc, TXP_IER, 0); 280 WRITE_REG(sc, TXP_IMR, 281 TXP_INT_SELF | TXP_INT_PCI_TABORT | TXP_INT_PCI_MABORT | 282 TXP_INT_DMA3 | TXP_INT_DMA2 | TXP_INT_DMA1 | TXP_INT_DMA0 | 283 TXP_INT_LATCH); 284 285 /* ack all interrupts */ 286 WRITE_REG(sc, TXP_ISR, TXP_INT_RESERVED | TXP_INT_LATCH | 287 TXP_INT_A2H_7 | TXP_INT_A2H_6 | TXP_INT_A2H_5 | TXP_INT_A2H_4 | 288 TXP_INT_SELF | TXP_INT_PCI_TABORT | TXP_INT_PCI_MABORT | 289 TXP_INT_DMA3 | TXP_INT_DMA2 | TXP_INT_DMA1 | TXP_INT_DMA0 | 290 TXP_INT_A2H_3 | TXP_INT_A2H_2 | TXP_INT_A2H_1 | TXP_INT_A2H_0); 291 292 if (txp_reset_adapter(sc)) 293 return (-1); 294 295 /* disable interrupts */ 296 WRITE_REG(sc, TXP_IER, 0); 297 WRITE_REG(sc, TXP_IMR, 298 TXP_INT_SELF | TXP_INT_PCI_TABORT | TXP_INT_PCI_MABORT | 299 TXP_INT_DMA3 | TXP_INT_DMA2 | TXP_INT_DMA1 | TXP_INT_DMA0 | 300 TXP_INT_LATCH); 301 302 /* ack all interrupts */ 303 WRITE_REG(sc, TXP_ISR, TXP_INT_RESERVED | TXP_INT_LATCH | 304 TXP_INT_A2H_7 | TXP_INT_A2H_6 | TXP_INT_A2H_5 | TXP_INT_A2H_4 | 305 TXP_INT_SELF | TXP_INT_PCI_TABORT | TXP_INT_PCI_MABORT | 306 TXP_INT_DMA3 | TXP_INT_DMA2 | TXP_INT_DMA1 | TXP_INT_DMA0 | 307 TXP_INT_A2H_3 | TXP_INT_A2H_2 | TXP_INT_A2H_1 | TXP_INT_A2H_0); 308 309 return (0); 310 } 311 312 int 313 txp_reset_adapter(struct txp_softc *sc) 314 { 315 u_int32_t r; 316 int i; 317 318 WRITE_REG(sc, TXP_SRR, TXP_SRR_ALL); 319 DELAY(1000); 320 WRITE_REG(sc, TXP_SRR, 0); 321 322 /* Should wait max 6 seconds */ 323 for (i = 0; i < 6000; i++) { 324 r = READ_REG(sc, TXP_A2H_0); 325 if (r == STAT_WAITING_FOR_HOST_REQUEST) 326 break; 327 DELAY(1000); 328 } 329 330 if (r != STAT_WAITING_FOR_HOST_REQUEST) { 331 printf("%s: reset hung\n", TXP_DEVNAME(sc)); 332 return (-1); 333 } 334 335 return (0); 336 } 337 338 int 339 txp_download_fw(struct txp_softc *sc) 340 { 341 struct txp_fw_file_header *fileheader; 342 struct txp_fw_section_header *secthead; 343 u_int32_t r, i, ier, imr; 344 size_t buflen; 345 int sect, err; 346 u_char *buf; 347 348 ier = READ_REG(sc, TXP_IER); 349 WRITE_REG(sc, TXP_IER, ier | TXP_INT_A2H_0); 350 351 imr = READ_REG(sc, TXP_IMR); 352 WRITE_REG(sc, TXP_IMR, imr | TXP_INT_A2H_0); 353 354 for (i = 0; i < 10000; i++) { 355 r = READ_REG(sc, TXP_A2H_0); 356 if (r == STAT_WAITING_FOR_HOST_REQUEST) 357 break; 358 DELAY(50); 359 } 360 if (r != STAT_WAITING_FOR_HOST_REQUEST) { 361 printf("not waiting for host request\n"); 362 return (-1); 363 } 364 365 /* Ack the status */ 366 WRITE_REG(sc, TXP_ISR, TXP_INT_A2H_0); 367 368 err = loadfirmware("3c990", &buf, &buflen); 369 if (err) { 370 printf("failed loadfirmware of file 3c990: errno %d\n", 371 err); 372 return (err); 373 } 374 375 fileheader = (struct txp_fw_file_header *)buf; 376 if (bcmp("TYPHOON", fileheader->magicid, sizeof(fileheader->magicid))) { 377 printf("firmware invalid magic\n"); 378 goto fail; 379 } 380 381 /* Tell boot firmware to get ready for image */ 382 WRITE_REG(sc, TXP_H2A_1, letoh32(fileheader->addr)); 383 WRITE_REG(sc, TXP_H2A_2, letoh32(fileheader->hmac[0])); 384 WRITE_REG(sc, TXP_H2A_3, letoh32(fileheader->hmac[1])); 385 WRITE_REG(sc, TXP_H2A_4, letoh32(fileheader->hmac[2])); 386 WRITE_REG(sc, TXP_H2A_5, letoh32(fileheader->hmac[3])); 387 WRITE_REG(sc, TXP_H2A_6, letoh32(fileheader->hmac[4])); 388 WRITE_REG(sc, TXP_H2A_0, TXP_BOOTCMD_RUNTIME_IMAGE); 389 390 if (txp_download_fw_wait(sc)) { 391 printf("fw wait failed, initial\n"); 392 goto fail; 393 } 394 395 secthead = (struct txp_fw_section_header *)(buf + 396 sizeof(struct txp_fw_file_header)); 397 398 for (sect = 0; sect < letoh32(fileheader->nsections); sect++) { 399 if (txp_download_fw_section(sc, secthead, sect, buf, buflen)) 400 goto fail; 401 secthead = (struct txp_fw_section_header *) 402 (((u_int8_t *)secthead) + letoh32(secthead->nbytes) + 403 sizeof(*secthead)); 404 } 405 406 WRITE_REG(sc, TXP_H2A_0, TXP_BOOTCMD_DOWNLOAD_COMPLETE); 407 408 for (i = 0; i < 10000; i++) { 409 r = READ_REG(sc, TXP_A2H_0); 410 if (r == STAT_WAITING_FOR_BOOT) 411 break; 412 DELAY(50); 413 } 414 if (r != STAT_WAITING_FOR_BOOT) { 415 printf("not waiting for boot\n"); 416 goto fail; 417 } 418 419 WRITE_REG(sc, TXP_IER, ier); 420 WRITE_REG(sc, TXP_IMR, imr); 421 422 free(buf, M_DEVBUF, 0); 423 return (0); 424 fail: 425 free(buf, M_DEVBUF, 0); 426 return (-1); 427 } 428 429 int 430 txp_download_fw_wait(struct txp_softc *sc) 431 { 432 u_int32_t i, r; 433 434 for (i = 0; i < 10000; i++) { 435 r = READ_REG(sc, TXP_ISR); 436 if (r & TXP_INT_A2H_0) 437 break; 438 DELAY(50); 439 } 440 441 if (!(r & TXP_INT_A2H_0)) { 442 printf("fw wait failed comm0\n"); 443 return (-1); 444 } 445 446 WRITE_REG(sc, TXP_ISR, TXP_INT_A2H_0); 447 448 r = READ_REG(sc, TXP_A2H_0); 449 if (r != STAT_WAITING_FOR_SEGMENT) { 450 printf("fw not waiting for segment\n"); 451 return (-1); 452 } 453 return (0); 454 } 455 456 int 457 txp_download_fw_section(struct txp_softc *sc, 458 struct txp_fw_section_header *sect, int sectnum, u_char *buf, 459 size_t buflen) 460 { 461 struct txp_dma_alloc dma; 462 int rseg, err = 0; 463 struct mbuf m; 464 u_int16_t csum; 465 466 /* Skip zero length sections */ 467 if (sect->nbytes == 0) 468 return (0); 469 470 /* Make sure we aren't past the end of the image */ 471 rseg = ((u_int8_t *)sect) - ((u_int8_t *)buf); 472 if (rseg >= buflen) { 473 printf("fw invalid section address, section %d\n", sectnum); 474 return (-1); 475 } 476 477 /* Make sure this section doesn't go past the end */ 478 rseg += letoh32(sect->nbytes); 479 if (rseg >= buflen) { 480 printf("fw truncated section %d\n", sectnum); 481 return (-1); 482 } 483 484 /* map a buffer, copy segment to it, get physaddr */ 485 if (txp_dma_malloc(sc, letoh32(sect->nbytes), &dma, 0)) { 486 printf("fw dma malloc failed, section %d\n", sectnum); 487 return (-1); 488 } 489 490 bcopy(((u_int8_t *)sect) + sizeof(*sect), dma.dma_vaddr, 491 letoh32(sect->nbytes)); 492 493 /* 494 * dummy up mbuf and verify section checksum 495 */ 496 m.m_type = MT_DATA; 497 m.m_next = m.m_nextpkt = NULL; 498 m.m_len = letoh32(sect->nbytes); 499 m.m_data = dma.dma_vaddr; 500 m.m_flags = 0; 501 csum = in_cksum(&m, letoh32(sect->nbytes)); 502 if (csum != sect->cksum) { 503 printf("fw section %d, bad cksum (expected 0x%x got 0x%x)\n", 504 sectnum, sect->cksum, csum); 505 err = -1; 506 goto bail; 507 } 508 509 bus_dmamap_sync(sc->sc_dmat, dma.dma_map, 0, 510 dma.dma_map->dm_mapsize, BUS_DMASYNC_PREWRITE); 511 512 WRITE_REG(sc, TXP_H2A_1, letoh32(sect->nbytes)); 513 WRITE_REG(sc, TXP_H2A_2, letoh16(sect->cksum)); 514 WRITE_REG(sc, TXP_H2A_3, letoh32(sect->addr)); 515 WRITE_REG(sc, TXP_H2A_4, dma.dma_paddr >> 32); 516 WRITE_REG(sc, TXP_H2A_5, dma.dma_paddr & 0xffffffff); 517 WRITE_REG(sc, TXP_H2A_0, TXP_BOOTCMD_SEGMENT_AVAILABLE); 518 519 if (txp_download_fw_wait(sc)) { 520 printf("%s: fw wait failed, section %d\n", 521 sc->sc_dev.dv_xname, sectnum); 522 err = -1; 523 } 524 525 bus_dmamap_sync(sc->sc_dmat, dma.dma_map, 0, 526 dma.dma_map->dm_mapsize, BUS_DMASYNC_POSTWRITE); 527 528 bail: 529 txp_dma_free(sc, &dma); 530 531 return (err); 532 } 533 534 int 535 txp_intr(void *vsc) 536 { 537 struct txp_softc *sc = vsc; 538 struct txp_hostvar *hv = sc->sc_hostvar; 539 u_int32_t isr; 540 int claimed = 0; 541 542 /* mask all interrupts */ 543 WRITE_REG(sc, TXP_IMR, TXP_INT_RESERVED | TXP_INT_SELF | 544 TXP_INT_A2H_7 | TXP_INT_A2H_6 | TXP_INT_A2H_5 | TXP_INT_A2H_4 | 545 TXP_INT_A2H_2 | TXP_INT_A2H_1 | TXP_INT_A2H_0 | 546 TXP_INT_DMA3 | TXP_INT_DMA2 | TXP_INT_DMA1 | TXP_INT_DMA0 | 547 TXP_INT_PCI_TABORT | TXP_INT_PCI_MABORT | TXP_INT_LATCH); 548 549 bus_dmamap_sync(sc->sc_dmat, sc->sc_host_dma.dma_map, 0, 550 sizeof(struct txp_hostvar), BUS_DMASYNC_POSTWRITE|BUS_DMASYNC_POSTREAD); 551 552 isr = READ_REG(sc, TXP_ISR); 553 while (isr) { 554 claimed = 1; 555 WRITE_REG(sc, TXP_ISR, isr); 556 557 if ((*sc->sc_rxhir.r_roff) != (*sc->sc_rxhir.r_woff)) 558 txp_rx_reclaim(sc, &sc->sc_rxhir, &sc->sc_rxhiring_dma); 559 if ((*sc->sc_rxlor.r_roff) != (*sc->sc_rxlor.r_woff)) 560 txp_rx_reclaim(sc, &sc->sc_rxlor, &sc->sc_rxloring_dma); 561 562 if (hv->hv_rx_buf_write_idx == hv->hv_rx_buf_read_idx) 563 txp_rxbuf_reclaim(sc); 564 565 if (sc->sc_txhir.r_cnt && (sc->sc_txhir.r_cons != 566 TXP_OFFSET2IDX(letoh32(*(sc->sc_txhir.r_off))))) 567 txp_tx_reclaim(sc, &sc->sc_txhir, &sc->sc_txhiring_dma); 568 569 if (sc->sc_txlor.r_cnt && (sc->sc_txlor.r_cons != 570 TXP_OFFSET2IDX(letoh32(*(sc->sc_txlor.r_off))))) 571 txp_tx_reclaim(sc, &sc->sc_txlor, &sc->sc_txloring_dma); 572 573 isr = READ_REG(sc, TXP_ISR); 574 } 575 576 bus_dmamap_sync(sc->sc_dmat, sc->sc_host_dma.dma_map, 0, 577 sizeof(struct txp_hostvar), BUS_DMASYNC_POSTWRITE|BUS_DMASYNC_POSTREAD); 578 579 /* unmask all interrupts */ 580 WRITE_REG(sc, TXP_IMR, TXP_INT_A2H_3); 581 582 txp_start(&sc->sc_arpcom.ac_if); 583 584 return (claimed); 585 } 586 587 void 588 txp_rx_reclaim(struct txp_softc *sc, struct txp_rx_ring *r, 589 struct txp_dma_alloc *dma) 590 { 591 struct ifnet *ifp = &sc->sc_arpcom.ac_if; 592 struct txp_rx_desc *rxd; 593 struct mbuf *m; 594 struct mbuf_list ml = MBUF_LIST_INITIALIZER(); 595 struct txp_swdesc *sd; 596 u_int32_t roff, woff; 597 int idx; 598 u_int16_t sumflags = 0; 599 600 roff = letoh32(*r->r_roff); 601 woff = letoh32(*r->r_woff); 602 idx = roff / sizeof(struct txp_rx_desc); 603 rxd = r->r_desc + idx; 604 605 while (roff != woff) { 606 607 bus_dmamap_sync(sc->sc_dmat, dma->dma_map, 608 idx * sizeof(struct txp_rx_desc), sizeof(struct txp_rx_desc), 609 BUS_DMASYNC_POSTREAD); 610 611 if (rxd->rx_flags & RX_FLAGS_ERROR) { 612 printf("%s: error 0x%x\n", sc->sc_dev.dv_xname, 613 letoh32(rxd->rx_stat)); 614 ifp->if_ierrors++; 615 goto next; 616 } 617 618 /* retrieve stashed pointer */ 619 bcopy((u_long *)&rxd->rx_vaddrlo, &sd, sizeof(sd)); 620 621 bus_dmamap_sync(sc->sc_dmat, sd->sd_map, 0, 622 sd->sd_map->dm_mapsize, BUS_DMASYNC_POSTREAD); 623 bus_dmamap_unload(sc->sc_dmat, sd->sd_map); 624 bus_dmamap_destroy(sc->sc_dmat, sd->sd_map); 625 m = sd->sd_mbuf; 626 free(sd, M_DEVBUF, 0); 627 m->m_pkthdr.len = m->m_len = letoh16(rxd->rx_len); 628 629 #ifdef __STRICT_ALIGNMENT 630 { 631 /* 632 * XXX Nice chip, except it won't accept "off by 2" 633 * buffers, so we're force to copy. Supposedly 634 * this will be fixed in a newer firmware rev 635 * and this will be temporary. 636 */ 637 struct mbuf *mnew; 638 639 MGETHDR(mnew, M_DONTWAIT, MT_DATA); 640 if (mnew == NULL) { 641 m_freem(m); 642 goto next; 643 } 644 if (m->m_len > (MHLEN - 2)) { 645 MCLGET(mnew, M_DONTWAIT); 646 if (!(mnew->m_flags & M_EXT)) { 647 m_freem(mnew); 648 m_freem(m); 649 goto next; 650 } 651 } 652 mnew->m_pkthdr.len = mnew->m_len = m->m_len; 653 mnew->m_data += 2; 654 bcopy(m->m_data, mnew->m_data, m->m_len); 655 m_freem(m); 656 m = mnew; 657 } 658 #endif 659 660 #if NVLAN > 0 661 /* 662 * XXX Another firmware bug: the vlan encapsulation 663 * is always removed, even when we tell the card not 664 * to do that. Restore the vlan encapsulation below. 665 */ 666 if (rxd->rx_stat & htole32(RX_STAT_VLAN)) { 667 m->m_pkthdr.ether_vtag = ntohs(rxd->rx_vlan >> 16); 668 m->m_flags |= M_VLANTAG; 669 } 670 #endif 671 672 if (rxd->rx_stat & htole32(RX_STAT_IPCKSUMBAD)) 673 sumflags |= M_IPV4_CSUM_IN_BAD; 674 else if (rxd->rx_stat & htole32(RX_STAT_IPCKSUMGOOD)) 675 sumflags |= M_IPV4_CSUM_IN_OK; 676 677 if (rxd->rx_stat & htole32(RX_STAT_TCPCKSUMBAD)) 678 sumflags |= M_TCP_CSUM_IN_BAD; 679 else if (rxd->rx_stat & htole32(RX_STAT_TCPCKSUMGOOD)) 680 sumflags |= M_TCP_CSUM_IN_OK; 681 682 if (rxd->rx_stat & htole32(RX_STAT_UDPCKSUMBAD)) 683 sumflags |= M_UDP_CSUM_IN_BAD; 684 else if (rxd->rx_stat & htole32(RX_STAT_UDPCKSUMGOOD)) 685 sumflags |= M_UDP_CSUM_IN_OK; 686 687 m->m_pkthdr.csum_flags = sumflags; 688 689 ml_enqueue(&ml, m); 690 691 next: 692 bus_dmamap_sync(sc->sc_dmat, dma->dma_map, 693 idx * sizeof(struct txp_rx_desc), sizeof(struct txp_rx_desc), 694 BUS_DMASYNC_PREREAD); 695 696 roff += sizeof(struct txp_rx_desc); 697 if (roff == (RX_ENTRIES * sizeof(struct txp_rx_desc))) { 698 idx = 0; 699 roff = 0; 700 rxd = r->r_desc; 701 } else { 702 idx++; 703 rxd++; 704 } 705 woff = letoh32(*r->r_woff); 706 } 707 708 if_input(ifp, &ml); 709 710 *r->r_roff = htole32(woff); 711 } 712 713 void 714 txp_rxbuf_reclaim(struct txp_softc *sc) 715 { 716 struct txp_hostvar *hv = sc->sc_hostvar; 717 struct txp_rxbuf_desc *rbd; 718 struct txp_swdesc *sd; 719 u_int32_t i, end; 720 721 end = TXP_OFFSET2IDX(letoh32(hv->hv_rx_buf_read_idx)); 722 i = TXP_OFFSET2IDX(letoh32(hv->hv_rx_buf_write_idx)); 723 724 if (++i == RXBUF_ENTRIES) 725 i = 0; 726 727 rbd = sc->sc_rxbufs + i; 728 729 while (i != end) { 730 sd = (struct txp_swdesc *)malloc(sizeof(struct txp_swdesc), 731 M_DEVBUF, M_NOWAIT); 732 if (sd == NULL) 733 break; 734 735 MGETHDR(sd->sd_mbuf, M_DONTWAIT, MT_DATA); 736 if (sd->sd_mbuf == NULL) 737 goto err_sd; 738 739 MCLGET(sd->sd_mbuf, M_DONTWAIT); 740 if ((sd->sd_mbuf->m_flags & M_EXT) == 0) 741 goto err_mbuf; 742 sd->sd_mbuf->m_pkthdr.len = sd->sd_mbuf->m_len = MCLBYTES; 743 if (bus_dmamap_create(sc->sc_dmat, TXP_MAX_PKTLEN, 1, 744 TXP_MAX_PKTLEN, 0, BUS_DMA_NOWAIT, &sd->sd_map)) 745 goto err_mbuf; 746 if (bus_dmamap_load_mbuf(sc->sc_dmat, sd->sd_map, sd->sd_mbuf, 747 BUS_DMA_NOWAIT)) { 748 bus_dmamap_destroy(sc->sc_dmat, sd->sd_map); 749 goto err_mbuf; 750 } 751 752 bus_dmamap_sync(sc->sc_dmat, sc->sc_rxbufring_dma.dma_map, 753 i * sizeof(struct txp_rxbuf_desc), 754 sizeof(struct txp_rxbuf_desc), BUS_DMASYNC_POSTWRITE); 755 756 /* stash away pointer */ 757 bcopy(&sd, (u_long *)&rbd->rb_vaddrlo, sizeof(sd)); 758 759 rbd->rb_paddrlo = ((u_int64_t)sd->sd_map->dm_segs[0].ds_addr) 760 & 0xffffffff; 761 rbd->rb_paddrhi = ((u_int64_t)sd->sd_map->dm_segs[0].ds_addr) 762 >> 32; 763 764 bus_dmamap_sync(sc->sc_dmat, sd->sd_map, 0, 765 sd->sd_map->dm_mapsize, BUS_DMASYNC_PREREAD); 766 767 bus_dmamap_sync(sc->sc_dmat, sc->sc_rxbufring_dma.dma_map, 768 i * sizeof(struct txp_rxbuf_desc), 769 sizeof(struct txp_rxbuf_desc), BUS_DMASYNC_PREWRITE); 770 771 hv->hv_rx_buf_write_idx = htole32(TXP_IDX2OFFSET(i)); 772 773 if (++i == RXBUF_ENTRIES) { 774 i = 0; 775 rbd = sc->sc_rxbufs; 776 } else 777 rbd++; 778 } 779 return; 780 781 err_mbuf: 782 m_freem(sd->sd_mbuf); 783 err_sd: 784 free(sd, M_DEVBUF, 0); 785 } 786 787 /* 788 * Reclaim mbufs and entries from a transmit ring. 789 */ 790 void 791 txp_tx_reclaim(struct txp_softc *sc, struct txp_tx_ring *r, 792 struct txp_dma_alloc *dma) 793 { 794 struct ifnet *ifp = &sc->sc_arpcom.ac_if; 795 u_int32_t idx = TXP_OFFSET2IDX(letoh32(*(r->r_off))); 796 u_int32_t cons = r->r_cons, cnt = r->r_cnt; 797 struct txp_tx_desc *txd = r->r_desc + cons; 798 struct txp_swdesc *sd = sc->sc_txd + cons; 799 struct mbuf *m; 800 801 while (cons != idx) { 802 if (cnt == 0) 803 break; 804 805 bus_dmamap_sync(sc->sc_dmat, dma->dma_map, 806 cons * sizeof(struct txp_tx_desc), 807 sizeof(struct txp_tx_desc), 808 BUS_DMASYNC_POSTWRITE); 809 810 if ((txd->tx_flags & TX_FLAGS_TYPE_M) == 811 TX_FLAGS_TYPE_DATA) { 812 bus_dmamap_sync(sc->sc_dmat, sd->sd_map, 0, 813 sd->sd_map->dm_mapsize, BUS_DMASYNC_POSTWRITE); 814 bus_dmamap_unload(sc->sc_dmat, sd->sd_map); 815 m = sd->sd_mbuf; 816 if (m != NULL) { 817 m_freem(m); 818 txd->tx_addrlo = 0; 819 txd->tx_addrhi = 0; 820 } 821 } 822 ifq_clr_oactive(&ifp->if_snd); 823 824 if (++cons == TX_ENTRIES) { 825 txd = r->r_desc; 826 cons = 0; 827 sd = sc->sc_txd; 828 } else { 829 txd++; 830 sd++; 831 } 832 833 cnt--; 834 } 835 836 r->r_cons = cons; 837 r->r_cnt = cnt; 838 if (cnt == 0) 839 ifp->if_timer = 0; 840 } 841 842 int 843 txp_alloc_rings(struct txp_softc *sc) 844 { 845 struct txp_boot_record *boot; 846 struct txp_swdesc *sd; 847 u_int32_t r; 848 int i, j; 849 850 /* boot record */ 851 if (txp_dma_malloc(sc, sizeof(struct txp_boot_record), &sc->sc_boot_dma, 852 BUS_DMA_COHERENT)) { 853 printf("can't allocate boot record\n"); 854 return (-1); 855 } 856 boot = (struct txp_boot_record *)sc->sc_boot_dma.dma_vaddr; 857 bzero(boot, sizeof(*boot)); 858 sc->sc_boot = boot; 859 860 /* host variables */ 861 if (txp_dma_malloc(sc, sizeof(struct txp_hostvar), &sc->sc_host_dma, 862 BUS_DMA_COHERENT)) { 863 printf("can't allocate host ring\n"); 864 goto bail_boot; 865 } 866 bzero(sc->sc_host_dma.dma_vaddr, sizeof(struct txp_hostvar)); 867 boot->br_hostvar_lo = htole32(sc->sc_host_dma.dma_paddr & 0xffffffff); 868 boot->br_hostvar_hi = htole32(sc->sc_host_dma.dma_paddr >> 32); 869 sc->sc_hostvar = (struct txp_hostvar *)sc->sc_host_dma.dma_vaddr; 870 871 /* high priority tx ring */ 872 if (txp_dma_malloc(sc, sizeof(struct txp_tx_desc) * TX_ENTRIES, 873 &sc->sc_txhiring_dma, BUS_DMA_COHERENT)) { 874 printf("can't allocate high tx ring\n"); 875 goto bail_host; 876 } 877 bzero(sc->sc_txhiring_dma.dma_vaddr, sizeof(struct txp_tx_desc) * TX_ENTRIES); 878 boot->br_txhipri_lo = htole32(sc->sc_txhiring_dma.dma_paddr & 0xffffffff); 879 boot->br_txhipri_hi = htole32(sc->sc_txhiring_dma.dma_paddr >> 32); 880 boot->br_txhipri_siz = htole32(TX_ENTRIES * sizeof(struct txp_tx_desc)); 881 sc->sc_txhir.r_reg = TXP_H2A_1; 882 sc->sc_txhir.r_desc = (struct txp_tx_desc *)sc->sc_txhiring_dma.dma_vaddr; 883 sc->sc_txhir.r_cons = sc->sc_txhir.r_prod = sc->sc_txhir.r_cnt = 0; 884 sc->sc_txhir.r_off = &sc->sc_hostvar->hv_tx_hi_desc_read_idx; 885 for (i = 0; i < TX_ENTRIES; i++) { 886 if (bus_dmamap_create(sc->sc_dmat, TXP_MAX_PKTLEN, 887 TXP_MAXTXSEGS, MCLBYTES, 0, BUS_DMA_NOWAIT, 888 &sc->sc_txd[i].sd_map) != 0) { 889 for (j = 0; j < i; j++) { 890 bus_dmamap_destroy(sc->sc_dmat, 891 sc->sc_txd[j].sd_map); 892 sc->sc_txd[j].sd_map = NULL; 893 } 894 goto bail_txhiring; 895 } 896 } 897 898 /* low priority tx ring */ 899 if (txp_dma_malloc(sc, sizeof(struct txp_tx_desc) * TX_ENTRIES, 900 &sc->sc_txloring_dma, BUS_DMA_COHERENT)) { 901 printf("can't allocate low tx ring\n"); 902 goto bail_txhiring; 903 } 904 bzero(sc->sc_txloring_dma.dma_vaddr, sizeof(struct txp_tx_desc) * TX_ENTRIES); 905 boot->br_txlopri_lo = htole32(sc->sc_txloring_dma.dma_paddr & 0xffffffff); 906 boot->br_txlopri_hi = htole32(sc->sc_txloring_dma.dma_paddr >> 32); 907 boot->br_txlopri_siz = htole32(TX_ENTRIES * sizeof(struct txp_tx_desc)); 908 sc->sc_txlor.r_reg = TXP_H2A_3; 909 sc->sc_txlor.r_desc = (struct txp_tx_desc *)sc->sc_txloring_dma.dma_vaddr; 910 sc->sc_txlor.r_cons = sc->sc_txlor.r_prod = sc->sc_txlor.r_cnt = 0; 911 sc->sc_txlor.r_off = &sc->sc_hostvar->hv_tx_lo_desc_read_idx; 912 913 /* high priority rx ring */ 914 if (txp_dma_malloc(sc, sizeof(struct txp_rx_desc) * RX_ENTRIES, 915 &sc->sc_rxhiring_dma, BUS_DMA_COHERENT)) { 916 printf("can't allocate high rx ring\n"); 917 goto bail_txloring; 918 } 919 bzero(sc->sc_rxhiring_dma.dma_vaddr, sizeof(struct txp_rx_desc) * RX_ENTRIES); 920 boot->br_rxhipri_lo = htole32(sc->sc_rxhiring_dma.dma_paddr & 0xffffffff); 921 boot->br_rxhipri_hi = htole32(sc->sc_rxhiring_dma.dma_paddr >> 32); 922 boot->br_rxhipri_siz = htole32(RX_ENTRIES * sizeof(struct txp_rx_desc)); 923 sc->sc_rxhir.r_desc = 924 (struct txp_rx_desc *)sc->sc_rxhiring_dma.dma_vaddr; 925 sc->sc_rxhir.r_roff = &sc->sc_hostvar->hv_rx_hi_read_idx; 926 sc->sc_rxhir.r_woff = &sc->sc_hostvar->hv_rx_hi_write_idx; 927 bus_dmamap_sync(sc->sc_dmat, sc->sc_rxhiring_dma.dma_map, 928 0, sc->sc_rxhiring_dma.dma_map->dm_mapsize, BUS_DMASYNC_PREREAD); 929 930 /* low priority ring */ 931 if (txp_dma_malloc(sc, sizeof(struct txp_rx_desc) * RX_ENTRIES, 932 &sc->sc_rxloring_dma, BUS_DMA_COHERENT)) { 933 printf("can't allocate low rx ring\n"); 934 goto bail_rxhiring; 935 } 936 bzero(sc->sc_rxloring_dma.dma_vaddr, sizeof(struct txp_rx_desc) * RX_ENTRIES); 937 boot->br_rxlopri_lo = htole32(sc->sc_rxloring_dma.dma_paddr & 0xffffffff); 938 boot->br_rxlopri_hi = htole32(sc->sc_rxloring_dma.dma_paddr >> 32); 939 boot->br_rxlopri_siz = htole32(RX_ENTRIES * sizeof(struct txp_rx_desc)); 940 sc->sc_rxlor.r_desc = 941 (struct txp_rx_desc *)sc->sc_rxloring_dma.dma_vaddr; 942 sc->sc_rxlor.r_roff = &sc->sc_hostvar->hv_rx_lo_read_idx; 943 sc->sc_rxlor.r_woff = &sc->sc_hostvar->hv_rx_lo_write_idx; 944 bus_dmamap_sync(sc->sc_dmat, sc->sc_rxloring_dma.dma_map, 945 0, sc->sc_rxloring_dma.dma_map->dm_mapsize, BUS_DMASYNC_PREREAD); 946 947 /* command ring */ 948 if (txp_dma_malloc(sc, sizeof(struct txp_cmd_desc) * CMD_ENTRIES, 949 &sc->sc_cmdring_dma, BUS_DMA_COHERENT)) { 950 printf("can't allocate command ring\n"); 951 goto bail_rxloring; 952 } 953 bzero(sc->sc_cmdring_dma.dma_vaddr, sizeof(struct txp_cmd_desc) * CMD_ENTRIES); 954 boot->br_cmd_lo = htole32(sc->sc_cmdring_dma.dma_paddr & 0xffffffff); 955 boot->br_cmd_hi = htole32(sc->sc_cmdring_dma.dma_paddr >> 32); 956 boot->br_cmd_siz = htole32(CMD_ENTRIES * sizeof(struct txp_cmd_desc)); 957 sc->sc_cmdring.base = (struct txp_cmd_desc *)sc->sc_cmdring_dma.dma_vaddr; 958 sc->sc_cmdring.size = CMD_ENTRIES * sizeof(struct txp_cmd_desc); 959 sc->sc_cmdring.lastwrite = 0; 960 961 /* response ring */ 962 if (txp_dma_malloc(sc, sizeof(struct txp_rsp_desc) * RSP_ENTRIES, 963 &sc->sc_rspring_dma, BUS_DMA_COHERENT)) { 964 printf("can't allocate response ring\n"); 965 goto bail_cmdring; 966 } 967 bzero(sc->sc_rspring_dma.dma_vaddr, sizeof(struct txp_rsp_desc) * RSP_ENTRIES); 968 boot->br_resp_lo = htole32(sc->sc_rspring_dma.dma_paddr & 0xffffffff); 969 boot->br_resp_hi = htole32(sc->sc_rspring_dma.dma_paddr >> 32); 970 boot->br_resp_siz = htole32(CMD_ENTRIES * sizeof(struct txp_rsp_desc)); 971 sc->sc_rspring.base = (struct txp_rsp_desc *)sc->sc_rspring_dma.dma_vaddr; 972 sc->sc_rspring.size = RSP_ENTRIES * sizeof(struct txp_rsp_desc); 973 sc->sc_rspring.lastwrite = 0; 974 975 /* receive buffer ring */ 976 if (txp_dma_malloc(sc, sizeof(struct txp_rxbuf_desc) * RXBUF_ENTRIES, 977 &sc->sc_rxbufring_dma, BUS_DMA_COHERENT)) { 978 printf("can't allocate rx buffer ring\n"); 979 goto bail_rspring; 980 } 981 bzero(sc->sc_rxbufring_dma.dma_vaddr, sizeof(struct txp_rxbuf_desc) * RXBUF_ENTRIES); 982 boot->br_rxbuf_lo = htole32(sc->sc_rxbufring_dma.dma_paddr & 0xffffffff); 983 boot->br_rxbuf_hi = htole32(sc->sc_rxbufring_dma.dma_paddr >> 32); 984 boot->br_rxbuf_siz = htole32(RXBUF_ENTRIES * sizeof(struct txp_rxbuf_desc)); 985 sc->sc_rxbufs = (struct txp_rxbuf_desc *)sc->sc_rxbufring_dma.dma_vaddr; 986 for (i = 0; i < RXBUF_ENTRIES; i++) { 987 sd = (struct txp_swdesc *)malloc(sizeof(struct txp_swdesc), 988 M_DEVBUF, M_NOWAIT); 989 990 /* stash away pointer */ 991 bcopy(&sd, (u_long *)&sc->sc_rxbufs[i].rb_vaddrlo, sizeof(sd)); 992 993 if (sd == NULL) 994 break; 995 996 MGETHDR(sd->sd_mbuf, M_DONTWAIT, MT_DATA); 997 if (sd->sd_mbuf == NULL) { 998 goto bail_rxbufring; 999 } 1000 1001 MCLGET(sd->sd_mbuf, M_DONTWAIT); 1002 if ((sd->sd_mbuf->m_flags & M_EXT) == 0) { 1003 goto bail_rxbufring; 1004 } 1005 sd->sd_mbuf->m_pkthdr.len = sd->sd_mbuf->m_len = MCLBYTES; 1006 if (bus_dmamap_create(sc->sc_dmat, TXP_MAX_PKTLEN, 1, 1007 TXP_MAX_PKTLEN, 0, BUS_DMA_NOWAIT, &sd->sd_map)) { 1008 goto bail_rxbufring; 1009 } 1010 if (bus_dmamap_load_mbuf(sc->sc_dmat, sd->sd_map, sd->sd_mbuf, 1011 BUS_DMA_NOWAIT)) { 1012 bus_dmamap_destroy(sc->sc_dmat, sd->sd_map); 1013 goto bail_rxbufring; 1014 } 1015 bus_dmamap_sync(sc->sc_dmat, sd->sd_map, 0, 1016 sd->sd_map->dm_mapsize, BUS_DMASYNC_PREREAD); 1017 1018 sc->sc_rxbufs[i].rb_paddrlo = 1019 ((u_int64_t)sd->sd_map->dm_segs[0].ds_addr) & 0xffffffff; 1020 sc->sc_rxbufs[i].rb_paddrhi = 1021 ((u_int64_t)sd->sd_map->dm_segs[0].ds_addr) >> 32; 1022 } 1023 bus_dmamap_sync(sc->sc_dmat, sc->sc_rxbufring_dma.dma_map, 1024 0, sc->sc_rxbufring_dma.dma_map->dm_mapsize, 1025 BUS_DMASYNC_PREWRITE); 1026 sc->sc_hostvar->hv_rx_buf_write_idx = htole32((RXBUF_ENTRIES - 1) * 1027 sizeof(struct txp_rxbuf_desc)); 1028 1029 /* zero dma */ 1030 if (txp_dma_malloc(sc, sizeof(u_int32_t), &sc->sc_zero_dma, 1031 BUS_DMA_COHERENT)) { 1032 printf("can't allocate response ring\n"); 1033 goto bail_rxbufring; 1034 } 1035 bzero(sc->sc_zero_dma.dma_vaddr, sizeof(u_int32_t)); 1036 boot->br_zero_lo = htole32(sc->sc_zero_dma.dma_paddr & 0xffffffff); 1037 boot->br_zero_hi = htole32(sc->sc_zero_dma.dma_paddr >> 32); 1038 1039 /* See if it's waiting for boot, and try to boot it */ 1040 for (i = 0; i < 10000; i++) { 1041 r = READ_REG(sc, TXP_A2H_0); 1042 if (r == STAT_WAITING_FOR_BOOT) 1043 break; 1044 DELAY(50); 1045 } 1046 if (r != STAT_WAITING_FOR_BOOT) { 1047 printf("not waiting for boot\n"); 1048 goto bail; 1049 } 1050 WRITE_REG(sc, TXP_H2A_2, sc->sc_boot_dma.dma_paddr >> 32); 1051 WRITE_REG(sc, TXP_H2A_1, sc->sc_boot_dma.dma_paddr & 0xffffffff); 1052 WRITE_REG(sc, TXP_H2A_0, TXP_BOOTCMD_REGISTER_BOOT_RECORD); 1053 1054 /* See if it booted */ 1055 for (i = 0; i < 10000; i++) { 1056 r = READ_REG(sc, TXP_A2H_0); 1057 if (r == STAT_RUNNING) 1058 break; 1059 DELAY(50); 1060 } 1061 if (r != STAT_RUNNING) { 1062 printf("fw not running\n"); 1063 goto bail; 1064 } 1065 1066 /* Clear TX and CMD ring write registers */ 1067 WRITE_REG(sc, TXP_H2A_1, TXP_BOOTCMD_NULL); 1068 WRITE_REG(sc, TXP_H2A_2, TXP_BOOTCMD_NULL); 1069 WRITE_REG(sc, TXP_H2A_3, TXP_BOOTCMD_NULL); 1070 WRITE_REG(sc, TXP_H2A_0, TXP_BOOTCMD_NULL); 1071 1072 return (0); 1073 1074 bail: 1075 txp_dma_free(sc, &sc->sc_zero_dma); 1076 bail_rxbufring: 1077 for (i = 0; i < RXBUF_ENTRIES; i++) { 1078 bcopy((u_long *)&sc->sc_rxbufs[i].rb_vaddrlo, &sd, sizeof(sd)); 1079 if (sd) 1080 free(sd, M_DEVBUF, 0); 1081 } 1082 txp_dma_free(sc, &sc->sc_rxbufring_dma); 1083 bail_rspring: 1084 txp_dma_free(sc, &sc->sc_rspring_dma); 1085 bail_cmdring: 1086 txp_dma_free(sc, &sc->sc_cmdring_dma); 1087 bail_rxloring: 1088 txp_dma_free(sc, &sc->sc_rxloring_dma); 1089 bail_rxhiring: 1090 txp_dma_free(sc, &sc->sc_rxhiring_dma); 1091 bail_txloring: 1092 txp_dma_free(sc, &sc->sc_txloring_dma); 1093 bail_txhiring: 1094 txp_dma_free(sc, &sc->sc_txhiring_dma); 1095 bail_host: 1096 txp_dma_free(sc, &sc->sc_host_dma); 1097 bail_boot: 1098 txp_dma_free(sc, &sc->sc_boot_dma); 1099 return (-1); 1100 } 1101 1102 int 1103 txp_dma_malloc(struct txp_softc *sc, bus_size_t size, 1104 struct txp_dma_alloc *dma, int mapflags) 1105 { 1106 int r; 1107 1108 if ((r = bus_dmamem_alloc(sc->sc_dmat, size, PAGE_SIZE, 0, 1109 &dma->dma_seg, 1, &dma->dma_nseg, 0)) != 0) 1110 goto fail_0; 1111 1112 if ((r = bus_dmamem_map(sc->sc_dmat, &dma->dma_seg, dma->dma_nseg, 1113 size, &dma->dma_vaddr, mapflags | BUS_DMA_NOWAIT)) != 0) 1114 goto fail_1; 1115 1116 if ((r = bus_dmamap_create(sc->sc_dmat, size, 1, size, 0, 1117 BUS_DMA_NOWAIT, &dma->dma_map)) != 0) 1118 goto fail_2; 1119 1120 if ((r = bus_dmamap_load(sc->sc_dmat, dma->dma_map, dma->dma_vaddr, 1121 size, NULL, BUS_DMA_NOWAIT)) != 0) 1122 goto fail_3; 1123 1124 dma->dma_paddr = dma->dma_map->dm_segs[0].ds_addr; 1125 return (0); 1126 1127 fail_3: 1128 bus_dmamap_destroy(sc->sc_dmat, dma->dma_map); 1129 fail_2: 1130 bus_dmamem_unmap(sc->sc_dmat, dma->dma_vaddr, size); 1131 fail_1: 1132 bus_dmamem_free(sc->sc_dmat, &dma->dma_seg, dma->dma_nseg); 1133 fail_0: 1134 return (r); 1135 } 1136 1137 void 1138 txp_dma_free(struct txp_softc *sc, struct txp_dma_alloc *dma) 1139 { 1140 bus_dmamap_unload(sc->sc_dmat, dma->dma_map); 1141 bus_dmamem_unmap(sc->sc_dmat, dma->dma_vaddr, dma->dma_map->dm_mapsize); 1142 bus_dmamem_free(sc->sc_dmat, &dma->dma_seg, dma->dma_nseg); 1143 bus_dmamap_destroy(sc->sc_dmat, dma->dma_map); 1144 } 1145 1146 int 1147 txp_ioctl(struct ifnet *ifp, u_long command, caddr_t data) 1148 { 1149 struct txp_softc *sc = ifp->if_softc; 1150 struct ifreq *ifr = (struct ifreq *) data; 1151 int s, error = 0; 1152 1153 s = splnet(); 1154 1155 switch(command) { 1156 case SIOCSIFADDR: 1157 ifp->if_flags |= IFF_UP; 1158 txp_init(sc); 1159 break; 1160 1161 case SIOCSIFFLAGS: 1162 if (ifp->if_flags & IFF_UP) { 1163 txp_init(sc); 1164 } else { 1165 if (ifp->if_flags & IFF_RUNNING) 1166 txp_stop(sc); 1167 } 1168 break; 1169 1170 case SIOCGIFMEDIA: 1171 case SIOCSIFMEDIA: 1172 error = ifmedia_ioctl(ifp, ifr, &sc->sc_ifmedia, command); 1173 break; 1174 1175 default: 1176 error = ether_ioctl(ifp, &sc->sc_arpcom, command, data); 1177 } 1178 1179 if (error == ENETRESET) { 1180 if (ifp->if_flags & IFF_RUNNING) 1181 txp_set_filter(sc); 1182 error = 0; 1183 } 1184 1185 splx(s); 1186 return(error); 1187 } 1188 1189 void 1190 txp_init(struct txp_softc *sc) 1191 { 1192 struct ifnet *ifp = &sc->sc_arpcom.ac_if; 1193 int s; 1194 1195 txp_stop(sc); 1196 1197 s = splnet(); 1198 1199 txp_set_filter(sc); 1200 1201 txp_command(sc, TXP_CMD_TX_ENABLE, 0, 0, 0, NULL, NULL, NULL, 1); 1202 txp_command(sc, TXP_CMD_RX_ENABLE, 0, 0, 0, NULL, NULL, NULL, 1); 1203 1204 WRITE_REG(sc, TXP_IER, TXP_INT_RESERVED | TXP_INT_SELF | 1205 TXP_INT_A2H_7 | TXP_INT_A2H_6 | TXP_INT_A2H_5 | TXP_INT_A2H_4 | 1206 TXP_INT_A2H_2 | TXP_INT_A2H_1 | TXP_INT_A2H_0 | 1207 TXP_INT_DMA3 | TXP_INT_DMA2 | TXP_INT_DMA1 | TXP_INT_DMA0 | 1208 TXP_INT_PCI_TABORT | TXP_INT_PCI_MABORT | TXP_INT_LATCH); 1209 WRITE_REG(sc, TXP_IMR, TXP_INT_A2H_3); 1210 1211 ifp->if_flags |= IFF_RUNNING; 1212 ifq_clr_oactive(&ifp->if_snd); 1213 1214 if (!timeout_pending(&sc->sc_tick)) 1215 timeout_add_sec(&sc->sc_tick, 1); 1216 1217 splx(s); 1218 } 1219 1220 void 1221 txp_tick(void *vsc) 1222 { 1223 struct txp_softc *sc = vsc; 1224 struct ifnet *ifp = &sc->sc_arpcom.ac_if; 1225 struct txp_rsp_desc *rsp = NULL; 1226 struct txp_ext_desc *ext; 1227 int s; 1228 1229 s = splnet(); 1230 txp_rxbuf_reclaim(sc); 1231 1232 if (txp_command2(sc, TXP_CMD_READ_STATISTICS, 0, 0, 0, NULL, 0, 1233 &rsp, 1)) 1234 goto out; 1235 if (rsp->rsp_numdesc != 6) 1236 goto out; 1237 if (txp_command(sc, TXP_CMD_CLEAR_STATISTICS, 0, 0, 0, 1238 NULL, NULL, NULL, 1)) 1239 goto out; 1240 ext = (struct txp_ext_desc *)(rsp + 1); 1241 1242 ifp->if_ierrors += ext[3].ext_2 + ext[3].ext_3 + ext[3].ext_4 + 1243 ext[4].ext_1 + ext[4].ext_4; 1244 ifp->if_oerrors += ext[0].ext_1 + ext[1].ext_1 + ext[1].ext_4 + 1245 ext[2].ext_1; 1246 ifp->if_collisions += ext[0].ext_2 + ext[0].ext_3 + ext[1].ext_2 + 1247 ext[1].ext_3; 1248 1249 out: 1250 if (rsp != NULL) 1251 free(rsp, M_DEVBUF, 0); 1252 1253 splx(s); 1254 timeout_add_sec(&sc->sc_tick, 1); 1255 } 1256 1257 void 1258 txp_start(struct ifnet *ifp) 1259 { 1260 struct txp_softc *sc = ifp->if_softc; 1261 struct txp_tx_ring *r = &sc->sc_txhir; 1262 struct txp_tx_desc *txd; 1263 int txdidx; 1264 struct txp_frag_desc *fxd; 1265 struct mbuf *m; 1266 struct txp_swdesc *sd; 1267 u_int32_t prod, cnt, i; 1268 1269 if (!(ifp->if_flags & IFF_RUNNING) || ifq_is_oactive(&ifp->if_snd)) 1270 return; 1271 1272 prod = r->r_prod; 1273 cnt = r->r_cnt; 1274 1275 while (1) { 1276 if (cnt >= TX_ENTRIES - TXP_MAXTXSEGS - 4) 1277 goto oactive; 1278 1279 m = ifq_dequeue(&ifp->if_snd); 1280 if (m == NULL) 1281 break; 1282 1283 sd = sc->sc_txd + prod; 1284 sd->sd_mbuf = m; 1285 1286 switch (bus_dmamap_load_mbuf(sc->sc_dmat, sd->sd_map, m, 1287 BUS_DMA_NOWAIT)) { 1288 case 0: 1289 break; 1290 case EFBIG: 1291 if (m_defrag(m, M_DONTWAIT) == 0 && 1292 bus_dmamap_load_mbuf(sc->sc_dmat, sd->sd_map, m, 1293 BUS_DMA_NOWAIT) == 0) 1294 break; 1295 default: 1296 m_freem(m); 1297 continue; 1298 } 1299 1300 txd = r->r_desc + prod; 1301 txdidx = prod; 1302 txd->tx_flags = TX_FLAGS_TYPE_DATA; 1303 txd->tx_numdesc = 0; 1304 txd->tx_addrlo = 0; 1305 txd->tx_addrhi = 0; 1306 txd->tx_totlen = m->m_pkthdr.len; 1307 txd->tx_pflags = 0; 1308 txd->tx_numdesc = sd->sd_map->dm_nsegs; 1309 1310 if (++prod == TX_ENTRIES) 1311 prod = 0; 1312 1313 #if NVLAN > 0 1314 if (m->m_flags & M_VLANTAG) { 1315 txd->tx_pflags = TX_PFLAGS_VLAN | 1316 (htons(m->m_pkthdr.ether_vtag) << TX_PFLAGS_VLANTAG_S); 1317 } 1318 #endif 1319 1320 if (m->m_pkthdr.csum_flags & M_IPV4_CSUM_OUT) 1321 txd->tx_pflags |= TX_PFLAGS_IPCKSUM; 1322 #ifdef TRY_TX_TCP_CSUM 1323 if (m->m_pkthdr.csum_flags & M_TCP_CSUM_OUT) 1324 txd->tx_pflags |= TX_PFLAGS_TCPCKSUM; 1325 #endif 1326 #ifdef TRY_TX_UDP_CSUM 1327 if (m->m_pkthdr.csum_flags & M_UDP_CSUM_OUT) 1328 txd->tx_pflags |= TX_PFLAGS_UDPCKSUM; 1329 #endif 1330 1331 bus_dmamap_sync(sc->sc_dmat, sd->sd_map, 0, 1332 sd->sd_map->dm_mapsize, BUS_DMASYNC_PREWRITE); 1333 1334 fxd = (struct txp_frag_desc *)(r->r_desc + prod); 1335 for (i = 0; i < sd->sd_map->dm_nsegs; i++) { 1336 fxd->frag_flags = FRAG_FLAGS_TYPE_FRAG | 1337 FRAG_FLAGS_VALID; 1338 fxd->frag_rsvd1 = 0; 1339 fxd->frag_len = sd->sd_map->dm_segs[i].ds_len; 1340 fxd->frag_addrlo = 1341 ((u_int64_t)sd->sd_map->dm_segs[i].ds_addr) & 1342 0xffffffff; 1343 fxd->frag_addrhi = 1344 ((u_int64_t)sd->sd_map->dm_segs[i].ds_addr) >> 1345 32; 1346 fxd->frag_rsvd2 = 0; 1347 1348 bus_dmamap_sync(sc->sc_dmat, 1349 sc->sc_txhiring_dma.dma_map, 1350 prod * sizeof(struct txp_frag_desc), 1351 sizeof(struct txp_frag_desc), BUS_DMASYNC_PREWRITE); 1352 1353 if (++prod == TX_ENTRIES) { 1354 fxd = (struct txp_frag_desc *)r->r_desc; 1355 prod = 0; 1356 } else 1357 fxd++; 1358 1359 } 1360 1361 ifp->if_timer = 5; 1362 1363 #if NBPFILTER > 0 1364 if (ifp->if_bpf) 1365 bpf_mtap_ether(ifp->if_bpf, m, BPF_DIRECTION_OUT); 1366 #endif 1367 1368 txd->tx_flags |= TX_FLAGS_VALID; 1369 bus_dmamap_sync(sc->sc_dmat, sc->sc_txhiring_dma.dma_map, 1370 txdidx * sizeof(struct txp_tx_desc), 1371 sizeof(struct txp_tx_desc), BUS_DMASYNC_PREWRITE); 1372 1373 #if 0 1374 { 1375 struct mbuf *mx; 1376 int i; 1377 1378 printf("txd: flags 0x%x ndesc %d totlen %d pflags 0x%x\n", 1379 txd->tx_flags, txd->tx_numdesc, txd->tx_totlen, 1380 txd->tx_pflags); 1381 for (mx = m; mx != NULL; mx = mx->m_next) { 1382 for (i = 0; i < mx->m_len; i++) { 1383 printf(":%02x", 1384 (u_int8_t)m->m_data[i]); 1385 } 1386 } 1387 printf("\n"); 1388 } 1389 #endif 1390 1391 WRITE_REG(sc, r->r_reg, TXP_IDX2OFFSET(prod)); 1392 } 1393 1394 r->r_prod = prod; 1395 r->r_cnt = cnt; 1396 return; 1397 1398 oactive: 1399 ifq_set_oactive(&ifp->if_snd); 1400 r->r_prod = prod; 1401 r->r_cnt = cnt; 1402 } 1403 1404 /* 1405 * Handle simple commands sent to the typhoon 1406 */ 1407 int 1408 txp_command(struct txp_softc *sc, u_int16_t id, u_int16_t in1, 1409 u_int32_t in2, u_int32_t in3, u_int16_t *out1, u_int32_t *out2, 1410 u_int32_t *out3, int wait) 1411 { 1412 struct txp_rsp_desc *rsp = NULL; 1413 1414 if (txp_command2(sc, id, in1, in2, in3, NULL, 0, &rsp, wait)) 1415 return (-1); 1416 1417 if (!wait) 1418 return (0); 1419 1420 if (out1 != NULL) 1421 *out1 = letoh16(rsp->rsp_par1); 1422 if (out2 != NULL) 1423 *out2 = letoh32(rsp->rsp_par2); 1424 if (out3 != NULL) 1425 *out3 = letoh32(rsp->rsp_par3); 1426 free(rsp, M_DEVBUF, 0); 1427 return (0); 1428 } 1429 1430 int 1431 txp_command2(struct txp_softc *sc, u_int16_t id, u_int16_t in1, 1432 u_int32_t in2, u_int32_t in3, struct txp_ext_desc *in_extp, 1433 u_int8_t in_extn,struct txp_rsp_desc **rspp, int wait) 1434 { 1435 struct txp_hostvar *hv = sc->sc_hostvar; 1436 struct txp_cmd_desc *cmd; 1437 struct txp_ext_desc *ext; 1438 u_int32_t idx, i; 1439 u_int16_t seq; 1440 1441 if (txp_cmd_desc_numfree(sc) < (in_extn + 1)) { 1442 printf("%s: no free cmd descriptors\n", TXP_DEVNAME(sc)); 1443 return (-1); 1444 } 1445 1446 idx = sc->sc_cmdring.lastwrite; 1447 cmd = (struct txp_cmd_desc *)(((u_int8_t *)sc->sc_cmdring.base) + idx); 1448 bzero(cmd, sizeof(*cmd)); 1449 1450 cmd->cmd_numdesc = in_extn; 1451 seq = sc->sc_seq++; 1452 cmd->cmd_seq = htole16(seq); 1453 cmd->cmd_id = htole16(id); 1454 cmd->cmd_par1 = htole16(in1); 1455 cmd->cmd_par2 = htole32(in2); 1456 cmd->cmd_par3 = htole32(in3); 1457 cmd->cmd_flags = CMD_FLAGS_TYPE_CMD | 1458 (wait ? CMD_FLAGS_RESP : 0) | CMD_FLAGS_VALID; 1459 1460 idx += sizeof(struct txp_cmd_desc); 1461 if (idx == sc->sc_cmdring.size) 1462 idx = 0; 1463 1464 for (i = 0; i < in_extn; i++) { 1465 ext = (struct txp_ext_desc *)(((u_int8_t *)sc->sc_cmdring.base) + idx); 1466 bcopy(in_extp, ext, sizeof(struct txp_ext_desc)); 1467 in_extp++; 1468 idx += sizeof(struct txp_cmd_desc); 1469 if (idx == sc->sc_cmdring.size) 1470 idx = 0; 1471 } 1472 1473 sc->sc_cmdring.lastwrite = idx; 1474 1475 WRITE_REG(sc, TXP_H2A_2, sc->sc_cmdring.lastwrite); 1476 bus_dmamap_sync(sc->sc_dmat, sc->sc_host_dma.dma_map, 0, 1477 sizeof(struct txp_hostvar), BUS_DMASYNC_PREREAD); 1478 1479 if (!wait) 1480 return (0); 1481 1482 for (i = 0; i < 10000; i++) { 1483 bus_dmamap_sync(sc->sc_dmat, sc->sc_host_dma.dma_map, 0, 1484 sizeof(struct txp_hostvar), BUS_DMASYNC_POSTREAD); 1485 idx = letoh32(hv->hv_resp_read_idx); 1486 if (idx != letoh32(hv->hv_resp_write_idx)) { 1487 *rspp = NULL; 1488 if (txp_response(sc, idx, id, seq, rspp)) 1489 return (-1); 1490 if (*rspp != NULL) 1491 break; 1492 } 1493 bus_dmamap_sync(sc->sc_dmat, sc->sc_host_dma.dma_map, 0, 1494 sizeof(struct txp_hostvar), BUS_DMASYNC_PREREAD); 1495 DELAY(50); 1496 } 1497 if (i == 1000 || (*rspp) == NULL) { 1498 printf("%s: 0x%x command failed\n", TXP_DEVNAME(sc), id); 1499 return (-1); 1500 } 1501 1502 return (0); 1503 } 1504 1505 int 1506 txp_response(struct txp_softc *sc, u_int32_t ridx, u_int16_t id, 1507 u_int16_t seq, struct txp_rsp_desc **rspp) 1508 { 1509 struct txp_hostvar *hv = sc->sc_hostvar; 1510 struct txp_rsp_desc *rsp; 1511 1512 while (ridx != letoh32(hv->hv_resp_write_idx)) { 1513 rsp = (struct txp_rsp_desc *)(((u_int8_t *)sc->sc_rspring.base) + ridx); 1514 1515 if (id == letoh16(rsp->rsp_id) && letoh16(rsp->rsp_seq) == seq) { 1516 *rspp = mallocarray(rsp->rsp_numdesc + 1, 1517 sizeof(struct txp_rsp_desc), M_DEVBUF, M_NOWAIT); 1518 if ((*rspp) == NULL) 1519 return (-1); 1520 txp_rsp_fixup(sc, rsp, *rspp); 1521 return (0); 1522 } 1523 1524 if (rsp->rsp_flags & RSP_FLAGS_ERROR) { 1525 printf("%s: response error: id 0x%x\n", 1526 TXP_DEVNAME(sc), letoh16(rsp->rsp_id)); 1527 txp_rsp_fixup(sc, rsp, NULL); 1528 ridx = letoh32(hv->hv_resp_read_idx); 1529 continue; 1530 } 1531 1532 switch (letoh16(rsp->rsp_id)) { 1533 case TXP_CMD_CYCLE_STATISTICS: 1534 case TXP_CMD_MEDIA_STATUS_READ: 1535 break; 1536 case TXP_CMD_HELLO_RESPONSE: 1537 printf("%s: hello\n", TXP_DEVNAME(sc)); 1538 break; 1539 default: 1540 printf("%s: unknown id(0x%x)\n", TXP_DEVNAME(sc), 1541 letoh16(rsp->rsp_id)); 1542 } 1543 1544 txp_rsp_fixup(sc, rsp, NULL); 1545 ridx = letoh32(hv->hv_resp_read_idx); 1546 hv->hv_resp_read_idx = letoh32(ridx); 1547 } 1548 1549 return (0); 1550 } 1551 1552 void 1553 txp_rsp_fixup(struct txp_softc *sc, struct txp_rsp_desc *rsp, 1554 struct txp_rsp_desc *dst) 1555 { 1556 struct txp_rsp_desc *src = rsp; 1557 struct txp_hostvar *hv = sc->sc_hostvar; 1558 u_int32_t i, ridx; 1559 1560 ridx = letoh32(hv->hv_resp_read_idx); 1561 1562 for (i = 0; i < rsp->rsp_numdesc + 1; i++) { 1563 if (dst != NULL) 1564 bcopy(src, dst++, sizeof(struct txp_rsp_desc)); 1565 ridx += sizeof(struct txp_rsp_desc); 1566 if (ridx == sc->sc_rspring.size) { 1567 src = sc->sc_rspring.base; 1568 ridx = 0; 1569 } else 1570 src++; 1571 sc->sc_rspring.lastwrite = ridx; 1572 hv->hv_resp_read_idx = htole32(ridx); 1573 } 1574 1575 hv->hv_resp_read_idx = htole32(ridx); 1576 } 1577 1578 int 1579 txp_cmd_desc_numfree(struct txp_softc *sc) 1580 { 1581 struct txp_hostvar *hv = sc->sc_hostvar; 1582 struct txp_boot_record *br = sc->sc_boot; 1583 u_int32_t widx, ridx, nfree; 1584 1585 widx = sc->sc_cmdring.lastwrite; 1586 ridx = letoh32(hv->hv_cmd_read_idx); 1587 1588 if (widx == ridx) { 1589 /* Ring is completely free */ 1590 nfree = letoh32(br->br_cmd_siz) - sizeof(struct txp_cmd_desc); 1591 } else { 1592 if (widx > ridx) 1593 nfree = letoh32(br->br_cmd_siz) - 1594 (widx - ridx + sizeof(struct txp_cmd_desc)); 1595 else 1596 nfree = ridx - widx - sizeof(struct txp_cmd_desc); 1597 } 1598 1599 return (nfree / sizeof(struct txp_cmd_desc)); 1600 } 1601 1602 void 1603 txp_stop(struct txp_softc *sc) 1604 { 1605 struct ifnet *ifp = &sc->sc_arpcom.ac_if; 1606 1607 timeout_del(&sc->sc_tick); 1608 1609 /* Mark the interface as down and cancel the watchdog timer. */ 1610 ifp->if_flags &= ~IFF_RUNNING; 1611 ifq_clr_oactive(&ifp->if_snd); 1612 ifp->if_timer = 0; 1613 1614 txp_command(sc, TXP_CMD_TX_DISABLE, 0, 0, 0, NULL, NULL, NULL, 1); 1615 txp_command(sc, TXP_CMD_RX_DISABLE, 0, 0, 0, NULL, NULL, NULL, 1); 1616 } 1617 1618 void 1619 txp_watchdog(struct ifnet *ifp) 1620 { 1621 } 1622 1623 int 1624 txp_ifmedia_upd(struct ifnet *ifp) 1625 { 1626 struct txp_softc *sc = ifp->if_softc; 1627 struct ifmedia *ifm = &sc->sc_ifmedia; 1628 u_int16_t new_xcvr; 1629 1630 if (IFM_TYPE(ifm->ifm_media) != IFM_ETHER) 1631 return (EINVAL); 1632 1633 if (IFM_SUBTYPE(ifm->ifm_media) == IFM_10_T) { 1634 if ((ifm->ifm_media & IFM_GMASK) == IFM_FDX) 1635 new_xcvr = TXP_XCVR_10_FDX; 1636 else 1637 new_xcvr = TXP_XCVR_10_HDX; 1638 } else if (IFM_SUBTYPE(ifm->ifm_media) == IFM_100_TX) { 1639 if ((ifm->ifm_media & IFM_GMASK) == IFM_FDX) 1640 new_xcvr = TXP_XCVR_100_FDX; 1641 else 1642 new_xcvr = TXP_XCVR_100_HDX; 1643 } else if (IFM_SUBTYPE(ifm->ifm_media) == IFM_AUTO) { 1644 new_xcvr = TXP_XCVR_AUTO; 1645 } else 1646 return (EINVAL); 1647 1648 /* nothing to do */ 1649 if (sc->sc_xcvr == new_xcvr) 1650 return (0); 1651 1652 txp_command(sc, TXP_CMD_XCVR_SELECT, new_xcvr, 0, 0, 1653 NULL, NULL, NULL, 0); 1654 sc->sc_xcvr = new_xcvr; 1655 1656 return (0); 1657 } 1658 1659 void 1660 txp_ifmedia_sts(struct ifnet *ifp, struct ifmediareq *ifmr) 1661 { 1662 struct txp_softc *sc = ifp->if_softc; 1663 struct ifmedia *ifm = &sc->sc_ifmedia; 1664 u_int16_t bmsr, bmcr, anar, anlpar; 1665 1666 ifmr->ifm_status = IFM_AVALID; 1667 ifmr->ifm_active = IFM_ETHER; 1668 1669 if (txp_command(sc, TXP_CMD_PHY_MGMT_READ, 0, MII_BMSR, 0, 1670 &bmsr, NULL, NULL, 1)) 1671 goto bail; 1672 if (txp_command(sc, TXP_CMD_PHY_MGMT_READ, 0, MII_BMSR, 0, 1673 &bmsr, NULL, NULL, 1)) 1674 goto bail; 1675 1676 if (txp_command(sc, TXP_CMD_PHY_MGMT_READ, 0, MII_BMCR, 0, 1677 &bmcr, NULL, NULL, 1)) 1678 goto bail; 1679 1680 if (txp_command(sc, TXP_CMD_PHY_MGMT_READ, 0, MII_ANAR, 0, 1681 &anar, NULL, NULL, 1)) 1682 goto bail; 1683 1684 if (txp_command(sc, TXP_CMD_PHY_MGMT_READ, 0, MII_ANLPAR, 0, 1685 &anlpar, NULL, NULL, 1)) 1686 goto bail; 1687 1688 if (bmsr & BMSR_LINK) 1689 ifmr->ifm_status |= IFM_ACTIVE; 1690 1691 if (bmcr & BMCR_ISO) { 1692 ifmr->ifm_active |= IFM_NONE; 1693 ifmr->ifm_status = 0; 1694 return; 1695 } 1696 1697 if (bmcr & BMCR_LOOP) 1698 ifmr->ifm_active |= IFM_LOOP; 1699 1700 if (bmcr & BMCR_AUTOEN) { 1701 if ((bmsr & BMSR_ACOMP) == 0) { 1702 ifmr->ifm_active |= IFM_NONE; 1703 return; 1704 } 1705 1706 anlpar &= anar; 1707 if (anlpar & ANLPAR_TX_FD) 1708 ifmr->ifm_active |= IFM_100_TX|IFM_FDX; 1709 else if (anlpar & ANLPAR_T4) 1710 ifmr->ifm_active |= IFM_100_T4|IFM_HDX; 1711 else if (anlpar & ANLPAR_TX) 1712 ifmr->ifm_active |= IFM_100_TX|IFM_HDX; 1713 else if (anlpar & ANLPAR_10_FD) 1714 ifmr->ifm_active |= IFM_10_T|IFM_FDX; 1715 else if (anlpar & ANLPAR_10) 1716 ifmr->ifm_active |= IFM_10_T|IFM_HDX; 1717 else 1718 ifmr->ifm_active |= IFM_NONE; 1719 } else 1720 ifmr->ifm_active = ifm->ifm_cur->ifm_media; 1721 return; 1722 1723 bail: 1724 ifmr->ifm_active |= IFM_NONE; 1725 ifmr->ifm_status &= ~IFM_AVALID; 1726 } 1727 1728 void 1729 txp_show_descriptor(void *d) 1730 { 1731 struct txp_cmd_desc *cmd = d; 1732 struct txp_rsp_desc *rsp = d; 1733 struct txp_tx_desc *txd = d; 1734 struct txp_frag_desc *frgd = d; 1735 1736 switch (cmd->cmd_flags & CMD_FLAGS_TYPE_M) { 1737 case CMD_FLAGS_TYPE_CMD: 1738 /* command descriptor */ 1739 printf("[cmd flags 0x%x num %d id %d seq %d par1 0x%x par2 0x%x par3 0x%x]\n", 1740 cmd->cmd_flags, cmd->cmd_numdesc, letoh16(cmd->cmd_id), 1741 letoh16(cmd->cmd_seq), letoh16(cmd->cmd_par1), 1742 letoh32(cmd->cmd_par2), letoh32(cmd->cmd_par3)); 1743 break; 1744 case CMD_FLAGS_TYPE_RESP: 1745 /* response descriptor */ 1746 printf("[rsp flags 0x%x num %d id %d seq %d par1 0x%x par2 0x%x par3 0x%x]\n", 1747 rsp->rsp_flags, rsp->rsp_numdesc, letoh16(rsp->rsp_id), 1748 letoh16(rsp->rsp_seq), letoh16(rsp->rsp_par1), 1749 letoh32(rsp->rsp_par2), letoh32(rsp->rsp_par3)); 1750 break; 1751 case CMD_FLAGS_TYPE_DATA: 1752 /* data header (assuming tx for now) */ 1753 printf("[data flags 0x%x num %d totlen %d addr 0x%x/0x%x pflags 0x%x]", 1754 txd->tx_flags, txd->tx_numdesc, txd->tx_totlen, 1755 txd->tx_addrlo, txd->tx_addrhi, txd->tx_pflags); 1756 break; 1757 case CMD_FLAGS_TYPE_FRAG: 1758 /* fragment descriptor */ 1759 printf("[frag flags 0x%x rsvd1 0x%x len %d addr 0x%x/0x%x rsvd2 0x%x]", 1760 frgd->frag_flags, frgd->frag_rsvd1, frgd->frag_len, 1761 frgd->frag_addrlo, frgd->frag_addrhi, frgd->frag_rsvd2); 1762 break; 1763 default: 1764 printf("[unknown(%x) flags 0x%x num %d id %d seq %d par1 0x%x par2 0x%x par3 0x%x]\n", 1765 cmd->cmd_flags & CMD_FLAGS_TYPE_M, 1766 cmd->cmd_flags, cmd->cmd_numdesc, letoh16(cmd->cmd_id), 1767 letoh16(cmd->cmd_seq), letoh16(cmd->cmd_par1), 1768 letoh32(cmd->cmd_par2), letoh32(cmd->cmd_par3)); 1769 break; 1770 } 1771 } 1772 1773 void 1774 txp_set_filter(struct txp_softc *sc) 1775 { 1776 struct arpcom *ac = &sc->sc_arpcom; 1777 struct ifnet *ifp = &sc->sc_arpcom.ac_if; 1778 u_int32_t hashbit, hash[2]; 1779 u_int16_t filter; 1780 int mcnt = 0; 1781 struct ether_multi *enm; 1782 struct ether_multistep step; 1783 1784 if (ifp->if_flags & IFF_PROMISC) { 1785 filter = TXP_RXFILT_PROMISC; 1786 goto setit; 1787 } 1788 1789 if (ac->ac_multirangecnt > 0) 1790 ifp->if_flags |= IFF_ALLMULTI; 1791 1792 filter = TXP_RXFILT_DIRECT; 1793 1794 if (ifp->if_flags & IFF_BROADCAST) 1795 filter |= TXP_RXFILT_BROADCAST; 1796 1797 if (ifp->if_flags & IFF_ALLMULTI) 1798 filter |= TXP_RXFILT_ALLMULTI; 1799 else { 1800 hash[0] = hash[1] = 0; 1801 1802 ETHER_FIRST_MULTI(step, ac, enm); 1803 while (enm != NULL) { 1804 mcnt++; 1805 hashbit = (u_int16_t)(ether_crc32_be(enm->enm_addrlo, 1806 ETHER_ADDR_LEN) & (64 - 1)); 1807 hash[hashbit / 32] |= (1 << hashbit % 32); 1808 ETHER_NEXT_MULTI(step, enm); 1809 } 1810 1811 if (mcnt > 0) { 1812 filter |= TXP_RXFILT_HASHMULTI; 1813 txp_command(sc, TXP_CMD_MCAST_HASH_MASK_WRITE, 1814 2, hash[0], hash[1], NULL, NULL, NULL, 0); 1815 } 1816 } 1817 1818 setit: 1819 txp_command(sc, TXP_CMD_RX_FILTER_WRITE, filter, 0, 0, 1820 NULL, NULL, NULL, 1); 1821 } 1822 1823 void 1824 txp_capabilities(struct txp_softc *sc) 1825 { 1826 struct ifnet *ifp = &sc->sc_arpcom.ac_if; 1827 struct txp_rsp_desc *rsp = NULL; 1828 struct txp_ext_desc *ext; 1829 1830 if (txp_command2(sc, TXP_CMD_OFFLOAD_READ, 0, 0, 0, NULL, 0, &rsp, 1)) 1831 goto out; 1832 1833 if (rsp->rsp_numdesc != 1) 1834 goto out; 1835 ext = (struct txp_ext_desc *)(rsp + 1); 1836 1837 sc->sc_tx_capability = ext->ext_1 & OFFLOAD_MASK; 1838 sc->sc_rx_capability = ext->ext_2 & OFFLOAD_MASK; 1839 1840 ifp->if_capabilities = IFCAP_VLAN_MTU; 1841 1842 #if NVLAN > 0 1843 if (rsp->rsp_par2 & rsp->rsp_par3 & OFFLOAD_VLAN) { 1844 sc->sc_tx_capability |= OFFLOAD_VLAN; 1845 sc->sc_rx_capability |= OFFLOAD_VLAN; 1846 ifp->if_capabilities |= IFCAP_VLAN_HWTAGGING; 1847 } 1848 #endif 1849 1850 #if 0 1851 /* not ready yet */ 1852 if (rsp->rsp_par2 & rsp->rsp_par3 & OFFLOAD_IPSEC) { 1853 sc->sc_tx_capability |= OFFLOAD_IPSEC; 1854 sc->sc_rx_capability |= OFFLOAD_IPSEC; 1855 ifp->if_capabilities |= IFCAP_IPSEC; 1856 } 1857 #endif 1858 1859 if (rsp->rsp_par2 & rsp->rsp_par3 & OFFLOAD_IPCKSUM) { 1860 sc->sc_tx_capability |= OFFLOAD_IPCKSUM; 1861 sc->sc_rx_capability |= OFFLOAD_IPCKSUM; 1862 ifp->if_capabilities |= IFCAP_CSUM_IPv4; 1863 } 1864 1865 if (rsp->rsp_par2 & rsp->rsp_par3 & OFFLOAD_TCPCKSUM) { 1866 sc->sc_rx_capability |= OFFLOAD_TCPCKSUM; 1867 #ifdef TRY_TX_TCP_CSUM 1868 sc->sc_tx_capability |= OFFLOAD_TCPCKSUM; 1869 ifp->if_capabilities |= IFCAP_CSUM_TCPv4; 1870 #endif 1871 } 1872 1873 if (rsp->rsp_par2 & rsp->rsp_par3 & OFFLOAD_UDPCKSUM) { 1874 sc->sc_rx_capability |= OFFLOAD_UDPCKSUM; 1875 #ifdef TRY_TX_UDP_CSUM 1876 sc->sc_tx_capability |= OFFLOAD_UDPCKSUM; 1877 ifp->if_capabilities |= IFCAP_CSUM_UDPv4; 1878 #endif 1879 } 1880 1881 if (txp_command(sc, TXP_CMD_OFFLOAD_WRITE, 0, 1882 sc->sc_tx_capability, sc->sc_rx_capability, NULL, NULL, NULL, 1)) 1883 goto out; 1884 1885 out: 1886 if (rsp != NULL) 1887 free(rsp, M_DEVBUF, 0); 1888 } 1889