1 /* $OpenBSD: if_txp.c,v 1.110 2014/07/13 23:10:23 deraadt Exp $ */ 2 3 /* 4 * Copyright (c) 2001 5 * Jason L. Wright <jason@thought.net>, Theo de Raadt, and 6 * Aaron Campbell <aaron@monkey.org>. All rights reserved. 7 * 8 * Redistribution and use in source and binary forms, with or without 9 * modification, are permitted provided that the following conditions 10 * are met: 11 * 1. Redistributions of source code must retain the above copyright 12 * notice, this list of conditions and the following disclaimer. 13 * 2. Redistributions in binary form must reproduce the above copyright 14 * notice, this list of conditions and the following disclaimer in the 15 * documentation and/or other materials provided with the distribution. 16 * 17 * THIS SOFTWARE IS PROVIDED BY THE AUTHORS ``AS IS'' AND ANY EXPRESS OR 18 * IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED 19 * WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE 20 * ARE DISCLAIMED. IN NO EVENT SHALL THE AUTHORS OR THE VOICES IN THEIR HEADS 21 * BE LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR 22 * CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF 23 * SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS 24 * INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN 25 * CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) 26 * ARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF 27 * THE POSSIBILITY OF SUCH DAMAGE. 28 */ 29 30 /* 31 * Driver for 3c990 (Typhoon) Ethernet ASIC 32 */ 33 34 #include "bpfilter.h" 35 #include "vlan.h" 36 37 #include <sys/param.h> 38 #include <sys/systm.h> 39 #include <sys/sockio.h> 40 #include <sys/mbuf.h> 41 #include <sys/malloc.h> 42 #include <sys/kernel.h> 43 #include <sys/socket.h> 44 #include <sys/device.h> 45 #include <sys/timeout.h> 46 47 #include <net/if.h> 48 #include <net/if_dl.h> 49 #include <net/if_types.h> 50 51 #ifdef INET 52 #include <netinet/in.h> 53 #include <netinet/in_systm.h> 54 #include <netinet/ip.h> 55 #include <netinet/if_ether.h> 56 #endif 57 58 #include <net/if_media.h> 59 60 #if NBPFILTER > 0 61 #include <net/bpf.h> 62 #endif 63 64 #if NVLAN > 0 65 #include <net/if_types.h> 66 #include <net/if_vlan_var.h> 67 #endif 68 69 #include <machine/bus.h> 70 71 #include <dev/mii/mii.h> 72 #include <dev/mii/miivar.h> 73 #include <dev/pci/pcireg.h> 74 #include <dev/pci/pcivar.h> 75 #include <dev/pci/pcidevs.h> 76 77 #include <dev/pci/if_txpreg.h> 78 79 /* 80 * These currently break the 3c990 firmware, hopefully will be resolved 81 * at some point. 82 */ 83 #undef TRY_TX_UDP_CSUM 84 #undef TRY_TX_TCP_CSUM 85 86 int txp_probe(struct device *, void *, void *); 87 void txp_attach(struct device *, struct device *, void *); 88 void txp_attachhook(void *vsc); 89 int txp_intr(void *); 90 void txp_tick(void *); 91 int txp_ioctl(struct ifnet *, u_long, caddr_t); 92 void txp_start(struct ifnet *); 93 void txp_stop(struct txp_softc *); 94 void txp_init(struct txp_softc *); 95 void txp_watchdog(struct ifnet *); 96 97 int txp_chip_init(struct txp_softc *); 98 int txp_reset_adapter(struct txp_softc *); 99 int txp_download_fw(struct txp_softc *); 100 int txp_download_fw_wait(struct txp_softc *); 101 int txp_download_fw_section(struct txp_softc *, 102 struct txp_fw_section_header *, int, u_char *, size_t); 103 int txp_alloc_rings(struct txp_softc *); 104 void txp_dma_free(struct txp_softc *, struct txp_dma_alloc *); 105 int txp_dma_malloc(struct txp_softc *, bus_size_t, struct txp_dma_alloc *, int); 106 void txp_set_filter(struct txp_softc *); 107 108 int txp_cmd_desc_numfree(struct txp_softc *); 109 int txp_command(struct txp_softc *, u_int16_t, u_int16_t, u_int32_t, 110 u_int32_t, u_int16_t *, u_int32_t *, u_int32_t *, int); 111 int txp_command2(struct txp_softc *, u_int16_t, u_int16_t, 112 u_int32_t, u_int32_t, struct txp_ext_desc *, u_int8_t, 113 struct txp_rsp_desc **, int); 114 int txp_response(struct txp_softc *, u_int32_t, u_int16_t, u_int16_t, 115 struct txp_rsp_desc **); 116 void txp_rsp_fixup(struct txp_softc *, struct txp_rsp_desc *, 117 struct txp_rsp_desc *); 118 void txp_capabilities(struct txp_softc *); 119 120 void txp_ifmedia_sts(struct ifnet *, struct ifmediareq *); 121 int txp_ifmedia_upd(struct ifnet *); 122 void txp_show_descriptor(void *); 123 void txp_tx_reclaim(struct txp_softc *, struct txp_tx_ring *, 124 struct txp_dma_alloc *); 125 void txp_rxbuf_reclaim(struct txp_softc *); 126 void txp_rx_reclaim(struct txp_softc *, struct txp_rx_ring *, 127 struct txp_dma_alloc *); 128 129 struct cfattach txp_ca = { 130 sizeof(struct txp_softc), txp_probe, txp_attach, 131 }; 132 133 struct cfdriver txp_cd = { 134 NULL, "txp", DV_IFNET 135 }; 136 137 const struct pci_matchid txp_devices[] = { 138 { PCI_VENDOR_3COM, PCI_PRODUCT_3COM_3CR990 }, 139 { PCI_VENDOR_3COM, PCI_PRODUCT_3COM_3CR990TX }, 140 { PCI_VENDOR_3COM, PCI_PRODUCT_3COM_3CR990TX95 }, 141 { PCI_VENDOR_3COM, PCI_PRODUCT_3COM_3CR990TX97 }, 142 { PCI_VENDOR_3COM, PCI_PRODUCT_3COM_3CR990SVR95 }, 143 { PCI_VENDOR_3COM, PCI_PRODUCT_3COM_3CR990SVR97 }, 144 { PCI_VENDOR_3COM, PCI_PRODUCT_3COM_3C990BTXM }, 145 { PCI_VENDOR_3COM, PCI_PRODUCT_3COM_3C990BSVR }, 146 { PCI_VENDOR_3COM, PCI_PRODUCT_3COM_3CR990FX }, 147 }; 148 149 int 150 txp_probe(struct device *parent, void *match, void *aux) 151 { 152 return (pci_matchbyid((struct pci_attach_args *)aux, txp_devices, 153 nitems(txp_devices))); 154 } 155 156 void 157 txp_attachhook(void *vsc) 158 { 159 struct txp_softc *sc = vsc; 160 struct ifnet *ifp = &sc->sc_arpcom.ac_if; 161 u_int16_t p1; 162 u_int32_t p2; 163 int s; 164 165 s = splnet(); 166 printf("%s: ", sc->sc_dev.dv_xname); 167 168 if (txp_chip_init(sc)) { 169 printf("failed chip init\n"); 170 splx(s); 171 return; 172 } 173 174 if (txp_download_fw(sc)) { 175 splx(s); 176 return; 177 } 178 179 if (txp_alloc_rings(sc)) { 180 splx(s); 181 return; 182 } 183 184 if (txp_command(sc, TXP_CMD_MAX_PKT_SIZE_WRITE, TXP_MAX_PKTLEN, 0, 0, 185 NULL, NULL, NULL, 1)) { 186 splx(s); 187 return; 188 } 189 190 if (txp_command(sc, TXP_CMD_STATION_ADDRESS_READ, 0, 0, 0, 191 &p1, &p2, NULL, 1)) { 192 splx(s); 193 return; 194 } 195 196 p1 = htole16(p1); 197 sc->sc_arpcom.ac_enaddr[0] = ((u_int8_t *)&p1)[1]; 198 sc->sc_arpcom.ac_enaddr[1] = ((u_int8_t *)&p1)[0]; 199 p2 = htole32(p2); 200 sc->sc_arpcom.ac_enaddr[2] = ((u_int8_t *)&p2)[3]; 201 sc->sc_arpcom.ac_enaddr[3] = ((u_int8_t *)&p2)[2]; 202 sc->sc_arpcom.ac_enaddr[4] = ((u_int8_t *)&p2)[1]; 203 sc->sc_arpcom.ac_enaddr[5] = ((u_int8_t *)&p2)[0]; 204 205 printf("address %s\n", ether_sprintf(sc->sc_arpcom.ac_enaddr)); 206 sc->sc_cold = 0; 207 208 ifmedia_init(&sc->sc_ifmedia, 0, txp_ifmedia_upd, txp_ifmedia_sts); 209 ifmedia_add(&sc->sc_ifmedia, IFM_ETHER|IFM_10_T, 0, NULL); 210 ifmedia_add(&sc->sc_ifmedia, IFM_ETHER|IFM_10_T|IFM_HDX, 0, NULL); 211 ifmedia_add(&sc->sc_ifmedia, IFM_ETHER|IFM_10_T|IFM_FDX, 0, NULL); 212 ifmedia_add(&sc->sc_ifmedia, IFM_ETHER|IFM_100_TX, 0, NULL); 213 ifmedia_add(&sc->sc_ifmedia, IFM_ETHER|IFM_100_TX|IFM_HDX, 0, NULL); 214 ifmedia_add(&sc->sc_ifmedia, IFM_ETHER|IFM_100_TX|IFM_FDX, 0, NULL); 215 ifmedia_add(&sc->sc_ifmedia, IFM_ETHER|IFM_AUTO, 0, NULL); 216 217 sc->sc_xcvr = TXP_XCVR_AUTO; 218 txp_command(sc, TXP_CMD_XCVR_SELECT, TXP_XCVR_AUTO, 0, 0, 219 NULL, NULL, NULL, 0); 220 ifmedia_set(&sc->sc_ifmedia, IFM_ETHER|IFM_AUTO); 221 222 ifp->if_softc = sc; 223 ifp->if_flags = IFF_BROADCAST | IFF_SIMPLEX | IFF_MULTICAST; 224 ifp->if_ioctl = txp_ioctl; 225 ifp->if_start = txp_start; 226 ifp->if_watchdog = txp_watchdog; 227 ifp->if_baudrate = IF_Mbps(10); 228 IFQ_SET_MAXLEN(&ifp->if_snd, TX_ENTRIES); 229 IFQ_SET_READY(&ifp->if_snd); 230 bcopy(sc->sc_dev.dv_xname, ifp->if_xname, IFNAMSIZ); 231 232 txp_capabilities(sc); 233 234 timeout_set(&sc->sc_tick, txp_tick, sc); 235 236 /* 237 * Attach us everywhere 238 */ 239 if_attach(ifp); 240 ether_ifattach(ifp); 241 242 splx(s); 243 } 244 245 void 246 txp_attach(struct device *parent, struct device *self, void *aux) 247 { 248 struct txp_softc *sc = (struct txp_softc *)self; 249 struct pci_attach_args *pa = aux; 250 pci_chipset_tag_t pc = pa->pa_pc; 251 pci_intr_handle_t ih; 252 const char *intrstr = NULL; 253 bus_size_t iosize; 254 255 sc->sc_cold = 1; 256 257 if (pci_mapreg_map(pa, TXP_PCI_LOMEM, PCI_MAPREG_TYPE_MEM, 0, 258 &sc->sc_bt, &sc->sc_bh, NULL, &iosize, 0)) { 259 printf(": can't map mem space %d\n", 0); 260 return; 261 } 262 263 sc->sc_dmat = pa->pa_dmat; 264 265 /* 266 * Allocate our interrupt. 267 */ 268 if (pci_intr_map(pa, &ih)) { 269 printf(": couldn't map interrupt\n"); 270 return; 271 } 272 273 intrstr = pci_intr_string(pc, ih); 274 sc->sc_ih = pci_intr_establish(pc, ih, IPL_NET, txp_intr, sc, 275 self->dv_xname); 276 if (sc->sc_ih == NULL) { 277 printf(": couldn't establish interrupt"); 278 if (intrstr != NULL) 279 printf(" at %s", intrstr); 280 printf("\n"); 281 return; 282 } 283 printf(": %s\n", intrstr); 284 285 if (rootvp == NULL) 286 mountroothook_establish(txp_attachhook, sc); 287 else 288 txp_attachhook(sc); 289 290 } 291 292 int 293 txp_chip_init(struct txp_softc *sc) 294 { 295 /* disable interrupts */ 296 WRITE_REG(sc, TXP_IER, 0); 297 WRITE_REG(sc, TXP_IMR, 298 TXP_INT_SELF | TXP_INT_PCI_TABORT | TXP_INT_PCI_MABORT | 299 TXP_INT_DMA3 | TXP_INT_DMA2 | TXP_INT_DMA1 | TXP_INT_DMA0 | 300 TXP_INT_LATCH); 301 302 /* ack all interrupts */ 303 WRITE_REG(sc, TXP_ISR, TXP_INT_RESERVED | TXP_INT_LATCH | 304 TXP_INT_A2H_7 | TXP_INT_A2H_6 | TXP_INT_A2H_5 | TXP_INT_A2H_4 | 305 TXP_INT_SELF | TXP_INT_PCI_TABORT | TXP_INT_PCI_MABORT | 306 TXP_INT_DMA3 | TXP_INT_DMA2 | TXP_INT_DMA1 | TXP_INT_DMA0 | 307 TXP_INT_A2H_3 | TXP_INT_A2H_2 | TXP_INT_A2H_1 | TXP_INT_A2H_0); 308 309 if (txp_reset_adapter(sc)) 310 return (-1); 311 312 /* disable interrupts */ 313 WRITE_REG(sc, TXP_IER, 0); 314 WRITE_REG(sc, TXP_IMR, 315 TXP_INT_SELF | TXP_INT_PCI_TABORT | TXP_INT_PCI_MABORT | 316 TXP_INT_DMA3 | TXP_INT_DMA2 | TXP_INT_DMA1 | TXP_INT_DMA0 | 317 TXP_INT_LATCH); 318 319 /* ack all interrupts */ 320 WRITE_REG(sc, TXP_ISR, TXP_INT_RESERVED | TXP_INT_LATCH | 321 TXP_INT_A2H_7 | TXP_INT_A2H_6 | TXP_INT_A2H_5 | TXP_INT_A2H_4 | 322 TXP_INT_SELF | TXP_INT_PCI_TABORT | TXP_INT_PCI_MABORT | 323 TXP_INT_DMA3 | TXP_INT_DMA2 | TXP_INT_DMA1 | TXP_INT_DMA0 | 324 TXP_INT_A2H_3 | TXP_INT_A2H_2 | TXP_INT_A2H_1 | TXP_INT_A2H_0); 325 326 return (0); 327 } 328 329 int 330 txp_reset_adapter(struct txp_softc *sc) 331 { 332 u_int32_t r; 333 int i; 334 335 WRITE_REG(sc, TXP_SRR, TXP_SRR_ALL); 336 DELAY(1000); 337 WRITE_REG(sc, TXP_SRR, 0); 338 339 /* Should wait max 6 seconds */ 340 for (i = 0; i < 6000; i++) { 341 r = READ_REG(sc, TXP_A2H_0); 342 if (r == STAT_WAITING_FOR_HOST_REQUEST) 343 break; 344 DELAY(1000); 345 } 346 347 if (r != STAT_WAITING_FOR_HOST_REQUEST) { 348 printf("%s: reset hung\n", TXP_DEVNAME(sc)); 349 return (-1); 350 } 351 352 return (0); 353 } 354 355 int 356 txp_download_fw(struct txp_softc *sc) 357 { 358 struct txp_fw_file_header *fileheader; 359 struct txp_fw_section_header *secthead; 360 u_int32_t r, i, ier, imr; 361 size_t buflen; 362 int sect, err; 363 u_char *buf; 364 365 ier = READ_REG(sc, TXP_IER); 366 WRITE_REG(sc, TXP_IER, ier | TXP_INT_A2H_0); 367 368 imr = READ_REG(sc, TXP_IMR); 369 WRITE_REG(sc, TXP_IMR, imr | TXP_INT_A2H_0); 370 371 for (i = 0; i < 10000; i++) { 372 r = READ_REG(sc, TXP_A2H_0); 373 if (r == STAT_WAITING_FOR_HOST_REQUEST) 374 break; 375 DELAY(50); 376 } 377 if (r != STAT_WAITING_FOR_HOST_REQUEST) { 378 printf("not waiting for host request\n"); 379 return (-1); 380 } 381 382 /* Ack the status */ 383 WRITE_REG(sc, TXP_ISR, TXP_INT_A2H_0); 384 385 err = loadfirmware("3c990", &buf, &buflen); 386 if (err) { 387 printf("failed loadfirmware of file 3c990: errno %d\n", 388 err); 389 return (err); 390 } 391 392 fileheader = (struct txp_fw_file_header *)buf; 393 if (bcmp("TYPHOON", fileheader->magicid, sizeof(fileheader->magicid))) { 394 printf("firmware invalid magic\n"); 395 goto fail; 396 } 397 398 /* Tell boot firmware to get ready for image */ 399 WRITE_REG(sc, TXP_H2A_1, letoh32(fileheader->addr)); 400 WRITE_REG(sc, TXP_H2A_2, letoh32(fileheader->hmac[0])); 401 WRITE_REG(sc, TXP_H2A_3, letoh32(fileheader->hmac[1])); 402 WRITE_REG(sc, TXP_H2A_4, letoh32(fileheader->hmac[2])); 403 WRITE_REG(sc, TXP_H2A_5, letoh32(fileheader->hmac[3])); 404 WRITE_REG(sc, TXP_H2A_6, letoh32(fileheader->hmac[4])); 405 WRITE_REG(sc, TXP_H2A_0, TXP_BOOTCMD_RUNTIME_IMAGE); 406 407 if (txp_download_fw_wait(sc)) { 408 printf("fw wait failed, initial\n"); 409 goto fail; 410 } 411 412 secthead = (struct txp_fw_section_header *)(buf + 413 sizeof(struct txp_fw_file_header)); 414 415 for (sect = 0; sect < letoh32(fileheader->nsections); sect++) { 416 if (txp_download_fw_section(sc, secthead, sect, buf, buflen)) 417 goto fail; 418 secthead = (struct txp_fw_section_header *) 419 (((u_int8_t *)secthead) + letoh32(secthead->nbytes) + 420 sizeof(*secthead)); 421 } 422 423 WRITE_REG(sc, TXP_H2A_0, TXP_BOOTCMD_DOWNLOAD_COMPLETE); 424 425 for (i = 0; i < 10000; i++) { 426 r = READ_REG(sc, TXP_A2H_0); 427 if (r == STAT_WAITING_FOR_BOOT) 428 break; 429 DELAY(50); 430 } 431 if (r != STAT_WAITING_FOR_BOOT) { 432 printf("not waiting for boot\n"); 433 goto fail; 434 } 435 436 WRITE_REG(sc, TXP_IER, ier); 437 WRITE_REG(sc, TXP_IMR, imr); 438 439 free(buf, M_DEVBUF, 0); 440 return (0); 441 fail: 442 free(buf, M_DEVBUF, 0); 443 return (-1); 444 } 445 446 int 447 txp_download_fw_wait(struct txp_softc *sc) 448 { 449 u_int32_t i, r; 450 451 for (i = 0; i < 10000; i++) { 452 r = READ_REG(sc, TXP_ISR); 453 if (r & TXP_INT_A2H_0) 454 break; 455 DELAY(50); 456 } 457 458 if (!(r & TXP_INT_A2H_0)) { 459 printf("fw wait failed comm0\n"); 460 return (-1); 461 } 462 463 WRITE_REG(sc, TXP_ISR, TXP_INT_A2H_0); 464 465 r = READ_REG(sc, TXP_A2H_0); 466 if (r != STAT_WAITING_FOR_SEGMENT) { 467 printf("fw not waiting for segment\n"); 468 return (-1); 469 } 470 return (0); 471 } 472 473 int 474 txp_download_fw_section(struct txp_softc *sc, 475 struct txp_fw_section_header *sect, int sectnum, u_char *buf, 476 size_t buflen) 477 { 478 struct txp_dma_alloc dma; 479 int rseg, err = 0; 480 struct mbuf m; 481 u_int16_t csum; 482 483 /* Skip zero length sections */ 484 if (sect->nbytes == 0) 485 return (0); 486 487 /* Make sure we aren't past the end of the image */ 488 rseg = ((u_int8_t *)sect) - ((u_int8_t *)buf); 489 if (rseg >= buflen) { 490 printf("fw invalid section address, section %d\n", sectnum); 491 return (-1); 492 } 493 494 /* Make sure this section doesn't go past the end */ 495 rseg += letoh32(sect->nbytes); 496 if (rseg >= buflen) { 497 printf("fw truncated section %d\n", sectnum); 498 return (-1); 499 } 500 501 /* map a buffer, copy segment to it, get physaddr */ 502 if (txp_dma_malloc(sc, letoh32(sect->nbytes), &dma, 0)) { 503 printf("fw dma malloc failed, section %d\n", sectnum); 504 return (-1); 505 } 506 507 bcopy(((u_int8_t *)sect) + sizeof(*sect), dma.dma_vaddr, 508 letoh32(sect->nbytes)); 509 510 /* 511 * dummy up mbuf and verify section checksum 512 */ 513 m.m_type = MT_DATA; 514 m.m_next = m.m_nextpkt = NULL; 515 m.m_len = letoh32(sect->nbytes); 516 m.m_data = dma.dma_vaddr; 517 m.m_flags = 0; 518 csum = in_cksum(&m, letoh32(sect->nbytes)); 519 if (csum != sect->cksum) { 520 printf("fw section %d, bad cksum (expected 0x%x got 0x%x)\n", 521 sectnum, sect->cksum, csum); 522 err = -1; 523 goto bail; 524 } 525 526 bus_dmamap_sync(sc->sc_dmat, dma.dma_map, 0, 527 dma.dma_map->dm_mapsize, BUS_DMASYNC_PREWRITE); 528 529 WRITE_REG(sc, TXP_H2A_1, letoh32(sect->nbytes)); 530 WRITE_REG(sc, TXP_H2A_2, letoh16(sect->cksum)); 531 WRITE_REG(sc, TXP_H2A_3, letoh32(sect->addr)); 532 WRITE_REG(sc, TXP_H2A_4, dma.dma_paddr >> 32); 533 WRITE_REG(sc, TXP_H2A_5, dma.dma_paddr & 0xffffffff); 534 WRITE_REG(sc, TXP_H2A_0, TXP_BOOTCMD_SEGMENT_AVAILABLE); 535 536 if (txp_download_fw_wait(sc)) { 537 printf("%s: fw wait failed, section %d\n", 538 sc->sc_dev.dv_xname, sectnum); 539 err = -1; 540 } 541 542 bus_dmamap_sync(sc->sc_dmat, dma.dma_map, 0, 543 dma.dma_map->dm_mapsize, BUS_DMASYNC_POSTWRITE); 544 545 bail: 546 txp_dma_free(sc, &dma); 547 548 return (err); 549 } 550 551 int 552 txp_intr(void *vsc) 553 { 554 struct txp_softc *sc = vsc; 555 struct txp_hostvar *hv = sc->sc_hostvar; 556 u_int32_t isr; 557 int claimed = 0; 558 559 /* mask all interrupts */ 560 WRITE_REG(sc, TXP_IMR, TXP_INT_RESERVED | TXP_INT_SELF | 561 TXP_INT_A2H_7 | TXP_INT_A2H_6 | TXP_INT_A2H_5 | TXP_INT_A2H_4 | 562 TXP_INT_A2H_2 | TXP_INT_A2H_1 | TXP_INT_A2H_0 | 563 TXP_INT_DMA3 | TXP_INT_DMA2 | TXP_INT_DMA1 | TXP_INT_DMA0 | 564 TXP_INT_PCI_TABORT | TXP_INT_PCI_MABORT | TXP_INT_LATCH); 565 566 bus_dmamap_sync(sc->sc_dmat, sc->sc_host_dma.dma_map, 0, 567 sizeof(struct txp_hostvar), BUS_DMASYNC_POSTWRITE|BUS_DMASYNC_POSTREAD); 568 569 isr = READ_REG(sc, TXP_ISR); 570 while (isr) { 571 claimed = 1; 572 WRITE_REG(sc, TXP_ISR, isr); 573 574 if ((*sc->sc_rxhir.r_roff) != (*sc->sc_rxhir.r_woff)) 575 txp_rx_reclaim(sc, &sc->sc_rxhir, &sc->sc_rxhiring_dma); 576 if ((*sc->sc_rxlor.r_roff) != (*sc->sc_rxlor.r_woff)) 577 txp_rx_reclaim(sc, &sc->sc_rxlor, &sc->sc_rxloring_dma); 578 579 if (hv->hv_rx_buf_write_idx == hv->hv_rx_buf_read_idx) 580 txp_rxbuf_reclaim(sc); 581 582 if (sc->sc_txhir.r_cnt && (sc->sc_txhir.r_cons != 583 TXP_OFFSET2IDX(letoh32(*(sc->sc_txhir.r_off))))) 584 txp_tx_reclaim(sc, &sc->sc_txhir, &sc->sc_txhiring_dma); 585 586 if (sc->sc_txlor.r_cnt && (sc->sc_txlor.r_cons != 587 TXP_OFFSET2IDX(letoh32(*(sc->sc_txlor.r_off))))) 588 txp_tx_reclaim(sc, &sc->sc_txlor, &sc->sc_txloring_dma); 589 590 isr = READ_REG(sc, TXP_ISR); 591 } 592 593 bus_dmamap_sync(sc->sc_dmat, sc->sc_host_dma.dma_map, 0, 594 sizeof(struct txp_hostvar), BUS_DMASYNC_POSTWRITE|BUS_DMASYNC_POSTREAD); 595 596 /* unmask all interrupts */ 597 WRITE_REG(sc, TXP_IMR, TXP_INT_A2H_3); 598 599 txp_start(&sc->sc_arpcom.ac_if); 600 601 return (claimed); 602 } 603 604 void 605 txp_rx_reclaim(struct txp_softc *sc, struct txp_rx_ring *r, 606 struct txp_dma_alloc *dma) 607 { 608 struct ifnet *ifp = &sc->sc_arpcom.ac_if; 609 struct txp_rx_desc *rxd; 610 struct mbuf *m; 611 struct txp_swdesc *sd; 612 u_int32_t roff, woff; 613 int idx; 614 u_int16_t sumflags = 0; 615 616 roff = letoh32(*r->r_roff); 617 woff = letoh32(*r->r_woff); 618 idx = roff / sizeof(struct txp_rx_desc); 619 rxd = r->r_desc + idx; 620 621 while (roff != woff) { 622 623 bus_dmamap_sync(sc->sc_dmat, dma->dma_map, 624 idx * sizeof(struct txp_rx_desc), sizeof(struct txp_rx_desc), 625 BUS_DMASYNC_POSTREAD); 626 627 if (rxd->rx_flags & RX_FLAGS_ERROR) { 628 printf("%s: error 0x%x\n", sc->sc_dev.dv_xname, 629 letoh32(rxd->rx_stat)); 630 ifp->if_ierrors++; 631 goto next; 632 } 633 634 /* retrieve stashed pointer */ 635 bcopy((u_long *)&rxd->rx_vaddrlo, &sd, sizeof(sd)); 636 637 bus_dmamap_sync(sc->sc_dmat, sd->sd_map, 0, 638 sd->sd_map->dm_mapsize, BUS_DMASYNC_POSTREAD); 639 bus_dmamap_unload(sc->sc_dmat, sd->sd_map); 640 bus_dmamap_destroy(sc->sc_dmat, sd->sd_map); 641 m = sd->sd_mbuf; 642 free(sd, M_DEVBUF, 0); 643 m->m_pkthdr.len = m->m_len = letoh16(rxd->rx_len); 644 645 #ifdef __STRICT_ALIGNMENT 646 { 647 /* 648 * XXX Nice chip, except it won't accept "off by 2" 649 * buffers, so we're force to copy. Supposedly 650 * this will be fixed in a newer firmware rev 651 * and this will be temporary. 652 */ 653 struct mbuf *mnew; 654 655 MGETHDR(mnew, M_DONTWAIT, MT_DATA); 656 if (mnew == NULL) { 657 m_freem(m); 658 goto next; 659 } 660 if (m->m_len > (MHLEN - 2)) { 661 MCLGET(mnew, M_DONTWAIT); 662 if (!(mnew->m_flags & M_EXT)) { 663 m_freem(mnew); 664 m_freem(m); 665 goto next; 666 } 667 } 668 mnew->m_pkthdr.rcvif = ifp; 669 mnew->m_pkthdr.len = mnew->m_len = m->m_len; 670 mnew->m_data += 2; 671 bcopy(m->m_data, mnew->m_data, m->m_len); 672 m_freem(m); 673 m = mnew; 674 } 675 #endif 676 677 #if NVLAN > 0 678 /* 679 * XXX Another firmware bug: the vlan encapsulation 680 * is always removed, even when we tell the card not 681 * to do that. Restore the vlan encapsulation below. 682 */ 683 if (rxd->rx_stat & htole32(RX_STAT_VLAN)) { 684 m->m_pkthdr.ether_vtag = ntohs(rxd->rx_vlan >> 16); 685 m->m_flags |= M_VLANTAG; 686 } 687 #endif 688 689 #if NBPFILTER > 0 690 /* 691 * Handle BPF listeners. Let the BPF user see the packet. 692 */ 693 if (ifp->if_bpf) 694 bpf_mtap_ether(ifp->if_bpf, m, BPF_DIRECTION_IN); 695 #endif 696 697 if (rxd->rx_stat & htole32(RX_STAT_IPCKSUMBAD)) 698 sumflags |= M_IPV4_CSUM_IN_BAD; 699 else if (rxd->rx_stat & htole32(RX_STAT_IPCKSUMGOOD)) 700 sumflags |= M_IPV4_CSUM_IN_OK; 701 702 if (rxd->rx_stat & htole32(RX_STAT_TCPCKSUMBAD)) 703 sumflags |= M_TCP_CSUM_IN_BAD; 704 else if (rxd->rx_stat & htole32(RX_STAT_TCPCKSUMGOOD)) 705 sumflags |= M_TCP_CSUM_IN_OK; 706 707 if (rxd->rx_stat & htole32(RX_STAT_UDPCKSUMBAD)) 708 sumflags |= M_UDP_CSUM_IN_BAD; 709 else if (rxd->rx_stat & htole32(RX_STAT_UDPCKSUMGOOD)) 710 sumflags |= M_UDP_CSUM_IN_OK; 711 712 m->m_pkthdr.csum_flags = sumflags; 713 714 ether_input_mbuf(ifp, m); 715 716 next: 717 bus_dmamap_sync(sc->sc_dmat, dma->dma_map, 718 idx * sizeof(struct txp_rx_desc), sizeof(struct txp_rx_desc), 719 BUS_DMASYNC_PREREAD); 720 721 roff += sizeof(struct txp_rx_desc); 722 if (roff == (RX_ENTRIES * sizeof(struct txp_rx_desc))) { 723 idx = 0; 724 roff = 0; 725 rxd = r->r_desc; 726 } else { 727 idx++; 728 rxd++; 729 } 730 woff = letoh32(*r->r_woff); 731 } 732 733 *r->r_roff = htole32(woff); 734 } 735 736 void 737 txp_rxbuf_reclaim(struct txp_softc *sc) 738 { 739 struct ifnet *ifp = &sc->sc_arpcom.ac_if; 740 struct txp_hostvar *hv = sc->sc_hostvar; 741 struct txp_rxbuf_desc *rbd; 742 struct txp_swdesc *sd; 743 u_int32_t i, end; 744 745 end = TXP_OFFSET2IDX(letoh32(hv->hv_rx_buf_read_idx)); 746 i = TXP_OFFSET2IDX(letoh32(hv->hv_rx_buf_write_idx)); 747 748 if (++i == RXBUF_ENTRIES) 749 i = 0; 750 751 rbd = sc->sc_rxbufs + i; 752 753 while (i != end) { 754 sd = (struct txp_swdesc *)malloc(sizeof(struct txp_swdesc), 755 M_DEVBUF, M_NOWAIT); 756 if (sd == NULL) 757 break; 758 759 MGETHDR(sd->sd_mbuf, M_DONTWAIT, MT_DATA); 760 if (sd->sd_mbuf == NULL) 761 goto err_sd; 762 763 MCLGET(sd->sd_mbuf, M_DONTWAIT); 764 if ((sd->sd_mbuf->m_flags & M_EXT) == 0) 765 goto err_mbuf; 766 sd->sd_mbuf->m_pkthdr.rcvif = ifp; 767 sd->sd_mbuf->m_pkthdr.len = sd->sd_mbuf->m_len = MCLBYTES; 768 if (bus_dmamap_create(sc->sc_dmat, TXP_MAX_PKTLEN, 1, 769 TXP_MAX_PKTLEN, 0, BUS_DMA_NOWAIT, &sd->sd_map)) 770 goto err_mbuf; 771 if (bus_dmamap_load_mbuf(sc->sc_dmat, sd->sd_map, sd->sd_mbuf, 772 BUS_DMA_NOWAIT)) { 773 bus_dmamap_destroy(sc->sc_dmat, sd->sd_map); 774 goto err_mbuf; 775 } 776 777 bus_dmamap_sync(sc->sc_dmat, sc->sc_rxbufring_dma.dma_map, 778 i * sizeof(struct txp_rxbuf_desc), 779 sizeof(struct txp_rxbuf_desc), BUS_DMASYNC_POSTWRITE); 780 781 /* stash away pointer */ 782 bcopy(&sd, (u_long *)&rbd->rb_vaddrlo, sizeof(sd)); 783 784 rbd->rb_paddrlo = ((u_int64_t)sd->sd_map->dm_segs[0].ds_addr) 785 & 0xffffffff; 786 rbd->rb_paddrhi = ((u_int64_t)sd->sd_map->dm_segs[0].ds_addr) 787 >> 32; 788 789 bus_dmamap_sync(sc->sc_dmat, sd->sd_map, 0, 790 sd->sd_map->dm_mapsize, BUS_DMASYNC_PREREAD); 791 792 bus_dmamap_sync(sc->sc_dmat, sc->sc_rxbufring_dma.dma_map, 793 i * sizeof(struct txp_rxbuf_desc), 794 sizeof(struct txp_rxbuf_desc), BUS_DMASYNC_PREWRITE); 795 796 hv->hv_rx_buf_write_idx = htole32(TXP_IDX2OFFSET(i)); 797 798 if (++i == RXBUF_ENTRIES) { 799 i = 0; 800 rbd = sc->sc_rxbufs; 801 } else 802 rbd++; 803 } 804 return; 805 806 err_mbuf: 807 m_freem(sd->sd_mbuf); 808 err_sd: 809 free(sd, M_DEVBUF, 0); 810 } 811 812 /* 813 * Reclaim mbufs and entries from a transmit ring. 814 */ 815 void 816 txp_tx_reclaim(struct txp_softc *sc, struct txp_tx_ring *r, 817 struct txp_dma_alloc *dma) 818 { 819 struct ifnet *ifp = &sc->sc_arpcom.ac_if; 820 u_int32_t idx = TXP_OFFSET2IDX(letoh32(*(r->r_off))); 821 u_int32_t cons = r->r_cons, cnt = r->r_cnt; 822 struct txp_tx_desc *txd = r->r_desc + cons; 823 struct txp_swdesc *sd = sc->sc_txd + cons; 824 struct mbuf *m; 825 826 while (cons != idx) { 827 if (cnt == 0) 828 break; 829 830 bus_dmamap_sync(sc->sc_dmat, dma->dma_map, 831 cons * sizeof(struct txp_tx_desc), 832 sizeof(struct txp_tx_desc), 833 BUS_DMASYNC_POSTWRITE); 834 835 if ((txd->tx_flags & TX_FLAGS_TYPE_M) == 836 TX_FLAGS_TYPE_DATA) { 837 bus_dmamap_sync(sc->sc_dmat, sd->sd_map, 0, 838 sd->sd_map->dm_mapsize, BUS_DMASYNC_POSTWRITE); 839 bus_dmamap_unload(sc->sc_dmat, sd->sd_map); 840 m = sd->sd_mbuf; 841 if (m != NULL) { 842 m_freem(m); 843 txd->tx_addrlo = 0; 844 txd->tx_addrhi = 0; 845 ifp->if_opackets++; 846 } 847 } 848 ifp->if_flags &= ~IFF_OACTIVE; 849 850 if (++cons == TX_ENTRIES) { 851 txd = r->r_desc; 852 cons = 0; 853 sd = sc->sc_txd; 854 } else { 855 txd++; 856 sd++; 857 } 858 859 cnt--; 860 } 861 862 r->r_cons = cons; 863 r->r_cnt = cnt; 864 if (cnt == 0) 865 ifp->if_timer = 0; 866 } 867 868 int 869 txp_alloc_rings(struct txp_softc *sc) 870 { 871 struct ifnet *ifp = &sc->sc_arpcom.ac_if; 872 struct txp_boot_record *boot; 873 struct txp_swdesc *sd; 874 u_int32_t r; 875 int i, j; 876 877 /* boot record */ 878 if (txp_dma_malloc(sc, sizeof(struct txp_boot_record), &sc->sc_boot_dma, 879 BUS_DMA_COHERENT)) { 880 printf("can't allocate boot record\n"); 881 return (-1); 882 } 883 boot = (struct txp_boot_record *)sc->sc_boot_dma.dma_vaddr; 884 bzero(boot, sizeof(*boot)); 885 sc->sc_boot = boot; 886 887 /* host variables */ 888 if (txp_dma_malloc(sc, sizeof(struct txp_hostvar), &sc->sc_host_dma, 889 BUS_DMA_COHERENT)) { 890 printf("can't allocate host ring\n"); 891 goto bail_boot; 892 } 893 bzero(sc->sc_host_dma.dma_vaddr, sizeof(struct txp_hostvar)); 894 boot->br_hostvar_lo = htole32(sc->sc_host_dma.dma_paddr & 0xffffffff); 895 boot->br_hostvar_hi = htole32(sc->sc_host_dma.dma_paddr >> 32); 896 sc->sc_hostvar = (struct txp_hostvar *)sc->sc_host_dma.dma_vaddr; 897 898 /* high priority tx ring */ 899 if (txp_dma_malloc(sc, sizeof(struct txp_tx_desc) * TX_ENTRIES, 900 &sc->sc_txhiring_dma, BUS_DMA_COHERENT)) { 901 printf("can't allocate high tx ring\n"); 902 goto bail_host; 903 } 904 bzero(sc->sc_txhiring_dma.dma_vaddr, sizeof(struct txp_tx_desc) * TX_ENTRIES); 905 boot->br_txhipri_lo = htole32(sc->sc_txhiring_dma.dma_paddr & 0xffffffff); 906 boot->br_txhipri_hi = htole32(sc->sc_txhiring_dma.dma_paddr >> 32); 907 boot->br_txhipri_siz = htole32(TX_ENTRIES * sizeof(struct txp_tx_desc)); 908 sc->sc_txhir.r_reg = TXP_H2A_1; 909 sc->sc_txhir.r_desc = (struct txp_tx_desc *)sc->sc_txhiring_dma.dma_vaddr; 910 sc->sc_txhir.r_cons = sc->sc_txhir.r_prod = sc->sc_txhir.r_cnt = 0; 911 sc->sc_txhir.r_off = &sc->sc_hostvar->hv_tx_hi_desc_read_idx; 912 for (i = 0; i < TX_ENTRIES; i++) { 913 if (bus_dmamap_create(sc->sc_dmat, TXP_MAX_PKTLEN, 914 TX_ENTRIES - 4, TXP_MAX_SEGLEN, 0, 915 BUS_DMA_NOWAIT, &sc->sc_txd[i].sd_map) != 0) { 916 for (j = 0; j < i; j++) { 917 bus_dmamap_destroy(sc->sc_dmat, 918 sc->sc_txd[j].sd_map); 919 sc->sc_txd[j].sd_map = NULL; 920 } 921 goto bail_txhiring; 922 } 923 } 924 925 /* low priority tx ring */ 926 if (txp_dma_malloc(sc, sizeof(struct txp_tx_desc) * TX_ENTRIES, 927 &sc->sc_txloring_dma, BUS_DMA_COHERENT)) { 928 printf("can't allocate low tx ring\n"); 929 goto bail_txhiring; 930 } 931 bzero(sc->sc_txloring_dma.dma_vaddr, sizeof(struct txp_tx_desc) * TX_ENTRIES); 932 boot->br_txlopri_lo = htole32(sc->sc_txloring_dma.dma_paddr & 0xffffffff); 933 boot->br_txlopri_hi = htole32(sc->sc_txloring_dma.dma_paddr >> 32); 934 boot->br_txlopri_siz = htole32(TX_ENTRIES * sizeof(struct txp_tx_desc)); 935 sc->sc_txlor.r_reg = TXP_H2A_3; 936 sc->sc_txlor.r_desc = (struct txp_tx_desc *)sc->sc_txloring_dma.dma_vaddr; 937 sc->sc_txlor.r_cons = sc->sc_txlor.r_prod = sc->sc_txlor.r_cnt = 0; 938 sc->sc_txlor.r_off = &sc->sc_hostvar->hv_tx_lo_desc_read_idx; 939 940 /* high priority rx ring */ 941 if (txp_dma_malloc(sc, sizeof(struct txp_rx_desc) * RX_ENTRIES, 942 &sc->sc_rxhiring_dma, BUS_DMA_COHERENT)) { 943 printf("can't allocate high rx ring\n"); 944 goto bail_txloring; 945 } 946 bzero(sc->sc_rxhiring_dma.dma_vaddr, sizeof(struct txp_rx_desc) * RX_ENTRIES); 947 boot->br_rxhipri_lo = htole32(sc->sc_rxhiring_dma.dma_paddr & 0xffffffff); 948 boot->br_rxhipri_hi = htole32(sc->sc_rxhiring_dma.dma_paddr >> 32); 949 boot->br_rxhipri_siz = htole32(RX_ENTRIES * sizeof(struct txp_rx_desc)); 950 sc->sc_rxhir.r_desc = 951 (struct txp_rx_desc *)sc->sc_rxhiring_dma.dma_vaddr; 952 sc->sc_rxhir.r_roff = &sc->sc_hostvar->hv_rx_hi_read_idx; 953 sc->sc_rxhir.r_woff = &sc->sc_hostvar->hv_rx_hi_write_idx; 954 bus_dmamap_sync(sc->sc_dmat, sc->sc_rxhiring_dma.dma_map, 955 0, sc->sc_rxhiring_dma.dma_map->dm_mapsize, BUS_DMASYNC_PREREAD); 956 957 /* low priority ring */ 958 if (txp_dma_malloc(sc, sizeof(struct txp_rx_desc) * RX_ENTRIES, 959 &sc->sc_rxloring_dma, BUS_DMA_COHERENT)) { 960 printf("can't allocate low rx ring\n"); 961 goto bail_rxhiring; 962 } 963 bzero(sc->sc_rxloring_dma.dma_vaddr, sizeof(struct txp_rx_desc) * RX_ENTRIES); 964 boot->br_rxlopri_lo = htole32(sc->sc_rxloring_dma.dma_paddr & 0xffffffff); 965 boot->br_rxlopri_hi = htole32(sc->sc_rxloring_dma.dma_paddr >> 32); 966 boot->br_rxlopri_siz = htole32(RX_ENTRIES * sizeof(struct txp_rx_desc)); 967 sc->sc_rxlor.r_desc = 968 (struct txp_rx_desc *)sc->sc_rxloring_dma.dma_vaddr; 969 sc->sc_rxlor.r_roff = &sc->sc_hostvar->hv_rx_lo_read_idx; 970 sc->sc_rxlor.r_woff = &sc->sc_hostvar->hv_rx_lo_write_idx; 971 bus_dmamap_sync(sc->sc_dmat, sc->sc_rxloring_dma.dma_map, 972 0, sc->sc_rxloring_dma.dma_map->dm_mapsize, BUS_DMASYNC_PREREAD); 973 974 /* command ring */ 975 if (txp_dma_malloc(sc, sizeof(struct txp_cmd_desc) * CMD_ENTRIES, 976 &sc->sc_cmdring_dma, BUS_DMA_COHERENT)) { 977 printf("can't allocate command ring\n"); 978 goto bail_rxloring; 979 } 980 bzero(sc->sc_cmdring_dma.dma_vaddr, sizeof(struct txp_cmd_desc) * CMD_ENTRIES); 981 boot->br_cmd_lo = htole32(sc->sc_cmdring_dma.dma_paddr & 0xffffffff); 982 boot->br_cmd_hi = htole32(sc->sc_cmdring_dma.dma_paddr >> 32); 983 boot->br_cmd_siz = htole32(CMD_ENTRIES * sizeof(struct txp_cmd_desc)); 984 sc->sc_cmdring.base = (struct txp_cmd_desc *)sc->sc_cmdring_dma.dma_vaddr; 985 sc->sc_cmdring.size = CMD_ENTRIES * sizeof(struct txp_cmd_desc); 986 sc->sc_cmdring.lastwrite = 0; 987 988 /* response ring */ 989 if (txp_dma_malloc(sc, sizeof(struct txp_rsp_desc) * RSP_ENTRIES, 990 &sc->sc_rspring_dma, BUS_DMA_COHERENT)) { 991 printf("can't allocate response ring\n"); 992 goto bail_cmdring; 993 } 994 bzero(sc->sc_rspring_dma.dma_vaddr, sizeof(struct txp_rsp_desc) * RSP_ENTRIES); 995 boot->br_resp_lo = htole32(sc->sc_rspring_dma.dma_paddr & 0xffffffff); 996 boot->br_resp_hi = htole32(sc->sc_rspring_dma.dma_paddr >> 32); 997 boot->br_resp_siz = htole32(CMD_ENTRIES * sizeof(struct txp_rsp_desc)); 998 sc->sc_rspring.base = (struct txp_rsp_desc *)sc->sc_rspring_dma.dma_vaddr; 999 sc->sc_rspring.size = RSP_ENTRIES * sizeof(struct txp_rsp_desc); 1000 sc->sc_rspring.lastwrite = 0; 1001 1002 /* receive buffer ring */ 1003 if (txp_dma_malloc(sc, sizeof(struct txp_rxbuf_desc) * RXBUF_ENTRIES, 1004 &sc->sc_rxbufring_dma, BUS_DMA_COHERENT)) { 1005 printf("can't allocate rx buffer ring\n"); 1006 goto bail_rspring; 1007 } 1008 bzero(sc->sc_rxbufring_dma.dma_vaddr, sizeof(struct txp_rxbuf_desc) * RXBUF_ENTRIES); 1009 boot->br_rxbuf_lo = htole32(sc->sc_rxbufring_dma.dma_paddr & 0xffffffff); 1010 boot->br_rxbuf_hi = htole32(sc->sc_rxbufring_dma.dma_paddr >> 32); 1011 boot->br_rxbuf_siz = htole32(RXBUF_ENTRIES * sizeof(struct txp_rxbuf_desc)); 1012 sc->sc_rxbufs = (struct txp_rxbuf_desc *)sc->sc_rxbufring_dma.dma_vaddr; 1013 for (i = 0; i < RXBUF_ENTRIES; i++) { 1014 sd = (struct txp_swdesc *)malloc(sizeof(struct txp_swdesc), 1015 M_DEVBUF, M_NOWAIT); 1016 1017 /* stash away pointer */ 1018 bcopy(&sd, (u_long *)&sc->sc_rxbufs[i].rb_vaddrlo, sizeof(sd)); 1019 1020 if (sd == NULL) 1021 break; 1022 1023 MGETHDR(sd->sd_mbuf, M_DONTWAIT, MT_DATA); 1024 if (sd->sd_mbuf == NULL) { 1025 goto bail_rxbufring; 1026 } 1027 1028 MCLGET(sd->sd_mbuf, M_DONTWAIT); 1029 if ((sd->sd_mbuf->m_flags & M_EXT) == 0) { 1030 goto bail_rxbufring; 1031 } 1032 sd->sd_mbuf->m_pkthdr.len = sd->sd_mbuf->m_len = MCLBYTES; 1033 sd->sd_mbuf->m_pkthdr.rcvif = ifp; 1034 if (bus_dmamap_create(sc->sc_dmat, TXP_MAX_PKTLEN, 1, 1035 TXP_MAX_PKTLEN, 0, BUS_DMA_NOWAIT, &sd->sd_map)) { 1036 goto bail_rxbufring; 1037 } 1038 if (bus_dmamap_load_mbuf(sc->sc_dmat, sd->sd_map, sd->sd_mbuf, 1039 BUS_DMA_NOWAIT)) { 1040 bus_dmamap_destroy(sc->sc_dmat, sd->sd_map); 1041 goto bail_rxbufring; 1042 } 1043 bus_dmamap_sync(sc->sc_dmat, sd->sd_map, 0, 1044 sd->sd_map->dm_mapsize, BUS_DMASYNC_PREREAD); 1045 1046 sc->sc_rxbufs[i].rb_paddrlo = 1047 ((u_int64_t)sd->sd_map->dm_segs[0].ds_addr) & 0xffffffff; 1048 sc->sc_rxbufs[i].rb_paddrhi = 1049 ((u_int64_t)sd->sd_map->dm_segs[0].ds_addr) >> 32; 1050 } 1051 bus_dmamap_sync(sc->sc_dmat, sc->sc_rxbufring_dma.dma_map, 1052 0, sc->sc_rxbufring_dma.dma_map->dm_mapsize, 1053 BUS_DMASYNC_PREWRITE); 1054 sc->sc_hostvar->hv_rx_buf_write_idx = htole32((RXBUF_ENTRIES - 1) * 1055 sizeof(struct txp_rxbuf_desc)); 1056 1057 /* zero dma */ 1058 if (txp_dma_malloc(sc, sizeof(u_int32_t), &sc->sc_zero_dma, 1059 BUS_DMA_COHERENT)) { 1060 printf("can't allocate response ring\n"); 1061 goto bail_rxbufring; 1062 } 1063 bzero(sc->sc_zero_dma.dma_vaddr, sizeof(u_int32_t)); 1064 boot->br_zero_lo = htole32(sc->sc_zero_dma.dma_paddr & 0xffffffff); 1065 boot->br_zero_hi = htole32(sc->sc_zero_dma.dma_paddr >> 32); 1066 1067 /* See if it's waiting for boot, and try to boot it */ 1068 for (i = 0; i < 10000; i++) { 1069 r = READ_REG(sc, TXP_A2H_0); 1070 if (r == STAT_WAITING_FOR_BOOT) 1071 break; 1072 DELAY(50); 1073 } 1074 if (r != STAT_WAITING_FOR_BOOT) { 1075 printf("not waiting for boot\n"); 1076 goto bail; 1077 } 1078 WRITE_REG(sc, TXP_H2A_2, sc->sc_boot_dma.dma_paddr >> 32); 1079 WRITE_REG(sc, TXP_H2A_1, sc->sc_boot_dma.dma_paddr & 0xffffffff); 1080 WRITE_REG(sc, TXP_H2A_0, TXP_BOOTCMD_REGISTER_BOOT_RECORD); 1081 1082 /* See if it booted */ 1083 for (i = 0; i < 10000; i++) { 1084 r = READ_REG(sc, TXP_A2H_0); 1085 if (r == STAT_RUNNING) 1086 break; 1087 DELAY(50); 1088 } 1089 if (r != STAT_RUNNING) { 1090 printf("fw not running\n"); 1091 goto bail; 1092 } 1093 1094 /* Clear TX and CMD ring write registers */ 1095 WRITE_REG(sc, TXP_H2A_1, TXP_BOOTCMD_NULL); 1096 WRITE_REG(sc, TXP_H2A_2, TXP_BOOTCMD_NULL); 1097 WRITE_REG(sc, TXP_H2A_3, TXP_BOOTCMD_NULL); 1098 WRITE_REG(sc, TXP_H2A_0, TXP_BOOTCMD_NULL); 1099 1100 return (0); 1101 1102 bail: 1103 txp_dma_free(sc, &sc->sc_zero_dma); 1104 bail_rxbufring: 1105 for (i = 0; i < RXBUF_ENTRIES; i++) { 1106 bcopy((u_long *)&sc->sc_rxbufs[i].rb_vaddrlo, &sd, sizeof(sd)); 1107 if (sd) 1108 free(sd, M_DEVBUF, 0); 1109 } 1110 txp_dma_free(sc, &sc->sc_rxbufring_dma); 1111 bail_rspring: 1112 txp_dma_free(sc, &sc->sc_rspring_dma); 1113 bail_cmdring: 1114 txp_dma_free(sc, &sc->sc_cmdring_dma); 1115 bail_rxloring: 1116 txp_dma_free(sc, &sc->sc_rxloring_dma); 1117 bail_rxhiring: 1118 txp_dma_free(sc, &sc->sc_rxhiring_dma); 1119 bail_txloring: 1120 txp_dma_free(sc, &sc->sc_txloring_dma); 1121 bail_txhiring: 1122 txp_dma_free(sc, &sc->sc_txhiring_dma); 1123 bail_host: 1124 txp_dma_free(sc, &sc->sc_host_dma); 1125 bail_boot: 1126 txp_dma_free(sc, &sc->sc_boot_dma); 1127 return (-1); 1128 } 1129 1130 int 1131 txp_dma_malloc(struct txp_softc *sc, bus_size_t size, 1132 struct txp_dma_alloc *dma, int mapflags) 1133 { 1134 int r; 1135 1136 if ((r = bus_dmamem_alloc(sc->sc_dmat, size, PAGE_SIZE, 0, 1137 &dma->dma_seg, 1, &dma->dma_nseg, 0)) != 0) 1138 goto fail_0; 1139 1140 if ((r = bus_dmamem_map(sc->sc_dmat, &dma->dma_seg, dma->dma_nseg, 1141 size, &dma->dma_vaddr, mapflags | BUS_DMA_NOWAIT)) != 0) 1142 goto fail_1; 1143 1144 if ((r = bus_dmamap_create(sc->sc_dmat, size, 1, size, 0, 1145 BUS_DMA_NOWAIT, &dma->dma_map)) != 0) 1146 goto fail_2; 1147 1148 if ((r = bus_dmamap_load(sc->sc_dmat, dma->dma_map, dma->dma_vaddr, 1149 size, NULL, BUS_DMA_NOWAIT)) != 0) 1150 goto fail_3; 1151 1152 dma->dma_paddr = dma->dma_map->dm_segs[0].ds_addr; 1153 return (0); 1154 1155 fail_3: 1156 bus_dmamap_destroy(sc->sc_dmat, dma->dma_map); 1157 fail_2: 1158 bus_dmamem_unmap(sc->sc_dmat, dma->dma_vaddr, size); 1159 fail_1: 1160 bus_dmamem_free(sc->sc_dmat, &dma->dma_seg, dma->dma_nseg); 1161 fail_0: 1162 return (r); 1163 } 1164 1165 void 1166 txp_dma_free(struct txp_softc *sc, struct txp_dma_alloc *dma) 1167 { 1168 bus_dmamap_unload(sc->sc_dmat, dma->dma_map); 1169 bus_dmamem_unmap(sc->sc_dmat, dma->dma_vaddr, dma->dma_map->dm_mapsize); 1170 bus_dmamem_free(sc->sc_dmat, &dma->dma_seg, dma->dma_nseg); 1171 bus_dmamap_destroy(sc->sc_dmat, dma->dma_map); 1172 } 1173 1174 int 1175 txp_ioctl(struct ifnet *ifp, u_long command, caddr_t data) 1176 { 1177 struct txp_softc *sc = ifp->if_softc; 1178 struct ifaddr *ifa = (struct ifaddr *) data; 1179 struct ifreq *ifr = (struct ifreq *) data; 1180 int s, error = 0; 1181 1182 s = splnet(); 1183 1184 switch(command) { 1185 case SIOCSIFADDR: 1186 ifp->if_flags |= IFF_UP; 1187 switch (ifa->ifa_addr->sa_family) { 1188 #ifdef INET 1189 case AF_INET: 1190 txp_init(sc); 1191 arp_ifinit(&sc->sc_arpcom, ifa); 1192 break; 1193 #endif /* INET */ 1194 default: 1195 txp_init(sc); 1196 break; 1197 } 1198 break; 1199 1200 case SIOCSIFFLAGS: 1201 if (ifp->if_flags & IFF_UP) { 1202 txp_init(sc); 1203 } else { 1204 if (ifp->if_flags & IFF_RUNNING) 1205 txp_stop(sc); 1206 } 1207 break; 1208 1209 case SIOCGIFMEDIA: 1210 case SIOCSIFMEDIA: 1211 error = ifmedia_ioctl(ifp, ifr, &sc->sc_ifmedia, command); 1212 break; 1213 1214 default: 1215 error = ether_ioctl(ifp, &sc->sc_arpcom, command, data); 1216 } 1217 1218 if (error == ENETRESET) { 1219 if (ifp->if_flags & IFF_RUNNING) 1220 txp_set_filter(sc); 1221 error = 0; 1222 } 1223 1224 splx(s); 1225 return(error); 1226 } 1227 1228 void 1229 txp_init(struct txp_softc *sc) 1230 { 1231 struct ifnet *ifp = &sc->sc_arpcom.ac_if; 1232 int s; 1233 1234 txp_stop(sc); 1235 1236 s = splnet(); 1237 1238 txp_set_filter(sc); 1239 1240 txp_command(sc, TXP_CMD_TX_ENABLE, 0, 0, 0, NULL, NULL, NULL, 1); 1241 txp_command(sc, TXP_CMD_RX_ENABLE, 0, 0, 0, NULL, NULL, NULL, 1); 1242 1243 WRITE_REG(sc, TXP_IER, TXP_INT_RESERVED | TXP_INT_SELF | 1244 TXP_INT_A2H_7 | TXP_INT_A2H_6 | TXP_INT_A2H_5 | TXP_INT_A2H_4 | 1245 TXP_INT_A2H_2 | TXP_INT_A2H_1 | TXP_INT_A2H_0 | 1246 TXP_INT_DMA3 | TXP_INT_DMA2 | TXP_INT_DMA1 | TXP_INT_DMA0 | 1247 TXP_INT_PCI_TABORT | TXP_INT_PCI_MABORT | TXP_INT_LATCH); 1248 WRITE_REG(sc, TXP_IMR, TXP_INT_A2H_3); 1249 1250 ifp->if_flags |= IFF_RUNNING; 1251 ifp->if_flags &= ~IFF_OACTIVE; 1252 1253 if (!timeout_pending(&sc->sc_tick)) 1254 timeout_add_sec(&sc->sc_tick, 1); 1255 1256 splx(s); 1257 } 1258 1259 void 1260 txp_tick(void *vsc) 1261 { 1262 struct txp_softc *sc = vsc; 1263 struct ifnet *ifp = &sc->sc_arpcom.ac_if; 1264 struct txp_rsp_desc *rsp = NULL; 1265 struct txp_ext_desc *ext; 1266 int s; 1267 1268 s = splnet(); 1269 txp_rxbuf_reclaim(sc); 1270 1271 if (txp_command2(sc, TXP_CMD_READ_STATISTICS, 0, 0, 0, NULL, 0, 1272 &rsp, 1)) 1273 goto out; 1274 if (rsp->rsp_numdesc != 6) 1275 goto out; 1276 if (txp_command(sc, TXP_CMD_CLEAR_STATISTICS, 0, 0, 0, 1277 NULL, NULL, NULL, 1)) 1278 goto out; 1279 ext = (struct txp_ext_desc *)(rsp + 1); 1280 1281 ifp->if_ierrors += ext[3].ext_2 + ext[3].ext_3 + ext[3].ext_4 + 1282 ext[4].ext_1 + ext[4].ext_4; 1283 ifp->if_oerrors += ext[0].ext_1 + ext[1].ext_1 + ext[1].ext_4 + 1284 ext[2].ext_1; 1285 ifp->if_collisions += ext[0].ext_2 + ext[0].ext_3 + ext[1].ext_2 + 1286 ext[1].ext_3; 1287 ifp->if_opackets += rsp->rsp_par2; 1288 ifp->if_ipackets += ext[2].ext_3; 1289 1290 out: 1291 if (rsp != NULL) 1292 free(rsp, M_DEVBUF, 0); 1293 1294 splx(s); 1295 timeout_add_sec(&sc->sc_tick, 1); 1296 } 1297 1298 void 1299 txp_start(struct ifnet *ifp) 1300 { 1301 struct txp_softc *sc = ifp->if_softc; 1302 struct txp_tx_ring *r = &sc->sc_txhir; 1303 struct txp_tx_desc *txd; 1304 int txdidx; 1305 struct txp_frag_desc *fxd; 1306 struct mbuf *m, *mnew; 1307 struct txp_swdesc *sd; 1308 u_int32_t firstprod, firstcnt, prod, cnt, i; 1309 1310 if ((ifp->if_flags & (IFF_RUNNING | IFF_OACTIVE)) != IFF_RUNNING) 1311 return; 1312 1313 prod = r->r_prod; 1314 cnt = r->r_cnt; 1315 1316 while (1) { 1317 IFQ_POLL(&ifp->if_snd, m); 1318 if (m == NULL) 1319 break; 1320 mnew = NULL; 1321 1322 firstprod = prod; 1323 firstcnt = cnt; 1324 1325 sd = sc->sc_txd + prod; 1326 sd->sd_mbuf = m; 1327 1328 if (bus_dmamap_load_mbuf(sc->sc_dmat, sd->sd_map, m, 1329 BUS_DMA_NOWAIT)) { 1330 MGETHDR(mnew, M_DONTWAIT, MT_DATA); 1331 if (mnew == NULL) 1332 goto oactive1; 1333 if (m->m_pkthdr.len > MHLEN) { 1334 MCLGET(mnew, M_DONTWAIT); 1335 if ((mnew->m_flags & M_EXT) == 0) { 1336 m_freem(mnew); 1337 goto oactive1; 1338 } 1339 } 1340 m_copydata(m, 0, m->m_pkthdr.len, mtod(mnew, caddr_t)); 1341 mnew->m_pkthdr.len = mnew->m_len = m->m_pkthdr.len; 1342 IFQ_DEQUEUE(&ifp->if_snd, m); 1343 m_freem(m); 1344 m = mnew; 1345 if (bus_dmamap_load_mbuf(sc->sc_dmat, sd->sd_map, m, 1346 BUS_DMA_NOWAIT)) 1347 goto oactive1; 1348 } 1349 1350 if ((TX_ENTRIES - cnt) < 4) 1351 goto oactive; 1352 1353 txd = r->r_desc + prod; 1354 txdidx = prod; 1355 txd->tx_flags = TX_FLAGS_TYPE_DATA; 1356 txd->tx_numdesc = 0; 1357 txd->tx_addrlo = 0; 1358 txd->tx_addrhi = 0; 1359 txd->tx_totlen = m->m_pkthdr.len; 1360 txd->tx_pflags = 0; 1361 txd->tx_numdesc = sd->sd_map->dm_nsegs; 1362 1363 if (++prod == TX_ENTRIES) 1364 prod = 0; 1365 1366 if (++cnt >= (TX_ENTRIES - 4)) 1367 goto oactive; 1368 1369 #if NVLAN > 0 1370 if (m->m_flags & M_VLANTAG) { 1371 txd->tx_pflags = TX_PFLAGS_VLAN | 1372 (htons(m->m_pkthdr.ether_vtag) << TX_PFLAGS_VLANTAG_S); 1373 } 1374 #endif 1375 1376 if (m->m_pkthdr.csum_flags & M_IPV4_CSUM_OUT) 1377 txd->tx_pflags |= TX_PFLAGS_IPCKSUM; 1378 #ifdef TRY_TX_TCP_CSUM 1379 if (m->m_pkthdr.csum_flags & M_TCP_CSUM_OUT) 1380 txd->tx_pflags |= TX_PFLAGS_TCPCKSUM; 1381 #endif 1382 #ifdef TRY_TX_UDP_CSUM 1383 if (m->m_pkthdr.csum_flags & M_UDP_CSUM_OUT) 1384 txd->tx_pflags |= TX_PFLAGS_UDPCKSUM; 1385 #endif 1386 1387 bus_dmamap_sync(sc->sc_dmat, sd->sd_map, 0, 1388 sd->sd_map->dm_mapsize, BUS_DMASYNC_PREWRITE); 1389 1390 fxd = (struct txp_frag_desc *)(r->r_desc + prod); 1391 for (i = 0; i < sd->sd_map->dm_nsegs; i++) { 1392 if (++cnt >= (TX_ENTRIES - 4)) { 1393 bus_dmamap_sync(sc->sc_dmat, sd->sd_map, 1394 0, sd->sd_map->dm_mapsize, 1395 BUS_DMASYNC_POSTWRITE); 1396 goto oactive; 1397 } 1398 1399 fxd->frag_flags = FRAG_FLAGS_TYPE_FRAG | 1400 FRAG_FLAGS_VALID; 1401 fxd->frag_rsvd1 = 0; 1402 fxd->frag_len = sd->sd_map->dm_segs[i].ds_len; 1403 fxd->frag_addrlo = 1404 ((u_int64_t)sd->sd_map->dm_segs[i].ds_addr) & 1405 0xffffffff; 1406 fxd->frag_addrhi = 1407 ((u_int64_t)sd->sd_map->dm_segs[i].ds_addr) >> 1408 32; 1409 fxd->frag_rsvd2 = 0; 1410 1411 bus_dmamap_sync(sc->sc_dmat, 1412 sc->sc_txhiring_dma.dma_map, 1413 prod * sizeof(struct txp_frag_desc), 1414 sizeof(struct txp_frag_desc), BUS_DMASYNC_PREWRITE); 1415 1416 if (++prod == TX_ENTRIES) { 1417 fxd = (struct txp_frag_desc *)r->r_desc; 1418 prod = 0; 1419 } else 1420 fxd++; 1421 1422 } 1423 1424 /* 1425 * if mnew isn't NULL, we already dequeued and copied 1426 * the packet. 1427 */ 1428 if (mnew == NULL) 1429 IFQ_DEQUEUE(&ifp->if_snd, m); 1430 1431 ifp->if_timer = 5; 1432 1433 #if NBPFILTER > 0 1434 if (ifp->if_bpf) 1435 bpf_mtap_ether(ifp->if_bpf, m, BPF_DIRECTION_OUT); 1436 #endif 1437 1438 txd->tx_flags |= TX_FLAGS_VALID; 1439 bus_dmamap_sync(sc->sc_dmat, sc->sc_txhiring_dma.dma_map, 1440 txdidx * sizeof(struct txp_tx_desc), 1441 sizeof(struct txp_tx_desc), BUS_DMASYNC_PREWRITE); 1442 1443 #if 0 1444 { 1445 struct mbuf *mx; 1446 int i; 1447 1448 printf("txd: flags 0x%x ndesc %d totlen %d pflags 0x%x\n", 1449 txd->tx_flags, txd->tx_numdesc, txd->tx_totlen, 1450 txd->tx_pflags); 1451 for (mx = m; mx != NULL; mx = mx->m_next) { 1452 for (i = 0; i < mx->m_len; i++) { 1453 printf(":%02x", 1454 (u_int8_t)m->m_data[i]); 1455 } 1456 } 1457 printf("\n"); 1458 } 1459 #endif 1460 1461 WRITE_REG(sc, r->r_reg, TXP_IDX2OFFSET(prod)); 1462 } 1463 1464 r->r_prod = prod; 1465 r->r_cnt = cnt; 1466 return; 1467 1468 oactive: 1469 bus_dmamap_unload(sc->sc_dmat, sd->sd_map); 1470 oactive1: 1471 ifp->if_flags |= IFF_OACTIVE; 1472 r->r_prod = firstprod; 1473 r->r_cnt = firstcnt; 1474 } 1475 1476 /* 1477 * Handle simple commands sent to the typhoon 1478 */ 1479 int 1480 txp_command(struct txp_softc *sc, u_int16_t id, u_int16_t in1, 1481 u_int32_t in2, u_int32_t in3, u_int16_t *out1, u_int32_t *out2, 1482 u_int32_t *out3, int wait) 1483 { 1484 struct txp_rsp_desc *rsp = NULL; 1485 1486 if (txp_command2(sc, id, in1, in2, in3, NULL, 0, &rsp, wait)) 1487 return (-1); 1488 1489 if (!wait) 1490 return (0); 1491 1492 if (out1 != NULL) 1493 *out1 = letoh16(rsp->rsp_par1); 1494 if (out2 != NULL) 1495 *out2 = letoh32(rsp->rsp_par2); 1496 if (out3 != NULL) 1497 *out3 = letoh32(rsp->rsp_par3); 1498 free(rsp, M_DEVBUF, 0); 1499 return (0); 1500 } 1501 1502 int 1503 txp_command2(struct txp_softc *sc, u_int16_t id, u_int16_t in1, 1504 u_int32_t in2, u_int32_t in3, struct txp_ext_desc *in_extp, 1505 u_int8_t in_extn,struct txp_rsp_desc **rspp, int wait) 1506 { 1507 struct txp_hostvar *hv = sc->sc_hostvar; 1508 struct txp_cmd_desc *cmd; 1509 struct txp_ext_desc *ext; 1510 u_int32_t idx, i; 1511 u_int16_t seq; 1512 1513 if (txp_cmd_desc_numfree(sc) < (in_extn + 1)) { 1514 printf("%s: no free cmd descriptors\n", TXP_DEVNAME(sc)); 1515 return (-1); 1516 } 1517 1518 idx = sc->sc_cmdring.lastwrite; 1519 cmd = (struct txp_cmd_desc *)(((u_int8_t *)sc->sc_cmdring.base) + idx); 1520 bzero(cmd, sizeof(*cmd)); 1521 1522 cmd->cmd_numdesc = in_extn; 1523 seq = sc->sc_seq++; 1524 cmd->cmd_seq = htole16(seq); 1525 cmd->cmd_id = htole16(id); 1526 cmd->cmd_par1 = htole16(in1); 1527 cmd->cmd_par2 = htole32(in2); 1528 cmd->cmd_par3 = htole32(in3); 1529 cmd->cmd_flags = CMD_FLAGS_TYPE_CMD | 1530 (wait ? CMD_FLAGS_RESP : 0) | CMD_FLAGS_VALID; 1531 1532 idx += sizeof(struct txp_cmd_desc); 1533 if (idx == sc->sc_cmdring.size) 1534 idx = 0; 1535 1536 for (i = 0; i < in_extn; i++) { 1537 ext = (struct txp_ext_desc *)(((u_int8_t *)sc->sc_cmdring.base) + idx); 1538 bcopy(in_extp, ext, sizeof(struct txp_ext_desc)); 1539 in_extp++; 1540 idx += sizeof(struct txp_cmd_desc); 1541 if (idx == sc->sc_cmdring.size) 1542 idx = 0; 1543 } 1544 1545 sc->sc_cmdring.lastwrite = idx; 1546 1547 WRITE_REG(sc, TXP_H2A_2, sc->sc_cmdring.lastwrite); 1548 bus_dmamap_sync(sc->sc_dmat, sc->sc_host_dma.dma_map, 0, 1549 sizeof(struct txp_hostvar), BUS_DMASYNC_PREREAD); 1550 1551 if (!wait) 1552 return (0); 1553 1554 for (i = 0; i < 10000; i++) { 1555 bus_dmamap_sync(sc->sc_dmat, sc->sc_host_dma.dma_map, 0, 1556 sizeof(struct txp_hostvar), BUS_DMASYNC_POSTREAD); 1557 idx = letoh32(hv->hv_resp_read_idx); 1558 if (idx != letoh32(hv->hv_resp_write_idx)) { 1559 *rspp = NULL; 1560 if (txp_response(sc, idx, id, seq, rspp)) 1561 return (-1); 1562 if (*rspp != NULL) 1563 break; 1564 } 1565 bus_dmamap_sync(sc->sc_dmat, sc->sc_host_dma.dma_map, 0, 1566 sizeof(struct txp_hostvar), BUS_DMASYNC_PREREAD); 1567 DELAY(50); 1568 } 1569 if (i == 1000 || (*rspp) == NULL) { 1570 printf("%s: 0x%x command failed\n", TXP_DEVNAME(sc), id); 1571 return (-1); 1572 } 1573 1574 return (0); 1575 } 1576 1577 int 1578 txp_response(struct txp_softc *sc, u_int32_t ridx, u_int16_t id, 1579 u_int16_t seq, struct txp_rsp_desc **rspp) 1580 { 1581 struct txp_hostvar *hv = sc->sc_hostvar; 1582 struct txp_rsp_desc *rsp; 1583 1584 while (ridx != letoh32(hv->hv_resp_write_idx)) { 1585 rsp = (struct txp_rsp_desc *)(((u_int8_t *)sc->sc_rspring.base) + ridx); 1586 1587 if (id == letoh16(rsp->rsp_id) && letoh16(rsp->rsp_seq) == seq) { 1588 *rspp = mallocarray(rsp->rsp_numdesc + 1, 1589 sizeof(struct txp_rsp_desc), M_DEVBUF, M_NOWAIT); 1590 if ((*rspp) == NULL) 1591 return (-1); 1592 txp_rsp_fixup(sc, rsp, *rspp); 1593 return (0); 1594 } 1595 1596 if (rsp->rsp_flags & RSP_FLAGS_ERROR) { 1597 printf("%s: response error: id 0x%x\n", 1598 TXP_DEVNAME(sc), letoh16(rsp->rsp_id)); 1599 txp_rsp_fixup(sc, rsp, NULL); 1600 ridx = letoh32(hv->hv_resp_read_idx); 1601 continue; 1602 } 1603 1604 switch (letoh16(rsp->rsp_id)) { 1605 case TXP_CMD_CYCLE_STATISTICS: 1606 case TXP_CMD_MEDIA_STATUS_READ: 1607 break; 1608 case TXP_CMD_HELLO_RESPONSE: 1609 printf("%s: hello\n", TXP_DEVNAME(sc)); 1610 break; 1611 default: 1612 printf("%s: unknown id(0x%x)\n", TXP_DEVNAME(sc), 1613 letoh16(rsp->rsp_id)); 1614 } 1615 1616 txp_rsp_fixup(sc, rsp, NULL); 1617 ridx = letoh32(hv->hv_resp_read_idx); 1618 hv->hv_resp_read_idx = letoh32(ridx); 1619 } 1620 1621 return (0); 1622 } 1623 1624 void 1625 txp_rsp_fixup(struct txp_softc *sc, struct txp_rsp_desc *rsp, 1626 struct txp_rsp_desc *dst) 1627 { 1628 struct txp_rsp_desc *src = rsp; 1629 struct txp_hostvar *hv = sc->sc_hostvar; 1630 u_int32_t i, ridx; 1631 1632 ridx = letoh32(hv->hv_resp_read_idx); 1633 1634 for (i = 0; i < rsp->rsp_numdesc + 1; i++) { 1635 if (dst != NULL) 1636 bcopy(src, dst++, sizeof(struct txp_rsp_desc)); 1637 ridx += sizeof(struct txp_rsp_desc); 1638 if (ridx == sc->sc_rspring.size) { 1639 src = sc->sc_rspring.base; 1640 ridx = 0; 1641 } else 1642 src++; 1643 sc->sc_rspring.lastwrite = ridx; 1644 hv->hv_resp_read_idx = htole32(ridx); 1645 } 1646 1647 hv->hv_resp_read_idx = htole32(ridx); 1648 } 1649 1650 int 1651 txp_cmd_desc_numfree(struct txp_softc *sc) 1652 { 1653 struct txp_hostvar *hv = sc->sc_hostvar; 1654 struct txp_boot_record *br = sc->sc_boot; 1655 u_int32_t widx, ridx, nfree; 1656 1657 widx = sc->sc_cmdring.lastwrite; 1658 ridx = letoh32(hv->hv_cmd_read_idx); 1659 1660 if (widx == ridx) { 1661 /* Ring is completely free */ 1662 nfree = letoh32(br->br_cmd_siz) - sizeof(struct txp_cmd_desc); 1663 } else { 1664 if (widx > ridx) 1665 nfree = letoh32(br->br_cmd_siz) - 1666 (widx - ridx + sizeof(struct txp_cmd_desc)); 1667 else 1668 nfree = ridx - widx - sizeof(struct txp_cmd_desc); 1669 } 1670 1671 return (nfree / sizeof(struct txp_cmd_desc)); 1672 } 1673 1674 void 1675 txp_stop(struct txp_softc *sc) 1676 { 1677 struct ifnet *ifp = &sc->sc_arpcom.ac_if; 1678 1679 timeout_del(&sc->sc_tick); 1680 1681 /* Mark the interface as down and cancel the watchdog timer. */ 1682 ifp->if_flags &= ~(IFF_RUNNING | IFF_OACTIVE); 1683 ifp->if_timer = 0; 1684 1685 txp_command(sc, TXP_CMD_TX_DISABLE, 0, 0, 0, NULL, NULL, NULL, 1); 1686 txp_command(sc, TXP_CMD_RX_DISABLE, 0, 0, 0, NULL, NULL, NULL, 1); 1687 } 1688 1689 void 1690 txp_watchdog(struct ifnet *ifp) 1691 { 1692 } 1693 1694 int 1695 txp_ifmedia_upd(struct ifnet *ifp) 1696 { 1697 struct txp_softc *sc = ifp->if_softc; 1698 struct ifmedia *ifm = &sc->sc_ifmedia; 1699 u_int16_t new_xcvr; 1700 1701 if (IFM_TYPE(ifm->ifm_media) != IFM_ETHER) 1702 return (EINVAL); 1703 1704 if (IFM_SUBTYPE(ifm->ifm_media) == IFM_10_T) { 1705 if ((ifm->ifm_media & IFM_GMASK) == IFM_FDX) 1706 new_xcvr = TXP_XCVR_10_FDX; 1707 else 1708 new_xcvr = TXP_XCVR_10_HDX; 1709 } else if (IFM_SUBTYPE(ifm->ifm_media) == IFM_100_TX) { 1710 if ((ifm->ifm_media & IFM_GMASK) == IFM_FDX) 1711 new_xcvr = TXP_XCVR_100_FDX; 1712 else 1713 new_xcvr = TXP_XCVR_100_HDX; 1714 } else if (IFM_SUBTYPE(ifm->ifm_media) == IFM_AUTO) { 1715 new_xcvr = TXP_XCVR_AUTO; 1716 } else 1717 return (EINVAL); 1718 1719 /* nothing to do */ 1720 if (sc->sc_xcvr == new_xcvr) 1721 return (0); 1722 1723 txp_command(sc, TXP_CMD_XCVR_SELECT, new_xcvr, 0, 0, 1724 NULL, NULL, NULL, 0); 1725 sc->sc_xcvr = new_xcvr; 1726 1727 return (0); 1728 } 1729 1730 void 1731 txp_ifmedia_sts(struct ifnet *ifp, struct ifmediareq *ifmr) 1732 { 1733 struct txp_softc *sc = ifp->if_softc; 1734 struct ifmedia *ifm = &sc->sc_ifmedia; 1735 u_int16_t bmsr, bmcr, anar, anlpar; 1736 1737 ifmr->ifm_status = IFM_AVALID; 1738 ifmr->ifm_active = IFM_ETHER; 1739 1740 if (txp_command(sc, TXP_CMD_PHY_MGMT_READ, 0, MII_BMSR, 0, 1741 &bmsr, NULL, NULL, 1)) 1742 goto bail; 1743 if (txp_command(sc, TXP_CMD_PHY_MGMT_READ, 0, MII_BMSR, 0, 1744 &bmsr, NULL, NULL, 1)) 1745 goto bail; 1746 1747 if (txp_command(sc, TXP_CMD_PHY_MGMT_READ, 0, MII_BMCR, 0, 1748 &bmcr, NULL, NULL, 1)) 1749 goto bail; 1750 1751 if (txp_command(sc, TXP_CMD_PHY_MGMT_READ, 0, MII_ANAR, 0, 1752 &anar, NULL, NULL, 1)) 1753 goto bail; 1754 1755 if (txp_command(sc, TXP_CMD_PHY_MGMT_READ, 0, MII_ANLPAR, 0, 1756 &anlpar, NULL, NULL, 1)) 1757 goto bail; 1758 1759 if (bmsr & BMSR_LINK) 1760 ifmr->ifm_status |= IFM_ACTIVE; 1761 1762 if (bmcr & BMCR_ISO) { 1763 ifmr->ifm_active |= IFM_NONE; 1764 ifmr->ifm_status = 0; 1765 return; 1766 } 1767 1768 if (bmcr & BMCR_LOOP) 1769 ifmr->ifm_active |= IFM_LOOP; 1770 1771 if (bmcr & BMCR_AUTOEN) { 1772 if ((bmsr & BMSR_ACOMP) == 0) { 1773 ifmr->ifm_active |= IFM_NONE; 1774 return; 1775 } 1776 1777 anlpar &= anar; 1778 if (anlpar & ANLPAR_TX_FD) 1779 ifmr->ifm_active |= IFM_100_TX|IFM_FDX; 1780 else if (anlpar & ANLPAR_T4) 1781 ifmr->ifm_active |= IFM_100_T4|IFM_HDX; 1782 else if (anlpar & ANLPAR_TX) 1783 ifmr->ifm_active |= IFM_100_TX|IFM_HDX; 1784 else if (anlpar & ANLPAR_10_FD) 1785 ifmr->ifm_active |= IFM_10_T|IFM_FDX; 1786 else if (anlpar & ANLPAR_10) 1787 ifmr->ifm_active |= IFM_10_T|IFM_HDX; 1788 else 1789 ifmr->ifm_active |= IFM_NONE; 1790 } else 1791 ifmr->ifm_active = ifm->ifm_cur->ifm_media; 1792 return; 1793 1794 bail: 1795 ifmr->ifm_active |= IFM_NONE; 1796 ifmr->ifm_status &= ~IFM_AVALID; 1797 } 1798 1799 void 1800 txp_show_descriptor(void *d) 1801 { 1802 struct txp_cmd_desc *cmd = d; 1803 struct txp_rsp_desc *rsp = d; 1804 struct txp_tx_desc *txd = d; 1805 struct txp_frag_desc *frgd = d; 1806 1807 switch (cmd->cmd_flags & CMD_FLAGS_TYPE_M) { 1808 case CMD_FLAGS_TYPE_CMD: 1809 /* command descriptor */ 1810 printf("[cmd flags 0x%x num %d id %d seq %d par1 0x%x par2 0x%x par3 0x%x]\n", 1811 cmd->cmd_flags, cmd->cmd_numdesc, letoh16(cmd->cmd_id), 1812 letoh16(cmd->cmd_seq), letoh16(cmd->cmd_par1), 1813 letoh32(cmd->cmd_par2), letoh32(cmd->cmd_par3)); 1814 break; 1815 case CMD_FLAGS_TYPE_RESP: 1816 /* response descriptor */ 1817 printf("[rsp flags 0x%x num %d id %d seq %d par1 0x%x par2 0x%x par3 0x%x]\n", 1818 rsp->rsp_flags, rsp->rsp_numdesc, letoh16(rsp->rsp_id), 1819 letoh16(rsp->rsp_seq), letoh16(rsp->rsp_par1), 1820 letoh32(rsp->rsp_par2), letoh32(rsp->rsp_par3)); 1821 break; 1822 case CMD_FLAGS_TYPE_DATA: 1823 /* data header (assuming tx for now) */ 1824 printf("[data flags 0x%x num %d totlen %d addr 0x%x/0x%x pflags 0x%x]", 1825 txd->tx_flags, txd->tx_numdesc, txd->tx_totlen, 1826 txd->tx_addrlo, txd->tx_addrhi, txd->tx_pflags); 1827 break; 1828 case CMD_FLAGS_TYPE_FRAG: 1829 /* fragment descriptor */ 1830 printf("[frag flags 0x%x rsvd1 0x%x len %d addr 0x%x/0x%x rsvd2 0x%x]", 1831 frgd->frag_flags, frgd->frag_rsvd1, frgd->frag_len, 1832 frgd->frag_addrlo, frgd->frag_addrhi, frgd->frag_rsvd2); 1833 break; 1834 default: 1835 printf("[unknown(%x) flags 0x%x num %d id %d seq %d par1 0x%x par2 0x%x par3 0x%x]\n", 1836 cmd->cmd_flags & CMD_FLAGS_TYPE_M, 1837 cmd->cmd_flags, cmd->cmd_numdesc, letoh16(cmd->cmd_id), 1838 letoh16(cmd->cmd_seq), letoh16(cmd->cmd_par1), 1839 letoh32(cmd->cmd_par2), letoh32(cmd->cmd_par3)); 1840 break; 1841 } 1842 } 1843 1844 void 1845 txp_set_filter(struct txp_softc *sc) 1846 { 1847 struct arpcom *ac = &sc->sc_arpcom; 1848 struct ifnet *ifp = &sc->sc_arpcom.ac_if; 1849 u_int32_t hashbit, hash[2]; 1850 u_int16_t filter; 1851 int mcnt = 0; 1852 struct ether_multi *enm; 1853 struct ether_multistep step; 1854 1855 if (ifp->if_flags & IFF_PROMISC) { 1856 filter = TXP_RXFILT_PROMISC; 1857 goto setit; 1858 } 1859 1860 if (ac->ac_multirangecnt > 0) 1861 ifp->if_flags |= IFF_ALLMULTI; 1862 1863 filter = TXP_RXFILT_DIRECT; 1864 1865 if (ifp->if_flags & IFF_BROADCAST) 1866 filter |= TXP_RXFILT_BROADCAST; 1867 1868 if (ifp->if_flags & IFF_ALLMULTI) 1869 filter |= TXP_RXFILT_ALLMULTI; 1870 else { 1871 hash[0] = hash[1] = 0; 1872 1873 ETHER_FIRST_MULTI(step, ac, enm); 1874 while (enm != NULL) { 1875 mcnt++; 1876 hashbit = (u_int16_t)(ether_crc32_be(enm->enm_addrlo, 1877 ETHER_ADDR_LEN) & (64 - 1)); 1878 hash[hashbit / 32] |= (1 << hashbit % 32); 1879 ETHER_NEXT_MULTI(step, enm); 1880 } 1881 1882 if (mcnt > 0) { 1883 filter |= TXP_RXFILT_HASHMULTI; 1884 txp_command(sc, TXP_CMD_MCAST_HASH_MASK_WRITE, 1885 2, hash[0], hash[1], NULL, NULL, NULL, 0); 1886 } 1887 } 1888 1889 setit: 1890 txp_command(sc, TXP_CMD_RX_FILTER_WRITE, filter, 0, 0, 1891 NULL, NULL, NULL, 1); 1892 } 1893 1894 void 1895 txp_capabilities(struct txp_softc *sc) 1896 { 1897 struct ifnet *ifp = &sc->sc_arpcom.ac_if; 1898 struct txp_rsp_desc *rsp = NULL; 1899 struct txp_ext_desc *ext; 1900 1901 if (txp_command2(sc, TXP_CMD_OFFLOAD_READ, 0, 0, 0, NULL, 0, &rsp, 1)) 1902 goto out; 1903 1904 if (rsp->rsp_numdesc != 1) 1905 goto out; 1906 ext = (struct txp_ext_desc *)(rsp + 1); 1907 1908 sc->sc_tx_capability = ext->ext_1 & OFFLOAD_MASK; 1909 sc->sc_rx_capability = ext->ext_2 & OFFLOAD_MASK; 1910 1911 ifp->if_capabilities = IFCAP_VLAN_MTU; 1912 1913 #if NVLAN > 0 1914 if (rsp->rsp_par2 & rsp->rsp_par3 & OFFLOAD_VLAN) { 1915 sc->sc_tx_capability |= OFFLOAD_VLAN; 1916 sc->sc_rx_capability |= OFFLOAD_VLAN; 1917 ifp->if_capabilities |= IFCAP_VLAN_HWTAGGING; 1918 } 1919 #endif 1920 1921 #if 0 1922 /* not ready yet */ 1923 if (rsp->rsp_par2 & rsp->rsp_par3 & OFFLOAD_IPSEC) { 1924 sc->sc_tx_capability |= OFFLOAD_IPSEC; 1925 sc->sc_rx_capability |= OFFLOAD_IPSEC; 1926 ifp->if_capabilities |= IFCAP_IPSEC; 1927 } 1928 #endif 1929 1930 if (rsp->rsp_par2 & rsp->rsp_par3 & OFFLOAD_IPCKSUM) { 1931 sc->sc_tx_capability |= OFFLOAD_IPCKSUM; 1932 sc->sc_rx_capability |= OFFLOAD_IPCKSUM; 1933 ifp->if_capabilities |= IFCAP_CSUM_IPv4; 1934 } 1935 1936 if (rsp->rsp_par2 & rsp->rsp_par3 & OFFLOAD_TCPCKSUM) { 1937 sc->sc_rx_capability |= OFFLOAD_TCPCKSUM; 1938 #ifdef TRY_TX_TCP_CSUM 1939 sc->sc_tx_capability |= OFFLOAD_TCPCKSUM; 1940 ifp->if_capabilities |= IFCAP_CSUM_TCPv4; 1941 #endif 1942 } 1943 1944 if (rsp->rsp_par2 & rsp->rsp_par3 & OFFLOAD_UDPCKSUM) { 1945 sc->sc_rx_capability |= OFFLOAD_UDPCKSUM; 1946 #ifdef TRY_TX_UDP_CSUM 1947 sc->sc_tx_capability |= OFFLOAD_UDPCKSUM; 1948 ifp->if_capabilities |= IFCAP_CSUM_UDPv4; 1949 #endif 1950 } 1951 1952 if (txp_command(sc, TXP_CMD_OFFLOAD_WRITE, 0, 1953 sc->sc_tx_capability, sc->sc_rx_capability, NULL, NULL, NULL, 1)) 1954 goto out; 1955 1956 out: 1957 if (rsp != NULL) 1958 free(rsp, M_DEVBUF, 0); 1959 } 1960