1 /* $OpenBSD: if_txp.c,v 1.104 2011/04/05 18:01:21 henning Exp $ */ 2 3 /* 4 * Copyright (c) 2001 5 * Jason L. Wright <jason@thought.net>, Theo de Raadt, and 6 * Aaron Campbell <aaron@monkey.org>. All rights reserved. 7 * 8 * Redistribution and use in source and binary forms, with or without 9 * modification, are permitted provided that the following conditions 10 * are met: 11 * 1. Redistributions of source code must retain the above copyright 12 * notice, this list of conditions and the following disclaimer. 13 * 2. Redistributions in binary form must reproduce the above copyright 14 * notice, this list of conditions and the following disclaimer in the 15 * documentation and/or other materials provided with the distribution. 16 * 17 * THIS SOFTWARE IS PROVIDED BY THE AUTHORS ``AS IS'' AND ANY EXPRESS OR 18 * IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED 19 * WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE 20 * ARE DISCLAIMED. IN NO EVENT SHALL THE AUTHORS OR THE VOICES IN THEIR HEADS 21 * BE LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR 22 * CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF 23 * SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS 24 * INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN 25 * CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) 26 * ARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF 27 * THE POSSIBILITY OF SUCH DAMAGE. 28 */ 29 30 /* 31 * Driver for 3c990 (Typhoon) Ethernet ASIC 32 */ 33 34 #include "bpfilter.h" 35 #include "vlan.h" 36 37 #include <sys/param.h> 38 #include <sys/systm.h> 39 #include <sys/sockio.h> 40 #include <sys/mbuf.h> 41 #include <sys/malloc.h> 42 #include <sys/kernel.h> 43 #include <sys/socket.h> 44 #include <sys/device.h> 45 #include <sys/timeout.h> 46 47 #include <net/if.h> 48 #include <net/if_dl.h> 49 #include <net/if_types.h> 50 51 #ifdef INET 52 #include <netinet/in.h> 53 #include <netinet/in_systm.h> 54 #include <netinet/in_var.h> 55 #include <netinet/ip.h> 56 #include <netinet/if_ether.h> 57 #endif 58 59 #include <net/if_media.h> 60 61 #if NBPFILTER > 0 62 #include <net/bpf.h> 63 #endif 64 65 #if NVLAN > 0 66 #include <net/if_types.h> 67 #include <net/if_vlan_var.h> 68 #endif 69 70 #include <machine/bus.h> 71 72 #include <dev/mii/mii.h> 73 #include <dev/mii/miivar.h> 74 #include <dev/pci/pcireg.h> 75 #include <dev/pci/pcivar.h> 76 #include <dev/pci/pcidevs.h> 77 78 #include <dev/pci/if_txpreg.h> 79 80 /* 81 * These currently break the 3c990 firmware, hopefully will be resolved 82 * at some point. 83 */ 84 #undef TRY_TX_UDP_CSUM 85 #undef TRY_TX_TCP_CSUM 86 87 int txp_probe(struct device *, void *, void *); 88 void txp_attach(struct device *, struct device *, void *); 89 void txp_attachhook(void *vsc); 90 int txp_intr(void *); 91 void txp_tick(void *); 92 int txp_ioctl(struct ifnet *, u_long, caddr_t); 93 void txp_start(struct ifnet *); 94 void txp_stop(struct txp_softc *); 95 void txp_init(struct txp_softc *); 96 void txp_watchdog(struct ifnet *); 97 98 int txp_chip_init(struct txp_softc *); 99 int txp_reset_adapter(struct txp_softc *); 100 int txp_download_fw(struct txp_softc *); 101 int txp_download_fw_wait(struct txp_softc *); 102 int txp_download_fw_section(struct txp_softc *, 103 struct txp_fw_section_header *, int, u_char *, size_t); 104 int txp_alloc_rings(struct txp_softc *); 105 void txp_dma_free(struct txp_softc *, struct txp_dma_alloc *); 106 int txp_dma_malloc(struct txp_softc *, bus_size_t, struct txp_dma_alloc *, int); 107 void txp_set_filter(struct txp_softc *); 108 109 int txp_cmd_desc_numfree(struct txp_softc *); 110 int txp_command(struct txp_softc *, u_int16_t, u_int16_t, u_int32_t, 111 u_int32_t, u_int16_t *, u_int32_t *, u_int32_t *, int); 112 int txp_command2(struct txp_softc *, u_int16_t, u_int16_t, 113 u_int32_t, u_int32_t, struct txp_ext_desc *, u_int8_t, 114 struct txp_rsp_desc **, int); 115 int txp_response(struct txp_softc *, u_int32_t, u_int16_t, u_int16_t, 116 struct txp_rsp_desc **); 117 void txp_rsp_fixup(struct txp_softc *, struct txp_rsp_desc *, 118 struct txp_rsp_desc *); 119 void txp_capabilities(struct txp_softc *); 120 121 void txp_ifmedia_sts(struct ifnet *, struct ifmediareq *); 122 int txp_ifmedia_upd(struct ifnet *); 123 void txp_show_descriptor(void *); 124 void txp_tx_reclaim(struct txp_softc *, struct txp_tx_ring *, 125 struct txp_dma_alloc *); 126 void txp_rxbuf_reclaim(struct txp_softc *); 127 void txp_rx_reclaim(struct txp_softc *, struct txp_rx_ring *, 128 struct txp_dma_alloc *); 129 130 struct cfattach txp_ca = { 131 sizeof(struct txp_softc), txp_probe, txp_attach, 132 }; 133 134 struct cfdriver txp_cd = { 135 NULL, "txp", DV_IFNET 136 }; 137 138 const struct pci_matchid txp_devices[] = { 139 { PCI_VENDOR_3COM, PCI_PRODUCT_3COM_3CR990 }, 140 { PCI_VENDOR_3COM, PCI_PRODUCT_3COM_3CR990TX }, 141 { PCI_VENDOR_3COM, PCI_PRODUCT_3COM_3CR990TX95 }, 142 { PCI_VENDOR_3COM, PCI_PRODUCT_3COM_3CR990TX97 }, 143 { PCI_VENDOR_3COM, PCI_PRODUCT_3COM_3CR990SVR95 }, 144 { PCI_VENDOR_3COM, PCI_PRODUCT_3COM_3CR990SVR97 }, 145 { PCI_VENDOR_3COM, PCI_PRODUCT_3COM_3C990BTXM }, 146 { PCI_VENDOR_3COM, PCI_PRODUCT_3COM_3C990BSVR }, 147 { PCI_VENDOR_3COM, PCI_PRODUCT_3COM_3CR990FX }, 148 }; 149 150 int 151 txp_probe(struct device *parent, void *match, void *aux) 152 { 153 return (pci_matchbyid((struct pci_attach_args *)aux, txp_devices, 154 nitems(txp_devices))); 155 } 156 157 void 158 txp_attachhook(void *vsc) 159 { 160 struct txp_softc *sc = vsc; 161 struct ifnet *ifp = &sc->sc_arpcom.ac_if; 162 u_int16_t p1; 163 u_int32_t p2; 164 int s; 165 166 s = splnet(); 167 printf("%s: ", sc->sc_dev.dv_xname); 168 169 if (txp_chip_init(sc)) { 170 printf("failed chip init\n"); 171 splx(s); 172 return; 173 } 174 175 if (txp_download_fw(sc)) { 176 splx(s); 177 return; 178 } 179 180 if (txp_alloc_rings(sc)) { 181 splx(s); 182 return; 183 } 184 185 if (txp_command(sc, TXP_CMD_MAX_PKT_SIZE_WRITE, TXP_MAX_PKTLEN, 0, 0, 186 NULL, NULL, NULL, 1)) { 187 splx(s); 188 return; 189 } 190 191 if (txp_command(sc, TXP_CMD_STATION_ADDRESS_READ, 0, 0, 0, 192 &p1, &p2, NULL, 1)) { 193 splx(s); 194 return; 195 } 196 197 p1 = htole16(p1); 198 sc->sc_arpcom.ac_enaddr[0] = ((u_int8_t *)&p1)[1]; 199 sc->sc_arpcom.ac_enaddr[1] = ((u_int8_t *)&p1)[0]; 200 p2 = htole32(p2); 201 sc->sc_arpcom.ac_enaddr[2] = ((u_int8_t *)&p2)[3]; 202 sc->sc_arpcom.ac_enaddr[3] = ((u_int8_t *)&p2)[2]; 203 sc->sc_arpcom.ac_enaddr[4] = ((u_int8_t *)&p2)[1]; 204 sc->sc_arpcom.ac_enaddr[5] = ((u_int8_t *)&p2)[0]; 205 206 printf("address %s\n", ether_sprintf(sc->sc_arpcom.ac_enaddr)); 207 sc->sc_cold = 0; 208 209 ifmedia_init(&sc->sc_ifmedia, 0, txp_ifmedia_upd, txp_ifmedia_sts); 210 ifmedia_add(&sc->sc_ifmedia, IFM_ETHER|IFM_10_T, 0, NULL); 211 ifmedia_add(&sc->sc_ifmedia, IFM_ETHER|IFM_10_T|IFM_HDX, 0, NULL); 212 ifmedia_add(&sc->sc_ifmedia, IFM_ETHER|IFM_10_T|IFM_FDX, 0, NULL); 213 ifmedia_add(&sc->sc_ifmedia, IFM_ETHER|IFM_100_TX, 0, NULL); 214 ifmedia_add(&sc->sc_ifmedia, IFM_ETHER|IFM_100_TX|IFM_HDX, 0, NULL); 215 ifmedia_add(&sc->sc_ifmedia, IFM_ETHER|IFM_100_TX|IFM_FDX, 0, NULL); 216 ifmedia_add(&sc->sc_ifmedia, IFM_ETHER|IFM_AUTO, 0, NULL); 217 218 sc->sc_xcvr = TXP_XCVR_AUTO; 219 txp_command(sc, TXP_CMD_XCVR_SELECT, TXP_XCVR_AUTO, 0, 0, 220 NULL, NULL, NULL, 0); 221 ifmedia_set(&sc->sc_ifmedia, IFM_ETHER|IFM_AUTO); 222 223 ifp->if_softc = sc; 224 ifp->if_flags = IFF_BROADCAST | IFF_SIMPLEX | IFF_MULTICAST; 225 ifp->if_ioctl = txp_ioctl; 226 ifp->if_start = txp_start; 227 ifp->if_watchdog = txp_watchdog; 228 ifp->if_baudrate = 10000000; 229 IFQ_SET_MAXLEN(&ifp->if_snd, TX_ENTRIES); 230 IFQ_SET_READY(&ifp->if_snd); 231 ifp->if_capabilities = 0; 232 bcopy(sc->sc_dev.dv_xname, ifp->if_xname, IFNAMSIZ); 233 234 txp_capabilities(sc); 235 236 timeout_set(&sc->sc_tick, txp_tick, sc); 237 238 /* 239 * Attach us everywhere 240 */ 241 if_attach(ifp); 242 ether_ifattach(ifp); 243 244 splx(s); 245 } 246 247 void 248 txp_attach(struct device *parent, struct device *self, void *aux) 249 { 250 struct txp_softc *sc = (struct txp_softc *)self; 251 struct pci_attach_args *pa = aux; 252 pci_chipset_tag_t pc = pa->pa_pc; 253 pci_intr_handle_t ih; 254 const char *intrstr = NULL; 255 bus_size_t iosize; 256 257 sc->sc_cold = 1; 258 259 if (pci_mapreg_map(pa, TXP_PCI_LOMEM, PCI_MAPREG_TYPE_MEM, 0, 260 &sc->sc_bt, &sc->sc_bh, NULL, &iosize, 0)) { 261 printf(": can't map mem space %d\n", 0); 262 return; 263 } 264 265 sc->sc_dmat = pa->pa_dmat; 266 267 /* 268 * Allocate our interrupt. 269 */ 270 if (pci_intr_map(pa, &ih)) { 271 printf(": couldn't map interrupt\n"); 272 return; 273 } 274 275 intrstr = pci_intr_string(pc, ih); 276 sc->sc_ih = pci_intr_establish(pc, ih, IPL_NET, txp_intr, sc, 277 self->dv_xname); 278 if (sc->sc_ih == NULL) { 279 printf(": couldn't establish interrupt"); 280 if (intrstr != NULL) 281 printf(" at %s", intrstr); 282 printf("\n"); 283 return; 284 } 285 printf(": %s\n", intrstr); 286 287 if (rootvp == NULL) 288 mountroothook_establish(txp_attachhook, sc); 289 else 290 txp_attachhook(sc); 291 292 } 293 294 int 295 txp_chip_init(struct txp_softc *sc) 296 { 297 /* disable interrupts */ 298 WRITE_REG(sc, TXP_IER, 0); 299 WRITE_REG(sc, TXP_IMR, 300 TXP_INT_SELF | TXP_INT_PCI_TABORT | TXP_INT_PCI_MABORT | 301 TXP_INT_DMA3 | TXP_INT_DMA2 | TXP_INT_DMA1 | TXP_INT_DMA0 | 302 TXP_INT_LATCH); 303 304 /* ack all interrupts */ 305 WRITE_REG(sc, TXP_ISR, TXP_INT_RESERVED | TXP_INT_LATCH | 306 TXP_INT_A2H_7 | TXP_INT_A2H_6 | TXP_INT_A2H_5 | TXP_INT_A2H_4 | 307 TXP_INT_SELF | TXP_INT_PCI_TABORT | TXP_INT_PCI_MABORT | 308 TXP_INT_DMA3 | TXP_INT_DMA2 | TXP_INT_DMA1 | TXP_INT_DMA0 | 309 TXP_INT_A2H_3 | TXP_INT_A2H_2 | TXP_INT_A2H_1 | TXP_INT_A2H_0); 310 311 if (txp_reset_adapter(sc)) 312 return (-1); 313 314 /* disable interrupts */ 315 WRITE_REG(sc, TXP_IER, 0); 316 WRITE_REG(sc, TXP_IMR, 317 TXP_INT_SELF | TXP_INT_PCI_TABORT | TXP_INT_PCI_MABORT | 318 TXP_INT_DMA3 | TXP_INT_DMA2 | TXP_INT_DMA1 | TXP_INT_DMA0 | 319 TXP_INT_LATCH); 320 321 /* ack all interrupts */ 322 WRITE_REG(sc, TXP_ISR, TXP_INT_RESERVED | TXP_INT_LATCH | 323 TXP_INT_A2H_7 | TXP_INT_A2H_6 | TXP_INT_A2H_5 | TXP_INT_A2H_4 | 324 TXP_INT_SELF | TXP_INT_PCI_TABORT | TXP_INT_PCI_MABORT | 325 TXP_INT_DMA3 | TXP_INT_DMA2 | TXP_INT_DMA1 | TXP_INT_DMA0 | 326 TXP_INT_A2H_3 | TXP_INT_A2H_2 | TXP_INT_A2H_1 | TXP_INT_A2H_0); 327 328 return (0); 329 } 330 331 int 332 txp_reset_adapter(struct txp_softc *sc) 333 { 334 u_int32_t r; 335 int i; 336 337 WRITE_REG(sc, TXP_SRR, TXP_SRR_ALL); 338 DELAY(1000); 339 WRITE_REG(sc, TXP_SRR, 0); 340 341 /* Should wait max 6 seconds */ 342 for (i = 0; i < 6000; i++) { 343 r = READ_REG(sc, TXP_A2H_0); 344 if (r == STAT_WAITING_FOR_HOST_REQUEST) 345 break; 346 DELAY(1000); 347 } 348 349 if (r != STAT_WAITING_FOR_HOST_REQUEST) { 350 printf("%s: reset hung\n", TXP_DEVNAME(sc)); 351 return (-1); 352 } 353 354 return (0); 355 } 356 357 int 358 txp_download_fw(struct txp_softc *sc) 359 { 360 struct txp_fw_file_header *fileheader; 361 struct txp_fw_section_header *secthead; 362 u_int32_t r, i, ier, imr; 363 size_t buflen; 364 int sect, err; 365 u_char *buf; 366 367 ier = READ_REG(sc, TXP_IER); 368 WRITE_REG(sc, TXP_IER, ier | TXP_INT_A2H_0); 369 370 imr = READ_REG(sc, TXP_IMR); 371 WRITE_REG(sc, TXP_IMR, imr | TXP_INT_A2H_0); 372 373 for (i = 0; i < 10000; i++) { 374 r = READ_REG(sc, TXP_A2H_0); 375 if (r == STAT_WAITING_FOR_HOST_REQUEST) 376 break; 377 DELAY(50); 378 } 379 if (r != STAT_WAITING_FOR_HOST_REQUEST) { 380 printf("not waiting for host request\n"); 381 return (-1); 382 } 383 384 /* Ack the status */ 385 WRITE_REG(sc, TXP_ISR, TXP_INT_A2H_0); 386 387 err = loadfirmware("3c990", &buf, &buflen); 388 if (err) { 389 printf("failed loadfirmware of file 3c990: errno %d\n", 390 err); 391 return (err); 392 } 393 394 fileheader = (struct txp_fw_file_header *)buf; 395 if (bcmp("TYPHOON", fileheader->magicid, sizeof(fileheader->magicid))) { 396 printf("firmware invalid magic\n"); 397 goto fail; 398 } 399 400 /* Tell boot firmware to get ready for image */ 401 WRITE_REG(sc, TXP_H2A_1, letoh32(fileheader->addr)); 402 WRITE_REG(sc, TXP_H2A_2, letoh32(fileheader->hmac[0])); 403 WRITE_REG(sc, TXP_H2A_3, letoh32(fileheader->hmac[1])); 404 WRITE_REG(sc, TXP_H2A_4, letoh32(fileheader->hmac[2])); 405 WRITE_REG(sc, TXP_H2A_5, letoh32(fileheader->hmac[3])); 406 WRITE_REG(sc, TXP_H2A_6, letoh32(fileheader->hmac[4])); 407 WRITE_REG(sc, TXP_H2A_0, TXP_BOOTCMD_RUNTIME_IMAGE); 408 409 if (txp_download_fw_wait(sc)) { 410 printf("fw wait failed, initial\n"); 411 goto fail; 412 } 413 414 secthead = (struct txp_fw_section_header *)(buf + 415 sizeof(struct txp_fw_file_header)); 416 417 for (sect = 0; sect < letoh32(fileheader->nsections); sect++) { 418 if (txp_download_fw_section(sc, secthead, sect, buf, buflen)) 419 goto fail; 420 secthead = (struct txp_fw_section_header *) 421 (((u_int8_t *)secthead) + letoh32(secthead->nbytes) + 422 sizeof(*secthead)); 423 } 424 425 WRITE_REG(sc, TXP_H2A_0, TXP_BOOTCMD_DOWNLOAD_COMPLETE); 426 427 for (i = 0; i < 10000; i++) { 428 r = READ_REG(sc, TXP_A2H_0); 429 if (r == STAT_WAITING_FOR_BOOT) 430 break; 431 DELAY(50); 432 } 433 if (r != STAT_WAITING_FOR_BOOT) { 434 printf("not waiting for boot\n"); 435 goto fail; 436 } 437 438 WRITE_REG(sc, TXP_IER, ier); 439 WRITE_REG(sc, TXP_IMR, imr); 440 441 free(buf, M_DEVBUF); 442 return (0); 443 fail: 444 free(buf, M_DEVBUF); 445 return (-1); 446 } 447 448 int 449 txp_download_fw_wait(struct txp_softc *sc) 450 { 451 u_int32_t i, r; 452 453 for (i = 0; i < 10000; i++) { 454 r = READ_REG(sc, TXP_ISR); 455 if (r & TXP_INT_A2H_0) 456 break; 457 DELAY(50); 458 } 459 460 if (!(r & TXP_INT_A2H_0)) { 461 printf("fw wait failed comm0\n"); 462 return (-1); 463 } 464 465 WRITE_REG(sc, TXP_ISR, TXP_INT_A2H_0); 466 467 r = READ_REG(sc, TXP_A2H_0); 468 if (r != STAT_WAITING_FOR_SEGMENT) { 469 printf("fw not waiting for segment\n"); 470 return (-1); 471 } 472 return (0); 473 } 474 475 int 476 txp_download_fw_section(struct txp_softc *sc, 477 struct txp_fw_section_header *sect, int sectnum, u_char *buf, 478 size_t buflen) 479 { 480 struct txp_dma_alloc dma; 481 int rseg, err = 0; 482 struct mbuf m; 483 u_int16_t csum; 484 485 /* Skip zero length sections */ 486 if (sect->nbytes == 0) 487 return (0); 488 489 /* Make sure we aren't past the end of the image */ 490 rseg = ((u_int8_t *)sect) - ((u_int8_t *)buf); 491 if (rseg >= buflen) { 492 printf("fw invalid section address, section %d\n", sectnum); 493 return (-1); 494 } 495 496 /* Make sure this section doesn't go past the end */ 497 rseg += letoh32(sect->nbytes); 498 if (rseg >= buflen) { 499 printf("fw truncated section %d\n", sectnum); 500 return (-1); 501 } 502 503 /* map a buffer, copy segment to it, get physaddr */ 504 if (txp_dma_malloc(sc, letoh32(sect->nbytes), &dma, 0)) { 505 printf("fw dma malloc failed, section %d\n", sectnum); 506 return (-1); 507 } 508 509 bcopy(((u_int8_t *)sect) + sizeof(*sect), dma.dma_vaddr, 510 letoh32(sect->nbytes)); 511 512 /* 513 * dummy up mbuf and verify section checksum 514 */ 515 m.m_type = MT_DATA; 516 m.m_next = m.m_nextpkt = NULL; 517 m.m_len = letoh32(sect->nbytes); 518 m.m_data = dma.dma_vaddr; 519 m.m_flags = 0; 520 csum = in_cksum(&m, letoh32(sect->nbytes)); 521 if (csum != sect->cksum) { 522 printf("fw section %d, bad cksum (expected 0x%x got 0x%x)\n", 523 sectnum, sect->cksum, csum); 524 err = -1; 525 goto bail; 526 } 527 528 bus_dmamap_sync(sc->sc_dmat, dma.dma_map, 0, 529 dma.dma_map->dm_mapsize, BUS_DMASYNC_PREWRITE); 530 531 WRITE_REG(sc, TXP_H2A_1, letoh32(sect->nbytes)); 532 WRITE_REG(sc, TXP_H2A_2, letoh16(sect->cksum)); 533 WRITE_REG(sc, TXP_H2A_3, letoh32(sect->addr)); 534 WRITE_REG(sc, TXP_H2A_4, dma.dma_paddr >> 32); 535 WRITE_REG(sc, TXP_H2A_5, dma.dma_paddr & 0xffffffff); 536 WRITE_REG(sc, TXP_H2A_0, TXP_BOOTCMD_SEGMENT_AVAILABLE); 537 538 if (txp_download_fw_wait(sc)) { 539 printf("%s: fw wait failed, section %d\n", 540 sc->sc_dev.dv_xname, sectnum); 541 err = -1; 542 } 543 544 bus_dmamap_sync(sc->sc_dmat, dma.dma_map, 0, 545 dma.dma_map->dm_mapsize, BUS_DMASYNC_POSTWRITE); 546 547 bail: 548 txp_dma_free(sc, &dma); 549 550 return (err); 551 } 552 553 int 554 txp_intr(void *vsc) 555 { 556 struct txp_softc *sc = vsc; 557 struct txp_hostvar *hv = sc->sc_hostvar; 558 u_int32_t isr; 559 int claimed = 0; 560 561 /* mask all interrupts */ 562 WRITE_REG(sc, TXP_IMR, TXP_INT_RESERVED | TXP_INT_SELF | 563 TXP_INT_A2H_7 | TXP_INT_A2H_6 | TXP_INT_A2H_5 | TXP_INT_A2H_4 | 564 TXP_INT_A2H_2 | TXP_INT_A2H_1 | TXP_INT_A2H_0 | 565 TXP_INT_DMA3 | TXP_INT_DMA2 | TXP_INT_DMA1 | TXP_INT_DMA0 | 566 TXP_INT_PCI_TABORT | TXP_INT_PCI_MABORT | TXP_INT_LATCH); 567 568 bus_dmamap_sync(sc->sc_dmat, sc->sc_host_dma.dma_map, 0, 569 sizeof(struct txp_hostvar), BUS_DMASYNC_POSTWRITE|BUS_DMASYNC_POSTREAD); 570 571 isr = READ_REG(sc, TXP_ISR); 572 while (isr) { 573 claimed = 1; 574 WRITE_REG(sc, TXP_ISR, isr); 575 576 if ((*sc->sc_rxhir.r_roff) != (*sc->sc_rxhir.r_woff)) 577 txp_rx_reclaim(sc, &sc->sc_rxhir, &sc->sc_rxhiring_dma); 578 if ((*sc->sc_rxlor.r_roff) != (*sc->sc_rxlor.r_woff)) 579 txp_rx_reclaim(sc, &sc->sc_rxlor, &sc->sc_rxloring_dma); 580 581 if (hv->hv_rx_buf_write_idx == hv->hv_rx_buf_read_idx) 582 txp_rxbuf_reclaim(sc); 583 584 if (sc->sc_txhir.r_cnt && (sc->sc_txhir.r_cons != 585 TXP_OFFSET2IDX(letoh32(*(sc->sc_txhir.r_off))))) 586 txp_tx_reclaim(sc, &sc->sc_txhir, &sc->sc_txhiring_dma); 587 588 if (sc->sc_txlor.r_cnt && (sc->sc_txlor.r_cons != 589 TXP_OFFSET2IDX(letoh32(*(sc->sc_txlor.r_off))))) 590 txp_tx_reclaim(sc, &sc->sc_txlor, &sc->sc_txloring_dma); 591 592 isr = READ_REG(sc, TXP_ISR); 593 } 594 595 bus_dmamap_sync(sc->sc_dmat, sc->sc_host_dma.dma_map, 0, 596 sizeof(struct txp_hostvar), BUS_DMASYNC_POSTWRITE|BUS_DMASYNC_POSTREAD); 597 598 /* unmask all interrupts */ 599 WRITE_REG(sc, TXP_IMR, TXP_INT_A2H_3); 600 601 txp_start(&sc->sc_arpcom.ac_if); 602 603 return (claimed); 604 } 605 606 void 607 txp_rx_reclaim(struct txp_softc *sc, struct txp_rx_ring *r, 608 struct txp_dma_alloc *dma) 609 { 610 struct ifnet *ifp = &sc->sc_arpcom.ac_if; 611 struct txp_rx_desc *rxd; 612 struct mbuf *m; 613 struct txp_swdesc *sd; 614 u_int32_t roff, woff; 615 int idx; 616 u_int16_t sumflags = 0; 617 618 roff = letoh32(*r->r_roff); 619 woff = letoh32(*r->r_woff); 620 idx = roff / sizeof(struct txp_rx_desc); 621 rxd = r->r_desc + idx; 622 623 while (roff != woff) { 624 625 bus_dmamap_sync(sc->sc_dmat, dma->dma_map, 626 idx * sizeof(struct txp_rx_desc), sizeof(struct txp_rx_desc), 627 BUS_DMASYNC_POSTREAD); 628 629 if (rxd->rx_flags & RX_FLAGS_ERROR) { 630 printf("%s: error 0x%x\n", sc->sc_dev.dv_xname, 631 letoh32(rxd->rx_stat)); 632 ifp->if_ierrors++; 633 goto next; 634 } 635 636 /* retrieve stashed pointer */ 637 bcopy((u_long *)&rxd->rx_vaddrlo, &sd, sizeof(sd)); 638 639 bus_dmamap_sync(sc->sc_dmat, sd->sd_map, 0, 640 sd->sd_map->dm_mapsize, BUS_DMASYNC_POSTREAD); 641 bus_dmamap_unload(sc->sc_dmat, sd->sd_map); 642 bus_dmamap_destroy(sc->sc_dmat, sd->sd_map); 643 m = sd->sd_mbuf; 644 free(sd, M_DEVBUF); 645 m->m_pkthdr.len = m->m_len = letoh16(rxd->rx_len); 646 647 #ifdef __STRICT_ALIGNMENT 648 { 649 /* 650 * XXX Nice chip, except it won't accept "off by 2" 651 * buffers, so we're force to copy. Supposedly 652 * this will be fixed in a newer firmware rev 653 * and this will be temporary. 654 */ 655 struct mbuf *mnew; 656 657 MGETHDR(mnew, M_DONTWAIT, MT_DATA); 658 if (mnew == NULL) { 659 m_freem(m); 660 goto next; 661 } 662 if (m->m_len > (MHLEN - 2)) { 663 MCLGET(mnew, M_DONTWAIT); 664 if (!(mnew->m_flags & M_EXT)) { 665 m_freem(mnew); 666 m_freem(m); 667 goto next; 668 } 669 } 670 mnew->m_pkthdr.rcvif = ifp; 671 mnew->m_pkthdr.len = mnew->m_len = m->m_len; 672 mnew->m_data += 2; 673 bcopy(m->m_data, mnew->m_data, m->m_len); 674 m_freem(m); 675 m = mnew; 676 } 677 #endif 678 679 #if NVLAN > 0 680 /* 681 * XXX Another firmware bug: the vlan encapsulation 682 * is always removed, even when we tell the card not 683 * to do that. Restore the vlan encapsulation below. 684 */ 685 if (rxd->rx_stat & htole32(RX_STAT_VLAN)) { 686 m->m_pkthdr.ether_vtag = ntohs(rxd->rx_vlan >> 16); 687 m->m_flags |= M_VLANTAG; 688 } 689 #endif 690 691 #if NBPFILTER > 0 692 /* 693 * Handle BPF listeners. Let the BPF user see the packet. 694 */ 695 if (ifp->if_bpf) 696 bpf_mtap_ether(ifp->if_bpf, m, BPF_DIRECTION_IN); 697 #endif 698 699 if (rxd->rx_stat & htole32(RX_STAT_IPCKSUMBAD)) 700 sumflags |= M_IPV4_CSUM_IN_BAD; 701 else if (rxd->rx_stat & htole32(RX_STAT_IPCKSUMGOOD)) 702 sumflags |= M_IPV4_CSUM_IN_OK; 703 704 if (rxd->rx_stat & htole32(RX_STAT_TCPCKSUMBAD)) 705 sumflags |= M_TCP_CSUM_IN_BAD; 706 else if (rxd->rx_stat & htole32(RX_STAT_TCPCKSUMGOOD)) 707 sumflags |= M_TCP_CSUM_IN_OK; 708 709 if (rxd->rx_stat & htole32(RX_STAT_UDPCKSUMBAD)) 710 sumflags |= M_UDP_CSUM_IN_BAD; 711 else if (rxd->rx_stat & htole32(RX_STAT_UDPCKSUMGOOD)) 712 sumflags |= M_UDP_CSUM_IN_OK; 713 714 m->m_pkthdr.csum_flags = sumflags; 715 716 ether_input_mbuf(ifp, m); 717 718 next: 719 bus_dmamap_sync(sc->sc_dmat, dma->dma_map, 720 idx * sizeof(struct txp_rx_desc), sizeof(struct txp_rx_desc), 721 BUS_DMASYNC_PREREAD); 722 723 roff += sizeof(struct txp_rx_desc); 724 if (roff == (RX_ENTRIES * sizeof(struct txp_rx_desc))) { 725 idx = 0; 726 roff = 0; 727 rxd = r->r_desc; 728 } else { 729 idx++; 730 rxd++; 731 } 732 woff = letoh32(*r->r_woff); 733 } 734 735 *r->r_roff = htole32(woff); 736 } 737 738 void 739 txp_rxbuf_reclaim(struct txp_softc *sc) 740 { 741 struct ifnet *ifp = &sc->sc_arpcom.ac_if; 742 struct txp_hostvar *hv = sc->sc_hostvar; 743 struct txp_rxbuf_desc *rbd; 744 struct txp_swdesc *sd; 745 u_int32_t i, end; 746 747 end = TXP_OFFSET2IDX(letoh32(hv->hv_rx_buf_read_idx)); 748 i = TXP_OFFSET2IDX(letoh32(hv->hv_rx_buf_write_idx)); 749 750 if (++i == RXBUF_ENTRIES) 751 i = 0; 752 753 rbd = sc->sc_rxbufs + i; 754 755 while (i != end) { 756 sd = (struct txp_swdesc *)malloc(sizeof(struct txp_swdesc), 757 M_DEVBUF, M_NOWAIT); 758 if (sd == NULL) 759 break; 760 761 MGETHDR(sd->sd_mbuf, M_DONTWAIT, MT_DATA); 762 if (sd->sd_mbuf == NULL) 763 goto err_sd; 764 765 MCLGET(sd->sd_mbuf, M_DONTWAIT); 766 if ((sd->sd_mbuf->m_flags & M_EXT) == 0) 767 goto err_mbuf; 768 sd->sd_mbuf->m_pkthdr.rcvif = ifp; 769 sd->sd_mbuf->m_pkthdr.len = sd->sd_mbuf->m_len = MCLBYTES; 770 if (bus_dmamap_create(sc->sc_dmat, TXP_MAX_PKTLEN, 1, 771 TXP_MAX_PKTLEN, 0, BUS_DMA_NOWAIT, &sd->sd_map)) 772 goto err_mbuf; 773 if (bus_dmamap_load_mbuf(sc->sc_dmat, sd->sd_map, sd->sd_mbuf, 774 BUS_DMA_NOWAIT)) { 775 bus_dmamap_destroy(sc->sc_dmat, sd->sd_map); 776 goto err_mbuf; 777 } 778 779 bus_dmamap_sync(sc->sc_dmat, sc->sc_rxbufring_dma.dma_map, 780 i * sizeof(struct txp_rxbuf_desc), 781 sizeof(struct txp_rxbuf_desc), BUS_DMASYNC_POSTWRITE); 782 783 /* stash away pointer */ 784 bcopy(&sd, (u_long *)&rbd->rb_vaddrlo, sizeof(sd)); 785 786 rbd->rb_paddrlo = ((u_int64_t)sd->sd_map->dm_segs[0].ds_addr) 787 & 0xffffffff; 788 rbd->rb_paddrhi = ((u_int64_t)sd->sd_map->dm_segs[0].ds_addr) 789 >> 32; 790 791 bus_dmamap_sync(sc->sc_dmat, sd->sd_map, 0, 792 sd->sd_map->dm_mapsize, BUS_DMASYNC_PREREAD); 793 794 bus_dmamap_sync(sc->sc_dmat, sc->sc_rxbufring_dma.dma_map, 795 i * sizeof(struct txp_rxbuf_desc), 796 sizeof(struct txp_rxbuf_desc), BUS_DMASYNC_PREWRITE); 797 798 hv->hv_rx_buf_write_idx = htole32(TXP_IDX2OFFSET(i)); 799 800 if (++i == RXBUF_ENTRIES) { 801 i = 0; 802 rbd = sc->sc_rxbufs; 803 } else 804 rbd++; 805 } 806 return; 807 808 err_mbuf: 809 m_freem(sd->sd_mbuf); 810 err_sd: 811 free(sd, M_DEVBUF); 812 } 813 814 /* 815 * Reclaim mbufs and entries from a transmit ring. 816 */ 817 void 818 txp_tx_reclaim(struct txp_softc *sc, struct txp_tx_ring *r, 819 struct txp_dma_alloc *dma) 820 { 821 struct ifnet *ifp = &sc->sc_arpcom.ac_if; 822 u_int32_t idx = TXP_OFFSET2IDX(letoh32(*(r->r_off))); 823 u_int32_t cons = r->r_cons, cnt = r->r_cnt; 824 struct txp_tx_desc *txd = r->r_desc + cons; 825 struct txp_swdesc *sd = sc->sc_txd + cons; 826 struct mbuf *m; 827 828 while (cons != idx) { 829 if (cnt == 0) 830 break; 831 832 bus_dmamap_sync(sc->sc_dmat, dma->dma_map, 833 cons * sizeof(struct txp_tx_desc), 834 sizeof(struct txp_tx_desc), 835 BUS_DMASYNC_POSTWRITE); 836 837 if ((txd->tx_flags & TX_FLAGS_TYPE_M) == 838 TX_FLAGS_TYPE_DATA) { 839 bus_dmamap_sync(sc->sc_dmat, sd->sd_map, 0, 840 sd->sd_map->dm_mapsize, BUS_DMASYNC_POSTWRITE); 841 bus_dmamap_unload(sc->sc_dmat, sd->sd_map); 842 m = sd->sd_mbuf; 843 if (m != NULL) { 844 m_freem(m); 845 txd->tx_addrlo = 0; 846 txd->tx_addrhi = 0; 847 ifp->if_opackets++; 848 } 849 } 850 ifp->if_flags &= ~IFF_OACTIVE; 851 852 if (++cons == TX_ENTRIES) { 853 txd = r->r_desc; 854 cons = 0; 855 sd = sc->sc_txd; 856 } else { 857 txd++; 858 sd++; 859 } 860 861 cnt--; 862 } 863 864 r->r_cons = cons; 865 r->r_cnt = cnt; 866 if (cnt == 0) 867 ifp->if_timer = 0; 868 } 869 870 int 871 txp_alloc_rings(struct txp_softc *sc) 872 { 873 struct ifnet *ifp = &sc->sc_arpcom.ac_if; 874 struct txp_boot_record *boot; 875 struct txp_swdesc *sd; 876 u_int32_t r; 877 int i, j; 878 879 /* boot record */ 880 if (txp_dma_malloc(sc, sizeof(struct txp_boot_record), &sc->sc_boot_dma, 881 BUS_DMA_COHERENT)) { 882 printf("can't allocate boot record\n"); 883 return (-1); 884 } 885 boot = (struct txp_boot_record *)sc->sc_boot_dma.dma_vaddr; 886 bzero(boot, sizeof(*boot)); 887 sc->sc_boot = boot; 888 889 /* host variables */ 890 if (txp_dma_malloc(sc, sizeof(struct txp_hostvar), &sc->sc_host_dma, 891 BUS_DMA_COHERENT)) { 892 printf("can't allocate host ring\n"); 893 goto bail_boot; 894 } 895 bzero(sc->sc_host_dma.dma_vaddr, sizeof(struct txp_hostvar)); 896 boot->br_hostvar_lo = htole32(sc->sc_host_dma.dma_paddr & 0xffffffff); 897 boot->br_hostvar_hi = htole32(sc->sc_host_dma.dma_paddr >> 32); 898 sc->sc_hostvar = (struct txp_hostvar *)sc->sc_host_dma.dma_vaddr; 899 900 /* high priority tx ring */ 901 if (txp_dma_malloc(sc, sizeof(struct txp_tx_desc) * TX_ENTRIES, 902 &sc->sc_txhiring_dma, BUS_DMA_COHERENT)) { 903 printf("can't allocate high tx ring\n"); 904 goto bail_host; 905 } 906 bzero(sc->sc_txhiring_dma.dma_vaddr, sizeof(struct txp_tx_desc) * TX_ENTRIES); 907 boot->br_txhipri_lo = htole32(sc->sc_txhiring_dma.dma_paddr & 0xffffffff); 908 boot->br_txhipri_hi = htole32(sc->sc_txhiring_dma.dma_paddr >> 32); 909 boot->br_txhipri_siz = htole32(TX_ENTRIES * sizeof(struct txp_tx_desc)); 910 sc->sc_txhir.r_reg = TXP_H2A_1; 911 sc->sc_txhir.r_desc = (struct txp_tx_desc *)sc->sc_txhiring_dma.dma_vaddr; 912 sc->sc_txhir.r_cons = sc->sc_txhir.r_prod = sc->sc_txhir.r_cnt = 0; 913 sc->sc_txhir.r_off = &sc->sc_hostvar->hv_tx_hi_desc_read_idx; 914 for (i = 0; i < TX_ENTRIES; i++) { 915 if (bus_dmamap_create(sc->sc_dmat, TXP_MAX_PKTLEN, 916 TX_ENTRIES - 4, TXP_MAX_SEGLEN, 0, 917 BUS_DMA_NOWAIT, &sc->sc_txd[i].sd_map) != 0) { 918 for (j = 0; j < i; j++) { 919 bus_dmamap_destroy(sc->sc_dmat, 920 sc->sc_txd[j].sd_map); 921 sc->sc_txd[j].sd_map = NULL; 922 } 923 goto bail_txhiring; 924 } 925 } 926 927 /* low priority tx ring */ 928 if (txp_dma_malloc(sc, sizeof(struct txp_tx_desc) * TX_ENTRIES, 929 &sc->sc_txloring_dma, BUS_DMA_COHERENT)) { 930 printf("can't allocate low tx ring\n"); 931 goto bail_txhiring; 932 } 933 bzero(sc->sc_txloring_dma.dma_vaddr, sizeof(struct txp_tx_desc) * TX_ENTRIES); 934 boot->br_txlopri_lo = htole32(sc->sc_txloring_dma.dma_paddr & 0xffffffff); 935 boot->br_txlopri_hi = htole32(sc->sc_txloring_dma.dma_paddr >> 32); 936 boot->br_txlopri_siz = htole32(TX_ENTRIES * sizeof(struct txp_tx_desc)); 937 sc->sc_txlor.r_reg = TXP_H2A_3; 938 sc->sc_txlor.r_desc = (struct txp_tx_desc *)sc->sc_txloring_dma.dma_vaddr; 939 sc->sc_txlor.r_cons = sc->sc_txlor.r_prod = sc->sc_txlor.r_cnt = 0; 940 sc->sc_txlor.r_off = &sc->sc_hostvar->hv_tx_lo_desc_read_idx; 941 942 /* high priority rx ring */ 943 if (txp_dma_malloc(sc, sizeof(struct txp_rx_desc) * RX_ENTRIES, 944 &sc->sc_rxhiring_dma, BUS_DMA_COHERENT)) { 945 printf("can't allocate high rx ring\n"); 946 goto bail_txloring; 947 } 948 bzero(sc->sc_rxhiring_dma.dma_vaddr, sizeof(struct txp_rx_desc) * RX_ENTRIES); 949 boot->br_rxhipri_lo = htole32(sc->sc_rxhiring_dma.dma_paddr & 0xffffffff); 950 boot->br_rxhipri_hi = htole32(sc->sc_rxhiring_dma.dma_paddr >> 32); 951 boot->br_rxhipri_siz = htole32(RX_ENTRIES * sizeof(struct txp_rx_desc)); 952 sc->sc_rxhir.r_desc = 953 (struct txp_rx_desc *)sc->sc_rxhiring_dma.dma_vaddr; 954 sc->sc_rxhir.r_roff = &sc->sc_hostvar->hv_rx_hi_read_idx; 955 sc->sc_rxhir.r_woff = &sc->sc_hostvar->hv_rx_hi_write_idx; 956 bus_dmamap_sync(sc->sc_dmat, sc->sc_rxhiring_dma.dma_map, 957 0, sc->sc_rxhiring_dma.dma_map->dm_mapsize, BUS_DMASYNC_PREREAD); 958 959 /* low priority ring */ 960 if (txp_dma_malloc(sc, sizeof(struct txp_rx_desc) * RX_ENTRIES, 961 &sc->sc_rxloring_dma, BUS_DMA_COHERENT)) { 962 printf("can't allocate low rx ring\n"); 963 goto bail_rxhiring; 964 } 965 bzero(sc->sc_rxloring_dma.dma_vaddr, sizeof(struct txp_rx_desc) * RX_ENTRIES); 966 boot->br_rxlopri_lo = htole32(sc->sc_rxloring_dma.dma_paddr & 0xffffffff); 967 boot->br_rxlopri_hi = htole32(sc->sc_rxloring_dma.dma_paddr >> 32); 968 boot->br_rxlopri_siz = htole32(RX_ENTRIES * sizeof(struct txp_rx_desc)); 969 sc->sc_rxlor.r_desc = 970 (struct txp_rx_desc *)sc->sc_rxloring_dma.dma_vaddr; 971 sc->sc_rxlor.r_roff = &sc->sc_hostvar->hv_rx_lo_read_idx; 972 sc->sc_rxlor.r_woff = &sc->sc_hostvar->hv_rx_lo_write_idx; 973 bus_dmamap_sync(sc->sc_dmat, sc->sc_rxloring_dma.dma_map, 974 0, sc->sc_rxloring_dma.dma_map->dm_mapsize, BUS_DMASYNC_PREREAD); 975 976 /* command ring */ 977 if (txp_dma_malloc(sc, sizeof(struct txp_cmd_desc) * CMD_ENTRIES, 978 &sc->sc_cmdring_dma, BUS_DMA_COHERENT)) { 979 printf("can't allocate command ring\n"); 980 goto bail_rxloring; 981 } 982 bzero(sc->sc_cmdring_dma.dma_vaddr, sizeof(struct txp_cmd_desc) * CMD_ENTRIES); 983 boot->br_cmd_lo = htole32(sc->sc_cmdring_dma.dma_paddr & 0xffffffff); 984 boot->br_cmd_hi = htole32(sc->sc_cmdring_dma.dma_paddr >> 32); 985 boot->br_cmd_siz = htole32(CMD_ENTRIES * sizeof(struct txp_cmd_desc)); 986 sc->sc_cmdring.base = (struct txp_cmd_desc *)sc->sc_cmdring_dma.dma_vaddr; 987 sc->sc_cmdring.size = CMD_ENTRIES * sizeof(struct txp_cmd_desc); 988 sc->sc_cmdring.lastwrite = 0; 989 990 /* response ring */ 991 if (txp_dma_malloc(sc, sizeof(struct txp_rsp_desc) * RSP_ENTRIES, 992 &sc->sc_rspring_dma, BUS_DMA_COHERENT)) { 993 printf("can't allocate response ring\n"); 994 goto bail_cmdring; 995 } 996 bzero(sc->sc_rspring_dma.dma_vaddr, sizeof(struct txp_rsp_desc) * RSP_ENTRIES); 997 boot->br_resp_lo = htole32(sc->sc_rspring_dma.dma_paddr & 0xffffffff); 998 boot->br_resp_hi = htole32(sc->sc_rspring_dma.dma_paddr >> 32); 999 boot->br_resp_siz = htole32(CMD_ENTRIES * sizeof(struct txp_rsp_desc)); 1000 sc->sc_rspring.base = (struct txp_rsp_desc *)sc->sc_rspring_dma.dma_vaddr; 1001 sc->sc_rspring.size = RSP_ENTRIES * sizeof(struct txp_rsp_desc); 1002 sc->sc_rspring.lastwrite = 0; 1003 1004 /* receive buffer ring */ 1005 if (txp_dma_malloc(sc, sizeof(struct txp_rxbuf_desc) * RXBUF_ENTRIES, 1006 &sc->sc_rxbufring_dma, BUS_DMA_COHERENT)) { 1007 printf("can't allocate rx buffer ring\n"); 1008 goto bail_rspring; 1009 } 1010 bzero(sc->sc_rxbufring_dma.dma_vaddr, sizeof(struct txp_rxbuf_desc) * RXBUF_ENTRIES); 1011 boot->br_rxbuf_lo = htole32(sc->sc_rxbufring_dma.dma_paddr & 0xffffffff); 1012 boot->br_rxbuf_hi = htole32(sc->sc_rxbufring_dma.dma_paddr >> 32); 1013 boot->br_rxbuf_siz = htole32(RXBUF_ENTRIES * sizeof(struct txp_rxbuf_desc)); 1014 sc->sc_rxbufs = (struct txp_rxbuf_desc *)sc->sc_rxbufring_dma.dma_vaddr; 1015 for (i = 0; i < RXBUF_ENTRIES; i++) { 1016 sd = (struct txp_swdesc *)malloc(sizeof(struct txp_swdesc), 1017 M_DEVBUF, M_NOWAIT); 1018 1019 /* stash away pointer */ 1020 bcopy(&sd, (u_long *)&sc->sc_rxbufs[i].rb_vaddrlo, sizeof(sd)); 1021 1022 if (sd == NULL) 1023 break; 1024 1025 MGETHDR(sd->sd_mbuf, M_DONTWAIT, MT_DATA); 1026 if (sd->sd_mbuf == NULL) { 1027 goto bail_rxbufring; 1028 } 1029 1030 MCLGET(sd->sd_mbuf, M_DONTWAIT); 1031 if ((sd->sd_mbuf->m_flags & M_EXT) == 0) { 1032 goto bail_rxbufring; 1033 } 1034 sd->sd_mbuf->m_pkthdr.len = sd->sd_mbuf->m_len = MCLBYTES; 1035 sd->sd_mbuf->m_pkthdr.rcvif = ifp; 1036 if (bus_dmamap_create(sc->sc_dmat, TXP_MAX_PKTLEN, 1, 1037 TXP_MAX_PKTLEN, 0, BUS_DMA_NOWAIT, &sd->sd_map)) { 1038 goto bail_rxbufring; 1039 } 1040 if (bus_dmamap_load_mbuf(sc->sc_dmat, sd->sd_map, sd->sd_mbuf, 1041 BUS_DMA_NOWAIT)) { 1042 bus_dmamap_destroy(sc->sc_dmat, sd->sd_map); 1043 goto bail_rxbufring; 1044 } 1045 bus_dmamap_sync(sc->sc_dmat, sd->sd_map, 0, 1046 sd->sd_map->dm_mapsize, BUS_DMASYNC_PREREAD); 1047 1048 sc->sc_rxbufs[i].rb_paddrlo = 1049 ((u_int64_t)sd->sd_map->dm_segs[0].ds_addr) & 0xffffffff; 1050 sc->sc_rxbufs[i].rb_paddrhi = 1051 ((u_int64_t)sd->sd_map->dm_segs[0].ds_addr) >> 32; 1052 } 1053 bus_dmamap_sync(sc->sc_dmat, sc->sc_rxbufring_dma.dma_map, 1054 0, sc->sc_rxbufring_dma.dma_map->dm_mapsize, 1055 BUS_DMASYNC_PREWRITE); 1056 sc->sc_hostvar->hv_rx_buf_write_idx = htole32((RXBUF_ENTRIES - 1) * 1057 sizeof(struct txp_rxbuf_desc)); 1058 1059 /* zero dma */ 1060 if (txp_dma_malloc(sc, sizeof(u_int32_t), &sc->sc_zero_dma, 1061 BUS_DMA_COHERENT)) { 1062 printf("can't allocate response ring\n"); 1063 goto bail_rxbufring; 1064 } 1065 bzero(sc->sc_zero_dma.dma_vaddr, sizeof(u_int32_t)); 1066 boot->br_zero_lo = htole32(sc->sc_zero_dma.dma_paddr & 0xffffffff); 1067 boot->br_zero_hi = htole32(sc->sc_zero_dma.dma_paddr >> 32); 1068 1069 /* See if it's waiting for boot, and try to boot it */ 1070 for (i = 0; i < 10000; i++) { 1071 r = READ_REG(sc, TXP_A2H_0); 1072 if (r == STAT_WAITING_FOR_BOOT) 1073 break; 1074 DELAY(50); 1075 } 1076 if (r != STAT_WAITING_FOR_BOOT) { 1077 printf("not waiting for boot\n"); 1078 goto bail; 1079 } 1080 WRITE_REG(sc, TXP_H2A_2, sc->sc_boot_dma.dma_paddr >> 32); 1081 WRITE_REG(sc, TXP_H2A_1, sc->sc_boot_dma.dma_paddr & 0xffffffff); 1082 WRITE_REG(sc, TXP_H2A_0, TXP_BOOTCMD_REGISTER_BOOT_RECORD); 1083 1084 /* See if it booted */ 1085 for (i = 0; i < 10000; i++) { 1086 r = READ_REG(sc, TXP_A2H_0); 1087 if (r == STAT_RUNNING) 1088 break; 1089 DELAY(50); 1090 } 1091 if (r != STAT_RUNNING) { 1092 printf("fw not running\n"); 1093 goto bail; 1094 } 1095 1096 /* Clear TX and CMD ring write registers */ 1097 WRITE_REG(sc, TXP_H2A_1, TXP_BOOTCMD_NULL); 1098 WRITE_REG(sc, TXP_H2A_2, TXP_BOOTCMD_NULL); 1099 WRITE_REG(sc, TXP_H2A_3, TXP_BOOTCMD_NULL); 1100 WRITE_REG(sc, TXP_H2A_0, TXP_BOOTCMD_NULL); 1101 1102 return (0); 1103 1104 bail: 1105 txp_dma_free(sc, &sc->sc_zero_dma); 1106 bail_rxbufring: 1107 for (i = 0; i < RXBUF_ENTRIES; i++) { 1108 bcopy((u_long *)&sc->sc_rxbufs[i].rb_vaddrlo, &sd, sizeof(sd)); 1109 if (sd) 1110 free(sd, M_DEVBUF); 1111 } 1112 txp_dma_free(sc, &sc->sc_rxbufring_dma); 1113 bail_rspring: 1114 txp_dma_free(sc, &sc->sc_rspring_dma); 1115 bail_cmdring: 1116 txp_dma_free(sc, &sc->sc_cmdring_dma); 1117 bail_rxloring: 1118 txp_dma_free(sc, &sc->sc_rxloring_dma); 1119 bail_rxhiring: 1120 txp_dma_free(sc, &sc->sc_rxhiring_dma); 1121 bail_txloring: 1122 txp_dma_free(sc, &sc->sc_txloring_dma); 1123 bail_txhiring: 1124 txp_dma_free(sc, &sc->sc_txhiring_dma); 1125 bail_host: 1126 txp_dma_free(sc, &sc->sc_host_dma); 1127 bail_boot: 1128 txp_dma_free(sc, &sc->sc_boot_dma); 1129 return (-1); 1130 } 1131 1132 int 1133 txp_dma_malloc(struct txp_softc *sc, bus_size_t size, 1134 struct txp_dma_alloc *dma, int mapflags) 1135 { 1136 int r; 1137 1138 if ((r = bus_dmamem_alloc(sc->sc_dmat, size, PAGE_SIZE, 0, 1139 &dma->dma_seg, 1, &dma->dma_nseg, 0)) != 0) 1140 goto fail_0; 1141 1142 if ((r = bus_dmamem_map(sc->sc_dmat, &dma->dma_seg, dma->dma_nseg, 1143 size, &dma->dma_vaddr, mapflags | BUS_DMA_NOWAIT)) != 0) 1144 goto fail_1; 1145 1146 if ((r = bus_dmamap_create(sc->sc_dmat, size, 1, size, 0, 1147 BUS_DMA_NOWAIT, &dma->dma_map)) != 0) 1148 goto fail_2; 1149 1150 if ((r = bus_dmamap_load(sc->sc_dmat, dma->dma_map, dma->dma_vaddr, 1151 size, NULL, BUS_DMA_NOWAIT)) != 0) 1152 goto fail_3; 1153 1154 dma->dma_paddr = dma->dma_map->dm_segs[0].ds_addr; 1155 return (0); 1156 1157 fail_3: 1158 bus_dmamap_destroy(sc->sc_dmat, dma->dma_map); 1159 fail_2: 1160 bus_dmamem_unmap(sc->sc_dmat, dma->dma_vaddr, size); 1161 fail_1: 1162 bus_dmamem_free(sc->sc_dmat, &dma->dma_seg, dma->dma_nseg); 1163 fail_0: 1164 return (r); 1165 } 1166 1167 void 1168 txp_dma_free(struct txp_softc *sc, struct txp_dma_alloc *dma) 1169 { 1170 bus_dmamap_unload(sc->sc_dmat, dma->dma_map); 1171 bus_dmamem_unmap(sc->sc_dmat, dma->dma_vaddr, dma->dma_map->dm_mapsize); 1172 bus_dmamem_free(sc->sc_dmat, &dma->dma_seg, dma->dma_nseg); 1173 bus_dmamap_destroy(sc->sc_dmat, dma->dma_map); 1174 } 1175 1176 int 1177 txp_ioctl(struct ifnet *ifp, u_long command, caddr_t data) 1178 { 1179 struct txp_softc *sc = ifp->if_softc; 1180 struct ifaddr *ifa = (struct ifaddr *) data; 1181 struct ifreq *ifr = (struct ifreq *) data; 1182 int s, error = 0; 1183 1184 s = splnet(); 1185 1186 switch(command) { 1187 case SIOCSIFADDR: 1188 ifp->if_flags |= IFF_UP; 1189 switch (ifa->ifa_addr->sa_family) { 1190 #ifdef INET 1191 case AF_INET: 1192 txp_init(sc); 1193 arp_ifinit(&sc->sc_arpcom, ifa); 1194 break; 1195 #endif /* INET */ 1196 default: 1197 txp_init(sc); 1198 break; 1199 } 1200 break; 1201 1202 case SIOCSIFFLAGS: 1203 if (ifp->if_flags & IFF_UP) { 1204 txp_init(sc); 1205 } else { 1206 if (ifp->if_flags & IFF_RUNNING) 1207 txp_stop(sc); 1208 } 1209 break; 1210 1211 case SIOCGIFMEDIA: 1212 case SIOCSIFMEDIA: 1213 error = ifmedia_ioctl(ifp, ifr, &sc->sc_ifmedia, command); 1214 break; 1215 1216 default: 1217 error = ether_ioctl(ifp, &sc->sc_arpcom, command, data); 1218 } 1219 1220 if (error == ENETRESET) { 1221 if (ifp->if_flags & IFF_RUNNING) 1222 txp_set_filter(sc); 1223 error = 0; 1224 } 1225 1226 splx(s); 1227 return(error); 1228 } 1229 1230 void 1231 txp_init(struct txp_softc *sc) 1232 { 1233 struct ifnet *ifp = &sc->sc_arpcom.ac_if; 1234 int s; 1235 1236 txp_stop(sc); 1237 1238 s = splnet(); 1239 1240 txp_set_filter(sc); 1241 1242 txp_command(sc, TXP_CMD_TX_ENABLE, 0, 0, 0, NULL, NULL, NULL, 1); 1243 txp_command(sc, TXP_CMD_RX_ENABLE, 0, 0, 0, NULL, NULL, NULL, 1); 1244 1245 WRITE_REG(sc, TXP_IER, TXP_INT_RESERVED | TXP_INT_SELF | 1246 TXP_INT_A2H_7 | TXP_INT_A2H_6 | TXP_INT_A2H_5 | TXP_INT_A2H_4 | 1247 TXP_INT_A2H_2 | TXP_INT_A2H_1 | TXP_INT_A2H_0 | 1248 TXP_INT_DMA3 | TXP_INT_DMA2 | TXP_INT_DMA1 | TXP_INT_DMA0 | 1249 TXP_INT_PCI_TABORT | TXP_INT_PCI_MABORT | TXP_INT_LATCH); 1250 WRITE_REG(sc, TXP_IMR, TXP_INT_A2H_3); 1251 1252 ifp->if_flags |= IFF_RUNNING; 1253 ifp->if_flags &= ~IFF_OACTIVE; 1254 1255 if (!timeout_pending(&sc->sc_tick)) 1256 timeout_add_sec(&sc->sc_tick, 1); 1257 1258 splx(s); 1259 } 1260 1261 void 1262 txp_tick(void *vsc) 1263 { 1264 struct txp_softc *sc = vsc; 1265 struct ifnet *ifp = &sc->sc_arpcom.ac_if; 1266 struct txp_rsp_desc *rsp = NULL; 1267 struct txp_ext_desc *ext; 1268 int s; 1269 1270 s = splnet(); 1271 txp_rxbuf_reclaim(sc); 1272 1273 if (txp_command2(sc, TXP_CMD_READ_STATISTICS, 0, 0, 0, NULL, 0, 1274 &rsp, 1)) 1275 goto out; 1276 if (rsp->rsp_numdesc != 6) 1277 goto out; 1278 if (txp_command(sc, TXP_CMD_CLEAR_STATISTICS, 0, 0, 0, 1279 NULL, NULL, NULL, 1)) 1280 goto out; 1281 ext = (struct txp_ext_desc *)(rsp + 1); 1282 1283 ifp->if_ierrors += ext[3].ext_2 + ext[3].ext_3 + ext[3].ext_4 + 1284 ext[4].ext_1 + ext[4].ext_4; 1285 ifp->if_oerrors += ext[0].ext_1 + ext[1].ext_1 + ext[1].ext_4 + 1286 ext[2].ext_1; 1287 ifp->if_collisions += ext[0].ext_2 + ext[0].ext_3 + ext[1].ext_2 + 1288 ext[1].ext_3; 1289 ifp->if_opackets += rsp->rsp_par2; 1290 ifp->if_ipackets += ext[2].ext_3; 1291 1292 out: 1293 if (rsp != NULL) 1294 free(rsp, M_DEVBUF); 1295 1296 splx(s); 1297 timeout_add_sec(&sc->sc_tick, 1); 1298 } 1299 1300 void 1301 txp_start(struct ifnet *ifp) 1302 { 1303 struct txp_softc *sc = ifp->if_softc; 1304 struct txp_tx_ring *r = &sc->sc_txhir; 1305 struct txp_tx_desc *txd; 1306 int txdidx; 1307 struct txp_frag_desc *fxd; 1308 struct mbuf *m, *mnew; 1309 struct txp_swdesc *sd; 1310 u_int32_t firstprod, firstcnt, prod, cnt, i; 1311 1312 if ((ifp->if_flags & (IFF_RUNNING | IFF_OACTIVE)) != IFF_RUNNING) 1313 return; 1314 1315 prod = r->r_prod; 1316 cnt = r->r_cnt; 1317 1318 while (1) { 1319 IFQ_POLL(&ifp->if_snd, m); 1320 if (m == NULL) 1321 break; 1322 mnew = NULL; 1323 1324 firstprod = prod; 1325 firstcnt = cnt; 1326 1327 sd = sc->sc_txd + prod; 1328 sd->sd_mbuf = m; 1329 1330 if (bus_dmamap_load_mbuf(sc->sc_dmat, sd->sd_map, m, 1331 BUS_DMA_NOWAIT)) { 1332 MGETHDR(mnew, M_DONTWAIT, MT_DATA); 1333 if (mnew == NULL) 1334 goto oactive1; 1335 if (m->m_pkthdr.len > MHLEN) { 1336 MCLGET(mnew, M_DONTWAIT); 1337 if ((mnew->m_flags & M_EXT) == 0) { 1338 m_freem(mnew); 1339 goto oactive1; 1340 } 1341 } 1342 m_copydata(m, 0, m->m_pkthdr.len, mtod(mnew, caddr_t)); 1343 mnew->m_pkthdr.len = mnew->m_len = m->m_pkthdr.len; 1344 IFQ_DEQUEUE(&ifp->if_snd, m); 1345 m_freem(m); 1346 m = mnew; 1347 if (bus_dmamap_load_mbuf(sc->sc_dmat, sd->sd_map, m, 1348 BUS_DMA_NOWAIT)) 1349 goto oactive1; 1350 } 1351 1352 if ((TX_ENTRIES - cnt) < 4) 1353 goto oactive; 1354 1355 txd = r->r_desc + prod; 1356 txdidx = prod; 1357 txd->tx_flags = TX_FLAGS_TYPE_DATA; 1358 txd->tx_numdesc = 0; 1359 txd->tx_addrlo = 0; 1360 txd->tx_addrhi = 0; 1361 txd->tx_totlen = m->m_pkthdr.len; 1362 txd->tx_pflags = 0; 1363 txd->tx_numdesc = sd->sd_map->dm_nsegs; 1364 1365 if (++prod == TX_ENTRIES) 1366 prod = 0; 1367 1368 if (++cnt >= (TX_ENTRIES - 4)) 1369 goto oactive; 1370 1371 #if NVLAN > 0 1372 if (m->m_flags & M_VLANTAG) { 1373 txd->tx_pflags = TX_PFLAGS_VLAN | 1374 (htons(m->m_pkthdr.ether_vtag) << TX_PFLAGS_VLANTAG_S); 1375 } 1376 #endif 1377 1378 if (m->m_pkthdr.csum_flags & M_IPV4_CSUM_OUT) 1379 txd->tx_pflags |= TX_PFLAGS_IPCKSUM; 1380 #ifdef TRY_TX_TCP_CSUM 1381 if (m->m_pkthdr.csum_flags & M_TCP_CSUM_OUT) 1382 txd->tx_pflags |= TX_PFLAGS_TCPCKSUM; 1383 #endif 1384 #ifdef TRY_TX_UDP_CSUM 1385 if (m->m_pkthdr.csum_flags & M_UDP_CSUM_OUT) 1386 txd->tx_pflags |= TX_PFLAGS_UDPCKSUM; 1387 #endif 1388 1389 bus_dmamap_sync(sc->sc_dmat, sd->sd_map, 0, 1390 sd->sd_map->dm_mapsize, BUS_DMASYNC_PREWRITE); 1391 1392 fxd = (struct txp_frag_desc *)(r->r_desc + prod); 1393 for (i = 0; i < sd->sd_map->dm_nsegs; i++) { 1394 if (++cnt >= (TX_ENTRIES - 4)) { 1395 bus_dmamap_sync(sc->sc_dmat, sd->sd_map, 1396 0, sd->sd_map->dm_mapsize, 1397 BUS_DMASYNC_POSTWRITE); 1398 goto oactive; 1399 } 1400 1401 fxd->frag_flags = FRAG_FLAGS_TYPE_FRAG | 1402 FRAG_FLAGS_VALID; 1403 fxd->frag_rsvd1 = 0; 1404 fxd->frag_len = sd->sd_map->dm_segs[i].ds_len; 1405 fxd->frag_addrlo = 1406 ((u_int64_t)sd->sd_map->dm_segs[i].ds_addr) & 1407 0xffffffff; 1408 fxd->frag_addrhi = 1409 ((u_int64_t)sd->sd_map->dm_segs[i].ds_addr) >> 1410 32; 1411 fxd->frag_rsvd2 = 0; 1412 1413 bus_dmamap_sync(sc->sc_dmat, 1414 sc->sc_txhiring_dma.dma_map, 1415 prod * sizeof(struct txp_frag_desc), 1416 sizeof(struct txp_frag_desc), BUS_DMASYNC_PREWRITE); 1417 1418 if (++prod == TX_ENTRIES) { 1419 fxd = (struct txp_frag_desc *)r->r_desc; 1420 prod = 0; 1421 } else 1422 fxd++; 1423 1424 } 1425 1426 /* 1427 * if mnew isn't NULL, we already dequeued and copied 1428 * the packet. 1429 */ 1430 if (mnew == NULL) 1431 IFQ_DEQUEUE(&ifp->if_snd, m); 1432 1433 ifp->if_timer = 5; 1434 1435 #if NBPFILTER > 0 1436 if (ifp->if_bpf) 1437 bpf_mtap_ether(ifp->if_bpf, m, BPF_DIRECTION_OUT); 1438 #endif 1439 1440 txd->tx_flags |= TX_FLAGS_VALID; 1441 bus_dmamap_sync(sc->sc_dmat, sc->sc_txhiring_dma.dma_map, 1442 txdidx * sizeof(struct txp_tx_desc), 1443 sizeof(struct txp_tx_desc), BUS_DMASYNC_PREWRITE); 1444 1445 #if 0 1446 { 1447 struct mbuf *mx; 1448 int i; 1449 1450 printf("txd: flags 0x%x ndesc %d totlen %d pflags 0x%x\n", 1451 txd->tx_flags, txd->tx_numdesc, txd->tx_totlen, 1452 txd->tx_pflags); 1453 for (mx = m; mx != NULL; mx = mx->m_next) { 1454 for (i = 0; i < mx->m_len; i++) { 1455 printf(":%02x", 1456 (u_int8_t)m->m_data[i]); 1457 } 1458 } 1459 printf("\n"); 1460 } 1461 #endif 1462 1463 WRITE_REG(sc, r->r_reg, TXP_IDX2OFFSET(prod)); 1464 } 1465 1466 r->r_prod = prod; 1467 r->r_cnt = cnt; 1468 return; 1469 1470 oactive: 1471 bus_dmamap_unload(sc->sc_dmat, sd->sd_map); 1472 oactive1: 1473 ifp->if_flags |= IFF_OACTIVE; 1474 r->r_prod = firstprod; 1475 r->r_cnt = firstcnt; 1476 } 1477 1478 /* 1479 * Handle simple commands sent to the typhoon 1480 */ 1481 int 1482 txp_command(struct txp_softc *sc, u_int16_t id, u_int16_t in1, 1483 u_int32_t in2, u_int32_t in3, u_int16_t *out1, u_int32_t *out2, 1484 u_int32_t *out3, int wait) 1485 { 1486 struct txp_rsp_desc *rsp = NULL; 1487 1488 if (txp_command2(sc, id, in1, in2, in3, NULL, 0, &rsp, wait)) 1489 return (-1); 1490 1491 if (!wait) 1492 return (0); 1493 1494 if (out1 != NULL) 1495 *out1 = letoh16(rsp->rsp_par1); 1496 if (out2 != NULL) 1497 *out2 = letoh32(rsp->rsp_par2); 1498 if (out3 != NULL) 1499 *out3 = letoh32(rsp->rsp_par3); 1500 free(rsp, M_DEVBUF); 1501 return (0); 1502 } 1503 1504 int 1505 txp_command2(struct txp_softc *sc, u_int16_t id, u_int16_t in1, 1506 u_int32_t in2, u_int32_t in3, struct txp_ext_desc *in_extp, 1507 u_int8_t in_extn,struct txp_rsp_desc **rspp, int wait) 1508 { 1509 struct txp_hostvar *hv = sc->sc_hostvar; 1510 struct txp_cmd_desc *cmd; 1511 struct txp_ext_desc *ext; 1512 u_int32_t idx, i; 1513 u_int16_t seq; 1514 1515 if (txp_cmd_desc_numfree(sc) < (in_extn + 1)) { 1516 printf("%s: no free cmd descriptors\n", TXP_DEVNAME(sc)); 1517 return (-1); 1518 } 1519 1520 idx = sc->sc_cmdring.lastwrite; 1521 cmd = (struct txp_cmd_desc *)(((u_int8_t *)sc->sc_cmdring.base) + idx); 1522 bzero(cmd, sizeof(*cmd)); 1523 1524 cmd->cmd_numdesc = in_extn; 1525 seq = sc->sc_seq++; 1526 cmd->cmd_seq = htole16(seq); 1527 cmd->cmd_id = htole16(id); 1528 cmd->cmd_par1 = htole16(in1); 1529 cmd->cmd_par2 = htole32(in2); 1530 cmd->cmd_par3 = htole32(in3); 1531 cmd->cmd_flags = CMD_FLAGS_TYPE_CMD | 1532 (wait ? CMD_FLAGS_RESP : 0) | CMD_FLAGS_VALID; 1533 1534 idx += sizeof(struct txp_cmd_desc); 1535 if (idx == sc->sc_cmdring.size) 1536 idx = 0; 1537 1538 for (i = 0; i < in_extn; i++) { 1539 ext = (struct txp_ext_desc *)(((u_int8_t *)sc->sc_cmdring.base) + idx); 1540 bcopy(in_extp, ext, sizeof(struct txp_ext_desc)); 1541 in_extp++; 1542 idx += sizeof(struct txp_cmd_desc); 1543 if (idx == sc->sc_cmdring.size) 1544 idx = 0; 1545 } 1546 1547 sc->sc_cmdring.lastwrite = idx; 1548 1549 WRITE_REG(sc, TXP_H2A_2, sc->sc_cmdring.lastwrite); 1550 bus_dmamap_sync(sc->sc_dmat, sc->sc_host_dma.dma_map, 0, 1551 sizeof(struct txp_hostvar), BUS_DMASYNC_PREREAD); 1552 1553 if (!wait) 1554 return (0); 1555 1556 for (i = 0; i < 10000; i++) { 1557 bus_dmamap_sync(sc->sc_dmat, sc->sc_host_dma.dma_map, 0, 1558 sizeof(struct txp_hostvar), BUS_DMASYNC_POSTREAD); 1559 idx = letoh32(hv->hv_resp_read_idx); 1560 if (idx != letoh32(hv->hv_resp_write_idx)) { 1561 *rspp = NULL; 1562 if (txp_response(sc, idx, id, seq, rspp)) 1563 return (-1); 1564 if (*rspp != NULL) 1565 break; 1566 } 1567 bus_dmamap_sync(sc->sc_dmat, sc->sc_host_dma.dma_map, 0, 1568 sizeof(struct txp_hostvar), BUS_DMASYNC_PREREAD); 1569 DELAY(50); 1570 } 1571 if (i == 1000 || (*rspp) == NULL) { 1572 printf("%s: 0x%x command failed\n", TXP_DEVNAME(sc), id); 1573 return (-1); 1574 } 1575 1576 return (0); 1577 } 1578 1579 int 1580 txp_response(struct txp_softc *sc, u_int32_t ridx, u_int16_t id, 1581 u_int16_t seq, struct txp_rsp_desc **rspp) 1582 { 1583 struct txp_hostvar *hv = sc->sc_hostvar; 1584 struct txp_rsp_desc *rsp; 1585 1586 while (ridx != letoh32(hv->hv_resp_write_idx)) { 1587 rsp = (struct txp_rsp_desc *)(((u_int8_t *)sc->sc_rspring.base) + ridx); 1588 1589 if (id == letoh16(rsp->rsp_id) && letoh16(rsp->rsp_seq) == seq) { 1590 *rspp = (struct txp_rsp_desc *)malloc( 1591 sizeof(struct txp_rsp_desc) * (rsp->rsp_numdesc + 1), 1592 M_DEVBUF, M_NOWAIT); 1593 if ((*rspp) == NULL) 1594 return (-1); 1595 txp_rsp_fixup(sc, rsp, *rspp); 1596 return (0); 1597 } 1598 1599 if (rsp->rsp_flags & RSP_FLAGS_ERROR) { 1600 printf("%s: response error: id 0x%x\n", 1601 TXP_DEVNAME(sc), letoh16(rsp->rsp_id)); 1602 txp_rsp_fixup(sc, rsp, NULL); 1603 ridx = letoh32(hv->hv_resp_read_idx); 1604 continue; 1605 } 1606 1607 switch (letoh16(rsp->rsp_id)) { 1608 case TXP_CMD_CYCLE_STATISTICS: 1609 case TXP_CMD_MEDIA_STATUS_READ: 1610 break; 1611 case TXP_CMD_HELLO_RESPONSE: 1612 printf("%s: hello\n", TXP_DEVNAME(sc)); 1613 break; 1614 default: 1615 printf("%s: unknown id(0x%x)\n", TXP_DEVNAME(sc), 1616 letoh16(rsp->rsp_id)); 1617 } 1618 1619 txp_rsp_fixup(sc, rsp, NULL); 1620 ridx = letoh32(hv->hv_resp_read_idx); 1621 hv->hv_resp_read_idx = letoh32(ridx); 1622 } 1623 1624 return (0); 1625 } 1626 1627 void 1628 txp_rsp_fixup(struct txp_softc *sc, struct txp_rsp_desc *rsp, 1629 struct txp_rsp_desc *dst) 1630 { 1631 struct txp_rsp_desc *src = rsp; 1632 struct txp_hostvar *hv = sc->sc_hostvar; 1633 u_int32_t i, ridx; 1634 1635 ridx = letoh32(hv->hv_resp_read_idx); 1636 1637 for (i = 0; i < rsp->rsp_numdesc + 1; i++) { 1638 if (dst != NULL) 1639 bcopy(src, dst++, sizeof(struct txp_rsp_desc)); 1640 ridx += sizeof(struct txp_rsp_desc); 1641 if (ridx == sc->sc_rspring.size) { 1642 src = sc->sc_rspring.base; 1643 ridx = 0; 1644 } else 1645 src++; 1646 sc->sc_rspring.lastwrite = ridx; 1647 hv->hv_resp_read_idx = htole32(ridx); 1648 } 1649 1650 hv->hv_resp_read_idx = htole32(ridx); 1651 } 1652 1653 int 1654 txp_cmd_desc_numfree(struct txp_softc *sc) 1655 { 1656 struct txp_hostvar *hv = sc->sc_hostvar; 1657 struct txp_boot_record *br = sc->sc_boot; 1658 u_int32_t widx, ridx, nfree; 1659 1660 widx = sc->sc_cmdring.lastwrite; 1661 ridx = letoh32(hv->hv_cmd_read_idx); 1662 1663 if (widx == ridx) { 1664 /* Ring is completely free */ 1665 nfree = letoh32(br->br_cmd_siz) - sizeof(struct txp_cmd_desc); 1666 } else { 1667 if (widx > ridx) 1668 nfree = letoh32(br->br_cmd_siz) - 1669 (widx - ridx + sizeof(struct txp_cmd_desc)); 1670 else 1671 nfree = ridx - widx - sizeof(struct txp_cmd_desc); 1672 } 1673 1674 return (nfree / sizeof(struct txp_cmd_desc)); 1675 } 1676 1677 void 1678 txp_stop(struct txp_softc *sc) 1679 { 1680 struct ifnet *ifp = &sc->sc_arpcom.ac_if; 1681 1682 timeout_del(&sc->sc_tick); 1683 1684 /* Mark the interface as down and cancel the watchdog timer. */ 1685 ifp->if_flags &= ~(IFF_RUNNING | IFF_OACTIVE); 1686 ifp->if_timer = 0; 1687 1688 txp_command(sc, TXP_CMD_TX_DISABLE, 0, 0, 0, NULL, NULL, NULL, 1); 1689 txp_command(sc, TXP_CMD_RX_DISABLE, 0, 0, 0, NULL, NULL, NULL, 1); 1690 } 1691 1692 void 1693 txp_watchdog(struct ifnet *ifp) 1694 { 1695 } 1696 1697 int 1698 txp_ifmedia_upd(struct ifnet *ifp) 1699 { 1700 struct txp_softc *sc = ifp->if_softc; 1701 struct ifmedia *ifm = &sc->sc_ifmedia; 1702 u_int16_t new_xcvr; 1703 1704 if (IFM_TYPE(ifm->ifm_media) != IFM_ETHER) 1705 return (EINVAL); 1706 1707 if (IFM_SUBTYPE(ifm->ifm_media) == IFM_10_T) { 1708 if ((ifm->ifm_media & IFM_GMASK) == IFM_FDX) 1709 new_xcvr = TXP_XCVR_10_FDX; 1710 else 1711 new_xcvr = TXP_XCVR_10_HDX; 1712 } else if (IFM_SUBTYPE(ifm->ifm_media) == IFM_100_TX) { 1713 if ((ifm->ifm_media & IFM_GMASK) == IFM_FDX) 1714 new_xcvr = TXP_XCVR_100_FDX; 1715 else 1716 new_xcvr = TXP_XCVR_100_HDX; 1717 } else if (IFM_SUBTYPE(ifm->ifm_media) == IFM_AUTO) { 1718 new_xcvr = TXP_XCVR_AUTO; 1719 } else 1720 return (EINVAL); 1721 1722 /* nothing to do */ 1723 if (sc->sc_xcvr == new_xcvr) 1724 return (0); 1725 1726 txp_command(sc, TXP_CMD_XCVR_SELECT, new_xcvr, 0, 0, 1727 NULL, NULL, NULL, 0); 1728 sc->sc_xcvr = new_xcvr; 1729 1730 return (0); 1731 } 1732 1733 void 1734 txp_ifmedia_sts(struct ifnet *ifp, struct ifmediareq *ifmr) 1735 { 1736 struct txp_softc *sc = ifp->if_softc; 1737 struct ifmedia *ifm = &sc->sc_ifmedia; 1738 u_int16_t bmsr, bmcr, anar, anlpar; 1739 1740 ifmr->ifm_status = IFM_AVALID; 1741 ifmr->ifm_active = IFM_ETHER; 1742 1743 if (txp_command(sc, TXP_CMD_PHY_MGMT_READ, 0, MII_BMSR, 0, 1744 &bmsr, NULL, NULL, 1)) 1745 goto bail; 1746 if (txp_command(sc, TXP_CMD_PHY_MGMT_READ, 0, MII_BMSR, 0, 1747 &bmsr, NULL, NULL, 1)) 1748 goto bail; 1749 1750 if (txp_command(sc, TXP_CMD_PHY_MGMT_READ, 0, MII_BMCR, 0, 1751 &bmcr, NULL, NULL, 1)) 1752 goto bail; 1753 1754 if (txp_command(sc, TXP_CMD_PHY_MGMT_READ, 0, MII_ANAR, 0, 1755 &anar, NULL, NULL, 1)) 1756 goto bail; 1757 1758 if (txp_command(sc, TXP_CMD_PHY_MGMT_READ, 0, MII_ANLPAR, 0, 1759 &anlpar, NULL, NULL, 1)) 1760 goto bail; 1761 1762 if (bmsr & BMSR_LINK) 1763 ifmr->ifm_status |= IFM_ACTIVE; 1764 1765 if (bmcr & BMCR_ISO) { 1766 ifmr->ifm_active |= IFM_NONE; 1767 ifmr->ifm_status = 0; 1768 return; 1769 } 1770 1771 if (bmcr & BMCR_LOOP) 1772 ifmr->ifm_active |= IFM_LOOP; 1773 1774 if (bmcr & BMCR_AUTOEN) { 1775 if ((bmsr & BMSR_ACOMP) == 0) { 1776 ifmr->ifm_active |= IFM_NONE; 1777 return; 1778 } 1779 1780 anlpar &= anar; 1781 if (anlpar & ANLPAR_TX_FD) 1782 ifmr->ifm_active |= IFM_100_TX|IFM_FDX; 1783 else if (anlpar & ANLPAR_T4) 1784 ifmr->ifm_active |= IFM_100_T4|IFM_HDX; 1785 else if (anlpar & ANLPAR_TX) 1786 ifmr->ifm_active |= IFM_100_TX|IFM_HDX; 1787 else if (anlpar & ANLPAR_10_FD) 1788 ifmr->ifm_active |= IFM_10_T|IFM_FDX; 1789 else if (anlpar & ANLPAR_10) 1790 ifmr->ifm_active |= IFM_10_T|IFM_HDX; 1791 else 1792 ifmr->ifm_active |= IFM_NONE; 1793 } else 1794 ifmr->ifm_active = ifm->ifm_cur->ifm_media; 1795 return; 1796 1797 bail: 1798 ifmr->ifm_active |= IFM_NONE; 1799 ifmr->ifm_status &= ~IFM_AVALID; 1800 } 1801 1802 void 1803 txp_show_descriptor(void *d) 1804 { 1805 struct txp_cmd_desc *cmd = d; 1806 struct txp_rsp_desc *rsp = d; 1807 struct txp_tx_desc *txd = d; 1808 struct txp_frag_desc *frgd = d; 1809 1810 switch (cmd->cmd_flags & CMD_FLAGS_TYPE_M) { 1811 case CMD_FLAGS_TYPE_CMD: 1812 /* command descriptor */ 1813 printf("[cmd flags 0x%x num %d id %d seq %d par1 0x%x par2 0x%x par3 0x%x]\n", 1814 cmd->cmd_flags, cmd->cmd_numdesc, letoh16(cmd->cmd_id), 1815 letoh16(cmd->cmd_seq), letoh16(cmd->cmd_par1), 1816 letoh32(cmd->cmd_par2), letoh32(cmd->cmd_par3)); 1817 break; 1818 case CMD_FLAGS_TYPE_RESP: 1819 /* response descriptor */ 1820 printf("[rsp flags 0x%x num %d id %d seq %d par1 0x%x par2 0x%x par3 0x%x]\n", 1821 rsp->rsp_flags, rsp->rsp_numdesc, letoh16(rsp->rsp_id), 1822 letoh16(rsp->rsp_seq), letoh16(rsp->rsp_par1), 1823 letoh32(rsp->rsp_par2), letoh32(rsp->rsp_par3)); 1824 break; 1825 case CMD_FLAGS_TYPE_DATA: 1826 /* data header (assuming tx for now) */ 1827 printf("[data flags 0x%x num %d totlen %d addr 0x%x/0x%x pflags 0x%x]", 1828 txd->tx_flags, txd->tx_numdesc, txd->tx_totlen, 1829 txd->tx_addrlo, txd->tx_addrhi, txd->tx_pflags); 1830 break; 1831 case CMD_FLAGS_TYPE_FRAG: 1832 /* fragment descriptor */ 1833 printf("[frag flags 0x%x rsvd1 0x%x len %d addr 0x%x/0x%x rsvd2 0x%x]", 1834 frgd->frag_flags, frgd->frag_rsvd1, frgd->frag_len, 1835 frgd->frag_addrlo, frgd->frag_addrhi, frgd->frag_rsvd2); 1836 break; 1837 default: 1838 printf("[unknown(%x) flags 0x%x num %d id %d seq %d par1 0x%x par2 0x%x par3 0x%x]\n", 1839 cmd->cmd_flags & CMD_FLAGS_TYPE_M, 1840 cmd->cmd_flags, cmd->cmd_numdesc, letoh16(cmd->cmd_id), 1841 letoh16(cmd->cmd_seq), letoh16(cmd->cmd_par1), 1842 letoh32(cmd->cmd_par2), letoh32(cmd->cmd_par3)); 1843 break; 1844 } 1845 } 1846 1847 void 1848 txp_set_filter(struct txp_softc *sc) 1849 { 1850 struct arpcom *ac = &sc->sc_arpcom; 1851 struct ifnet *ifp = &sc->sc_arpcom.ac_if; 1852 u_int32_t hashbit, hash[2]; 1853 u_int16_t filter; 1854 int mcnt = 0; 1855 struct ether_multi *enm; 1856 struct ether_multistep step; 1857 1858 if (ifp->if_flags & IFF_PROMISC) { 1859 filter = TXP_RXFILT_PROMISC; 1860 goto setit; 1861 } 1862 1863 again: 1864 filter = TXP_RXFILT_DIRECT; 1865 1866 if (ifp->if_flags & IFF_BROADCAST) 1867 filter |= TXP_RXFILT_BROADCAST; 1868 1869 if (ifp->if_flags & IFF_ALLMULTI) 1870 filter |= TXP_RXFILT_ALLMULTI; 1871 else { 1872 hash[0] = hash[1] = 0; 1873 1874 ETHER_FIRST_MULTI(step, ac, enm); 1875 while (enm != NULL) { 1876 if (bcmp(enm->enm_addrlo, enm->enm_addrhi, ETHER_ADDR_LEN)) { 1877 /* 1878 * We must listen to a range of multicast 1879 * addresses. For now, just accept all 1880 * multicasts, rather than trying to set only 1881 * those filter bits needed to match the range. 1882 * (At this time, the only use of address 1883 * ranges is for IP multicast routing, for 1884 * which the range is big enough to require 1885 * all bits set.) 1886 */ 1887 ifp->if_flags |= IFF_ALLMULTI; 1888 goto again; 1889 } 1890 1891 mcnt++; 1892 hashbit = (u_int16_t)(ether_crc32_be(enm->enm_addrlo, 1893 ETHER_ADDR_LEN) & (64 - 1)); 1894 hash[hashbit / 32] |= (1 << hashbit % 32); 1895 ETHER_NEXT_MULTI(step, enm); 1896 } 1897 1898 if (mcnt > 0) { 1899 filter |= TXP_RXFILT_HASHMULTI; 1900 txp_command(sc, TXP_CMD_MCAST_HASH_MASK_WRITE, 1901 2, hash[0], hash[1], NULL, NULL, NULL, 0); 1902 } 1903 } 1904 1905 setit: 1906 txp_command(sc, TXP_CMD_RX_FILTER_WRITE, filter, 0, 0, 1907 NULL, NULL, NULL, 1); 1908 } 1909 1910 void 1911 txp_capabilities(struct txp_softc *sc) 1912 { 1913 struct ifnet *ifp = &sc->sc_arpcom.ac_if; 1914 struct txp_rsp_desc *rsp = NULL; 1915 struct txp_ext_desc *ext; 1916 1917 if (txp_command2(sc, TXP_CMD_OFFLOAD_READ, 0, 0, 0, NULL, 0, &rsp, 1)) 1918 goto out; 1919 1920 if (rsp->rsp_numdesc != 1) 1921 goto out; 1922 ext = (struct txp_ext_desc *)(rsp + 1); 1923 1924 sc->sc_tx_capability = ext->ext_1 & OFFLOAD_MASK; 1925 sc->sc_rx_capability = ext->ext_2 & OFFLOAD_MASK; 1926 1927 ifp->if_capabilities |= IFCAP_VLAN_MTU; 1928 1929 #if NVLAN > 0 1930 if (rsp->rsp_par2 & rsp->rsp_par3 & OFFLOAD_VLAN) { 1931 sc->sc_tx_capability |= OFFLOAD_VLAN; 1932 sc->sc_rx_capability |= OFFLOAD_VLAN; 1933 ifp->if_capabilities |= IFCAP_VLAN_HWTAGGING; 1934 } 1935 #endif 1936 1937 #if 0 1938 /* not ready yet */ 1939 if (rsp->rsp_par2 & rsp->rsp_par3 & OFFLOAD_IPSEC) { 1940 sc->sc_tx_capability |= OFFLOAD_IPSEC; 1941 sc->sc_rx_capability |= OFFLOAD_IPSEC; 1942 ifp->if_capabilities |= IFCAP_IPSEC; 1943 } 1944 #endif 1945 1946 if (rsp->rsp_par2 & rsp->rsp_par3 & OFFLOAD_IPCKSUM) { 1947 sc->sc_tx_capability |= OFFLOAD_IPCKSUM; 1948 sc->sc_rx_capability |= OFFLOAD_IPCKSUM; 1949 ifp->if_capabilities |= IFCAP_CSUM_IPv4; 1950 } 1951 1952 if (rsp->rsp_par2 & rsp->rsp_par3 & OFFLOAD_TCPCKSUM) { 1953 sc->sc_rx_capability |= OFFLOAD_TCPCKSUM; 1954 #ifdef TRY_TX_TCP_CSUM 1955 sc->sc_tx_capability |= OFFLOAD_TCPCKSUM; 1956 ifp->if_capabilities |= IFCAP_CSUM_TCPv4; 1957 #endif 1958 } 1959 1960 if (rsp->rsp_par2 & rsp->rsp_par3 & OFFLOAD_UDPCKSUM) { 1961 sc->sc_rx_capability |= OFFLOAD_UDPCKSUM; 1962 #ifdef TRY_TX_UDP_CSUM 1963 sc->sc_tx_capability |= OFFLOAD_UDPCKSUM; 1964 ifp->if_capabilities |= IFCAP_CSUM_UDPv4; 1965 #endif 1966 } 1967 1968 if (txp_command(sc, TXP_CMD_OFFLOAD_WRITE, 0, 1969 sc->sc_tx_capability, sc->sc_rx_capability, NULL, NULL, NULL, 1)) 1970 goto out; 1971 1972 out: 1973 if (rsp != NULL) 1974 free(rsp, M_DEVBUF); 1975 } 1976